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LC875W00 SERIES USER`S MANUAL

1. 3 1 7 3 5 2 Functions 3 17 3 5 3 Related Registers eee eee ee eee eee ee eee eee 3 1 8 3 5 4 Options 3 22 3 5 5 HALT and HOLD Mode Operation eee ee eee eee ee eee eee eee eee eee eee ee re 3 22 Port 8 mrsnanansursasanauueanuuesssuauauueanseusesuuausuueasseuuauuansuassuuaussusessenuauuansssscnuaus 3 23 3 6 1 Overview 3 23 3 6 2 Functions eee eee eee ee eee eee ee ee eee ee ee ey 3 23 3 6 3 Related Registers eee eee eee eee eee eee rere eee eee eee eee ee ee ee eee eee ee eee eee 3 23 3 6 4 HALT and HOLD Mode Operation eee eee rere eee ee eee eee eee eee eee ee eee eee 3 23 Port A mrsnanansuresssuanauuuuessanuauueanseussunausensassuuauuensesesuuausensenenuauuansecsecnuaus 3 24 3 7 1 Overview eee eee rere rere eee ee eee ee
2. 3 1 19 3 23 4 Related Registers eee eee ree reer ere Creer ere ee errr ee rere cere rere eee reer 3 1 20 PWMA PWMB 3 126 3 24 1 Overview eee eee rere ere terete rrr errr errr errr errr rere ree rr eee reece ree ee rer 3 1 26 3 24 2 Functions eee rere rere reer reer eer errr reer ere errr ere rer errr errr ee ree eee ee ree eee rere 3 1 26 iv Contents 3 24 3 Circuit Configuration POMOC POO RE RS NES S ERES NES E orale E 3 1 27 3 24 4 Related Registers ELESE EELEE EATE eee ee eee OR 8 Rn 3 1 28 3 24 5 Setting Up the PWM4 PWM5 Output Ports nmm 3 129 3 25 8 bit AD Converter ADC M HH HH 3 134 3 25 1 Overview m M RR RN TEM m B Ra E NIU m Tree eT Erte 3 1 34 3 25 2 Functions EELEESLILISLUCILLILLIDOIL LIO I ele 3 1 34 3 25 3 Circuit Configuration REN RS M MS RAS M RES assu BN URS NE BM EU UE SMS Ma UE 3 1 35 3 25 4 Related Registers TCR A RENEE RARER ETE ICE ROCHE RICO CRI E ER 3 1 35 Chapter 4 Control 4 1 4 1 Interrupt Function asasasasasasaasananusaauananananasanuanuananuananananaansanasausansunanuanaan 4 1 4 1 1 Overview RSEN NR
3. 3 9 3 3 2 Functions ee ee ee ee eee ee 3 9 3 3 3 Related Registers 3 1 0 3 3 4 Options 3 14 3 3 5 HALT and HOLD Mode Operation eee eee rere eee eee eee eee ee eee ee ee ee ee eee 3 14 Port 3 mrsnanansursassanauuausessenuauueansesesunausuueassenuanueassesscsuuausauseessesuauuenssssenuaus 3 1 5 3 4 1 Overview 3 1 5 3 4 2 Functions 3 1 5 3 4 3 Related Registers eee ere eee eee eee er ere eee eee ee eee eee eee eee eee ee eee eee ee 3 1 5 3 4 4 Options eee reer errr ere ree rere ree eee ee eee eee ee eee eee eee eee ee eee ee ee ee ee eee ee ee 3 1 6 3 4 5 HALT and HOLD Mode Operation eee eee rere eee eee eee ee eee eee ee ee ee ee ee 3 16 Port 7 HARRARARRSRARAESARSRSARARRARARRASRARARRARARRRRARARRRSRARARRARARRRRARARRARARARRARARRRRARARRARAM 3 1 7 3 5 1 Overview
4. LC875W00 Chapter 4 Interrupt Source Flag Register IFLGR Processing Example When interrupts INTO INT2 TOL and INT3 occurred H L level interrupts enabled P set to 02h and IE to 82h Vector address 0001Bh H interrupt level Vector address 00003h X interrupt level Normal operation No interrupt Reading IFLGR returns data FFh because the microcontroller is not in the interrupt state TOL interrupt source is set and interrupt to vector address 0013h occurs Interrupt level L IFLGR is read to refer to TOL INT4 INT2 source flags associated with vector address 0013h and data F3h is read INT3 interrupt source is set and interrupt to vector address 001Bh occurs Interrupt level H IFLGR is read to refer to BTI BTO INTS INT3 source flags associated with vector address 001Bh and data C7h is read INTO interrupt source is set and interrupt to vector address 0003h occurs Interrupt level X IFLGR is read to refer to INTO source flag associated with vector address 0003h and data FFh is read Clear INTO interrupt source flag then execute RETI instruction to exit X level interrupt state Return to H interrupt level IFLGR is read to refer to BTI BTO INTS INT3 source flags associated with vector address 001Bh and data C7h is read INT2 L level interrupt occurs at this point No interrupt is generated because the current interrupt level is H Interrupt
5. 3 1 3 1 3 Related Registers 3 2 3 1 4 Options snsasuuansauanasuunsanuASsuaySRARERAESEHARERRARERRARRARERRARRRGRARRRRRRRGGRRARRRARRRGaR aua ee nu 3 4 3 1 5 HALT and HOLD Mode Operation sessanasusnansessanasaunsusnusasusuensasssesssnansama 3 4 3 2 Port 1 3 5 3 2 1 Overview 3 5 3 3 3 4 3 5 3 6 3 7 3 8 3 9 Contents 3 2 2 Functions eee eee rere errr eee ree eee ree eee ee ee eee eee eee eee ee ee ee eee ee ee eee ee eee ee 3 5 3 2 3 Related Registers eee eee ere eee eee eee eee eee ee eee eee ee ee ee ee ee ee eee ee re 3 5 3 2 4 Options eee eee eee eee eee eee eee ee eee eee eee ee eee eee eee ee eee ee ee eee ee ee ee 3 8 3 2 5 HALT and HOLD Mode Operation 3 8 Port 2 mrsnananssrseassaunauuansessunuaueesesasuananeuasasanuaueueseenenananensusssnuausesecusenusanes 3 9 3 3 1 Overview
6. PWML 013 LL LL LoL jt jt dt je LIL LL ae Lg munmsmnmrmimlMmii n PWML 04 LL JL LU PM D dU TU PWML 05 11 4 LL IL it _ LIL PUMI dor spp Te e E PWML 06 LIL LILLE LIL Lit Lt PWML 017 IL 4 ee PWMH PWML 018 PWMH PWML 019 PWMH PWML 01A PWMH PWML 01B PWMH PWML 01C PWMH PWML 01D PWML O LILILILILILILILILILTLIUILILJLIL PWML 01F The fundamental wave period is variable within the range of 4619256 Fundamental wave period Value represented by to PWMOCA 1 x 16 The overall period can be changed by changing the fundamental wave period The overall period is made up of 16 fundamental wave periods 3 124 LC875W00 Chapter 3 Examples Wave comparison when the 12 bit PWM contains 237 H 12 bit register configuration PWMH PWML 237 H 1 Pulse added system this series D Overall period PWMH IL pe ee PWML 237 2 Ordinary system Since the ripple component of the integral output in this system is greater than that of the pulse added system as seen from the figure below the pulse added system is considered better for motor controlling uses lt Over
7. wa a ree ye SE RE 3E 3 ir 22 77 22 SG EE EIER AES I 4 1 2 Fese 0000 0000 R PI 4 bit i6 3 0 0T PIZDDR PTIDOR PTODOK PISDT PTT 0000 0000 w DR mri mri INTOIF AI 3 Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 0 0000 0000 R W 123CR INT3HEG INTSLEG INTSIF INT2HEG INT2LEG INT2IF INT2IE i 0000 0000 Ra Mx 0000 0000 R Mm Fe ooon 0000 ew NR DA Daces SLADCL Dacre DART DACRO RA Pe output AD input 8 RM E oars am 0000 0000 P RAN e e eer c ol 0 H 0 L Pp E IP EM E bee Cais a Pes i ee NUN gp eee OE I m 0 0 T6R 0 0
8. The high data output at a that is selected as an N channel open drain output user option is represented by an open circuit 3 6 LC875W00 Chapter P17FCR bit 7 P17 function control timer 1 PWMH and base timer BUZ output control This bit controls the output data at pin P17 When P17 is placed in output mode PI7DDR 1 and P17FCR is set to 1 the AND of timer 1 PWMH output and BUZ output from the base timer is EORed with the port data latch and the result is placed at pin P17 P16FCR bit 6 P16 function control timer 1 PWML output control This bit controls the output data at pin P16 When P16 is placed in output mode P16DDR 1 P16FCR is set to 1 the EOR of timer 1 PWML output data and the port data latch is placed at pin P16 P15FCR bit 5 P15 function control SIO1 clock output control This bit controls the output data at pin P15 When P15 is placed in output mode PISDDR 1 and PI5FCR is set to 1 the OR of the SIOI clock output data and the port data latch is placed at pin P15 P14FCR bit 4 P14 function control SIO1 data output control This bit controls the output data at pin P14 When P14 is placed in output mode PI4DDR 1 and P14FCR is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P14 When SIO1 is active SIO1 input data is read from P14 regardless of the I O state of P14 P13FCR bit 3 P13 function control SIO1 da
9. NKCOV NKCAP2 NKCAPI NKCAPO NKEN bit 7 Counter control When set to 0 the NK control circuit is inactive When set to 1 the NK control circuit is active The timer 0 operation is switched to make an asynchronous high speed counter with timer 0 being the higher order counter Counting is started by setting this bit to 1 and starting timer 0 in the external clock mode NKCMP2 to bits 6 to 4 Match register As soon as the counter reaches the count value equivalent to timer 0 match register value 1 x 8 value of NKCMP2 to NKCMPO a match detection signal occurs generating real time output of the required value and setting the match flag of timer 0 Subsequently the real time output port relinquishes the real time output capability and changes its state in synchronization with the data in the port latch The real time output function and match detection function will not be resumed until the next NKREG write operation is performed NKCOV NKCAP2 to NKCAPO bits to 0 Capture register The NK counter value is captured into these bits in synchronization with the timer OL capture operation NKCOV is a carry into timer 0 When this bit is set to 1 the capture value of timer 0 must be corrected by 1 NKCAP2 to NKCAPO carry the capture value of the NK counter These bits are read only 3 46 LC875W00 Chapter 3 NK comparison value TOL comparison value TOL counter 8 bits NK c
10. Bits 7 and 0 of PITST FE47 are reserved for testing They must always be set to 0 Bit 2 of PITST FE47 is used to control the realtime output of the high speed clock counter It is explained in the chapter on high speed clock counters 3 2 3 Related Registers 3 2 8 4 Port 1 data latch P1 1 The port 1 data latch is an 8 bit register for controlling the port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If the P1 FE44 is manipulated using the NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W Pl P17 P16 P15 P14 P13 P12 P11 P10 3 5 Port 1 3 2 3 2 1 data direction register PIDDR 1 This register is an 8 bit register that controls the I O direction of port 1 data in 1 bit units Port P1n is placed in output mode when bit PInDDR is set to 1 and in input mode when bit PInDDR is set to 0 2 When bit PInDDR is set to 0 and bit P1n of the port 1 data latch is set to 1 port PIn becomes an input with a pull up resistor Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE45 0000 0000 R W PIDDR P17DDR 16 PISDDR PI4DDR P13DDR PI2DDR P1
11. 3 14 42 Timer 1 prescaler control register T1PRR 1 This register sets up the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer TIL is updated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE19 0000 0000 R W TIHPRE TIHPRC2 TIHPRCI TIHPRCO TILPRE TILPRC2 TILPRCI TILPRCO T1HPRE bit 7 Controls the timer 1 prescaler high byte T1HPRC2 bit 6 Controls the timer 1 prescaler high byte T1HPRC1 bit 5 Controls the timer 1 prescaler high byte T1HPRCO bit 4 Controls the timer 1 prescaler high byte 2 T1HPRC1 0 Prescaler Count 0 gt 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 T1LPRE bit 3 Controls the timer 1 prescaler low byte T1LPRC2 bit 2 Controls the timer 1 prescaler low byte TA1LPRC 1 bit 1 Controls the timer 1 prescaler low byte T1LPRCO bit 0 Controls the timer 1 prescaler low byte 3 56 LC875W00 Chapter 3 T1LPRE TA1LPRC2 T1LPRC1 TiLPRCO T1L Presc
12. Coss ee Sass E 3 48 914 2 ORANDI DU UNE FE REN de 3 48 3 44 8 Circuit Configuration meme 3 50 3 14 4 Related Registers eee 3 55 Timers 4 and 5 T4 5 s HH HH 3 59 35 0 se max side aha uelts Cao od ue bata ieu uode da 3 59 3 59 3 15 3 Circuit Configuration meme 3 59 3 15 4 Related Registers eene 3 61 Timers 6 and 7 T6 T7 s Hm Henn 3 63 3 63 EIS MEZ NI LLLQLL BI 3 63 3 16 3 Circuit Configuration meme 3 63 3 16 4 Related Registers eene 3 65 Base Timer BT mmm MH 3 67 Ce WARMER Olan LLL 3 67 Bila ei 3 67 3 17 3 Circuit Configuration 55 mmm eene 3 68 iii 3 18 3 19 3 20 3 21 3 22 3 23 3 24 Contents 3 1 7 4 Related Registers eee eee reer eee rere eee rere eee eee ree eee ere 3 69 Serial Interface 0 5100 3 71 3 1 8 1 3 71 3 18 2 Functions eee eee terete ere rr rere rere rere rere rrr rer rere rere ere ree eee rere eee rere 3 71 3 18 3 Circuit Configuration m 3 72 3 1 8 4 Related Registers eee eee eee re eee reer ee rere eee rere reece
13. ea DEREN Rw scono FE31 0000 0000 R W SBUFO CE ose L8 SG SG SN 4 5 3 5 C 5 5 5 2 5 5 2 5 5 FE33 0000 0000 RAW setro 5007 50706 507805 507804 501802 507802 SCTROI 57800 R 5 5 5 5 5 R o een SS TENDS pT 567 SBRGI6 SBRGIS SBRGI4 SBRGI3 SBRGI2 5 SERGIO FE37 0000 0000 R W SWCONO Controls suspension of SOWSTP SWCONB6 SWCONB5 SOXBYT4 SOXBYT3 SOXBYT2 SOXBYT1 SOXBYTO continuous 5100 transfer 58002 2 588200 SI2WRT SI2RUN SI2OVR SI2END FE39 00000000 RAW SBU2 3 SBUF27 SBUF26 SBUF25 SBUF24 SBUF23 SBUF22 SBUF2 SBUF20 FE3A 00000000 RAW setr f SI2BN2 51281 SI2BNO 50704 SCTR23 SCTR22 501821 507820 FE3B 0000 0000 R W SI2PC Controls 102 dedicated ports 51250 SI2P2C SI2PIC SI2POC SI2P3D SI2P2D SI2PID SI2POD FE3C 00000000 RAW taser reco Taco TIE 10 TAE resp TT 114111144 4 414 k AI 2 LC875W00 APPENDIX I Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 0000 0000 R W 8 bit timer
14. is to be used in the receive mode the will not function normally if this bit is set to 1 Start bit neq Figure 3 22 1 UART2 Block Diagram Receive Mode 3 109 UART1 Stop bit Note The position of the stop bit differs depending on the bit length to be transferred Start bit 11 bit shift register TSFT2 V Data output LSB first At beginning of transmit operation TBUF2 gt TSFT2 TBUF2 FEEBh Clock generator circuit Data length and data bit 8 set Baudrate generator UBR2 FEEAh UART output control gt P34 UART output format control Note os ns or o ar os ws UCON2 FEE9h UCONO FEE8h bit 7 Interrupt request Note Bit 4 of P3DDR at FE4D must be set to O when the UART2 transmit data is to be output Transmit data is not output if this bit is set to 1 Figure 3 22 2 UART2 Block Diagram Transmit Mode 3 110 LC875W00 Chapter 3 22 4 Related Registers 3 22 4 4 UART2 control register 2 UCON2 1 Thisregister is an 8 bit register that controls the receive operation and interrupts for the UART2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEE8 0000 0000 UCON2 UBRSEL2 STRDET2 IRECRUN2 STPERR2 U2B3 RBIT82 RECEND2 RECIE2 UBRSEL2 bit 7 UART2 baudrate generator period control 1 When this bit is set to 1 the UART2 baudrate generator generates clocks having a period of n 1
15. PN MUL24 RAM8 amp lt 1 Bit 8 of RAM address DIV24 for storing results is set to 1 Note A 1 is read and processed if the processing target is an 8 bit register no bit 8 gt RAED CH INC INC 9 bits INCW INC 17 bits DE DB DEC 9 bits DEC 17 bits DEC 9 bits check low order 8 bits DEC 9 bits check low order 8 bits SETI Legends REGS Bit 8 of a RAM or SFR location REGHS REGLS Bit 8 of the high order byte of a RAM location or SFR bit 8 of the low order byte RAMS Bit 8 of a RAM location RAMHS8 RAMLS 8 of the high order byte of a RAM location bit of the low order byte 2 11 2 12 LC875W00 Chapter 3 Peripheral System Configuration This chapter describes the internal functional blocks peripheral system of this series of microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix for reference 3 1 Port 0 3 1 1 Overview Port 0 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction and the pull up resistors is accomplished through the data direction register in 4 bit units This port can also serve as a pin for external interrupts and can release HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output
16. Data output SCTRO FE33h gt lock Cloc MSB first SIOO output control P10 SBUFO FE31h P10 port latch 2 2 2 2 2 2 2z 4 5 aia exchange P10 output control the end of 8 bit data transmission reception Number of EH SIT S100 output control 11 P11 port latch P11 output control os e ps o SWCONO FE37h Clock generator circuit SIOO output control 12 MSB LSB first select P12 port latch P12 output control Baudrate generator Serial transfer end flag SBRO FE32h SIOO overrun flag eo on SCONO FE30h Interrupt request Figure 3 18 2 5100 Continuous Data Transmission Reception Mode Block Diagram SIOCTR 1 3 74 LC875W00 Chapter 3 3 18 4 Related Registers 3 18 4 1 5100 control register SCONO 1 Thisregister is an 8 bit register that controls the operation and interrupts of SIOO Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE30 0000 0000 R W SCONO SIOBNK SIOWRT SIORUN SIOCTR SIODIR SIOOVR SIOEND SIOIE SIOBNK bit 7 Transfer RAM address control during continuous data transmission reception 1 When this bit is set to 1 transfer of continuous transmission reception data is carried out between RAM addresses 01E0 H to 01FF H and SBUFO 2 When this bit is set to 0 transfer of continuous transmission reception data is carried out between RAM addresses
17. value range X to E Tcyc When UCON2 UBRSEL2 1 2 4 8192 TUBR2 UBR2 value 1 x Tcyc value range to Tcyc Setting the UBR2 to 00 H is inhibited Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEEA 0000 0000 R W UBR2 U2BRG7 U2BRG6 U2BRG5 U2BRG4 U2BRG3 U2BRG2 U2BRGI U2BRGO 3 113 UART1 3 22 4 4 UART2 transmit data register TBUF2 1 This register is an 8 bit register that stores the data to be transmitted through UART2 2 Data from the TBUF2 is transferred to the transmit shift register TSFT2 at the beginning of a transmit operation Load the next data after checking the transmit shift register transfer flag UCON3 TEPTY2 Bit 8 of the transmit data must be loaded into the transmit data bit 8 storage bit UCON3 TBIT82 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEEB 0000 0000 R W TBUF2 T2BUF7 T2BUF6 T2BUF5 T2BUF4 T2BUF3 T2BUF2 T2BUFO 3 22 4 5 UART2 receive data register RBUF2 1 This register is an 8 bit register that stores the data that is received through the UART2 2 The data from the receive shift register RSFT2 is transferred to this RBUF2 at the end of a receive operation Bit8 of the received data is placed in the receive data bit 8 storage bit UCON2 RBIT82 Bit 7 of RBUF2 is set to 0 when the receive data length is 7 bits Address Initial Value R W N
18. Address 7FH R63 upper Re3 lower R63 7EH 03H upper 02H R1 lower R1 2 01H RO upper RO lwe RO 0 Figure 2 10 1 Allocation of Indirect Registers 2 11 Addressing Modes LC870000 series microcontrollers support the following seven addressing modes 1 Immediate immediate data refers to data whose value has been established at program preparation assembly time 2 Indirect register Rn indirect 0 lt n lt 63 3 Indirect register Rn register indirect 0 lt n lt 63 4 Indirect register RO Offset value indirect 5 Direct 6 ROM table look up 7 External data memory access The rest of this section describes these addressing modes 2 11 1 Immediate Addressing The immediate addressing mode allows 8 bit 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD 12H Loads the accumulator with byte data 12H Ll LDW 1234 Loads the BA register pair with word data 1234 PUSH 349 Loads the stack with byte data 34H ADD 56H Adds byte data 56H to the accumulator BE 78H L1 Compares byte data 78H with the accumulator for a branch 2 6 LC875W00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected registe
19. When a reset occurs or a X tal HOLD mode release signal base timer interrupt INTO INTI INT2 INT4 5 or POINT occurs bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode 4 13 Standby 4 3 3 Related Registers 4 3 3 1 Power control register PCON 3 bit register 1 power control register is a 3 bit register that specifies the operating mode normal HALT HOLD X tal HOLD Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 PCON XTIDLE IDLE Bits 7 to 3 These bits do not exist They are always read as 1 XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating mode Normal or HALT mode HOLD mode E 0 TER 1 These bits must be set with an instruction When the microcontroller enters HOLD mode all oscillations main clock subclock and RC are suspended and bits 0 1 4 and 5 of the OCR are set to 0 When the microcontroller returns from HOLD mode the main clock and RC oscillator resume oscillation The subclock oscillator restores the state that is established before HOLD mode is entered and the system clock is set to RC When the microcontroller enters X tal HOLD mode all oscillations except XT main clock and RC are suspended but the contents of the OCR register remain unchanged When the micro
20. 0 3 Setting up the ports Designate the clock and data ports as N channel open drain output ports 4 Starting communication sending an address Load SBUFI with address data Set SIIRUN transfer a start bit SBUFI 8 bits stop bit H 5 Checking address data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW Check that the data read from SBUFI matches the transferred data A mismatch implies that the current transfer and another master operation overlap 3 86 LC875W00 Chapter 6 Sending data Load SBUFI with output data e Clear SIIEND and exit interrupt processing transfer SBUFI 8 bits stop bit H 7 Checking sent data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW e Check that the data read from SBUFI matches the transferred data A mismatch implies that the current transfer and another master operation overlap Return to step 6 when continuing data transmission Go to step 10 to terminate communication 8 Receiving data S
21. 32 3 2 When this bit is set to 0 the UARTI baudrate generator generates clocks having a period of n 1 x 8 3 n represents the value of the UART baudrate generator at FED2h STRDET bit 6 UART1 start bit detection control 1 When this bit is set to 1 the start bit detection falling edge detection function is enabled 2 When this bit is set to 0 the start bit detection falling edge detection function is disabled This bit must be set to 1 to enable the start bit detection function when UARTI is to be used in continuous receive mode If this bit is set to 1 when the receive port P33 is held at a low level RECRUN is automatically set and the UART 1 starts the receive operation RECRUN bit 5 UART1 receive start flag 1 This bit is set and a receive operation starts when a falling edge of the signal at the receive port P33 is detected when the start bit detection function is enabled STRDET 1 2 This bit is automatically cleared at the end of the receive operation If this bit is cleared during the receive operation the operation is aborted in the middle of the processing When a receive operation is forced to terminate prematurely RECEND is set to 1 and the contents of the receive shift register are transferred to RBUF And STPERR is set to 1 if the state of the last data bit that is received on the forced termination is low STPERR bit 4 UART1 stop bit error flag 1 Th
22. 4 Reset When it stops operation or a match signal occurs on the mode 0 or 2 condition 3 14 3 6 Timer 1 high byte T1H 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset When it stops operation or a match signal occurs on the mode 0 2 or 3 condition 3 51 3 14 3 8 2 3 14 3 9 2 3 Timer 1 match data register low byte T1LR 8 bit register with a match buffer register This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte TIL The match buffer register is updated as follows When it is inactive TILRUN O the match register matches TILR When it is active TILRUN I1 the match buffer register is loaded with the contents of TILR when the value of T1L reaches 0 Timer 1 match data register high byte TTHR 8 bit register with a match buffer register This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte T1H The match buffer register is updated as follows e When it is
23. The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the B register designates the high order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEO1 0000 0000 R W BREG BREG7 BREG6 BREGS BREG4 BREG3 BREG2 BREGI BREGO 2 7 Register The C register is used with the ACC and B register to store the results of computation during the execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address FEO2H of the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 CREG5 CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation resul
24. The period of the internal clock is programmable within the range of n 1 x 2 Tcyc n 1 to 255 Note n 0 is inhibited 2 Continuous data transmission reception Transmits and receives bit streams whose length is variable in 1 bit units between 1 and 256 bits Transfer is carried out in clock synchronization mode Either the internal or external clock can be used The period of the internal clock is programmable within the range of n 1 x 2 110 255 Note n 0 is inhibited e 1 to 256 bits of send data is automatically transferred from RAM to the data shift register SBUFO and receive data is automatically transferred from the data shift register SBUFO to RAM 3 Interrupt generation An interrupt request is generated at the end of communication when the interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to the control serial interface 0 5100 SCONO SBUFO SBRO SCTRO SWCONO PI PIDDR PIFCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE30 0000 0000 R W SCONO SIOBNK SIOWRT SIORUN SIOCTR SIODIR SIOOVR SIOEND SIOIE 3 71 Circuit Configuration 5100 control register SCONO 8 bit register This register controls the operation and interrupts of SIOO SIOO data shift register SBUFO 8 bit register This register is an 8 bit shift register that performs data input and
25. This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 OOOOBH interrupt level control flag e A 1 in this bit sets all interrupts to vector address 0000BH to L level e A 0 in this bit sets all interrupts to vector address 0000BH to the X level XCNTO bit 0 00003H interrupt level control flag e A 1 in this bit sets all interrupts to vector address 00003H to the L level e A 0 in this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 This register 1s an 8 bit register that selects the interrupt level H L to vector addresses 00013H to 0004BH Address Initial value RAW Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 09 00000000 IP43 IP3B IP33 IP2B IP23 IP1B IP13 Interrupt Vector Address 0004BH 00043H 0003BH 0002BH 00023H 0001BH 00013H 4 1 4 3 Interrupt source flag register IFLGR 1 This register is an 8 bit register that can be used to identify the interrupt source flag related to the vector address used in an interr
26. SWCONB6 SWCONBS bits 6 and 5 These bits can be read and written with instructions The user can use these bits freely SOXBYTA to SOXBYTO bits 4 to 0 These bits can be read to determine the number of bytes transferred in continuous data transfer mode 3 76 LC875W00 Chapter 3 3 18 4 6 RAM used in continuous data transmission reception mode SIOO can transmit and receive 1 to 256 bits of serial data continuously in continuous data transmission reception mode using the RAM area from 01CO H to 01 FF H 1 2 3 3 18 5 3 18 5 1 3 4 5 6 The RAM area from 01CO H to 01DF H is used when SIOBNK 0 The RAM area from O1EO H to is used when SIOBNK 1 In continuous data transmission reception mode data transmission reception is started after the operation flag is set and RAM data at the lowest address is transferred to SBUFO after the contents of RAM and SBUFO are exchanged when SIJOWRT 1 After 8 bits of data are transmitted and received the RAM data from the next RAM address is transferred to SBUFO the contents of RAM and SBUFO are exchanged when SIOWRT 1 and data transmission reception processing is continued The last 8 bits or less of received data are left in SBUFO and not exchanged with data in RAM If the volume of data to transmit receive is set to 8 bits or less after the operation flag is set and RAM data is transferred to SBUFO after the contents of RAM and SBUFO are exchanged w
27. 2 Interrupts are programmable in 5 different time schemes High speed clock counter Capable of counting clocks with a maximum clock rate of 24 MHz at a main clock of 12 MHz 1 2 Real time output Serial Interface SIO 5100 8 bit synchronous serial interface 1 LSB first MSB first is selectable 2 Built in 8 bit baudrate generator maximum transfer clock rate 4 Tcyc 3 Automatic continuous data communication 1 to 256 bits SIO1 8 bit asynchronous synchronous serial interface Mode 0 Mode 1 Mode 2 Mode 3 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512 Tcyc transfer clock Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048 Tcyc baudrate Bus mode 1 start bit 8 data bits 2 to 512 Tcyc transfer clock Bus mode 2 start detection 8 data bits stop detection SIO2 8 bit synchronous serial interface 1 LSB first 2 Built in 8 bit baudrate generator maximum transfer clock rate i Tcyc 3 Automatic continuous data communication 1 to 32 bytes UART 2 channels Full duplex Data length 7 8 9 bits selectable Stop bit 1 bit 2 bits in continuous data transmission D 2 3 4 8192 Built in baudrate generator 8 to FA Tcyc baudrate 1 2 LC875W00 Chapter 1 AD converter 8 bits x 15 channels e PWM Variable period 12 bit PWM x 4 channels Remote control receiver circuit multiplexed with P73 INT3 TOIN pin e Noise filtering funct
28. DACRB bit 5 Reference voltage generation control This bit turns on 1 and off 0 the power to the ladder resistor network for generating the reference voltage When this bit is set to 1 power is supplied to the ladder resistor network and the reference voltage is generated This bit must be set to 1 to perform AD conversion When set to 0 no power is supplied to the ladder resistor network and therefore no reference voltage is generated This bit must be cleared except during AD conversion to save power consumption This bit is automatically reset to prevent the reference voltage from being generated when HALT or HOLD mode is entered SLADCL bit 3 AD conversion time control This bit and bit ADCR2 ADCR bit 2 control the AD conversion time See the description on the ADCR2 bit DACR2 bit 2 Fixed bit This bit must always be set to 0 bit 1 Fixed bit This bit must always be set to 0 DACRO bit 0 Fixed bit This bit must always be set to 0 Notes e DACRS is automatically set to 0 when HALT or HOLD mode is entered The reference voltage must be generated DACR5 1 to perform AD conversion Bits O 1 2 6 and 7 of the reference voltage generator circuit control register DACR must always be set to 0 No correct AD conversion results will be obtained if any one of these bits is set to nonzero 3 137 3 25 4 3 AD conversion result register ADRR 1 Thisregister is an 8 bit register for sto
29. PDN IDLE Bits 7 to 3 These bits do not exist They are always read as 1 XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating mode Normal or HALT mode 0 X tal HOLD mode 1 These bits must be set with an instruction When the microcontroller enters HOLD mode all oscillations main clock subclock and RC are suspended and bits 0 1 4 and 5 of the OCR are set to 0 When the microcontroller returns from HOLD mode the main clock and RC oscillator resume oscillation The subclock restores the state that is established before HOLD mode is entered and the system clock is set to RC When the microcontroller enters X tal HOLD mode all oscillations except XT main clock and RC are suspended but the contents of the OCR register remain unchanged When the microcontroller returns from X tal HOLD mode the system clock to be used when HOLD mode is entered needs to be set to either subclock or RC because no adequate oscillation stabilization time can be secured for the main clock Since X tal HOLD mode is used usually for low current clock counting less current will be consumed if the system clock is switched to the subclock and the main clock and RC oscillations are suspended before X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 PDN is cleared when a HOLD mode release signal INTO INT1 INT2 INT4 5 or PO
30. took CLKOEN CKODV2 CKODV 3 1 Port 0 3 1 3 Related Registers 3 1 31 Port 0 data latch PO 1 The port O data latch is an 8 bit register for controlling the port 0 output data and port 0 interrupts 2 When this register is read with an instruction data at pins POO to 07 is read in If the PO FE40 is manipulated using the NOT1 SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the port pins 3 Port 0 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE40 0000 0000 R W PO PO7 P06 P05 P04 P03 P02 01 00 3 1 3 2 Port 0 data direction register PODDR 1 This register is a 6 bit register that controls the I O direction of port 0 data in 4 bit units the pull up resistors in 4 bit units and port 0 interrupts Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE41 00 0000 R W PODDR POFLG POIE POHPU POLPU POHDDR POLDDR POFLG bit 5 PO interrupt source flag This flag is set when a low level is applied to the port 0 that is set up for input port and the corresponding PO 40 bit is set A HOLD mode release signal and an interrupt request to vector address 004BH are generated when both this bit and the interrupt request enable bit POIE are set to 1 This bit must be cleared with an
31. 01CO H to 01DF H and SBUFO SIOWRT bit 6 RAM write control during continuous data transmission reception 1 When this bit is set to 1 the contents of data RAM and SBUFO are automatically exchanged during continuous data transmission reception 2 When this bit is set to 0 the contents of data RAM are automatically transferred to SBUFO during continuous data transmission reception but the contents of data RAM remain unchanged SIORUN bit 5 SIOO operation flag 1 Alinthis bit indicates that SIOO is running 2 This bit must be set with an instruction 3 This bit is automatically cleared at the end of serial transfer on the rising edge of the last clock involved in the transfer SIOCTR bit 4 SIOO continuous data transmission reception synchronous 8 bit control 1 Alinthis bit places SIOO into continuous data transmission reception mode 2 A Qin this bit places SIOO into synchronous 8 bit mode 3 This bit is automatically cleared at the end of serial transfer on the rising edge of the last clock involved in the transfer SIODIR bit 3 MSB LSB first select 1 Alinthis bit places SIOO into MSB first mode 2 A Qin this bit places SIOO into LSB first mode SIOOVR bit 2 SIOO overrun flag 1 This bitis set when a falling edge of the input clock is detected with SIORUN 0 2 This bit is set when a falling edge of the input clock is detected during internal data communication between SBUFO and RAM with each 8
32. 1 This bit is set at the end of a receive operation if the state of the received stop bit the last data bit received is low 2 Thisbit must be cleared with an instruction U2B3 bit 3 General purpose flag 1 This bit can be used as a general purpose flag bit Any attempt to manipulate this bit exerts no influence on the operation of the functional block 82 bit 2 UART2 receive data bit 8 storage bit 1 This bit position is loaded with bit 8 of the received data at the end of receive operation when the data length is set to 9 bits UCON2 8 9BIT2 1 8 7BIT2 0 If the receive operation is terminated prematurely this bit position is loaded with the last received bit but one 2 Thisbit must be cleared with an instruction 3 111 UART1 RECEND2 bit 1 UART2 receive end flag 1 This bitis set at the end of a receive operation When this bit is set the received data is transferred from the receive shift register RSFT2 to the receive data register RBUF2 2 This bit must be cleared with an instruction the continuous receive mode the next receive operation is not carried out even when the UART2 detects data that sets the receive start flag RECRUN2 before this bit is set RECIE2 bit 0 UART2 receive interrupt request enable control 1 When this bit and RECEND2 are set to 1 an interrupt request to vector address 0033H is generated 3 22 4 UART2 control register UCONS3 1 Thisregister is
33. 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The low order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the respective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC Value BNK Value 00000H 9 mwm 9 INmmumm 3 mua 9 How 9 wu 9 changed 0 Unconditional branch Unchanged U Conditional branch BE BNE DBNZ DBZ BZ BNZ PC PC nb r8 128 to 127 Unchanged instructions BZW BNZW BP BN BPC nb Number of instruction bytes U U Call instructions CALL al7 PC al7 RCALL 112 PC PC 2 112 2048 to 2047 RCALLA PC PC 1 Areg 0 to 255 Unchanged Return instructions RET RETI PC16 to 08 SP BNK is set PCO7 to 00 SP 1 to bit 8 of SP denotes the contents of RAM Sp address desi
34. 3 In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data bit that is received data about the position of the stop bit Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE35 00000 0000 R W SBUFI 5 8 SBUFI7 SBUF16 SBUFI5 SBUFIA SBUFI3 SBUF12 SBUF11 SBUFIO 3 19 5 3 Baudrate generator register SBR1 1 Thisregister is an 8 bit register that defines the baudrate of SIO1 2 Loading this register with data causes the baudrate generating counter to be initialized immediately 3 The baudrate varies from mode to mode the baudrate generator is disabled in mode 3 Modes 0 and 2 TSBRI SBRI value 1 x 2Tcyc Value range 2 to 512 Tcyc Mode 1 TSBRI z SBRI value 1 x 8Tcyc Value range 8 to 2048Tcyc Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRGI7 SBRGI6 SBRGI5 SBRG14 SBRGI3 SBRGI2 SBRGII SBRG10 LC875W00 Chapter 3 20 Serial Interface 2 5102 3 20 1 Overview The serial interface 2 SIO2 incorporated in this series of microcontrollers is a synchronous serial interface that is provided with a continuous data transfer function 3 20 2 Functions 1 Synchronous 8 bit serial interface 5102 performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock SIO2 can transmit and receive 1 to 32 bytes of data continuously The sta
35. This function detects low edge a high edge or both edges and sets the interrupt flag They can also be used as timer 0 capture 1 signal inputs 3 Hold mode release function When the interrupt flag and interrupt enable flag are set by INT4 or INT5 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When signal change that sets the interrupt flag is input to INT4 or INT5 in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INT4 or INTS data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when INT4 or INTS data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 or 5 it is recommended that INT4 or 5 be used in the double edge interrupt mode 3 9 Port 2 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE48 0000 0000 R W P2 P27 P26 P25 P24 P23 P22 P21 P20 3 3 8 Related Registers 3 3 3 1 Port 2 data latch P2 1 The port2 data latch is an 8 bit register for controlling the port 2 output data and pull up resistors 2 When this register is read with an instruction
36. count value setting and counter value capture bits 2 Start stop Controlled by the start stop operation of timer counter 0 low byte TOL when NKEN 1 3 Count clock External input signals from P72 INT2 TOIN NKIN pin 4 Real time output The real time output port must be set to the output mode When NKEN bit 7 is set to 0 the real time output port relinquishes its real time output capability and synchronizes itself with the data in the port latch When the value that will result in NKEN 1 is written into NKREG the real time output port restores its real time output capability and holds the output data In this state the contents of the port latch must be replaced by the next real time output value When the high speed clock counter keeps counting and reaches the count value TOLR 1 x 8 value of NKCMP2 to NKCMPO real time output turns to the required value Subsequently the real time output port relinquishes the real time output capability and synchronizes itself with the data in the port latch To restore the real time output capability a value that will result in NKEN 1 must be written into NKREG 5 Capture clock Generated in synchronization with the capture clock for TOL timer 0 low byte 3 13 3 2 P1TST register 1 Thereal time output function is enabled when DSNKOT PITST register bit 2 is set to 0 2 The real time output function is disabled when DSNKOT PITST register bit 2 is set to 1 In this case the rea
37. data at pins P20 to P27 is read in If the P2 FE48 is manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port 2 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE48 0000 0000 R W P2 P27 P26 P25 P24 P23 P22 P21 P20 3 3 3 2 Port 2 data direction register P2DDR 1 This register is an 8 bit register that controls the I O direction of the port 2 data in 1 bit units Port P2n is placed in output mode when bit P2nDDR is set to and in input mode when bit P2nDDR is set to 0 2 When bit P2nDDR is set to 0 and the bit P2n of the port 2 data latch is set to 1 port P2n becomes input with a pull up resistor Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE49 0000 0000 R W P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Register Data Port P2n State Internal Pull up Resistor OFF ARRA Enabled Internal pull up resistor Enabled High open CMOS N channel open drain 3 3 3 3 External interrupt 4 5 control register 145CR 1 This register is an 8 bit register for controlling external interrupts 4 and 5 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4A 0000 0000 R W I45CR INTSHEG INTSLEG INTSIF INTSIE INTAHEG INTA4LEG INT4IF
38. however cannot be set by a rising edge occurring when P72 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P72 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P72 it is recommended that P72 be used in the double edge interrupt mode Interrupt Input Timer 0 Input Output Signal Count Detection Input N channel open drain L level H level Timer OL Enabled programmable L edge H edge Finer on Enabled pull up L edge H edge Available Enabled resistor both edges Available TimerOH Note P70 and P71 HOLD mode release is available only when level detection is set Capture Hold Mode Input Release Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESC 0000 0000 R W P7 P73DDR P72DDR P71DDR P70DDR P73DT P72DT P71DT P70DT 3 5 3 Related Registers 3 5 3 1 Port 7 control register 1 Thisregister is an 8 bit register for controlling the I O of port 7 data and pull up resistors 2 When this register is read with an instruction data at pins P70 to P73 is read into bits 0 to 3 Bits 4 to 7 are loaded with bits 4 to 7 of register P7 If the P7 FESC is manipulated using the NOTI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced as bits 0 to 3 instead of the data at port pins 3 Port 7 data can always be
39. is supplied to the system as the system clock The frequency divider circuit is made up of two stages The first stage allows the selection of division ratios of i Or 2 The second stage allows the selection of division ratios of 1 a A l 7 or 1 128 3 Oscillator circuit control The three oscillators are stopped or enabled independently by instructions 4 Multiplexed input pin functions The crystal oscillator pins XT1 XT2 can also be used as an input port 5 Oscillator circuit states by mode Mode Clock Main Clock Subclock RC Oscillator System Clock Reset Running Stopped Running RC oscillator Programmable Programmable Programmable Programmable HALT State established State established State established State established at entry time at entry time at entry time at entry time HOLD Stopped Stopped Stopped Stopped Immediately after tat tablish exit from HOLD Running ab ished RC oscillator at entry time mode State established t t X tal HOLD Stopped at entry Gh Stopped Stopped Immediately after exit from X tal HOLD State established State established State established State established at entry time at entry time at entry time at entry time Note See Section 4 3 Standby Function for the procedures to enter and exit microcontroller operating modes 4 6 LC875W00 Chapter 4 Reset Main clock started Subclock stopped RC oscillator s
40. of 8th clock Input data read in on rising edge of 9th clock SBUFI shifter at beginning of operation Rising edge of 8th clock Input data read in on rising edge of 9th clock SIO1 output control P13 port latch P13 output control ex T SH P13 lt SIO1 output control P14 port latch P14 output control P14 MSB LSB first select Baudrate generator Serial transfer end flag SBR1 FE36h Overrun flag Y bit7 bite bits bita bit3 bit2 bit1 bito SCON1 FE34h SIO1 output control P15 port latch P15 output control P15 Interrupt request Figure 3 19 1 5101 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1z0 SI1M0z0 3 83 SIO1 Start bit additional circuit Shift input Start stop bit additional circuit At time operation starts LSB MSB first select Shift input 8 bit shift register SIOSF1 Shift clock transfer ends Stop bit data input P13 port latch P13 output control SBUF1 FE35h Stop bit input clock Clock generator circuit Baudrate Set SEND when generator stop bit data ends SBR1 FE36h 5101 output control P14 output control Overrun flag SCON1 FE34h Interrupt request SIO1 output control gt gt m P13 P14 port latch 2 gt da Figure 3 19 2 5101
41. 0 These 4 bits have nothing to do with the control functions on timers 6 and 7 See the description of port 0 for details on these bits 3 66 3 17 3 17 1 LC875W00 Chapter Base Timer BT Overview The base timer BT incorporated in this series of microcontrollers is a 14 bit binary up counter that provides the following five functions 1 2 3 4 5 3 17 2 2 3 4 5 6 Clock timer 14 bit binary up counter High speed mode when used as a 6 bit base timer Buzzer output Hold mode release Functions Clock timer The base timer can count clocks at 0 5 second intervals when a 32 768 kHz subclock is used as the count clock for the base timer In this case one of the three clocks cycle clock timer counter 0 prescaler output or subclock must be loaded in the input signal select register ISL as the base timer count clock 14 bit binary up counter A 14 bit binary up counter can be constructed using an 8 bit binary up counter and a 6 bit binary up counter These counters can be cleared under program control High speed mode when used as a 6 bit base timer When the base timer is used as a 6 bit timer it can clock at intervals of approximately 2 ms if the 32 768 kHz subclock is used as the count clock The bit length can be specified using the base timer control register BTCR Buzzer output function The base timer can generate a 2kHz buzzer when the 32 768 kHz subclock is used
42. 1 a match must occur in all 16 bits of data for a match signal to occur TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated Notes TOHCMP TOLCMP must be cleared to 0 with an instruction e When the 16 bit mode is to be used TOLRUN TOHRUN must be set to the same value at the same time to control operation TOLCMP and TOHCMP are set at the same time in the 16 bit mode 3 12 4 Timer 0 programmable prescaler match register TOPRR 1 Thisregister is an 8 bit register that is used to define the clock period Tpr of timer counter 0 2 Thecount value of the prescaler starts at 0 when TOPRR is loaded with data 3 1 Tcyc Period of cycle clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE11 0000 0000 TOPRR TOPRR7 TOPRR6 TOPRRS TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO 3 12 4 3 Timer counter 0 low byte TOL 1 Thisis a read only 8 bit timer counter It counts the number of match signals from the prescaler external signals Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 01 5 TOL4 TOL3 TOL2 TOLO 3 12 44 Timer counter 0 high byte 1 Thisis a read only 8 bit timer counter It counts the number of match signals from the prescaler or overflows occurrin
43. 2 See Table 3 19 1 for the conditions for setting and clearing this bit SI1REC bit 4 SIO1 receive transmit control 1 Setting this bit to 1 places SIO1 into receive mode 2 Setting this bit to 0 places SIO1 into transmit mode SI DIR bit 3 MSB LSB first select 1 Setting this bit to 1 places SIO1 into MSB first mode 2 Setting this bit to 0 places SIO1 into LSB first mode 3 89 SIO1 SI1OVR bit 2 SIO1 overrun flag 1 This bitis set when a falling edge of the input clock is detected when SI1RUN 0 2 In mode 1 2 or 3 this bit is set if the conditions for setting SIIEND are established when SIIEND 1 3 In mode 3 this bit is set when the start condition is detected 4 This bit must be cleared with an instruction SHEND bit 1 Serial transfer end flag 1 This bit is set when serial transfer terminates see Table 3 19 1 2 Thisbit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control When this bit and SITEND are set to 1 an interrupt request to vector address 003BH is generated 3 19 5 2 Serial buffer 1 SBUF1 1 Serial buffer 1 is a 9 bit register used to store data to be handled during SIO1 serial transfer 2 The low order 8 bits of SBUFI are transferred to the data shift register for data transmission reception at the beginning of transfer processing and the contents of the shift register are placed in the low order 8 bits of SBUFI when 8 bit data is transferred
44. 4 Reset Function 441 Overview The reset function initializes the microcontroller when it is powered on or while it is running 4 4 2 Functions This series of microcontrollers provides the following two types of resetting function 1 External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200 us or longer Note however that a low level of a small duration less than 200 ys is likely to trigger a reset The RES pin can serve as a power on reset pin when it is provided with an external time constant element 2 Runaway detection reset function using a watchdog timer The watchdog timer of this series of microcontrollers can be used to detect and reset runaway conditions by connecting a resistor and a capacitor to its external interrupt pin P70 INTO TOLCP and making an appropriate time constant element An example of a resetting circuit is shown in Figure 4 4 1 Exterior of Interior of microcontroller microcontroller Watchdog timer P70 INTO Internal reset signal Synchronization circuit Figure 4 4 1 Reset Circuit Block Diagram 4 19 Reset 4 4 3 Reset State When a reset is generated by the RES pin or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system clock is switched to the internal RC oscillator when a reset occu
45. 8 bits PCO to The 8 bits of the port C data control register PC FE70 are used to control the port output data The 8 bits of the port C data direction register PCDDR FE71 are used to control the I O direction of data in 1 bit units The output type can be selected from N channel open drain output and CMOS output as a user option Each port bit is provided with a programmable pull up resistor 2 Register configuration e tis necessary to manipulate the following special function registers to control port Initial Value 0000 0000 0000 0000 3 9 3 Related Registers 3 9 8 1 Port C data latch PC 1 The port C data latch is an 8 bit register for controlling port C output data and pull up resistors 2 When this register is read with an instruction data at pins PCO to PC7 is read in If the PC FE70 is manipulated using the NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port C data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE70 0000 0000 R W PC PC7 PC6 5 PC4 PC3 PC2 PCI PCO 3 9 3 2 Port C data direction register PCDDR 1 This register is an 8 bit register that controls the I O direction of port C data in 1 bit units Port PCn is placed in output mode when the bit PCnDDR is set to 1 and in input mode whe
46. M OCC Ok r re er een 4 19 4 4 2 Functions 4 19 443 Reset State EC NER MEM EN EE 4 20 4 5 Watchdog Timer Function 4 21 4 5 1 Overview REM EAR REB RERUM FN RAN MBA MR RAN SEE NR RBS RM NEA 4 21 4 5 2 Functions 4 21 453 Circuit Configuration Wil WR NES RUNE NNNM RN RAE PUR FRE MERE CIN NEA NER CE NU MUNERE RENE E S UIN 4 21 4 5 4 Related Registers RR RR ara M Eu NR NR wa RN eel n n a ju M EN wate el evade dear wae ate oe el Wie UN 4 22 4 5 5 Using the Watchdog Timer RES Sui EE QVE EGER DENS teehee E C XQ EE EE FERES 4 24 Appendix Special Function Register SFR Map Al 1 9 Appendix Il Port Block Diagrams Hmmm All 1 13 1 1 1 LC875W00 Chapter 1 Overview Overview LC875W00 series is an 8 bit microcontroller that centered around a CPU running at a minimum bus cycle time of 83 3 ns integrates on a
47. OV is set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive number 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number 2 4 LC875W00 Chapter 2 3 When the high order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the high order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 4 1 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there is an odd number of 175 in the A register It is cleared to 0 when there is an even number of 175 in the A register 2 9 Stack Pointer SP LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the microcontroller type The SP is 16 bits long and made up of two registers SPL at address FEOAH and S
48. T7R NIMM p 6 atari m OIR 5 AI 4 LC875W00 APPENDIX I Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 FE7D 0000 0000 R W NKREG NKEN NKCMP2 NKCMP 1 NKCMPO NKCOV NKCAP2 NKCAP1 NKCAPO FE7E 0000 0000 FSRO FLASH control bit 4 is R O FSROB7 FSROB6 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ Fix to 0 Fix to 0 FE7F 0000 0000 R W Base timer control Brst Bron Bre BTCIO BTIFO BTIEO d UR d SEM ECLOG JE __ 4 2 uit HE pope qp to d lc Fees 2 441111411 no Lo s a n _ 1 SERES NP PRECES Lees 4121 41 EH NA EE RN CT NAE AUT LIN AI 5 Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 FE9C LC875W00 APPENDIX I Address Initial Value R W LC875W00 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 E 2 p rd FE 2 f FE o Fee
49. TOCA1H 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIF XXXX R TOCA1H7 TOCA1H6 TOCA1H5 TOCA1H4 TOCA1H3 TOCA1H2 TOCA1HI TOCA1HO NK Counter 3 13 3 13 1 High speed Clock Counter Overview The high speed clock counter is a 3 bit counter that has real time output capability It is coupled with timer counter 0 to form an 11 or 19 bit high speed counter It can accept clocks with periods of as short as 2 the cycle time The high speed clock counter is also equipped with a 4 bit capture register incorporating a carry bit 3 13 2 Functions 1 11 bit or 19 bit programmable high speed counter 2 3 4 The 11 bit or 19 bit timer counter coupling the timer counter 0 low byte TOL and timer counter 0 high byte TOH functions as an 11 or 19 bit programmable high speed counter that counts the external input signals from the P72 INT2 TOIN NKIN pin The coupled timer counter 0 counts the number of overflows occurring in the 3 bit counter In this case timer 0 functions as a free running counter Real time output A real time output is placed at pin P17 Real time output is a function to change the state of output at a port into real time when the count value of a counter reaches the required value This change in output
50. W SCON2 SBR2C2 SBR2CI SBR2CO SDWRT SDRUN SIZOVR SDEND SDIE SBR2C2 bit 7 SIO2 communication clock cycle control SBR2C1 bit 6 SIO2 communication clock cycle control SBR2CO0 bit 5 5102 communication clock cycle control Value of SCON2 bits7 to5 2 Transfer clock rate TSBR1 3 Table 3 20 1 5102 Transfer Clock Rates Value of SCON2 bits 7 to 5 Transfer clock rate 3 93 SIO2 SI2WRT bit 4 SIO2 data RAM write control 1 When this bit is set to 1 the contents of data RAM are exchanged with the contents of the SBUF2 before 8 bit data transmission starts 2 When this bit is set to O the contents of data RAM are transferred to the SBUF2 before 8 bit data transmission starts but the contents of RAM remain unchanged SI2RUN bit 3 SIO2 operation flag 1 Alinthis bit indicates that SIO2 is running 2 This bit must be set with an instruction 3 This bit is automatically cleared at the end of serial transfer on the rising edge of the last clock for data transfer SI2OVR bit 2 SIO2 overrun flag 1 This bitis set on detection of a falling edge of the input clock with SI2RUN set to 0 2 This bit is set when a falling edge of the input clock is detected during internal data communication between SBUF2 and RAM on every transfer of 8 bit data 3 This bit must be read at the end of communication to verify that communication has been performed normally 4 This bit m
51. and PAS are shared with port A It is necessary to manipulate the following special function registers to control the AD converter ADCR ADRR DACR P8 P7 PA PADDR Initial value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE60 0000 0000 ADCR ADCR7 ADCR6 ADCRS ADCR4 ADCR3 ADCR2 ADCRI ADCRO EE TUER NUES NES a ruo raw pace pacer pacs paces stabec Pres unnm ew m vsr me ms rm pm m mo 3 134 LC875W00 Chapter 3 3 25 3 Circuit Configuration 3 25 3 4 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion results The conversion end bit ADCRI is set when a 32 64 128 256 Tcyc conversion is completed The conversion results are placed in the AD conversion result register ADRR 3 25 3 2 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 15 channels of analog signals 3 25 3 3 Reference voltage generator circuit 1 The reference voltage generator circuit consists of a network of ladder resistors and a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage is controlled by the refere
52. and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when R5 contains OFDFFH and the C register contains 1 since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 lies outside the basic area and is placed in the ACC as the result of LD If the instruction LD R5 C is executed when RS contains and the C register contains 2 since the basic area is 2 SFR area to FEFFH the intended address 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of B register are placed in the ACC as the result of the computation 1 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off In this addressing mode the results of adding the 7 bit signed offs
53. as system clock 101 1 32 of frequency of source oscillator selected as system clock 110 1 64 of frequency of source oscillator selected as system clock 111 Frequency of source oscillator selected as subclock 3 3 Port 0 lt Notes on the use of the clock output function gt Follow notes 1 to 3 given below when using the clock output feature Anomalies may be observed in the waveform of the port clock output if these notes are violated 1 Do not change the frequency of the clock output divider setting when CLKOEN bit 3 is set to 1 gt Do not change the settings of CKODV2 to CKODVO bits 2 to 0 2 Do not change the system clock selection when CLKOEN bit 3 is set to 1 gt Do not change the settings of CLKCB5 CLKCBA bits 5 and 4 of the OCR register 3 will not go to 0 immediately even when the user executes an instruction that loads the POFCR register with data that sets the state of CLKOEN from 1 to 0 CLKOEN is set to 0 at the end of the clock that is being output on detection of the rising edge of the clock Accordingly when changing the clock divider setting or changing the system clock selection after setting CLKOEN to 0 with an instruction be sure to read the CLKOEN value in advance and make sure that it is 0 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output 3 1 5 HALT and HOLD Mode Operation When in HALT
54. bit counter The interval at which overflows occur is 64tBST When this bit is set to 0 the base timer interrupt 0 flag is set when an overflow occurs in the 14 bit counter The interval at which overflows occur is 16384tBST This bit must be set to 1 when high speed mode is to be used BTON bit 6 Base timer operation control When this bit is set to 0 the base timer stops when the count value reaches 0 When this bit is set to 1 the base timer continues operation BTC11 bit 5 Base timer interrupt 1 period control BTC10 bit 4 Base timer interrupt 1 period control Base Timer Interrupt 0 Base Timer Interrupt 1 Period Period 16384tBST 32tBST patie ie AO ie oOo 3 E Co ees w Co _ tBST The period of the input clock selected by the input signal select register ISL BTIF1 bit 3 Base timer interrupt 1 flag This flag is set at the interval equal to the base timer interrupt 1 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIE1 bit 2 Base timer interrupt 1 request enable control Setting this bit and BTIFI to 1 generates X tal HOLD mode release signal and interrupt request to vector address 001BH BTIFO bit 1 Base timer interrupt 0 flag This flag is set at the interval equal to the base timer interrupt 0 period that is defined by BTFST and BTC10 This flag must be c
55. can be selected as the output type in 1 bit units 3 1 2 Functions 1 Input output port 8 bits POO to P07 The port output data is controlled by the port 0 data latch PO FE40 in 1 bit units T O control of POO to is accomplished by POLDDR PODDR FE41 bit 0 control of P04 to P07 is accomplished by POHDDR PODDR FE41 bit 1 Port bits selected as CMOS outputs as user options are provided with programmable pull up resistors The programmable pull up resistors for POO to are controlled by POLPU PODDR FE41 bit 2 The programmable pull up resistors for P04 to P07 are controlled by POHPU PODDR FE41 bit 3 2 Interrupt pin function POFLG PODDR FE41 bit 5 is set when an input port is specified and 0 level data is input to one of port bits whose corresponding bit in the port 0 data latch PO FE40 is set to 1 In this case if POIE PODDR FE41 bit 4 is set to 1 HOLD mode is released and an interrupt request to vector address 004BH is generated 3 Multiplexed functions Pin 05 is also used as system clock output pin P06 as timer 6 toggle output and pin P07 as timer 7 toggle output Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE40 0000 0000 R W PO PO7 P06 P05 P04 P03 P02 01 00 1 0000 rw PoDDR POFLG poe POHPU POLDDR Fe42 0000
56. clock is programmable within the range of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop bit asynchronous serial communication The baudrate is programmable within the range of 8 to 2048 Tcyc 3 Mode 2 Bus master e SIOI is used as a bus master controller The start conditions are automatically generated but the stop conditions must be generated by manipulating ports Clock synchronization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combined with mode 3 to provide support for multi master configurations The period of the output clock is programmable within the range of 2 to 512 Tcyc 4 Mode 3 Bus slave e SIOI is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the generation of an acknowledge require program intervention e SIOI can generate an interrupt by forcing the clock line to low level on the falling edge of the 8th clock for recognition by a program 5 Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable flag is set 6 Itis necessary to manipulate the following special function registers to control the serial interface 1 5101 e SCONI SBUFI 5 PI PIDDR PIFCR 3 80 Address LC875W00 Chapter 3 Initial Value R W Name BI
57. contents of TOL and are captured into the capture registers TOCAIL and at the same time on external input detection signals from the P24 INTS TIIN TOLCP TOHCP INT7 TOHCPI pin TO period TOHR TOLR 1 x TOPRR 1 x 16 bits 4 Mode 3 16 bit programmable counter with two 16 bit capture registers Timer counter 0 serves as a 16 bit programmable counter that counts the number of external input detection signals from the P72 INT2 TOIN and P73 INT3 TOIN pins The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from the P71 INTI TOHCP P73 INT3 TOIN and P20 to P27 timer OH capture input pins The contents of TOL are captured into the capture registers TOCAIL and at the same time on external input detection signals from the P24 INTS T1IN TOLCP TOHCP INT7 TOHCPI pin TO period TOHR TOLR 1 16 bits 5 Interrupt generation TOL or TOH interrupt request is generated at the counter period for timer counter TOL or TOH if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control the timer counter 0 TO e TOCNT TOPRR TOL TOLR TOHR ISL 101 I23CR I45CR I67CR 3 35 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG
58. data 5 Next transmit data processing Repeat steps 3 and 4 above To end a continuous transmit operation clear UCON3 TRNSIE2 while not clearing UCONG TEPTY2 and exit the interrupt in the step 3 processing and the transmit operation that is being performed at that time will be the last transmit operation that the UART2 executes 3 116 LC875W00 Chapter 3 3 22 5 3 Setting up the UART2 communications ports When using port 3 as the UART2 port 1 Setting up the receive port P35 Register Data Receive Port P35 Internal Pull up P35DDR State Resistor Input Off The UART2 receives no data normally if P3SDDR is set to 1 2 Setting up the transmit port P34 Register Data Internal Pull up P34DDR Transmit Port P34 State Resistor CMOS output or o r 0 Nechannet open drain output On The UART2 transmits no data if P34DDR is set to 1 3 22 6 UART2 HALT Mode Operation 3 22 6 1 Receive mode 1 receive mode operation is enabled in HALT mode If UCON2 STRDET2 is set to 1 when the microcontroller enters HALT mode the receive processing will be restarted if data that sets UCON2 RECRUN2 is input at the end of a receive operation 2 HALT mode can be released using the UART2 receive interrupt 3 22 6 2 Transmit mode 1 A transmit mode operation is enabled in HALT mode If the continuous transmit mo
59. ee ree 3 96 3 21 2 Functions eee retro rere rere rere rr rere re rere rere rere terre rere reer ere eee cree ee ee ree 3 96 3 21 3 Circuit Configuration eee eee eee ere ree Cer ree ee ee eee rer ee reer err 3 97 3 21 4 Related Registers eee eee reer eee ere eer reer ere reer rr ers 3 1 00 3 21 5 UART1 Continuous Communication Processing Examples 5551 3 104 3 21 6 UART1 HALT Mode Operation TP 3 106 Asynchronous Serial Interface 2 UART2 3 107 3 22 1 Overview eee rere errr ere rer errr errr reer errr rere rrr rer rere rere ree rece ree eee rer 3 1 07 3 22 2 Functions eee errr errr eer Crete errr errr ere re rere rere rer errr errr ee ree eee rere ee eee re 3 1 07 3 22 3 Circuit Configuration ee eee eee CeCe ere eee eee ree errr 3 1 08 3 22 4 Related Registers eee eee eee eee ee eee rere ee rere rere eee reer 3 1 11 3 22 5 UART2 Continuous Communication Processing Examples 3 115 3 22 6 UART2 HALT Mode Operation TP 3 117 PWMO PWM 1 nem MMRMHMHHHHHmHMHHHHHHMHHHHHHHHHHMHHHHHHHHHHHIHHHIHHHHHHneHmHMMennn 3 118 3 23 1 Overview 3 1 18 3 23 2 Functions errr rrr ere errr rere errr errr eer ere rere rere errr errr 3 1 18 3 23 3 Circuit Configuration
60. ere eee cee ree eee eer ee 3 75 3 18 5 SIOO Communication Examples TP PL 3 77 3 18 6 SIOO HALT Mode Operation IL 3 79 Serial Interface 1 SIO1 eee eee eee eee eee rere eee ee eee errr eee reer eee eee eee 3 80 3 1 9 1 Overview eee rere reer rer reer errr reer errr ere eee ree eee rere eee rere ee rere 3 80 3 19 2 Functions eee error rere creer rr ree rere rere rere ere rere rere reer ere eee ere eee ee ere 3 80 3 1 93 Circuit Configuration eee eee eee reece ere eee eee re eee ee rere eee creer 3 81 3 19 4 SIO1 Communication Examples eee eee eee eee eee eee rer ere ree rr 3 85 3 1 95 Related Registers eee eee eee eer rere ere eee re rere rere eee eee ee eer eer 3 89 Serial Interface 2 SIO2 eee eee eee eee ee eee eee eee ee eee ee ee eee reer eee eee eee 3 91 3 20 1 Overview eee eee rere reer err rere rere rere rere errr errr eee rere ee rere Cece ere ee ere 3 91 3 20 2 Functions eee eee rere reer rer rere rere rere rr rrr rere Creer eee re ree eee rere ee ee ree 3 91 3 20 3 Circuit Configuration 3 91 3 20 4 SIO2 Communication Examples eee eee eee eee eee eee eer errr errr 3 92 3 20 5 Related Registers 3 93 Serial Interface 1 UART1 eee eee eee eee eee reer eee nn 3 96 3 21 41 Overview eee eee terre rere rr rere rere rere rere errr rere rer reer ere eee rere ee
61. inactive TIHRUN O the match register matches When it is active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Timer 1 low byte output TTPWML TIPWML output is fixed at the high level when is inactive If TIL is active the TIPWML output is fixed at the low level when TILR FFH Timer 1 low byte output is a toggle output whose state changes on a TIL match signal when TIPWM timer 1 control register bit 4 is set to 0 When TIPWM timer 1 control register bit 4 is set to 1 this PWM output is cleared on an TIL overflow and set on a match signal 3 14 3 10 Timer 1 high byte output TTPWMH D 2 3 The TIPWMH output is fixed at the high level when T1H is inactive If TIH is active the TIPWMH output is fixed at the low level when TIHR FFH The timer high byte output is a toggle output whose state changes on a T1H match signal when 0 or TILONG 1 When 1 and TILONG 0 this PWM output is cleared on a overflow and set on a match signal 3 52 LC875W00 Chapter 3 Clock 2Tcyc gt or external events Set in l45CR FE4Ah l45SL FE4Bh registers Clock 2Tcyc gt T1H prescaler T1PWML output T1L prescaler Invert T1PWMH output Match buffer register Match buffer register Reload Reload hr T1LCMP T1HR T1HCMP flag set flag set
62. instruction as it is not cleared automatically POIE bit 4 PO interrupt request enable When this bit and POFLG to are set to 1 a HOLD mode release signal and an interrupt request to vector address 004BH are generated POHPU bit 3 PO7 to P04 pull up resistor control When this bit is set to 1 and POHDDR to 0 pull up resistors are connected to port bits 7 to P04 that are selected as CMOS output POLPU bit 2 PO3 to POO pull up resistor control When this bit is set to 1 and POLDDR to 0 pull up resistors are connected to port bits to POO that are selected as CMOS output POHDDR bit 1 P07 to P04 I O control When this bit is set to 1 7 to P04 are placed into output mode in which case the contents of the corresponding port 0 data latch PO are output When this bit is set to 0 PO7 to P04 are placed into input mode and POFLG is set when a low level is detected at a port whose corresponding port 0 data latch PO bit is set to 1 POLDDR bit 0 to POO I O control When this bit is set to 1 to POO are placed into output mode in which case the contents of the corresponding port 0 data latch PO are output When this bit is set to 0 to POO are placed into input mode and POFLG is set when a low level 15 detected at a port whose corresponding port 0 data latch PO bit is set to 1 LC875W00 Chapter 3 1 33 Port 0 function control register POFCR 1 Thisregister is a 6 bit register that contr
63. is established when HALT or HOLD mode is entered 3 23 PortA 3 7 Port A 3 7 1 Overview Port A is a 6 bit I O port equipped with programmable pull up resistors It is made up of a data control latch and a control circuit The direction of the signals can be specified in 1 bit units As a user option either CMOS output or N channel open drain output can be specified as the output type in 1 bit units 3 7 2 Functions 1 Input output ports 6 bits PAO to PAS The 8 bits of the port A data control register PA FE68 are used to control the port output data bits O to 5 The 8 bits of the port A data direction register PADDR FE69 are used to control the I O direction of data bits O to 5 in 1 bit units The output type can be selected from N channel open drain output and CMOS output as a user option Each port bit is provided with a programmable pull up resistor 2 Register configuration tis necessary to manipulate the following special function registers to control port A Initial Value 0000 0000 0000 0000 3 7 3 Related Registers 3 7 8 1 Port A data latch PA 1 The port A data latch is an 8 bit register for controlling port A output data and pull up resistors 2 When this register is read with an instruction data at pins PAO to PAS is read in If the PA FE68 is manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced
64. is generated INT6HEG bit 3 INT6 rising edge detection control INT6LEG bit 2 INT6 falling edge detection control When the data change specified in bits 3 and 2 is given to the P20 pin timer OL capture 1 signal is generated INT6LEG INT6 Interrupt Conditions P20 Pin Data No edge detected Falling edge detected 0 0 1 o SS INTG6IF bit 1 INT6 interrupt source flag This bit is set when the conditions specified by INT6HEG and INT6LEG are satisfied When this bit and the INT6 interrupt request enable bit INTO6IE are set to 1 an interrupt request to vector address 0023H is generated This bit must be cleared with an instruction as it is not cleared automatically bit 0 INT6 interrupt request enable When this bit and INTGIF are set to 1 an interrupt request to vector address 0023H is generated Port 2 3 3 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 3 5 HALT and Hold Mode Operation When in HALT or HOLD mode port 2 retains the state that is established when HALT or HOLD mode is entered 3 14 LC875W00 Chapter 3 4 3 4 1 Overview Port 3 is a 7 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a contr
65. is recognized 3 If at least one of INT4 and 5 is specified as timer 1 count clock input timer 1L functions as event counter If neither INT4 nor INTS is specified for timer 1 count clock input the timer 1L counter counts on every 2 Tcyc 3 12 LC875W00 Chapter 3 3 3 5 External interrupt 6 7 control register I67CR 1 This register is 8 bit register for controlling external interrupts 6 and 7 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4E 0000 0000 R W I67CR INT7HEG INT7LEG INT7IF INT7IE INTOHEG INT6LEG INTGIF INTGIE INT7HEG bit 7 INT7 rising edge detection control INT7LEG bit 6 INT7 falling edge detection control When the data change specified in bits 7 and 6 is given to the P24 pin timer OH capture 1 signal is generated INT7HEG INT7LEG INT7 Interrupt Conditions P24 Pin Data No edge detected Falling edge detected 0 0 1 o Rising ease detects INT7IF bit 5 INT7 interrupt source This bit is set when the conditions specified by INT7HEG and INT7LEG are satisfied When this bit and the INT7 interrupt request enable bit INT7IE are set to 1 an interrupt request to vector address 002BH is generated This bit must be cleared with an instruction as it is not cleared automatically INT7IE bit 4 INT7 interrupt request enable When this bit and INT7IF are set to 1 an interrupt request to vector address 002BH
66. occurs asynchronously with any clock for the microcontroller Capture operation The value of the high speed clock counter is captured into NKCOV and NKCAP2 to NKCAPO in synchronization with the capture operation of TOL timer 0 low byte NKCOV is a carry into timer counter 0 When this bit is set to 1 the capture value of timer counter 0 must be corrected by 1 NKCAP2 to NKCAPO carry the capture value of the high speed clock counter Interrupt generation The required timer counter 0 flag is set when the high speed clock counter and timer counter 0 keep counting and their count value reaches timer 0 match register value 1 x 8 value of NKCMP2 to NKCMPO In this case a TOL or TOH interrupt request is generated if the interrupt request enable bit is set 3 44 LC875W00 Chapter 3 5 Itis necessary to manipulate the following special function registers to control the high speed clock counter NKREG PITST TOCNT TOL TOH TOLR TOHR ISL IO1CR I23CR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE7D 0000 0000 R W NKREG NKEN NKCMP2 NKCOV NKCAP2 NKCAPI NKCAPO ww pitst psor RW 0000 0000 TOLRS TOLR4 TOLR3 RW RW RW RW 3 13 3 Circuit Configuration 3 13 3 1 High speed clock counter control register NKREG 8 bit register 1 This register controls the high speed clock counter It contains the start
67. or HOLD mode the state of low level output is retained but the high level output of CMOS and pull up resistors are turned off 3 4 LC875W00 Chapter 3 2 Port 1 3 2 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit Control of the input output signal direction is accomplished by the data direction register in 1 bit units Port 1 can also be used as a serial interface I O port or PWM output port by manipulating the function control register As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 2 2 Functions 1 Input output port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch P1 FE44 and the I O direction is controlled by the port data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor 2 Multiplexed functions P17 is also used as the timer 1 PWMH base timer BUZ output P16 as the timer 1 PWML output P15 to P13 as SIO1 and P12 to P10 as SIOO I O Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W Pll P10 Pl P17 P16 P15 P14 P13 P12 PIDDR rec nono Pitst
68. output transistor for watchdog timer is controlled by a program on time is automatic Input output pull up resistor controlled by a program P71 to P73 Input mode Pull up resistor off P80 to P87 N channel open drain N channel transistor off PAO to PAS Input mode Pull up resistor off N channel open drain N channel transistor is turned on off under program control Input output pull up resistor is controlled by a program Input output pull up resistor is controlled by a program PBO to PB7 Input mode Pull up resistor off PCO to PC4 PC6 to PC7 Input mode Pull up resistor off 5 Output mode N channel transistor on Pull up resistor off PEO to PE7 Input mode Pull up resistor off PFO to PF7 Input mode Pull up resistor resistor is controlled off by a program SI2P0 to Input mode Input output is SI2P3 controlled by a program PWMO to Input mode Input output is PWMI controlled by a program Input output pull up resistor is controlled by a program Input output pull up resistor is controlled by a program Input output pull up resistor is controlled by a program Input output pull up Same as in normal mode nput output is in the state established at entry time Pull up resistor off N channel output transistor for watchdog timer is off automatic on time extension function reset 4 17 Stan
69. read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESC 0000 0000 R W P7 P73DDR P72DDR P71DDR P70DDR P73DT P72DT P7IDT P7ODT Register Data Port P7n State Internal Pull up P7nDDR Input Resistor Enabled ae A o i O LC875W00 Chapter P73DDR bit 7 P73 I O control A 1 or 0 in this bit controls the output CMOS or input of pin P73 P72DDR bit 6 P72 1 0 control A 1 or 0 in this bit controls the output CMOS or input of pin P72 P71DDR bit 5 P71 I O control A 1 or 0 in this bit controls the output CMOS or input of pin P71 P70DDR bit 4 P70 I O control A 1 or 0 in this bit controls the output N channel open drain or input of pin P70 P73DT bit 3 P73 data The value of this bit is output from pin P73 when P73DDR is set to 1 A 1 or 0 in this bit turns on or off the internal pull up resistor for pin P73 P72DT bit 2 P72 data The value of this bit is output from pin P72 when P72DDR is set to 1 A 1 or 0 in this bit turns on or off the internal pull up resistor for pin P72 P71DT bit 1 P71 data The value of this bit is output from pin P71 when P71DDR is set to 1 A 1 or 0 in this bit turns on or off the internal pull up resistor for pin P71 P70DT bit 0 P70 data The value of this bit is output from pin P70 when P70DDR is set to 1 Since this bit is N channel open drain output
70. tal HOLD modes that are used to reduce current consumption at power failure time or in program standby mode In a standby mode the execution of all instructions is suspended 4 3 2 Functions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing HALT mode is entered by setting bit 0 of the PCON register to 1 Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode All oscillations are suspended The microcontroller suspends the execution of instructions and its peripheral circuits stop processing HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 0 In this case bit 0 of the PCON register HALT mode setting flag is automatically set When a reset occurs or a HOLD mode release signal INTO INT2 INT4 5 or POINT occurs bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode 3 X tal HOLD mode All oscillations except the subclock oscillation are suspended The microcontroller suspends the execution of instructions and all the peripheral circuits except the base timer stop processing X tal HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 1s set to 1 In this case bit 0 of the PCON register HALT mode setting flag is automatically set
71. the start bit falling edge of the signal is detected at the receive port P35 5 Nextreceive data processing Repeat steps 2 3 and 4 above To end a continuous receive operation clear UCON2 STRDET2 during a receive operation and this receive operation will be the last receive operation that the UART2 executes 3 115 UART1 3 22 5 2 Continuous 8 bit data transmit mode first transmit data 55H Stop bit cM ee Next start bit Beginning of Start bit Transmit data LSB first Beginning of transmi my P34 output i End of trangmit TUBR2 1 lt 1 AS 1 gt 3 1 lt 5 1 1 1 2 4 Figure 3 22 4 Example of Continuous 8 bit Data Transmit Mode Processing 1 Setting the clock Setthe transfer rate UBR2 Setting up transmit data Load the transmit data TBUF2 55H Setting the data length transmit port and interrupts Setup the transmit control register UCON3 31H Set P34DDR P3DDR bit 4 to 0 and P34 P3 bit 4 to 0 2 Starting a transmit operation e Set UCON3 TRUN2 3 Transmit interrupt processing Load the next transmit data TBUF2 xxH Clear UCON3 TEPTY2 and exit the interrupt routine 4 End ofa transmit operation e When the transmit operation ends UCON3 TRUN2 is automatically cleared and automatically set in the same cycle Tcyc continuous data transmt mode only this processing takes 1 Tcyc of time The UART2 then starts transmission of the next transmit
72. the mode Set as follows SIIMO 1 SIIMI 1 SIIDIR SIIIE 1 SIIREC 0 Setting up ports Designate the clock and data ports as N channel open drain output ports Starting communication waiting for an address Set SILREC SIIRUN is automatically set on detection of a start bit Perform receive processing 8 bits and set the clock output to 0 on the falling edge of the 8th clock which generates an interrupt Checking for address data after an interrupt Detecting a start condition sets SILOVR Check SIITRUNz1 and SIIOVR 1 to determine if the address has been received 5 is not automatically cleared Clear it by instruction Read SBUF1 and check the address If no address match occurs clear SILRUN and SIIEND and exit interrupt processing then wait for a stop condition detection at in step 8 Receiving data Clear SIIEND and exit interrupt processing If a receive sequence has been performed send an acknowledge and release the clock port after the lapse of SBRI value 1 x Tcyc When a stop condition is detected SITRUN is automatically cleared and an interrupt is generated Then clear SILEND to exit interrupt processing and return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs The clock counter is cleared if a start condition is detected in the middle of receive proc
73. two 16 bit capture registers Mode 3 16 bit programmable counter with two 16 bit capture registers Functions Mode 0 Two channels of 8 bit programmable timer with a programmable prescaler with two 8 bit capture registers Two independent 8 bit programmable timers TOL and TOH run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P72 INT2 TOIN TOCLP and P20 to P27 timer OL capture input pins The contents of TOL are captured into the capture register on external input detection signals from the P20 INTS T 1IN TOLCP TOHCP INT6 TOLCP1 pin The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P71 INTI TOHCP P73 INT3 TOIN TOHCP P20 to P27 timer OH capture input pins The contents of TOH are captured into the capture register TOCA1H on external input detection signals from the P24 INTS T1IN TOLCP TOHCP INT7 TOHCPI pin TOL period TOLR 1 x TOPRR 1 x Tcyc TOH period TOHR 1 x TOPRR 1 x Tcyc Tcyc Period of cycle clock Mode 1 8 bit programmable timer with a programmable prescaler with two 8 bit capture registers 8 bit programmable counter with two 8 bit capture registers TOL serves as an 8 bit programmable counter that counts the number of external input detection signals fro
74. type however it is placed in the high impedance state when P70DT is set to 1 A 1 or 0 in this bit turns on or off the internal pull up resistor for pin P70 3 5 3 2 External interrupt 0 1 control register 101CR 1 This register is 8 bit register for controlling external interrupts 0 and 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W 101 INTILH INTILV INTHE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P71 Pin Data 0 Falling edge detected Low level detected 0 fe es Port 7 INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit INTIIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 0
75. with 6 bit prescaler z T4R7 T4R6 T4R5 T4R4 T4R3 T4R2 FEsF 0000 0000 Rm S bit timer with 6 bit presoaler TT 6 Tora oom ew m M ws m mooo mw f PME POLPU Ponor E ako cLKoDvr GLKODVO FE43 0000 0000 2 Controls XT2 general purpose p XT2PCB7 XT2PCB6 XT2PCB5 XT2PCB4 XT2PCB3 XT2PCB2 XT2DR XT2DT port output Fu 0000 0000 RF Ms P4 P Pi 0000 0000 RW Pio PUDOR PISODR PI2DDR PIODDR Fese 000000 RU eR UFG Piaron Piaron PI2FCR PIOFCR re F fm Fu 0000 0000 Rw m Ps PM Pm Ph 0000 0000 reaa 00000 RU ias insir INISIE inanca INTALEG 0000 0000 RW i5 5 i2 raso 00 0000 A LL _ 000 0000 Fut 0000 0000 Rw INPRE INTLEG INITIF ime
76. 0 ea 268 1 o rsng ease deca SS INT4IF bit 1 INT4 interrupt source flag This bit is set when the conditions specified by INT4HEG and INT4LEG are satisfied When this bit and the INT4 interrupt request enable bit INTAIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when INT4 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 it is recommended that INT4 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT4IE bit 0 INT4 interrupt request enable When this bit and INT4IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 3 34 External interrupt 4 5 pin select register 14551 1 This register is an 8 bit register used to select pins for the external interrupts 4 and 5 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE4B 0000 0000 R W I45SL I5SL3 I5SL2 1561 1 1551 0 14513 14512 14511 14510 Port 2 15513 bit 7 INT5 pin select 15512 bit 6 INT5 pin select I5SL3 I5SL2 Pin Assigned to INT5 Port P24 Port P25 0 0 o0 1 j o1 0 P
77. 0 Chapter 2 2 11 6 ROM Table Look up Addressing The LC870000 series microcontrollers can read 2 byte data into the BA register pair at once using the LDCW instruction Three addressing modes Rn C and off are available for this purpose In this case only Rn is configured as a 17 bit register 128K byte space For models with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SET1 or instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 TBL gt gt 16 amp 1 Loads Pl in PSW with bit 16 of the TBL address STW RO Loads indirect register RO with the TBL address bits 16 to 0 LDCW l Reads the ROM table B 78H ACC 12H MOV 1 Loads register with 01H LDCW _ RO C Reads the ROM table B 78H ACC 12H INC Increments the register by 1 LDCW _ RO Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW needs to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing LC870000 series mi
78. 1 4 n 1 2 3 Period of cycle clock 2 Timer 5 5 Timer 5 is an 8 bit timer that runs on either 4Tcyc 16Tcyc 64Tcyc clock T5 period T5R 1 x 4 nz1 2 3 Tcyc Period of cycle clock 3 Interrupt generation Interrupt request to vector address 004BH is generated when the overflow flag is set at the interval of timer 4 or timer 5 period and the corresponding interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control the timer 4 T4 and timer 5 T5 T45CNT T4R T5R Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3C 0000 0000 R W T45CNT 5 5 0 T4CO 5 TSIE TSR7 3 15 3 Circuit Configuration 3 15 3 1 Timer 4 5 control register T45CNT 8 bit register 1 This register controls the operation and interrupts of T4 and T5 3 15 3 2 Timer 4 counter TACTR 8 bit counter 1 timer 4 counter counts the number of clocks from the timer 4 prescaler Its value reaches 0 on the clock following the clock that brought about the value specified in the timer 4 period setting register T4R when the interrupt flag is set 2 When T4CO and T4C1 T45CNT FE3C bits 4 and 5 set to 0 the timer 4 counter stops at a count value of 0 In the other cases the timer 4 counter continues operation 3 When data is written into wh
79. 1 Output TTPWMH T1PWML T1PWMH T1PWML Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC 4 x Tcyc count x 4 x Tcyc or Period 2 TILR 1 x TILPRC count x events PWM output Period 256 x TI HPRC count x Tcyc PWM output Period 256 x TILPRC count x Tcyc Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC TIPWML period count x 4 x Tcyc 2 1 0 or Period 2 T1HR 1 x TIHPRC count x or Period 2 TILR 1 x TILPRC TILR 1 x TILPRC count count x events x events 3 1 1 Toggle output Period T1HR 1 x TIHPRC count x PWM output Period 256 x TILPRC count TIPWML period x 2 x Tcyc T1HCMP bit 3 T1H match flag This flag is set if reaches 0 when is active TIHRUN 1 This flag must be cleared with an instruction 3 55 T1HIE bit 2 interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and are set to 1 T1LCMP bit 1 T1L match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction T1LIE bit 0 T1L interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 Note TIHCMP and TILCMP must be cleared to 0 with an instruction
80. 10L NITL S LNI L8c VINMd 0 d SINMd T d IXLN d IXUN Ed XLN PEc 9 d 29 1 3 Pinout SI2P1 SI2 SB2 SI2P0 SO2 PF6 5 PF4 PF3 PF2 PEL PFO VDD4 VSS4 PET PE6 5 4 2 1 PEO QIP100E 14x20 lead free halogen free product 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 75 74 73 72 71 50 49 48 47 46 45 44 43 O 82 83 84 88 42 89 LC875W00 90 QIP100E 38 91 92 93 37 94 36 95 35 34 97 33 98 32 99 31 22 23 24 25 26 27 28 29 30 19 20 21 9 10 11 12 13 14 15 16 17 18 8 5 4 Z08 HINMdTL 21d IINMdTL 01d 1 25 014 185 15 4 0 105 614 005 1 7 085 0IS 11d 7 005 01 23 28 9Nv 98d J SNv s8d YNv vsd Nv 8d Nv 28d INV T8 C 242 145 Issa 0 UNV ZLX OINV LLX 1 sau 0 dOHOL NIOL amp LNI 4d 49 10 L NIO L Z LNI G4d 1 6NV dOHOL TINI TLd LJ 8Nv d9 10 L 0 LNI 02d 0 INV SVd LJ J INV Vd 7 81 PB2 85 1 86 87 5 4 P
81. 1DDR PIODDR Register Data Port P1n State Internal Pull up 0 0 Embed woe neges Enabled Internal pull up resister Enabled High open CMOS N channel open drain 3 2 8 3 1 function control register P1FCR 1 Thisregister is an 8 bit register that controls the multiplexed output of port 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 0000 0000 R W PIFCR P17FCR P16FCR PISFCR P14FCR P12FCR PIOFCR Pin Pin Data in Output Mode P1nDDR 1 Value of port data latch P17 AND data of timer 1 PWMH and base timer BUZ outputs NAND data of timer 1 PWMH and base timer BUZ outputs Value of port data latch P16 Timer 1 PWML data Timer 1 PWML inverted data Value of port data latch P15 SIO1 clock output data High output Value of port data latch P14 SIO1 output data High output Value of port data latch P13 SIO1 output data High output Value of port data latch P12 SIOO clock output data High output Value of port data latch P11 SIOO output data High output Value of port data latch P10 SIOO output data High output o1 o0 rae RES ea 0 So ME NAE EE Lor og EN NEUEN Lor og j ME UN UE d _ ecl a ae p pM BST NINE NAE EK E E E zr
82. 4 Load SCON2 FE38 with data to set the transfer clock and transfer mode and to start the transfer Control Internal Clock Transmit Start Flag Overrun End Flag Interrupt Period Receive Error Flag Enable Mode Flag SCON2 bit 765 SBR2C2 to 0 4 SDWRT 5 Transmis Stop No No Interrupt sion only overrun interrupt disabled error request 001 9 Receive 1 Start 1 Overrun 1 Interrupt 1 Interrupt transmit error request enabled receive present present Automatically Automatically Automatically Interrupt cleared at end set on error set at end of request to of processing processing vector address 003BH generated when both SDEND and SDIE are set to 1 111 5 Starting operation e When SIZ2WRT 1 the contents of SBUF2 and RAM at the starting address are automatically exchanged and operation starts e When SI2WRT 0 the SBUF2 is automatically loaded with the contents of RAM at the starting address and operation starts 6 Terminating operation e When the communication of the specified number of bytes ends the SI2RUN is cleared and SDEND is set automatically Note that the last data received is left not in RAM but in the SBUF2 3 20 5 Related Registers 3 20 5 1 5102 control register SCON2 1 Thisregister is an 8 bit register that controls the operation and interrupts of SIO2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE38 0000 0000 R
83. 4 1 the available instructions vary depending on the RAM address The efficiency of the ROM used and a higher execution speed can be attempted using these instructions properly 2 2 LC875W00 Chapter 2 FFFFH Reserved for system FFOOH FEFFH SFR space FDFFH 2 900 Stack space 9 bit 0200H 01FFH KRAAK 7 0 pmS Note Some registers are 9 bit gt 0100H 0000H instruction direct long Bit instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect Non bit instruction direct short Figure 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the low order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the high order 9 bits in SP 2 after which SP is set to SP 2 2 5 Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address FEOOH in the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO 00 0000 0000 R W AREG AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREGO 2 6 Register
84. 6 1 Overview Port 8 is an 8 bit I O port that consists of a data latch and a control circuit The I O direction can be set in 1 bit units The output type of port 8 is N channel open drain There is no user option for this port 3 6 2 Functions 1 Input output port 8 bits P80 to P87 The port 8 data latch P8 FE63 is used to control switching between L level output and output disable 2 Analog voltage input function Ports P80 to P87 are used to receive the analog voltage input to the AD converter Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE63 1111 1111 R W P8 P87 P86 P85 P84 P83 P82 P81 P80 3 6 3 Related Registers 3 6 3 1 Port 8 data latch P8 1 The port 8 data latch is an 8 bit register for controlling I O of port 8 2 When this register is read with an instruction data at pins P80 to P87 is read into bits 0 to 7 of the register If the P8 FE63 is manipulated using the NOTI CLR1 SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 8 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE63 1111 1111 R W P8 P87 P86 P85 P84 P83 P82 P81 P80 Register Data Port P8n State P8n Input Output 0 Enabled Lo W 3 6 4 HALT and HOLD Mode Operation When in HALT or HOLD mode port 8 retains the state that
85. 7 3 2 6 bit binary up counter 1 This counter is a 6 bit up counter that receives as its input the signal selected by the input signal select register ISL or the overflow signal from the 8 bit counter and generates set signals for base timer interrupts 0 and 1 The switching of the input clock is accomplished by the base timer control register BTCR 3 17 3 3 Base timer input clock source 1 The clock input to the base timer tBST can be selected from among the cycle clock timer 0 prescaler and subclock via the input signal select register ISL Set in ISL FE5Fh register i 16tBST Buzzer output 8 bit counter Tcyc Timer 0 prescaler Selector Subclock 256tBST 6 bit counter 16384 64tBST gt BTIFO flag set Selector BTIF1 flag set Selector Figure 3 17 1 Base Timer Block Diagram 3 68 LC875W00 Chapter 3 3 17 4 Related Registers 3 17 4 1 Base timer control register BTCR 1 This register is 8 bit register that controls the operation of the base timer Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTON BTC10 BTIF1 BTIFO BTIEO BTFST bit 7 Base timer interrupt 0 period control This bit is used to select the interval at which base timer interrupt 0 is to occur When this bit is set to 1 the base timer interrupt O flag is set when an overflow occurs in the 6
86. 8 bit programmable timer lt 8 bit programmable timer Figure 3 14 1 Mode 0 Block Diagram T1LONG 0 T1PWM 0 Clock 1 gt T1L prescaler Clock 1Tcyc gt T1H prescaler Overflow Reset Overflow T1PWML output Set Reset T1PWMH output Set Match buffer register Match buffer register lt Reload Y 2 Reload T1LCMP T1HCMP lt 8 bit PWM lt 8 bit PWM Figure 3 14 2 Mode 1 Block Diagram T1LONG 0 T1PWM 1 Clock 2Tcyc TiL prescaler or external events Set in 145CR FE4Ah I45SL FEABh registers Clear TIL Invert T1PWMH output Invert T1PWML output Match buffer register Match buffer register Reload Badiy 3 TiLR T1HR flag set flag set lt 16 bit programmable timer gt Figure 3 14 3 Mode 2 Block Diagram T1LONG 1 T1PWM 0 Clock Clock 1 gt prescaler T1H prescaler lt T1PWML output Match buffer Overflow Invert T1PWMH output register Match buffer register Reload Reload YY uestem T1LCMP T1HCMP T1LR flag set flag set 16 bit programmable timer gt Figure 3 14 4 Mode Block Diagram T1LONG 1 T1PWM 1 3 54 LC875W00 Chapter 3 3 14 4 Related Registers 3 14 41 Timer 1 control register T1CNT 1 This register is an 8 bit register that controls the o
87. B3 VSS3 VDD3 PCT DBGP2 PC4 PC6 DBGP1 PC5 DBGPO PC3 rci 96 PCO PAO PAL paz 100 SANYO 1 5 1 4 System Block Diagram Interrupt control le Standby control 4 ROM Flash ROM M CF 5 RC 5 55 5 4 5 0 k Bus interface ACC SIO1 6 7 Port 0 B register SIO2 gt Port 1 C register Timer 0 lt gt gt Port 3 Timer 1 gt gt Port 7 BOT 4 gt Port 8 PSW Timer 5 ADC RAR PWM 0 INTO to INT3 noise filter RAM PWM 1 Port 2 INT4 to INT7 Stack pointer Base timer lt gt Port A P Timer 6 Port B Watchdog timer Timer 7 lt gt gt Port UART 1 4 7 gt UART 2 gt Port F PWM 5 gt 78 PWM 4 1 6 LC875W00 Chapter 1 1 5 Pin Functions Pin Description Option VSS1 VSS2 power supply pins No VSS3 VSS4 VDDI VDD2 power supply pins VDD3 VDD4 Port Porto 8 bit I O port POO to P07 O specifiable in 4 bit units Pull up resistors can
88. BRSEL 1 32 64 8192 TUBR UBR value 1 x Tcyc value range to 3 Tcyc Setting the to 00 H is inhibited Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FED2 0000 0000 R W UBR UBRG7 UBRG6 UBRGS UBRG4 UBRG3 UBRG2 UBRGI UBRGO 3 102 3 21 4 4 1 LC875W00 Chapter UART1 transmit data register This register is an 8 bit register that stores the data to be transmitted through the UART1 Data from the TBUF is transferred to the transmit shift register TSFT at the beginning of a transmit operation Load the next data after checking the transmit shift register transfer flag UCONI TEPTY Bit 8 of the transmit data must be loaded into the transmit data bit 8 storage bit UCON1 TBITS8 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FED3 3 21 4 5 1 2 0000 0000 R W TBUF TBUF6 TBUF5 TBUF4 TBUF3 TBUF2 TBUFO UART1 receive data register RBUF This register is an 8 bit register that stores the data that is received through the The data from the receive shift register RSFT is transferred to this RBUF at the end of a receive operation Bit 8 of the received data is placed in the receive data bit 8 storage bit UCONO RBITS Bit 7 of RBUF is set to 0 when the receive data length is 7 bits Address Initial Value R W
89. C1 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock Subclock Timer counter 0 prescaler output BUZON bit 3 Buzzer output select This bit enables the buzzer output tBST 16 When this bit is set to 1 the signal that is derived by dividing the base timer clock by 16 is sent to port P17 as buzzer output When this bit is set to 0 the buzzer output is held high NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select NFSEL NFON Noise Filter Time Constant 1 1 STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When this bit is set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P72 Note When timer OL capture signal input or timer OH capture signal input is specified for INT4 or 5 together with port 7 the signal from port 7 is ignored 3 5 4 Options There is no user option for port 7 3 5 5 HALT HOLD Mode Operation The pull up resistor of P70 is turned off P71 to P73 retain the state that is established when HALT or HOLD mode is entered 3 22 LC875W00 Chapter 3 6 8 3
90. CMOS 8 BIT MICROCONTROLLER LC875W00 SERIES eel USER S MANUAL i REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or
91. D1 pin and prolong the backup time Be sure to electrically short the VSS1 VSS2 VSS3 and VSS4 pins Example 1 When backup is active in HOLD mode the high level of the port outputs is supplied by the backup capacitors Power NDVI supply 4 For backup VDD2 777 77 VDD3 777 VDD4 77 VSS1 VSS2 VSS3 554 Example 2 The high level output at the ports is not sustained and unstable when the HOLD mode backup is in effect Power VDD1 supply For backup 1 VDD2 777 E 777 gt VDD3 777 1 7 7 VSS1 VSS2 553 554 77 2 Internal Configuration 2 1 Memory Space LC875W00 Chapter 2 LC870000 series microcontrollers have the following three types of memory space 256K bytes 128K bytes 2 banks 64K bytes 0000H to out of 0000H to FFFFH is shared 1 Program memory space 2 Internal data memory space 3 External data memory space Address Program memory pas ROM bank 1 1FFFFH ROM bank 0 128KB 00000H with the stack area 16M bytes Address FFFFH FFOOH FEFFH FDFFH 0000H External data Address memory space FFFFFFH RAM 16 MB 000000H Note SFR is the area in which special function registers such as the accumulator are allocated see Appendix 1 Figure 2 1 1 Types of Memory Space
92. Falling edge detected 0 1 Low level detected INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 5 33 External interrupt 2 3 control register I23CR 1 This register is an 8 bit register for controlling external interrupts 2 and 3 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W 123CR INT3HEG INT3LEG INT3IF INT3IE 2 INT2LEG INT2IF INT2IE bit 7 INT3 rising edge detection control INT3LEG bit 6 INT3 falling edge detection control INT3HEG INT3LEG INT3 Interrupt Conditions P73 Pin Data No edge detected Falling edge detected 0 0 or 1 0 1 INTSIF bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit
93. Fixed bit This bit must always be set to 0 PFDDR2 bit 5 PF5 PF4 I O control A lorO in this bit controls the output CMOS or input of pins PF5 PFSEL2 bit 4 Fixed bit This bit must always be set to 0 PFDDR 1 bit 3 PF2 I O control A lorO in this bit controls the output CMOS or input of pins and PF2 PFSEL1 bit 2 Fixed bit This bit must always be set to 0 PFDDRO bit 1 PF1 PFO I O control A lorO in this bit controls the output CMOS or input of pins and PFO PFSELO bit 0 Fixed bit This bit must always be set to 0 LC875W00 Chapter Caution The output input control of the PF pins cannot be set up properly if the PFSELn is set to 1 3 11 4 HALT and HOLD Mode Operation When in HALT or HOLD mode port F retains the state that is established when HALT or HOLD mode is entered 3 33 3 12 Timer Counter 0 TO 3 12 1 Overview The timer counter 0 TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions 1 2 3 4 3 12 2 1 2 0 Two channels of 8 bit programmable timer with a programmable prescaler with two 8 bit capture registers Mode 1 8 bit programmable timer with a programmable prescaler with two 8 bit capture registers 8 bit programmable counter with two 8 bit capture registers Mode 2 16 bit programmable timer with a programmable prescaler with
94. ID SI2POD Register Data Port SI2Pn State SDPnC S12PnD Input Output Enabled Open 0 0 Port SIO2 Output SIO2 Input SDPO Data CMOS SI2P1 Data N channel open drain SI2P2 Clock CMOS SI2P3 Clock CMOS C A 3 95 UART1 3 21 Asynchronous Serial Interface 1 UART1 3 21 1 Overview This series of microcontrollers incorporates an asynchronous serial interface 1 UART1 that has the following characteristics and features 1 Data length 7 8 9 bits LSB first 2 Stop bits 1 bit 2 bits in continuous transmission mode 3 Parity bits None 4 Transfer rate 2 to 258 or to E Tcyc 5 Full duplex communication The independent transmitter and receiver blocks allow both transmit and receive operations to be performed at the same time Both transmitter and receiver blocks adopt a double buffer configuration so that data can be transmitted and received continuously 3 21 2 Functions 1 Asynchronous serial UARTI Performs full duplex asynchronous serial communication using a data length of 7 8 or 9 bits with 1 stop bit The transfer rate of the UARTI is programmable within the range of e to 208 64 8192 3 to 73 2 Continuous data transmission reception Performs continuous transmission of serial data whose data length and transfer rate are fixed the data length and transfer rate that are identified at the beginning of transmission
95. INT or a reset occurs 4 BitO is automatically set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into HALT mode 2 This bit is automatically set when bit is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 9 System Clock 4 2 4 2 Oscillation control register OCR 8 bit register 1 This register is an 8 bit register that controls the operation of the oscillator circuits selects the system clock and reads data from the XT1 and XT2 pins Except for read only bits 3 and 2 all bits of this register can be read or written Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEOE 0000 XX00 R W OCR CLKSGL EXTOSC CLKCB5 CLKCB4 XT2IN XTIIN RCSTOP CFSTOP CLKSGL bit 7 Clock frequency division select 1 When this bit is set to 1 the clock selected by bits 4 and 5 is used as the system clock as is 2 When this bit is set to 0 the clock having the frequency of of the clock selected by bits 4 and 5 is used as the system clock EXTOSC bit 6 XT1 XT2 function control 1 When this bit is set to 1 the and XT2 pins serve as the pins for subclock oscillation and are ready for oscillation when a crystal resonator 32 768kHz standard capacitors feedback resistors and damping resistors are connected When the OCR register is read in this case bit 3 reads the data at the X
96. INT4IE INT5HEG bit 7 INT5 rising edge detection control INT5LEG bit 6 INT5 falling edge detection control INT5HEG INT5LEG INT5 Interrupt Conditions Pin Data No edge detected Falling edge detected 0 0 ra 1 0 LC875W00 Chapter INTSIF bit 5 INT5 interrupt source This bit is set when the conditions specified by INTSHEG and INTSLEG are satisfied When this bit and the INTS interrupt request enable bit INTSIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated The interrupt flag however cannot be set by a rising edge occurring when INTS data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when INTS data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INTS5 it is recommended that 5 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INTSIE bit 4 INT5 interrupt request enable When this bit and INTSIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated INTAHEG bit 3 INT4 rising edge detection control INTALEG bit 2 INT4 falling edge detection control INTAHEG INT4LEG INT4 Interrupt Conditions Pin Data No edge detected Falling edge detected 0
97. IT4 BIT3 BIT2 BIT1 BITO FE24 0000 0000 R W PWMOC PWMOC7 PWMOC6 PWMOCS PWMOC4 ENPWMI ENPWMO PWMOOV PWMOIE PWMOC7 to bits 7 to 4 PWMO PWM f period control e Fundamental wave period Value represented by PWMOC7 to PWMOCA 1 x 16 Overall period Fundamental wave period x 16 ENPWM bit 3 PWM1 operation control e When this bit is set to 1 PWM1 is activated e When this bit is set to 0 the PWMI output ternary can be controlled using bits 7 to 4 of PWMIL bit 2 PWMO operation control When this bit is set to 1 PWMO is activated When this bit is set to 0 the PWMO output ternary can be controlled using bits 7 to 4 of PWMOL PWMOOV bit 1 PWMO PWMt overflow flag This bit is set at the interval equal to the overall period of PWM This flag must be cleared with an instruction PWMOIE bit 0 PWMO PWM interrupt request enable control An interrupt request to vector addresses 004BH is generated when this bit and PWMOOV are set to 1 3 28 4 PWMO compare register L PWMOL 4 bit register 1 Thisregister controls the additional pulses of PWMO 2 PWMOL is assigned bits 7 to 4 and all of its low order 4 bits set to 1 when read 3 When the PWMO control bit PWMOC FE24 bit 2 is set to 0 the output of PWMO ternary can be controlled using bits 7 to 4 of PWMOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT
98. ITS BIT2 BIT1 BITO FEOF 0H00 H000 R W WDT WDTFLG WDTBS WDTHLT WDTCLR WDTRST WDTRUN Bit Name Function WDTFLG bit 7 Runaway detection flag 0 No runaway 1 Runaway WDTBS bit 5 General purpose flag Can be used as a general purpose flag WDTHLT bit 4 HALT HOLD mode function control 0 Enables the watchdog timer 1 Disables the watchdog timer WDTCLR bit 2 Watchdog timer clear control 0 Disables the watchdog timer for clearing 1 Enables the watchdog timer for clearing 0 Disables reset runaway condition 1 Triggers reset on a runway condition WDTRUN bit 0 Watchdog timer operation control 0 Maintains watchdog timer operating state 1 Starts watchdog timer operation WDTFLG bit 7 Runaway detection flag This bit is set when a program runaway condition is detected by the watchdog timer The application can identify the occurrence of a program runaway condition by monitoring this bit provided that WDTRST is set to 1 This bit is not reset automatically It must be reset with an instruction 4 22 LC875W00 Chapter 4 WDTBS5 bit 5 General purpose flag This bit can be used as a general purpose flag Manipulating this bit exerts no influence on the operation of the functional block WDTHLT bit 4 HALT HOLD mode function control This bit enables 0 or disables 1 the watchdog timer when the microcontroller is in the HALT or HOLD state When this bit is set to 1 WDTCLR WDTRST
99. KNEE PENNE RENE SEE Pele eam ae Sele cer ie EE MERE EE E 4 1 4 1 2 Functions ssassasanasansnuansanasasanansaassacunanasasauauhanalaashshasahdasasiuunuanauusunanuauuaa 4 1 4 1 3 Circuit Configuration M RI n m eee er eee NN eh 4 2 4 1 4 Related Registers E RR EALA E RU RIA 4 3 4 2 System Clock Generator Function 4 6 4 2 1 Overview MEER ERN RENE RES ER EN EN QE DA EE E E 4 6 4 2 2 Functions ao 4 6 4 2 3 Circuit Configuration RETR REC ee ee ICICI ERE EAT 4 7 4 2 4 Related Registers ORS SE COR OSC EBEN AC RE ES PE EE E EE RU QE QE E M ME 4 9 4 3 Standby Function me HH 4 13 4 3 1 Overview 4 13 4 3 2 Functions sassananasassanansanausauuanuausanunuuasanasuausaAnsaAnanunuansanasausunansassanunuansananuus 4 13 4 3 3 Related Registers em miM m GEN M M m m MIB M URB M N 4 14 4 4 Reset Function MICE fur ER LEO etnias aia ae wey EUCH RET SS 4 1 9 4 4 1 Overview HVE
100. Mode 1 Asynchronous Serial UART Block Diagram SI1M1 0 511 0 1 3 84 LC875W00 Chapter 3 3 19 4 SIO1 Communication Examples 3 19 4 1 Synchronous serial communication mode 0 1 Setting the clock Setup SBRI when using an internal clock 2 Setting the mode e Set as follows SIIMO 0 5 1 0 SIIDIR SIME 1 3 Setting up the ports and SIIREC bit 4 Clock Port P15 Internal clock Output Data Output Port Data I O Port P13 P14 Data transmission only Output Data transmission reception 3 wire Output Data transmission reception 2 wire N channel open drain output 4 Setting up output data e Write output data into SBUFI data transmission mode SI1REC 0 SI1REC 5 Starting operation Set SHRUN 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing 3 19 4 2 Asynchronous serial communication mode 1 1 Setting the baudrate Setup SBRI 2 Setting the mode Setas follows SIIMO 1 SIIMI 0 SIIDIR SIIIE 1 3 Setting up the ports Data Output Port Data I O Port P13 P14 Data transmission reception 2 wire Output Input Data transmission reception 1 wire aE are N channel open drain output 4 Starting transmission e Set SIIREC to 0 and write output data into SBUFI e Set SIIRU
101. N 3 85 SIO1 Note Use the SIO1 data I O port P14 when using the 8101 transmission only in mode 1 In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode 1 is on the falling edge of data is always detected at the data I O port P14 Consequently if the transmit port is assigned to the data output port P13 it is likely that data transmissions are started unexpectedly according to the changes in the state of P14 5 Starting receive operation Set SIIREC to 1 Once SIIREC is set to 1 do not attempt to write data to the SCONI register until the SIIEND flag is set Detect the falling edge of receive data 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing Note Make sure that the following conditions are met when performing continuous reception processing with 5101 in mode I UART The number of stop bits is set to 2 or greater e Clearing of SUEND during interrupt processing terminates before the next start arrives 3 19 43 Bus master mode mode 2 1 Setting the clock e Setup SBRI 2 Setting the mode follows 51 0 0 SIIMI 1 SIIDIR SIIIE 1 5
102. N TILRUN TILONG TIPWM TIHCMP TILCMP TILIE e mus mz mu ruo Lem ewoxe x rm rms rms Note 1 The output of the TIPWML is fixed at the high level if the TIL is stopped If the TIL is running the output of the TIPWML is fixed at the low level when TILR FFH The output of TIPWMH is fixed at the high level if the T1H is stopped If the T1H is running the output of the TIPWMH is fixed at the low level when TIHR FFH 3 49 3 14 3 Circuit Configuration 3 14 31 Timer 1 control register 8 bit register 1 This register controls the operation and interrupts of the TIL and 3 14 3 2 Timer 1 prescaler control register T1PRR 8 bit counter 1 This register sets the clocks for TIL and 3 14 3 3 Timer 1 prescaler low byte 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock Varies with operating mode T1LONG T1PWM T1L Prescaler Count Clock 2 Tcyc events Note 1 Tcyc Note 2 2 Tcyc events Note 1 Teye Note 2 Note 1 TIL serves as an event counter when INT4 or INTS is specified as the timer 1 count clock input in the external interrupt 4 5 pin select register I45SL It serves as a timer that runs using 2 Tcyc as its count clock if neither INT4 no
103. Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FED4 0000 0000 R W RBUF RBUF7 RBUF6 5 RBUF4 RBUF3 RBUF2 RBUFI RBUFO 3 103 UART1 3 21 5 UART1 Continuous Communication Processing Examples 3 21 5 4 Continuous 8 bit data receive mode first received data 55H Start bit Next start bit Beginning Receive data LSB first End of of receive 7 T sz 9 2 3 4 5 Scar 1 2 3 Figure 3 21 3 Example of Continuous 8 bit Data Receive Mode Processing Setting the clock Setthe transfer rate UBR Setting the data length e Clear UCONI 8 9BIT and 8 7BIT Configuring the UARTI for receive processing and setting up the receive port and interrupts Setup the receive control register UCONO 41H Set P33DDR P3DDR bit 3 to 0 and P33 P3 bit 3 to 0 Starting a receive operation UCONO RECRUN is set when a falling edge of the signal at the receive port P33 is detected End of a receive operation When the receive operation ends UCONO RECRUN is automatically cleared and UCONO RECEND is set The UARTI then waits for the start bit of the next receive data Receive interrupt processing e Read the receive data RBUF Clear UCONO RECEND and STPERR and exit the interrupt routine When changing the data length and baudrate for the next receive operation do so before the start bit falling edge of the signal is detected at the receive port P33 Next receive dat
104. O FE20 0000 HHHH PWMOL PWMOL3 PWMOL2 PWMOL1 PWMOLO PWMOL1 PWMOLO FE20 bits 5 amp 4 ENPWMO PWMOL3 PWMOL2 FE24 bit 2 FE20 bit 7 FE20 bit 6 Output HI Z 3 120 LC875W00 Chapter 3 3 23 43 PWMO compare register PWMOH 8 bit register 1 Thisregister controls the fundamental wave pulse width of PWMO Fundamental wave pulse width Value represented by PWMOH7 to PWMOHO 1 2 When bits 7 to 4 of PWMOL are all fixed at 0 PVMO be used as period programmable 8 bit PWM that is controlled by PWMOH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE21 0000 0000 PWMOH PWMO0OH7 PWMOH6 PWMOH5 PWMOH3 2 PWMOH 1 PWMOHO 3 23 44 PWM l compare register L PWM1L 4 bit register 1 This register controls the additional pulses of PWMI 2 PWMIL is assigned bits 7 to 4 and all of its low order 4 bits are set to 1 when read 3 When the PWMI control bit PWMOC FE24 bit 3 is set to 0 the output of PWMI ternary can be controlled using bits 7 to 4 of PWMIL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE22 0000 HHHH PWMIL PWMIL3 PWMIL2 PWMILI PWMILO ENPWM1 PWM1L3 PWM1L2 FE24 bit 3 FE22 bit 7 FE22 bit 6 FE22 bits 5 amp 4 3 23 4 5 PWM1 compare register PWM1H 8 bit register 1 regi
105. ONI TEPTY cannot be cleared in this case the UART stops processing after completing that transmit operation 2 HALT mode can be released using the UARTI transmit interrupt 3 106 LC875W00 Chapter 3 22 Asynchronous Serial Interface 2 UART2 3 221 Overview This series of microcontrollers incorporates an asynchronous serial interface 2 UART2 that has the following characteristics and features 1 Data length 7 8 9 bits LSB first 2 Stop bits 1 bit 2 bits in continuous transmission mode 3 Parity bits None 4 Transfer rate 2 to NS Tcyc or to Ll Tcyc 5 Full duplex communication The independent transmitter and receiver blocks allow both transmit and receive operations to be performed at the same time Both transmitter and receiver blocks adopt a double buffer configuration so that data can be transmitted and received continuously 3 22 2 Functions 1 Asynchronous serial UART2 Performs full duplex asynchronous serial communication using a data length of 7 8 or 9 bits with 1 stop bit The transfer rate of the UART2 is programmable within the range of e to 208 64 8192 3 to 73 2 Continuous data transmission reception Performs continuous transmission of serial data whose data length and transfer rate are fixed the data length and transfer rate that are identified at the beginning of transmission are used The number of stop bits used in the continuous tra
106. OO 3 18 4 4 Continuous data bit register SCTRO 1 This register is used to specify the bit length of serial data to be transmitted received through SIOO in continuous data transmission reception mode 2 valid value range is from 00 to FF H 3 When continuous data transmission reception is started with this register set to OO H 1 bit of data transmission reception is carried out after the contents of data RAM are transferred to SBUFO after the contents of RAM and SBUFO are exchanged when SIOWRT 1 Number of bits transferred SCTRO value 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE33 0000 0000 R W SCTRO SCTRO7 SCTRO6 SCTROS 5 04 SCTRO3 SCTRO2 SCTRO1 SCTROO 3 18 4 5 Continuous data transfer control register SWCONO 1 This register is used to suspend or resume the operation of SIOO in byte units in continuous data transmission reception mode and to read the number of transferred bytes bits 4 to 0 are read only Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE37 0000 0000 R W SWCONO SOWSTP SWCONB6SWCONBS SOXBYTA SOXBYT3 SOXBYT2 SOXBYTI1 SOXBYTO SOWSTP bit 7 When this bit is set to 1 SIOO stops operation after completing the transfer of 1 byte data in continuous transfer mode 1 byte of serial data separated at the beginning of serial transfer Serial transfer resumes when this bit is subsequently set to 0
107. Overall period iTcyc programmable in iTcyc increments 5 Interrupt generation Interrupt requests are generated at the intervals equal to the overall PWM period if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control to control and PWMS PWM4L PWM4H PWMSL PWMAC P3DDR P3 Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE72 0000 HHHH R W PWM4L PWM4L3 PWM4L2 PWM4L1 PWM4L0 RW PWMSL PWMSLO PWMSL BWMOLD m epe eec melde er 3 126 3 24 3 3 24 3 1 1 3 24 3 2 1 2 3 24 3 3 1 2 3 24 3 4 1 2 3 24 3 5 1 2 LC875W00 Chapter 3 Circuit Configuration PWM4 PWM5 control register PWM4C 8 bit register This register controls the operation and interrupts of PWM4 PWMS PWM4 compare register L PWMAL 4 bit register This register controls the additional pulses of PWMA PWMAL is assigned bits 7 to 4 and all of its low order 4 bits are set to 1 when read PWM4 compare register PWM4H 8 bit register This register controls the fundamental wave pulse width of PWMA When bits 7 to 4 of PWMAL are all fixed at 0 PWMA can be used as period programmable 8 bit PWM that is controlled by PWM4H 5 compare register L PWM5L 4 bit register This register controls the additional pulses of PWMS PWMSL is assigned bits 7 to 4
108. PBDDR 1 This register is 8 bit register that controls the I O direction of port B data in 1 bit units Port PBn is placed in output mode when the bit PBnDDR is set to 1 and in input mode when the bit PBnDDR is set to 0 2 Port PBn is configured as an input pin with a pull up resistor when the bit PBnDDR is set to 0 and port B data latch bit PBn is set to 1 3 26 LC875W00 Chapter Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE6D 0000 0000 R W PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PBIDDR PBODDR Register Data Port PBn State Internal Pull up EL PBnDDR input 7 Resistor Enabled Open Enabled High open CMOS N channel open drain 3 8 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 8 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port B retains the state that is established when HALT or HOLD mode is entered 3 27 Port C 3 9 Port C 3 9 1 Overview Port C is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data control latch and a control circuit The direction of the signals can be specified in 1 bit units As a user option either CMOS output or N channel open drain output can be specified as the output type in 1 bit units 3 9 2 Functions 1 Input output port
109. PH at address It is initialized to 0000H when a reset is performed The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEOA 0000 0000 R W SPL SP7 SP6 SP5 SP4 SP3 SP2 5 1 5 0 The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP SP SP 1 ROMBANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off which use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes These addressing modes use 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses be used as ordinary RAM in 1 byte 9 bits units if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 RAM Reserved for system
110. PWM compare register L PWML 12 bit register structure PWMH PWML XXXX XXXX XXXX 12 bits How pulses are added to the fundamental wave periods Example 1 PWM compare register H PWMH 00 H e PWM compare register L PWML 0OtoF H M Overall 3 1 4 a Fundamental Fundamental Fundamental Fundamental Fundamental Fundamental wave period wave period 1 wave period 2 wave period 13 wave period 14 wave period 15 0 111 21 3141516171 91101 11112 1 13114115 Fundamental period signal PWMH PWML 000 PWMH PWML 001 PWMH PWML 002 PWMH PWML 003 PWMH PWML 004 PWMH PWML 005 PWMH PWML 006 PWMH PWML 007 PWMH PWML 008 PWMH PWML 009 PWMH PWML 00A PWMH PWML 00B PWMH PWML 00C PWMH PWML 00D PWMH PWML 00E edi e cde TEE PWMH n H H H Hn hn H H h Hh H nH H R PWML 00F 3 131 PWM45 How pulses are added to fundamental wave periods PWM compare register H PWMH PWM compare register L PWML 01 H OtoF gt Fundamental Fundamental Fundamental Fundamental Fundamental Fundamental wave period 0 wave period 1 wave period2 wave period 13 wave period 14 wave period 15 Fundamental period ep qoa qo
111. S lt lt L RB oL o 40 Q sw bits 3 0 D CMOS Q or Pin C Nch OD O 5 lt lt L Lf PO interrupt detect 5 2 1010 PODDR FE41 Int request to vector 0004B PO FE40 bit 7 P07 pin input data um PO FE40 bit 6 PO6 pin input data 40 bit 5 P05 pin input data 40 bit 4 P04 pin input data PODDR FE41 bit 1 40 bit 3 P03 pin input data PO interrupt detect 40 bit 2 Pull up resistor is P02 pin input data Not attached if N channel OD option is selected 40 bit 1 B Programmable if CMOS option is selected P01 pin input data PO FEsO p PODDR FE41 bito P05 Clock output system subclock selectable Port 0 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 1 Port Block Diagrams Function outputs 7 6 P1FCR FE46 bits 7 6 pgp ae W P1FCR C 2 4 R P1FCR SW d 221 9 FE44 CMOS 0 Dek Pi W P1 Nch OD XOR 17 16 5 L 1 P1DDR 45 bits 7 6 D Q W P1DDR P16 None Timer 1LPWM output R P1DDR SIO1 data input SIO1 data output SIO1 data output 5100 clock input 5100 clock output SIOO data input SIOO data output Pio None SIOO data output Function outputs 5 0 P1FCR FE46 bits 5 0 b W P1FCR T
112. SiGe Peg deg oy tee age Ed signal PWMH PWML 010 PWMH 011 PWML 012 PWMH PWML 013 PWMH PWML 014 PWMH PWML 015 PWMH PWML 016 PWMH PWML 017 PWMH PWML 018 PWMH PWML 019 PWMH PWML 01A PWMH PWML 01B PWMH PWML 01C PWMH PWML 01D PWM qno peso E E ES PEE s z g PWML 01F The fundamental wave period is variable within the range of 4619256 Fundamental wave period Value represented by PWMOC7 to PWMOCA 1 x 16 The overall period can be changed by changing the fundamental wave period The overall period is made up of 16 fundamental wave periods 3 132 LC875W00 Chapter 3 Examples Wave comparison when the 12 bit PWM contains 237 H 12 bit register configuration gt PWMH PWML 237 H 1 Pulse added system this series Overall period PWML 237 2 Ordinary system Since the ripple component of the integral output in this system is greater than that of the pulse added system as seen from the figure below the pulse added system is considered better for motor controlling uses Overall period e e PWMH PWML 237 Ripple 3 133 ADC 3 25 3 25 1 8 bit AD Converter ADC Overview This series of microcontrollers incorporates an 8 bit resolution AD converter that has
113. Special Function Register SFR Map Appendix ll Port 0 Block Diagram Port 1 Block Diagram Port 2 Block Diagram Port 3 Block Diagram Port 7 Block Diagram Port 8 Block Diagram Port A Block Diagram Port B Block Diagram e Port C Block Diagram Port E Port F Block Diagram Port SI2P SIO2 Block Diagram Port PWM1 PWM2 Block Diagram LC875W00 APPENDIX I Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 0 FFF XXXX R W RAM4KB 9 bits long HER MES ES Fear sts mien 0000 0000 RW me eR pene PIS e a 2541 24 ium SSS ife rms mue 1 reos 000 9 www Fe x Dl 0000 woo Ra s Wu wis 0000 0000 ww i ime ims 0000 0000 RW 9X 5 sw se se s Le m o we p m Dom gt Fo ew L Lee an aov FEE 0000 X00 R
114. T2 pin and bit 2 reads 0 2 When this bit is set to 0 the and XT2 pins serve as input pins When the OCR register is read in this case bit 3 reads the data at the XT2 pin and bit 2 reads the data at the XT1 pin 5 bit 5 System clock select CLKCBA bit 4 System clock select 1 CLKCBS and CLKCBA are used to select the system clock 2 5 and CLKCBA are cleared at reset time or when HOLD mode is entered CLKCB5 CLKCB4 System Clock Internal RC oscillator 0 0 XT2IN bit 3 XT2 data read only XTAIN bit 2 XT1 data read only 1 Data that can be read via XTIIN varies as summarized below according to the value of EXTOSC bit 6 EXTOSC XT2IN XT1IN 0 XT2 pin data pin data RCSTOP bit 1 Internal RC oscillator control 1 Setting this bit to 1 stops the oscillation of the internal RC oscillator 2 Setting this bit to 0 starts the oscillation of the internal RC oscillator 3 When a reset occurs this bit is cleared and the internal RC oscillator is enabled for oscillation 4 This bit is cleared when the microcontroller enters HOLD mode internal RC oscillator is stopped Immediately after the microcontroller exits HOLD mode the internal RC oscillator is activated and designated as the system clock source 5 state of this bit remains unchanged when the microcontroller enters X tal HOLD mode internal RC oscillator is stopped The state
115. T8 BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE34 0000 0000 SCONI SIIMI SIIMO SIIRUN SIIREC SIIDIR 5 SIIIE SBUFI7 SBUFIO SBRGIO 3 19 3 4 2 Circuit Configuration 5101 control register SCON1 8 bit register This register controls the operation and interrupts of SIOI 5101 shift register SIOSF1 8 bit shift register This register is a shift register used to transfer and receive SIO1 data This register cannot be accessed with an instruction It is accessed via SBUFI SIO1 buffer 1 SBUF1 9 bit register The low order 8 bits of SBUFI are transferred to SIOSF1 at the beginning of data transfer At the end of data transfer the contents of SIOSFI are placed in the low order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUFI it is possible to check for a stop bit 5101 baudrate generator SBR1 8 bit reload counter This is a reload counter for generating internal clocks The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 81 SIO1 Table 3 19 1 5101 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transfer Receive Transfer Receive Transfer Receive Transfer Receive SI1REC 0 SHREC 1 SI1REC 0 SHREC 1 SI1REC 0 SHREC 1 SHMREC 0 SHREC 1 None None Output Input See 1 and 2 Not required Not required See 2 below Low Low below Data o
116. TOLCP bit 6 Timer OL capture signal input port select These 2 bits have nothing to do with the control function of the base timer bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 DE 1 9 Sh SSCS BUZON bit 3 Buzzer output select This bit enables the buzzer output tBST 16 When this bit is set to 1 a signal that is obtained by dividing the base timer clock by 16 is sent to port P17 as the buzzer output When this bit is set to 0 the buzzer output is fixed at a high level NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select STOIN bit 0 Timer 0 count clock input port select These 3 bits have nothing to do with the control function of the base timer 3 70 LC875W00 Chapter 3 3 18 Serial Interface 0 5100 3 18 1 Overview The serial interface 0 SIOO incorporated in this series of microcontrollers has the following two major functions 1 Synchronous 8 bit serial I O 2 or 3 wire system 3 to 212 transfer clock 2 Continuous data transmission reception transfer of data whose length varies between 1 and 256 bits in 1 bit units 4 to 212 transfer clock 3 18 2 Functions 1 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock
117. TOLEXT TOHIE TOLCMP TOLIE Frei m mus ms mu mu Cres 00000000 r rur rene rona rons mw Crue mes ments Tocata meno oooxx 5 rocana rocana rocana Tecan e rocan rocas rocana roca froca reir e rocam roca i canne rocas rocx ma rocas TOCA THO 3 12 3 Circuit Configuration 3 12 3 1 Timer counter 0 control register TOCNT 8 bit register 1 This register controls the operation and interrupts of TOL and 3 12 3 2 Programmable prescaler match register TOPRR 8 bit register 1 This register stores the match data for the programmable prescaler 3 12 3 3 Programmable prescaler 8 bit counter 1 Start stop This register runs in modes other than HOLD mode 2 Countclock Cycle clock period 1 3 Match signal A match signal is generated when the count value matches the value of register TOPRR period 1 to 256 Tcyc 4 Reset The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR 3 12 3 4 Timer counter 0 low byte TOL 8 bit counter 1 Start stop This
118. XT1 Dedicated oscillator ports 2 CF2 Reset pins 1 RES e Power pins 8 VSS1 to VSS4 VDD1 to VDD4 1 1 Timers Timer 0 16 bit timer counter with capture registers Mode 0 Mode 1 Mode 2 Mode 3 8 bit timer with an 8 bit programmable prescaler with two 8 bit capture registers x 2 channels 8 bit timer with an 8 bit programmable prescaler with two 8 bit capture registers 8 bit counter with two 8 bit capture registers 16 bit timer with an 8 bit programmable prescaler with two 16 bit capture registers 16 bit counter with two 16 bit capture registers Timer 1 16 bit timer counter that supports PWM toggle output Mode 0 Mode 1 Mode 2 Mode 3 8 bit timer with an 8 bit prescaler with toggle output 8 bit timer counter with toggle output 8 bit PWM with an 8 bit prescaler x 2 channels 16 bit timer counter with an 8 bit prescaler with toggle output toggle output also possible from the low order 8 bits 16 bit timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as PWM Timer 4 8 bit timer with a 6 bit prescaler Timer 5 8 bit timer with a 6 bit prescaler Timer 6 8 bit timer with a 6 bit prescaler with toggle output Timer 7 8 bit timer with a 6 bit prescaler with toggle output Base timer 1 clock can be selected from among a subclock 32 768 kHz crystal oscillator system clock and timer 0 prescaler output
119. Z INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port 3 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4C H000 0000 R W P3 P36 P35 P34 P33 P32 P31 P30 3 4 3 2 Port 3 data direction register P3DDR 1 This register is 7 bit register that controls the I O direction of the port 3 data 1 bit units Port P3n is placed in output mode when the bit P3nDDR is set to 1 and in input mode when bit P3nDDR is set to 0 2 When the bit P3nDDR is set to 0 and bit P3n of the port 3 data latch is set to 1 port P3n becomes an input with a pull up resistor Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4D 000 0000 R W P3DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 Register Data Port P3n State Internal Pull up Resistor Enabled Open OFF Enabled Internal pull up resistor 0 Enabled High open CMOS N channel open drain 3 4 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 4 5 HALT and Hold Mode Operation When in HALT or HOLD mode port 3 retains the state that is established when HALT or HOLD mode is entered 3 5 3 5 1 LC875W00 Chapter Port 7 Over
120. a processing Repeat steps 2 3 and 4 above To end a continuous receive operation clear UCONO STRDET during a receive operation and this receive operation will be the last receive operation that the UARTI executes 3 104 LC875W00 Chapter 3 21 5 2 Continuous 8 bit data transmit mode first transmit data 55H Stop bit MM Next start bit Beginning of Start bit Transmit data LSB first Beginning of transmit ae M Y i 4 TE P32 output i End of transmit TUBR1 1 lt 1 As 1 gt 3 i 5 1 1 1 2 7 4 Figure 3 21 4 Example of Continuous 8 bit Data Transmit Mode Processing 1 Setting the clock Setthe transfer rate UBR Setting up transmit data Load the transmit data 55H Setting the data length transmit port and interrupts Setup the transmit control register UCONI 31H Set P32DDR P3DDR bit 2 to 0 and P32 P3 bit 2 to 0 2 Starting a transmit operation Set UCON1 TRUN 3 Transmit interrupt processing Load the next transmit data TBUF xxH Clear UCONI TEPTY and exit the interrupt routine 4 End of a transmit operation When the transmit operation ends UCONI TRUN is automatically cleared and automatically set in the same cycle Tcyc continuous data transmt mode only this processing takes 1 Tcyc of time The UARTI then starts transmission of the next transmit data 5 Next transmit data processing Repeat steps 3 and 4 above To e
121. able of Port 1 Multiplexed Pin Functions C 2 m R P1FCR d P1 FE44 bits 5 0 D 8 W P1 Q E OR P15 P10 5 L R P1 P1DDR FE45 bits 5 0 D Q W P1DDR C R P1DDR Port 1 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units 2 LC875W00 APPENDIX II W P2 P27 P20 R P2 W P2DDR R P2DDR P27 P26 P25 E P24 Timer 1 count clock Timer OL capture signal Timer OH capture signal Int request to vector 00013 Int request to vector 0001B I45SEL FE4B FE P D d E P21 E TT L P20 sy TJT L Timer 1 count clock Timer OL capture signal Timer OH capture signal AII 3 Port Block Diagrams Timer OH capture 1 signal Int request to vector 00023 Int request to vector 0002B Timer OL capture 1 signal Port 2 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units 4 LC875W00_ APPENDIX II Function outputs 0 1 P3 FE4C W P3 P31 P30 W P3DDR o 2 a Function outputs 2 4 CMOS W P3 rates Pin P34 P32 R P3 P3DDR FE4D D W P3DDR 3 C R P3DDR 5 Port Block Diagrams P3 FE4C W P3 P36 P35 P33 R P3 Special inputs 3 5 W P3DDR R P3DDR P UART2 data input UART data output Table of Port 3 Multiplexed Pin Functions Port 3 Block Diagram Option Output type CMOS o
122. al oscillator will not start Feedback resistor between and XT2 is turned off 2 1 CF oscillator inverter input Feedback resistor present between CF1 and CF2 2 CF oscillator inverter output Oscillation enabled POO to P07 e Input mode e Pull up resistor off P10 to P17 e Input mode e Pull up resistor off P20 to P27 Input mode Pull up resistor off P30 to P36 Input mode Pull up resistor off XT Input X tal oscillator will not start Feedback resistor between and XT2 is turned off C C F Controlled by register OCR FEOEH as oscillator input XT1 data can be read through register OCR FEOEH 0 is always read in oscillation mode Feedback resistor between XT1 and XT2 is controlled by a program Controlled by register OCR as X tal oscillator output XT2 data can be read through register FEOEH Input output controlled by a program Feedback resistor between and XT2 is controlled by a program CF oscillator inverter input Enabled disabled by register OCR FEOEH Feedback resistor present between CF1 and CF2 CF oscillator inverter output Enabled disabled by register OCR FEOEH Always set to VDD level regardless of state when oscillation is suspended Input output pull up resistor is controlled by a program Input output pull up resistor is controlle
123. aler Count 0 us 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 3 14 4 3 Timer 1 low byte T1L 1 This is a read only 8 bit timer It counts up on every prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIA 0000 0000 R TIL TIL6 TILS TIL3 TIL2 TILO 3 14 4 4 Timer 1 high byte T1H 1 Thisis a read only 8 bit timer It counts up on every prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIB 0000 0000 R T1H6 5 4 2 T1HO 3 14 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte 2 Match buffer register is updated as follows e When it is inactive TILRUN 0 the match register matches TILR When it is active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRO 3 14 4 6 Timer 1 match data register high byte T1HR 1 This register is used to store the match data for It has an 8 bit match buffer registe
124. all gt PWMH PWML 237 Ripple 3 125 PWM45 3 24 PWM4 PWM5 3 24 4 Overview This series of microcontrollers incorporates two 12 bit PWMs named PWM4 and PWMS Each PWM is made up of a PWM generator circuit that generates variable frequency 8 bit fundamental wave PWM and a 4 bit additional pulse generator 3 24 2 Functions 1 PWM4 Fundamental wave PWM mode register PWM4L 0 Fundamental wave period Tcyc programmable in 16 increments common to 5 e High level pulse width 0 to Fundamental wave period 1 3 programmable in 1 increments 2 4 Fundamental wave Additional pulse PWM mode Fundamental wave period 1910250 Tcyc programmable in E Tcyc increments common to PWM5 Overall period Fundamental wave period x 16 e High level pulse width 0 to Overall period iTcyc programmable in iTcyc increments 3 PWMS Fundamental wave PWM mode register PWMSL 0 Fundamental wave period programmable in 16 increments common to PWM4 e High level pulse width 0 to Fundamental wave period 1 programmable in 1 increments 4 PWMS5 Fundamental wave Additional pulse PWM mode Fundamental wave period Qon Tcyc programmable in 16 increments common to PWM4 Overall period Fundamental wave period x 16 e High level pulse width 0 to
125. ame BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEEC 0000 0000 R W RBUF2 R2BUF7 R2BUF6 R2BUF5 R2BUF4 R2BUF3 R2BUF2 R2BUFI R2BUFO 3 114 LC875W00 Chapter 3 22 5 UART2 Continuous Communication Processing Examples 3 22 5 1 Continuous 8 bit data receive mode first received data 55H Start bit Next start bit Beginning Receive data LSB first End of of receive receive v lt gt v P35 input 1 i mem d 1 gt Stop bit 1 lt 4 5 gt N 95 Figure 3 22 3 Example of Continuous 8 bit Data Receive Mode Processing 1 Setting the clock Setthe transfer rate UBR2 Setting the data length Clear UCON3 8 9BIT2 and 8 7BIT2 Configuring the for receive processing and setting up the receive port and interrupts Setup the receive control register UCON2 41H Set P35DDR P3DDR bit 5 to 0 and P35 P3 bit 5 to 0 2 Starting a receive operation e UCON2 RECRUN2 is set when a falling edge of the signal at the receive port P35 is detected 3 Endofareceive operation e When the receive operation ends UCON2 RECRUN2 is automatically cleared and UCON2 is set The UART2 then waits for the start bit of the next receive data 4 Receive interrupt processing Read the receive data RBUF2 e Clear UCON2 RECEND2 and STPERR2 and exit the interrupt routine When changing the data length and baudrate for the next receive operation do so before
126. an 8 bit register that controls the transmit operation data length and interrupts for the UART2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEE9 0000 0000 UCON3 TRUN2 8 9 2 TDDR2 TCMOS2 8 7BIT2 TBIT82 2 TRNSIE2 TRUN2 bit 7 UART2 transmit control 1 When this bit is set to 1 the UART2 starts a transmit operation 2 This bit is automatically cleared at the end of the transmit operation If this bit is cleared during the transmit operation the UART2 is disabled in the middle of the operation n continuous transmit mode this bit is cleared at the end of a transmit operation but is automatically set within the same cycle Tcyc Consequently transmit operations occur with intervening 1 Tcyc delays In the continuous transmit mode TRUN2 will not be set automatically if a bit manipulation instruction NOTI CLR1 SET1 is executed to UCON3 register in the same cycle in which TRUN2 is to be automatically cleared 8 9 BIT2 bit 6 UART2 transfer data length control 1 This bit and 8 7 BIT2 bit 3 are used to control the transfer data length of the UART2 8 9 BIT2 8 7 BIT2 Data Length in bits 1 0 9 UART2 will not run normally if the data length is changed in the middle of a transfer operation Be sure to manipulate this bit after confirming completion of a transfer operation The same data length is used wh
127. and WDTRUN are reset and the watchdog timer is stopped in the HALT or HOLD state When this bit is set to 0 WDTCLR WDTRST and WDTRUN remain unchanged and the watchdog timer continues operation even when the microcontroller enters the HALT or HOLD state WDTCLR bit 2 Watchdog timer clear control This bit enables 1 or disables 0 the discharge of capacitance from the external capacitor Setting the bit to 1 turns on the N channel transistor of the P70 INTO TOLCP pin discharging the external capacitors and clearing the watchdog timer The pulse stretcher circuit functions during this process Setting the bit to 0 disables to turn on the N channel transistor of the P70 INTO TOLCP pin and to clear the watchdog timer WDTRST bit 1 Runaway time reset control This bit enables 1 or disables 0 the reset sequence that is to be executed when the watchdog timer detects a program runaway When this bit set to 1 a reset is generated and execution restarts at program address 0000H when a program runaway is detected When the bit is set to 0 no reset occurs Instead an external interrupt INTO is generated and a call is made to vector address 0003H WDTRUN bit 0 Watchdog timer operation control This bit starts 1 or maintains 0 the state of the watchdog timer A 1 in this bit starts the watchdog timer function and a 0 exerts no influence on the operation of the watchdog timer This means that once the watchdog timer is started a program will no
128. and all of its low order 4 bits are set to 1 when read 5 compare register PWM5H 8 bit register This register controls the fundamental wave pulse width of PWMS When bits 7 to 4 of PWMSL are all fixed at 0 PWMS can be used as period programmable 8 bit PWM that is controlled by PWM5H 3 127 PWM45 3 24 4 Related Registers 3 2441 PWM4 PWM5 control register PWMAC 8 bit register 1 This register controls the operation and interrupts of PWM4 PWMS Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE76 0000 0000 R W PWM4C PWM4C7 PWM4C6 5 PWM4C4 ENPWMS ENPWM4 PWM40V PWM4IE PWM4C7 to PWM4C4 bits 7 to 4 PWM4 PWM5 period control e Fundamental wave period Value represented by PWM4C7 to PWMACA 1 x 15 Overall period Fundamental wave period x 16 ENPWM5 bit 3 PWM5 operation control When this bit is set to 1 the PWMS is activated When this bit is set to 0 the PWMS is deactivated ENPWM4 bit 2 PWM4 operation control When this bit is set to 1 the PWMA is activated When this bit is set to 0 the PWMA is deactivated bit 1 PWM4 PWM5 overflow flag This bit is set at the interval equal to the overall period of PWM This flag must be cleared with an instruction PWMAIE bit 0 PWM4 PWM5 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit a
129. are used The number of stop bits used in the continuous transmission mode is 2 see Figure 3 21 4 Performs continuous reception of serial data whose data length and transfer rate vary on each receive operation The transfer rate of the UARTI is programmable within the range of 8 to 208 64 8192 3 to 73 The transmit data is read from the transmit data register TBUF and the receive data is stored in the receive data register RBUF 3 Interrupt generation Interrupt requests are generated at the beginning of transmit operation and at the end receive operation if the interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control the asynchronous serial interface 1 UARTI e UCONO UCONI RBUF P3 PSDDR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDO 0000 0000 R W UCONO UBRSEL STRDET RECRUN STPERR U0B3 RBIT8 RECEND UCONI UBRGO UBRGO 3 06 LC875W00 Chapter Circuit Configuration UART1 control register 0 UCONO 8 bit register This register controls the receive operation and interrupts for the UART1 UART1 control register 1 UCON1 8 bit register This register controls the transmit operation data length and interrupts for the UARTI UART1 baudrate generator UBR 8 bit reload counter The UART1 baudrate generator is a rel
130. as the count clock The buzzer output can be controlled using the input signal select register ISL The buzzer output is ANDed with the timer 1 PWMH output and can be transmitted via pin P17 Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set The base timer can generate two types of interrupt requests base timer interrupt 0 and base timer interrupt 1 HOLD mode operation and HOLD mode release The base timer is enabled for operation in HOLD mode when bit 2 of the power control register PCON is set HOLD mode can be released by an interrupt from the base timer This function allows the microcontroller to perform low current intermittent operations 3 67 7 Itis necessary to manipulate the following special function registers to control the base timer BTCR ISL PIDDR P1 PIFCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTCII BTCIO BTIF1 BTIFO BTIEO 3 17 3 Circuit Configuration 3 17 3 1 8 bit binary up counter 1 This counter is an up counter that receives as its input the signal selected by the input signal select register ISL It generates a 2kHz buzzer output and base timer interrupt 1 flag set signals The overflow from this counter functions as the clock for the 6 bit binary counter 3 1
131. at all or to disable the watchdog timer from running in HOLD mode by setting WDTHLT to 1 Be sure to set WDTCLR to 0 when the watchdog timer is not to be used The P70 INTO TOLCP pin has two input levels The threshold level of the input pins of the watchdog timer circuit is higher than that of the port inputs and the interrupt detection level Refer to the latest SANYO Semiconductor Data Sheet for the input levels High threshold o gt Watchdog timer Port 7 circuit interrupt MOV 3 55H WDT Instruction P70 INTO TOLCP Fig 4 5 2 Pin Pull up Resistor OFF 4 25 Watchdog Timer 3 The external resistor to be connected to the watchdog timer can be omitted by setting bits 4 and 0 of the port 7 control register P7 5 to 0 1 and connecting a pull up resistor to the P70 INTO TOLCP pin see Figure 4 5 3 The resistance of the pull up resistor to be adopted in this case varies according to the power source voltage VDD Calculate the time constant of the watchdog timer while referring to the latest SANYO Semiconductor Data Sheet R 5 I HALT HOLD P70DT FESC bit 0 gt o Watchdog timer Port 7 circuit interrupt MOV 55H WDT Instruction P70 INTO TOLCP P70DDR FESC bit 4 P70DT FESC bit 0 Fig 4 5 3 Sample Application Circuit with a Pull up Resistor 4 26 Appendixes Table of Contents Appendix l
132. be identified by monitoring ADCRI An interrupt request to vector address 0043H is generated by setting ADCRO DACRS is automatically cleared before the microcontroller enters HALT or HOLD mode In HALT or HOLD mode neither current flows into the ladder resistance network nor reference voltage is generated When the microcontroller enters reset HALT or HOLD mode while AD conversion is in progress ADCR3 is automatically reset stopping the conversion function and DACRS is reset so that no current will flow into the ladder resistor network The results of conversion in such a case are undefined Make sure that only input voltages that fall within the specified range are supplied to pins P80 ANO to P87 AN7 P70 AN8 P71 AN9 XTI ANIO XT2 AN11 PA3 AN12 PA4 AN13 and PAS AN 14 Application of a voltage higher than VDD or lower than VSS to an input pin may exert adverse influences on the converted value of the channel in question or other channels To prevent reduction in conversion accuracy due to noise interferences add an external capacitor of 1000 pF or so to each analog input pin or perform conversion operations several times and take an average of their results If digital pulses are applied to pins adjacent to the analog input pin that is being subject to conversion or if the state of data at the adjacent pins is changed expected conversion results may not be obtained due to coupling noises caused by such actions Correct conversio
133. be turned on and off in 4 bit units HOLD release input Port 0 interrupt input Multiplexed pin functions P05 System clock output P06 Timer 6 toggle output P07 Timer 7 toggle output Portti 1 8 bit I O port Yes C to P17 I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P10 SIOO data output P11 SIOO data input bus I O P12 SIOO clock I O P13 5101 data output P14 SIOI data input bus I O P15 SIO1 clock I O P16 Timer 1 PWML output P17 Timer 1 PWMH output buzzer output Port 2 e 8 bit I O port Yes I O specifiable in 1 bit units P20 to P27 Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P20 INT4 input HOLD release input timerlevent input timer OL capture input timer OH capture input INT6 input timer OL capture input P21 to P23 INT4 input HOLD release input timerlevent input timer OL capture input timer OH capture input P24 5 input HOLD release input timer 1 event input timer OL capture input timer OH capture input INT7 input timer OH capture input P25 to P27 INT5 input HOLD release input timer 1 event input timer OL capture input timer OH capture input Interrupt acknowledge type Rising Rising Falling amp H level L level Falling INT4 x x 5 x x INT6 x x INT7 x x Continued
134. bit transfer 3 Read this bit and judge if the communication is performed normally at the end of the communication 4 This bit must be cleared with an instruction SIOEND bit 1 Serial transfer end flag 1 This bit is set at the end of serial transfer on the rising edge of the last clock involved in the transfer 2 This bit must be cleared with an instruction SIOIE bit 0 SIOO interrupt request generation enable control 1 When this bit and SIOEND are set to 1 an interrupt request to vector address 0033H is generated 3 75 5100 3 18 4 2 Serial buffer SBUFO 1 This register is an 8 bit shift register for 5100 serial transfer 2 Data to be transmitted received is written to and read from this shift register directly Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE31 0000 0000 R W SBUFO SBUFO7 SBUF06 SBUFOS SBUF04 SBUFO3 SBUFO2 SBUFOI SBUFOO 3 18 4 3 Baudrate generator register SBRO 1 Thisregister is an 8 bit register that defines the transfer rate of SIOO serial transfer 2 transfer rate is computed as follows TSBRO SBRO value 1 x 2 SBRO can take a value from 1 to 255 and the valid value range of TSBRO is from 3 to 22 The SBRO value of OO H is prohibited Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE32 0000 0000 R W SBRO SBRGO7 SBRG06 SBRGOS SBRG04 SBRGO3 SBRGO2 SBRGO1 SBRG
135. ble pull up resistor Bits PEO to PE7 are CMOS output port bits Initial Value BIT2 0000 0000 PE2 0000 0000 PEFCR PEDDR3 PESEL3 PEDDR2 PESEL2 PEDDRI PESELI PEDDRO PESELO 3 10 3 Related Registers 3 10 31 Port E data latch PE 1 The port E data latch is an 8 bit register for controlling port E output data and pull up resistors 2 When the latched data is 1 the corresponding pin is provided with a pull up register regardless of the I O state of the pin 3 When this register is read with an instruction data at pins PEO to PE7 is read in If the PE FE28 is manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 4 E data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE28 0000 0000 R W PE PE7 PE6 PES PE4 PE3 PE2 0 PEFCR Setting PEn State Programmable Pull up o om 3 10 3 2 Port E control register PEFCR 1 This register is an 8 bit register that controls the I O direction of the port E data in 2 bit units Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE29 0000 0000 R W PEFCR PEDDR3 PESEL3 PEDDR2 PESEL2 PEDDRI PESELI PEDDRO PESELO 3 30 PEDDRS bit 7 PE7 PE6 I O control A 1 or 0 in this bit controls the output CMOS or in
136. change that sets the interrupt flag is supplied to the port selected from P70 and P72 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle intervals for the duration of the input signal Timer 0H capture input function A timer OH capture signal is generated each time a signal change that sets the interrupt flag is supplied to the port selected from P71 and P73 When a selected level of signal is input to P71 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle intervals for the duration of the input signal 3 17 Port 7 6 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO or INT2 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When a signal change that sets the interrupt flag is input to P70 or P71 that is specified for level triggered interrupt in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set When a signal change that sets the interrupt flag is input to P72 in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag
137. clocks It can generate clocks at intervals of n 1 x 5 or n 1 x Tcyc n 1 to 255 Note n 0 is inhibited UART2 transmit data register TBUF2 8 bit register This register is an 8 bit register for storing the data to be transmitted UART2 transmit shift register TSFT2 11 bit shift register This register is used to send serial data via the UART2 This register cannot be accessed directly with an instruction It must be accessed through the transmit data register TBUF2 UART2 receive data register RBUF2 8 bit register This register is an 8 bit register for storing receive data UART2 receive shift register RSFT2 11 bit shift register This register is used to receive serial data via the UART2 This register cannot be accessed directly with an instruction It must be accessed through the receive data register RBUF2 3 108 LC875W00 Chapter 3 Data input LSB first Start bit Note The position of the start bit differs depending on the bit length M bit to be transferred 11 bit shift register RSFT2 Egger At end of receive operation RSFT2 gt RBUF2 RBUF2 FEECh a Data bit 8 9 bit data receive mode only Clock generator circuit Stop bit error flag Baudrate Falling edge detector P generator At beginning of circuit E AE receive zd UBR2 FEEAh UCON2 FEE8h p Interrupt request Note Bit 5 of PSDDR at FE4D must be set to 0 when the
138. controller returns from X tal HOLD mode the system clock to be used when X tal HOLD mode is entered needs to be set to either subclock or RC because no adequate oscillation stabilization time can be secured for the main clock Since X tal HOLD mode is used usually for low current clock counting less current will be consumed if the system clock is switched to the subclock and the main clock and RC oscillations are suspended before X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 PDN is cleared when a HOLD mode release signal INTO INT1 INT2 INT4 5 or POINT or a reset occurs IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into HALT mode 2 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 14 LC875W00 Chapter 4 Table 4 3 1 Standby Mode Operations Item Mode Reset State HALT Mode HOLD Mode X tal HOLD Mode Entry conditions RES applied PCON register PCON register PCON register Reset from watchdog Bit 1 0 Bit 2 0 Bit 2 1 umer Bit 0 1 Bit 1 1 Bit 1 1 Data changed Initialized as shown WDT bits 2 to 0 are WDT bits 2 to 0 are WDT bits 2 to 0 are cleared if WDT register cleared if WDT FEOF bit 4 is set register FEOF bit 4 PCON bit 0 turns to 1 is set register FEOE bit 0 turns to bits 5 4 1 and O are l cleared Main clock Running State
139. count clock control T7 Count Clock Timer 7 prescaler and timer counter are stopped in the reset state T6C1 bit 5 T6 count clock control T6CO bit 4 T6 count clock control T6 Count Clock Timer 6 prescaler and timer counter are stopped in the reset state T7OV bit 3 T7 overflow flag This flag is set at the interval of timer 7 period when timer 7 is running This flag must be cleared with an instruction T7IE bit 2 T7 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T7OV are set to 1 T6OV bit 1 T6 overflow flag This flag is set at the interval of timer 6 period when timer 6 is running This flag must be cleared with an instruction T6IE bit 0 T6 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T6OV are set to 1 3 16 4 2 Timer 6 period setting register T6R 1 Thisregister is an 8 bit register for defining the period of timer 6 Timer 6 period T6R value 1 x Timer 6 prescaler value 4 16 or 64 Tcyc 2 When data is written into T6R while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7A 0000 0000 R W T6R T6R7 T6R6 T6R5 T6R4 T6R3 T6R2 T6R1 T6RO 6 T7 3 16 4 3 Timer 7 period setting register T7R 1 This register is an 8 bit regi
140. counter is stopped and started by the 0 1 value of TOLRUN timer 0 control register bit 6 2 Countclock Either a prescaler match signal or an external signal must be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 3 Match signal match signal is generated when the count value matches the value of the match buffer register 16 bits of data must match in the 16 bit mode 4 Reset When the counter stops operation or a match signal is generated 3 12 3 5 Timer counter 0 high byte 8 bit counter 1 Start stop This counter is stopped and started by the 0 1 value of TOHRUN timer 0 control register bit 7 2 Countclock Either a prescaler match signal or a TOL match signal must be selected through the 0 1 value of TOLONG timer 0 control register bit 5 3 Match signal match signal is generated when the count value matches the value of the match buffer register 16 bits of data must match in the 16 bit mode 4 Reset When the counter stops operation or a match signal is generated 3 36 3 12 3 6 1 2 3 12 3 7 1 2 3 12 3 8 1 2 3 12 3 9 1 2 3 12 3 10 1 2 LC875W00 Chapter Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matc
141. crocontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highest order byte of the address and the contents 16 bits of either Rn Rn C or RO off as the low order bytes of the address Examples LDW 3456H Sets up the low order 16 bits STW R5 Loads the indirect register R5 with the low order 16 bits of the address MOV ZI2H B Sets up the high order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123456H to the accumulator Note This series of microcontrollers does not have the capability to access external memory 2 9 2 12 Wait Sequence 2 12 1 Wait Sequence Occurrence This series of microcontrollers performs wait sequences that suspend the execution of instructions in the following cases 1 2 2 12 2 1 2 3 4 5 When continuous data transfer is performed over 5100 with SIOCTR SCONO bit 4 set wait request is generated ahead of each transfer of 8 bit data in which case a 1 cycle of wait operation RAM data transfer is performed When transmission of data is performed with the SIO2 a wait request is generated ahead of each transfer of 8 bit data in which case a cycle of wait operation RAM data transfer is performed What is a Wait Sequence When a wait request occurs out of the factors expla
142. d by a program Input output pull up resistor is controlled by a program Input output pull up resistor is controlled by a program Oscillation suspended when used as oscillator input pin Oscillation state maintained in X tal HOLD mode Feedback resistor between and 2 is in state established at entry time Oscillation suspended when used as X tal oscillator input pin Always set to VDD level regardless of XT1 state Oscillation state maintained in X tal HOLD mode Feedback resistor between and 2 is in state established at entry time Oscillation suspended Feedback resistor present between and CF2 Oscillation suspended Always set to VDD level regardless of CF1 state Low level output preserved but high level output turned off Pull up resistor off HOLD mode established at entry time HOLD mode established at entry time Same as when reset Entry time state when X tal HOLD state is released Same as when reset Entry time state when X tal HOLD state is released Same as in normal Continued on next page Pin States and Operating Modes continued Pin Name Reset Time Normal Mode LC875W00 Chapter 4 On Exit from HALT Mode HOLD HOLD Mode P70 Input mode Pull up resistor off Input output pull up resistor controlled by a program N channel
143. dby Reset state entry conditions Low level applied to RES pin Reset signal generated by watchdog timer HOLD mode entry conditions PCON register FEO7 bit 2 set to 0 and bit 1 to 1 HOLD mode All oscillators stopped Since OCR register bits 0 1 4 and 5 are cleared the main clock and RC oscillator are started and RC oscillator is designated as system clock source when HOLD mode is released CPU and peripheral modules are stopped HOLD mode release conditions INTO or INT1 level interrupt request generated Request for INT2 INT4 INT5 or port 0 interrupt generated Resetting conditions established Note 1 e All modes e Reset Main clock stopped Subclock stopped RC oscillator started All registers initialized Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally 1 HALT mode All oscillators retain the state established when the HALT mode is entered CPU stopped Peripheral modules keep running Reset state cancellation conditions Lapse of predetermined time after resetting conditions are cancelled X tal HOLD mode entry conditions PCON register 07 bit 2 set to 1 and bit 1 to 1 e X tal HOLD mode Main clock and RC oscillator stopped Subclock retains the state established when X tal HOLD mode is entered Contents of OCR register remain unchanged CPU enters this mod
144. de 15 specified when the microcontroller enters HALT mode the UART2 will restart transmit processing after terminating a transmit operation Since UCON3 TEPTY2 cannot be cleared in this case the UART2 stops processing after completing that transmit operation 2 HALT mode can be released using the UART2 transmit interrupt 3 117 PWMO1 3 23 3 23 1 PWMO PWM1 Overview This series of microcontrollers incorporates two 12 bit PWMs named PWMO and PWMI Each PWM is made up of a PWM generator circuit that generates variable frequency 8 bit fundamental wave PWM and a 4 bit additional pulse generator PWMO and are provided with dedicated I O pins PVMO PWM I respectively 3 23 2 1 2 3 4 5 Address Functions Fundamental wave PWM mode register PWMOL 0 Fundamental wave period 1516159 Tcyc programmable 18 Tcyc increments common to PWM1 High level pulse width 0 to Fundamental wave period 1 programmable in 1 increments PWMO Fundamental wave Additional pulse PWM mode Fundamental wave period 1910259 Teye programmable in 18 increments common to PWM1 Overall period Fundamental wave period x 16 e High level pulse width 0 to Overall period 1 programmable in 1 increments PWMI Fundamental wave PWM mode register PWM1L 0 Fundamental wave period 16256 Teye programmable in 18 i
145. e at the XT2 pin Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE43 0000 0000 R W XT2PC XT2PCB7 XT2PCB6 2 5 XT2PCB4 XT2PCB3 2 2 XT2DR XT2DT XT2PCB7 to XT2PCB2 bits 7 to 2 General purpose flags These bits can be used as general purpose flag bits Any manipulation of these bits exerts no influence on the operation of this function block XT2DR bit 1 XT2 input output control XT2DT bit 0 XT2 output data Register Data Port XT2 State XT2DT XT2DR Input Output Enabled Open Enabled Open 0 0 eee co o a Note The XT2 general purpose output port function is disabled when EXTOSC OCR register FEOEH bit 6 is set to 1 To enable this port as a general purpose output port set EXTOSC to 0 System Clock 4 244 System clock divider control register CLKDIV 3 bit register 1 This register controls system clock divider Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 000 R W CLKDIV CLKDV2 CLKDVI CLKDVO Bits 7 to 3 These bits do not exist They are always read as 1 CLKDV2 bit 2 CLKDV1 bit 1 These bits set the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 4 12 LC875W00 Chapter 4 4 3 Standby Function 4 3 1 Overview This series of microcontrollers supports three standby modes called HALT HOLD and X
146. e after selecting subclock or RC oscillator clock as system clock and stopping main clock CPU and all peripheral modules except base timer stop operation Base timer retains the state established when X tal HOLD mode is entered When X tal HOLD mode is exited the oscillators return to the state established when the mode is entered X tal HOLD mode release conditions Base timer interrupt request generated INTO or INT1 level interrupt request generated Request for INT2 INT4 INT5 or Port 0 interrupt generated Resetting condition established Note 1 HALT mode release conditions Interrupt request accepted Note 2 Resetting conditions established Note 1 HALT mode entry conditions PCON register 07 bit 1 set to 0 and bit 0 to 1 Note 1 The CPU enters the reset state when the resetting conditions are established Note 2 The CPU cannot return from HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into HALT HOLD or X tal HOLD mode Interrupt level at which the CPU entered HALT HOLD or X tal HOLD mode Interrupt request level that can release HALT mode No interrupt request present X H and L levels L level X and H levels H level X level X level None unable to release with interrupt Fig 4 3 1 Standby Mode State Transition Diagram 4 18 LC875W00 Chapter 4 4
147. e reference timer TIPWML TIPWMH generate a signal that toggles at the interval of TIL and period respectively Note 1 3 48 LC875W00 Chapter 3 TIL period T1LR 1 x TILPRC count x 2Tcyc or TILR 1 x TILPRC count events detected TIPWML period lt period x 2 period TIHR 1 x TIHPRC count x TIL period 1 x TIHPRC count x 1 x TILPRC count events detected TIPWMH period period x 2 4 Mode3 16 bit programmable timer with an 8 bit prescaler with toggle output the low order 8 bits may be used as a PWM A 16 bit programmable timer runs on the cycle clock The low order 8 bits run as PWM TIPWML having a period of 256 Tcyc TIPWMH generates a signal that toggles at the interval of T1 period Note 1 TIPWML period 2256 x TILPRC count x Tcyc TIPWML low period TILR 1 x TILPRC count x Tcyc period T1HR 1 x TIHPRC count x TIPWML period TIPWMH period period x 2 5 Interrupt generation TIL interrupt request is generated at the counter period of the TIL or timer if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control the timer 1 T1 TICNT TIL T1H TILR TIHR TIPRR PI PIDDR PIFCR P2 P2DDR I45CR I45SL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE18 0000 0000 TICNT TIHRU
148. e same time Continued on next page 3 82 LC875W00 Chapter 3 Table 3 19 1 5101 Operations and Operating Modes cont Synchronous Mode 0 UART Mode 1 Bus Master Mode 2 Slave Mode 3 Transfer Receive Transfer Receive Transfer Receive Transfer Receive SI1REC 0 SHREC 1 0 SHREC 1 SI1REC 0 SI1REC 1 SHREC 0 sHREC 1 SIIOVR 1 lt 1 lt 1 lt 1 E bit 2 Falling edge Falling edge SILEND set Falling edge of clock of clock conditions of clock detected detected met when detected when when SIIEND 1 when 5 0 SILRUN 0 SIIRUN 0 2 2 2 SIIEND set SIIEND set SIIEND set conditions conditions conditions met when met when met when SIIEND 1 SIIEND 1 SIIEND 1 3 Start bit detected Clear Instruction lt Instruction lt Instruction lt Instruction gt Shifter data update Shifter gt SBUFI bits 0 to 7 Automatic update of SBUFI bit 8 Clock SBUF1 shifter at beginning of operation When 8 bit data transferred shifter at beginning of operation Rising edge of 8th clock dat rec Input data read in on stop bit When 8 bit a eived Clock generator circuit Data input lt a Data 8 bit shift register SIOSF1 output Ly At time At time operation transfer ends starts bit7 bit6 bit5 bit4 bit3 bit2 bito SBUF1 FE35h Clock SBUFI shifter at beginning of operation Rising edge
149. ea is 2 SFR to FEFFH the intended address 2 lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of B register are placed in the ACC as the result of computation OFFO1H amp 0FFH 0FE00H OFE01H 2 11 5 Direct Addressing dst Direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates the optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction L1 STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H 11 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 8 LC875W0
150. ee eee eee ee ee ee ee eee ee ee eee ee ee ee ee ee ey 3 24 3 7 2 Functions 3 24 3 7 3 Related Registers eee ere terre eee eee eee eer eee eee ee ee eee eee eee eee eee ee ee eee eee 3 24 3 7 4 Options eee eee ere rere rere rer rere rere eee ee eee eee eee ee eee ee ee eee ee eee eee ee ee ee ee ee 3 25 3 7 5 HALT and HOLD Mode Operation eee rere eee eee ee ee eee eee eee ee eee ee ee 3 25 Port B mrsnanansursasanuansuasesenuauueansessasuuamsensasenuauueansesssuuausessesaenuauuansececnuaus 3 26 3 8 1 Overview 3 26 3 8 2 Functions 3 26 3 8 3 Related Registers eee eee eee eee eee eee eee eee ee eee ee eee eee ee eee eee ee eee eee ee 3 26 3 8 4 Options 3 27 3 8 5 HALT and HOLD Mode Operation eee eee ere eee eee eee eee eee ee eee ee eee ee re 3 27 Port gt ere eee e rere re eee rere reer eee e
151. em clock to i Or 1 z 4 state of the XT1 and XT2 pins can be read as bits 2 and 3 of this register 4 2 3 6 2 general purpose port output control register XT2PC 8 bit register 1 This register controls the general purpose output N channel open drain type at the XT2 pin 4 2 8 7 System clock division control register CLKDIV 3 bit register 1 This register controls the operation of the system clock divider circuit The division ratio of the clock 101010101 1 1 1 an tt or can be set to 17227 4 8 16 32 64 128 5 4 2 CLKSGL CLKDV2 0 2 Main clock CFSTOP gt CF oscillator System clock SCLK Selector Frequency division 5 56 4 9 23 0 oS 9 RCSTOP gt RC oscillator cock To base timer Subclock EXTOSC gt Sub oscillator fSCLK System clock frequency fCYC Cycle clock frequency Minimum instruction cycle fCYC 3 x fSCLK Fig 4 2 1 System Clock Generator Block Diagram 4 8 LC875W00 Chapter 4 4 2 4 Related Registers 4 2 4 1 Power control register PCON 3 bit register 1 This register is a 3 bit register used to specify the operating mode normal HALT HOLD X tal HOLD See Section 4 3 Standby Function for the procedures to enter and exit microcontroller operating modes Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 H000 R W gt XTIDLE
152. emarks BIT8 BIT7 BIT6 BIT5 BIT4 2 0 XXXX R TOCAIL Timer 0 capture register 1L TOCAIL7 TOCAIL6 TOCA1L5 TOCAIL4 TOCAIL3 0 112 1 TOCAILO FEIF XXX XXX R Timer 0 capture register iH TOCAIHS TOCATH3 2 TOCATHI TOCATHO 20 0000 HHHH R W PWMOcompare L additional PNMOLS PWMOL2 PWMOLO FE21 0000 0000 R W PWMOH Pwm o compare H reference 1 PNMOH7 PWMOHG PWMOHS PWMOH4 2 PNMOHI PMMOHO FE22 0000 HHHH R W PWM1 compare additional 2 Pwo 22 0000 0000 R W PWM1 compare reference 1 PNMIH7 PWMIHG PWMIH4 2 FE25 HHHH HHXX R PMMOIP 0 PWM 1 port input _ fl sg EH FE28 00000000 RAM PE PEO FE29 0000 0000 R W PEFCR FE2A 00000000 RAM PF Anae FE2B 0000 0000 R W PFFCR IS Sees MU Page E FED TT pup a 1 rg SETS
153. en both transmit and receive operations are to be performed at the same time TDDR2 bit 5 UART2 transmit port output control 1 When this bit is set to 1 the transmit data is placed at the transmit port P34 No transmit data is output if bit 4 of P3DDR at FE4D is set to 1 2 When this bit is set to 0 no transmit data is placed at the transmit port P34 The transmit port is placed in high open CMOS N channel open drain mode if this bit is set to 1 when the UART2 has stopped a transmit operation TRUN2 0 This bit must always be set to 0 when the UART2 transmit function is not to be used TCMOS2 bit 4 UART2 transmit port output type control 1 When this bit is set to 1 the output type of the transmit port is to CMOS 2 When this bit is set to 0 the output type of the transmit port P34 is set to N channel open drain 3 112 LC875W00 Chapter 8 7 BIT2 bit 3 UART2 transfer data length control 1 This bit and 8 9 BIT2 bit 6 are used to control the transfer data length of the UART2 TBIT82 bit 2 UART2 transmit data bit 8 storage bit 1 This bit stores bit 8 of the transmit data when the data length is set to 9 bits 8 9BIT2 1 and 8 7BIT2 0 TEPTY2 bit 1 UART2 transmit shift register transfer flag 1 2 This bit is set when data transfer from the transmit data register TBUF2 to the transmit shift register TSFT2 ends at the beginning of the transm
154. ent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC875W00 SERIES USER S MANUAL Rev 1 00 February 4 2011 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit
155. er 7 T7 incorporated in this series of microcontrollers are 8 bit timers with two independently controlled 6 bit prescalers 3 16 2 Functions 1 Timer 6 6 Timer 6 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock It can generate at pin P06 toggle waveforms whose frequency is equal to the period of timer 6 T6 period 6 1 4 nz1 2 3 Tcyc Period of cycle clock 2 Timer 7 T7 Timer 7 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock It can generate at pin 07 toggle waveforms whose frequency is equal to the period of timer 7 T7 period T7R 1 x 4 Tcye nz1 2 3 Period of cycle clock 3 Interrupt generation Interrupt request to vector address 0043H is generated when the overflow flag is set at the interval of timer 6 or timer 7 period and the corresponding interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control the timer 6 T6 and timer 7 T7 T67CNT T6R T7R POFCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 R W T67CNT 7 0 T6CO T7IE T6OV T6IE r2 0000 porcr CLKOEN CKODV2 CKODVO 3 16 3 Circuit Configuration 3 16 3 1 Timer 6 7 control register TG7CNT 8 bit register 1 Thisregister controls the operation and interrupts o
156. er eee eee eee ee eC eee eee Cee ee eee eee ee ee rer 3 28 3 9 1 Overview eee eee ere eee rere rere ee eee ee ee eee eee eee eee ee ee eee eee eee eee ee ee ee ee 3 28 3 9 2 Functions 3 28 ii 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 Contents 3 9 3 Related Registers meme 3 28 3 94 Options mmm eene 3 29 3 9 5 HALT and HOLD Mode Operation mme 3 29 act 3 30 3 10 1 Overview S Dax 3 30 34039 Functions bo MEIN 3 30 3 10 3 Related Registers eee 3 30 3 10 4 HALT and HOLD Mode Operation mmm 3 31 acp 3 32 9311 1 Overview LLLI E 3 32 amp o e aep en ER idtm cuu dU os ui tox I ieu t Se Une 3 32 3 11 3 Related Registers eene 3 32 3 11 4 HALT and HOLD Mode Operation mmm 3 33 Timer Counter 0 TO Hem HH HH HH 3 34 3 12 1 Overview LLLI 3 34 3 34 3 42 3 Circuit Configuration mmm 3 36 3 42 4 Related Registers eee 3 41 High speed Clock Counter H He 3 44 3143 1 OUST LEE 3 44 9143 2 Te DE I rr er errr re caer eres Ce 3 44 3 13 3 Circuit Coufiguration meme 3 45 3 13 4 Related Registers eee 3 46 Timer Counter 1 T1 e M HH 3 48
157. eriod for the timer 5 determined by T5CO and 5 T45CNT FE3C bits 6 and 7 Table 3 15 2 Timer 5 Count Clocks T5 Count Clock The timer 5 prescaler and timer counter are in the reset state 64 Tcyc 3 15 3 7 Timer 5 period setting register T5R 8 bit register 1 Thisregister defines the period of timer 5 2 When data is written into T5R while timer 5 is running both the timer 5 prescaler and counter are cleared and start counting again 3 60 LC875W00 Chapter 3 3 15 4 Related Registers 3 15 4 1 Timer 4 5 control register T45CNT 1 This register is an 8 bit register that controls the operation and interrupts of T4 and TS Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3C 0000 0000 R W 5 5 T5CO T4CO 5 5 1 bit 7 5 count clock control T5CO bit 6 T5 count clock control T5C1 T5CO T5 Count Clock 0 The timer 5 prescaler and timer counter are stopped in the reset state 1 4 0 1 o l6Ty 0 T4C1 bit 5 T4 count clock control T4CO bit 4 T4 count clock control T4 Count Clock The timer 4 prescaler and timer counter are stopped in the reset state T5OV bit 3 T5 overflow flag This flag is set at the interval of timer 5 period when timer 5 is running This flag must be cleared with an instruction T5IE bit 2 T5 interrupt request enable control An interru
158. esesausanesenessssesonenasuseseonanausesanansanenenaneun 2 6 2 1 1 1 Immediate Addressing sessasasaunanssusasunsenspassuanassanssausucnuasmansusuansonuanes 2 6 2 11 2 Indirect Register Indirect Addressing Rn 2 7 2 11 3 Indirect Register C Register Indirect Addressing Rn C nn 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off 2 8 2 1 1 5 Direct Addressing dst sasssnsasussanssauuasuasusasenasaunscusssanHusanasuussuasusuanusuonanuua 2 8 2 1 1 6 ROM Table Look up Addressing sassansasuonanscsuuasenusanansuensnyuessenausasunscunsanenansuasn 2 9 2 1 1 7 External Data Memory Addressing sesssnasssnanssnuasesuananasuunscsuanansaunanscuauauuon 2 9 2 1 2 Wait Sequence 2 1 0 2 1 21 Wait Sequence Occurrence sasasssanssauusnuuanuuuasussansasaumauuauunsaunumsunmauunsa uuuunauunmuuu 2 1 0 2 1 2 2 What is a Wait Sequence sassnusuauanuasuuassuauunssansauauanunuaumausuunsaunuuausauunuasas 2 1 0 Chapter 3 Peripheral System Configuration iUis id 3 1 3 1 Port 0 3 1 3 1 1 Overview BRRARRRARARRSESARRRARRARRSRRARRRARRRGRRARRRARRRGSRARRRRRRRGRRARRRARRRSRARRRRRRRGRRAR RR Rn 3 1 3 1 2 Functions
159. essing in which case another 8 clocks are required to generate an interrupt Read SBUFI and store the read data Note Bit 8 of SBUFI is not yet updated because the rising edge of 9th clock has not yet occurred Return to in step 6 to continue receive processing Sending data 1 3e Clear SII REC Load SBUFI with output data Clear and exit interrupt processing Send an acknowledge for the preceding reception operation and release the clock port after the lapse of SBR1 value 1 x Tcyc Perform a send operation 8 bits and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs Go to 3 in step 7 when SIIRUN is set to 1 When SII RUN is set to 0 implying an interrupt from 4 in step 7 clear SIIEND and SIIOVR and return to 1 in step 4 Read SBUF1 and check send data as required Note Bit 8 of SBUF1 is not yet updated because the rising edge of 9th clock has not yet occurred 3 88 LC875W00 Chapter 3 Load SBUFI with the next output data e Clear SIIEND and exit interrupt processing Release the clock port after the lapse of SBRI value 1 x Return to 1 in step7 when an acknowledge from the master is present L When there is no acknowledge presented from the master H SIO1 recognizing the end of data transmission automatically clears 1 and releases the data port However in a case that restart co
160. established at entry Stopped Stopped oscillation time Internal RC Running State established at entry Stopped Stopped oscillation time Subclock Stopped State established at entry Stopped State established at oscillation time entry time PU Stopped Stopped Stopped M RES Undefined Data retained Data retained Data retained When watchdog timer reset Data retained Base timer Stopped State established at entry Stopped State established at time entry time Peripheral Stopped State established at entry Stopped Stopped modules except time base timer Exit conditions Entry conditions nterrupt request Interrupt request from Interrupt request from accepted INTO to INT2 INT4 INTO to INT2 INTA Reset entry conditions INTS or POINT INT5 POINT or base established Reset entry conditions timer established Reset entry conditions established Returned mode Normal mode Notel HALT Note HALT Notel Data changed on PCON register bit0 0 PCON register bit 1 0 PCON register bit 1 0 exit Note 1 The microcontroller switches into the reset state if it exits the current mode on the establishment of reset entry conditions entry separate table cleared if WDT register FEOF bit 4 is set canceled 4 15 Standby Table 4 3 2 Pin Name Reset Time Normal Mode Pin States and Operating Modes this series HALT Mode HOLD Mode On Exit from HOLD RE Input S XTI Input X t
161. et SIIREC to 1 Clear SIIEND and exit interrupt processing receive 8 bits output SBUFI bit 8 acknowledge 9 Reading received data after an interrupt Read SBUFI Return to step 8 to continue reception of data e Go to in step 10 to terminate processing At this moment SBUFI bit 8 data has already been presented as acknowledge data and the clock for the master side has been released 10 Terminating communication e Manipulate the clock output port PISFCR 0 PISDDR 1 P1520 and set the clock output to 0 e Manipulate the data output port P14FCR 0 PI4DDR 1 P14 0 and set the data output to 0 Restore the clock output port into the original state PISFCR 1 PISDDR 1 P15 0 and release the clock output e Wait for all slaves to release the clock and the clock to be set to 1 e Allow for a data setup time then manipulate the data output port P14FCR 0 P14DDR 1 P14 1 and set the data output to 1 In this case the SIO1 overrun flag SILOVR SCONI FE24 bit 2 is set but this will exert no influence on the operation of SIO1 e Restore the data output port into the original state set PI4FCR to 1 then PI4DDR to 1 and P14 to 0 e Clear SITEND and 5 then exit interrupt processing Return to step 4 to repeat processing 3 87 SIO1 3 19 4 4 2 3 4 5 6 7 Bus slave mode mode 3 Setting the clock Set up SBRI to set the acknowledge data setup time Setting
162. et data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains FEO2H and off has a value of 7EH 2 for example the A register FEO2H 2 is designated Examples When contains 123H RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator L1 STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three functional areas as explained in Section 2 1 namely 1 system reserved area FF00H to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains OFDFFH since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 lies outside the basic area and is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic ar
163. f T6 and T7 3 16 3 2 Timer 6 counter T6CTR 8 bit counter 1 The timer 6 counter counts the number of clocks from the timer 6 prescaler T6PR The value of timer 6 counter T6CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 6 period setting register when the interrupt flag T6OV is set 2 When T6CO and T67CNT FE78 bits 4 and 5 are set to 0 the timer 6 counter stops at a count value of 0 In the other cases the timer 6 counter continues operation 3 When data is written into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 63 6 T7 3 16 3 3 Timer 6 prescaler T6PR 6 bit counter 1 This prescaler is used to define the clock period for the timer 6 determined by T6CO and T6C1 T67CNT FE78 bits 4 and 5 Table 3 16 1 Timer 6 Count Clocks T6C1 T6CO T6 Count Clock 0 Timer 6 prescaler and timer counter are in the reset state 1 4 Tcyc 1 0 f Ty 64 3 16 3 4 Timer 6 period setting register 8 bit register 1 This register defines the period of timer 6 2 When data is written into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 16 3 5 Timer 7 counter T7CTR 8 bit counter 1 timer 7 counter counts the number of clocks from the timer 7 prescaler T7PR The value of timer 7 c
164. g in TOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHO 3 12 4 5 Timer counter 0 match data register low byte TOLR 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the low order byte of timer counter 0 16 bits of data must match in 16 bit mode 2 The match buffer register is updated as follows When it is inactive TOLRUN 0 the match register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLRI TOLRO 3 42 LC875W00 Chapter 3 3 12 4 6 Timer counter 0 match data register high byte 1 This register is used to store the match data for It has 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data must match in 16 bit mode 2 match buffer register is updated as follows When it is inactive TOHRUN 0 the match register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded wi
165. g the cycle clock by 2 or the number of external events while TIH functions as an 8 bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2 Two independent 8 bit programmable timers T1L and T1H run on a clock that is obtained by dividing the cycle clock by 2 TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and period respectively Note 1 Mode 1 TIL period TILR 1 TILPRC count x 2Tcyc T1LR 1 x TILPRC count events detected TIPWML period T1L period x 2 period x TIHPRC count x 2Tcyc TIPWMH period T1H period x 2 Two channels of 8 bit PWM with an 8 bit prescaler Two independent 8 bit PWMs TIPWML and TIPWMH run on the cycle clock Mode 2 TIPWML period 2256 x TILPRC count x Tcyc TIPWML low period T1LR 1 x TILPRC count x Tcyc TIPWMH period z 256 x TIHPRC count x Tcyc TIPWMH low period T1HR 1 x TIHPRC count x Tcyc 16 bit programmable timer counter with an 8 bit prescaler with toggle output the low order 8 bits may be used as a timer counter with toggle output A 16 bit programmable timer counter runs that counts the number of signals obtained by dividing the cycle clock by 2 or the number of external events Since interrupts can occur from the low order 8 bit timer at the interval of T1L period the low order 8 bits of this 16 bit programmable timer counter can be used as th
166. gnated by the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes 2 3 Program Memory ROM This series of microcontrollers has a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the type of microcontroller The ROM table look up instruction LDC can be used to reference all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 1FF00H to IFFFFH for this series of microcontroller is reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM This series of microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the type of the microcontroller 9 bits are used to access addresses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table look up instruction LDC however their bit length is set to 17 bits 9 high order bits 8 low order bits As shown in Figure 2
167. hannel open drain output 4 Setting up the continuous data bit register Specify the number of bits to be subject to continuous transmission reception processing 5 Setting up output data Write the output data of the specified bit length to data RAM at the specified address in data transmission or data transmission reception mode Write to RAM addresses 01CO H to 01DF H when SIOBNK 0 RAM addresses 01 EO H to 01FF H when SIOBNK 1 Data transmission and reception processing is started after the operation flag is set and the contents of RAM and SBUFO are exchanged Consequently there is no need to load the data into SBUFO 6 Starting operation Set SIOCTR Set SIORUN Suspending continuous data transfer processing Set SOWSTP Resuming continuous data transfer processing Clear SOWSTP Checking the number of bytes transferred during continuous data transfer processing Read SOXBYTA to SOXBYTO 7 Reading data after an interrupt Received data has been stored in data RAM at the specified address and SBUFO RAM addresses 01C1 H to 01DF H when SIOBNK 0 RAM addresses 01 E1 H to 01FF H when SIOBNK 1 The last 8 bits or less of received data are left in SBUFO and not present in RAM Clear SIOEND Return to step 5 when repeating transmission reception processing 3 78 3 18 6 3 18 6 1 2 3 18 6 2 2 LC875W00 Chapter 3 5 0 HALT Mode Operation Synch
168. hen SIOWRT 1 data transmission and reception are carried out Any data received after the transmission reception processing terminated is left in SBUFO and not exchanged with data in RAM 5 0 Communication Examples Synchronous 8 bit mode Setting the clock Set up SBRO when using an internal clock Setting the mode e Set as follows SIOCTR 0 SIODIR SIOIE 1 Setting up the ports Clock Port Internal clock Output Data Output Port Data I O Port Data transmission only Output Data transmission reception 3 wire Output Data transmission reception 2 wire O N channel open drain output Setting up output data Write the output data into SBUFO in data transmission or data transmission reception mode Starting operation Set SIORUN Reading data after an interrupt Read SBUFO SBUFO has been loaded with serial data from the data I O port even the transmission mode Clear SIOEND Return to step 4 when repeating processing 3 77 5100 3 18 5 2 Continuous data transmission reception mode 1 Setting the clock Setup SBRO when using an internal clock 2 Setting the mode Setas follows SIOBNK SIOWRT 1 SIODIR 7 SIOIE 1 3 Setting up the ports Internal clock Output External clock Input Data Output Port Data I O Port Data transmission only Output Data transmission reception 3 wire Output Data transmission reception 2 wire N c
169. hes the value of the low order byte of timer counter 0 16 bits of data must match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOLRUN 0 the match register matches TOLR e When it is active TOLRUN 1 the match buffer register is loaded with the contents of when a match signal is generated Timer counter 0 match data register high byte TOHR 8 bit register with a match buffer register This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data must match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOHRUN O the match register matches TOHR e When it is active TOHRUN 1 the match buffer register is loaded with the contents of TOHR when a match signal is generated Timer counter 0 capture register low byte TOCAL 8 bit register Capture clock External input detection signals from the P70 INTO TOLCP P72 INT2 TOIN TOLCP and P20 to P27 timer OL capture input pins when TOLONG timer 0 control register bit 5 is set to 0 External input detection signals from the P73 INT3 TOIN and P20 to P27 timer OH capture input pins when TOLONG timer 0 control register bit 5 is set to 1 Capture data Contents of the low order b
170. high level setting the runaway detection flag 2 Actions to be taken following the detection of a runaway condition The microcontroller can take one of the following actions when the watchdog timer detects a program runaway condition Reset program reexecution External interrupt INTO generation program continuation The priority of the external interrupt INTO can be changed using the master interrupt enable control register IE 4 5 3 Circuit Configuration The watchdog timer is made up of a high threshold buffer a pulse stretcher circuit and a watchdog timer control register Its configuration diagram is shown in Figure 4 5 1 High threshold buffer The high threshold buffer detects the charging voltage of the external capacitor Pulse stretcher circuit The pulse stretcher circuit discharges the external capacitor for longer than the specified time to ensure reliable discharging The stretching time is from 1920 to 2048 Tcyc Watchdog timer control register WDT The watchdog timer control register controls the operation of the watchdog timer 4 21 Watchdog Timer INTO interrupt P70 INTO TOLCP Reset Interrupt control circuit Pulse stretcher circuit MOV 55H WDT Instruction 71 15441 2 110 WDT FEOF Fig 4 5 1 Watchdog Timer Circuit 4 5 4 Related Registers 4 5 4 1 Watchdog timer control register WDT Address Initial value R W Name BIT7 BIT6 BITS BIT4 B
171. iable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Port C VO 8 bit I O port Yes PCO to PC7 I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions flash ROM type PC5 to PC7 On chip debugger interface DBGPO to DBGP2 Port E 8 bit I O port No PEO to PE7 I O specifiable in 2 bit units Pull up resistors can be turned on and off in 1 bit units Port F IO 8 bit I O port No PFO to PE7 I O specifiable in 2 bit units Pull up resistors can be turned on and off in 1 bit units Continued on next page 1 8 LC875W00 Chapter 1 Pin functions continued Pin Description SIO2 port 4 bit I O port I O specifiable in 1 bit units Multiplexed pin functions SI2P0 SIO2 data output SI2P1 5102 data input bus I O SI2P2 SIO2 clock I O SI2P0 to SI2P3 SI2P3 SIO2 clock output PWMO PWMO output port Can be used as a general purpose I O port PWMI I O PWMI output port Can be used as a general purpose I O port RES I Reset pin 32 768 kHz crystal resonator input pin No Multiplexed pin functions ANIO AD converter input port General purpose input port Must be connected to VDD1 if not to be used 32 768 kHz crystal resonator output pin No Multiplexed pin functions AN11 AD converter input port General purpose I O port Must be set for oscillation and kept open if n
172. ile timer 4 is running both the timer 4 prescaler and counter are cleared and start counting again 3 59 T4 T5 3 15 3 3 Timer 4 prescaler T4PR 6 bit counter 1 This prescaler is used to define the clock period for the timer 4 determined by T4CO and T4C1 T45CNT FE3C bits 4 and 5 Table 3 15 1 Timer 4 Count Clocks T4C1 0 Count Clock 0 The timer 4 prescaler and timer counter in the reset state 1 4 1 167 64 3 15 3 4 Timer 4 period setting register T4R 8 bit register 1 This register defines the period of timer 4 2 When data is written into T4R while timer 4 is running both the timer 4 prescaler and counter are cleared and start counting again 3 15 3 5 Timer 5 counter T5CTR 8 bit counter 1 Thetimer 5 counter counts the number of clocks from the timer 5 prescaler 5 Its value reaches 0 on the clock following the clock that brought about the value specified in the timer 5 period setting register T5R when the interrupt flag T5OV is set 2 When T5CO and 5 T45CNT FE3C bits 6 and 7 are set to 0 the timer 5 counter stops at a count value of 0 In the other cases the timer 5 counter continues operation 3 When data is written into T5R while timer 5 is running both the timer 5 prescaler and counter are cleared and start counting again 3 15 3 6 Timer 5 prescaler T5PR 6 bit counter 1 This prescaler is used to define the clock p
173. ined in Subsection 2 12 1 the CPU suspends the execution of the instruction for one cycle during which the required data is transferred This is called a wait sequence The peripheral circuits such as timers and PWM continue processing during the wait sequence A wait sequence extends over no more than two cycles The microcontroller performs no wait sequence when it is in HALT or HOLD mode Note that one cycle of discrepancy is introduced between the progress of the program counter and time once a wait sequence occurs 2 10 LC875W00 Chapter 2 Table 2 4 1 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction Bit 8 RAM SFR P1 PSW Bit 1 Remarks LD LDW P1 lt REG8 P1 lt REGH8 as Z PUSH PUSH PI REGS PUSHW PL REGHS PUSH P P1 bitl when PSW is REG8 RAMS PI RAMS8 popped REGH8 lt RAMH 8 REGL8 lt RAML8 PIX P1 lt bit1 when high order address of PSW is popped Bit 8 ignored LD LDW ST STW MOV POP BA P1 lt RAMH8 X REG8OPI Same as left XCHW REGHS8 PI REGL8 lt Pl P1 lt REGH8 Same as left INC 9 bits 1 lt after computation INC 17 bits REGL8 lt low byte of CY 1 lt after computation DEC 9 bits 1 lt after computation DECW DEC 17 bits PI REGHS after REGL8 lt low byte of CY inverted computation C DBNZ DEC 9 bits P1 lt REG8 Z DEC 9 bits P1 lt REG8 NOTI C CRI f 2
174. instead of the data at port pins 3 Port A data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE68 0000 0000 R W PA FIXO FIXO PAS PA4 PA3 PA2 PAI PAO 3 7 3 2 Port A data direction register PADDR 1 This register is an 8 bit register that controls the I O direction of port A data in 1 bit units Port PAn is placed in output mode when the bit PAnDDR is set to 1 and in input mode when the bit PAnDDR is set to 0 2 Port PAn is configured as an input pin with a pull up resistor when the bit PAnDDR is set to 0 and port A data latch bit PAn is set to 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE69 0000 0000 R W PADDR FIXO PASDDR PA4DDR PA3DDR PA2DDR PAIDDR PAODDR LC875W00 Chapter Register Data Port PAn State Internal Pull up PAnDDR Input Resistor Enabled OFF 0 0 Enabled High open CMOS N channel open drain 3 7 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 7 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port A retains the state that is established when HALT or HOLD mode is entered 3 25 Port B 3 8 Port B 3 8 1 Overview Port B is an 8 bit I O port that is made up of a data control latch and a control circuit The d
175. ion noise filter time constant selectable from among 1 Tcyc 32 Tcyc and 128 Noise filtering function is available for the INT3 TOIN or TOHCP signals at pin P73 If P73 is read with an instruction the signal level at the pin is read regardless of the noise filtering function e Watchdog timer 1 Watchdog timer with an external RC circuit 2 Interrupt or system reset is selectable Clock output function 1 Capable of generating D gt gt or 2 frequency of the source oscillator clock selected as the system clock 2 gt Capable of generating the source oscillator clock for the subclock Interrupts 29 sources 10 vector addresses 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt request of the level equal to or lower than the current interrupt is not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the smallest vector address is given priority Vector Level Interrupt Source 00003H XorL INTO 00013H INT2 TOL INT4 0001BH INT3 INTS Base timer 0 Base timer 1 i e Priority levels X gt gt When interrupts of same level occur at same time an interrupt with the smallest vector address is given priority Subroutine stack levels Up t
176. irection of the signals can be specified in 1 bit units As a user option either CMOS output or N channel open drain output can be specified as the output type in 1 bit units 3 8 2 Functions 1 Input output port 8 bits PBO to PB7 The 8 bits of the port B data control register PB FE6C are used to control the port output data The 8 bits of the port B data direction register PBDDR FE6D are used to control the I O direction of data in 1 bit units The output type can be selected from N channel open drain output and CMOS output as a user option Each port bit is provided with a programmable pull up resistor 2 Register configuration tis necessary to manipulate the following special function registers to control port B Initial Value 0000 0000 0000 0000 3 8 3 Related Registers 3 8 31 Port B data latch PB 1 The port B data latch is an 8 bit register for controlling port B output data 2 When this register is read with an instruction data at pins PBO to PB7 is read in If the PB FE6C is manipulated using the NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port B data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE6C 0000 0000 R W PB PB7 PB6 PBS PB4 PB3 PB2 PBO 3 8 3 2 Port B data direction register
177. is bit is set at the end of a receive operation if the state of the received stop bit the last data bit received is low 2 This bit must be cleared with an instruction 00 3 bit 3 General purpose flag 1 This bit can be used as a general purpose flag bit Any attempt to manipulate this bit exerts no influence on the operation of the functional block RBITS bit 2 UART1 receive data bit 8 storage bit 1 This bit position is loaded with bit 8 of the received data at the end of receive operation when the data length is set to 9 bits UCONI 8 9BIT 1 8 7BIT 0 If the receive operation is terminated prematurely this bit position is loaded with the last received bit but one 2 This bit must be cleared with an instruction 3 100 LC875WO00 Chapter RECEND bit 1 UART1 receive end flag 1 This bit is set at the end of a receive operation When this bit is set the received data is transferred from the receive shift register RSFT to the receive data register RBUF 2 This bit must be cleared with an instruction the continuous receive mode the next receive operation is not carried out even when the UARTI detects data that sets the receive start flag RECRUN before this bit is set RECIE bit 0 UART1 receive interrupt request enable control 1 When this bit and RECEND are set to 1 an interrupt request to vector address 0033H is generated 3 21 4 2 UART1 control register 1 UCON1 1 Thisregister is an 8 b
178. is in progress ADCR2 bit 2 AD conversion time control This bit and bit SLADCL DACR bit 2 control the AD conversion time Table below shows the relationship between the values of these bits and the AD conversion times AD Conversion time Tcyc ADCR2 SLADCL Set the conversion time to an appropriate value using the frequency of the cycle clock and these two bits ADCR2 SLADCL ADCR bit 1 AD conversion end flag This bit identifies the end of AD conversion It is set when AD conversion is finished An interrupt request to vector address 0043H is generated if ADCRO is set to 1 If ADCRI is set to 0 it indicates that no AD conversion is in progress This flag must be cleared with an instruction ADCRO bit 0 AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADCRI are set to 1 Note In HALT or HOLD mode ADCR3 is set to 0 and AD conversion is disabled 3 136 LC875W00 Chapter 3 3 25 4 2 Reference voltage generator circuit control register DACR 1 This register is an 8 bit register for controlling the operation of the AD converter Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO ruo ww pace pace paces paces sanct pacea pacer DACR7 bit 7 Fixed bit This bit must always be set to 0 DACRE bit 6 Fixed bit This bit must always be set to 0
179. it operation This bit is set in the cycle Tcyc following the one in which the transmit control bit TRUN2 is set to 1 This bit must be cleared with an instruction When performing a continuous transmit operation make sure that this bit is set before each loading of the next transmit data into the transmit data register TBUF2 When this bit is subsequently cleared the transmit control bit TRUN2 is automatically set at the end of the transmit operation TRNSIE2 bit 0 UART2 transmit interrupt request enable control 1 3 22 4 3 1 2 An interrupt request to vector address 003BH is generated when this bit TEPTY2 are set to 1 UART2 baudrate generator UBR2 The UART2 baudrate generator is an 8 bit register that sets the transfer rate of the UART2 transfer The counter for the baudrate generator is initialized when a UART2 transfer operation is stopped or terminated UCON2 RECRUN2 UCON3 TRUN2 0 Do not change the transfer rate in the middle of a UART2 transfer operation The UART2 will not function normally if the baudrate is changed during operation Always make sure that the transfer operation has ended before changing the baudrate The same transfer rate is used when both transmit and receive operations are to be performed at the same time This also holds true when continuous transmit and receive operations are to be performed at the same time When UCON2 UBRSEL2 0 TUBR2 UBR2 value 1 x 5
180. it register that controls the transmit operation data length and interrupts for the UARTI Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FED1 0000 0000 R W UCONI TRUN 8 9BIT TDDR TCMOS 8 7BIT TBIT8 TEPTY TRNSIE TRUN bit 7 UART1 transmit control 1 When this bit is set to 1 the UARTI starts a transmit operation 2 This bit is automatically cleared at the end of the transmit operation If this bit is cleared during the transmit operation the operation is aborted in the middle of the processing n continuous transmit mode this bit is cleared at the end of a transmit operation but is automatically set within the same cycle Tcyc Consequently transmit operations occur with intervening 1 Tcyc delays the continuous transmit mode TRUN will not be set automatically if a bit manipulation instruction NOTI CLR1 SET1 is executed to UCONI register in the same cycle in which TRUN is to be automatically cleared 8 9 BIT bit 6 UART1 transfer data length control 1 This bit and 8 7 BIT bit 3 are used to control the transfer data length of the UARTI 8 9 BIT 8 7 BIT Data Length in bits 9 1 0 a a a will not run normally if the data length is changed in the middle of a transfer operation Be sure to manipulate this bit after confirming completion of a transfer operation The same data length is used when both transmit and receive
181. l time output pin functions as an ordinary port pin 3 45 NK Counter 3 13 3 3 Timer counter 0 operation TOLEXT TOCNT bit 4 must be set to 1 when a high speed clock counter is to be used When NKEN 1 and TOLONG TOCNT bit 5 0 timer OH runs in the normal mode and timer OL 15 coupled with the high speed clock counter to form an 11 bit free running counter When NKEN 1 and TOLONG TOCNT bit 5 1 timer 0 is coupled with the NK counter to form a 19 bit free running counter When a free running counter reaches the count value timer 0 match register valuet 1 x 8 value of NKCMP2 to NKCMPO a match detection signal occurs generating real time output of the required value and setting the match flag of timer 0 No new match signal is detected until the next NKREG write operation is performed The match data for these free running counters must always be greater than the current counter value When updating the match data the match register for timer 0 must be set up before loading the match register for NKREG NKCMP2 to NKCMPO with data Even if the same value is loaded it must be written into NKREG to start a search for a match 3 13 4 Related Register 3 13 4 1 High speed clock counter control register NKREG 1 This register is 8 bit register that controls the operation of the high speed clock counter Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7D 0000 0000 R W NKREG NKEN 2
182. leared with an instruction 3 69 BTIEO bit 0 Base timer interrupt 0 request enable control Setting this bit and BTIFO to 1 generates X tal HOLD mode release signal and interrupt request to vector address 001BH Notes The system clock and base timer clock cannot be selected at the same time as the subclock when BTFST BTCIO 1 high speed mode e Note that BTIFI is likely to be set to 1 when BTC11 and BTC10 are rewritten e If HOLD mode is entered while running the base timer when the cycle clock or subclock is selected as the base timer clock source the base timer is subject to the influence of unstable oscillations caused by the main clock and subclock when they are started following the release of HOLD mode resulting in an erroneous count from the base timer When entering HOLD mode therefore it is recommended that the base timer be stopped e This series of microcontrollers supports X tal HOLD mode which enables low current intermittent operation In this mode all operations other than the base timer can be suspended 3 17 4 2 Input signal select register ISL 1 This register is an 8 bit register that controls the timer 0 input noise filter time constant buzzer output and base timer clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer capture signal input port select S
183. level H IFLGR is read to refer to BTI BTO INTS INT3 source flags associated with vector address 001Bh and data C7h is read Clear INT3 interrupt source flag then execute RETI instruction to exit H level interrupt state Return to L interrupt level IFLGR is read to refer to TOL INT4 INT2 source flags associated with vector address 0013h and data F7h is read Clear TOL and INT2 interrupt source flags then execute RETI instruction to exit L level interrupt processing routine Return to no interrupt state Reading IFLGR returns data FFh because the microcontroller is not in the interrupt state Normal operation No interrupt 4 5 System Clock 4 2 System Clock Generator Function 4 21 Overview This series of microcontrollers incorporates three systems of oscillator circuits i e the main clock oscillator subclock oscillator and RC oscillator as system clock generator circuits The RC oscillator circuit has built in resistors and capacitors so that no external circuit is required The system clock can be selected from these three types of clock sources under program control 4 2 2 Functions 1 System clock select The system clock is selected under program control from three types of clocks generated by the main clock oscillator subclock oscillator and RC oscillator 2 System clock frequency division Frequency of the oscillator clock selected as the system clock is divided and the resultant clock
184. lowing the one in which the transmit control bit TRUN is set to 1 This bit must be cleared with an instruction When performing a continuous transmit operation make sure that this bit is set before each loading of the next transmit data into the transmit data register TBUF When this bit is subsequently cleared the transmit control bit TRUN is automatically set at the end of the transmit operation TRNSIE bit 0 UART1 transmit interrupt request enable control 1 3 21 4 3 1 2 An interrupt request to vector address 003 is generated when this bit and set to 1 UART1 baudrate generator UBR The UART1 baudrate generator is an 8 bit register that sets the transfer rate of the UARTI transfer The counter for the baudrate generator is initialized when a UARTI transfer operation is stopped or terminated UCONO RECRUN UCON1 TRUN 0 Do not change the transfer rate in the middle of a UARTI transfer operation The UARTI will not function normally if the baudrate is changed during operation Always make sure that the transfer operation has ended before changing the baudrate The same transfer rate is used when both transmit and receive operations are to be performed at the same time This also holds true when continuous transmit and receive operations are to be performed at the same time When UCONO UBRSEL 0 6 2048 TUBR UBR value 1 x i Tcyc value range X to When UCONO U
185. ls the additional pulses of PWMO PWMOL is assigned bits 7 to 4 and all of its low order 4 bits are set to 1 when read When the PWMO control bit PWMOC FE24 bit 2 is set to 0 the output of PWMO ternary can be controlled using bits 7 to 4 of PWMOL PWMO compare register PWMOH 8 bit register This register controls the fundamental wave pulse width of PWMO When bits 7 to 4 of PWMOL are all fixed at 0 PWMO can be used as period programmable 8 bit PWM that is controlled by PWMOH PWM compare register L PWMT1L 4 bit register This register controls the additional pulses of PWMI PWMIL is assigned bits 7 to 4 and all of its low order 4 bits are set to 1 when read When the PWMI control bit PWMOC FE24 bit 3 is set to 0 the output of PWMI ternary can be controlled using bits 7 to 4 of PWMIL PWM compare register PWM1H 8 bit register This register controls the fundamental wave pulse width of PWMI When bits 7 to 4 of PWMIL are all fixed at 0 PWMI can be used as period programmable 8 bit PWM that is controlled by PWM1H 01 port input register PWMO1P 2 bit register PWMO data can be read into this register as bit 0 PWMI data can be read into this register as bit 1 3 119 01 3 23 4 Related Registers 3 23 4 1 PWMO0 PWM1 control register PWMOC 8 bit register 1 This register controls the operation and interrupts of PWMO and PWM 1 Address Initial Value R W BIT7 BIT6 BIT5 B
186. m oon Erose oikees xran RGSTOP CESTOP Lr wi OE eric ran ro ToLoNG FE11 0000 0000 TOPRR pom E TOPRR7 TOPRR6 TOPRR5 TOPRR4 TOPRR3 TOPRR2 TORT TOPRRO 0000 0000 ms mua mu mu T5 _ Les O y o ne 0000 0000 Fes 900 WT TR TONO FETE UC R Timer o camre resser Toca Tocas Tocata Toca s TOONLI TOCALI TocaLo FETT R Timer 0 capture resister Toome Tocas Tocana Toca Tocant Tocano 0000 0000 rts 000000 re O TILPRE TILPRGE TILRCI TILPROO rA 0000 000 R TL mu Tus ms ma m nu Fi 0000 0000 R m8 mm rm nes nm nm mmo ric 0000 0000 mu Tu Tum rus rus rio TURO rip 000 w rw o O rw nme ri Address Initial Value R W 10875400 R
187. m the P72 INT2 TOIN and P73 INT3 TOIN pins TOH serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P72 INT2 TOIN TOLCP and P20 to P27 timer OL capture input pins The contents of TOL are captured into the capture register TOCA1L on external input detection signals from the P20 INTS T1IN TOLCP TOHCP INTO TOLCPI pin 3 34 LC875W00 Chapter The contents of are captured into the capture register TOCAH on external input detection signals from the P71 INT1 TOHCP P73 INT3 TOIN TOHCP and P20 to P27 timer OH capture input pins The contents of are captured into the capture register TOCA1H on external input detection signals from the P24 INTS T1IN TOLCP TOHCP INT7 TOHCPI pin TOL period TOLR 1 TOH period TOHR 1 x TOPRR 1 x Tcyc 3 Mode 2 16 bit programmable timer with a programmable prescaler with two 16 bit capture registers Timer counter 0 serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from the P71 INTI TOHCP P73 INT3 TOIN and P20 to P27 timer OH capture input pins The
188. must be cleared with an instruction as it is not cleared automatically 3 20 LC875W00 Chapter INTSIE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated 2 bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P72 Pin Data No one detected INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when P72 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P72 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P72 it is recommended that P72 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 5 8 4 Input signal select register ISL 1 This register is an 8 bit register that cont
189. n results may not be obtained because of noise interferences if the state of port outputs is changing To minimize the adverse influences of noise interferences it is necessary to keep the line resistance across the power supply and the VDD pins of the microcontroller at minimum This should be kept in mind when designing an application circuit 3 139 ADC 3 140 LC875W00 Chapter 4 4 Control Functions 4 1 4 1 1 Interrupt Function Overview This series of microcontrollers has the capability to control three levels of multiple interrupts 1 low level L high level H and highest level X The master interrupt enable and interrupt priority control registers are used to enable or disable interrupts and determine the priority of interrupts The interrupt source flag register shows a list of interrupt source flags that can be examined to identify the interrupt source associated with the vector address that is used at the time of an interrupt 4 1 2 Functions 1 2 3 4 5 Interrupt processing Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 When the microcontroller receives an interrupt request from a peripheral module it determines the interrupt level priority and interrupt enable status of the interrupt If the interrupt request is legitimate for processing the microcontroller saves
190. n the bit PCnDDR is set to 0 2 PCn is configured as an input pin with a pull up resistor when the bit PCnDDR is set to 0 and port C data latch bit PCn is set to 1 3 28 LC875W00 Chapter Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE71 0000 0000 R W PCDDR PC7DDR PC6DDR PCSDDR PC4DDR PC3DDR PC2DDR PCIDDR PCODDR Register Data Port PCn State Internal Pull up PCnDDR Input Resistor Enabled OFF 0 0 ol Enabled Internal pull up resistor Enabled High open CMOS N channel open drain 3 9 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 9 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port C retains the state that is established when HALT or HOLD mode is entered 3 29 Port E 3 10 Port E 3 10 1 Overview Port E is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a control register and a control circuit Control of the input output signal direction is accomplished by the control register in 2 bit units 3 10 2 Functions 1 Input output port 8 bits PEO to PE7 The port E data latch PE FE28 is used to control the port output data and the port E control register PEFCR FE29 to control the I O direction of port data Each port bit is provided with a programma
191. n the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts Vector Selectable Level Interrupt Sources 00003H XorL INTO 0 e Priority levels X gt When interrupts of the same level occur at the same time the interrupt with the smallest vector address is given priority 7 Interrupt source list IFLGR register FE05 is used to show list of interrupt source flags related to the vector address that is used at the time of an interrupt 8 It is necessary to manipulate the following special function registers to show a list of interrupt sources to enable interrupt and to specify their priority IE IP Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 05 1111 1111 R IFLGR IFLGR7 IFLGR6 IFLGRS5 IFLGR4 IFLGR3 IFLGR2 IFLGRI IFLGRO Feos 0000 ww xro HFLG LFLG xcnro Fe09 0000 0000 rw was tras mse ps3 P wip IPIS 4 1 3 X Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 This register enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 Theregister selects the level L or X of interrupts to vector add
192. nce voltage generator circuit control register DACR The reference voltage output ranges from VDD to VSS 3 25 4 Related Registers 3 25 4 4 AD converter control register ADCR 1 Thisregister is an 8 bit register that controls the operation of the AD converter Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE60 0000 0000 R W ADCR ADCR7 ADCR6 ADCRS ADCR4 ADCR3 ADCR2 ADCRI ADCRO ADCR7 bit 7 ADCR6 bit 6 AD e eM ADCRS bit 5 conversion input signal select ADCRA bit 4 These 4 bits are used to select the signal to be subject to AD conversion 3 135 ADC ADCR7 ADCR6 ADCR5 ADCR4 Signal Input pin 0 0 0 0 P80 ANO o 9 9 0 SUS o 9 34 9 AN Zo 9 3 4 aw S rum et wave 1 1 P87 AN7 Zo 1 Fas 3 9 9 Zo 1 3 ADCR3 bit 3 AD converter operation control This bit starts 1 and stops 0 AD conversion processing AD conversion starts when it is set to 1 This bit is automatically reset when AD conversion terminates A conversion time of 32 64 128 or 256 Tcyc is required to complete an AD conversion process The conversion time must be selected using ADCR2 AD conversion stops when this bit is set to 0 Correct conversion results cannot be obtained if this bit is cleared during AD conversion processing This bit must never be cleared while AD conversion
193. ncrements common to PWMO High level pulse width 0 to Fundamental wave period 1 programmable in 1 increments PWMI Fundamental wave Additional pulse PWM mode Fundamental wave period 61256 Teye programmable in 16 increments common to PWMO Overall period Fndamental wave period x 16 High level pulse width 0 to Overall period 1 programmable in 1 increments Interrupt generation Interrupt requests are generated at the intervals equal to the overall PWM period if the interrupt request enable bit is set It is necessary to manipulate the following special function registers to control PWMO and PWMI PWMOL PWMOH PWMIL PWMIH PWMOC PWMOIP Initial Value BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE20 0000 HHHH PWMOL PWMOL3 PWMOL2 PWMOLI PWMOLO wmon pwmona vans runi ooo mw pwns ewm pwani ewo _ ms e l on ewon 3 118 3 23 3 3 2 3 23 3 4 2 3 3 23 3 5 2 3 23 3 6 2 LC875W00 Chapter 3 Circuit Configuration PWMO0 PWM1 control register PWMOC 8 bit register This register controls the operation and interrupts of PWMO and PWMI PWMO compare register L PWMOL 4 bit register This register contro
194. nd PWM4OV are set to 1 3 24 4 PWMMH compare register L PWMAL 4 bit register 1 Thisregister controls the additional pulses of PWMA 2 PWMAL is assigned bits 7 to 4 and all of its low order 4 bits are set to 1 when read Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE72 0000 HHHH PWM4L PWM4L3 PWM4L2 PWM4L1 PWM4L0 3 24 4 3 PWM4 compare register PWM4H 8 bit register 1 Thisregister controls the fundamental wave pulse width of PWMA Fundamental wave pulse width Value represented by PWM4H7 to x 1 2 When bits 7 to 4 of PWMAL are all fixed at 0 PWM4 be used period programmable 8 bit PWM that is controlled by PWM4H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE73 0000 0000 PWM4H PWM4H7 PWM4H6 PWM4H5 PWM4H4 PWM4H3 PWM4H2 PWMAHO 3 128 LC875W00 Chapter 3 3 24 4 4 PWM5 compare register L PWM5L 4 bit register 1 This register controls the additional pulses of PWM5 2 PWMSL is assigned bits 7 to 4 and all of its low order 4 bits set to when read Address Initial Value R W BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE74 0000 HHHH PWMSL PWMSL3 PWMSL2 PWM5L1 PWMSLO 3 24 4 5 PWM5 compare register PWM5H 8 bit register 1 This register controls the fundamental wave pulse width of PWMS Fundamen
195. nd a continuous transmit operation clear UCONI TRNSIE while not clearing UCONI TEPTY and exit the interrupt in the step 3 processing and the transmit operation that is being performed at that time will be the last transmit operation that the UARTI executes 3 105 UART1 3 21 5 3 Setting up the UART1 communications ports When using port 3 as the UARTI port 1 Setting up the receive port P33 Register Data Receive Port P33 Internal Pull up P33 P33DDR State Resistor 0 0 Input Off a E The UARTI receives no data normally if P33DDR is set to 1 2 Setting up the transmit port P32 Register Data Internal Pull up Transmit Port P32 State Resistor CMOS output Off N channel open drain output N channel open drain output The UARTI transmits no data if P32DDR is set to 1 3 21 6 UART1 HALT Mode Operation 3 21 6 1 Receive mode 1 A UART receive mode operation is enabled in HALT mode If UCONO STRDET is set to 1 when the microcontroller enters HALT mode the receive processing will be restarted if data that sets UCONO RECRUN is input at the end of a receive operation 2 HALT mode can be released using the UART receive interrupt 3 21 6 2 Transmit mode 1 A UART transmit mode operation is enabled in HALT mode If the continuous transmit mode is specified when the microcontroller enters HALT mode the UARTI will restart transmit processing after terminating a transmit operation Since UC
196. ndition comes just after the event SILREC must be set to 1 before exiting the interrupt SIIREC is for detecting a start condition and is not set automatically It may disturb the transmission of address from the master if there is an unexpected restart just after slave transmission when SIIREC is not set to 1 by instruction 4e When a stop condition is detected an interrupt is generated and processing returns 2 in step 7 8 Terminating communication e Set SILREC Return to in step 6 to cause communication to automatically terminate To force communication to termination clear SITRUN and SIIEND release the clock port e An interrupt occurs when a stop condition is detected Then clear 5 and SILOVR and return to 2 in step 4 3 19 5 Related Registers 3 19 5 1 5101 control register SCON1 1 This register is an 8 bit register that controls the operation and interrupts of SIO1 Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 SCONI SIIMI SIIMO SILRUN SIIREC SIIDIR SHOVR SIIIE SI1M1 bit 7 SIO1 mode control SI1MO bit 6 SIO1 mode control Table 3 19 2 SIO1 Operating Modes Mode 511 1 SI1M0 Operating Mode Synchronous 8 bit SIO 1 UART 1 stop bit no parity BRE RN NEL ee 3 i o SI1RUN bit 5 SIO1 operation flag 1 A 1 in this bit indicates that SIO1 is running
197. nsmission mode is 2 see Figure 3 22 4 Performs continuous reception of serial data whose data length and transfer rate vary on each receive operation The transfer rate of the UART2 is programmable within the range of 8 to 208 64 8192 3 to 73 The transmit data is read from the transmit data register TBUF2 and the receive data is stored in the receive data register RBUF2 3 Interrupt generation Interrupt requests are generated at the beginning of transmit operation and at the end receive operation if the interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control the asynchronous serial interface 2 UART2 e UCON2 UCON3 UBR2 TBUF2 RBUF2 PSDDR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEE8 0000 0000 R W UCON2 URBSEL2 STRDET2 RECRUN2 STPERR2 U2B3 RBIT82 RECEND2 RECIE2 U2BRG U2BRG2 T2BUF3 T2BUF1 U2BRGT U2BRG T2BUF3 T2BUFI 3 107 Circuit Configuration UART2 control register 2 UCON2 8 bit register This register controls the receive operation and interrupts for the UART2 UART2 control register UCON3 8 bit register This register controls the transmit operation data length and interrupts for the UART2 UART2 baudrate generator UBR2 8 bit reload counter The UART2 baudrate generator is a reload counter for generating internal
198. ntrol LC875W00 Chapter 3 Table 3 20 2 SIO2 Communication Data Starting Addresses Value of SCTR2 bits 7 to 5 Data starting address 01A0H 01COH SCTR24 bit 4 5102 communication data bytes setting SCTR23 bit 3 SIO2 communication data bytes setting SCTR22 bit 2 SIO2 communication data bytes setting SCTR21 bit 1 SIO2 communication data bytes setting 5 20 bit 0 SIO2 communication data bytes setting Communication data bytes Value of SCTR2 bits 4 to 0 1 3 20 5 4 SIO2 port control register SIPPC 8 bit register 1 This register controls the port for the 5102 interface 2 Thisregister can also serve as a general purpose port 3 When this register is read with an instruction data from pins 5 2 0 to SI2P3 is read into bits 0 to 3 Bits 4 to 7 are loaded with bits 4 to 7 of the register SIDPC If SI2PC FE3B is manipulated using the NOTI CLR1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the pins as bits 0 to 3 4 SI2P data can always be read regardless of the I O state of port 5 is designated as N channel open drain output only during 5102 output processing It is designated CMOS output when SI2P1C is set to 1 6 There is no user option for port SI2P Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3B 0000 0000 R W SI2PC SDP3C SDP2C SDPIC SI2POC SI2P3D SDP2D SDP
199. o 2048 levels stack is allocated in RAM High speed multiplication division instructions e 16 bits x 8 bits 5 Tcyc execution time 24 bits x 16 bits 12 Tcyc execution time e 16 bits 8 bits 8 Tcyc execution time e 24 bits 16 bits 12 Tcyc execution time Oscillator circuits e RC oscillator circuit internal For system clock e CF oscillator circuit For system clock Rf built in e Crystal oscillator circuit For low speed system clock 1 3 e Internal reset function Power on reset POR function 1 resets the system at the time when the power is turned on System clock divider function 1 Capable of running on low current 2 The minimum instruction cycle time can be selected from among 250 ns 500 ns 1 0 us 2 0 us 4 0 us 8 0us 16 0 us 32 0 us and 64 0 us at a main clock rate of 12 MHz Standby function HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation is not halted automatically 2 Released by system reset or occurrence of an interrupt e HOLD mode Suspends instruction execution and operation of the peripheral circuits 1 CF RC and crystal oscillators automatically stop operation 2 There are three ways of releasing HOLD mode lt 1 gt Setting the reset pin to the low level 2 Setting at least one of the pins INTO INT1 INT2 INT4 and INTS to the specified level lt 3 gt Establishing an interrup
200. oad counter for generating internal clocks It can generate clocks at intervals of n 1 x or n 1 x n 1 to 255 Note n 0 is inhibited UART1 transmit data register 8 bit register This register is an 8 bit register for storing the data to be transmitted UART1 transmit shift register TSFT 11 bit shift register This register is used to send serial data via the UART1 This register cannot be accessed directly with an instruction It must be accessed through the transmit data register TBUF UART1 receive data register RBUF 8 bit register This register is an 8 bit register for storing receive data UART1 receive shift register RSFT 11 bit shift register This register is used to receive serial data via the UARTI This register cannot be accessed directly with an instruction It must be accessed through the receive data register RBUF 3 97 UART1 Data input LSB first Start bit Note The position of the start bit differs depending on the bit length a bit to be transferred 11 bit shift register RSFT a ma At end of receive operation RSFT gt RBUF RBUF FED4h Data bit 8 9 bit data receive mode only Clock generator circuit Stop bit error flag Baudrate Falling edge detector P generator At beginning of circuit lis receive zd UBR FED2h E E S UCONO FEDOh Interrupt request Note Bit 3 of P3DDR at FE4D must be
201. of the internal RC oscillator immediately after the microcontroller exits X tal HOLD mode is determined by the state of this bit 6 This bit is not cleared when the microcontroller enters HALT mode The state of the internal RC oscillator is determined by the state of this bit 4 10 LC875W00 Chapter 4 CFSTOP bit 0 Main clock oscillator control 1 Setting this bit to 1 stops the oscillation of the main clock 2 Setting this bit to 0 starts the oscillation of the main clock oscillator circuit 3 When reset occurs or when HOLD mode is entered this bit is cleared and the main clock oscillator circuit is enabled for oscillation 4 This bit is cleared when the microcontroller enters HOLD mode main clock oscillation is stopped Immediately after the microcontroller exits HOLD mode the main clock oscillator circuit is activated 5 The state of this bit remains unchanged when the microcontroller enters X tal HOLD mode main clock oscillation is stopped The state of the main clock oscillator circuit immediately after the microcontroller exits X tal HOLD mode is determined by the state of this bit 6 This bit 1s not cleared when the microcontroller enters HALT mode The state of the main clock oscillator circuit 1s determined by the state of this bit 4 243 XT2 general purpose port output control register XT2PC 8 bit register 1 This register 1s an 8 bit register that controls the general purpose output N channel open drain typ
202. ol circuit Control of the input output signal direction is accomplished by the data direction register in l bit units Port 3 can also be used as a PWMA PWMS output port or a UART1 UART2 I O port As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 4 2 Functions 1 Input output port 7 bits P30 to P36 The port 3 data latch P3 FE4C is used to control the port output data and the port 3 data direction register P3DDR FE4D is used to control the I O direction of the port data Each port is provided with a programmable pull up resistor 2 Multiplexed functions e P30 is also used as PWMA output P31 as PWMS output P32 and P33 as UARTI I O and P34 and P35 as UART2 I O The functions are described in the corresponding chapters Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4C 000 0000 R W P3 P36 P35 P34 P33 P32 P31 P30 FED rw 3DDR PS6DDR P3SDDR P34DDR P33DDR P32DDR P3IDDR P30DDR 3 4 3 Related Registers 3 4 8 1 Port 3 data latch P3 1 The port3 data latch is a 7 bit register for controlling the port 3 output data and pull up resistors 2 When this register is read with an instruction data at pins P30 to P36 is read in If the P3 FE4C is manipulated using the NOTI CLR1 SET1 DBZ DBN
203. ols port 0 multiplexed pin outputs Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 00HH 0000 R W POFCR T7OE T6OE CLKOEN CKODV2 CKODV1 CKODVO T7OE bit 7 This bit controls the output data of pin P07 It is disabled when 07 is in input mode When P07 is in output mode 0 Outputs the value of the port data latch 1 Outputs the OR of the waveform that toggles at the period of timer 7 and the value of the port data latch T6OE bit 6 This bit controls the output data of pin P06 It is disabled when P06 is in input mode When P06 is in output mode 0 Outputs the value of the port data latch 1 Outputs the OR of the waveform that toggles at the period of timer 6 and the value of the port data latch CLKOEN bit 3 This bit controls the output data of pin POS It is disabled when POS is in input mode When 05 is in output mode 0 Outputs the value of the port data latch 1 Outputs the OR of the system clock output and the value the port data latch CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 These bits define the frequency of the system clock to be output to P05 000 Frequency of source oscillator selected as system clock 001 1 2 of frequency of source oscillator selected as system clock 010 1 4 of frequency of source oscillator selected as system clock 011 1 8 of frequency of source oscillator selected as system clock 100 1 16 of frequency of source oscillator selected
204. on next page 1 7 Pin functions continued Pin Port 3 e 7 bit I O port P30 to P36 I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P30 PWMA output P31 PWMS output P32 UARTI transmit P33 UARTI receive P34 UART2 transmit P35 UART2 receive Port 7 4 bit I O port P70 to P73 I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P70 INTO input HOLD release input timer OL capture input watchdog timer output P71 INTI input HOLD release input timer OH capture input P72 INT2 input HOLD release input timer 0 event input timer OL capture input P73 INT3 input with noise filter timer 0 event input timer OH capture input ANS P70 AN9 P71 AD converter input port Interrupt acknowledge type Rising amp L level Falling INTO O Description Ew 9 9 pee Port 8 8 bit I O port I O specifiable in 1 bit units Multiplexed pin functions P80 to P87 AD converter input port P80 to P87 Port A 6 bit I O port I O specifiable in 1 bit units EATER Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions PA3 to PA5 AD converter input port Port B IO 8 bit I O port Yes PBO to PB7 O specif
205. operations are to be performed at the same time TDDR bit 5 UART1 transmit port output control 1 When this bit is set to 1 the transmit data is placed at the transmit port P32 No transmit data is output if bit 2 of P3DDR at FE4D is set to 1 2 When this bit is set to 0 no transmit data is placed at the transmit port P32 The transmit port is placed in high open CMOS N channel open drain mode if this bit is set to 1 when the UART1 has stopped a transmit operation TRUN 0 This bit must always be set to 0 when the UART transmit function is not to be used TCMOS bit 4 UART1 transmit port output type control 1 When this bit is set to 1 the output type of the transmit port P32 is set to CMOS 2 When this bit is set to 0 the output type of the transmit port P32 is set to N channel open drain 3 101 UART1 8 7 BIT bit 3 UART1 transfer data length control D This bit and 8 9 BIT bit 6 are used to control the transfer data length of the UARTI TBITS8 bit 2 UART1 transmit data bit 8 storage bit 1 This bit stores bit 8 of the transmit data when the data length is set to 9 bits 8 9BIT 1 and 8 7BIT 0 bit 1 UART1 transmit shift register transfer flag 1 2 This bit is set when the data transfer from the transmit data register TBUF to the transmit shift register TSFT ends at the beginning of the transmit operation This bit is set in the cycle Tcyc fol
206. or output 3 Port 7 data can always be read regardless of the I O state of the port Address Initial value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESC 0000 0000 P73DDR P72DDR P71DDR P70DDR P73DT P72DT P7IDT P70DT 3 25 4 6 Port A registers PA PADDR 1 These registers are 8 bit registers that control the output data pull up resistors and I O direction of port A in 1 bit units 2 When using port A for analog input the pins used for input must be set to output disable 3 Port A data can always be read regardless of the I O state of the port Address Initial value BIT4 FE68 0000 0000 PA4 PAO weowo ww PA4DDR 3 138 3 25 4 7 2 3 4 5 6 7 8 9 10 LC875W00 Chapter Hints on the use of the ADC Control of reference voltage generation and selection of the conversion time and analog input channel must be accomplished before starting a conversion process The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest edition of SANYO Semiconductor Data Sheet to select an appropriate conversion time Setting ADCR3 to 0 while conversion is in progress will stop the conversion function When conversion is finished the AD conversion end flag ADCR1 is set and at the same time the AD converter operation control bit ADCR3 is reset The end of conversion condition can
207. os I5SL1 bit 5 INT5 pin function select 15510 bit 4 INT5 pin function select When the data change specified in the external interrupt 4 5 control register I45CR is given to the pin that is assigned to INTS timer 1 count clock input and timer 0 capture signal are generated 15511 15510 Function Other Than INT5 Interrupt 0 0 None Timer 1 count clock input 1 0 Timer OL capture signal input Timer OH capture signal input 14513 bit 3 INT4 pin select 14512 bit 2 INT4 pin select 0 1 mm 1 mm I I J 14511 bit 1 INT4 pin function select 14510 bit 0 INT4 pin function select When the data change specified in the external interrupt 4 5 control register I45CR is given to the pin that is assigned to INT4 timer 1 count clock input and timer 0 capture signal are generated 14511 14510 Function Other Than INT4 Interrupt 0 0 None Timer 1 count clock input o0 1 a ONE Timer OL capture signal input Timer OH capture signal input Notes 1 If timer OL capture signal input or timer OH capture signal input is specified for INT4 or INTS together with port 7 the signal from port 7 is ignored 2 If INT4 and INT5 are specified together with timer I count clock input timer OL capture signal input or timer OH capture signal input both interrupts are accepted If both INT4 and INTS events occur at the same time however only one event
208. ot to be used CFI Ceramic resonator input pin CF2 Ceramic resonator output pin 1 9 1 6 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into an input port even if it is in output mode Options Selected in Units of Output Type Pull up Resistor POO to P07 1 bit 0 P71 to P73 P80 to P87 Ne PAO to PAS PBO to PB7 CMOS channel open drain CMOS N channel open drain CMOS N channel open drain CMOS N channel open drain N channel open drain CMOS N channel open drain MOS N channel open drain CMOS Programmable Note 1 No Programmable Programmable Programmable N channel open drain Programmable N CMOS Programmable PCO to PC7 1 bit E 4 N channel open drain Programmable PEO to PE7 No Programmable Programmable PFO to PF7 No SDPO 5 2 2 SI2P3 No li MM CMOS CMOS when selected as normal port N channel open drain when selected as SIO2 data port No No CMOS No 32 768 kHz crystal resonator output N channel open drain when selected as general purpose output port Note 1 Pull up resistors for port 0 are controlled in 4 bit units POO to 03 04 to 07 LC875W00 Chapter 1 Make the following connection to minimize the noise input to the VD
209. other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter OVORVIOW ewes ite De Dd ie dele 1 1 1 Overview wasanasaanananansessusnasasesesansuscsanansssesenascussuasausensuausesesanansenenanasus 1 1 1 2 Features 1 1 1 3 Pinout BARRRRARASRARARRSRSARARRARARRRSRARARRARARRRRARARRARARRARARARRSRARARRARARRARARARRARARRRRARARE 1 5 1 A System Block Diagram sasanasassasnansuesosasssenssesenanssucsanansssanenanesossansa
210. ounter T7CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 7 period setting register T7R when the interrupt flag T7OV is set 2 When T7CO and T7C1 T67CNT FE78 bits 6 and 7 are set to 0 the timer 7 counter stops at a count value of 0 In the other cases the timer 7 counter continues operation 3 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again 3 16 3 6 Timer 7 prescaler T7PR 6 bit counter 1 This prescaler is used to define the clock period for the timer 7 determined by T7CO and T7C1 T67CNT FE78 bits 6 and 7 Table 3 16 2 Timer 7 Count Clocks T7 Count Clock Timer 7 prescaler and timer counter are in the reset state 3 16 3 7 Timer 7 period setting register T7R 8 bit register 1 Thisregister defines the period of timer 7 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again 3 64 LC875W00 Chapter 3 3 16 4 Related Registers 3 16 4 1 Timer 6 7 control register T67CNT 1 This register is an 8 bit register that controls the operation and interrupts of T6 and T7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 67 7 0 T6CO T70V T7IE T60V T7C1 bit 7 T7 count clock control T7CO bit 6 T7
211. ounter 3 bits NK capture 1 TOL capture 5 Figure 3 13 1 11 bit Counter Block Diagram TOLONG 0 Timer 0 8 bit mode TOL match signal TOL comparison value TOL counter 8 bits TOL capture NK comparison value TOH comparison value TOH counter 8 bits TOH capture TOL match signal NK counter 3 bits NK capture Capture signal Figure 3 13 2 19 bit Counter Block Diagram TOLONG 1 Timer 0 16 bit mode 3 47 3 14 Timer Counter 1 T1 3 14 1 D 2 3 4 3 14 2 2 3 Overview The timer counter 1 T1 incorporated in this series of microcontrollers is a 16 bit timer counter with a prescaler that provides the following four functions Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with toggle output Mode 1 Two channels of 8 bit PWM with an 8 bit prescaler Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output the low order 8 bits may be used as a timer counter with toggle output Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output the low order 8 bits may be used as a PWM Functions Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with toggle output TIL functions as an 8 bit programmable timer counter that counts the number of signals obtained by dividin
212. output operations at the same time 5100 baudrate generator SBRO 8 bit reload counter The SIOO baudrate generator is a reload counter for generating internal clocks It can generate clocks at intervals of n 1 x 2 n 1 to 255 Note n 0 is inhibited Continuous data bit register SCTRO 8 bit register This register controls the bit length of data to be transmitted or received in continuous data transmission reception mode Continuous data transfer control register SWCONO 8 bit register This register controls the suspension and resumption of serial transfers in byte units in continuous data transmission reception mode It allows the application program to read the number of bytes transferred in continuous data transmission reception mode 3 72 LC875W00 Chapter 3 Data input 8 bit shift register i Data LSB first ___ joutput 1 SIOO output control P10 eese oe enn ed rts Clock P10 output control 4 MSB first SBUFO FE31h 5100 output control P11 P11 port latch P11 output control Clock generator circuit MSB LSB first select P12 port latch P12 output control Baudrate generator Serial transfer end flag SBRO FE32h 6100 overrun flag SCONO FE30h Interrupt request Figure 3 18 1 5100 Synchronous 8 bit Serial I O Block Diagram SIOCTR 0 3 73 5100 Data input 8 bit shift register LSB first
213. peration and interrupts of TIL and Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHCMP TIHIE TILCMP TILIE T1HRUN bit 7 count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of has the same value as When this bit is set to 1 timer 1 high byte performs the required counting operation T1LRUN bit 6 T1L count control When this bit is set to 0 timer 1 low byte TIL stops on a count value of 0 The match buffer register of has the same value as TILR When this bit is set to 1 timer 1 low byte T1L performs the required counting operation T1LONG bit 5 Timer 1 bit length select When this bit is set to 0 timer 1 higher and low order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit timer since the timer 1 high byte T1H counts up at the period of the timer 1 low byte TIL Independent match signals are generated from and TIL when their count value matches the contents of the corresponding match buffer register regardless of the value of this bit T1PWM bit 4 T1 output mode select This bit and TILONG bit 5 determine the output mode of TI TIPWMH and TIPWML as summarized in Table 3 14 1 Table 3 14 1 Timer
214. pt request to vector address 004BH is generated when this bit and T5OV are set to 1 bit 1 T4 overflow flag This flag is set at the interval of timer 4 period when timer 4 is running This flag must be cleared with an instruction T4IE bit 0 T4 interrupt request enable control An interrupt request to vector address 004BH is generated when this bit and are set to 1 3 15 4 2 Timer 4 period setting register T4R 1 This register is an 8 bit register for defining the period of timer 4 Timer 4 period T4R value 1 x Timer 4 prescaler value 4 16 or 64 Tcyc 2 When data is written into T4R while timer 4 is running both the timer 4 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3E 0000 0000 R W T4R T4R7 T4R6 T4R5 T4R4 T4R3 T4R2 T4R1 0 14 T5 3 15 4 3 Timer 5 period setting register T5R 1 This register is an 8 bit register for defining the period of timer 5 Timer 5 period value 1 x Timer 5 prescaler value 4 16 or 64 Tcyc 2 When data is written into TSR while timer 5 is running both the timer 5 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3F 0000 0000 R W T5R T5R7 T5R6 5 5 TSR4 T5R3 T5R2 5 TSRO 3 62 LC875W00 Chapter 3 3 16 Timers 6 and 7 T6 T7 3 16 1 Overview The timer 6 T6 and tim
215. put of pins PE7 and PE6 PESELS bit 6 Fixed bit This bit must always be set to 0 PEDDR2 bit 5 PE5 PE4 I O control A lorO in this bit controls the output CMOS or input of pins PES and PESEL2 bit 4 Fixed bit This bit must always be set to 0 bit 3 PE2 I O control A lorO in this bit controls the output CMOS or input of pins and 2 bit 2 Fixed bit This bit must always be set to 0 PEDDRO bit 1 PE1 PEO I O control A 1 or 0 in this bit controls the output CMOS or input of pins PEI and PEO PESELO bit 0 Fixed bit This bit must always be set to 0 LC875W00 Chapter Caution The output input control of the PE pins cannot be set up properly if the PESELn is set to 1 3 10 4 HALT and HOLD Mode Operation When in HALT or HOLD mode port E retains the state that is established when HALT or HOLD mode is entered 3 31 Port F 3 11 Port F 3 11 1 Overview Port F is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a control register and a control circuit Control of the input output signal direction is accomplished by the control register in 2 bit units 3 11 2 Functions 1 Input output port 8 bits PFO to PF7 The port F data latch PF FF2A is used to control the port output data and the port F control register PFFCR FE2B to control the I O direction of port data Each port bit is p
216. r 3 3 Port 2 3 3 1 Overview Port 2 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished by the data direction register in 1 bit units Port 2 can be used as an input port for external interrupts It can also be used as an input port for the timer 1 count clock input timer 0 capture signal input timer 0 capture 1 signal input and HOLD mode release signal input As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 3 2 Functions 1 Input output port 8 bits P20 to P27 The port 2 data latch P2 FE48 is used to control the port output data and the port 2 data direction register P2DDR FE49 is used to control the I O direction of the port data Each port bit is provided with a programmable pull up resistor 2 Interrupt input pin function The port INT4 selected from P20 to P23 and the port 5 selected from P24 to P27 are provided with a pin interrupt function This function detects a low edge a high edge or both edges and sets the interrupt flag These two selected ports can also be used as timer 1 count clock input and timer 0 capture signal input e P20 INT6 and P24 INT7 are provided with a pin interrupt function
217. r A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte 2 The match buffer register is updated as follows e When it is inactive TIHRUN O the match register matches TIHR e When it is active TIHRUN 1 the match buffer register is loaded with the contents of T1HR when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEID 0000 0000 R W TIHR 7 TIHR6 5 4 2 0 3 57 Match buffer register value Modes 0 2 E 1 Match signal Interrupt flag set T1PWML T1PWM FFH Counter value Mode 1 TiL T1H Match signal LL o o n 3 T c 6 R 4 m 5 gt 5 Match buffer register value Mode 3 E Match signal Interrupt flag set T1PWMH FFH Counter value I 5 o 3 c c 5 2 per d o o gt 5 1 2 LC875W00 Chapter 3 3 15 Timers 4 and 5 4 T5 3 15 1 Overview The timer 4 T4 and timer 5 T5 incorporated in this series of microcontrollers are 8 bit timers with two independently controlled 6 bit prescalers 3 15 2 Functions 1 Timer 4 T4 Timer 4 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock T4 period T4R
218. r INT5 is specified as the timer 1 count clock input Note 2 TIL will not run normally if INT4 or INT5 is specified as the timer 1 count clock input when T1PWM 1 When TIPWM 1 do not specify INT4 or INT5 as the timer 1 count clock input 3 Prescaler count Determined by the TIPRC value The count clock for T1L is generated at the intervals determined by the prescaler count TILPRE TILPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count T 3 50 LC875W00 Chapter 3 3 14 3 4 Timer 1 prescaler high byte 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock Varies with operating mode Mode T1LONG T1PWM T1H Prescaler Count Clock 2 Tcyc 0 0 0 La lum 3 3 o 3 Prescaler count Determined by TIPRC value The count clock for T1H is generated at the intervals determined by the prescaler count T1HPRE T1HPRC2 T1HPRCO T1H Prescaler Count 4 Reset When the timer 1 stops operation or a T1H reset signal is generated 3 14 3 5 Timer 1 low byte T1L 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock TIL prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register
219. r N channel OD selectable in 1 bit units AII 6 LC875W00 APPENDIX II Bus P7 bits 3 1 P7 5 bits 7 5 HALT HOLD o m P7 FE5C bit 0 D Q a Pin lt P70 AD input INTO P7 bit 4 D Q from watchdog timer W P7 P73 P71 AD input R P7 Tmo Port 7 Pins Block Diagram Option None 7 Port Block Diagrams HE x Noise fitter filter m pe S Timer OH capture signal E gt S Timer 0 clock input Int request to L vector 00013 I23CR FE5E Cet Int request to vector 0001B T L INT2 L S Timer OL capture signal E L level Int request to vector 00003 101CR FESD Int request to vector 0000B INTO H level L level Port 7 Interrupt Block Diagram Option None 8 LC875W00 APPENDIX II P87 P80 AD input Port 8 AD pins Block Diagram Option None PA FE68 bits 5 0 PAS PAO PADDR FE69 bits 5 0 W PADDR R PADDR Port A Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units 9 Port Block Diagrams PB7 PBO R PB W PBDDR R PBDDR Port B Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units PC FE70 W PC PC7 PCO R PC W PCDDR R PCDDR Port C Block Diagram Option Output type CMOS or N channel OD selec
220. r contains for example FE02H it designates the C register Example When R3 contains 123H RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator L1 STW R3 Transfers the contents of BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FEO02H and the C register contains 1 the address register 2 1 FEO1H is designated Examples When R3 contains 123H and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator Ll STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of RAM address 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 C Ll Decrements the contents of RAM address 125H by 1
221. resses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 This register selects the level or L of interrupts to vector addresses 00013H to 0004BH 4 1 3 8 Interrupt source flag register IFLGR 8 bit register 1 This register shows a list of interrupt source flags related to the vector address that is used at the time of an interrupt LC875W00 Chapter 4 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 1 This register is a 6 bit register for controlling the interrupts Bits 6 to 4 are read only Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 8 0000 00 IE IE7 XFLG HFLG LFLG XCNTI XCNTO IE7 bit 7 H L level interrupt enable disable control e A in this bit enables H and L level interrupt requests to be accepted A 0 in this bit disables H and L level interrupt request to be accepted X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt
222. ring the results of AD conversion 2 Since data in this register is not established during AD conversion the conversion results must be read only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE61 0000 0000 R ADRR ADRR7 ADRR6 ADRR5 ADRR4 ADRR2 ADRRI ADRRO 3 25 4 4 Port 8 register P8 1 Thisregister is an 8 bit register that controls the I O of port 8 2 When this register is read with an instruction data from pins P80 to P87 is read into bits O to 7 If the P8 FE61 is manipulated using the NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the port pins 3 Port 8 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE63 1111 1111 R W P8 P87 P86 P85 P84 P83 P82 P81 P80 P87 to P80 bits 7 to 0 Pins P87 to P80 I O control 1 in these bits places the corresponding port 8 pin into input mode in which case the can be used to receive an ordinary input signal or analog input signal When these bits are set to 0 the corresponding pins are set to the low level 3 25 4 5 Port 7 register P7 1 Thisregister is an 8 bit register that controls the I O operation and pull up resistors of port 7 2 When port 7 is to be used for analog inputs the pins to be used must be disabled f
223. riods Example 1 PWM compare register H PWMH 00 H e PWM compare register L PWML 0OtoF H P1 period Fundamental Fundamental Fundamental X Fundamental Fundamental wave period wave period 1 wave period 2 wave period 13 wave period 14 wave period 15 Fundamental 0 if 2 3 4 15 6 7 8 signal PWMH PWML 000 PWMH PWML 001 PWMH PWML 002 PWMH PWML 003 PWMH PWML 004 PWMH PWML 005 PWMH PWML 006 PWMH PWML 007 PWMH PWML 008 PWMH PWML 009 PWMH PWML 00A PWMH PWML 00B PWMH PWML 00C PWMH PWML 00D PWMH PWML 00E PWMH i i PWML 00F LA ANANA A 3 123 PWMO1 How pulses are added to fundamental wave periods e PWM compare register H PWMH 01 H e PWM compare register L PWML OtoF H i Overall period n Fundamental Fundamental Fundamental Fundamental Fundamental Fundamental wave period wave period 1 wave period2 wave period 13 wave period 14 wave period 15 Fundamental penod 0 signal PM TUBES ENT EET NN RR RR A EN RN PWML 010 LL IL LLL LLL Es ME Ke no TS pose S SEE 280225 PWML 0 dC de LIE EE s 02 L aa ao La
224. rols the timer 0 input noise filter time constant buzzer output and base timer clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer capture signal input port select This bit selects the timer OH capture signal input port When this bit is set to 1 a timer OH capture signal is generated when an input that satisfies the INT1 interrupt detection conditions is supplied to P71 If the interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P71 When this bit is set to 0 a timer OH capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73 3 21 Port 7 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When this bit is set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P72 BTIM
225. ronous 8 bit mode SIOO synchronous 8 bit mode processing is enabled in HALT mode HALT mode can be released by an interrupt that is generated during SIOO synchronous 8 bit mode processing Continuous data transmission reception mode SIOO suspends processing immediately before the contents of RAM and SBUFO are exchanged when HALT mode is entered in continuous data transmission reception mode After HALT mode is entered SIOO continues processing until immediately before the contents of the first RAM address and SBUFO are exchanged After HALT mode is released SIOO resumes the suspended processing Since SIOO processing is suspended by HALT mode it is impossible to release HALT mode using a continuous data transmission reception mode SIOO interrupt 3 79 SIO1 3 19 Serial Interface 1 SIO1 3 19 1 Overview The serial interface 1 SIO1 incorporated in this series of microcontrollers provides the following four functions 1 Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system 2 to 512 Tcyc transfer clock 2 Mode 1 Asynchronous serial Half duplex 8 data bits 1 stop bit baudrate of 8 to 2048 Tcyc 3 Mode 2 Bus master start bit 8 data bits 2 to 512 Tcyc transfer clock 4 Mode 3 Bus slave start detection 8 data bits stop detection 3 19 2 Functions 1 Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The period of the internal
226. rovided with a programmable pull up resistor Bits PFO to PF7 are CMOS output port bits Initial Value BIT2 BITO 0000 0000 PF2 PFO 0000 0000 PFFCR PFDDR3 PFSEL3 PFDDR2 PFSEL2 PFDDRI PFSEL1 PFSELO 3 11 3 Related Registers 3 11 3 1 Port F data latch PF 1 The port data latch is an 8 bit register for controlling port output data and pull up resistors 2 When the latched data is 1 the corresponding pin is pulled up by a pull up register regardless of the I O state of the pin 3 When this register is read with an instruction data at pins PFO to PF7 is read in If the PF FE2A is manipulated using the NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 4 Port F data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE2A 0000 0000 R W PF PF7 PF6 PF5 PF4 PF3 PF2 PFO 3 11 3 2 Port F control register PFFCR 1 This register is an 8 bit register that controls the I O direction of the port F data in 2 bit units Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE2B 0000 0000 R W PFFCR PFDDR3 PFSEL3 PFDDR2 PFSEL2 PFDDRI PFSELI PFDDRO PFSELO 3 32 PFDDR3 bit 7 PF7 PF6 I O control A lorO in this bit controls the output CMOS or input of pins PF7 and PF6 PFSELS bit 6
227. rs hardware initialization is also carried out immediately even at power on time The system clock must be switched to the main clock when the main clock gets stabilized The program counter is initialized to 0000 on a reset See Appendix Special Functions Register SFR Map for the initial values of the special function registers SFR lt Notes and precautions gt The stack pointer is initialized to OOOOH Data RAM is never initialized by a reset Consequently note that the contents of RAM are undefined when power is turned on Be sure to set the RES pin to the low level when turning on the CPU Otherwise the CPU will be out of control during the period from power on till the time the RES pin goes to the low level 4 20 LC875W00 Chapter 4 4 5 Watchdog Timer Function 4 5 1 Overview This series of microcontrollers incorporates a watchdog timer that with an external RC circuit detects program runaway conditions The watchdog timer charges the external RC circuit that is connected to the P70 INTO TOLCP pin and when the level at the pin reaches the high level it triggers a reset or interrupt regarding that a program runaway occurred 4 5 2 Functions 1 Detection of a runaway condition A program that discharges the RC circuit periodically needs to be prepared If the program runaways it will not execute instructions that discharge the RC circuit This causes the P potential at the P70 INTO TOLCP pin to the
228. rting address of data transmission reception can be selected from 8 options The period of the internal clock is programmable within the range of 2 to 9 Data communication is carried out on an LSB first basis 2 Interrupt generation An interrupt request is generated at the end of communication when the interrupt request enable bit is set 3 Itis necessary to manipulate the following special function registers to control the serial interface 2 SIO2 e SCON2 SBUF2 SCTR2 SDPC Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE38 0000 0000 R W SCON2 SBR2C2 SBR2CI SBR2CO SI2WRT SDRUN S2OVR SEND SI2TE 3 20 3 Circuit Configuration 3 20 3 1 5102 control register SCON2 8 bit register 1 This register controls the operation and interrupts of 5102 3 20 3 2 SIO2 shift register SBUF2 8 bit shift register 1 Thisregister is used to transmit and receive data through SIO2 3 20 3 3 SIO2 transfer data control register SCTR2 8 bit register 1 This register is used to control the volume in bytes of data to transfer through SIO2 and to select the starting transfer address 3 20 3 4 SIO2 port control register 12 8 bit register 1 This register controls the port for the 5102 interface 2 This port can also serve as a general purpose port 3 91 SIO2 3 20 4 SIO2 Communication Examples 3 20 4 4 Synchronous serial interface 1 Se
229. s Feces FECB 0 eae FECA EL Ca T us Lm peo wes O es rr ras Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 FEDC Hi ree HS HE Hm een NER i 7 0000 0000 HB FEF4 UCON2 W i Tz 24 c a oll Gm EU pm x MESE p pm UcON2 RENE es TPERRZ U2BRG7 U2BRG6 U2BRG5 U2BRG4 U2BRG3 U2BRG2 U2BRG1 U2BRGO T2BUF7 T2BUF6 T2BUF5 T2BUF4 T2BUF3 T2BUF2 T2BUF1 T2BUFO R2BUF7 R2BUF6 R2BUF5 R2BUF4 R2BUF3 R2BUF2 R2BUF R2BUFO pan recu R R LC875W00 APPENDIX I Address Initial Value R W 10875400 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 FEFC Emp puc cc Rea ee E eee m PR xc _ o ie 9 AI 10 LC875W00 APPENDIX II Q d 2 T7OUT PO7 PO FE40 21 2 a bits 7 5 D W PO Q C Nch OD P07 P05 5 lt lt L 441 1 PO 40 bit 4 D CMOS Q or Pin C Nch OD P04
230. s in regista and I67CR FE4Eh need setting r omparator TOLCMP Match buffer register Relaod flag set TOHR TOLR lt i 6 bit programmable counter Figure 3 12 4 Mode Block Diagram TOLONG 1 TOLEXT 1 3 40 LC875W00 Chapter 3 3 12 4 Related Registers 3 12 4 1 Timer counter 0 control register TOCNT 1 This register is an 8 bit register that controls the operation and interrupts of TOL and Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit i
231. s pin reaches the high level a reset or interrupt is generated as specified in the watchdog timer control register WDT To run the program in the normal mode it is necessary to periodically discharge the RC circuit before the voltage at the P70 INTO TOLCP pin reaches the high level clearing the watchdog timer Execute the following instruction to clear the watchdog timer while it is running MOV 55H WDT This instruction turns on the N channel transistor at the P70 INTO TOLCP pin Owing to the pulse stretcher function keeps the transistor on after the MOV instruction 1s executed the capacitor keeps discharging for a period from a minimum of 1920 cycle times to a maximum of 2048 cycle times Detecting a runaway condition Unless the above mentioned instruction is executed periodically the RC circuit keeps charging because the watchdog timer is not cleared As charging proceeds and the voltage at the P70 INTO TOLCP pin reaches the high level the watchdog timer considers that a program runaway has occurred and triggers a reset or interrupt In this case the runaway detection flag WDTFLG is set If WDTRST is found to be 1 in this case a reset occurs and execution restarts at address 0000H If WDTRST is 0 an external interrupt INTO is generated and control is transferred to vector address 0003H e Hints on Use 1 2 To realize ultra low power operation using HOLD mode it is necessary not to use the watchdog timer
232. s set to 0 timer counter 0 higher and low order bytes function as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer register of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL is the match signal for the prescaler When this bit is set to 1 the count clock for TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH and a match signal is generated when is running TOHRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match must occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated 3 41 la TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL and a match signal is generated when TOL 15 running TOLRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG
233. set to 0 when the UARTI is to be used in the receive mode the UARTI will not function normally if this bit is set to 1 Start bit neq Figure 3 21 1 UART1 Block Diagram Receive Mode 3 98 LC875W00 Chapter 3 Stop bit Note The position of the stop bit differs depending on the bit length to be transferred Start bit 11 bit shift register TSFT Data output LSB first At beginning of transmit operation TBUF gt TSFT TBUF FED3h Clock generator circuit Data length and data bit 8 set Baudrate generator UBR FED2h UART output control gt E P32 UART output format control Note os n or o ar us vs UCON1 FED1h UCONO FEDOh bit 7 Interrupt request Note Bit 2 of PSDDR at FE4D must be set to O when the UARTI transmit data is to be output Transmit data is not output if this bit is set to 1 Figure 3 21 2 UART1 Block Diagram Transmit Mode 3 99 UART1 3 21 4 Related Registers 3 21 4 4 UART1 control register 0 UCONO 1 Thisregister is an 8 bit register that controls the receive operation and interrupts for the UARTI Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDO 0000 0000 UCONO UBRSEL STRDET RECRUN STPERR U0B3 RBIT8 RECEND RECIE UBRSEL bit 7 UART1 baudrate generator period control 1 When this bit is set to 1 the UARTI baudrate generator generates clocks having a period of n 1 x
234. single chip a number of hardware features such as 128K byte flash ROM onboard programmable 4K byte RAM a sophisticated 16 bit timer counter may be divided into 8 bit timers a 16 bit timer counter may be divided into 8 bit timers or 8 bit PWM modules four 8 bit timers with a prescaler a base timer serving as a time of day clock a high speed clock counter two synchronous SIO interfaces with automatic transfer function an asynchronous synchronous SIO interface two UART interfaces full duplex four 12 bit PWM modules an 8 bit 15 channel AD converter a system clock frequency divider an internal reset circuit and a 29 source 10 vector interrupt feature 1 2 Features ROM LC875W00 series LC87F5WCS8A 131072 x 8 bits flash ROM Capable of onboard programming with a wide range of supply voltages 2 7 to 5 5V Block erasable in 128 byte units RAM LC875W00 series LC87F5WCS8A 4096 x 9 bits Minimum bus cycle time e 83 3 ns at 12 MHz Note The bus cycle time here refers to the ROM read speed Minimum instruction cycle time Tcyc e 250 ns at 12 MHz Ports Normal withstand voltage I O ports Ports whose input output be specified in 1 bit units 64 P1n P2n P3n P70 to P73 P8n PAn PBn PCn S2Pn PWMO PWMI XT2 Ports whose input output can be specified in 2 bit units 16 PEn PFn Ports whose input output can be specified in 4 bit units 8 POn Normal withstand voltage input ports 1
235. ster controls the fundamental wave pulse width of PWM1 Fundamental wave pulse width Value represented by PWM1H7 to 1 x 2 When bits 7 to 4 of PWMIL are all fixed at 0 PWM1 can be used as period programmable 8 bit PWM that is controlled by PWM1H Additonal pulse E Fr o 1 2 4 counter Additional pulse PWMO0H PWMIH setting value Fundamental wave counter Fundamental PVM waveform PWM output waveform 3 121 01 3 23 4 6 PWMO 1 port input register PWMO1P 2 bit register 1 data can be read into this register as bit 0 2 PWMI data can be read into this register as bit 1 Address Initial Value Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE25 HHHHHHXX R PWMOIP PWMIIN PWMOIN Bits 7 to 2 These bits do not exist They are always read as 1 PWMHIN bit 1 PWM data read only PWMOIN bit 0 PWMO data read only 3 122 LC875W00 Chapter 3 The 12 bit PWM has the following waveform structure The overall period consists of 16 fundamental wave periods Afundamental wave period is represented by an 8 bit PWM PWM compare register H PWMH 4 bits are used to designate the fundamental wave period to which additional pulses are to be added PWM compare register L PWML 12 bit register structure PWMH PWML XXXX XXXX XXXX 12 bits e How pulses are added to the fundamental wave pe
236. ster for defining the period of timer 7 Timer 7 period T7R value 1 x Timer 7 prescaler value 4 16 or 64 Tcyc 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7B 0000 0000 R W T7R T7R7 T7R6 7 5 T7R4 T7R3 T7R2 T7R1 T7RO 3 16 4 4 Port 0 function control register POFCR 1 POFCR is an 8 bit register used to control the multiplexed output of port 0 pins It controls the toggle outputs of timers 6 and 7 00HH 0000 CLKOEN CKODV2 CKODV1 CKODVO T7OE bit 7 This flag is used to control the timer 7 toggle output at pin P07 This flag is disabled when pin 07 is set in the input mode When pin 07 is set in the output mode A 0 in this bit outputs the value of port data latch A in this bit outputs the OR of the value of the port data latch and the waveform which toggles at the interval equal to the timer 7 period T6OE bit 6 This flag is used to control the timer 6 toggle output at pin P06 This flag is disabled when pin 06 is set in the input mode When pin P06 is set in the output mode A 0 in this bit outputs the value of port data latch A in this bit outputs the OR of the value of the port data latch and the waveform which toggles at the interval equal to the timer 6 period CLKOEN bit 3 CKODV2 bit 2 CKODV1 bit 1 CKODVO bit
237. t be able to stop the watchdog timer stopped by a reset Caution If WDTRST is set to 1 a reset is triggered when INTO is set to 1 even if the watchdog timer is inactive The N channel transistor at pin P70 INTO TOLCP is turned on if the watchdog timer is stopped WDTRUN 0 setting the watchdog timer clear control bit WDTCLR to 1 Keep this in mind when programming if the watchdog timer function is not to be used More current than usual may be consumed depending on the program or application circuit 4 6 4 Master interrupt enable control register IE See Subsubsection 4 1 4 1 Master interrupt enable control register for details 4 6 4 3 Port 7 control register P7 See Subsubsection 3 5 3 1 Port 7 control register for details 4 23 Watchdog Timer 4 5 5 Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed Select the resistance R and the capacitance C that set the time constant of the external RC circuit greater than the time interval required to clear the watchdog timer 1 2 Initializing the watchdog timer All bits of the watchdog timer control register WDT are reset when a reset occurs If the P70 INTO TOLCP pin has been charged up to the high level discharge it down to the low level before starting the watchdog timer The internal N channel transistor is used for discharging Since it has an on resistance a discharging time equal to
238. t source at port 0 e X tal HOLD mode Suspends instruction execution and operation of the peripheral circuits except the base timer 1 The CF and RC oscillators automatically stop operation 2 state of crystal oscillator established when X tal HOLD mode is entered is retained 3 There are four ways of releasing X tal HOLD mode lt 1 gt Setting the reset pin to the low level 2 Setting at least one of the pins INTO INT1 2 INT4 and INTS to the specified level lt 3 gt Establishing an interrupt source at port 0 lt 4 gt Establishing an interrupt source in the base timer circuit On chip debugging function flash ROM type e Supports software debugging with the microcontroller mounted on the target board Package form e OIPIOOE 14x20 lead free and halogen free product Development tools e Evaluation EVA chip LC87EV690 e Emulator EVA62S ECB876600D SUB875C00 POD100QFP ICE B877300 SUB875C00 POD100QFP e On chip debugger TCB87 Type C 3 wire type LC87FSWC8A 1 4 LC875W00 Chapter 1 ZMOS ZdaIS O MOS EdzIS OWMd CSSA 00d 10c 0 0c 704 OO S0d O9L 90d OLL L0d 1d9 10 L 9 LNI dOHO L dO IO LL NTEL T LNI 0Gc dOHOL dO1OL NITL PLNI T2d dOHOL dOTOL NITL VINI ZZd dOHOL dO IOL NITL T LNI Gd IdOHOL LLNI dOHO L dO IO L NITL S LNI V Gd dOHOL dO10L NITL S LNI S8c dOHOL dO1OL NITL S LNI 92 d dOHOL dO
239. ta output control This bit controls the output data at pin P13 When P13 is placed in output mode PI3DDR 1 and P13FCR is set to 1 the OR of the 5101 output data and the port data latch is placed at pin P13 P12FCR bit 2 P12 function control SIOO clock output control This bit controls the output data at pin P12 When P12 is placed in output mode PI2DDR 1 and P12FCR is set to 1 the OR of the SIOO clock output data and the port data latch is placed at pin P12 P11FCR bit 1 P11 function control SIOO data output control This bit controls the output data at pin P11 When P11 is placed in output mode P11DDR 1 and P11FCR is set to 1 the OR of the 5100 output data and the port data latch is placed at pin P11 When the SIOO is active SIOO input data is read from P11 regardless of the I O state of P11 P10FCR bit 0 P10 function control SIOO data output control This bit controls the output data at pin P10 When P10 is placed in output mode PIODDR 1 and is set to 1 the OR of the SIOO output data and the port data latch is placed at pin P10 3 7 Port 1 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT HOLD Mode Operation When in HALT or HOLD mode port 1 retains the state that is established when HALT or HOLD mode is entered 3 8 LC875W00 Chapte
240. table in 1 bit units 10 W PEFCR W PFFCR R PEFCR R PFFCR PEFCR FE29 PFFCR FE2B Port E Port F Block Diagram Option None CMOS Output 11 LC875W00 APPENDIX II Port Block Diagrams SIO2 output clock SI2P FE3B bits 3 2 SI2P3 2 SI2P FE3B bits 7 6 5102 output data g SI2P FE3B a bit 1 SI2P FE3B bit 5 SI2P1 r ma EHE 5102 output data SI2P FE3B Bus Tmo SI2P lt lt Table of Port SI2P Multiplexed Pin Functions Port SI2P SIO2 Block Diagram Option None The output type of SI2P is CMOS However the output type of SI2P1 is set to N channel open drain in SIO2P data output mode 12 LC875W00 APPENDIX II PWM1 output data Pin 4 PWM1 PWM1L 22 bit 6 L P W PWM1L C R PWM1L PWMOC FE24 bit 3 L W PWMOC C Q R PWMOC PWMO output data PWMO PWMOL FE20 W PWMOL R PWMOL R PWMO1P Ports PWMO PWM1 Pins Block Diagram Option None 13 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear responsibility for obligations concerning pat
241. tal wave pulse width Value represented by PWM5H7 5 x 1 2 When bits 7 to 4 of PWMSL are all fixed at 0 PWMS5 can be used period programmable 8 bit PWM that is controlled by PWM5H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE75 0000 0000 R W PWM5H PWMSH7 5 6 5 5 PWM5H4 5 5 2 PVMSHI 5 Led S a 2 Additional pulse PWM4H PWMSH setting value Fundamental wave counter Fundamental PWM waveform PWM output waveform 3 24 5 Setting Up PWM4 and PWM5S Output Ports 1 P30 settings and conditions for generating PWM4 outputs are summarized below Register Data P30 State P30 P30DDR ENPWM4 0 Low PWMA output data XE 3 129 PWM45 2 The P31 settings and conditions for generating PWMS outputs are summarized below Register Data P31 P31DDR ENPWM5 0 Low PWM5S output data 1 0 of ri Eg A ES High open CMOS N channel open drain High open CMOS N channel open drain 3 130 LC875W00 Chapter 3 The 12 bit PWM has the following waveform structure The overall period consists of 16 fundamental wave periods A fundamental wave period is represented by an 8 bit PWM PWM compare register H PWMH 4 bits are used to designate the fundamental wave period to which additional pulses are to be added
242. tarted HOLD mode Main clock and RC oscillator are stopped Subclock retains the uc _ 4 Normal operating mode state established when X tal HOLD mode 8 1 Start stop of all oscillators HOLD mode is entered All oscillators stopped programmable Contents of OCR register are Since OCR register bits 0 1 4 and unchanged 5 are cleared the main clock and CPU enters this mode after RC oscillator are started and the RC selecting subclock or RC oscillator is used as system clock Baud as system source when HOLD mode is released and stopping main clock HALT mode lt _____ When X tal HOLD mode is exited All oscillators retain the state the oscillators return to the state established when HALT mode established when the mode is is entered entered 6 Itis necessary to manipulate the following special function registers to control the system clock PCON OCR CLKDIV XT2PC Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO HHHH 000 R W PCON XTIDLE PDN IDLE rc jetenv jousmvi cuv 4 2 3 Circuit Configuration 4 2 3 1 Main clock oscillator circuit 1 main clock oscillator circuit is ready for oscillation by connecting a ceramic resonator and a capacitor to and CF2 pins 2 CFI must be connected to VDD and CF2 must be released when
243. th the contents of TOHR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7 TOHR6 TOHRS TOHR4 TOHR3 TOHR2 TOHRI TOHRO 3 12 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI6 XXXX XXXX R TOCAL TOCAL7 TOCAL6 TOCALS TOCALA TOCAL3 TOCAL2 TOCALO 3 12 4 8 Timer counter 0 capture register high byte TOCAH 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI7 XXXX XXXX R TOCAH TOCAH7 TOCAH6 5 TOCAH3 2 TOCAHI TOCAHO 3 12 4 9 Timer counter 0 capture register 1 low byte TOCA1L 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIE XXXX R TOCAIL TOCA1L7 TOCA1L6 11 5 TOCA1L4 TOCA1L3 TOCA1L2 1 TOCA1LO 3 12 4 10 Timer counter 0 capture register 1 high byte
244. the features listed below It allows the microcontroller to take in analog signals easily 1 2 3 4 5 6 3 25 2 1 2 3 4 5 6 Address 8 bit resolution Successive approximation 15 channel analog input Conversion time select Reference voltage generation control T O port Functions Successive approximation The ADC has a resolution of 8 bits Requires a conversion time of 32 64 128 or 256 Tcyc cycle time The conversion results are placed in the AD conversion result register ADRR 15 channel analog input The signal to be converted is selected using the AD converter control register ADCR from 15 types of analog signals that are supplied from port 8 P70 P71 XT1 X T2 PA4 and PAS Conversion time select The AD conversion time can be selected from among 32Tcyc 64Tcyc 128Tcyc and 256Tcyc The AD converter control register ADCR and reference voltage generator circuit control register DACR are used to select the conversion time for appropriate AD conversion Reference voltage generation control The ADC incorporates a reference voltage generator whose output voltage can be controlled using the reference voltage generator circuit control register DACR There is no need to supply the reference voltage externally I O port Pins P80 to P87 can be used as 8 bit I O port pins of the N channel open drain output type Pins P70 and P71 are shared with port 7 Pins PA3 PA4
245. the main clock is not to be used 4 2 3 2 Subclock oscillator circuit 1 subclock oscillator circuit is ready for oscillation by connecting a crystal resonator 32 768 kHz standard a capacitor feedback resistor and a damping resistor to the XT1 and XT2 pins 2 state ofthe and XT2 pins can be read as bits 2 and 3 of the register OCR 3 The XT2 pin can carry a general purpose output signal N channel open drain 4 When the and XT2 pins are not to be used the pin must be connected to VDD the XT2 pin must be released and the bit 6 of the OCR register must be set 4 2 3 3 Internal RC oscillator circuit 1 internal RC oscillator circuit oscillates according to the built in resistors and capacitors 2 clock from the RC oscillator is selected as the system clock after the microcontroller exits reset or HOLD mode 3 Unlike main clock and subclock oscillators the RC oscillator starts oscillation at a normal frequency from the beginning of oscillation 4 7 System Clock 4 2 34 Power control register PCON 3 bit register 1 power control register specifies the operating mode normal HALT HOLD X tal HOLD 4 2 3 5 Oscillation control register OCR 8 bit register 1 This register controls the start stop operation of the oscillator circuits 2 This register selects the system clock 3 The register sets the division ratio of the oscillation clock to be used as the syst
246. the time constant of the external capacitance is required Set bits 0 and 4 of the port7 control register P7 FESC to 0 0 to make the P70 port output open Starting discharge Load WDT with 04H to turn on the N channel transistor at the P70 INTO TOLCP pin to start discharging the capacitor Checking the low level Check for data at the P70 INTO TOLCP pin Read the data at the P70 INTO TOLCP pin with an LD or similar instruction A 0 indicates that the P70 INTO TOLCP pin is at the low level Starting the watchdog timer 1 Set bit 2eWDTCLR and bit 0 WDTRUN to 1 2 Also set bit 1 WDTRST to 1 when a reset is to be triggered when a runaway condition 1s detected 3 To suspend the operation of the watchdog timer in HOLD or HALT mode set bit 4 WDTHLT at the same time The watchdog timer starts functioning when bit 0 WDTRUN is set to 1 Once the watchdog timer starts operation WDT is disabled for write it is allowed only to clear the watchdog timer and read WDT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped only when a reset occurs or when the microcontroller enters HALT or HOLD mode with WDTHLT being set In this case WDT bits 2 to 0 are reset 4 24 3 4 LC875W00 Chapter 4 Clearing the watchdog timer When the watchdog timer starts operation the external RC circuit connected to the P70 INTO TOLCP is charged When voltage at thi
247. the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the old state of the PC and interrupt level Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H and highest level X The interrupt function will not accept any interrupt request of the same level or lower level than that of the interrupt that is currently being processed Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests When interrupts of the same level occur at the same time an interrupt with a smaller vector address is given priority Interrupt request enable control The master interrupt enable register can be used to control enabling disabling of H and L level interrupt requests nterrupt requests of the X level cannot be disabled Interrupt disable period nterrupts are held disabled for a period of 2Tcyc after a write is made to the IE 08 or IP 09 register or after HOLD mode is released No interrupt can occur during the interval between the execution of an instruction that loads the PCON 07 register and the execution of the next instruction No interrupt can occur during the interval betwee
248. ting TOCAL TOCA1L TOCAH TOCA1H Capture Clear TOL TOH Match Match buffer register TOLCMP Match buffer register Reload flag set Reload TOLR TOHR programmable timer with Pm programmable timer with programmable prescaler programmable prescaler TOHCMP flag set Figure 3 12 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 Clock Clear Capture trigger Prescaler Registers 01 FE5Dh I23CR FESEh ISL FESFh I45CR FE4Ah I45SL FE4Bh and 167 FE4Eh need setting TOCAL TOCA1L TOCAH TOCA1H Capture Clock External input gt TOL Set in register ISL FE5Fh Match buffer register TOHCMP TOLCMP flag set Relaod flag set TOLR programmable counter programmable timer with programmable prescaler Figure 3 12 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 3 39 Clock Clear roe Match Capture trigger TOCAH TOCA1H TOCAL TOCA1L Registers 101CR FE5Dh l23CR FE5Eh ISL FE5Fh 145CR FE4Ah 14551 FE4Bh and I67CR FE4Eh need setting Match TOLCMP Match buffer register TRU flag set TOHR TOLR lt 16 bit programmable timer gt programmable prescaler Capture Figure 3 12 3 Mode 2 Block Diagram TOLONG 1 TOLEXT 0 Capture trigger Registers 0 Capture 23 FESEh ISL FE5Fh External input 2 ToL Clear 45CR FE4Ah 14551 FE4Bh
249. ts a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE06 0000 0000 R W PSW CY AC PSWBS PSWB4 LDCBNK OV CY bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are following four types of carries 1 Carry resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the high order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table look up instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table look up instruction 0 ROM ADR 0 to IFFFF 1 ROM ADR 20000 to 3FFFF OV bit 2 Overflow flag
250. tting up the port SIDPC FE3B Control SI2P3 Settings SI2P2 Settings SI2P1 Settings SI2PO Settings SI2PC bit General purpose Clock input Data input General purpose input general purpose general purpose input input input 01 Clock output 01 Clock output 01 Data output Data output drain For example load 5 2 FE3B register with 05H when using the SIP2 as the clock output pin SI2P1 as the data input pin SI2PO as the data output pin and SI2P3 as a general purpose input pin Note When selecting the SI2P3 as clock output and SI2P2 as general purpose input SIO2 communication using the internal clock does not function because SIO2 communication uses clock input output from the SI2P2pin 2 Setting the number of communication data bytes and the data starting address SCTR2 FE3A e Load SCTR2 bits 4 to 0 with the number of data bytes to communicate Communication data bytes Value of SCTR2 bits 4 to 0 1 Load SCTR2 bits 7 to 5 with the data starting address Control Data Starting RAM Address Data Byte Count SCTR2 bit 765 SDBN to 0 43210 SCTR24 to 20 000 Data starting RAM address 0100H Communication data bytes Data starting RAM address 0120H Value of bits 4 to 0 1 Data starting RAM address 0140H Data starting RAM address 0160H 3 Setting up output data Write output data into RAM in data transmission mode 3 02 LC875W00 Chapter 3
251. upt state The interrupt state is a microcontroller state in which either bit 4 5 or 6 of the IE register 08 is set 2 Reading this register when the microcontroller is not in the interrupt state returns all 15 7 00033 3 interrupt source flag bit assignments are listed in Table 4 1 1 Interrupt Source Flag Bit Assignments Bits to which no interrupt source flag is assigned return a when read 4 When the microcontroller is placed into the interrupt state the bit that is associated with the interrupt source is set to 1 and the bit that is not associated with the interrupt source is set to 0 see the example shown on the next page for details Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 05 1111 1111 R IFLGR IFLGR7 IFLGR6 IFLGRS5 IFLGR4 IFLGR3 IFLGR2 IFLGRI IFLGRO Table 4 1 1 Interrupt Source Flag Bit Assignments Vector Address 00003H FS gt Ne plex 00018 Basetimer1 Basetimero INTS IND 1 e AE HEY eee eee ple ere Erw pe ee INT TE 1 TIL 0033H UART2 receive UARTI receive 5100 ooosBH UART2 transmit UARTI transmit 802 sioi Apo power
252. usenenan 1 6 1 5 Pin Functions 1 7 16 Output Types 1 10 Chapter 2 Internal Configuration Veweiesesexvrexvrerresizcesarsesais sedate 2 1 21 Space 2 1 22 Counter PC sasanasasasnsansuasasasssususesenauasssesenansusanesanesessansuusenenan 2 1 2 3 Program Memory ROM sanassssananssassansnsuassauauseseusuaA sosanansesenansasenanansua 2 2 24 Internal Data Memory RAM ananassananssssasasussesesasuausesenanauuasanaususenaneuenas 2 2 2 5 Accumulator A Register ACC A senanasssssansssusosasasuonenananseuenanansauansuanenes 2 3 2 6 B Register B senanassssananssassananescssssuuasuesesanssuesenansenenanasausananeuassuanauenenes 2 3 2 7 Register C senanasssssnanssanasasssuasensenanssuenanansasananssesessasussesenanseseonananss 2 4 2 8 Program Status Word PSW wananassananansuasussusausensenssusosenanasussananeussansuenas 2 4 2 9 Stack Pointer SP sananassasanascasananssanausaneusessunssssessssaussesessanansenenanusanenenanas 2 5 2 10 Indirect Addressing Registers senanasasuanensuasesessssesesanansusenenanescanansuuusenenan 2 5 2 11 Addressing Modes sanasassananasesaunan
253. ust be cleared with an instruction SI2END bit 1 Serial transfer end flag 1 This bit is automatically set when serial transfer ends on the rising edge of the last clock for data transfer 2 Thisbit must be cleared with an instruction SI2IE bit 0 SIO2 interrupt request generation enable control 1 An interrupt request to vector address 003BH is generated when this bit and SIDEND are set to 1 3 20 5 2 5102 shift register 2 SBUF2 1 Thisregister is used to transmit and receive SIO2 data 2 When SI2WRT 1 the contents of SBUF2 and data RAM are exchanged before 8 bit data transmission starts 3 When SIZ2WRT 0 SBUF2 is loaded with the contents of data RAM before 8 bit data transmission starts Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE39 0000 0000 R W SBUF2 SBUF27 SBUF26 SBUF25 SBUF24 SBUF23 SBUF22 SBUF21 SBUF20 3 20 5 3 5102 transfer data control register SCTR2 8 bit register 1 This register is used to control the volume in bytes of SIO2 data to be transferred and to select the period of the internal clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3A 0000 0000 R W SCTR2 SDBN2 SDBNI SDBNO SCTR24 SCTR23 SCTR22 SCTR21 SCTR20 SI2BN2 bit 7 5102 communication data starting address control SI2BN1 bit 6 SIO2 communication data starting address control SI2BNO bit 5 SIO2 communication data starting address co
254. utput 8 8 8 8 8 8 8 8 Shift data 1s Shift data 1s Shift data 1s Shift data 1s Data input 8 lt 8 lt 8 lt 8 lt Input pin Input pin Input pin Input pin Stop bit None lt Output Input Input Output Input High H L H L SBUF1 bit8 H L L Clock 9 lt lt Low output Internal on falling edge of 8th clock Operation start SIIRUNT lt 1 1 on left side 1 on right 1 No start bit side Clock on falling released on falling edge of SILEND With start bit i on rising edge of SHRUN SILRUN 0 and when SHEND 0 SIIEND 0 Period 2 to 512 lt 8 to 2048 lt 2 to 512Tcye lt 2 to 512Tcyc lt SIIRUN Set Instruction lt 1 Start bit Instruction Already set Already set Start bit bit 5 Instruction detected 2 Start bit detected Clear End of lt End of stop lt 1 1 processing bit Stop Stop condition condition detected detected 2 2 When Ack 1 arbitration detected lost Note 1 Set End of lt End of stop lt 1 lt 1 processing bit Rising edge Falling of 9th clock edge of 8th 2 clock Stop 2 condition Stop detected condition detected SIIEND bit 1 Note 1 If internal data output state H and data port state L conditions are detected on the rising edges of the first to Sth clocks the microcontroller recognizes a bus contention loss and clears SITRUN and also stops the generation of the clock at th
255. view Port 7 is a 4 bit I O port equipped with programmable pull up resistors It is made up of a data control latch and a control circuit The input output direction of port data can be controlled in 1 bit units Port 7 can also be used as an input port for external interrupts It can also be used as an input port for the timer 0 count clock input capture signal input and HOLD mode release signal input There is no user option for this port 3 5 2 1 2 3 4 5 Functions Input output port 4 bits P70 to P73 The low order 4 bits of the port 7 control register P7 5 are used to control the port output data and the high order 4 bits to control the I O direction of port data e P70 is an N channel open drain output type and P71 to P73 are a CMOS output type Each port bit is provided with a programmable pull up resistor Interrupt input pin function e P70 and P71 are assigned to INTO and INT1 respectively and are used to detect a low or high level or a low or high edge and to set the interrupt flag e P72 and P73 are assigned to INT2 and INT3 respectively and are used to detect a low or high edge or both edges and to set the interrupt flag Timer 0 count input function A count signal is sent to timer 0 each time a signal change that sets the interrupt flag is supplied to a port selected from P72 and P73 Timer OL capture input function A timer OL capture signal is generated each time a signal
256. x 32 3 2 When this bit is set to 0 the UART2 baudrate generator generates clocks having a period of n 1 x 8 n represents the value of the UART baudrate generator UBR2 at FEEAh STRDET2 bit 6 UART2 start bit detection control 1 When this bit is set to 1 the start bit detection falling edge detection function is enabled 2 When this bit is set to O the start bit detection falling edge detection function is disabled This bit must be set to 1 to enable the start bit detection function when UART2 is to be used in continuous receive mode If this bit is set to 1 when the receive port P35 is held at a low level RECRUN2 is automatically set and the UART2 starts the receive operation RECRUN bit 5 UART2 receive start flag 1 This bit is set and a receive operation starts when a falling edge of the signal at the receive port P35 is detected when the start bit detection function is enabled STRDET2 1 2 This bit is automatically cleared at the end of the receive operation If this bit is cleared during the receive operation the UART2 is disabled in the middle of the operation When a receive operation is forced to terminate prematurely RECEND2 is set to 1 and the contents of the receive shift register are transferred to RBUF2 And STPERR2 is set to 1 if the state of the last data bit that is received on the forced termination is low STPERR2 bit 4 UART2 stop bit error flag
257. yte of timer counter 0 TOL Timer counter 0 capture register high byte TOCAH 8 bit register Capture clock External input detection signals from the P71 INT1 TOHCP P73 INT3 TOIN TOHCP and P20 to P27 timer OH capture input pins Capture data Contents of the high order byte of timer counter 0 TOH Timer counter 0 capture register 1 low byte TOCA1L 8 bit register Capture clock External input detection signals from the P20 INTS TIIN TOLCP TOHCP INTO TOLCPI pin when TOLONG timer 0 control register bit 5 is set to 0 External input detection signals from the P24 INTS TIIN TOLCP TOHCP INT7 TOHCP I pin when TOLONG timer 0 control register bit 5 is set to 1 Capture data Contents of timer counter 0 low byte TOL 3 37 10 3 12 3 11 Timer counter 0 capture register 1 high byte TOCA1H 8 bit register 1 Captureclock External input detection signals from the P24 INTS TIIN TOLCP TOHCP INT7 TOHCPI pin 2 Capture data Contents of timer counter 0 high byte Table 3 12 1 Timer 0 TOL Count Clocks Mode TOLONG TOLEXT TOH Count Clock TOL Count Clock TOH TOL Count Clock TOPRR match signal TOPRR match signal ASRS 3a 9 0 LL 0 mesas _ 1 a trait 3 38 LC875W00 Chapter 3 Clock Clear Fe Capture trigger Registers 101CR FE5Dh I23CR FE5Eh ISL FE5Fh Match I45CR FE4Ah 14551 FE4Bh TOPRR I67CR FE4Eh need set

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