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1. Table 23 A D Mode register B ADMODB address Ath bit description continued Bit Symbol Description 4 INBNDO When set 1 generates an interrupt if the conversion result is inside or equal to the boundary limits When cleared 0 generates an interrupt if the conversion result is outside the boundary limits 7 5 CLK2 CLK1 CLKO Clock divider to produce the ADC clock Divides CCLK by the value indicated below The resulting ADC clock should be 8 MHz or less A minimum of 0 5 MHz is required to maintain A D accuracy CLK2 0 Divisor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Table 24 A D Input select ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN13 AIN12 AIN11 AIN10 AINO3 AINO2 AINO1 AINOO Reset 0 0 0 0 0 0 0 0 Table 25 A D Input select ADINS address A3h bit description Bit Symbol Description 0 AINOO When set enables the Anin00 pin for sampling and conversion unused 1 AINO1 When set enables the Anin01 pin for sampling and conversion unused 2 AINO2 When set enables the Anin02 pin for sampling and conversion unused 3 AINO3 When set enables the Anin03 pin for sampling and conversion 4 AIN10 When set enables the Anin10 pin for sampling and conversion 5 AIN11 When set enables the Anin11 pin for sampling and conversion 6 AIN12 When set enables the Anin12 pin for sampling and conversion 7 AIN13 When set enables the Anin13 pin for sampling and c
2. lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 9 of 136 UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual NXP Semiconductors 1 5 Special function registers Remark SFR accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 10 of 136 lt q Juewinoog gt yenuew Jasq 6002 Arenuqa4 S xx L0 Ae pamasa Syu Ily 6002 Ad dXNO 9El JO LL Table 2 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 0000 0000 AUXR1 Auxiliary A2H CLKLP EBRR
3. User manual Rev 01 xx 5 February 2009 92 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 14 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 39 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC9201 9211 922A1 9241 9251 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was all
4. Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset X xX xX xX xX xX 0 0 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 64 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 59 Serial Port Status register SSTAT address BAh bit description Bit Symbol Description O STINT Status Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the numb
5. NXP Semiconductors UMennnnns lt Document ID gt 3 2 2 3 2 2 1 3 2 2 2 3 2 2 3 P89LPC9201 9211 922A1 9241 9251 User manual ADC operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel see Table 12 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCAN x bit in the ADMODA register Table 12 Input channels and result registers for fixed channel single auto scan single and auto scan continuous conversion mode Result register Input channel ADODATO Anin0O unused ADODAT1 Anin01 unused ADODAT2 Anin02 unused ADODAT3 Anin03 AD1DATO Anin10 AD1DAT1 Anin11 AD1DAT2 Anini2 AD1DAT3 Anin13 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result registers see Table 13 An interrupt if enabled will be generated after every four conversions Additional conversion results will again cycle through the four result registers overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the SCCx bit in the ADMODA register
6. has been received I2DAT action 1 0 0 x Repeated START will be or transmitted no l2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 xX STOP condition followed by a START condition will be transmitted STO flag will be reset lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 81 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 73 Master Transmitter mode continued Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO sl AA 30h Data byte in Load data byte or 0 0 0 Data byte will be transmitted l2DAT dee ACK bit will be received transmitted ACK has been no l2DAT action 1 0 0 Repeated SIART will be received or transmitted no I2DAT action 0 1 0 STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 38H Arbitration lostin No I2DAT action 0O 0 0 I2C bus will be released not SLA R W or data or addressed slave will be bytes entered No I2DAT action 1 0 0 A START condition will be transmitted when the bus becomes free Table 74 Master Receiver mode Status code Status of the IC Application software response Next
7. gt KBI5 gt CMPREF gt KBI6 gt CMP1 lt KBI7 gt T1 gt CMP2 lt CIN2B CIN2A gt tilli CLKOUT XTAL2 XTALI gt CIN1B gt porto 4 PORT 3 4 Voo Vss PP pi PORT 1 P89LPC9201 9211 922A1 ITIITI 002aae423 Fig 4 P89LPC9201 9211 922A1 logic symbol TXD lt RXD gt T0 lt SCL INTO gt SDA NTI lt RST KBIO AD11 KBI2 KBI6 gt CM KBI7 gt Fig5 P89LPC9241 9251 logic symbol gt CMP2 AD10 gt KBI1 CIN2B CIN2A AD12 KBI3 gt CIN1IB DAC1 lt AD13 KBI4 gt CINIA KBI5 gt CMPREF P1 Ti CLKOUT 4 XTAL2 XTALI gt Voo Vss s Load PORT 0 4 P89LPC9241 9251 aee eee al iii cr PORT 3 002aae424 TXD lt RXD gt T0 SCL lt INTO SDA PORT ing 4 RST lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 7 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 1 4 Block diagram P89LPC9201 9211 922A1 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80051 CPU oN 2 KB 4 kB 8 kB TXD CODE FLASH K UART RXD internal 256 BYTE y avs y REAL TIME CLOCK DATA RAM SYSTEM TIMER PORT 3 SCL 2 P3f 1 0 Te a e iK 1K gt I C BUS SDA ee 1 WATCHDOG TI
8. CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 CE2 CP2 CN2 OE2 CO2 CMF2 oo xx00 0000 00 0000 0000 00 0000 0000 00 0000 0000 Jenuewl 13SM LGZ6 LYZ6 LYZZ6 LLZ6 LO0OZ69d168d lt uuuuu gt NN S10 9NpuodIWM S dXN jenuew asn 600z Arenaga4 G xx L0 Ae QE JQe6 L lt q Juawinoog gt pamasa Syu Ily 6002 Ad dXNO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL I2STAT IENO IEN1 Description SFR addr Program flash E7H address high Program flash E6H address low Program flash E4H control Read Program flash E4H control Write Program flash E5H data I2C bus slave DBH address register Bit address I2C bus control D8H register I2C bus data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low I C bus status D9H register Bit address Interrupt A8H enable 0 Bit address Interrupt E8H enable 1 Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 BUSY HVA HVE SV Ol 70 0111 0000 FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O 00 0000 0000 I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 DF DE DD DC DB DA D9 D8 I2EN STA STO SI AA CRSEL 00 x000 00x0 0
9. Table 60 FE and RI when SM2 1 in Modes 2 and 3 Mode PCON 6 RB8 RI FE SMODO0 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 27 with SMODO 0 RI Occurs during STOP occurs during RB8 one bit before FE bit 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 27 with SMODO 1 RI Occurs during STOP occurs during STOP bit bit Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the
10. Table 13 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains ADxDATO Selected channel first conversion result ADxDAT1 Selected channel second conversion result ADxDAT2 Selected channel third conversion result ADxDAT3 Selected channel fourth conversion result Auto scan single conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 12 An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode This mode is selected by setting the SCANx bit in the ADMODA register NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 32 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 3 2 2 4 Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A conversion of each selected input will b
11. 7 Unprogrammed 0 x X x x x xX xX value Table 102 Flash User Configuration Byte 2 UCFG2 bit description Bit Symbol Description 0 6 Not used 7 CLKDBL Clock doubler When set doubles the output frequency of the internal RC oscillator 16 18 User security bytes This device has three security bits associated with each of its eight sectors as shown in Table 103 Table 103 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 115 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 104 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte ina MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global
12. Cleared by software 1 COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vref is selected as the negative comparator input 4 CPn Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CEn Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 6 7 reserved lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 87 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual CP1 OE1 P0 4 CINIA comparator 1 P0 3 CINIB i cot gt om CMP1 P0 6 P0 5 CMPREF Vref bg gt change detect CN1 gt interrupt change detect EC P0 2 CIN2A P0 1 CIN2B CMP2 P0 0 002aae433 Fig 36 Comparator input and output connections lt Document ID gt 12 2 12 3 12 4 Internal referen
13. PRE1 Clock Prescaler Tap Select Refer to Table 88 for details 7 PRE2 Table 88 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 94 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 88 Watchdog timeout vales continued PRE2 to PREO 100 101 110 111 WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog Nominal Clock 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 0 2 049 5 12 ms 341 5 us 255 524 289 1 31s 87 4 ms 0 4097 10 2 ms 682 8 us 255 1 048 577 2 62 s 174 8 ms lt Document ID gt 14 3 Watchdog clock source The watchdog timer system has an on chip 400 KHz oscillator The watchdog timer can be clocked from the watchdog oscillator PCLK or crystal oscillator refer to Figure 38 by configuring the WDCLK bit in the Watchdog
14. Watchdog timer Real time WDOVF RTCF 0053h EWDRT IEN0 6 IPOH 6 IP0 6 3 Yes clock 12C interrupt SI 0033h El2C IEN1 0 IPOH 0 IP0 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH 0 IP0 0 8 Yes lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 40 of 136 NXP Semiconductors UMennnnns Table 29 Summary of interrupts continued P89LPC9201 9211 922A1 9241 9251 User manual Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up Comparators 1 and 2 CMF1 CMF2 0043h EC IEN1 2 IPOH O0 IP0 0 11 Yes interrupts Serial port Tx TI 006Bh EST IEN1 6 IPOH O0 IP0 0 12 No ADC P89LPC9241 9251 ADCI1 BNDI1 0073h EAD IEN1 7 IP1H 7 1P1 7 15 lowest No Xo EXO EX1 EE EBO N wake up RICE _ gt KBIF a j if in power down ERTC EKBI RTCCON 1 CMF2 CMF1 EC EA IEO 7 TF1 ETI EI2C Do e ADCIO 1 ENADCI1 1 ADCI1 1 BNDIO 1 i PE S BNDI1 1 EAD 1 wor _ DJ mo gt ETO TI and RI RI j gt ES ESR EST to CPU s J H a pro D 1 P89LPC9241 9251 Fig 12 Interrupt sources interrupt enables and power down wake up sources 002aae429 5 I O ports The P89LPC9201 9211 922A1 9241 9251 has three I O ports Port 0 Port 1 and Port 3 Ports 0 and 1 are 8 bit por
15. become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer eee A om Se DR logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW C from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition P STOP condition 002aaa933 Fig 34 Format of Slave Transmitter mode NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 79 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 8 NN ADDRESS REGISTER INPUT FILTER P1 3 SDA OUTPUT STAGE gt BIT COUNTER ARBITRATION CCLK 2 INPUT AND SYNC LOGIC MING m FILTER AND z CONTROL Z P1 2 SCL LOGIC i SERIAL CLOCK OUTPUT interrupt Zz STAGE GENERATOR timer 1 _ overflow P1 2 I2CON CONTROL REGISTERS AND I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL STATUS status bus DECODER I2STAT STATUS REGISTER OND NNPaaAaRAQ Fig 35 1 C serial interface block diagram lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 80 of 136 NXP Semiconductors UMennnn
16. the device will wake up 15 Additional features The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 91 Table 90 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 x 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 97 of 136 NXP Semiconductors UMennnnns lt Document ID gt 15 1 15 2 P89LPC9201 9211 922A1 9241 9251 User manual Table 91 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC9201 9211 922A1 9241 9251 as if a hardware reset occurred 4 ENTO When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of the Timer 0 overflow rate Refer to Section 8 Timers 0 and 1 for details 5 ENT1 When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to Section 8 Timers 0 and 1 for details 6 EBRR UART Break Detect Reset Enable I
17. 0 0 xX X CCLKy 6 0 1 0 0 CELK 556 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLKY BRGR1 BRGR0 16 1 0 0 X CCLKy 1 X CELK 6 1 1 0 0 CELK 556TH 64 1 0 CCLK 256 TH1 32 X 1 CCLKY BRGR1 BRGR0 16 Table 53 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset xX xX xX xX xX xX 0 0 Table 54 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 BRGEN Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 52 for details 2 7 reserved timer 1 overflow PCLK based SMpBt eaneesu oO o baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 24 Baud rate generation for UART Modes 1 3 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMOD0 is logic 0 Break detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed low Since a br
18. 1 Push pull 1 0 Input only high impedance 1 1 Open drain Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 42 of 136 NXP Semiconductors UMennnnns
19. 10 1 10 2 10 3 The P89LPC9201 9211 922A1 9241 9251 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9201 9211 922A1 9241 9251 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes as described in the following sections Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 146 of the CPU clock frequency Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logi
20. 63 1 C data register IZ2DAT address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2DAT 7 1I2DAT 6 I2DAT 5 I2DAT 4 I2DAT 3 1I2DAT 2 I2DAT 1 I2DAT 0 Reset 0 0 0 0 0 0 0 0 12C slave address register I2ADR register is readable and writable and is only used when the 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Table 64 1 C slave address register I2ADR address DBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC Reset 0 0 0 0 0 0 0 0 Table 65 I C slave address register IZADR address DBh bit description Bit Symbol Description 0 GC General call bit When set the general call address OOH is recognized otherwise it is ignored 1 7 I2ADR1 7 7 bit own slave address When in master mode the contents of this register has no effect NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 73 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 11 3 I2C control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is cleared by hardware CRSEL determines the SCL source when the I C bus is in master mode In slave mode this bit is ign
21. 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 KBMASK 2 KBMASK 1 KBMASK 0 Reset 0 0 0 0 0 0 0 0 Table 84 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description 0 KBMASK O When set enables P0 0 as a cause of a Keypad Interrupt 1 KBMASK 1 When set enables P0 1 as a cause of a Keypad Interrupt 2 KBMASK 2 When set enables P0 2 as a cause of a Keypad Interrupt 3 KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt 4 KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt 5 KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt 6 KBMASK 6 When set enables P0 6 as a cause of a Keypad Interrupt 7 KBMASK 7 When set enables P0 7 as a cause of a Keypad Interrupt 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 14 Watchdog timer WDT The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset 14 1 Watchdog function The user has the ability using the WDCON CLKCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow I
22. AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 73 a e a a a a logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW 1 from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition P STOP condition 002aaa929 Fig 30 Format in the Master Transmitter mode 11 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to C Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 75 for details lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 77 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual arama A Pom A DD logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowle
23. Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 000x 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 FF 1111 1111 00 0000 0000 00 0000 0000 Jenuewl 19Sf 1 S26 LV26 LVCC6 L 26 LOC6Od 168d lt UUUUUPINN SIOJONPUOSIWSS dXN jenuew asn 600z Areniga4 G xx L0 AeY 9EL JO SL lt q u wnooq gt pamasa Syu Ily 6002 A a dXNO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B BRGROE BRGA1E2 BRGCON CMP1 CMP2 DIVM DPTR DPH DPL SFR addr Description A D_0 data D6H register 1 A D_0 data D7H register 2 A D_0 data F5H register 3 Auxiliary A2H function register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Comparator 1 ACH control register Comparator 2 ADH control register CPU clock 95H divide by M control Data pointer 2 bytes Data pointer 83H high Data pointer 82H low Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 a SBRGS BRGEN lool Xxxx Xx00
24. CLKOK is 0 clock switch is processing not completed When CLKOK is 1 clock switch is completed When start new clock source switch CLKOK is cleared automatically Notice that when CLKOK is 0 Writing to CLKCON register is not allowed During reset CLKCON register value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 Table 9 Clock control register CLKCON address FFDEh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO Reset 1 0 0 0 x x x x Table 10 Clock control register CLKCON address FFDEh bit description Bit Symbol Description 2 0 FOSC2 FOSC1 CPU oscillator type selection for clock switch See Section 2 for additional FOSCO information Combinations other than those shown in Table 11 are reserved for future use and should not be used 3 CLKDBL Clock doubler option for clock switch When set doubles the output frequency of the internal RC oscillator 4 XTALWD external crystal oscillator as the clock source of watchdog timer When 0 disable external crystal oscillator as the clock source of watchdog timer 6 5 z reserved CLKOK Clock switch completed flag When 1 clock switch is completed When 0 clock switch is processing and writing to register CLKCON is not allowed lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5
25. Control Register WDCON and XTALWD bit in CLKCON register When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU Table 89 Watchdog input clock selection WDCLK WDCON 0 XTALWD CLKCON 4 Watchdog input clock selection 0 0 PCLK 1 0 watchdog oscillator Xx 1 Crystal oscillator WDCLK bit is used to switch between watchdog oscillator and PCLK And XTALWD bit is used to switch between watchdog oscillator PCLK and crystal oscillator After changing clock source switching of the clock source will not immediately take effect As shown in Figure 40 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK
26. It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared BOD Interrupt Flag When BOD Interrupt is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit reserved 7 1 Reset vector Following reset the P89LPC9201 9211 922A1 9241 9251 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot NXP B V 2009 All rights reserved Bit Symbol 0 R_EX R_SF 2 R_WD 3 RBK 4 POF 5 BOF 6 BOIF T z lt Document ID gt User manual Rev 01 xx 5 February 2009 52 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT O 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000H 8 Timers 0 and 1 The P89LPC9201 9211 922A1 9241 9251 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Table 43 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the timer is
27. P89LPC9201 9211 922A1 9241 9251 User manual The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 13 Although the P89LPC9201 9211 922A1 9241 9251 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet Dynamic characteristics for glitch filter specifications VDD 2 CPU CLOCK DELAY P P trong ee weak port pin input data glitch rejection 002aaa914 Fig 13 Quasi bidirectional output lt Document ID gt 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an
28. SDA P1 2 TO SCL QO P89LPC9201 9211 922A1 002aae426 PO 1 CIN2B KBI1 P0 2 CIN2A KBI2 P0 3 CIN1B KBI3 P0 4 CIN1A KBI4 PO 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 PO 7 T1 KBI7 P1 0 TXD P1 1 RXD Fig 1 P89LPC9201 9211 922A1 TSSOP20 pin configuration P0 0 CMP2 KBIO P0 1 CIN2B KBI1 AD10 P1 7 P0 2 CIN2A KBI2 AD11 P1 6 P0 3 CIN1B KBI3 AD12 P1 5 RST P0 4 CIN1A KBI4 AD13 DAC1 Vss P0 5 CMPREF KBI5 P89LPC9241 9251 P3 1 XTAL1 Vpp P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 PO 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD 002aae425 Fig 2 P89LPC9241 9251 TSSOP20 pin configuration NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 3 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Fig 3 P89LPC922A1 DIP20 pin configuration P89LPC922A1 P0 0 CMP2 KBIO PO 1 CIN2B KBI1 P1 7 P0 2 CIN2A KBI2 P1 6 P0 3 CIN1B KBI3 P1 5 RST PO 4 CIN1A KBI4 Vss P0 5 CMPREF KBI5 P3 1 XTAL1 VDD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 PO 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD 002aae427 1 2 Pin description Table 1 Pin description Symbol Pin Type Description TSSOP20 DIP20 P0 0 to PO 7 I O Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up dis
29. Table 96 12C Control register I2CON address D8h 91 Table 97 Master Transmitter mode 94 Table 98 Master Receiver mode 95 Table 99 Slave Receiver mode 96 Table 100 Slave Transmitter mode 98 Table 101 SPI Control register SPCTL address E2h bit allocation 100 Table 102 SPI Control register SPCTL address E2h bit description 101 Table 103 SPI Status register SPSTAT address Eth bit allocation 101 Table 104 SPI Status register SPSTAT address E1h bit description 101 Table 105 SPI Data register SPDAT address E3h bit allocation 102 Table 106 SPI master and slave selection 103 Table 107 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation 110 Table 108 Comparator Control register CMP1 address ACh CMP2 address ADh bit description 110 Table 109 Keypad Pattern register KBPATN address 93h bit allocation 113 Table 110 Keypad Pattern register KBPATN address 93h bit description 113 Table 111 Keypad Control register KBCON address 94h bit allocation 114 Table 112 Keypad Control register KBCON address 94h bit description 114 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 125 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual Table 113 Keypad Interrupt Mask register KBMASK address 86h bit allocation 114 Table 114 Keypad Interrupt Mask register KBMASK address 86h bit descri
30. The temperature sensor is measured through AninO3 AninOO AninO1 and Anin02 are unused A block diagram of the A D converter is shown in Figure 11 The A D converter consists of an 4 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR 3 2 A D features e 8 bit 4 channel multiplexed input successive approximation A D converter e On chip wide range temperature sensor e Four result registers for each A D e Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode e Three conversion start modes Timer triggered start Start immediately Edge triggered e 8 bit conversion time of gt 1 61 us at an A D clock of 8 0 MHz e Interrupt or polled operation e High and low boundary limits interrupt e DAC output to a port pin with high output impedance e Clock divider e Power down mode lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 30 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual input MUX fe ee a x lt
31. Timer counter 0 Mode 3 two 8 bit counters cman overflow PCLK o on TEN TFn interrupt _ control 8 bits reload THn on falling transition and 256 THn on rising transition toggle TRn Gate THn INTn pin 8 bits ENTn 002aaa923 Fig 22 Timer counter 0 or 1 in mode 6 PWM auto reload 8 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and ENT1 in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 9 Real time clock system timer The P89LPC9201 9211 922A1 9241 9251 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 23 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 57 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual The Real time Clock is a 23 bit dow
32. Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about the
33. action taken by I C hardware I2STAT hardware to from I2DAT to I2CON STA STO SI STA 08H A START Load SLA R x 0 0 x SLA R will be transmitted ACK bit condition has will be received been transmitted 10H A repeat START Load SLA R or x 0 0 x As above condition has Load SLA W SLA W will be transmitted I2C bus been transmitted will be switched to Master Transmitter Mode 38H Arbitration lostin no I2DAT action 0 0 0 x l2C bus will be released it will enter NOT ACK bit or a slave mode no I2DAT action 1 0 0 xX A START condition will be transmitted when the bus becomes free 40h SLA R has been nol2DAT action 0 0 0 0 Data byte will be received NOT ACK transmitted ACK or bit will be returned has been received no jopaT action 0 0 0 1 Data byte will be received ACK bit or will be returned 48h SLA R has been No I2DAT action 1 0 0 x Repeated START will be transmitted transmitted NOT or ACK has been no I2DAT action 0 1 0 x STOP condition will be transmitted received or STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START or condition will be transmitted STO flag will be reset lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 82 of 136 UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual NXP Semiconductors Table 74 Master Receiver mode continued Status code Status of the I2C Application software respon
34. allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to us
35. authorization key present the MCU will perform a reset Flash write enable This device has hardware write enable protection This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 UCFG2 BOOTVEC and BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 109 of 136 NXP Semiconductors UMennnnns lt Document ID gt 16 15 16 16 P89LPC9201 9211 922A1 9241 9251 User manual is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA FMCON 0x08 FMDATA 0x96 The WE flag is CLEARED by writing the Clear Write Enable OBH command to FACON followed by a key value 96H to FMDATA or by a reset FMCON 0x0B FMDATA 0x96 The ISP function in this device sets the WE flag prior to calling the IAP routines The IAP function in this device executes a Clear Write Enable command following any write operation If the Write Enable function is active user code which calls IAP routines
36. be returned returned 78H Arbitration lostin nol2DAT action x 0 0 0 Data byte will be received and NOT SLA R W as or ACK will be returned master General ho I2DAT action x 0 0 1 Data byte will be received and ACK call address has will be returned been received ACK bit has been returned 80H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned own SLA address read data byte x 0 0 1 Data byte will be received ACK bit Data has been will be returned received ACK has been returned lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 83 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 75 Slave Receiver mode continued Status code Status of the 12C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 88H Previously Read data byte or 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or own SLA address general address Data nas Aii read data byte 0 0 0 1 Switched to not addressed SLA received NACK or mode Own SLA will be recognized has been returned general call address will be recognized if I2ADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be tr
37. bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 45 2 TOC T Timer or Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin 3 TOGATE Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set T1MO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the TiM1 Timer 1 mode see Table 45 6 T1C T _ Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin 7 T1GATE Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 53 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 44 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 TOM2 Reset x x x 0 x x x 0 Table 45 Timer Counter Auxiliary Mode register TAMOD address 8
38. bits 1 through 5 default to logic Os to enable the digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC9201 9211 922A1 9241 9251 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 45 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 32 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes l P0 0 POM1 0 POM2 0 KBIO CMP2 PO 1 POM1 1 POM2 1 KBI1 CIN2B Refer to Section 5 6 Port 0 and AD10 P89LPC9241 Analog Comparator functions for 9251 usage as analog inputs P0 2 POM1 2 POM2 2 KBI2 CIN2A AD11 P89LPC9241 9251 P0 3 POM1 3 POM2 3 KBI3 CIN1
39. buffer register Bit address Serial port 98H control Serial port BAH extended status register Bit functions and addresses Reset value MSB LSB Hex Binary g 3 P3M1 1 P3M1 0 03 1 xxxxxx11 2 E P3M2 1 P3M2 0 ooi XXXX XX00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 100 0000 0000 RTCPD VCPD ADPD I2PD SPD ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R_BK R_WD R_SF REX B RTCF RTCS1 RTCSO ERTC RTCEN 602461 011x xx00 ols 0000 0000 oole 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SM0 FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 Jenuew 13SM LGZ6 LYZ6 LYZZ6 LLZ6 LOZ69d168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew asn 600z Arenaqa4 G xx L0 AeY QEL dOn pamasa Syu Ily 6002 Ad dXNO lt q Juawinoog gt Table 4 Special function registers P89LPC9241 9251 continued indicates SFRs that are bit addressable Name SP TAMOD TCON THO THI TLO TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2 SFR addr Description Stack pointer 81H Timer 0 and 1 8FH auxiliary mode Bit address Timer 0 and 1 88H control Timer 0 high 8CH Timer 1 high 8DH Timer 0 low 8AH Timer 1 low 8BH Timer 0 and 1 89H mode Internal 96H oscillator trim reg
40. by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 66 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual TX clock J J jl jl J jl jl jl jl J J jl jl jl write to Il SBUF shift l l l l l l J jl fl transmit tart Tee wn Lo XO XX Xa XE X e X y stop pit TI d KO INTLO 0 INTLO 1 clock san RXD arwa A ot Ko Xr X02 Xs X
41. consists 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Five methods of programming this device are available e Parallel programming with industry standard commercial programmers NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 99 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application e Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite e A factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port e Note Flash erase program will be blocked if BOD FLASH is detected Vdd lt 2 4 V 16 4 Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and
42. data byte will be transmitted SLA R W as and ACK bit will be received master Own load data byte x 0 0 1 Data byte will be transmitted ACK SLA R has been bit will be received received ACK has been returned B8H Data byte in Load data byte or x 0 0 0 Last data byte will be transmitted I2DAT has been and ACK bit will be received transmitted ACK load data byte x 0 0 1 Data byte will be transmitted ACK has been received will be received lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 85 of 136 UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual NXP Semiconductors Table 76 Slave Transmitter mode continued Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA COH Data byte in No I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no recognition of own SLA or transmitted General call address NACK has been ng J2DAT action 0 0 0 1 Switched to not addressed SLA received or mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 no I2DAT action 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be reco
43. erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 105 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation 0 1 x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 x x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 16 19 Boot Vector register Table 106 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 value Table 107 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address the P89LPC9201 9211 922A1 9241 9251 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 5 7 reserved 16 20 Boot status register Table 108 Boot Status BOOTSTAT bit allocation
44. error occurs in the high voltage generator FMCMD 2 W Command byte bit 2 3 HVA R High voltage abort Set if either an interrupt or BOD FLASH is detected during a program or erase cycle FMCMD 3 W Command byte bit 3 4 7 R reserved 4 FMCMD 4 W Command byte bit 4 5 FMCMD 5 W Command byte bit 5 6 FMCMD 6 W Command byte bit 6 7 FMCMD 7 W Command byte bit 7 An assembly language routine to load the page register and perform an erase program operation is shown below PRERE ERRER EAKR EKER ERRE EREE ERE ERER EER ER EER R EREE ain pgm user code REALS EE EEL LE REL LE EN OR LER EAE LR RE RR EEE EERE aa Inputs R3 number of bytes to program byte 5 R4 page address MSB byte i R5 page address LSB byte i R7 pointer to data buffer in RAM byte Outputs R7 status byte x C clear on no error set on error z PRERE ERARE KARRE ERR ERORE REESE EK E E EERE E EER RRE K LOAD EQU 00H EP EQU 68H PGM_USER MOV FMCON LOAD load command clears page register MOV FMADRH R4 get high address MOV FMADRL R5 get low address MOV A R7 i MOV R0 A get pointer into R0 LOAD_PAGE MOV FMDAT R0 write data to page register INC RO point to next byte DJNZ R3 LOAD_PAGE do until count is zero MOV FMCON EP else erase amp program the page lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 102 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LP
45. feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution 2 11 Low power select The P89LPC9201 9211 922A1 9241 9251 is designed to run at 18 MHz CCLk maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 29 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 3 A D converter P89LPC9241 9251 3 1 General description The P89LPC9241 9251 has two analog to digital converter modules ADCO and ADC1 ADC1 is an 8 bit 4 channel multiplexed successive approximation analog to digital converter ADCO is dedicated for on chip temperature sensor which operates over wide temperature
46. in reset at power up until Vpp has reached its specified level Fig 9 quartz crystal or ceramic resonator iT XTAL1 eo it a i H XTAL2 002aad364 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Using the crystal oscillator lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 27 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual XTAL gt HIGH FREQUENCY MEDIUM FREQUENCY gt RTC XTAL2 lt LOW FREQUENCY gt ADC P89LPC9241 9251 L_ gt OSCCLK ow CCLK CPU RC OSCILLATOR RCCLK m4 WITH CLOCK DOUBLER 7 3728 MHz 14 7456 MHz 1 PCLK WATCHDOG l d WOT OSCILLATOR 400 kHz 5 PCLK J TIMER 0 AND 5 PEA I2C BUS UART 002aae428 Fig 10 Block diagram of oscillator control 2 8 Clock source switching on the fly P89LPC9201 9211 922A1 9241 9251 can implement clock source switch in any sources of watchdog oscillator 7 14MHz IRC oscillator crystal oscillator and external clock input during code is running CLKOK bit in register CLKCON is read only and used to indicate the clock switch status When
47. in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 21 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC9201 9211 922A1 9241 9251 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt 8 5 Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 22 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware e The low period of the TFn is in THn and should be between 1 and 254 and e The high period of the TFn is always 256 THn e Loading THn with 00h will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes Table 46 Timer Counter Control register TCON address 8
48. incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes are described later in this section Table 42 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1GATE T1C T T1iM1 T1MO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 43 Timer Counter Mode register TMOD address 89h
49. power cycle Vpp must fall below Vpor See P89LPC9201 9211 922A1 9241 9251 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources e External reset pin during power on or if user configured via UCFG1 e Power on detect e Brownout detect e Watchdog timer e Software reset e UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e A watchdog reset is similar to a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset previously set flag bits that have not been cleared will remain set lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 51 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual RPE UCFG1 6 a E WDTE UCFG1 7 watchdog timer reset n software reset SRST AUXR1 3 gt chip reset power on detect UART break detect EBAR AUXR1 6 __ brownout detect reset 002aae129 Fig 17 Block diagram of
50. sequence 116 16 3Watchdog clock source 118 16 4Watchdog Timer in Timer mode 119 16 5Power down operation 120 16 6Periodic wake up from power down without an external oscillator 120 17Additional features 120 17 1Software reset 121 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 134 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 17 2Dual Data Pointers 121 18Data EEPROM 122 18 1Data EEPROM read 123 18 2Data EEPROM write 123 18 3Hardware reset 124 18 4Multiple writes to the DEEDAT register 124 18 5Sequences of writes to DEECON and DEEDAT registers 124 18 6Data EEPROM Row Fill 124 18 7Data EEPROM Block Fill 125 19Flash memory 125 19 1General description 125 19 2Features 125 19 3Flash programming and erase 126 19 4Using Flash as data storage IAP Lite 126 19 5In circuit programming ICP 130 19 6ISP and IAP capabilities of the P89LPC9351 130 19 7Boot ROM 130 19 8Power on reset code execution 130 19 9Hardware activation of Boot Loader 131 19 10In system programming ISP 131 19 11Using the In system programming ISP 132 19 12In application programming IAP 135 19 13IAP authorization key 135 19 14Flash write enable 135 19 15Configuration byte protection 136 19 16IAP error status 136 19 17User configuration bytes 140 19 18User security bytes 141 19 19Boot Vector register 142 19 20Boot status register 142 N
51. the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog Timer if WOCLK WDCON 0 is logic 1 Could generate Interrupt or Reset either one can wake up the device e External interrupts INTO INT1 when programmed to level triggered mode e Keyboard Interrupt e Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock or watchdog timer is running during power down lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 49 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 36 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 Table 37 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 6 3 Power reduction modes PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or writ
52. the range defined by the ADCO boundary registers 4 SCAN1 When 1 selects single conversion mode auto scan or fixed channel for ADC1 5 SCC1 When 1 selects fixed channel continuous conversion mode for ADC1 6 BURST1 When 1 selects auto scan continuous conversion mode for ADC1 7 BNDI1 ADC1 boundary interrupt flag When set indicates that the converted result is outside of the range defined by the ADC1 boundary registers Table 22 A D Mode register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO INBNDO ENDAC1 ENDACO BSA1 BSAO Reset 0 0 0 0 0 0 0 0 Table 23 A D Mode register B ADMODB address Ath bit description Bit Symbol Description 0 BSAO ADCO Boundary Select All When 1 BNDIO will be set if any ADCO input exceeds the boundary limits When 0 BNDIO will be set only if the ADOO input exceeded the boundary limits 1 BSA1 ADC1 Boundary Select All When 1 BNDI1 will be set if any ADC1 input exceeds the boundary limits When 0 BNDI1 will be set only if the AD10 input exceeded the boundary limits 2 ENDACO when 0 selects ADC mode for ADCO Note This bit must be 0 when measure temperature sensor 3 ENDAC1 When 1 selects DAC mode for ADC1 when 0 selects ADC mode lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 37 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual
53. the record The P89LPC9201 9211 922A1 9241 9251 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 95 As a record is received by the P89LPC9201 9211 922A1 9241 9251 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC9201 9211 922A1 9241 9251 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 106 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual Table 95 In s
54. will need to set the Write Enable flag prior to each IAP write function call Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 UCFG2 BOOTVEC and BOOTSTAT This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes If the Configuration Write Protect bit CWP in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection CCP command in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming the Disable Clear Configuration Protection bit DCCP in BOOTSTAT 7 to a logic 1 When DCCP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programming modes IAP error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until t
55. will result in the device not entering ISP mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H RST tRL 002aaa912 Fig 41 Forcing ISP mode In system programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9201 9211 922A1 9241 9251 through the serial port This firmware is provided by NXP and embedded within each P89LPC9201 9211 922A1 9241 9251 device The NXP In System Programming facility has made in circuit programming in a
56. 0 0000 0000 00 0000 0000 STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 1111 1000 AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO EX0 00 0000 0000 EF EE ED EC EB EA E9 E8 EAD EST EC EKBI El2C ool 00x0 0000 Jenuewl 19Sf LGZ6 LYZ6 LYZZ6 LLZ6 LOZ69d168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew asn 6002 Aueniqa4 S Xx 10 AeY 9EL 0 02 lt q Juawinoog gt paniesal Syu Ily 6002 Ad dXNO Table 4 Special function registers P89LPC9241 9251 continued indicates SFRs that are bit addressable Name IPO IPOH IP1 IP1H KBCON KBMASK KBPATN PO P1 P3 POM1 POM2 P1M1 P1M2 Description SFR addr Bit address Interrupt B8H priority 0 Interrupt B7H priority 0 high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypad pattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PX0O ool x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PAD PST PC PKBI PI2C ool 00x0 0000 PADH PSTH PCH PKBIH PI2CH loo 00x0 0000 PATN KBIF oolt Xx
57. 0 erase and program cycles The cell is designed to optimize the erase and programming mechanisms P89LPC9201 9211 922A1 9241 9251 uses Vpp as the supply voltage to perform the Program Erase algorithms When voltage supply is lower than 2 4V the BOD FLASH is tripped and flash erase program is blocked 16 2 Features e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application e Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite e Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory e Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user e Programming and erase over the full operating voltage range e Read Programming Erase using ISP IAP or IAP Lite e Any flash program operation in 2 ms 4 ms for erase program e Programmable security for the code in the Flash for each sector e gt 100 000 typical erase program cycles for each byte e 10 year minimum data retention 16 3 Flash programming and erase The P89LPC9201 9211 922A1 9241 9251 program memory
58. 009 130 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 3 2 1 2Channel selection dependency 30 3 2 2Temperature sensor 30 3 2 3ADC operating modes 31 3 2 3 1Fixed channel single conversion mode 31 3 2 3 2Fixed channel continuous conversion mode 31 3 2 3 3Auto scan single conversion mode 32 3 2 3 4Auto scan continuous conversion mode 32 3 2 3 5Dual channel continuous conversion mode 32 3 2 3 6Single step mode 33 3 2 3 7Conversion mode selection bits 33 3 2 4Conversion start modes 33 3 2 4 1Timer triggered start 33 3 2 4 2Start immediately 33 3 2 4 3Edge triggered 33 3 2 4 4Dual start immediately 34 3 2 5Boundary limits interrupt 34 3 2 6DAC output to a port pin with high output impedance 34 3 2 7Clock divider 34 3 2 81 O pins used with ADC functions 34 3 2 9Power down and Idle mode 34 Alnterrupts 39 4 1 nterrupt priority structure 40 4 2External Interrupt pin glitch suppression 40 51 O ports 42 5 1Port configurations 43 5 2Quasi bidirectional output configuration 43 5 3Open drain output configuration 44 5 4Input only configuration 45 5 5Push pull output configuration 45 5 6Port 0 and Analog Comparator functions 46 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 131 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 5 7Additional port features 46 6P
59. 09 Fig 47 Comparator input and output connections111 Fig 48 Comparator configurations Suppose PGA1 is disabled or gain 1 112 Fig 49 Watchdog Prescaler116 Fig 50 Watchdog Timer in Watchdog Mode WDTE 1 119 Fig 51 Watchdog Timer in Timer Mode WDTE 0 120 Fig 52 Forcing ISP mode131 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 129 of 136 NXP Semiconductors UMennnnns 21 Contents P89LPC9201 9211 922A1 9241 9251 User manual lt Document ID gt 1Introduction 3 1 1Pin configuration 3 1 2Pin description 4 1 3Logic symbols 8 1 4Block diagram 9 1 5Special function registers 10 1 6Memory organization 21 2Clocks 22 2 1Enhanced CPU 22 2 2Clock definitions 22 2 2 1Oscillator Clock OSCCLKk 22 2 3External crystal oscillator option 22 2 3 1Low speed oscillator option 22 2 3 2Medium speed oscillator option 23 2 3 3High speed oscillator option 23 2 4Clock output 23 2 5On chip RC oscillator option 23 2 6Watchdog oscillator option 24 2 7External clock input option 24 2 8Clock sources switch on the fly 25 2 9Oscillator Clock OSCCLK wake up delay 26 2 10CPU Clock CCLK modification DIVM register 26 2 11Low power select 27 3A D converter 27 3 1General description 27 3 2A D features 27 3 2 1Programmable Gain Amplifier PGA 28 3 2 1 1PGA calibration 29 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2
60. 1 922A1 indicates SFRs that are bit addressable Name PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP TAMOD Description SFR addr Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Portdata 99H buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H Timer 0 and 1 8FH auxiliary mode Bit functions and addresses Reset value MSB LSB Hex Binary SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 100 0000 0000 RTCPD VCPD I2PD SPD oolt 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R_BK R_WD R_SF R_EX 3 RTCF RTCS1 RTCSO ERTC RTCEN 60UJIS1 011x xx00 ool 0000 0000 ools 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 Tl RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 T1M2 TOM2 00 XXX0 xxx0 Jenuewl 13SM LGZ6 LYZ6 LYZZ6 LLZ6 LOZ69d168d lt uuuuu gt NN S10 9NpuodIW S dXN jenuew asn 600z Areniga4 G xx L0 Ae lt q Juawinoog
61. 1 User manual Table 57 CCU prescaler control register high byte TPCR2H address CBh bit allocation 64 Table 58 CCU prescaler control register high byte TPCR2H address CBh bit description 64 Table 59 CCU prescaler control register low byte TPCR2L address CAh bit allocation 64 Table 60 CCU prescaler control register low byte TPCR2L address CAh bit description 64 Table 61 CCU control register 0 TCR20 address C8h bit allocation 65 Table 62 CCU control register 0 TCR20 address C8h bit description 65 Table 63 Capture compare control register CCRx address Exh bit allocation 66 Table 64 Capture compare control register CCRx address Exh bit description 66 Table 65 Event delay counter for input capture 67 Table 66 Output compare pin behavior 69 Table 67 CCU control register 1 TCR21 address F9h bit allocation 70 Table 68 CCU control register 1 TCR21 address FQh bit description 70 Table 69 CCU interrupt status encode register TISE2 address DEh bit allocation 72 Table 70 CCU interrupt status encode register TISE2 address DEh bit description 72 Table 71 CCU interrupt flag register TIFR2 address E9h bit allocation 73 Table 72 CCU interrupt flag register TIFR2 address E9h bit description 73 Table 73 CCU interrupt control register TICR2 address C9h bit allocation 73 Table 74 CCU interrupt control register TICR2 address C9h bit description 73 Table 75 UART SFR addresses 75 Table 76 UA
62. 41 9251 through a two wire serial interface NXP has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 103 of 136 NXP Semiconductors UMennnnns 16 6 16 7 16 8 P89LPC9201 9211 922A1 9241 9251 User manual board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature ISP and IAP capabilities of the P89LPC9201 9211 922A1 9241 9251 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 UCFG2 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user application Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash program memory This Boot ROM contains routines which handle all of the low le
63. 8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 47 Timer Counter Control register TCON address 88h bit description Bit Symbol Description o ITO Interrupt 0 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 IM Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 55 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 47 Timer Counter Control register TCON address 88h bit description continued Bit Symbol Description 3 1E1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared i
64. 9 Boot Vector BOOTVEC bit description 142 Table 140 Boot Status BOOTSTAT bit allocation 142 Table 141 Boot Status BOOTSTAT bit description 143 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 126 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 142 Instruction set summary 144 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 127 of 136 NXP Semiconductors UMennnnns 20 Figures P89LPC9201 9211 922A1 9241 9251 User manual lt Document ID gt Fig 1 TSSOP28 pin configuration3 Fig 2 PLCC28 pin configuration4 Fig 3 P89LPC9351 logic symbol8 Fig 4 Block diagram9 Fig 5 P89LPC9351 memory map21 Fig 6 Using the crystal oscillator24 Fig 7 Block diagram of oscillator control25 Fig 8 ADC block diagram28 Fig 9 PGA block diagram29 Fig 10 Interrupt sources interrupt enables and power down wake up sources42 Fig 11 Quasi bidirectional output44 Fig 12 Open drain output45 Fig 13 Input only45 Fig 14 Push pull output46 Fig 15 Block diagram of reset53 Fig 16 Timer counter 0 or 1 in Mode 0 13 bit counter 57 Fig 17 Timer counter 0 or 1 in mode 1 16 bit counter 57 Fig 18 Timer counter 0 or 1 in Mode 2 8 bit auto reload 57 Fig 19 Timer counter 0 Mode 3 two 8 bit counters 58 Fig 20 Timer counter 0 or 1 in mode 6 PWM auto reload 58 Fig 21 Real time clock system timer block dia
65. 9211 922A1 9241 9251 User manual PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of watchdog load register which can be the range of 0 to 255 The minimum number of tclks is tcelks 2 04 1 4 1 33 4 The maximum number of tclks is telks 2 255 1 1 1048577 5 Table 88 shows sample P89LPC9201 9211 922A1 9241 9251 timeout values Table 86 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO E WDRUN WDTOF WDCLK Reset 1 1 1 X x 1 1 0 1 Table 87 Watchdog Timer Control register WDCON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see Section 14 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 14 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO 6
66. 9241 9251 User manual Status code Status of the 12C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO sl AA AOH A STOP condition No I2DAT action 0 0 0 0 Switched to not addressed SLA or repeated mode no recognition of own SLA or START condition General call address hasbeenreceived no 12DAT action 0 0 0 1 Switched to not addressed SLA while still mode Own slave address will be addressed as recognized General call address SLA REC or will be recognized if I2ADR 0 1 SLA TRX no I2DAT action 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Table 76 Slave Transmitter mode Status code Status of the I C Application software response Next action taken by I C I2STAT hardware to from I2DAT_ _to I2CON hardware STA STO Si AA A8h Own SLA R has Load data byte or x 0 0 0 Last data byte will be transmitted been received and ACK bit will be received ACK has been load data byte x 0 0 1 Data byte will be transmitted ACK returned will be received BOh Arbitration lostin Load data byte or x 0 0 0 Last
67. Anin00 Anin01 Xe 2 1 MUX Anino2 r Anin03 SAR m e jH i Vsen a a es CONTROL f input MUX LOGIC AD10 Anin10 comp AD11 a t AD12 i SAR AD13 Anin13 T 002aae432 Fig 11 ADC block diagram P89LPC9241 9251 3 2 1 Temperature sensor An on chip wide range temperature sensor is integrated It provides temperature sensing capability of 40 C 85 C ADCO is dedicated for the temperature sensor And the temperature sensor is measured through Anin03 To get an accurate temperature value it is necessary to get supply voltage by measuring the internal reference voltage V ef bg first Temperature sensor voltage can be calculated by the following formula Veen Asen Vrep bgy Arep bg 1 In formula 1 Aref bg is the A D converting result of Vref og and Asen is the A D converting result of Ven Temperature Sensor transfer function can be shown in the following formula Vien mx temp b where m 11 3 mV C b 890 mV 2 Temperature Sensor usage steps Config TSEL1 and TSELO as 01 to choose internal reference voltage Using ADC to get converting result as Aret Config TSEL1 and TSELO as 10 to choose temperature sensor Using ADC to get converting result as Agen Calculate Vsen with formula 1 OO A N Calculate Temperature with formula 2 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 31 of 136
68. B AD12 P89LPC9241 9251 P0 4 POM1 4 POM2 4 KBI4 CIN1A AD13 DAC1 P89LP C9241 9251 P0 5 POM1 5 POM2 5 KBI5 CMPREF P0 6 POM1 6 POM2 6 KBI6 CMP1 PO 7 POM1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 P1M2 1 RXD P1 2 P1M1 2 P1M2 2 TO SCL Input only or open drain l P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INT1 P1 5 P1M1 5 P1M2 5 RST P1 6 P1M1 6 P1M2 6 P1 7 P1M1 7 P1M2 7 P3 0 P3M1 0 P3M2 0 CLKOUT XTAL2 P3 1 P3M1 1 P3M2 1 XTAL1 6 Power monitoring functions The P89LPC9201 9211 922A1 9241 9251 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect 6 1 Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level Enhanced BOD has 3 independent functions BOD reset BOD interrupt and BOD FLASH BOD reset will cause a processor reset and it is always on except in total power down mode It could not be disabled in software BOD interrupt will generate an interrupt and could be enabled or disabled in software lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 46 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual BOD reset and BOD inter
69. Bit 7 6 5 4 3 2 1 0 Symbol DCCP CWP AWP 7 BSB Factory default 0 0 0 0 0 0 0 1 value lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 116 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 109 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB 1 4 5 AWP 6 CWP 7 DCCP Description Boot Status Bit If programmed to logic 1 the P89LPC9201 9211 922A1 9241 9251 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector reserved Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA Disable Clear Configurat
70. C9201 9211 922A1 9241 9251 User manual MOV R7 FMCON copy status for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD CLR c clear error flag if good RET sand return BAD SETB Cc set error flag RET sand return A C language routine to load the page register and perform an erase program operation is shown below include lt REG9351 H gt unsigned char idata dbytes 64 data buffer unsigned char Fm_stat status result bit PGM_USER unsigned char unsigned char bit prog_fail void main prog_fail PGM_USER 0x1F 0xC0 bit PGM_USER unsigned char page_hi unsigned char page_lo define LOAD0x00 clear page register enable loading define EP0x68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page_hi FMADRL page_lo write my page address to addr regs for 1 0 1 lt 64 i 1 1 FMDATA dbytes i FMCON EP erase amp prog page command Fm_stat FMCON read the result status if Fm_stat amp Ox0F 0 prog_fail 1 else prog_fail 0 return prog_fail 16 5 In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9201 9211 922A1 92
71. CFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 Jenuew 19Sf 1S26 LV26 LVCC6 L 26 LOC6Od 168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew 1asQ 10 A34 6002 Au 9EL 0 EZ lt q Juawinoog gt pamasa Syu Ily 6002 A a dXNO Table 5 Extended special function registers P89LPC9241 9251 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGo 21 configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 Fosco B register TPSCON Temperature FFCAH TSEL1 TSELO 00 00000000 sensor control register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs 2 The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 Jenuewl 19S LGZ6 LYZ6 LYZZ6 LLZ6 LO0OZ69d168d lt UUUUUPINN SIOJONPUOSIWSS dXN NXP Semiconductors UMennn
72. CPn CNn OEn 101 CINnB CINnB COn VpReF 1 23 V gt San Vper 1 23 V m En 002aaa625 002aaa626 g CPn CNn OEn 110 h CPn CNn OEn 1 1 1 Fig 37 Comparator configurations Suppose PGA1 is disabled or gain 1 12 5 Comparators configuration example The code shown below is an example of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the CMP1 pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on CIN1A CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL POM1 030h for analog functions CIN1A CMPREF MOV CMP1 024h Turn on comparator 1 and set up for Positive input on CINIA Negative input from CMPREF pin Output to CMP1 pin enabled CALL delayl0us The comparator needs at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 89 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual SETB EC Enable the comparator interrupt SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case before returning 13 Keypad interrupt KBI The Keypad Interrupt function is intended primarily to
73. EDGEO 0 while in edge triggered mode An edge conversion start is triggered by a rising edge on P1 4 when EDGEO 1 while in edge triggered mode Timer Trigger Mode 0 Selects either stop mode TMMO 0 or timer trigger mode TMM0O 1 when the ADCS01 and ADCS00 bits 00 Enable A D Conversion complete Interrupt 0 When set will cause an interrupt if the ADCIO flag is set and the A D interrupt is enabled Enable A D boundary interrupt 0 When set will cause an interrupt if the boundary interrupt 0 flag BNDIO is set and the A D interrupt is enabled Table 18 A D Control register 1 ADCON1 address 97h bit allocation Bit Symbol Reset 7 6 ENBI1 ENADCI1 0 0 5 4 3 2 1 0 TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 0 0 0 0 0 0 Table 19 A D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 1 0 ADCS11 ADCS10 A D start mode bits see below 00 Timer Trigger Mode when TMM1 1 Conversions starts on overflow of Timer 0 When TMM1 0 no start occurs stop mode 01 Immediate Start Mode Conversion starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGE1 occurs 11 Dual Immediate Start Mode Both ADC A s start a conversion immediately 2 ENADC1 Enable A D channel 1 When set 1 enables ADC1 Must also be set for D A operation of this channel 3 ADCI1 A D Conversion complete Interrupt 1 Set when any conversion or set of mult
74. ENT1 ENTO SRST 0 DPS 00 0000 00x0 function register Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 0000 0000 BRGROZ Baud rate BEH 00 0000 0000 generator 0 rate low BRGRi2 Baud rate BFH 00 0000 0000 generator 0 rate high BRGCON Baud rate BDH SBRGS BRGEN 00l xxxx xx00 generator 0 control CMP1 Comparator 1 ACH E CE1 CP1 CN1 OE1 CO1 CMF1 00M xx00 0000 control register CMP2 Comparator 2 ADH CE2 CP2 CN2 OE2 CO2 CMF2 ool xx00 0000 control register DIVM CPU clock 95H 00 0000 0000 divide by M control DPTR Data pointer 2 bytes DPH Data pointer 83H 00 0000 0000 high DPL Data pointer 82H 00 0000 0000 low FMADRH Program flash E7H 00 0000 0000 address high FMADRL Program flash E6H 00 0000 0000 address low SIOJONPUOSIWIS dXN Jenuew 19Sf 1S26 LV26 LVCC6 L 26 LOC6Od 168d lt UUUUUPINN jenuew asn 600z Asenaga4 G xx L0 AeY 9EL JO ZL lt q u wnooq gt pamasa Syu Ily 6002 A a dXNO Table 2 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMCON Program flash E4H BUSY HVA HVE SV Ol 70 0111 0000 control Read Program flash E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 control Write FMDATA Program flash E5H 00 0000 0000 data I2ADR I2C bus slave DBH I2ADR 6 I2ADR 5 I2ADR 4
75. February 2009 28 of 136 NXP Semiconductors UMennnnns Table 11 P89LPC9201 9211 922A1 9241 9251 User manual Oscillator type selection for clock switch FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz a 5 011 Internal RC oscillator 7 373 MHz a 1 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz 2 9 Oscillator Clock OSCCLK wake up delay The P89LPC9201 9211 922A1 9241 9251 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 1024 OSCCLK cycles plus 60 us to 100 us If the clock source is the internal RC oscillator the delay is 200 us to 300 us If the clock source is watchdog oscillator or external clock the delay is 32 OSCCLK cycles 2 10 CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range of fosc to fogo 510 for N 0 CCLK fosc This
76. Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 45 1 3 reserved 4 T1M2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 45 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer AOTLn A6 serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter AOTHn A6 and AOTLn A6 are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5 111 Reserved User must not configure to this mode 5 7 reserved 8 1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 18 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it set
77. I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 address register Bit address DF DE DD DC DB DA D9 D8 I2CON I2C bus control D8H I2EN STA STO SI AA CRSEL 00 x000 00x0 register I2DAT 1 C bus data DAH register I2SCLH Serial clock DDH 00 0000 0000 generator SCL duty cycle register high I2SCLL Serial clock DCH 00 0000 0000 generator SCL duty cycle register low I2STAT I2C bus status D9H STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 1111 1000 register Bit address AF AE AD AC AB AA AQ A8 IENO Interrupt A8H EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 0000 0000 enable 0 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt E8H EST EC EKBI El2c ool 00x0 0000 enable 1 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x000 0000 priority 0 Jenuewl 19S LGZ6 LYZ6 LYZZ6 LLZ6 LOZ69d168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew asn go0z Areniqo4 S xx 19 Ay 9EL JO EL lt q Juawinoog gt pamasa Syu Ily 6002 Ad dXNO Table 2 indicates SFRs that are bit addressable Special function registers P89LPC9201 9211 922A1 Name IPOH IP1 IP1H KBCON KBMASK KBPATN PO Pi P3 POM1 POM2 P1M1 P1M2 P3M1 P3M2 Description SFR addr Interrupt B7H priority 0 high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H re
78. MER eal eal CONFIGURABLE 1 0s X C AND OSCILLATOR PORT 0 TIMER 0 TO PO 7 0 e CONFIGURABLE I Os C gt C TIMER 1 T1 gee CIN2B INTERRUPT COMPARATORS CINTA CMP1 CIN1B Nn OSCILLATOR DIVIDER Sock XTAL1 ona CONFIGURABLE ON CHIP RC POWER MONITOR e E SCLER OSCILLATOR WITH POWER ON RESET PE CLOCK DOUBLER BROWNOUT RESET XTAL2 002aae421 Fig 6 P89LPC9201 9211 922A1 Block diagram lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 8 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Fig 7 P89LPC9241 9251 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU a 4 kB 8 KB TXD coveriasH Y K UART ee internal 256 BYTE bus y K REAL TIME CLOCK DATA RAM SYSTEMTIMER PORT 3 SCL 2 Pario T CONFIGURABLE Vos K 1K I C BUS SDA PORT 1 WATCHDOG TIMER P1 7 0 F CONFIGURABLE I Os C C AND OSCILLATOR l PORTO TIMER 0 TO Po 7 0 CONFIGURABLE I Os C y TIMER 1 Ti CMP CINZB KEYPAD lt gt ANALOG CIN2A INTERRUPT COMPARATORS CINTA CMP1 CIN1B AD10 ADC1 DAC1 AD11 TEMPERATURE AD12 PROGRAMMABLE CPU SENSOR AD13 OSCILLATOR DIVIDER ogg L DAC1 XTAL1 CRYSTAL ON CHIP RC POWER MONITOR CONFIGURABLE OR E E SCOR OSCILLATOR WITH POWER ON RESET RESONATOR CLOCK DOUBLER BROWNOUT RESET XTAL2 P89LPC9241 9251 Block diagram 002aae422
79. RT baud rate generation 75 Table 77 Baud Rate Generator Control register BRGCON address BDh bit allocation 76 Table 78 Baud Rate Generator Control register BRGCON address BDh bit description 76 Table 79 Serial Port Control register SCON address 98h bit allocation 77 Table 80 Serial Port Control register SCON address 98h bit description 77 Table 81 Serial Port modes 77 Table 82 Serial Port Status register SSTAT address BAh bit allocation 77 Table 83 Serial Port Status register SSTAT address BAh bit description 78 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 124 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual Table 84 FE and RI when SM2 1 in Modes 2 and 3 81 Table 85 Slave 0 1 examples 84 Table 86 Slave 0 1 2 examples 84 Table 87 12C data register I2DAT address DAh bit allocation 86 Table 88 12C slave address register I2ADR address DBh bit allocation 86 Table 89 12C slave address register IZADR address DBh bit description86 Table 90 12C Control register I2CON address D8h bit allocation 87 Table 91 12C Control register I2CON address D8h bit description 87 Table 92 12C Status register I2STAT address D9h bit allocation 88 Table 93 12C Status register I2STAT address D9h bit description 88 Table 94 12C clock rates selection 89 Table 95 12C Control register I2CON address D8h 89
80. Rev 01 xx 5 February 2009 39 of 136 NXP Semiconductors UMennnnns 4 2 P89LPC9201 9211 922A1 9241 9251 User manual These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If ITn 0 external interrupt n is triggered by a low level detected at the INTn pin If ITn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level se
81. Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGRO Baud Rate Generator Rate Low Byte BEH BRGCON Baud Rate Generator Control BDH Baud Rate generator and selection The P89LPC9201 9211 922A1 9241 9251 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 24 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 62 of 136 NXP Semiconductors UMennnnns lt Document ID gt 10 8 10 9 P89LPC9201 9211 922A1 9241 9251 User manual Table 52 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1_ Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS
82. This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9201 9211 922A1 9241 9251 has 2 kB 4 kB 8 kB of on chip Code memory Table 6 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 24 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 2 Clocks 2 1 Enhanced CPU The P89LPC9201 9211 922A1 9241 9251 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles 2 2 Clock definitions The P89LPC9201 9211 922A1 9241 9251 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency see Figure 10 and Section 2 10 Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instruct
83. XP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 135 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 20Instruction set 144 21Legal information 147 21 1Definitions 147 21 2Disclaimers 147 21 3Trademarks 147 22Tables 148 23Figures 151 24Contents 152 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 136 of 136
84. ZCON address D8h bit description Bit Symbol Description 0 CRSEL SCL clock selection When set 1 Timer 1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL 1 reserved 2 AA The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The Adown slave address A6 has been received 2 The general call address has been received while the general call bit GC in IZADR is set 3 A data byte has been received while the 2C interface is in the Master Receiver Mode 4 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 12C interface is in the Master Receiver Mode 2 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 74 of 136 NXP Semiconductors UMennnnns lt Document ID gt 11 5 P89LPC9201 9211 922A1 9241 9251 User manual Table 67 12C Control register IZCON address D8h bit description continued Bit Symbol Description 3 SI 12C Interrupt Flag Thi
85. aX E X e X Y stop RI S receive 002aaa926 Fig 26 Serial Port Mode 1 only single transmit buffering case is shown 10 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF TX clock j j j j j j j j ji j j j ji ji write to fl SBUF shift j l j I I l j l j j l transmit start g PEDER bz Xba X BAX BS_X EEE a E INTLO 0 INTLO 1 RX 5 olock lL M M AA M M A AOO OOO AO OO N RXD era A o C O X E XE XE XE X X e Y stop e S j a SMODO 0 SMODO 1 receive 002aaa927 Fig 27 Serial Port Mode 2 or 3 only single transmit buffering case is shown 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 67 of 136 NXP Semiconductors UMennnnns lt Document ID gt 10 14 10 15 10 16 10 17 P89LPC9201 9211 922A1 9241 9251 User manual
86. abled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various special functions as described below P0 0 CMP2 3 0 P0 0 Port 0 bit 0 KBIO O CMP2 Comparator 2 output l KBIO Keyboard input 0 P0 1 CIN2B 26 0 P0 1 Port 0 bit 1 KBI1 AD10 l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 l AD10 ADC1 channel 0 analog input P89LPC9241 9251 P0 2 CIN2A 25 0 P0 2 Port 0 bit 2 KBI2 AD11 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 l AD11 ADC1 channel 1 analog input P89LPC9241 9251 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 4 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 1 Pin description continued Symbol Pin Type Description TSSOP20 DIP20 P0 3 CIN1B 24 0 P0 3 Port 0 bit 3 High current source KBIS AD12 l CIN1B Comparator 1 positive input B l KBI3 Keyboard input 3 l AD12 ADC1 channel 2 analog input P89LPC9241 9251 P0 4 CIN1A 23 O P0 4 Port 0 bit 4 High current source KBI4 DAC1 AD13 l CIN1A Comparator 1 positive input A l KBI4 Keyboard
87. after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset sources that affect these SFRs are power on reset and watchdog reset Jenuewl 13SM LGZ6 LYZ6 LYZZ6 LLZ6 LOZ69d168d lt UUUUUPINN 6002 Areniqo4 S XX L0 AY yenuew 1asq 9EL 0 OL lt q Juawinoog gt pamasa Syu Ily 6002 Ad dXNO Table 3 Extended special function registers P89LPC9201 9211 922A1 1 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGo 21 configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO EBI register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs 2 The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes fr
88. ansmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 90H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned General call Data fead data byte x 0 0 1 Data byte will be received and ACK has been will be returned received ACK has been returned 98H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or General call Data General call address has pee read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own slave address will be has been returned recognized General call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 84 of 136 NXP Semiconductors UMennnnns Table 75 Slave Receiver mode continued P89LPC9201 9211 922A1
89. anual Table 8 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol 0 TRIM O 1 TRIM 1 2 TRIM 2 3 TRIM 3 4 TRIM 4 5 TRIM 5 6 ENCLK 7 RCCLK Description Trim value Determines the frequency of the internal RC oscillator During reset these bits are loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of this register care should be taken to preserve the current TRIM value by reading this register modifying bits 6 or 7 as required and writing the result to this register when 1 CCLK is output on the XTAL2 pin provided the crystal oscillator is not being used when 1 selects the RC Oscillator output as the CPU clock CCLK This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle 2 6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz calibrated to 5 at room temperature This oscillator can be used to save power when a high clock frequency is not needed 2 7 External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 18 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 Mhz BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device
90. arry set on error clear on no error NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 112 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 97 IAP function calls continued IAP function IAP call parameters Misc Read Input parameters ACC 03h R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page Input parameters requires Adkey Ad ACC 04h R4 address MSB R5 address LSB R7 OOH erase page or 01H erase sector Return parameter s R7 data Carry set on error clear on no error lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 113 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 97 IAP function calls continued IAP function IAP call parameters Read Sector CRC Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear o
91. as received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SM1 With SMO defines the serial port mode see Table 57 7 SMO FE The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMOD0 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMOD0 is logic 0 default mode on any reset Table 57 Serial Port modes SMO SM1 UART mode UART baud rate 00 Mode 0 shift register CCLK default mode on any reset 01 Mode 1 8 bit VART Variable see Table 52 10 Mode 2 9 bit UART CCLK 5 or CCLKY 6 11 Mode 3 9 bit UART Variable see Table 52 Table 58 Serial Port Status register SSTAT address BAh bit allocation
92. ble 35 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 48 of 136 NXP Semiconductors UMennnnns Table 35 P89LPC9201 9211 922A1 9241 9251 User manual Power reduction modes PMOD1 PCON 1 0 0 PMODO PCON 0 0 1 Description Normal mode default no power reduction Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9201 9211 922A1 9241 9251 exits Power down mode via any reset or certain interrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set External interrupts should be programmed to level triggered mode to be used to exit Power down mode In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was ent
93. ble 39 BOD Trip points configuration48 Table 40 BOD Reset and BOD Interrupt configuration49 Table 41 Power reduction modes 50 Table 42 Power Control register PCON address 87h bit allocation 51 Table 43 Power Control register PCON address 87h bit description 51 Table 44 Power Control register A PCONA address B5h bit allocation 51 Table 45 Power Control register A PCONA address B5h bit description 51 Table 46 Reset Sources register RSTSRC address DFh bit allocation 53 Table 47 Reset Sources register RSTSRC address DFh bit description 53 Table 48 Timer Counter Mode register TMOD address 89h bit allocation 54 Table 49 Timer Counter Mode register TMOD address 89h bit description 54 Table 50 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation 55 Table 51 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description 55 Table 52 Timer Counter Control register TCON address 88h bit allocation 56 Table 53 Timer Counter Control register TCON address 88h bit description 56 Table 54 Real time Clock System Timer clock sources 60 Table 55 Real time Clock Control register RTCCON address D1h bit allocation 61 Table 56 Real time Clock Control register RTCCON address D1h bit description 62 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 123 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 925
94. c 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 61 of 136 NXP Semiconductors UMennnnns lt Document ID gt 10 4 10 5 10 6 10 7 P89LPC9201 9211 922A1 9241 9251 User manual the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved The baud rate is programmable to either 14 or 1 2 of the CCLK frequency as determined by the SMOD1 bit in PCON Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 SFR space The UART SFRs are at the following locations Table 51 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON
95. ce voltage An internal reference voltage Vretpg may supply a default reference when a single comparator input pin is used Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet for specifications Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator Comparators and power reduction modes Either or both comparators may remain enabled when Power down mode or Idle mode is acti
96. configuration is shown in Figure 16 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet Dynamic characteristics for glitch filter specifications lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 44 of 136 NXP Semiconductors UMennnnns lt Document ID gt 5 6 5 7 P89LPC9201 9211 922A1 9241 9251 User manual VDD strong pin port latch N data input data lt 4 l TOE glitch rejection 002aaa917 Fig 16 Push pull output Port 0 and Analog Comparator functions The P89LPC9201 9211 922A1 9241 9251 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 15 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins P0 1 through P0 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD
97. ct the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock then the RTC will use CCLK as its clock source NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 58 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 9 2 Changing RTCS1 RTCSO RTCS1 RTCSO cannot be changed if the RTC is currently enabled RTCCON O 1 Setting RTCEN and updating RTCS1 RTCSO may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 RTCSO 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device 9 3 1 Real time clock read back Users can read RTCDATH and RTCDATL registers and get the 16 bit counter portion of the RTC 9 4 Reset sources affecting the Real time clock Only power on reset and watchdog reset will reset the Real time Clock and its associated SFRs to their default state Table 48 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 0 00 High frequency crystal High frequency crystal DIVM 01 10 11 High fr
98. cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 95 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual MOV WFEED1 0A5H MOV WFEED2 05AH PCLK Watchdog PRESCALER Lo 8 BIT DOWN esei oscillator COUNTER A A A H crystal ee E i oscillator i i ji 1 ii J ji J SHADOW REGISTER i XTALWD WDCON A7H PRE2 PRE1 WDRUN TGF WDCLK prez pre1 preo worn woror wocr 002aae093 Fig 39 Watchdog Timer in Watchdog Mode WDTE 1 14 4 Watchdog Timer in Timer mode Figure 40 shows the Watchdog Timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in th
99. dge SDA LOW OO from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition 002aaa930 Fig 31 Format of Master Receiver mode After a repeated START condition 1 C bus may switch to the Master Transmitter Mode Ps TRL om Ta Be om TF logic 0 write L data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW C from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 32 A Master Receiver switches to Master Transmitter after sending Repeated Start 11 6 3 Slave Receiver mode In the Slave Receiver Mode data bytes are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register I2ADR and the 2C Control Register I2CON should be configured as follows Table 72 1 C Control register IZCON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 1 CRSEL is not used for slave mode I2EN must be set 1 to enable I2C function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After IZADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit w
100. dir data Exclusive OR immediate to direct byte 3 2 63 CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn dir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 to A7 MOV Ri data Move immediate to indirect memory 2 1 76 to 77 MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC toA 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 to E3 MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 Co POP dir Po
101. direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJUNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 to BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 to B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 120 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 18 Legal information lt Document ID gt 18 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 18 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warrant
102. e In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 79 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 7 KBPATN 6 KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O Reset 1 1 1 1 1 1 1 1 Table 80 Keypad Pattern register KBPATN address 93h bit description Bit Symbol Access Description 0 7 KBPATN 7 0 R W Pattern bit 0 bit 7 Table 81 Keypad Control register KBCON address 94h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 5 z z PATN_SEL KBIF Reset xX X xX X xX X 0 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 90 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 82 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN_SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved Table 83 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit
103. e performed and the result placed in the result register which corresponds to the selected input channel See Table 12 An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional conversion results will again cycle through the result registers of the selected channels overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the BURSTx bit in the ADMODA register 3 2 2 5 Dual channel continuous conversion mode The any combination of two of the four input channels can be selected for conversion The result of the conversion of the first channel is placed in the first result register The result of the conversion of the second channel is placed in the second result register The first channel is again converted and its result stored in the third result register The second channel is again converted and its result placed in the fourth result register See Table 14 An interrupt is generated if enabled after every set of four conversions two conversions per channel This mode is selected by setting the SCCx bit in the ADMODA register Table 14 Result registers and conversion results for dual channel continuous conversion mode Result register Contains ADxDATO First channel first conversion result ADxDAT1 Second channel first conversion result ADxDAT2 Fir
104. eak condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 63 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 Table 55 Serial Port Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO FE SM1 SM2 REN TB8 RB8 Tl RI Reset xX xX xX xX xX xX 0 0 Table 56 Serial Port Control register SCON address 98h bit description Bit Symbol Description Oo RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 it is set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that w
105. ed 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Manufacturer Id 11 Device ld 12 Derivative Id Example 0100000312EA 04 Erase Sector Page 03xxxx04ssaaaacc Where xxxx required field but value is a Addon Adt care A6 aaaa sector page address ss 01 erase sector ss 00 erase page cc checksum Example 03000004010000F8 05 Read Sector CRC 01xxxx05aacc Where xxxx required field but value is a Addon Adt care Ad aa sector address high byte cc checksum Example 0100000504F6 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 108 of 136 NXP Semiconductors UMennnnns lt Document ID gt 16 12 16 13 16 14 P89LPC9201 9211 922A1 9241 9251 User manual Table 95 In system Programming ISP hex record formats continued Record type Command daia function 06 Read Global CRC 0Oxxxx06cc Where xxxx required field but value is a Addon Adt care Ad cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where xxxx required field but value is a Addon Adt care A6 HH high byte of timer LL low byte of timer cc checksum Example 02000007FFFFF9 08 Reset MCU 0Oxxxx08cc Where xxxx required field but value is a Addon Adt care A6 cc chec
106. el 0 1 0 Fixed channel continuous continuous Dual channel Dual channel continuous continuous 1 0 0 Auto scan 1 0 0 Auto scan continuous continuous Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMMx bit and the ADCSx1 and ADCSx0 bits See Table 17 and Table 19 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCSx1 and ADCSx0 bits in the ADCONx register See Table 17 and Table 19 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCSx1 and ADCSx0 bits in the ADCONx register See Table 17 and Table 19 Boundary limits interrupt Each of the A D converters has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An int
107. entiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 71 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 11 I2C interface The C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultan
108. eously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 29 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus e Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 1 C bus will not be released The P89LPC9201 9211 922A1 9241 9251 device pro
109. equency crystal DIVM 1 00 High frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 001 0 00 Medium frequency crystal Medium frequency crystal 01 DIVM 10 11 Medium frequency crystal DIVM 1 00 Medium frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 59 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual Table 48 Real time Clock System Timer clock sources continued FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 010 0 00 Low frequency crystal Low frequency crystal 01 DIVM 10 11 Low frequency crystal DIV 1 00 Low frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 011 0 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Internal RC oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 100 0 00 High frequency crystal Watchdog oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 Xx XX undefined undefined 110 x XX undefined undefined 111 0 00 External clock i
110. er of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 f
111. eral call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 76 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The 2C bus will enter Master Transmitter Mode by setting the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be O8h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting
112. ered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 200ms to 300ms after start up for the internal RC or 32 OSCCLK cycles after start up for external clock input Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include e Brownout Detect e Watchdog Timer if WDCLK WDCON O0 is logic 1 e Comparators Note Comparators can be powered down separately with PCONA 5 set to logic 1 and comparators disabled e Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both
113. errupt will be generated if enabled if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundary limits will again be compared after all 8 bits have been converted The boundary status register BNDSTAO flags the channels which caused a boundary interrupt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 34 of 136 NXP Semiconductors UMennnnns 3 2 5 3 2 6 3 2 7 3 2 8 P89LPC9201 9211 922A1 9241 9251 User manual DAC output to a port pin with high output impedance The ADC1 A s DAC block can be output to a port pin In this mode the AD1DATS register is used to hold the value fed to the DAC After a value has been written to the DAC written to AD1DAT3 the DAC output will appear on the channel 3 pin The DAC output is enabled by the ENDAC1 bit in the ADMODB register See Table 23 Clock divider The A D converter requires that its internal clock sou
114. external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 14 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet Dynamic characteristics for glitch filter specifications NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 43 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual port pin port latch Fin data input data glitch rejection 002aaa915 Fig 14 Open drain output 5 4 Input only configuration The input port configuration is shown in Figure 15 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet Dynamic characteristics for glitch filter specifications input port data pin glitch rejection 002aaa916 Fig 15 Input only 5 5 Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port
115. f logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator A
116. gister Bit address Port 0 80H Bit address Port 1 90H Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 3 output B1H mode 1 Port 3 output B2H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary PWDRTH PBOH PSH PT1H PX1H PTOH PX0H ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PST PC PKBI PI2C oon 00x0 0000 PSTH PCH PKBIH PI2CH oom 00x0 0000 E 7 PATN KBIF oolt XXXX Xx00 _SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 E KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD mi B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFU 1111 1111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 ooi 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3U 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 000 00x0 xx00 g S E P3M1 1 P3M1 0 03i XXXX xx11 P3M2 1 P3M2 0 00L xxxx xx00 Jenuew 19S LGZ6 LYZ6 LYZZ6 LLZ6 LO0OZ69d168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew asn 600z Areniga4 G xx L0 Ae 9EL JO DL lt q Juewinoog gt pamasa Syu Ily 6002 Ad dXNO Table 2 Special function registers P89LPC9201 921
117. gnized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free C8H Last data byte in No I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no recognition of own SLA or transmitted General call address AA 0 ACK no I2DAT action 0 0 0 1 Switched to not addressed SLA has been received or mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 no I2DAT action 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 12 Analog comparators lt Document ID gt Two analog comparators are provided on the P89LPC9201 9211 922A1 9241 9251 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the out
118. gram59 Fig 22 Capture Compare Unit block diagram63 Fig 23 Asymmetrical PWM downcounting68 Fig 24 Symmetrical PWM68 Fig 25 Alternate output mode69 Fig 26 Capture compare unit interrupts72 Fig 27 Baud rate generation for UART Modes 1 3 76 Fig 28 Serial Port Mode 0 double buffering must be disabled 79 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 128 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Fig 29 Serial Port Mode 1 only single transmit buffering case is shown 80 Fig 30 Serial Port Mode 2 or 3 only single transmit buffering case is shown 80 Fig 31 Transmission with and without double buffering82 Fig 32 12C bus configuration86 Fig 33 Format in the Master Transmitter mode90 Fig 34 Format of Master Receiver mode91 Fig 35 A Master Receiver switches to Master Transmitter after sending Repeated Start91 Fig 36 Format of Slave Receiver mode92 Fig 37 Format of Slave Transmitter mode92 Fig 38 12C serial interface block diagram93 Fig 39 SPI block diagram100 Fig 40 SPI single master single slave configuration 102 Fig 41 SPI dual device configuration where either can be a master or a slave102 Fig 42 SPI single master multiple slaves configuration103 Fig 43 SPI slave transfer format with CPHA 0106 Fig 44 SPI slave transfer format with CPHA 1107 Fig 45 SPI master transfer format with CPHA 0108 Fig 46 SPI master transfer format with CPHA 11
119. gt Table 2 indicates SFRs that are bit addressable Special function registers P89LPC9201 9211 922A1 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control THO Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TLO Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 89H TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode TRIM Internal 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Bl6 oscillator trim register WDCON Watchdog A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK MIIS control register WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 SIOJONPUOSIWSS dXN pamasa Syu Ily 6002 Ad dXNO 9EL JO GL 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC9201 9211 922A1 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 4 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1
120. he erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 96 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 110 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 96 IAP error status Bit Flag Description 0 Ol Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set d
121. hich is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 76 for the status codes and actions lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 78 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW E from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition P STOP condition RS repeated START condition 002aaa932 Fig 33 Format of Slave Receiver mode 11 6 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application the 1 C bus may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to
122. higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 29 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure Table 28 Interrupt priority level Priority bits IPxH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPXH x 0 1 and can therefore be assigned to one of four levels as shown in Table 29 The P89LPC9201 9211 922A1 9241 9251 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers NXP B V 2009 All rights reserved User manual
123. i I OG i UMennnnn gt P89LPC9201 9211 922A1 9241 9251 User manual Rev 01 xx 5 February 2009 User manual Document information Info Keywords Content Absiract P89LPC9201 9211 922A1 9241 9251 Technical information for the P89LPC9201 9211 922A1 9241 9251 device founded by Philips NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Revision history Rev Date Description 01 20081118 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 2 of 136 NXP Semiconductors UMennnnns 1 Introduction P89LPC9201 921 1 922A1 9241 9251 User manual lt Document ID gt 1 1 The P89LPC9201 9211 922A1 9241 9251 are single chip microcontroller available in low cost packages based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC9201 9211 922A1 9241 9251 in order to reduce component count board space and system cost Pin configuration P0 0 CMP2 KBIO P1 7 P1 6 P1 5 RST Vss P3 1 XTAL1 P3 0 XTAL2 CLKOUT P1 4 INT1 P1 3 INTO
124. ies expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer Ads own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification 18 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus l
125. ill contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the Ol flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps e Write the LOAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags e Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 5 0 and since the erase program command uses FMADRH and FMADRL 7 6 the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL 7 6 at this time e Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register e Write the address of the next byte to be programmed to FMADRL if desired Not
126. ing 81 1 k 16Double buffering in different modes 81 r 17Transmit interrupts with double buffering enabled Modes 1 2 and 3 81 r 18The 9th bit bit 8 in double buffering Modes 1 2 and 3 82 11 19Multiprocessor communications 83 11 20Automatic address recognition 84 1212C interface 85 12 112C data register 86 12 2 12C slave address register 86 12 312C control register 87 12 412C Status register 88 12 512C SCL duty cycle registers I2SCLH and I2SCLL 88 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 133 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 12 612C operation modes 89 12 6 1Master Transmitter mode 89 12 6 2Master Receiver mode 90 12 6 3Slave Receiver mode 91 12 6 4Slave Transmitter mode 92 13Serial Peripheral Interface SPI 99 13 1Configuring the SPI 103 13 2Additional considerations for a slave 104 13 3Additional considerations for a master 104 13 4Mode change on SS 104 13 5Write collision 105 13 6Data mode 105 13 7SPI clock prescaler select 109 14Analog comparators 109 14 1Comparator configuration 109 14 2Internal reference voltage 111 14 3Comparator input pins 111 14 4Comparator interrupt 111 14 5Comparators and power reduction modes 112 14 6Comparators configuration example 112 15Keypad interrupt KBI 113 16Watchdog timer WDT 114 16 1Watchdog function 114 16 2Feed
127. input 4 O DAC1 Digital to analog converter output 1 P89LPC9241 9251 l AD13 ADC1 channel 3 analog input P89LPC9241 9251 P0 5 CMPREF 22 0 P0 5 Port 0 bit 5 High current source KBIS l CMPREF Comparator reference negative input l KBI5 Keyboard input 5 P0 6 CMP1 KBI6 20 1 O P0 6 Port 0 bit 6 High current source O CMP1 Comparator 1 output l KBI6 Keyboard input 6 PO 7 T1 KBI7 19 0 P0 7 Port 0 bit 7 High current source O T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 P1 0 to P1 7 VO Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for 0 three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 5 1 Port configurations for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 18 1 0 P1 0 Port 1 bit 0 O TXD Transmitter output for serial port P1 1 RXD 17 0 P1 1 Port 1 bit 1 l RXD Receiver input for serial port P1 2 TO SCL 12 0 P1 2 Port 1 bit 2 open drain when used as output 0 TO Timer c
128. ion Protection command If Programmed to A01 A6 the Clear Configuration Protection CCP command is disabled during ISP or IAP modes This command can still be used in ICP or parallel programmer modes If programmed to Ad0 A6 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programmer modes lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 117 of 136 NXP Semiconductors UMennnnns 17 Instruction set P89LPC9201 9211 922A1 9241 9251 User manual Table 110 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD A dir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 to 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 to 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with 1 1 96 to 97 borrow SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increme
129. ions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CCK 2 2 1 Oscillator Clock OSCCLK The P89LPC9201 9211 922A1 9241 9251 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source 2 3 Crystal oscillator option The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz It can be the clock source of OSCCLK RTC and WDT 2 3 1 Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration 2 3 2 Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration 2 3 3 High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration lt Document ID gt NXP B V 2009 All righ
130. iple conversions has completed Cleared by software 4 EDGE1 When 0 an Edge conversion start is triggered by a falling edge on P1 4 When 1 an Edge conversion start is triggered by a rising edge on P1 4 5 TMM1 Timer Trigger Mode 1 Selects either stop mode TMM1 0 or timer trigger mode TMM1 1 when the ADCS11 and ADCS10 bits 00 6 ENADCI1 Enable A D Conversion complete Interrupt 1 When set will cause an interrupt if the ADCI1 flag is set and the A D interrupt is enabled 7 ENBI1 Enable A D boundary interrupt 1 When set will cause and interrupt if the boundary interrupt 1flag BNDI1 is set and the A D interrupt is enabled lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 36 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 20 A D Mode register A ADMODA address OCOh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNDI1 BURST1 SCC1 SCAN1 BNDIO BURSTO SCCO SCANO Reset 0 0 0 0 0 0 0 0 Table 21 A D Mode register A ADMODA address O0COh bit description Bit Symbol Description 0 SCANO When 1 selects single conversion mode auto scan or fixed channel for ADCO 1 SCCO When 1 selects fixed channel continuous conversion mode for ADCO 2 BURSTO When 1 selects auto scan continuous conversion mode for ADCO 3 BNDIO ADCO boundary interrupt flag When set indicates that the converted result is outside of
131. ir business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 70 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 10 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are do
132. is mode lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 96 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual WDL C1H MOV WFEED1 0A5H MOV WFEED2 05AH PRESCALER Lo peel reset A A A PCLK Watchdog oscillator oscillator i XTALWD 002aae094 Fig 40 Watchdog Timer in Timer Mode WDTE 0 14 5 Power down operation The WDT oscillator and external crystal oscillator will continue to run in power down consuming approximately 50 pA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 14 3 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled 14 6 Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows
133. ister Watchdog A7H control register Watchdog load C1H Watchdog C2H feed 1 Watchdog C3H feed 2 Bit functions and addresses Reset value MSB LSB Hex Binary 07 0000 0111 T1iM2 TOM2 00 xxx0 xxx0 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O SSI 6 PRE2 PRE1 PREO WDRUN WDTOF WDCLK _ MIS FF 1111 1111 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC9241 9251 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 4 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset sources that affect these SFRs are power on reset and watchdog reset CLKCON register reset value comes from U
134. ksum Example 00000008F8 In application programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM_MTP The programming functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFO3H The IAP calls are shown in Table 97 IAP authorization key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH The following example was written using the Keil C compiler The methods used to access a specific physical address in memory may vary with other compilers include lt ABSACC H gt enable absolute memory access define key DBYTE QxFF force key to be at address OxFF short pgm_mtp void OxFF00 set pointer to IAP entry point key 0x96 set the authorization key pgm_mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key If an IAP routine that requires an authorization key is called without a valid
135. lso any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC9201 9211 922A1 9241 9251 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 98 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 16 Flash memory lt Document ID gt 16 1 General description The P89LPC9201 9211 922A1 9241 9251 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9201 9211 922A1 9241 9251 Flash reliably stores memory contents even after 100 00
136. lso set the ENADC1 and ENADCO0 bits in 51 registers ADCON1 and ADCONO lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 50 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 39 Power Control register A PCONA address B5h bit description continued Bit Symbol Description 5 VCPD Analog Voltage Comparators power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit 6 reserved 7 RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled 7 Reset The P1 5 RST pin can function as either an active low reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power on sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin low during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit Note During a
137. n t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 61 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 11000000 SADEN 11111101 SADEN 11111110 Given 1100 00X0 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 62 Slave 0 1 2 examples Example 1 Slave 0 SADDR SADEN Given lt Document ID gt Example 2 Example 3 11000000 Slave1 SADDR 11100000 Slave 2 SADDR 1100 0000 1111 1001 SADEN 1111 1010 SADEN 1111 1100 1100 OXX0 Given 1110 0X0X Given 1110 00XX ll ll In the above example the differ
138. n addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 14 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 91 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual When the timer is not enabled to reset the device on underflow the WDT canbe used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WOSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 85 for details Figure 40 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler can be the PCLK the nominal 400kHz watchdog oscillator or crystal o
139. n counter The clock source for this counter can be either the CPU clock CCLK or the XTAL1 2 oscillator There are five SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 RTCDATH Real time clock data register high RTCDATL Real time Clock data register low The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit The Real time Clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set The 16 bit counter portion of the RTC is readable by reading the RTCDATH and RTCDATL registers Reload on underflow J MED FREQ 23 bit t E RTCDATH RTCDATL Wake up from power down Power on reset XTAL2 XTAL1 LOW FREQ internal oscillators Int t if enabled snared with WOT i RTC underflow flag RTC enable RTC clk select Fig 23 Real time clock system timer block diagram pa ERTC 002aae091 lt Document ID gt 9 1 Real time clock source RTCS1 RTCSO RTCCONJ 6 5 are used to sele
140. n embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXDO RXDO and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 105 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 16 11 Using the In system programming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC9201 9211 922A1 9241 9251 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC lt crif gt In the Intel Hex record the NN represents the number of data bytes in
141. n hardware TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware PELE C T 0 overflow on Ten interrupt Tn pin OQ CT 1 i control 5 bits TR toggle j r L Tn pin Gate INTn pin ENTn 002aaa919 Fig 18 Timer counter 0 or 1 in Mode 0 13 bit counter C T 0 overflow PCLK on interrupt Tn pin O C T 1 control toggle TR or 1 Tn pin Gate INTn pin ENTn 002aaa920 Fig 19 Timer counter 0 or 1 in mode 1 16 bit counter PCLK ated overflow on TLn TFn gt interrupt Tn pin O CT 1 i control 8 bits reload toggle TR oo L Tn pin Gate THn INTn pin 8 bits ENTn Fig 20 Timer counter 0 or 1 in Mode 2 8 bit auto reload 002aaa921 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 56 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual PCLK ae overflow TO pi on mio TFO interrupt b C T 1 i control _ 8 bits toggle TRO on O To pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 5 ne TF1 gt interrupt on control toggle eA ot O T1 pin P0 7 ENT1 AUXR1 5 002aaa922 Fig 21
142. n no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 07h R4 address MSB R5 address LSB Return parameter s R7 data 16 17 User configuration bytes A number of user configurable features of the P89LPC9201 9211 922A1 9241 9251 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 and UCFG2 shown in Table 99 and Table 102 Table 98 Flash User Configuration Byte 1 UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE1 WDSE BOEO FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Table 99 Flash User Configuration Byte 1 UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks for additional information Combinations other than those 1 FOSC1 shown in Table 100 are reserved for future use and should not be used 2 FOSC2 3 BOEO Brownout Detect Configuration see Section 6 1 Brownout detection lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 114 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 99 Flash User C
143. needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page e Write the data for the next byte to be programmed to FMDATA e Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FMADRL 5 0 e Write the erase program command 68H to FMCON starting the erase program cycle e Read FMCON to check status If aborted repeat starting with the LOAD command Table 92 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R HVA HVE SV Ol Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O Reset 0 0 0 0 0 0 0 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 101 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 93 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an
144. nns P89LPC9201 9211 922A1 9241 9251 User manual 1 6 Memory organization FFOOh FFEFh 1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h OFFFh OCOOh OBFFh 0800h O7FFh 0400h O3FFh 0000h read protected ee PR IAP calls only IAP entry FFEFh FFh points R A Erp SPECIAL FUNCTION IDATA incl DATA r entry points for 128 BYTES ON CHIP 51 ASM code PEIER ae REGISTERS DATA MEMORY STACK C code Froon Pon s DIRECTLY ADDRESSABLE AND INDIR ADDR ai 7Fh ISP CODE 512B 1 ATA 128 BYTES ON CHIP 1FFFh DATA MEMORY STACK DIRECT AND INDIR ADDR 4 REG BANKS R 7 0 ISP serial loader entry points for UART auto baud I2C etc 1 00h SECTOR 6 1E00h data memory DATA IDATA SECTOR 5 SECTOR 4 SECTOR 3 FFFFh SECTOR 2 EXTENDED SFRs SECTOR 1 FFBOh SECTOR 0 002aae485 Fig 8 P89LPC9201 9211 922A1 9241 9251 memory map lt Document ID gt The various P89LPC9201 9211 922A1 9241 9251 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space OOh FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area
145. nput External clock input 01 DIVM 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 49 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCF RTCS1 RTCSO ERTC RTCEN Reset 0 1 1 x x x 0 0 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 60 of 136 NXP Semiconductors UMennnnns 10 UART P89LPC9201 9211 922A1 9241 9251 User manual Table 50 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt reserved RTCSO Real time Clock source select see Table 48 6 RTCS1 7 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software lt Document ID gt
146. ns P89LPC9201 9211 922A1 9241 9251 User manual Table 73 Master Transmitter mode Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 08H A START Load SLA W x 0 0 x SLA W will be transmitted condition has ACK bit will be received been transmitted 10H A repeat START Load SLA Wor x 0 0 x As above SLA W will be condition has Load SLA R transmitted I C bus switches been transmitted to Master Receiver Mode 18h SLA W has been Load databyte or 0 0 0 x Data byte will be transmitted transmitted ACK ACK bit will be received has been received ho 2DAT action 1 0 0 x Repeated START will be or transmitted no l2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 xX STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been Load data byte or 0 0 0 x Data byte will be transmitted transmitted ACK bit will be received NOT ACK has hol2DAT action 1 0 0 x Repeated START will be been received or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 xX STOP condition followed by a START condition will be transmitted STO flag will be reset 28h Data byte in Load data byte or 0 0 0 x Data byte will be transmitted I2DAT ke ACK bit will be received transmitted
147. nsitive it simply tracks the input pin level If an external interrupt has been programmed as level triggered and is enabled when the P89LPC9201 9211 922A1 9241 9251 is put into Power down mode or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction modes for details Note the external interrupt must be programmed as level triggered to wake up from Power down mode External Interrupt pin glitch suppression Most of the P89LPC9201 9211 922A1 9241 9251 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL TO P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 29 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h EXO IENO 0 IPOH O P0 0 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 IPOH 1 IPO 1 4 No External interrupt 1 IE1 0013h EX1 IENO 2 IPOH 2 IP0 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IP0 3 10 No Serial port Tx and Rx TI and RI 0023h ES ESR IEN0 4 IPOH 4 IP0 4 13 No Serial port Rx RI Brownout detect BOIF 002Bh EBO IENO 5 IPOH 5 IP0 5 2 Yes
148. nt register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DECA Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 118 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 110 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XRL A Rn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 to 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL
149. ntains the status code of the 12C interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined I2C states When any of these states entered the SI bit will be set Refer to Table 73 to Table 76 for details Table 68 1 C Status register I2STAT address D9h bit allocation Bit 7 6 5 4 3 2 1 Symbol STA 4 STA 3 STA 2 STA 1 STA 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 69 12C Status register I2STAT address D9h bit description Bit Symbol Description 0 2 Reserved are always set to 0 3 7 STA 0 4 12C Status code I2C SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the 12C interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency fpcix 2 I2ZSCLH I2SCLL Where fpcix is the frequency of PCLK NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 75 of 136 NXP Semiconductors UMennnnns lt Document ID gt 11 6 11 6 1 P89LPC9201 9211 922A1 9241 9251 User manual The values for l2SCLL and I2SCLH do not have to be the
150. ogo is a trademark of NXP B V NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 121 of 136 NXP Semiconductors UMennnnns 19 Tables P89LPC9201 9211 922A1 9241 9251 User manual lt Document ID gt Table 1 Pin description 4 Table 2 Special function registers 11 Table 3 Extended special function registers 1 20 Table 4 Data RAM arrangement22 Table 5 On chip RC oscillator trim register TRIM address 96h bit allocation23 Table 6 On chip RC oscillator trim register TRIM address 96h bit description 24 Table 7 Clock control register CLKCON address FFDEh bit allocation25 Table 8 Clock control register CLKCON address FFDEh bit description 26 Table 9 Oscillator type selection for clock switch 26 Table 10 PGA trim register 30 Table 11 PGA channel selection30 Table 12 Input channels and result registers for fixed channel single auto scan single and auto scan continuous conversion mode 31 Table 13 Result registers and conversion results for fixed channel continuous conversion mode 32 Table 14 Result registers and conversion results for dual channel continuous conversion mode 32 Table 15 Conversion mode bits 33 Table 16 A D Control register 0 ADCONO address 8Eh bit allocation 35 Table 17 A D Control register 0 ADCONO address 97h bit description 35 Table 18 A D Control register 1 ADCON1 address 97h bit allocation 35 Table 19 A D Control register 1 ADCON1 addres
151. om UCFG2 7 Jenuewl 19Sf 1 S26 LV26 LVCC6 L 26 LOC6Od 168d lt uuuuu gt NN S10 9NpuodIW S dXN jenuew 1asqQ Gogoz AuenigajG XX0 Aas me 9EL LQZ lt q u wnooq gt pamasa Syu Ily 6002 Ad dXNO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 Name ACC ADCONO ADCON1 ADINS ADMODA ADMODB ADOBH ADOBL ADODATO ADODAT1 ADODAT2 ADODAT3 AD1BH AD1BL AD1DATO Description SFR addr Bit address Accumulator EOH A D control 8Eh register 0 A D control 97H register 1 A D input A3H select A D mode COH register A A D mode A1H register B A D_0 BBH boundary high register A D_0 A6H boundary low register A D_0 data C5H register 0 A D_0 data C6H register 1 A D_0 data C7H register 2 A D_0 data F4H register 3 A D_0 C4H boundary high register A D_0 BCH boundary low register A D_0 data D5H register 0 Bit functions and addresses Reset value MSB E7 ENBIO ENBI1 AIN13 BNDI1 CLK2 E6 ENADCIO ENADCI1 AIN12 BURST1 CLK1 E5 TMMO TMM1 AIN11 SCC1 CLKO E4 EDGEO EDGE1 AIN10 SCAN1 INBNDO E3 ADCIO ADCI1 AINO3 BNDIO ENDAC1 E2 ENADCO ENADC1 AINO2 BURSTO ENDACO E1 ADCS01 ADCS11 AINO1 SCCO BSA1 LSB E0 ADCS00 ADCS10 AINOO SCANO BSAO Hex
152. onfiguration Byte 1 UCFG1 bit description continued Bit Symbol Description 4 WDSE Watchdog Safety Enable bit Refer to Table 85 Watchdog timer configuration for details 5 BOE1 Brownout Detect Configuration see Section 6 1 Brownout detection 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 85 Watchdog timer configuration for details Table 100 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz a 5 011 Internal RC oscillator 7 373 MHz a 1 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz Table 101 Flash User Configuration Byte 2 UCFG2 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKDBL 2
153. onversion Table 26 Temperature Sensor Control register TPSCON address FFCAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TSEL1 TSELO Reset 0 0 0 0 0 0 0 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 38 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 27 Temperature Sensor Control register TPSCON address FFCAh bit description P89LPC9241 9251 Bit 1 0 3 2 4 7 Symbol Description Reserved TSEL1 TSELO Temperature sensor mux selection Select among temperature sensor internal reference voltage and AD03 01 internal reference voltage 10 temperature sensor enabled and selected Reserved 4 Interrupts lt Document ID gt 4 1 The P89LPC9201 9211 922A1 9241 9251 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC9201 9211 922A1 9241 9251 s 12 13 interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a
154. or UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 10 10 More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission TI SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 25 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 65 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Q s1 A stes a ste st Be s16 si is si6 si s ste st on st6 st a si6 si at si6 S1 si6 st ue st6 si se ste st i si6 si i si6 write to SBUF shift LS transit RXD data out TxD shiftclock LILI CPLLT LS LEP LP LI LJ TI a E i WRITE to SCON clear RI LD RI l RXD DO D1 D2 D3 D4 g D5 g D6 g D7 data in TXD shift clock LILILILILILILI LJ receive 002aaa925 Fig 25 Serial Port Mode 0 double buffering must be disabled 10 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RxD RxD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide
155. ored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master I2C device When CRSEL 1 the 12C interface uses the Timer 1 overflow rate divided by 2 for the 12C clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of I C bus Timer overflow rate 2 PCLK 2 256 reload value If fosc 12 MHz reload value is 0 to 255 so I C data rate range is 11 72 Kbit sec to 3000 Kbit sec When CRSEL 0 the 12C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the 12C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the I C interface to transmit a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 66 12C Control register IZCON address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA CRSEL Reset x 0 0 0 0 0 x 0 Table 67 12C Control register I
156. ounter 0 external count input or overflow output open drain when used as output O SCL C bus serial clock input output P1 3 INTO SDA 11 1 0 P1 3 Port 1 bit 3 open drain when used as output l INTO External interrupt 0 input VO SDA C bus serial data input output P1 4 INT1 10 O P1 4 Port 1 bit 4 High current source l INT1 External interrupt 1 input lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 5 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 1 Pin description continued Symbol Pin Type Description TSSOP20 DIP20 P1 5 RST 6 l P1 5 Port 1 bit 5 input only RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force ISP mode P1 6 5 O P1 6 Port 1 bit 6 High current source P1 7 4 1 0 P1 7 Port 1 bit 7 High current source P3 0 to P3 1 1 0 Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin i
157. owed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WOCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON get WDCON SETB ACC 2 set WD_RUN 1 OV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed must occur immediately OV WFEED1 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of watchdog clocks before timing out is calculated by the following equations PRE tclks WDL 1 1 3 where NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 93 of 136 NXP Semiconductors UMennnnns P89LPC9201
158. ower down mode via PCONA 4 the internal clock to the ADC is disabled To fully power down the ADC the user should clear the ENADC bits in ADCONx registers Temperature sensor can be disabled via setting TSEL1 0 not to 10 In Power down mode or Total Power down mode the A D and Temp sensor do not function Table 16 A D Control register 0 ADCONO address 8Eh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCS01 ADCS00 Reset 0 0 0 0 0 0 0 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 35 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 17 A D Control register 0 ADCONO address 97h bit description Bit 1 0 Symbol ADCS01 ADCS00 ENADCO ADCIO EDGEO TMMO ENADCIO ENBIO Description A D start mode bits see below 00 Timer Trigger Mode when TMMO 1 Conversions starts on overflow of Timer 0 When TMMO 0 no start occurs stop mode 01 Immediate Start Mode Conversion starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGEO occurs Enable ADCO When set 1 enables ADCO when 0 the ADC is in power down A D Conversion complete Interrupt 0 Set when any conversion or set of multiple conversions has completed Cleared by software An edge conversion start is triggered by a falling edge on P1 4 when
159. ower monitoring functions 47 6 1Brownout detection 47 6 2Power on detection 49 6 3Power reduction modes 49 7Reset 52 7 1Reset vector 53 8Timers 0 and 1 54 8 1Mode 0 55 8 2Mode 1 55 8 3Mode 2 56 8 4Mode 3 56 8 5Mode 6 56 8 6Timer overflow toggle output 58 9Real time clock system timer 58 9 1Real time clock source 59 9 2Changing RTCS1 RTCSO 60 9 3Real time clock interrupt wake up 60 9 3 1Real time clock read back 60 9 4Reset sources affecting the Real time clock 60 10Capture Compare Unit CCU 62 10 1CCU Clock CCUCLK 62 10 2CCU Clock prescaling 62 10 3Basic timer operation 63 10 4Output compare 65 10 5Input capture 66 10 6PWM operation 67 10 7Alternating output mode 68 10 8Synchronized PWM register update 69 10 9HALT 69 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 132 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual 10 10PLL operation 70 10 11CCU interrupt structure 71 11UART 74 11 1Mode 0 74 11 2Mode 1 74 11 3Mode 2 74 11 4Mode 3 75 11 5SFR space 75 11 6Baud Rate generator and selection 75 11 7Updating the BRGR1 and BRGRO SFRs 75 11 8Framing error 76 11 9Break detect 76 11 10More about UART Mode 0 78 11 11More about UART Mode 1 79 11 12More about UART Modes 2 and 3 80 1 13Framing error and RI in Modes 2 and 3 with SM2 1 80 1 14Break detect 81 1 15Double buffer
160. p direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 119 of 136 UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual NXP Semiconductors Table 110 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLRC Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F 1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on
161. previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then If DBISEL is logic 0 no more interrupts will occur NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 68 of 136 NXP Semiconductors UMennnnns if P89LPC9201 9211 922A1 9241 9251 User manual If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertaint
162. ption 114 Table 115 Watchdog timer configuration 115 Table 116 Watchdog Timer Control register WDCON address A7h bit allocation 117 Table 117 Watchdog Timer Control register WDCON address A7h bit description 117 Table 118 Watchdog timeout vales 118 Table 119 Watchdog input clock selection118 Table 120 AUXR1 register address A2h bit allocation 120 Table 121 AUXR1 register address A2h bit description 121 Table 122 Data EEPROM control register DEECON address F th bit allocation122 Table 123 Data EEPROM control register DEECON address F1h bit description122 Table 124 Flash Memory Control register FMCON address E4h bit allocation 128 Table 125 Flash Memory Control register FMCON address E4h bit description 128 Table 126 Boot loader address and default Boot vector 131 Table 127 In system Programming ISP hex record formats 133 Table 128 IAP error status 137 Table 129 IAP function calls 138 Table 130 Flash User Configuration Byte 1 UCFG1 bit allocation 140 Table 131 Flash User Configuration Byte 1 UCFG1 bit description 140 Table 132 Oscillator type selection 141 Table 133 Flash User Configuration Byte 2 UCFG2 bit allocation 141 Table 134 Flash User Configuration Byte 2 UCFG2 bit description 141 Table 135 Sector Security Bytes SECx bit allocation 141 Table 136 Sector Security Bytes SECx bit description 142 Table 137 Effects of Security Bits 142 Table 138 Boot Vector BOOTVEC bit allocation 142 Table 13
163. put value changes NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 86 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 12 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 78 The overall connections to both comparators are shown in Figure 36 There are eight possible configurations for each comparator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 37 When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 77 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset x x 0 0 0 0 0 0 Table 78 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled
164. rce be in the range of 320kHz to 8MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 23 I O pins used with ADC functions The analog input pins maybe be used as either digital I O or as inputs to A D and thus have a digital input and output function In order to give the best analog performance pins that are being used with the ADC should have their digital outputs and inputs disabled and have the 5V tolerance disconnected Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 31 Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and its corresponding A D has been enabled When used as digital I O these pins are 5 V tolerant If selected as input signals in ADINS these pins will be 3V tolerant if the corresponding A D is enabled and the device is not in power down Otherwise the pin will remain 5V tolerant Please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet for specifications Power down and Idle mode In Idle mode the A D converter if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D interrupt is enabled Power can be reduced by disabling temperature sensor and A D If ADC is configured to be in p
165. reset Table 40 Reset Sources register RSTSRC address DFh bit allocation Bit Symbol Reset 7 6 5 4 3 2 1 0 BOIF BOF POF R_BK R_WD R_SF R_EX xX 0 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 41 Reset Sources register RSTSRC address DFh bit description Description external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset Watchdog Timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared BOD Reset Flag When BOD Reset is activated this bit is set
166. round to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 6 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 100 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON w
167. rupt each has 4 trip voltage levels BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are used as trip point configuration bits of BOD reset BOICFG1 bit and BOICFGO0 bit in register BODCFG are used as trip point configuration bits of BOD interrupt BOD reset voltage should be lower than BOD interrupt trip point Table 33 gives BOD trip points configuration In total power down mode PMOD1 PMODO 11 the circuitry for the Brownout Detection is disabled for lowest power consumption When PMOD1 PMODO not equal to 11 BOD reset is always on and BOD interrupt is enabled by setting BOI PCON 4 bit Please refer Table 34 for BOD reset and BOD interrupt configuration BOF bit RSTSRC 5 BOD reset flag is default as 0 and is set when BOD reset is tripped BOIF bit RSTSRC 6 BOD interrupt flag is default as 0 and is set when BOD interrupt is tripped BOD FLASH is used for flash program erase protection BOD FLASH is always on except in power down or total power down mode PCON 1 1 It can not be disabled in software BOD FLASH has only 1 trip voltage level of 2 4 V When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash program erase is blocked If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip voltage and is negated when Vpp rises above the brownout trip voltage For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the data
168. s 97h bit description 36 Table 20 A D Mode register A ADMODA address 0COh bit allocation 36 Table 21 A D Mode register A ADMODA address 0COh bit description 36 Table 22 A D Mode register B ADMODB address Ath bit allocation 36 Table 23 A D Mode register B ADMODB address A1h bit description 37 Table 24 A D Input select ADINS address A3h bit allocation 37 Table 25 A D Input select ADINS address A3h bit description 37 Table 26 PGA0 Control register PGACONDO address FFCAh bit allocation 37 Table 27 PGA0 Control register PGACONO address FFCAh bit description 38 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 122 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual Table 28 PGA1 Control register PGACON1 address FFEth bit allocation 38 Table 29 PGA1 Control register PGACON1 address FFE1h bit description 38 Table 30 PGAO Control register B PGACONOB address FFCEh bit allocation 39 Table 31 PGA0 Control register B PGACONOB address FFCEh bit description 39 Table 32 PGA1 Control register B PGACON1B address FFE4h bit allocation 39 Table 33 PGA1 Control register B PGACON1B address FFE4h bit description 39 Table 34 Interrupt priority level 40 Table 35 Summary of interrupts 41 Table 36 Number of I O pins available 43 Table 37 Port output configuration settings 43 Table 38 Port output configuration 47 Ta
169. s bit is set when one of the 25 possible 12C states is entered When EA bit and El2C IEN1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing 0 to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the 12C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to Aonot addressed A6 Slave Receiver Mode The STO flag is cleared by hardware automatically 5 STA Start Flag STA 1 I C bus enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the 12C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the 12C interface is in an addressed slave mode STA 0 no START condition or repeated START condition will be generated 6 I2EN 12C Interface Enable When set enables the 12C interface When clear the 12C function is disabled 7 reserved I2C Status register This is a read only register It co
170. s configured independently Refer to Section 5 1 Port configurations for details All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below P3 0 XTAL2 9 1 0 P3 0 Port 3 bit 0 CLKOUT O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 XTAL1 8 0 P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Vss 7 Ground 0 V reference Vpop 21 l Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 6 of 136 NXP Semiconductors UMennnnns 1 3 Logic symbols P89LPC9201 9211 922A1 9241 9251 User manual KBIO KBI1 KBI2 KBI3 KBI4 CINIA
171. s reserved User manual Rev 01 xx 5 February 2009 69 of 136 NXP Semiconductors UMennnnns lt Document ID gt 10 19 P89LPC9201 9211 922A1 9241 9251 User manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in the Section 10 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 becomes as follows 1 The double buffer is empty initially 2 The CPU writes to TB8 3 The CPU writes to SBUF 4 The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately o If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is logic 0 no more interrupt will occur If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a
172. s the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either TnGATE 0 or INTn 1 Setting TNGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 47 The TnGATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 18 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 8 2 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 19 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 54 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 8 3 Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 20 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 8 4 Mode 3 When Timer 1 is in Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0
173. same the user can give different duty cycles for SCL by setting these two registers However the value of the register must ensure that the data rate is in the 1 C data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended Table 70 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 Kbps to 1 8Kbpsto 0 9Kbpsto 5 86Kbpsto 2 93 Kbps to 922 Kbps 461 Kbps 230 Kbps 1500 Kbps 750 Kbps Timer 1 in Timer 1 in Timer 1 in Timer 1 in Timer 1 in mode 2 mode 2 mode 2 mode 2 mode 2 I2C operation modes Master Transmitter mode In this mode data is transmitted from master to slave Before the Master Transmitter mode can be entered I2CON must be initialized as follows Table 71 12C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate I2EN must be set to 1 to enable the I C function If the AA bit is 0 it will not acknowledge its own slave address or the gen
174. scillator selected by the WDCLK bit in the WDCON register and XTALWD bit in the CLKCON register Note that switching of the clock sources will not take effect immediately see Section 14 3 The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs its behavior is similar to power on reset Both POF and BOF are cleared Table 85 Watchdog timer configuration WDTE WDSE FUNCTION 0 x The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 1 0 The watchdog reset is enabled The user can set WDCLK to choose the clock source 1 1 The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 Watchdog oscillator crystal oscillator feed sequence r m r r gt l TO WATCHDOG XTALWD l l l DOWN COUNTER l I after one prescaler J l count delay PRE2 l PRE1 DECODE i PREO l 002aae092 Fig 38 Watchdog Prescaler Watchdog clock after a Watchdog lt Document ID gt NXP B V 2009 All rights reserved
175. se Next action taken by I2C hardware I2STAT hardware to from I2DAT to I2CON STA STO SI STA 50h Data byte has Read data byte 0 0 0 0 Data byte will be received NOT ACK been received bit will be returned ACK has been read data byte 0 0 0 1 Data byte will be received ACK bit returned will be returned 58h Data byte has Read data byte or 1 0 x Repeated START will be transmitted been received read data byte or 0 Xx STOP condition will be transmitted NACK has been STO flag will be reset returned aa read data byte 1 1 0 xX STOP condition followed by a START condition will be transmitted STO flag will be reset Table 75 Slave Receiver mode Status code Status of the I C Application software response Next action taken by I C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 60H Own SLA W has no I2DAT action x 0 0 0 Data byte will be received and NOT been received or ACK will be returned ACK has been no I2DAT action x 0 0 1 Data byte will be received and ACK received will be returned 68H Arbitration lostin No I2DAT action x 0 0 0 Data byte will be received and NOT SLA R Was or ACK will be returned master Own no I2DAT action x 0 0 1 Data byte will be received and ACK SLA W has been will be returned received ACK returned 70H General call No l2DAT action x 0 0 0 Data byte will be received and NOT address 00H has or ACK will be returned been received no I2DAT action x 0 0 1 Data byte will be received and ACK ACK has been will
176. sheet for specifications Table 33 BOD Trip points configuration BOE1 BOEO BOICFG1 BOICFGO BOD Reset BOD UCFG1 5 UCFG1 3 BOICFG 1 BOICFG 0 Interrupt 0 0 0 0 Reserved 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 2 2V 2 4V 0 1 1 0 2 2V 2 6V 0 1 1 1 2 2V 3 2V 1 0 0 0 Reserved 1 0 0 1 1 0 1 0 2 4V 2 6V 1 0 1 1 2 4V 3 2V 1 1 0 0 Reserved 1 1 0 1 1 1 1 0 1 1 1 1 3 0V 3 2V NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 47 of 136 NXP Semiconductors UMennnnns lt Document ID gt 6 2 6 3 P89LPC9201 9211 922A1 9241 9251 User manual Table 34 BOD Reset and BOD Interrupt configuration PMOD1 PMODO PCON 1 0 BOI EBO EA BOD BOD PCON 4 IENO 5 IENO 7 Reset Interrupt 11 total power down X X X N N 11 any mode other than total 0 X X Y N power down 1 0 x y N X 0 Y N 1 1 Y Y Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit BOF RSTSRC 5 will be set when POF is set Power reduction modes The P89LPC9201 9211 922A1 9241 9251 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Ta
177. st channel second conversion result ADxDAT3 Second channel second conversion result 3 2 2 6 Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in the result register which corresponds to the selected input channel See Table 12 May be used with any of the start modes This mode is selected by clearing the BURSTx SCCx and SCANx bits in the ADMODA register which correspond to the ADC in use 3 2 2 7 Conversion mode selection bits Each A D uses three bits in ADMODA to select the conversion mode for that A D These mode bits are summarized in Table 15 below Combinations of the three bits other than the combinations shown are undefined lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 33 of 136 NXP Semiconductors UMennnnns lt Document ID gt 3 2 3 3 2 3 1 3 2 3 2 3 2 3 3 3 2 4 P89LPC9201 9211 922A1 9241 9251 User manual Table 15 Conversion mode bits Burst1 SCC1 Scani ADC1conversion Burst0 SCCO Scan0 ADCO conversion mode mode 0 0 0 Single step 0 0 0 Single step 0 0 1 Fixed channel 0 0 1 Fixed channel single single Auto scan single Auto scan single 0 1 0 Fixed chann
178. t Vector set to the custom boot loader if desired Table 94 Boot loader address and default Boot vector Product Flash size End Signature bytes Sector Page Pre programmed Default Boot address Mfg id Id 1 Id 2 size size serial loader vector P89LPC9201 2kB x 8 07FFh 15h DDh 30h 1kBx8 64x8 0600h to 07FFh 07h P89LPC9211 4kBx8 OFFFh 15h DDh 31h 1kKBx8 64x8 OEOOh to OFFFh OFh lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 104 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 94 Boot loader address and default Boot vector continued Product P89LPC922A1 P89LPC9241 P89LPC9251 Flash size End Signature bytes Sector Page Pre programmed Default Boot address Mfg id Id 1 Id 2 size size serial loader vector 8 kB x8 1FFFh 15h DDh 32h 1kBx8 64x8 1E00h to 1FFFh 1Fh 4kBx8 OFFFh 15h DDh 33h 1kBx8 64x8 OE0Oh to OFFFh OFh 8 kB x8 1FFFh 15h DDh 34h 1kBx8 64x8 1E00h to 1FFFh 1Fh lt Document ID gt 16 9 Hardware activation of Boot Loader 16 10 The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 41 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after Vpp rises to its normal operating value This is followed by three and only three properly timed low going pulses Fewer or more than three pulses
179. ten by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt 5 Reserved 6 SMODO Framing Error Location e When logic 0 bit 7 of SCON is accessed as SMO for the UART e When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 UART Table 38 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 l Symbol RTCPD VCPD ADPD I2PD SPD Reset 0 0 0 0 0 0 0 0 Table 39 Power Control register A PCONA address B5h bit description Bit Symbol Description l 0 reserved 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit l 2 reserved 3 I2PD 12C power down When logic 1 the internal clock to the 1 C bus is disabled Note that in either Power down mode or Total Power down mode the 12C clock will be disabled regardless of this bit 4 ADPD A D Converter Power down When A01 A6 turns off the clock to the ADC To fully P89LPC9241 92 power down the ADC the user should a
180. ter that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 at room temperature Note the initial value is better than 1 please refer to the P89LPC9201 9211 922A1 9241 9251 data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency When the clock doubler option is enabled UCFG2 7 1 the output frequency is doubled If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower When clock doubler option is enabled BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level Table 7 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 26 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User m
181. thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are e FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to logic Os when the command is written e FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory e FMDATA Flash Data Register Accepts data to be loaded into the page register The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap a
182. ts and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 30 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 41 of 136 NXP Semiconductors UMennnnns lt Document ID gt 5 1 5 2 P89LPC9201 9211 922A1 9241 9251 User manual Table 30 Number of I O pins available Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 18 oscillator External RST pin supported 17 External clock input No external reset except during power up 17 External RST pin supported 16 Low medium high speed oscillator No external reset except during power up 16 external crystal or resonator External RST pin supported 15 Port configurations All but three I O port pins on the P89LPC9201 9211 922A1 9241 9251 may be configured by software to one of four types on a pin by pin basis as shown in Table 31 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 31 Port output configuration settings PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0
183. ts reserved User manual Rev 01 xx 5 February 2009 25 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual 2 4 Clock output The P89LPC9201 9211 922A1 9241 9251 supports a user selectable clock output function on the XTAL2 CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real time Clock and Watchdog Timer are not using the crystal oscillator as their clock source This allows external devices to synchronize to the P89LPC9201 9211 922A1 9241 9251 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is 1 that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of other bits of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register 2 5 On chip RC oscillator option The P89LPC9201 9211 922A1 9241 9251 has a 6 bit TRIM regis
184. uring IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed 4to7 unused reads as a logic 0 lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 111 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 97 IAP function calls IAP function IAP call parameters Program User Code Page Input parameters requires Adkey Ad Read Version Id Misc Write requires Adkey A6 lt Document ID gt ACC 00h R3 number of bytes to program R4 page address MSB R5 page address LSB R7 pointer to data buffer in RAM F1 0h use IDATA Return parameter s R7 status Carry set on error clear on no error Input parameters ACC 01h Return parameter s R7 IAP version id Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection Return parameter s R7 status C
185. vated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 88 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down mode and Idle mode as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode CINnA CINnA COn CMPREF D con CMPREF p gme 002aaa618 002aaa620 a CPn CNn OEn 000 b CPn CNn OEn 00 1 CINnA CINnA COn VREF 1 23 V gt COn VREF 1 23 V m i CMPn 002aaa621 002aaa622 c CPn CNn OEn 010 d CPn CNn OEn 0 1 1 CINnB co CINnB COn CMPREF i CMPREF CMPn 002aaa623 002aaa624 e CPn CNn OEn 100 f
186. vel details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FFOO to FFFFh thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power on reset code execution The P89LPC9201 9211 922A1 9241 9251 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC9201 9211 922A1 9241 9251 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location OOOOH which is the normal start address of the user s application code When the Boot Status Bit is set to one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default settings for this device is shown in Table 94 below The factory pre programmed boot loader can be erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector on the device Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boo
187. vides a byte oriented I C interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode lt Document ID gt NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 72 of 136 NXP Semiconductors UMennnnns lt Document ID gt P89LPC9201 9211 922A1 9241 9251 User manual ce one SCL P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE P89LPC9201 9211 WITH I2C BUS WITH I2C BUS 922A1 9241 9251 INTERFACE INTERFACE 002aae430 Fig 29 1 C bus configuration The P89LPC9201 9211 922A1 9241 9251 CPU interfaces with the I C bus through six Special Function Registers SFRs I2CON I2C Control Register I2DAT 1 C Data Register I2STAT 12C Status Register IZADR 12C Slave Address Register I2SCLH SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte I2C data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table
188. xx Xx00 _SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 1 KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD 0l B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 Lt POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFU 1111 1111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 ooi 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D30 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 ool 00x0 xx00 Jenuewl 19S 1S26 LV26 LVCC6 L 26 LOC6Od 168d lt UUUUUPINN SIOJONPUOSIWIS dXN jenuew asn 6002 Arenaqa4 G xx L0 Ae 9EL JO Le lt q u wnooq gt pamasa Syu Ily 6002 A a dXNO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT Description SFR addr Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Portdata 99H
189. y of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 write to SBUF TX interrupt TXD write to SBUF TX interrupt TXD write to SBUF TX interrupt AUTU LEE T Fig 28 Transmission with and without double buffering single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown if j l double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending TX interrupt DBISEL SSTAT 4 0 f i l l double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending TX interrupt DBISEL SSTAT 4 1 002aaa928 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt lt Document ID gt NXP B V 2009 All right
190. ystem Programming ISP hex record formats Record type 00 01 02 Command data function Program User Code Memory Page nnaaaa00dd ddcc Where nn number of bytes to program aaaa page address dd dd data bytes cc checksum Example 100000000102030405006070809DC3 Read Version Id 0Oxxxx01cc Where xxxx required field but value is a Addon Adt care Ad cc checksum Example 00000001 FF Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field but value is a Addon Adt care A6 ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection Example 020000020347B2 NXP B V 2009 All rights reserved User manual Rev 01 xx 5 February 2009 107 of 136 NXP Semiconductors UMennnnns P89LPC9201 9211 922A1 9241 9251 User manual Table 95 In system Programming ISP hex record formats continued Record type Command daia function 03 Miscellaneous Read Functions 01xxxx03sscc Where xxxx required field but value is a AAddon Adt care A6 ss subfunction code cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserv
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