User`s Manual Model ULM52C Universal Logical Module For
Contents
1. Due to the ultimate parallelism of an FPGA ULM52C can be programmed to perform multiple functions simultaneously whether mutually related or unrelated For example April 2004 Page 2 Manual ULM52C mdo ULM52C MAN 001 0 part of ULM52C may be programmed to execute trigger logic wile other parts serving as blocks of gated and non gated scalers digital delay and gate generators coincidence registers etc 2 SPECIFICATIONS Formfactor Single width CAMAC PC Board 4 layer double sided mixed surface mount and through hole CAMAC Connector Standard CAMAC card edge connector with gold plated fingers ECL Ports 52 mapped onto the pins of the user FPGA LEDs Six user programmable LEDs controlled by the FPGA configuration Clocks One 100 MHz External FPGA Clock Inputs Three rated at 110 MHz FPGA XC28200 6PQ208 by Xilinx FPGA Configuration Memory 4 MBit AT29C040A 3 3V by Atmel CAMAC Data Words 24 bit Front Panel Black anodized with white silk screen labeling Power Requirements 6V at approximately 1 A 6V at approximately 600 mA Depends on the user application April 2004 Page 3 Manual ULM52C mdo ULM52C MAN 001 0 3 ARCHITECTURE Block diagram of ULM52C is shown in Fig 1 As seen in this figure the user FPGA an XC28200 by Xilinx has exclusive control of ECL ports and user LEDs It connects to the CAMAC bus via a block of transceivers and buffers which allow one to implement a complete CAMA2. Because of the use of tri state transceivers ULM52C is both FastCamac 1 and FastCamac 2 ready The Camac Read and Write lines share FPGA pads with the actual direction of the data flow set by the utility CPLD in compliance with CAMAC standards This direction is decided by the state of the CAMAC control signals F8 and F16 and is consistent with a Write operation from CAMAC to FPGA when F8 is False High and F16 is True Low note that CAMAC utilizes April 2004 Page 11 Manual ULM52C mdo ULM52C MAN 001 0 inverse logics and is consistent with a Read operation from FPGA to CAMAC when both F8 and F16 are False High For control operations F8 is True Low and the data are not utilized The direction for these operations is set as for Write operations In the FPGA configuration the CAMAC data pads RW lt 1 gt RW lt 24 gt should be defined as bi directional with the output enable state consistent with the data flow direction described above All control lines are inputs except for LAM X and Q which are outputs Standard negative CAMAC logics applies to all CAMAC interface signals Table 1 Association between CAMAC R and W data lines physical FPGA pad numbers and their respective UCF names R W_ FPGA UCF R W FPGA UCF R W FPGA UCF line Pad Name line Pad Name line Pad Name 1 60 RW l 9 45 RW lt 9 gt 17 34 RW lt 17 gt
3. LOC P34 RW lt 18 gt LOC P33 RW lt 19 gt LOC P31 RW lt 20 gt LOC P30 7 94455994 ENE cl H April 2004 Page 19 Manual ULM52C mdo ULM52C MAN 001 0 ET RW lt 21 gt LOC P29 ET RW lt 22 gt LOC P27 ET RW lt 23 gt LOC P24 ET RW 24 LOC P23 User LED pads outputs ET RLED L LOC P180 ET RLED R LOC P179 ET GLED L LOC P178 ET GLED R LOC P176 ET YLED L LOC P175 ET YLED R LOC P174 ECL port standard I O pads inputs or outputs ET ECLA lt 1 gt LOC P167 ET ECLA lt 2 gt LOC P166 ET ECLA lt 3 gt LOC P164 ET ECLA lt 4 gt LOC P165 ET ECLA lt 5 gt LOC P162 ET ECLA lt 6 gt LOC P163 ET ECLA lt 7 gt LOC P160 ET ECLA lt 8 gt LOC P161 ET ECLA lt 9 gt LOC P149 ET ECLA lt 10 gt LOC P150 ET ECLA lt 11 gt LOC P148 ET ECLA lt 12 gt LOC P147 ET ECLA lt 13 gt LOC P142 ET ECLA lt 14 gt LOC P146 ET ECLA lt 15 gt LOC P141 ET ECLA lt 16 gt LOC P140 ET ECLB lt 1 gt LOC P139 ET ECLB lt 2 gt LOC P136 ET ECLB lt 3 gt LOC P135 ET ECLB lt 4 gt LOC P138 ET ECLB lt 5 gt LOC P1
4. APPENDICES 5 1 USER CONSTRAINTS FILE UCF The usage of FPGA pads is defined in the user constraints file UCF Part of such a file used by the Test Configuration is reproduced below Special pads ET USRCLK LOC P185 GCK3 ET USRCLKENA LOC P188 N N CAMAC control pads inputs N VELOS LOC P7 N vF lt 1 gt LOC P6 N F lt 2 gt LOC P5 N F lt 3 gt LOC P4 7 N F 4 LOC P3 N vA lt 0 gt LOC P17 N A lt 1 gt LOC P16 N vA lt 2 gt LOC P14 N A 3 LOC P8 N S 1 LOC P18 N S 2 LOC P20 N VTA TOC P 9 N C THOG P10 N YN LOC P15 CAMAC control pads outputs NET X LOC P617 NET Q LOC P62 NET LAM LOC P22 N N N N N N N N N N N N N N N N N N N N He A HA H HA E H H H td td E H H a dad HA CAMAC data lines bidirectional RW lt 1 gt LOC P60 RW lt 2 gt LOC P59 RW lt 3 gt LOC P58 RW lt 4 gt LOC P57 RW lt 5 gt LOC Rp49 RW lt 6 gt LOC P48 RW lt 7 gt LOC P47 RW lt 8 gt LOC R46 RW lt 9 gt LOC R45 RW lt 10 gt LOC P244 RW lt 11 gt LOC P43 RW lt 12 gt LOC P42 RW lt 13 gt LOC P417 RW lt 14 gt LOC P37 RW lt 15 gt LOC P36 RW lt 16 gt LOC P357 RW lt 17 gt
5. ECLB lt 5 gt DI 94 ECLD lt 1 gt B6 134 ECLB lt 6 gt D2 90 ECLD lt 2 gt B7 129 ECLB lt 7 gt D3 89 ECLD lt 3 gt B8 132 ECLB lt 8 gt D4 88 ECLD lt 4 gt B9 126 ECLB 9 D2 80 ECLCLK A B10 127 ECLB lt 10 gt D3 77 ECLCLK B B11 123 ECLB lt 11 gt D4 182 ECLCLK C B12 125 ECLB lt 12 gt 4 2 3 PADS ASSOCIATED WITH USER LEDs ULMS52C is equipped with six front panel user LEDs two red two green and two yellow all controlled by the FPGA configuration through expanding drivers These April 2004 Page 13 Manual ULM52C mdo ULM52C MAN 001 0 hardware drivers extend the duration of short pulses of at least 2 clock cycle duration to approx 25 ms to provide for a robust flash of the associated LED while not affecting the action of longer pulses or DC levels All LED ports are active high A non configured FPGA will cause all six LEDs to turn on a state that can be taken as indicative of a failure of the FPGA to boot Conversely user LEDs will signal a successful configuration of the FPGA by displaying a startup pattern foreseen by the user code In the UCF file See Appendix 5 1 LED pads are named RLED L RLED_R GLED L GLED R YLED L YLED R where R G and Y stand for Red Green and Yellow and L and R stand for Left and Right respectively Their association with physical pads of the FPGA is shown in Table 4 T
6. FA ECL PORTS Erare A AN ON NS 5 FAA USER CEDS Garoaren ea ee E E E E E a a e beke E E eres 5 4 OPERATING INSTRUCTIONS S a aaea a e aa Eaa aa E E E EEEE A Ade HARDWARE SET UP ke te vese dede doue A E vev pye bone NAT 7 della IMPORTANT RULES e eke fi e0odes setan yote sess riant esie a sesyon passe dooysyon testes Konpa sdosn ss sbanessyosenoefasdins 7 412 CONFIGURING FECL PORT S ee teceesdtiet epay espes asse en rAr non aai eE aAa AR AEA Eana 8 AWS JUMP R S NGS 6e dese dede aaa seas as donk dada ao dodo dice zion Aaa EEEa des ES AARE Oi APAS 10 4 2 PROGRAMMING OF THE USER FPGA sesessssesessesssseseeeesssrssesesreresrnsssesrsrrnessnsesrsreenesenseseseee 11 4 2 1 PADS ASSOCIATED WITH CAMAC INTERFACE ocoonnccocccnnononinonnnnnnnonanancnnonanancnnonononos 11 4 2 2 PADS ASSOCIATED WITH ECL PORTS 0L 0i20ireiieeorerooooooenooeoonoonooenouooooonesononoouooononne 12 4 2 3 PADS ASSOCIATED WITH USER LEDS cooconcniconononccnncanannnnnnnnoronononnncnonanancnnoronanaroninnonos 13 4 2 4 PADS ASSOCIATED WITH USER CLOCK AND CLOCK ENABLE 14 4 255 CONFIGURING SAA E ON 14 4 3 PROGRAMMING OF THE CONFIGURATION MEMORY 0 00i2etereteereoreroososooenossnonoonosonon 15 de APRENDICES ico ra anl dous ki nein ari i 19 Sl USER CONSTRAINTS FILE UCP v ur eenia e e e aaea aieiai 19 5 2 SUMMARY OF SYSTEM CAMAC COMMANDS eoooccoccoconncononnonnnanonanonccnnnanoncnanannonononaranincanans 21 April 2004 Page 1 Manual ULM52C mdo ULM
7. from top to bottom by labels A B C and D respectively while individual ports within a header are identified by numbers 1 through 16 ports A C or 1 through 4 port D It is important to note that as indicated on the front panel of ULM52C port 1 of each of the five headers is represented by the top pair of pins of the header As indicated by silk screen labels printed above each of the two columns of 13 16 pin sockets the input translators are to be placed into sockets in the left most column while the output translators are to be inserted into sockets of in the right most column The correspondence between the sockets and the ECL ports is indicated by silk screen labels printed on the left of the translator sockets In addition to translator ICs proper functioning of ECL ports requires either impedance matching resistor arrays of 8 x 50Q input ports or pull down resistor arrays of 8 x 470Q output ports These two types of arrays share Zig Zag sockets with the exception of their first common pins marked by dots The correspondence between the ECL ports and the 10 position rows of the Zig Zag sockets is indicated by silk screen labels printed on both sides of these sockets Figure 2 illustrates placement of translator chips and resistor arrays for ECL ports A5 A8 configured as inputs and ports A13 A16 configured as outputs Dots indicate pins 1 Fig 2 Placement of ECL port components for inputs blue and
8. pads share ECL ports with ECLD lt 2 gt ECLD lt 4 gt such that pads 90 89 and 89 are directly connected to pads 80 77 and 182 respectively NET ECLCLK A LOC P80 GCKO port D2 NET ECLCLK B OCET RIIT GCK1 port D3 NET ECLCLK_C LOC P182 GCK2 port D4 Siz SUMMARY OF SYSTEM CAMAC COMMANDS System CAMAC commands are used for programming the flash memory selecting the active boot programming sector of this memory and for resetting the FPGA All commands have function code F 19 Asterisks indicate don t care NF 19 A 0 D Data NF 19 A 1 D Data NF 19 A 2 D Data NF 19 A 3 D Data April 2004 Write Data into previously latched special address and latch new special address h5555 into flash memory Write Data into previously latched special address and latch new special address h2AAA into flash memory Write Data into previously latched data address increment the data address counter and latch the new data address into flash memory Write Data into previously latched data address and latch the new data address into flash memory Page 21 Manual ULM52C mdo ULM52C MAN 001 0 NF 19 A 4 D Set the utility CPLD in flash memory programming mode NF 19 A 5 D Exit flash memory programming mode NF 19 A 6 D Data Write Data into previously latched data address and increment the data address counter Don t latch the new data address Z VF 19 A 7 D Reset the data address counter to ze
9. provides sockets for respective polarizing pull down of complementary ECL input line resistor arrays These sockets are located left to the input translator sockets and are associated directly with the adjacent socket This association is also reflected in the silk screen label printed next to the socket Position of the pin 1 common is in this case indicated by the cut corner of the silk screen socket outline top most position The input polarizing resistors should be removed when the particular ports are configured as output ports Note that the use of polarizing resistors is not mandatory unless the user configuration of FPGA relies on a definite polarization It may be however a sound practice to use these resistors with every input translator Note that general rules for bussing of ECL input ports require that only the last port on the bus has its polarizing resistor installed 4 1 2 3 CONFIGURING OUTPUT PULL DOWN RESISTORS For a proper operation of ECL output ports 8 x 470Q pull down resistor arrays are to be inserted into proper rows of the Zig Zag sockets Note that each differential ECL output is associated with two signal lines and that both these lines need to be pulled April 2004 Page 9 Manual ULM52C mdo ULM52C MAN 001 0 down via resistors to Veg 5 2V Which is why for one quartet of outputs eight pull down resistors are needed The 8 x 470Q arrays are to be inserted with their common pins entering
10. 15 DQ1 place the FPGA in reset mode 111 NF 19 A 15 D 0 release the FPGA from reset mode A failure to boot configure is indicated by all six user LEDs on 4 3 PROGRAMMING OF THE CONFIGURATION MEMORY The FPGA XC28200 of the XILINX Spartan II series configuration file is 166980 bytes long It is generated by a proper software such as the XILINX Foundation Express ISE4 2 and higher and WebPack5 1 and higher in a form of a binary or ASCII file Both files start with some header data which must be skipped so that only the true configuration data is downloaded into the ATMEL AT29C040A Programmable Erasable Read Only Memory PEROM called here Flash Memory This memory chip can accommodate up to two ULMS52C configuration files Which part of the chip is programmed or used by the FPGA the active section is decided by default by the setting of the jumper JP20 on the ULM52C board or by a selection performed via CAMAC commands as described in Section 4 2 5 further above The manufacturer algorithm for programming an AT29C040A requires programming in 256 byte long sectors of data each sector programming sequence followed by a wait period During this wait period the memory chip executes an embedded protocol moving the 256 bytes of data from a buffer into the memory proper Programming of any sector must begin by a sequence of sector unlock commands Upon programming the 256 byte sector is automatically protected from inadvertent p
11. 2 59 RW lt 2 gt 10 44 RW lt 10 gt 18 33 RW lt 18 gt 3 58 RW lt 3 gt 11 43 RW lt 11 gt 19 31 RW lt 19 gt 4 57 RW lt 4 gt 12 42 RW lt 12 gt 20 30 RW lt 20 gt 5 49 RW lt 5 gt 13 41 RW lt 13 gt 21 29 RW lt 21 gt 6 48 RW lt 6 gt 14 37 RW lt 14 gt 22 27 RW lt 22 gt 7 47 RW lt 7 gt 15 36 RW lt 15 gt 23 24 RW lt 23 gt 8 46 RW lt 8 gt 16 35 RW lt 16 gt 24 23 RW lt 24 gt Table 2 Association between CAMAC control lines physical FPGA pad numbers and their respective UCF names Control FPGA UCF Control FPGA UCF Control FPGA UCF line Pad Name line Pad Name line Pad Name Fl 7 F lt 0 gt Al 17 A lt 0 gt C 10 C F2 6 F lt l gt A2 16 A lt 1 gt I 9 I F4 5 F lt 2 gt A4 14 A lt 2 gt N 15 N F8 4 F lt 3 gt A8 8 A lt 3 gt L 22 LAM FI6 3 F lt 4 gt Sl 18 S lt 1 gt X 6l X Z 21 Z S2 20 S lt 2 gt Q 62 Q 4 2 2 PADS ASSOCIATED WITH ECL PORTS As described in Section 4 1 ULM52C features a total of 52 ECL ports organized in three 34 pin and one 8 pin header named A D respectively The ECL ports communicate exclusively with FPGA For the actual numbers of the FPGA pads associated with individual ECL ports see Table 3 below and also Appendix A This appendix lists with abundant comments the relevant section of a user constraint file ucf that can be used at the implementation time of the April 2004 Page 12 Man
12. 33 ET ECLB lt 6 gt LOC P134 ET ECLB lt 7 gt LOC P129 ET ECLB lt 8 gt LOC P132 ET ECLB lt 9 gt LOC P126 ET ECLB lt 10 gt LOC P127 ET ECLB lt 11 gt LOC P123 ET ECLB lt 12 gt LOC P125 ET ECLB lt 13 gt LOC P121 ET ECLB lt 14 gt LOC P122 ET ECLB lt 15 gt LOC P120 ET ECLB lt 16 gt LOC P119 ET ECLC lt 1 gt LOC P115 ET ECLC lt 2 gt LOC P114 ZZ ZZZZ gt ZZZZAZZZZ AAZZZZAZZZZ 2222 ZAR ZEAE April 2004 Page 20 Manual ULM52C mdo ULM52C MAN 001 0 NET ECLC lt 3 gt LOC P112 NET ECLC lt 4 gt LOC P113 NET ECLC lt 5 gt LOC P110 NET ECLC lt 6 gt LOC P111 NET ECLC lt 7 gt LOC P109 NET ECLC lt 8 gt LOC P108 NET ECLC lt 9 gt LOC P101 NET ECLC lt 10 gt LOC P102 NET ECLC lt 11 gt LOC P99 NET ECLC lt 12 gt LOC P100 NET ECLC lt 13 gt LOC P97 NET ECLC lt 14 gt LOC P98 NET ECLC lt 15 gt LOC P95 NET ECLC lt 16 gt LOC P96 NET ECLD lt 1 gt LOC P94 NET ECLD lt 2 gt LOC P90 NET ECLD lt 3 gt LOC P89 NET ECLD lt 4 gt LOC P88 ECL port clock pads inputs Note that clock
13. 52C MAN 001 0 JTEC Model ULM52C Universal Logical Module 1 OVERVIEW JTEC Model ULMS2C is a highly versatile general purpose programmable universal logical module for use in CAMAC based systems By design it can communicate with external devices via 52 front panel ECL ports which can be configured in quartets either as inputs or outputs The ECL ports are mapped onto the ports of the user FPGA an XC2S200 by Xilinx On the other end ULM52C communicates with computers via the CAMAC bus utilizing full set of CAMAC commands and a 24 bit data bus Furthermore ULM52C features an on board 4 MByte EEPROM or flash memory allowing one to store up to two FPGA configuration files Few digital applications are outside of ULM52C range 1 1 SUMMARY OF FEATURES e 52 programmable front panel ECL ports configurable in quartets as either inputs or outputs organized in three 34 pin and one 8 pin headers Three ports can be configured as external clock ports of the FPGA e One user programmable FPGA XC2S200 6PQ208C by Xilinx Inc e One 4 MByte programmable erasable read only memory holding up to two FPGA configuration files o e Six front panel LEDs mapped onto ports of the user FPGA e FastCamac ready 1 2 POSSIBLE APPLICATIONS e Intelligent Data Buffer e Scalers Prescalers Coincidence Registers Time Stampers e Multilevel Trigger Logics e Digital Delay and Gate Generators e Detector Readout Processor e Histogramming Memory
14. C DRIVEN BY FORCE OF LOGIC User s Manual Model ULM52C Universal Logical Module For CAMAC Systems JTEC Instruments 32 Thompson Rd Rochester NY USA Tel 585 334 7215 http www jtec instruments com Information furnished by JTEC Instruments JTEC is believed to be accurate and reliable However no responsibility is assumed by JTEC for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patents rights of JTEC JTEC reserves the right to change specifications at any time without notice Copyright 2004 by JTEC Manual mdo ULM52C MAN 001 1 April 2004 Manual ULM52C mdo ULM52C MAN 001 0 TABLE OF CONTENTS Tes OMER VIEW yes up Sie nee AON Re Ae at aes ee rel fea os Ln Ad 2 1 1 SUMMARY OF FEATURES aion enetan e se divan asyo ve ate de loa vou dee ako ae an ekivo kmanse ekite vi tes de ie 2 1 27 POSSIBLE APPLICATIONS sites os sissies videos ey eya candi go sens bw eata dako E cvvie seed en pepe vye d oue re vo plase a 2 2 SPECIFICATIONS iero iii 3 35 ARCHITECTURE esc ai onn ali salt an Saved laca liada arid baay a De Eia 4 3 1 FIELD PROGRAMMABLE GATE ARRAY 0 0LiLelleieeelovoeeteetenooenoenonooeooenosooonoonosenennoenoenosononse 4 Sali de REASH MEMORY tib Ganr a e e is d s koni shine boo dese do bn ako abi sy okte kodase tie colectas 5 E JUTE EEE C PLD ove sit A AA ONES 5
15. C interface A utility CPLD controls the direction of data flow through the transceivers according to standard rules of CAMAC It allows one to program the on board flash memory with the FPGA configuration file and at the boot time of the FPGA it serializes the 8 bit flash memory words into a stream of single bits presented to the FPGA ECL PORTS Fig 1 Block diagram of ULM52C 3 1 FIELD PROGRAMMABLE GATE ARRAY The desired logical operations of ULM52C are to be programmed by the user into a Xilinx XC2S200 6PQ208C field programmable gate array chip FPGA Any logic that can be implemented as synchronous state machine or combinatorial equation may be programmed subject only to the availability of resources of the XC2S200 chip which are quite vast These resources include among other things April 2004 Page 4 Manual ULM52C mdo ULM52C MAN 001 0 i 5 292 logic cells 11 200 000 system gates iii 75 264 bits of distributed RAM iv 56kBits of block RAM v Clock management with 4 DLLs and vi Fast Carry Logic The FPGA is clocked at 100 MHz from an on board clock but can be also clocked externally via one of three special ECL ports at rates of up to 110 MHz The on board clock can be disabled by the FPGA firmware 3 1 1 FLASH MEMORY To provide for the storage of the FPGA configuration data ULM52C is equipped with one 4 MBit Programmable Erasable Read Only Memory Flash Memory an ATMEL AT29CC040A The si
16. G position of JP16 two right most pins is intended for in system programming reprogramming of the FPGA via the 6 pin JP10 JTAG header See also Fig 3 4 1 3 2 JP20 SETTINGS DEFAULT BOOT SECTOR The flash memory is capable of accommodating two FPGA configuration files Upon power up the FPGA boots from the sector of the memory selected by the default boot sector select jumper JP20 Sector 0 corresponds to the jumper connecting two leftmost pins of JP20 while Sector 1 to two rightmost pins connected Subsequently user may override the default selection by issuing proper CAMAC commands The command for selecting sector 0 is NF 19 A 14 D 0 and for selecting sector 1 is NF 19 A 14 D 1 To warm reboot the FPGA one must issue CAMAC commands NF 19 A 15 1 set FPGA in reset mode PGRM pin of the FPGA pulled Low and NF 19 A 15 0 release the FPGA from reset mode PGRM pin High April 2004 Pag Manual ULM52C mdo ULM52C MAN 001 0 FPGA TAG Fig 3 Location of jumpers Boot Mode Default Boot Sector 4 2 PROGRAMMING OF THE USER FPGA A successful use of ULM52C hinges critically on the quality of the user code loaded into its XC2S200 FPGA To write such a code the user must know the role of all pins of the FPGA as assigned to them by the design of the ULM52C 4 2 1 PADS ASSOCIATED WITH CAMAC INTERFACE The design of the ULM52C allows one to implement a complete CAMAC interface with a full 24 bit data bus
17. Therefore care should be taken to correctly identify and populate the sockets with translator ICs When not sure please consult JTEC Support service Rule 1 Only one translator IC either input or output is allowed for any single port Which in practical terms means that in any horizontal pair of sockets at most one should be filled Rule 2 When configuring input ports MC10125 it must be ascertained that the corresponding ports of the FPGA are configured indeed as input ports and not as output ports Rule 3 ULMS2C requires differential ECL inputs and will not function properly no damage will occur though with single ended ECL signals Which means among other things that these inputs cannot be driven by an ECL bus connected to ECL outputs of multiple external devices Rule 4 When configuring output ports make sure that the input polarizing resistor arrays for the particular quartets of ECL ports are removed from their respective sockets April 2004 Page 7 Manual ULM52C mdo ULM52C MAN 001 0 4 1 2 CONFIGURING ECL PORTS ECL to TTL conversion input and TTL to ECL conversion output is accomplished by 16 pin MC10125 and MC10124 ICs respectively Each converter IC is capable of interfacing up to four differential ECL ports to respective four TTL ports of the user FPGA Differential inputs of these ICs are directly connected to respective pairs of pins of front panel headers The headers are identified going
18. able 4 Front panel LED control pads of the FPGA LED FPGA UCF Name of LED FPGA UCF Name of Pad FPGA Pad Pad FPGA Pad Left Red 180 RLED L Right Red 179 RLED R Left Green 178 GLED L Right Green 176 GLED R Left Yellow 175 YLED L Right Yellow 174 YLED R 4 2 4 PADS ASSOCIATED WITH USER CLOCK AND CLOCK ENABLE User clock running at 100MHz is connected to pad 185 which is named USRCLK in the UCF file The clock enable active High is controlled by pad 188 named USRCLKENA By default the clock is running as the clock enable line is pulled High through a resistor The clock can be disabled by setting USRCLKENA Low in the FPGA configuration 4 2 5 CONFIGURING FPGA ULM52C offers two ways of configuring the FPGA 1 via the JTAG port or 11 from Flash Memory Programming via the JTAG port is recommended for development work when frequent reconfiguring is anticipated Configuring from Flash Memory requires prior storing of the desired configuration file in one of the two sectors of the memory chip The sector is selected upon power up according to the setting of the default boot selector jumper JP16 To boot the FPGA from the non default sector one must select the desired sector via April 2004 Page 14 Manual ULM52C mdo ULM52C MAN 001 0 CAMAC and then cause warm reboot by issuing the following set of CAMAC commands 1 NF 19 A 14 D 0 1 select sector 0 1 11 NF 19 A
19. ay input 5 ConfigData close the input file close 5 search for the start of configuration data hFF 255 skip the header data PointerToByte 1 while ConfigData PointerToByte lt gt 255 PointerToByte PointerToByte 1 Wend now PointerToByte points to first configuration byte enter flash memory programming mode CamacWrite16 N 4 19 reset address counter to zero CamacWrite16 N 7 19 loop over sectors for SectorNumber 1 to 653 loop over bytes in sector for ByteInSector 1 to 256 note that due to CAMAC negative logic the CAMAC data to be written is complement of ConfigData i e CamacLoadData not ConfigData CamacLoadData not ConfigData PointerToByte If AutoProtect then start programming a new sector with writing unlock codes latch special address h5555 CamacWrite16 N 0 19 0 write hAA to the latched address h5555 and latch new special address h2AAA note that due to CAMAC negative logic the CAMAC data to write is h55 not hAA CamacWrite16 N 1 19 h55 write h55 to the latched address h2AAA and latch new special address h5555 note that due to CAMAC negative logic the CAMAC data to write is hAA not h55 CamacWrite16 N 0 19 hA A write hA0 to the latched special address h5555 and latch data byte address April 2004 Page 16 Manual ULM52C mdo ULM52C MAN 001 0 note that due to CAMAC negative logic the CAMAC data to write is hSF not hA0 CamacWrite16 N 3 19 h5F Else
20. latch data address for next write operation CamacWrite16 N 12 19 0 End if if ByteInSector 256 then write data but don t latch next data address for the last byte in sector CamacWrite16 N 6 19 CamacLoadData increment PointerToByte PointerToByte PointerToByte 1 Else programm the presently latched address with the configuration byte found at the ConfigData PointerToByte increment data address and latch it CamacWrite16 N 2 19 CamacLoadData increment PointerToByte PointerToByte PointerToByte 1 end if next ByteInSector wait for the 256 byte long sector programmed into AT29C040A by the embedded firmware of this chip Delay 40 next SectorNumber exit programming mode CamacWrite16 N 5 19 0 End Sub Sample VB codes for setting and resetting of the software protection are given below Sub Protect sets software protection CamacWrite16 N 4 19 CamacWritel 6 N 0 19 0 CamacWrite16 N 1 19 h55 CamacWrite16 N 0 19 hA A CamacWrite16 N 6 19 h5F CamacWrite16 N 5 19 End Sub Sub UnProtect sets software protection CamacWrite16 N 4 19 CamacWritel 6 N 0 19 0 CamacWrite16 N 1 19 h55 CamacWrite16 N 0 19 hA A CamacWrite16 N 0 19 h7F April 2004 Page 17 Manual ULM52C mdo ULM52C MAN 001 0 CamacWrite16 N 1 19 h55 CamacWrite16 N 0 19 hA A CamacWrite16 N 6 19 hCF CamacWrite16 N 5 19 End Sub April 2004 Page 18 Manual ULM52C mdo ULM52C MAN 001 0 5
21. nt panel light emitting diodes LED all controlled by the user configuration of the FPGA Every LED is driven by a pulse length extender such that even short 20ns long pulses sent by the FPGA produce robust flashes while April 2004 Page 5 Manual ULM52C mdo ULM52C MAN 001 0 long pulses or DC levels are passed to the LED unaltered For an unconfigured FPGA all LEDs are on and hence these LEDs serve as status indicators of the FPGA booting April 2004 Page 6 Manual ULM52C mdo ULM52C MAN 001 0 4 OPERATING INSTRUCTIONS Successful operation of ULM52C requires its proper hardware setup and configuring of its user FPGA 4 1 HARDWARE SETUP The hardware setup of ULM52C includes i configuring its front panel ECL ports for operation in conjunction with the intended FPGA configuration and ii making sure that the two blocks of jumpers JP16 and JP20 controlling the boot process are configured properly Furthermore one is expected to connect respective ECL ports to external devices with twisted pair or flat ribbon cables The ECL ports are configurable in quartets either as inputs or outputs The three ports identified by silk screen labels on the front panel and on the ULM52C board as D2 E4 play a special role as they connect additionally via ECL to TTL translators MC10125 to clock inputs GCKO GCK2 of the FPGA 4 1 1 IMPORTANT RULES Improper configuring of ECL ports may result in the unit not functioning properly
22. outputs yellow April 2004 Page 8 Manual ULM52C mdo ULM52C MAN 001 0 4 1 2 1 CONFIGURING IMPEDANCE MATCHING RESISTOR ARRAYS FOR ECL INPUT PORTS As noted in subsection 4 1 2 further above to avoid reflections of incoming signals from the ECL input ports 8 x 50Qresistor arrays are to be inserted into proper rows of the Zig Zag sockets Note that each differential ECL input is associated with two signal lines and that both these lines need to be terminated Which is why for one quartet of inputs eight terminating resistors are needed The 8 x 50Q arrays are to be inserted with their common pins entering positions marked as Il bottom most positions of the 5 vertical Zig Zag sockets and left most positions of the 2 horizontal Zig Zag sockets Warning Even though each row of a 20 pin Zig Zag socket is capable of accommodating a typical commercial 9 x 50Q resistor array with ten pins one should use only 8 x 50Q arrays This is so because the pins on the opposite end with respect to I1 of the Zig Zag sockets labeled as O1 are connected to 5 2V to supply pull down voltage for output port resistor arrays 8 x 470Q see also sub section 4 1 2 3 Note that general rules for bussing of ECL input ports require that only the last port on the bus has its terminating resistor installed 4 1 2 2 CONFIGURING INPUT POLARIZING RESISTORS To guarantee a default logical zero at ECL input ports that are not externally driven ULM52C
23. positions marked as O1 top most positions of the 5 vertical sockets and right most positions of the two horizontal Zig Zag sockets Warning Even though each row of a 20 pin Zig Zag socket is capable of accommodating a typical commercial 9 x 4700 resistor array with ten pins one should use only 8 x 4700 arrays This is so because the pins on the opposite end with respect to O1 of the Zig Zag sockets labeled as I1 are connected to ECL bias voltage to supply terminating voltage for input port resistor arrays 8 x 50Q see also sub section 4 1 2 1 Note that general rules for bussing of ECL output ports require that only the last port on the bus has its pull down resistor installed 4 1 3 JUMPER SETTINGS There are two jumper blocks on the ULM52C board that must be properly configured for a normal operation of the module These are the 3 pin FPGA boot mode selection jumper JP16 next to the bottom left corner of the XC2S200 FPGA and the 3 pin default boot sector selection jumper JP20 above the AT29C040A flash memory 4 1 3 1 JP16 SETTINGS FPGA BOOT MODE JP16 has two positions identified by silk screen labels FLASH and JTAG respectively in Rev 0 silkscreen is missing For normal operation the jumper should be placed in the FLASH position 1 e connecting the two left most pins of JP16 This allows FPGA to boot upon power up from the default boot sector of the flash memory socketed AT29C040A The JTA
24. ro NF 19 A 12 D Latch the data address into flash memory YF 19 A 14 D 0 Select the first half of the flash memory as an active sector 0 JF 19 A 14 D 1 Select the second half of the flash memory as an active sector 1 ZZ NF 19 A 15 D 0 Release the FPGA from reset state drive the PRGM pin High NF 19JA 15 D 1 Set the FPGA in reset state pull the PRGM pin Low April 2004 Page 22
25. rogramming requiring always the unlock sequence for intentional programming The electrical signals necessary for the flash memory programming are generated by the utility CPLD in response to CAMAC commands Below listed is a sample Visual Basic code which allows one to program the configuration into the flash memory There are two ways of achieving software protection of the AT29C040A data One consists in preceding programming of each 256 byte long sector of this memory by a sequence of protection codes and is named here the autoprotect mode In the other mode one resets the protection of the memory by a sequence of codes programs the memory and sets the protection when so desired Note that the function code for all flash memory programming operations is F 19 Where the write data is arbitrary it is indicated by an asterix 1 e D April 2004 Page 15 Manual ULM52C mdo ULM52C MAN 001 0 Sub Flash ConfFile as string AutoProtect as Boolean VB code to load the FPGA configuration data into AT29C040A AutoProtect True causes programming in autoprotection mode ConfFile is the name of the configuration file produced by suitable software dim ConfigData 1 to 167300 as Byte extra length added to accommodate header dim PointerToByte as Long dim ByteInSector as Integer dim CamacLoadData as Integer open file with configuration data open ConfFile for input as 5 read the file into the ConfigData arr
26. ual ULM52C mdo ULM52C MAN 001 0 FPGA code Note that the user has no particular interest in knowing the pin associations as the UCF file takes care of this task automatically provided the design uses the proposed naming scheme Table 3 Association between ECL ports physical FPGA pad numbers and their respective UCF names ECL FPGA Pad UCF Name of ECL FPGA Pad UCF Name of Port FPGA Pad Port FPGA Pad Al 167 ECLA lt 1 gt B13 121 ECLB lt 13 gt A2 166 ECLA lt 2 gt B14 122 ECLB lt 14 gt A3 164 ECLA lt 3 gt B15 120 ECLB lt 15 gt A4 165 ECLA lt 4 gt B16 119 ECLB lt 16 gt A5 162 ECLA lt 5 gt CI 115 ECLC lt 1 gt A6 163 ECLA lt 6 gt C2 114 ECLC lt 2 gt A7 160 ECLA lt 7 gt C3 112 ECLC lt 3 gt A8 161 ECLA lt 8 gt C4 113 ECLC lt 4 gt A9 149 ECLA 9 C5 110 ECLC lt 5 gt A10 150 ECLA lt 10 gt C6 111 ECLC lt 6 gt All 148 ECLA lt 11 gt C7 109 ECLC lt 7 gt A12 147 ECLA lt 12 gt C8 108 ECLC lt 8 gt A13 142 ECLA lt 13 gt C9 101 ECLC lt 9 gt Al4 146 ECLA lt 14 gt C10 102 ECLC lt 10 gt Al5 141 ECLA lt 15 gt C11 99 ECLC lt 11 gt A16 140 ECLA lt 16 gt C12 100 ECLC lt 12 gt BI 139 ECLB lt 1 gt C13 97 ECLC lt 13 gt B2 136 ECLB lt 2 gt C14 98 ECLC lt 14 gt B3 135 ECLB lt 3 gt C15 95 ECLC lt 15 gt B4 138 ECLB lt 4 gt C16 96 ECLC lt 16 gt B5 133
27. ze of this memory is sufficient to accommodate up to two XC28200 configuration files one of which serves as a default boot configuration The Flash Memory can be reprogrammed in system via CAMAC interface The chip is socketed and is rated for 10 000 programming cycles and 20 year data retention 3 1 2 UTILITY CPLD To provide for the capability of in system programming of the flash memory ULM52C is equipped with a Complex Programmable Logical Device CPLD an XC95144XL by Xilinx During the FPGA boot process this CPLD converts 8 bit data words of the Flash Memory into a stream of configuration bits presented to the FPGA Furthermore through this utility CPLD one can select the boot sector of the FPGA overriding the setting of the boot selection jumper It has also control over the reset PRGM pin of the FPGA allowing one for a warm reboot of the FPGA 3 1 3 ECL PORTS ULM52C is equipped with 52 ECL ports organized in three 34 pin and one 8 pin header The ports are controlled exclusively by the FPGA and can be configured in quartets as either inputs or outputs but always unidirectional Three ECL ports serve special role as they are associated with clock inputs GCKO GCK1 and GCK2 of the FPGA As such they can serve as inputs for external clock signals to the FPGA These three ports connect also to standard I O pads of the FPGA and hence can be used also as normal ECL ports 3 1 4 USER LEDs ULM5S2C is equipped with six fro
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