Introduction to the Altera SOPC Builder Using VHDL Designs
Contents
1. clock B clk irq m interrupt reset Preset avalon B javalon_jtag_slave Write FIFO Data from Avalon to JTAG Buffer depth bytes 54 v IRQ threshold 8 C Construct using registers instead of memory blocks Read FIFO Data from JTAG to Avalon Buffer depth bytes 64 v IRQ threshold 8 C Construct using registers instead of memory blocks gt Simulated input character stream Contents i Prepare interactive windows Options INTERACTIVE_ASCI_OUTPUT Y Allow multiple connections O Allow muttiple connections to Avalon JTAG slave Figure 12 Define the JTAG UART interface 10 The complete system is depicted in Figure 13 Note that the SOPC Builder automatically chooses names for the various components The names are not necessarily descriptive enough to be easily associated with the target design but they can be changed In Figure 2 we use the names Switches and LEDs for the parallel input and output interfaces respectively These names can be used in the implemented system Right click on the pio_O name and then select Rename Change the name to Switches Similarly change pio_1 to LEDs 11 The base and end addresses of the various components in the designed system can be assigned by the user but they can also be assigned automatically by the SOPC Builder We will choose the latter possibility So select the command using the m2. coed lt i Bee E Figure 15 Define the reset vector and exception vector 13 Having specified all components needed to implement the desired system it can now be generated Select the System Generation tab which leads to the window in Figure 16 Turn off Simulation Create project simulator files because in this tutorial we will not deal with the simulation of hardware Click Generate on the bottom of the SOPC Builder window The SOPC Builder may prompt you to save changes to sopc fila Click Save to proceed The generation process produces the messages displayed in the figure When the message SUCCESS SYSTEM GENERATION COMPLETED appears click Exit to return to the main Quartus II window Kies nios_system als filenaam Altera Corporation University Program 17 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Altera SOPC Builder nios_system sopc D sopc_builder_tutorial nios_system sopc File Edit Module System View Tools Nios ll Help System Contents Options System module logic will be created in Verilog C Simulation Create project simulator files Nios Il Tools Nios Il Software Build Tools for Eclipse 2011 05 06 13 40 53 Running Generator Program for Switches 2011 05 06 13 40 54 Running Generator Program for LEDs 2011 05 06 13 40 55 Running Generator Program for jtag_uart_O 2011 05 06 13 40 56 Making arbitration and system top modules 2011
3. Figure 11 The parallel input interface included on a DE series board 8 In the same way specify the output parallel I O interface e Select Peripherals gt Microcontroller Peripherals gt PIO Parallel I O and click Add to reach the PIO Configuration Wizard again e Specify the width of the port to be 8 bits and choose the direction of the port to be Output On a DEO Nano board specify the width of the port to be 4 bits e Click Finish to return to the System Contents tab 9 We wish to connect to a host computer and provide a means for communication between the Nios II system and the host computer This can be accomplished by instantiating the JTAG UART interface as follows Select Interface Protocols gt Serial gt JTAG UART and click Add to reach the JTAG UART Configu ration Wizard in Figure 12 e Do not change the default settings e Click Finish to return to the System Contents tab Na stap 9 moet je een system ID component toevoegen Deze component vind je in SOPC builder bij Peripherals gt Debug and Performance gt Sytem ID Periphiral Verander de naam van het System ID component naar sysid om er voor te zorgen dat deze compatibel is met de Nios drivers en building tools Altera Corporation University Program 13 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS JTAG UART jtag uart_0 Tk JTAG UART Megatore altera_avalon_jtag_uart Documentation Block Diagram
4. functional units such as memories input output interfaces timers and communications interfaces To facilitate the implementation of such systems it is useful to have computer aided design CAD software for implementing a system on a programmable chip SOPC Altera s SOPC Builder is the software needed for this task This tutorial provides a basic introduction to Altera s SOPC Builder which will allow the reader to quickly implement a simple Nios II system on the DE series board For a fuller treatment of the SOPC Builder the reader can consult the Nios II Hardware Development Tutorial A complete description of the SOPC Builder can be found in the Quartus II Handbook Volume 4 SOPC Builder These documents are available on the Altera web site An example Nios II system can be implemented on a DE series board as shown in Figure 1 Host computer USB Blaster interface JTAG UART interface JTAG Debug module Avalon switch fabric Nios II processor SRAM SDRAM Flash Parallel O Serial O interface interface EMOTY interface interface interface Parallel T O port T O port lines lines Figure 1 A Nios II System implemented on a DE series board 2 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS The Nios II processor and the interfaces needed to connect to other chips on DE series boards are implemented in Cyclone s
5. System Contents System Generation Component Library Target Clock Settings 4 x Device Family Cyclone Il v Name Source clk_O External Project A H New component J Library Avalon Verification Suite Bridges and Adapters Debug Components Digital Signal Processing nterface Protocols Legacy Components Memories and Memory Contro Merlin Components Peripherals Debug and Performance Display G FPGA Peripherals Microcontroller Peripheral Interval Timer o Multiprocessor Coordinati aoa 9 Remove Eea a la v Address Map F Fiters Fiter Detaut To Do cpu_0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue To Do epu_0 No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Info onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex A inta nio M PIO innuts are not hardwired in test bench Undefined values will be read from PIO innuts during simulation 4 Next gt Generate Use Conn Name Description E cpu_o Nios Il Processor instruction_master Avalon Memory Mapped Master data_master Avalon Memory Mapped Master jtag_debug_module Avalon Memory Mapped Slave E onchip_memory2_0 On Chip Memory RAM or ROM Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave
6. debugging session by clicking the Actions gt Disconnect menu item 2 Click the Settings gt Program Settings menu item to launch the Project settings window with the Program settings tab selected 3 Select C Program as the Program Type in the drop down list The Monitor Program may prompt you to clear any currently selected source files Click Yes to proceed Note that lights s has been removed from the list of source files 4 Click Add and choose the lights c file 5 Click Ok to confirm the new program configuration The steps to compile load and run the program are the same as for an assembly language program 28 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Copyright 1991 2011 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but res
7. ji a viz Fitter Default To Do epu_0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue To Do epu_0 No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Info onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex Info pio_0 PIO inputs are not hardwired in test bench Undefined values will be read from PIO inputs during simulation Figure 13 The complete system on a DE series board Altera Corporation University Program May 2011 15 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS DoR Altera SOPC Builder Fie Edt Module System View Tools Niosil Help System Contents System Generation Component Library Target Clock Settings 4 x Device Family Cyclone Il v Name Source cik_0 External Project H New component Library Avalon Verification Suite Bridges and Adapters Debug Components Digital Signal Processing Hntertace Protocols ASI Ethernet H High Speed HInterlaken PCI Conn Name E cpu_0 instruction_master data_master jtag_debug_module E onchip_memory2_0 s1 E Switches Description Nios Il Processor Avalon Memory Mapped Master Avalon Memory Mapped Master Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave PIO Parallel 1 0 IRQ 0 IRQ 31 0x000028
8. switches SW3 0 and four LEDs LED3 0 We will use the SOPC Builder to design the hardware depicted in Figure 2 Next we will assign the Cyclone series pins to realize the connections between the parallel interfaces and the switches and LEDs which act as I O devices Then we will configure the FPGA to implement the designed system Finally we will use the software tool called the Altera Monitor Program to assemble download and execute a Nios II program that performs the desired task Doing this tutorial the reader will learn about e Using the SOPC Builder to design a Nios I based system e Integrating the designed Nios I system into a Quartus II project e Implementing the designed system on the DE series board e Running an application program on the Nios II processor 3 Altera s SOPC Builder The SOPC Builder is a tool used in conjuction with the Quartus II CAD software It allows the user to easily create a system based on the Nios II processor by simply selecting the desired functional units and specifying their parameters To implement the system in Figure 2 we have to instantiate the following functional units e Nios II processor which is referred to as a Central Processing Unit CPU e On chip memory which consists of the memory blocks in the Cyclone series chip we will specify a 4 Kbyte memory arranged in 32 bit words e Two parallel I O interfaces e JTAG UART interface for communication with the host computer To d
9. to reach the window in Figure 15 Select onchip_memory2_0 to be the memory device for both reset vector and exception vector as shown in the Figure 15 e Do not change the default setting for offset e Click Finish to return to the System Contents tab 16 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Nios Processor cpu_0 Nios II Processor Documentation Caches and Memory Interfaces Advanced Features MMU and MPU Settings JTAG Debug Module Custom Instru Core Nios Il Select a Nios Il core JONios lie ONios Ii s ONios If RISC RISC RISC Nios Il 32 bit 32 bit 32 bit Selector Guide Instruction Cache Instruction Cache Family Cyclone ll Branch Prediction Branch Prediction Hardware Multiply Hardware Multiply feystem 50 0 MHz Hardware Divide Hardware Divide Barrel Shifter Data Cache Dynamic Branch Prediction Performance at 50 0 MHz UptoSDMIPS Up to 25 DMIPS Up to 51 DMIPS Logic Usage 600 700 LEs 1200 1400 LEs 1400 1800 LEs Memory Usage Two M4Ks or equiv Two M4Ks cache Three M4Ks cache cpuid 0 Hardware Multiply Reset Vector Memory onchip_memory2_0 0x00001000 Exception Vector Memory RETEST eran v Offset 0x00001020 Include MMU Only include the MMU when using an operating system that explicitly supports an MMU Fast TLB Miss Exception Vector Memory Offset p Include MPU
10. will be specified Click OK to reach the window in Figure 5 Quartus may recommand you to use Qsys Click OK to proceed Altera Corporation University Program 5 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS New Project Wizard Directory Name Top Level Entity page 1 of 5 What is the working directory For this project D sopc_builder_tutorial What is the name of this project lights m What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design file lights O had Use Existing Project Settings lt Back Finish Cancel Help Figure 3 Create a new project Board Device Name DEO Cyclone III EP3C16F484C6 DEO Nano Cyclone IVE EP4CE22F17C6 DE1 Cyclone II EP2C20F484C7 DE2 Cyclone II EP2C35F672C6 DE2 70 Cyclone II EP2C70F896C6 DE2 115 Cyclone IVE EP4CE1 15F29C7 Table 1 DE series FPGA device names 6 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS I Create New System System Name nios_system Target HDL Verilog Figure 4 Create a new Nios II system 3 Figure 5 displays the System Contents tab of the SOPC Builder which is used to add components to the system and configure the selected components to meet the design requirements The availa
11. window on a DE series board Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS 5 Next specify the processor as follows e On the left side of the window in Figure 5 expand Processors select Nios Il Processor and click Add which leads to the window in Figure 6 Nios I Processor cpu_0 E3 Nios II Processor Core Nios II Caches and Memory Interfaces Advanced Features MMU and MPU Settings JTAG Debug Module Custom Instructions Core Nios Il Select a Nios II core JONios le ONios ll s ONios II RISC RISC RISC Nios Il 32 bit 32 bit 32 bit Selector Guide Instruction Cache Instruction Cache Family Cyclone Il Branch Prediction Branch Prediction Hardware Multiply Hardware Multiply teystem 50 0 MHz Hardware Divide Hardware Divide it Barrel Shifter Coulee Data Cache Dynamic Branch Prediction Performance at 50 0 MHz Upto SDMIPS Up to 25 DMIPS Upto 51 DMIPS Logic Usage 600 700 LEs 1200 1400 LEs 1400 1800 LEs Memory Usage Two M4Ks or equiv Two M4Ks cache Three M4Ks cache Hardware Multiply Embedder hiuttinlie Hardware Divide Reset Vector Memory v Offset oxo Exception Vector Memory v Offset 0x20 Include MMU Only include the MMU when using an operating system that explicitly supports an MMU Fast TLB Miss Exception Vector Memory Offset 5 9 Include MPU A Warning Reset vector and Exception vec
12. 00 Disassembly Breakpoints Memory Watches Trace Terminal rl9 0x00000000 JTAG UART link established using cable USB Blaster USB 0 device 1 instance 0x00 ibd Info amp Errors ak Verified 0K a Connection established to GDB server at localhost 240 Symbols loaded Source code loaded INFO Program Trace not enabled because trace requirti v Info amp Errors GDB Server Figure 26 Display of the downloaded program e single stepping through the program e examining the contents of processor registers e examining the contents of the memory e setting breakpoints for debugging purposes e disassembling the downloaded program Altera Corporation University Program May 2011 27 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS A description of this software and all of its features is available in the Altera Monitor Program tutorial 5 2 Using a C Language Program An application program written in the C language can be handled in the same way as the assembly language pro gram A C program that implements our simple task is given in Figure 27 Enter this code into a file called lights c define Switches volatile char 0x0003000 define LEDs char 0x0003010 void main while 1 LEDs Switches Figure 27 C language code to control the lights Perform the following steps to use this program 1 Disconnect from the current
13. 00 Ox0000Zfft 0x00001000 Ox00001fft 0x00003000 0x0000300f SDI Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave JTAG UART Avalon Memory Mapped Slave Serial Avalon ST JTAG 0x00003010 Ox0000301f Avalon ST Serial SPI 3 Wire Serial UART RS 232 Se Y gt dP Add E jtag_uart_0 avalon_jtag_slave 0x00003020 0x00003027 lt XC Remove 5 Edit x La C z Address Map F Fitters Fitter Default To Do epu_0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue To Do epu_0 No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Info onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex Info Switches PIO inputs are not hardwired in test bench Undefined values will be read from PIO inputs during simulation q Pre Next gt Generate Figure 14 The final specification on a DE series board 12 The behaviour of the Nios II processor when it is reset is defined by its reset vector It is the location in the memory device the processor fetches the next instruction when it is reset Similarly the exception vector is the memory address the processor goes to when an interrupt is raised To specify these two parameters perform the following e Right click on the cpu_0 and then select Edit
14. 05 06 13 40 58 Generating Quartus symbol for top level nois_system 2011 05 06 13 40 58 Generating Symbol D sopc_builder_tutorial nois_system bst 2011 05 06 13 40 58 Creating command line system generation script D sope_builder_tutorial nois_system_generation_script 2011 05 06 13 40 58 Running setup for HDL simulator modelsim 2011 05 06 13 40 58 Completed generation for system nois_system 2011 05 06 13 40 58 THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED SOPC Builder database D sopce_builder_tutorial nois_system ptt System HDL Model D sopc_builder_tutorial nois_system v System Generation Script D sopc_builder_tutorial nois_system_generation_script 2011 05 06 13 40 58 SUCCESS SYSTEM GENERATION COMPLETED Info System generation was successful lt Into onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex Info Switches PIO inputs are not hardwired in test bench Undefined values will be read from PIO inputs during simulation Exit Help q Prev Next gt Figure 16 Generation of the system Changes to the designed system are easily made at any time by reopening the SOPC Builder tool Any component in the System Contents tab of the SOPC Builder can be selected and deleted or a new component can be added and the system regenerated 4 Integration of the Nios II System into a Quartus II Project To complete the hardware design we have to perform the
15. 2 Programming and Configuration Program and configure the Cyclone series FPGA in the JTAG programming mode as follows 1 Connect the DE series board to the host computer by means of a USB cable plugged into the USB Blaster port Turn on the power to the DE series board Ensure that the RUN PROG switch is in the RUN position 2 Select Tools gt Programmer to reach the window in Figure 19 3 If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up 4 The configuration file lights sof should be listed in the window If the file is not already listed then click Add File and select it 5 Click the box under Program Configure to select this action 6 At this point the window settings should appear as indicated in Figure 19 Press Start to configure the FPGA W Programmer D sopc_builder_tutorial lights lights lights cdf DER File Edit view Processing Tools Window Help C Enable real time ISP to allow background programming For MAX II and MAX devices Device Checksum Usercode Program Verify Blank Examine Seci wih start B Configure Check wih st il EP2C35F672 0042E4D0 FFFFFFFF Stop ae Auto Detect X Delete ab add File ie Change File ap Save File CELLLLLEI fi up EP2C35F672 ooooooooo gt 4 poooooooo Figure 19 T
16. DESIGNS Altera Monitor Program Nios II DER X Info amp Errors Figure 21 The Altera Monitor Program window on startup 24 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS New Project Wizard E3 Specify a project name and directory D tsopc_buder_tutorial rv fights S O Figure 22 Specify the project directory and name New Project Wizard ied Specify a system a leo har Racinon stam Oooo Figure 23 The System Specification window Altera Corporation University Program 25 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS New Project Wizard Specify program details D sopc_builder_tutorial app_software lights s Figure 24 Specify the binary file to use New Project Wizard Specify program memory settings Figure 25 The program memory settings window 26 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Next to assemble and download the light s program click the Actions gt Compile amp Load menu item The Altera Monitor Program will invoke an assembler program followed by a linker program The commands used to invoke these programs and the output they produce can be viewed in the Info amp Errors window of the Monitor Program window After the program has been downloaded onto the board th
17. ION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Enter this code into a file lights s and place the file into a working directory We placed the file into the direc tory sopc_builder_tutorial app_software The program has to be assembled and converted into an S Record file lights srec suitable for downloading into the implemented Nios II system Altera provides the monitor software called Altera Monitor Program for use with the DE series board This soft ware provides a simple means for compiling assembling and downloading of programs into a Nios II system imple mented on a DE series board It also makes it possible for the user to perform debugging tasks A description of this software is available in the Altera Monitor Program tutorial Open the Altera Monitor Program which leads to the window in Figure 21 This software needs to know the characteristics of the designed Nios II system which are given in the ptf file nios_system ptf Click the File gt New Project menu item to display the New Project Wizard window shown in Figure 22 and perform the following steps 1 Enter the sopc_builder_tutorial directory as the Project directory by typing it directly into the Project directory field or by browsing to it using the Browse button 2 Enter lights as the Project name and click Next gt leading to Figure 23 3 From the Select a System drop down box select lt Custom System gt 4 Click Browse beside the System Description
18. a Introduction to the Altera SOPC Builder Using VHDL Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software which is used to implement a system that uses the Nios II processor on an Altera FPGA device The system development flow is illustrated by giving step by step instructions for using the SOPC Builder in conjuction with the Quartus II software to implement a simple system The last step in the development process involves configuring the designed circuit in an actual FPGA device and running an application program To show how this is done it is assumed that the user has access to an Altera DE series Development and Education board connected to a computer that has Quartus II and Nios II software installed The screen captures in the tutorial were obtained using the Quartus II version 11 0 if other versions of the software are used some of the images may be slightly different Contents e Nios II System e Altera s SOPC Builder e Integration of the Nios II System into a Quartus II Project e Running the Application Program Altera Corporation University Program 1 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS 2 Nios Il System Altera s Nios II is a soft processor defined in a hardware description language which can be implemented in Altera s FPGA devices by using the Quartus II CAD system To implement a useful system it is necessary to add other
19. ale hesen rave raer veraa gt To Do epu 0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue D ToDo epu_0 No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Warning epu_ Reset vector and Exception vector cannot be set until memory devices are connected to the Nios processor Lea e are rp Comete Figure 7 The defined processor on a DE series board 6 To specify the on chip memory perform the following Select Memories and Memory Controllers gt On Chip gt On Chip Memory RAM or ROM and click Add In the On Chip Memory Configuration Wizard window shown in Figure 8 set the Data width to 32 bits and the Total Memory Size to 4 Kbytes 4096 bytes 64 KBytes 65536 bytes e Do not change the other default settings Click Finish which returns to the System Contents tab as indicated in Figure 9 Altera Corporation University Program 9 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS On Chip Memory RAM or ROM onchip_memory2_0 x ER On Chip Memory RAM or ROM Megetere atera_avalon_onchip_memory2 Figure 8 Define the on chip memory 10 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Altera SOPC Builder DER Fie Edit Module System View Tools Niosil Help System Content
20. ble components are listed on the left side of the window Before choosing our components examine the area in the figure labeled Target Check the setting for the Device Family and ensure that the correct family is selected for the DE series board Table 1 lists the device families associated with DE series boards 4 The Nios II processor runs under the control of a clock For this tutorial we will make use of the 50 MHz clock that is provided on the DE series board As shown in Figure 5 it is possible to specify the names and frequency of clock signals in the SOPC Builder display If not already included in this list specify a clock named clk_0 with the source designated as External and the frequency set to 50 0 MHz Altera SOPC Builder File Edit Module System Yiew Tools Help DoR System Contents System Generation Component Library Target 4 x Device Family Cyclone Il Project a OQ New component J Library Avalon Verification Suite Bridges and Adapters Debug Components Digital Signal Processing nterface Protocols Legacy Components Memories and Memory Contro Merlin Components Peripherals PLL H Processor Additions 4 Processors SLS Video and Image Processing gt Clock Settings Name Source clk_0 External Description New F Address Map l F Fitters Filter Default Figure 5 The System Contents tab
21. e program is displayed in the Disassembly window of the Monitor Program as illustrated in Figure 26 Observe that movia is a pseudoinstruction which is implemented as two separate instructions Click the Actions gt Continue menu item to execute the program With the program running you can now test the design by turning the switches SW7 to SW0 on and off the LEDs should respond accordingly The Monitor Program allows a number of useful functions to be performed in a simple manner They include Altera Monitor Program Nios II lights ncf lights srec Paused Eile Settings Actions Windows Help AA IR QPHH NS Disassembly Registers Goto instruction Address hex or symbol name Reg Value Global _start _start movia r2 Switches _start ox00001000 orhi r2 zero 0x0 0x00001004 05c00l4 ori r2 r2 0x3000 movia r3 LEDs 0x00001008 00c00034 orhi r3 zero 0x0 0x0000100c joc04l14 ori r3 r3 Ox3010 loop ldbio r4 Of r2 loop 0x00001010 1 J2 ldbio r4 O r2 stbio r4 O r3 0x00001014 125 stbio r4 O r3 e hr sxc 0x ONNO1 N10 Loon rl 0x00000000 ee Ipc 0x00001000 zero 0x00000000 rl 0x00000000 r2 0x00000000 r3 0x00000000 r4 0x00000000 r5 0x00000000 r 0x00000000 r 0x00000000 Jf r8 0x00000000 r9 0x00000000 rlo ox00000000 rll 0x00000000 rl2 0x00000000 rl3 0x00000000 rl4 0x00000000 rl5 0x00000000 rl6 0x00000000 rls 0x000000
22. efine the desired system start the Quartus II software and perform the following steps 1 Create a new Quartus II project for your system As shown in Figure 3 we stored our project in a directory called sopc_builder_tutorial and we assigned the name lights to both the project and its top level design entity You can choose a different directory or project name but Werken op een USB stick is niet aan te bevelen omdat het dan extra veel tijd kost om te 4 synthetiseren en te compileren Altera Corporation University Program May 2011 Bij stap 1 op pagina 4 moet je gewoon op Next klikken bij de dialogbox die verschijnt na figure 3 Op pagina 6 Bij de volgende dialogbox moet je de juiste FPGA chip device name selecteren volgens de tabel op pagina 6 Daarna nog eenmaal op Next klikken en daarna op Finish INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS does not permit the use of spaces in file names For example an attempt to use a directory name sopc builder tutorial would lead to an error In your project from the list of available devices choose the appropriate device name for the FPGA used on the DE series board A list of devices names on DE series boards can be found in Table 1 2 Select Tools gt SOPC Builder which leads to the pop up box in Figure 4 Enter nios_system as the system name this will be the name of the system that the SOPC Builder will generate Choose VHDL as the target HDL in which the system module
23. enus at the top of the SOPC Builder window System gt Assign Base Addresses which produces the assignment shown in Figure 14 14 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Altera SOPC Builder File Edit Module System View Tools Nios il Help System Contents System Generation Component Library Target Clock Settings 4 x Device Family Cyclone II Name Source leko External Project 0 New component Library Avalon Verification Suite Bridges and Adapters Debug Components Digital Signal Processing Interface Protocols ASI Ethernet High Speed H Interlaken PCI SDI Serial Avalon ST JTAG Avalon ST Serial Name Description E cpu_0 Nios Il Processor instruction_master Avalon Memory Mapped Master data_master Avalon Memory Mapped Master jtag_debug_module Avalon Memory Mapped Slave onchip_memory2_ On Chip Memory RAM or ROM s1 Avalon Memory Mapped Slave E pio_0 PIO Parallel 1 0 s1 Avalon Memory Mapped Slave E pio_1 PIO Parallel 1 0 s1 Avalon Memory Mapped Slave amp jtag_uart_0 JTAG UART avalon_jtag_slave Avalon Memory Mapped Slave SPI 3 Wire Serial UART RS 232 Se Y C lt IRQ 0 0x00000800 0x00002000 0x00000010 IRQ 31 Ox00000 fff Ox0000zfft 0x0000000f 0x0000001f 0x00000027 dp Add 9 Remove E3 eat zZ
24. eries FPGA chips These components are interconnected by means of the interconnection network called the Avalon Switch Fabric The memory blocks in the Cyclone series device can be used to provide an on chip memory for the Nios II processor The SRAM SSRAM SDRAM and Flash memory chips may be accessed through the appropriate interfaces if they are supported on the DE series board Parallel and serial input output interfaces provide typical I O ports used in computer systems A special JTAG UART interface is used to connect to the circuitry that provides a Universal Serial Bus USB link to the host computer to which the DE series board is connected This circuitry and the associated software is called the USB Blaster Another module called the JTAG Debug module is provided to allow the host computer to control the Nios II system It makes it possible to perform operations such as downloading programs into memory starting and stopping execution setting breakpoints and collecting real time execution trace data Since all parts of the Nios II system implemented on the FPGA chip are defined by using a hardware description language a knowledgeable user could write such code to implement any part of the system This would be an onerous and time consuming task Instead one can use the SOPC Builder to implement a desired system simply by choosing the required components and specifying the parameters needed to make each component fit the overall requirements o
25. erves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties repre sentations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed Altera Corporation University Program 29 May 2011
26. f the system In this tutorial we will illustrate the capability of the SOPC Builder by designing a very simple system The same approach is used to design large systems Host computer USB Blaster interface JTAG UART interface JTAG Debug module Avalon switch fabric Switches LEDs parallel input parallel output interface interface Nios II processor SW7 Swo LEDG7 LEDGO Figure 2 A simple example of a Nios II system Altera Corporation University Program 3 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Our example system is given in Figure 2 The system realizes a trivial task Eight toggle switches on the DE series board SW7 0 are used to turn on or off the eight green LEDs LEDG7 0 The switches are connected to the Nios II system by means of a parallel I O interface configured to act as an input port The LEDs are driven by the signals from another parallel I O interface configured to act as an output port To achieve the desired operation the eight bit pattern corresponding to the state of the switches has to be sent to the output port to activate the LEDs This will be done by having the Nios II processor execute a program stored in the on chip memory Continuous operation is required such that as the switches are toggled the lights change accordingly Note that on a DEO Nano board there are only four dip switches Therefore if you have this board use the four dip
27. field to display a file selection window and choose the nios_system ptf file Note that this file is in the design directory sopc_builder_tutorial 5 Specifying the sof file in the Quartus II Programming SOF File field allows the user to download the pro gramming file onto the board from the Altera Monitor Program Note that we need not specify this file as we have already downloaded the programming file onto the board 6 Click Next gt 7 Select Assembly Program as the program type from the drop down menu and click Next gt leading to Figure 24 8 Click Add to display a file selection window and choose the lights s file and click select Note that this file is in the directory sopc_builder_tutorial app_software Upon returning to the window in Figure 24 click Next gt 9 Ensure that the Host Connection is set to the USB Blaster the Processor is set to cpu_0 and the Terminal Device is set to the JTAG UART and click Next gt 10 The Altera Monitor Program also needs to know where to load the application program In our case this is the memory block in the FPGA device The SOPC Builder assigned the name onchip_memory2_0 to this block As shown in Figure 25 the Monitor Program has already selected the correct memory device 11 Having provided the necessary information click Finish to confirm the system configuration Altera Corporation University Program 23 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL
28. following e Instantiate the module generated by the SOPC Builder into the Quartus II project e Assign the FPGA pins e Compile the designed circuit e Program and configure the Cyclone series device on the DE series board 18 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS 4 1 Instantiation of the Module Generated by the SOPC Builder The instantiation of the generated module depends on the design entry method chosen for the overall Quartus II project We have chosen to use VHDL but the approach is similar for both Verilog and schematic entry methods Normally the Nios II module is likely to be a part of a larger design However in the case of our simple example there is no other circuitry needed All we need to do is instantiate the Nios II system in our top level VHDL file and connect inputs and outputs of the parallel I O ports as well as the clock and reset inputs to the appropriate pins on the Cyclone series device The VHDL entity generated by the SOPC Builder is in the file nios_system vhd in the directory of the project Note that the name of the VHDL entity is the same as the system name specified when first using the SOPC Builder The VHDL code is quite large Figure 17 depicts the portion of the code that defines the port signals for the entity nios_system The 8 bit vector that is the input to the parallel port Switches is called in_port_to_the_Switches The 8 bit out
29. he Programmer window Hoofdstuk 5 het laatste hoofdstuk van deze tutorial slaan we over omdat wij de NiosII EDS Embedded Design Suite voor het ontwikkelen van de software geen gebruiken Zie verder op http od eduweb hhs nl es pract0 htm Having configured the required hardware in the FPGA device it is now necessary to create and execute an application program that performs the desired operation This can be done by writing the required program either in the Nios II assembly language or in a high level language such as C We will illustrate both approaches 5 Altera Corporation University Program 21 May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS A parallel I O interface generated by the SOPC Builder is accessible by means of registers in the interface Depend ing on how the PIO is configured there may be as many as four registers One of these registers is called the Data register In a PIO configured as an input interface the data read from the Data register is the data currently present on the PIO input lines In a PIO configured as an output interface the data written by the Nios II processor into the Data register drives the PIO output lines If a PIO is configured as a bidirectional interface then the PIO inputs and outputs use the same physical lines In this case there is a Data Direction register included which determines the direction of the input output transfer In our unidirectional PIOs it is o
30. n assignments on the DE series board to your project The procedure for making pin assignments is described in the tutorial Quartus IT Introduction Using VHDL De signs Note that an easy way of making the pin assignments when we use the same pin names as in the DE series User Manual is to import the assignments from file On a DE2 70 board you may also need to change operating moWe of the nCEO pin to regular I O This can be done by going to Assignments gt Device gt Device and Pin Options amp Dual Purpose Pins and double clicking on the Value field of the nCEO pin and Je kan via Assignments gt Import Assignments een csv importeren am jde benodigde file kun je vinden op http od eduweb hhs nl es practO htm Let op daarna moet je de nCEO pin nog goedzetten zoals hierboven staat uitgelegd Altera Corporation University Prog May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS changing it to Use as regular I O De bovenstaande code is niet correct Zie http od eduweb hhs nl es pract0 htm voor de juiste code Having made the necessary settings Nios II system such as some signals being ignored You may see some warning messages associated with the Yinused or having wrong bit lengths of vectors these warnings can be Kies Processing gt Start Compilation 20 Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS 4
31. nly necessary to have the Data register The addresses assigned by the SOPC Builder are 0x00003000 for the Data register in the PIO called Switches and 0x00003010 for the Data register in the PIO called LEDs as indicated in Figure 14 5 1 Using a Nios Il Assembly Language Program Figure 20 gives a Nios II assembly language program that implements our trivial task The program loads the addresses of the Data registers in the two PIOs into processor registers r2 and r3 It then has an infinite loop that merely transfers the data from the input PIO Switches to the output PIO LEDs The program includes the assembler directive include nios_macros s which informs the Assembler to use the Nios II macros that specify how the movia pseudoinstructions can be assembled include nios_macros s equ Switches 0x00003000 equ LEDs 0x00003010 global _start _start movia r2 Switches movia r3 LEDs loop ldbio r4 0 r2 stbio r4 0 r3 br loop Figure 20 Assembly language code to control the lights The directive global _start indicates to the Assembler that the label _start is accessible outside the assembled object file This label is the default label we use to indicate to the Linker program the beginning of the application program For a detailed explanation of the Nios II assembly language instructions see the tutorial Introduction to the Altera Nios II Soft Processor 22 Altera Corporation University Program May 2011 INTRODUCT
32. put vector is called out_port_from_the_LEDs The clock and reset signals are called clk_O and reset_n respectively Note that the reset signal is added automatically by the SOPC Builder it is called reset_n because it is active low Gentity nios system is 1864 E port 1885 1 global signals 1886 signal clk 0 IN S5TD_LOGIC 1887 signal reset_n IN STD_LOGIC 1888 1889 the_LEDs 1890 signal out_port_from the_LEDs OUT STD_LOGIC_VECTOR 7 DOWNTO 0 1891 1892 the_Switches 1893 Signal in_port_to_the Switches IN STD_LOGIC_VECTOR 7 DOWNTO 0 1894 Me 1895 end entity nios_system 1896 Figure 17 A part of the generated VHDL module Dit is een beetje vaag en ook niet helemaal juist Volg de instructies op http bd eduweb hhs nl es pract0 htm Figure 18 shows a top level VHDL module that instantiates the Nios II system This entity is named lights be cause this is the fame we specified in Figure 3 for the top level design entity in our Quartus II project Note that the input and output ports of the entity use the pin names for the 50 MHz clock CLOCK_50 pushbutton switches KEY toggle switches SW and green LEDs LEDG that are specified in the DE series User Manual On a DEO Nang board you have to change the code slightly to use four dip switches SW3 0 and four LEDs LED3 0 Add this file and all the vhd files produced by the SOPC Builder to your Quartus II project Also add the necessary pi
33. rt to be 8 bits and choose the direction of the port to be Input as shown in the figure On a DEO Nano board specify the width of the port to be 4 bits e Click Finish to return to the System Contents tab as given in Figure 11 Altera Corporation University Program 11 May 2011 12 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS PIO Parallel 1 0 pio_O Se PIO Parallel 1 0 Megatore ltera_avalon_pio clock Becik reset Bereset avalon B s1 conduit B external_connection Basic Settings Width 1 32 bits Direction Output Register Enable individual bit setting clearing Edge capture register C Synchronously capture Edge Type RISING Enable bit clearing for edge capture register Interrupt C Generate IRQ IRQ Type LEVEL Level Interrupt CPU when any unmasked I O pin is logic true Edge Interrupt CPU when any unmasked bit in the edge capture register is logic true Available when synchronous capture is enabled gt Test bench wiring FJ Hardwire PIO inputs in test bench Drive inputs to e Info pio_0 PIO inputs are not hardwired in test bench Undefined values lt m gt Figure 10 Define a parallel input interface Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Altera SOPC Builder DoR Fie Edit Module System Yiew Tools MNioslil Help
34. s System Generation Component Library Target Clock Settings 4 x Device Family Cyclone Il v Name Source clk_0 External ject al H New component rary Avalon Verification Suite Bridges and Adapters Debug Components Digital Signal Processing E cpu_0 Nios II Processor interface Protocols instruction_master Avalon Memory Mapped Master Legacy Components data_master Avalon Memory Mapped Master Memories and Memory Controllers y jtag_debug_module Avalon Memory Mapped Slave 0x00000800 Ox000OOfff External Memory Interfaces Ll amp onchip_memory2_0 On Chip Memory RAM or ROM On Chip Avalon Memory Mapped Slave w 0x00002000 Ox000OZfff Avalon ST Dual Clock Avalon ST Multi Chan Avalon ST Round Rot Avalon ST Single Cloc On Chip FIFO Memory On Chip Memory RAI Name Description To Do epu_0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue To Do epu_0 No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Info onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex d Pre Next gt Generate Figure 9 The on chip memory included on a DE series board 7 Specify the input parallel I O interface as follows e Select Peripherals gt Microcontroller Peripherals gt PIO Parallel I O and click Add to reach the PIO Configuration Wizard in Figure 10 e Specify the width of the po
35. tor cannot be set until memory devices are connected to the Nios Il processor Figure 6 Create a Nios II processor e Choose Nios II e which is the simplest version of the processor Click Finish to return to the window in Figure 5 which now shows the Nios II processor specified as indicated in Figure 7 There may be some warnings or error messages displayed in the SOPC Builder Messages window at the bottom of the screen because some parameters have not yet been specified Ignore these messages as we will provide the necessary data later Altera Corporation University Program May 2011 INTRODUCTION TO THE ALTERA SOPC BUILDER USING VHDL DESIGNS Altera SOPC Builder File Edit Module System View Tools Nosi Help System Contents System Generation Component Library Target Clock Settings S x Device Family v Name Project clk_0 HY New component Library Avalon Veritication Sute Bridges and Adapters di Debug Components Use Conn Name Description Digital Signal Processing 5 cpu_o Nios II Processor interface Protocols instruction_master Avalon Memory Mapped Master Legacy Components date_master Avalon Memory Mapped Master IRQ 0 IRQ 314x 4 Memories and Memory Controllers jtag_debug_module Avalon Memory Mapped Slave Ox00000800 Ox00000fft Merlin Components Peripherals PLL Processor Additions Processors SmaNios li Processor SLS Video and Image Processing lt gt
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