Errata Sheet
Contents
1. 1 Label_C JMPR cc_xx Label_A End of Loop instruction must be JMPR single word instruction jump must be taken in loop iteration n and n 1 PEC transfer must occur in loop iteration n Example2 Label_A instruction x Begin of Loop1 instruction x 1 Label_C JMPR cc_xx Label_A End of Loop1 Begin of Loop2 instruction must be JMPR single word instruction jump not taken in loop iteration n 1 i e Loop2 is entered jump must be taken in loop iteration n and n 1 PEC transfer must occur in loop iteration n Label_B JMP Label_C End of Loop2 JMP may be any of the following jump instructions JMPR cc_zz JMPA cc_zz JB JNB JBC JNBS jump taken in loop iteration n 1 A code sequence with the basic structure of Example1 was generated e g by a compiler for comparison of double words long variables Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 3 of 8 Workarounds 1 use aJMPA instruction instead of a JMPR instruction when this instruction can be the direct target of a preceding JMPR JMPA JB JNB JBC JNBS instruction or 2 insert another instruction e g NOP as branch target when a JMPR instruction would be the direct target of a preceding JMPR JMPA JB JNB JBC JNBS instruction or 3 change the loop structure such that instead of jumping from Label_B to Label_C and then to Label_A the jump from Label_B directly goes to Label_A Notes on compilers In the Hightec compiler b2. ignored and no further instructions are fetched from external memory i e the CPU is in a quasi idle state This problem will only occur in the following situations a the instructions following the PWRDN instruction are located in external memory and a multiplexed bus configuration with memory tristate waitstate bit MTTCx 0 is used or b the instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral CAN and the instructions following the PWRDN instruction are located in external memory In this case the problem will occur for any bus configuration Note the on chip peripherals are still working correctly in particular the Watchdog Timer will reset the device upon an overflow Interrupts and PEC transfers however can not be processed In case NMI is asserted low while the device is in this quasi idle state power down mode is entered Workaround Ensure that no instruction which writes to external memory or an XPeripheral preceeds the PWRDN instruction otherwise insert e g a NOP instruction in front of PWRDN When a muliplexed bus with memory tristate waitstate is used the PWRDN instruction should be executed out of internal RAM Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 2 of 8 BUS 18 PEC Transfers after JMPR instruction Problems may occur when a PEC transfer immediately follows a taken JMPR instruction when the following sequence of 4 conditions is met label
3. SIEMENS Microcontroller Components Errata Sheet January 11 1999 Release 1 0 Device C164CI 8R Stepping Code Marking EES AB C MQFP 80 ES AB AB Package MQFP 80 This Errata Sheet describes the deviations from the current user documentation The classification and numbering system is module oriented in a continual ascending sequence over several derivatives as well already solved deviations are included So gaps inside this enumeration could occur The current documentation is Data Sheet C164Cl Data Sheet 02 98 until separate or updated Data Sheet is available User s Manual C164Cl User s Manual V1 1 1998 08 Target Specification C164xy 8R V1 0 1998 07 until updated User s Manual is available Instruction Set Manual 12 97 Version 1 2 Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 1 of 8 Functional Problems PWRDN 1 Execution of PWRDN Instruction while pin NMI high When instruction PWRDN is executed while pin NMI is at a high level power down mode should not be entered and the PWRDN instruction should be ignored However under the conditions described below the PWRDN instruction may not be
4. eginning with version Gcc 2 7 2 1 for SAB C16x V3 1 Rel 1 1 patchlevel 5 a switch m bus18 is implemented as workaround for this problem In addition optimization has to be set at least to level 1 with u1 The Keil C compiler and run time libraries do not generate or use instruction sequences where a JMPR instruction can be the target of another jump instruction i e the conditions for this problem do not occur In the TASKING C166 Software Development Tools the code sequence related to problem BUS 18 can be generated in Assembly The problem can also be reproduced in C language by using a particular sequence of GOTOs With V6 0r3 TASKING tested all the Libraries C startup code and the extensive set of internal test suite sources and the BUS 18 related code sequence appeared to be NOT GENERATED To prevent introduction of this erroneous code sequence the TASKING Assembler V6 0r3 has been extended with the CHECKBUS18 control which generates a WARNING in the case the described code sequence appears When called from within EDE the Assembler control CHECKBUS18 is automatically activated Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 4o0f 8 ADC 11 Modifications of ADM field while bit ADST 0 The A D converter may unintentionally start one auto scan single conversion sequence when the following sequence of conditions is true 1 the A D converter has finished a fixed channel single conversio
5. ep ES AA Functional Problems AC DC Deviations Functional Short Description Fixed in Problem PWRDN 1_ Execution of PWRDN Instruction while pin NMI high BUS 18 PEC transfers after JMPR ADC 11 Modifications of ADM field while bit ADST 0 X9 Read Access to XPERSs in Visible Mode RTC 4 Undefined Results after write to 114 POWER 7 _ Wake Up from Sleep while RTC switched off JU UE AC DC Short Description Fixed in Deviation DC VDD 2_ Device Supply Voltage V min 4 4 V for CAN Module only DC HYS 1_ Input Hysteresis Special Threshold 300 mV DC VILS 1__ Input low voltage Special Threshold 1 7 V DC IPDR 2 Power down mode supply current with RTC running 200 25 xX fascia HA Application Support Group Munich Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 80f 8
6. n contents of T14REL Workaround Load T14REL 1 and T14 2 with the desired value POWER 7 Wake Up from Sleep while RTC switched off After wake up from Sleep Mode the CPU is immediately started unless waiting for correct clock function During the first phase of the oscillator startup time the input clock can be disturbed and in worst case f exceeds the specified value resulting in CPU malfunctions Workaround Leave RTC on while in Sleep Mode SYSCON1 1 0 01b Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 6 of 8 Deviations from Electrical and Timing Specification The following table lists the deviations of the DC AC characteristics from the specification in the C164Cl Data Sheet 02 98 e DC VDD 2 Von 4 4 5 5 V instead of 4 25 5 5 V for CAN module only Problem Parameter Limit Values Unit Test short name min max DC HYS 1 Input Hysteresis Special 300 400 DC VILS 1 Input low voltage Special 0 5 1 7 2 0 DC IPDR 2 Power down mode supply l or 200 25 xX fose IMA V 5 5V current with RTC running instead of fosc in MHz 100 25 x fose 1 For V gt 4 4V and fpu lt 16 MHz the specified value is guaranteed by design 2 For fyy lt 8 MHz the specified V value for CAN module is guaranteed by design cPU Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 7 of 8 History List since device st
7. n of an analog channel n gt 0 i e contents of ADCON ADCH n during this conversion 2 the A D converter is idle i e ADBSY 0 3 then the conversion mode in the ADC Mode Selection field ADM is changed to Auto Scan Single ADM 10b or Continuous ADM 11b mode without setting bit ADST 1 with the same instruction Under these conditions the A D converter will unintentionally start one auto scan single conversion sequence beginning with channel n 1 down to channel number 0 When no interrupt or PEC is servicing the A D Conversion Complete Interrupt interrupt request flag ADCIR will be set and for n gt 1 also the A D Overrun Error interrupt request flag will be set unless the wait for ADDAT read mode had been selected When ADCON ADWR 1 wait for ADDAT read the converter will wait after 2 conversions until ADDAT is read In case the channel number ADCH has been changed before or with the same instruction which selected the auto scan mode this channel number has no effect on the unintended auto scan sequence i e it is not used in this auto scan sequence Note When a conversion is already in progress and then the configuration in register ADCON is changed the new conversion mode in ADM is evaluated after the current conversion the new channel number in ADCH and new status of bit ADST are evaluated after the current conversion when a conversion in fixed channel conversion mode is in progress and after the curre
8. nt conversion sequence i e after conversion of channel 0 when a conversion in an auto scan mode is in progress In this case it is a specified operational behaviour that channels n 1 0 are converted when ADM is changed to an auto scan mode while a fixed channel conversion of channel n is in progress see e g C164Cl User s Manual V1 0 p 18 4 Workaround When an auto scan conversion is to be performed always start the A D converter with the same instruction which sets the configuration in register ADCON Semiconductor Group Errata Sheet C164CI 8R EES ES AB AB 1 0 Es 50f 8 X9 Read Access to XPERs in Visible Mode The data of a read access to an XBUS Peripheral CAN in Visible Mode SYSCON 1 1 is not driven to the external bus PORTO is tristated during such read accesses Note that in Visible Mode PORT1 will drive the address for an access to an XBUS Peripheral even when only a multiplexed external bus is enabled Note on Interrupt Register behaviour of the CAN module Due to the internal state machine of the CAN module a specific delay has to be considered between resetting INTPND and reading the updated value of INTID See Application Note AP2924 Interrupt Register behaviour of the CAN module in Siemens 16 bit Microcontrollers on http www siemens de semiconductor products ics 34 pdf ap292401 pdf RTC 4 Undefined Results after write to T14 A write operation to T14 leads to undefined results depending o
9. s refer to following examples 1 in an instruction sequence which represents a loop a jump instruction Label_B which is capable of loading the jump cache JMPR JMPA JB JNB JBC JNBS is taken 2 the target of this jump instruction directly is a JMPR instruction Label_C which is also taken and whose target is at address A Label_A 3 a PEC transfer occurs immediately after this JMPR instruction Label_C 4 inthe following program flow the JMPR instruction Label_C is taken a second time and no other JMPR JMPA JB JNB JBC JNBS or instruction which has branched to a different code segment JMPS CALLS or interrupt has been processed in the meantime i e the condition for a jump cache hit for the JMPR instruction Label_C is true In this case when the JMPR instruction Label_C is taken for the second time as described in condition 4 above and the 2 words stored in the jump cache word address A and A 2 have been processed the word at address A 2 is erroneously fetched and executed instead of the word at address A 4 Note the problem does not occur when the jump instruction Label_C is a JMPA instruction the program sequence is executed from internal Flash Example Label_A instruction x Begin of Loop instruction x 1 Label_B JMP Label_C JMP may be any of the following jump instructions JMPR cc_zz JMPA cc_zz JB JNB JBC JNBS jump must be taken in loop iteration n jump must not be taken in loop iteration n
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