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1. d dd I Mix dg A UEM UI LM LLL C LI UE EE i d E IU LE e Author Benjamin Grydehoej Create the 4th February 2006 Last update the 14th April 2006 File prom rom lt et Hardware xilinx Spartans xc3s20 chain Notepad Microsoft version 5 1 compiler PCCOMP alpha 1 7 3 by Francesco Poderico Version 1 0 4 P Test program for PicoBlaze BGEPBl Microcontroller The program test the serial port with receive and transmit Tr P CPC TC A A A A A TCI TIERE TCI A A A A TC PCIE RC TRI ea A A AAA AA IC RC TC NTC a ibxspartans h Include PicoBlaze compiler PCCOMP functions BGEPBIl Hh f f Include BGEPSl controller options SFR Add new variables for test program unsigned char serial value unsigned char Interrupt status unsigned char buffer status void maintvaid ff Set haud rate to 1152 Hz outchar THES x O set High byte for timer baud rate outchar TLES 0x16 set Low byte for timer baud rate autchar IEMO 0x80 set Enable All Interrupt outchartIENl OxOlj z activate serial Interrupt wh lee serial value inchar SBUF Read value from serial buffer if itserial value 0x737 f If serial value equal to s startj outchar sBUF H 3 f f Print HEY to the serial port outchartsBUF E 1 oautchartsBUF Yx 3 Interrupt status inchart IscQ f Read Interrupt flag buffer status inchar scan r Read Buffer Status nurchar P4 Interrupt_status ff write Interrupt Flag to
2. Chapter 3 Implementation of serial UART 3 1 Introduction This chapter describes the option for the serial UART transmitter and Receiver Macros development by the company Ken Chapman Xilinx Ltd The macros package is created to run on following FPGA S Virtex Virtex E Virtex Il Spartan ll and Spartan 3 The macros provide the functionality of a simple UART transmitter and simple UART received each with the fixed characteristics of 1 start bit 8 data bits serially transmitted and received least significant bit first No Parity and 1 stop bit P This option makes it possible to communicate with a PC using a standard configuration the only thing needed setup for running the communication successfully is the Baud Rate timing which has been made adjustable in the SFR Register for the BGEPB1 microcontroller option Specification The standard baud rate the UART runs with is from 9600 and can support up to 115200 The serial UART operates after the standard with asynchronous receiver and transmitter that means the transmitter and receiver is not synchronised The Serial UART contains an embedded 16 byte FIFO First In First Out buffer which just looks at the total size of data received or transmitted The serial UART block diagrams for RX and TX is show in figure 3 1 UART TX UART RX Serial 18 Slices 22 Slices Figure 3 1 Serial UART block diagrams The data is transmitted serially LSB first and given a bit rate from
3. Chapter 2 Implementation of PicoBlaze TM with I O ports interface Napier University Edinburgh 2 8 Test and result The practical test is done with a logic analyzer as in this example it is connected to port 4 and 5 Port 4 is the values send in from port 3 in this case the slide switch on the development board is set to HEX 55 and port 5 is run as a counter counting up Figure 2 11 shows the screenshot from the data analyzer program which has been used to check the output from the FPGA measurement on the development board The port connection of the FPGA is shown in appendix C page 56 i3 Antl6 16 bit Logic Analyzer File Analyzer View Help HS Aa SPN 2 BH 1 Module Sample Clock Speed Trigger Position 50 Trigger Type RL2UBRD1 1MHz lus ES C Patten Edge Module Select This selection box shows all the modules detected on the PC Itis updated every 10 seconds If there is more than one module you can selectthe module to use 1 024 350 89b 832 768 704 640 Cae ae E png ue EL 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 CO 1 011ms C1 346us Difference 665us 1 50376 KHz Waveforms Advanced Triggering RL2UBRD1 is an Antl amp Module done Pins 15 BEBE RES EI EL O a Threshold e Advanced 1 5 B 576 512 448 384 320 ea eae Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 209 Chapter 5 Implementation of serial UART Napier University Edinburgh
4. Serial Buffer 0x09 Timer Baud rate serial low byte SFR TLBS HEX 09 0x0A Timer Baud rate serial high byte SFR TLBS HEX 10 0x0B Serial Channel Control Register SFR SCON HEX 0B 0x0C INTERRUPT ENABLES SFR IENO HEX 0C 0x0D INTERRUPT ENABLES SFR IEN1 HEX 0C OXx0E INTERRUPT SERVICE CONTROL SFR ISCO0 HEX 0E 0x0F TIMER SERVICE CONTROL SFR TCON HEX OF 0x10 Timer Count 0 TC0 HEX 10 0x11 Timer Count 1 Low byte TCL1 HEX 11 0x12 Timer Count 1 High byte TCH1 HEX 12 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 55 Appendix C Pin Option for FPGA and Development board Napier University Edinburgh Pin Option for FPGA and Development board O Name VO Direction PIN Bank Connector SRAM tx Output R13 BANKA TXDOT mo npt T3 BANKA RD 0 reset Input L14 BANK3 BTN3 UserReset PORT 5 7 InOut A10 BANK1 A2ExpansionConnector 28 PORT 5 6 InQut B10 BANK1 A2ExpansionConnector 27 PORT 5 5 InOut A9 BANK A2ExpansionConnector 26 PORT 5 4 Imout A8 BANKO A2ExpansinConnector 25 PORT_5 lt 3 gt InOut B8 BANKO A2 Expansion Connector 24 PORT_5 lt 2 gt InOut A7 BANKO A2 Expansion Connector 23 PORT_5 lt 1 gt InOut B7 BANKO A2 Expansion Connector 22 PORT_5 lt 0 gt InOut B6 BANKO A2 Expansion Connector 21
5. up b had Lar DJ LG elsif WE io i io X OF then Write to TCON register TRO timer lt Data in 10 0 Start timer 0 with set a l TRl timer lt Data in io 2 Start timer 1 with set a l elsif RE io l and ID io X F then lead status flag and which timer a Y Z2 gt gt Ale re ale OT Data out io lt 0000 TF1 timer amp TR1 timer TFO timer amp TRO timer Timer Count 0 ni elsif WE io and ID ic X l0 then Reload new value to timer 0 TCO timer lt lata 1i LO Timer Count 1 TCL HEX ll and TCH HEX elsif WE io I and ID o X 11 then Reload new value to Timer 2 TC1 timer 7 DOWNTO 0 lt Data in io Set the low byte elsif WE io l and ID io X 12 then TC timer 15 DOWNTO 8 lt Data in io Lid i L LO Pa Pa Bo B3 R3 RM PI Pa Lal GJ GJ Lu La La Timer Interrupt Service Routine elsif ETO ints l and TFU_timer 1 and ITO int 0 and EA ant 1 then IT int lt 1 Set Timer 0 Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze elsif T1 int l and TF1 timer l and ITl int 0 and EA int l1 then ETL int e OT 3 Set Timer 1 Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze Figure 4 1 VHDL code for Timer control ey Ln um O io 00 Led Lad Mad La kad Lal E The VHDL code in figure 4 2 shows the code for the counter used for timer 0 The code for timer 1 is exactly the same
6. 16 Byte Wide Registers O PF Enable ATE SABUN s4 s5 s6 s7 IN PORT gt Operand 2 Figure 2 1 PicoBlaze embedded microcontroller Block Diagram Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 13 Chapter 2 Implementation of PicoBlazeTM with I O ports interface Napier University Edinburgh 2 3 Implementation of core and Parallel I O with interrupts The block diagram in figure 2 2 show the PicoBlaze connected with instruction ROM and the I O interface for read and writes 8 bits values HEX 00 FF to the ports PO P1 P3 P4 and P5 and write 16 bits addressed HEX 0000 FFFF out to port 2 compared with the purple I O ports block and blue address decoder block at the BGEPB1 emulation 8051 peripherals block respectively in the diagram in figure 1 1 page 8 The system is created with three external interrupt pins at port 1 to receive external interrupts from hardware example a keyboard switch or some other hardware inputs The PicoBlaze processor core communicate to the Input Output Ports block I O block via OUT PORT which is an 8 bit data transmit out of the microcontroller in an internal pipeline to the I O block To receive data the internal pipeline IN PORT is used which receive 8 bit data value from the I O block The PORT ID is the port identity to chose the right channel for read or write via the internal pipeline it is possible to control up to 256 I O ports Instruction ROM
7. 95 Frame Length position 1 lt 95 position downto 95 Frame Length position Frame 1 lt 1 Set the recessive bit position position 1 Add one to position END IF END IF END LOOP ELSE Frame lt Frame 93 DOWNTO 0 amp 1 END IF END IF END PROCESS dout lt Frame 94 Send data out on the CAN TX port end CAN TX Figures 6 8 VHDL code for transmit data via Data Link Layer Benjamin Grydehoej 04007714 BEng Honours Electronic and Computer Engineering 41 Chapter 6 Design of CAN BUS Interface Napier University Edinburgh 6 4 Simulation This simulation in figure 6 9 shows the data output from the CAN transmission VHDL code there will be send out to the CAN hardware interface from the FPGA Figure 6 9 Simulation of CAN TX in ModelSim 6 5 Test and result The CAN transmission is tested by sending the data packet as described in chapter 6 3 the data packet is received with a CAN USB unit from www canusb com The CAN unit is connected to the computer via USB and as a node at the network For measurement the right data packet in the development process is connected an Oscilloscope from the company Tektronix type TDS 220 there are a digital real time stores oscilloscope There is measurement differential on the CAN bus signal between the CAN L pin2 and the CAN H pin 7 at the SUB D connector The ground probe from the oscilloscope is connected to pin 2 the signal is inverted c
8. Channel Control Register SCON 239 Data out io 000 amp BDP uart amp RBH uart amp RBF uart amp TBH uart amp TBF uart 240 241 Serial Interrupt handling 242 elsif ESO int l and ISO int 0 and rx data present 1l and EA int 1 then 243 ISO int lt 1 Set Serial Interrupt FLAG 244 245 M 246 INTERRUPT SYSTEM 247 This program handle the Interrupt System there use the three register 248 named IENO Interrupt Enable 0 IEN1 Interrupt Enable 2 and ISCO 249 Interrupt Service Control Activate with help of the SFR the IENO 250 and IEN1 enables the interrupt and the ISCO show the status for the 251 interrupts 252 rr H M M me wr ea ae oe an an nr ee 253 INTERRUPT ENABLES SFR IENO HEX OC 254 rro 255 EA WDT ET2 ET1 ETO EX2 EX1 EXO 256 at an een e e e e e e 257 elsif WE io 1 and ID io X OC then 258 EA int lt Data in io 7 Activate or deactivate all Interrupts EA 259 WDT int lt Data in io 6 Activate or deactivate WDT 260 ET2 int lt Data in io 5 Activate or deactivate Interrupts Timer 2 261 ET1 int lt Data in io 4 Activate or deactivate Interrupts Timer 1 262 ETO int lt Data in io 3 Activate or deactivate Interrupts Timer O0 263 EX2 int lt
9. Data in io 2 Activate or deactivate External Interrupt 2 264 EX1 int lt Data in io 1 Activate or deactivate External Interrupt 1 265 EXO0 int lt Data in io 0 Activate or deactivate External Interrupt 0 266 i INTERRUPT ENABLES SFR IEN1 HEX 0D 267 M 268 e x x X X 2 ECO ESO 269 en a M M M M 270 elsif WE io 1 and ID io K 0D then 271 ECO int lt Data in io 1 Activate or deactivate CAN BUS Interrupt 212 ESO int lt Data in io 0 Activate or deactivate Serial Interrupt Page 4 Benjamin Grydehoey 04007714 BEng Honours Electronic and Computer Engineering a Appendix A The VHDL code for VO Interface Napier University Edinburgh 273 274 275 276 211 278 279 280 281 C vhd1 BGEPB1 IO Ports vhd n INTERRUPT SERVICE CONTROL SFR ISCO HEX OE ci Fem 130 ITZ ITA 170 IX 124 TKO elsif WE io 1 and ID io X OE then ICO int lt Data in io 7 Clear Interrupt FLAG for CAN BUS ISO int lt Data in io 6 Clear Interrupt FLAG for Serial IT2 int lt Data in io 5 Clear Interrupt FLAG for Timer 2 ITl int lt Data in io 4 Clear Interrupt FLAG for Timer 1 ITO int lt Data in io 3 Clear Interrupt FLAG for Timer 0 IX2 int lt Data in io 2 Clear Interrupt FLAG for External 2 IXl int lt Data in io 1 Cl
10. IXO_ int em C0 Clear FLAG Extern 0 Interrupt INL ED GNE ED GENS GNE GENES GENE GENS NES NEL A GUN TL E GENE ZEN IEEE US GU GNE GENES GENE UNES E GENE END GENS END ENS GEL NE GER GE GEN GNE NER GENS GENS GENE GUN NUES GENE GENS INED GNU EE GEN ee GEL GERE UNES GNE E GENS GEN AN GG Input amp Output Interface This program function looks at the incoming port address from the PicoBlaze processor core and control via write enable WE io and the read enable RE io for Read or write to the Ports the ID is control from the processor and set the SFR value to the right port Port 0 I O SFR PO HEX 01 DataBus elsif WE io l and ID io X 01 then Port 0 io lt Data in 10 Send data from Microcontroller to Port 0 elsif RE io l and ID io x 01 then Data out io lt Port 0 io Send data from Port 0 to Microcontroller Port 1 I O SFR Pl HEX 02 elsif WE io 1 and ID io X 02 then Port 1l io lt Data in io Send data from Microcontroller to Port 1 elsif RE io l and ID io X 02 then Data out io lt Port l io Send data from Port 1 to Microcontroller Port 2 I O SFR P2 HEX 03 Address Bus Low and HEX 04 Address Bus High elsif WE io 1 and ID io X 03 then Port 2 io 7 DOWNTO 0 lt Data in io 7 DOWNTO 0 Send low byte to Port 2 elsif WE io 1 and ID io X 04 then Port Z io 15 DOWNTO 8 lt Data in io 7 DOWNTO 0 Send high byte to Port 2 Port 3 I O SFR P3 HEX 05 el
11. Implementation of PicoBlaze with I O ports interface 2 tib OCMC LEOTE noi ono A II ee ea etes tt 12 2 2 Background of PicoBlaze M eene tette tnter trennen nennt 12 2 3 Implementation of core and Parallel I O with interrupts ooooooonnccnnnnnnnnonononocccnnnnononanonionocoss 14 2 9 VEDLE code tor the VO Ports Interface is dades 15 Reset LO Standard E 15 Waiteand ead to dO DORIS a A o 16 nte EFUDE US VS Ms 17 2 6 TeSE SOLID are qii MAA A SUR iecpd ue eme 20 2 T STEREO EIOTE S oi ecc o ee et D nuncu red onm MET pM aud 21 PPM Weis EE E 1 OACI OPEP un O A arr EEE 22 Chapter 3 Implementation of serial UART LIO AICA 23 BG CIC OE doe crescit esca O e success ch acehamacee ii dut esi aep both diua eed t ce Ee bored dns 23 3 2 Implementauon or serial ART a tai 24 RCAC a sure tO U DART noct hg Pe d d btt end t tttm iE 25 BAUD Rato TIMIDE iii iii ident oes 26 Seral TALUS Reise a a 2 OPEET EOT o EEE E edi ut E E ob adi cu bct todo MEA ed cu Lepus 28 Sd WE HMM T 28 Chapter 4 Implementation of Timers 2 T I ttodue HO uso t A IE MCE DM MC UEM 29 22 mplementquom OL TETS ii over a tns itu o tuns idt Wels sedan pita Lov rami tul 29 RA E onec a LIUM S ee Md pente 3l Calculation or tmier value oco o ee ue 22 ANGST ERST tias 33 AA Test and POSU e ee oet o meti E NEM Masa MED MEM I MM UA 34 Chapter 5 Implementation of Serial Flash ROM interface SADOU SEM AU MEC inier ba e e e ee e ti utet pte ne id
12. amp CRC del amp ACK slot amp ACK del amp mom J 3 ELSIF Data Length 8 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR amp 00 amp control 4 DATA O amp DATA DATA2 amp DATA3 amp DATA4 amp DATA5 DATA6 amp DATA7 amp CRC amp CRC del amp ACK slot 4 ACK del 4 0 END IF position 0 Insert the recessive and the dominant bit after every five bit and transmit with bit encoding Non Return to Zero FOR i IN O TO 94 LOOP position position l Count the position up IF Frame i l THEN Compare the frame bit with bit counti countl tl Count the value countl up with countO 0 Set the count to zero IF countl gt 5 THEN If Count is 5 the dominant bit countl 0 Set the countl to zero countO 1 lt Set the count to one identically value one one will be set Frame 95 position 1 downto 95 Frame Length position 1 lt 95 position downto 95 Frame Length position Frame i lt 0 Set the dominant bit position positiontl Add one to position END IF ELSIF Frame i s 0 THEN Compare the frame bit with bit value zero count count0 1 Count the value count up with one countl 0 Set the countl to zero IF count gt 5 THEN If Count is 5 the recessive bit will be set count 0 Set the count to zero countl 1 Set the countl to one Frame 95 position 1 downto
13. equal to the set timer value it will activate the Interrupt and the C code program will be enable to response to the interrupt and after end reading the C code program will be enable to clear the interrupt and continue The timer value is set by a timer register and will be reloaded every time there sends a new value to this register 4 2 Implementation of Timers The Timers is implemented in the block named Input Output ports in the block diagram shown in chapter 3 at page 14 in figure 3 2 for communicate with the SFR to set timer value start stop timer and the Interrupt service control register After system reset on the FPGA the timers will default be set to maximum value this will say the 8 bit timer is set to HEX FF or integer 255 and the 16 bit timer is set to HEX FFFF or integer 65535 Both timer will be stop after reset and shall starts via the TCON register Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 29 Chapter 4 Implementation of Timers Napier University Edinburgh The VHDL code in figure 4 1 show the option of the timer service control register made after the same method in chapter 2 for the interrupt control Where the looks on the incoming register value and do option out from that nis program function start stop timer to run and the reading flag function The supports also the reload value for and T G3 La Ld Aj O c ke kal OD c 0 O cou Im CPI um Loa DP dE
14. 0 P5 7 0 Input Output Ports lt P M m ES cd M WE io RE io Reset io P1 0 EXO INTERRUPT P1 1 EX1 INTERRUPT ACK P1 2 EX2 UART TX i Reset buffer Data in 7 0 4 Data to uart 7 0 write buffer Write to uart tx buffer full gt TBF uart tx buffer half full 9 TBH uart UART RX Serial TX Reset buffer Data out 7 0 J3 Data from uart 7 0 gt read buffer lt _ Read from uart Serial Rx buffer data present 9 Rx data present rx buffer full 9 RBF_uart rx buffer half full 9 RBH uart Figure 3 2 Block diagram with TX and RX UART Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 24 Chapter 3 Implementation of serial UART Napier University Edinburgh Read and write to UART The Serial UART communicates via the serial buffer for transmitting and receiving data named Serial Buffer SBUF and this is control by the SFR value HEX 08 F
15. 1Kx18 Block PicoBlaze Core INSTRUCTION 17 0 OUT 17 0 ADDRESS 9 0 ADDRESS 9 0 OUT PORT 7 0 IN PORT 7 0 PORT ID 7 0 WRITE STROBE READ STROBE Input Output Ports INTERRUPT INTERRUPT ACK Data in io 7 0 Data out io 7 0 ID io 7 0 E io E io DataBus PO 7 0 P1 7 0 AddBus P2 15 0 3 7 0 4 7 0 5 7 0 INTERRUPT INTERRUPT ACK Figure 2 2 Block diagram over I O interface 14 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering Chapter 2 Implementation of PicoBlazeTM with I O ports interface Napier University Edinburgh 2 5 VHDL code for the I O Ports interface The VHDL code is program in Xilinx project navigator made from the BGEPB1 Special Function Register SFR shown in the requirement specifications in chapter 1 4 table 1 1 at page 9 The complete code is shown in appendix A page 50 under this text there are a cut out of the reset routines from the I O interface code Reset to standard value This code show the value of the l O ports after reset where all ports will be set to high impedance level or synthesizable tri state buffer The Address bus is set to Hexadecimal 0000 this means the address bus will point on the memory at address 0 the maximum size of addressable memory will be 2 65336 or 64Kbyt
16. Appendix A The VHDL code for VO Interface Napier University Edinburgh The VHDL code for I O Interface C vhd1 BGEPB1 IO Ports vhd 1 rcr ce che cde dee che AA AAA AAA de cec dnce ode cde cie de cde che ce ce oce ie e che oe cde che cde ce ce cde cech diede ke cde ode che code deck cce cde ce oe de oie ce e cde ck cock ode oce oe oe ceo 2 COPYRIGHT BENJAMIN GRYDEHOEJ WWW BG ELEKTRONIK DK 2006 FPGA SPARTAN 3 3 EOS ceo ceo desc ce ceo co ce CAO AAA oc eoe AAA AAA ok NEAR eo deo eo ko ok ko eo ko AAA koc ck ck AAA AAA AAA AAA AAA o 4 Author Benjamin Grydehoe 5 Create the llth November 2005 6 Last update the 11th April 2006 7 File IO PORTS VHD 8 Target Hardware Xilinx Spartan3 XC35200 9 Tool chain Xilinx Project Navicator 6 3 03i 10 Wersion LO 11 12 DESCRIPTION 15 SSS 14 This VHDL code controls the Input Output Ports Serial UART and the SFR 15 register with Interrupt controls and Timer function The Sub functions 16 is described in the code before the program All commandos for 17 communication in this program are control by the Special Function Register 18 there is listed under this text 19 SSSSSsssssesssssssssssesssssssSssssssssssssssssssssse5 20 satel SPECIAL FUNCTION REGISTER 21 22 Symbol Name Address 23 lt PO Port 0 HEX 01 24 is Pl Port 1 HEX 02 25 Ss P2L Port 2 Address Bus low byte HEX 03 26
17. COPYRIGHT BENJAMIN GRYDEHOEJ WWW BG ELEKTRONIK DK 2006 SFR for BGEPBI 8 eee dee de dede dede dee eee dee RRR dee dede dede de dee de dede EERE dede de RRR ERE dee esee de dede dee dee dee desee sededee eee desee dede deese Author Create the Last update the File Target Hardware Tool chain Compiler Version Benjamin Grydehoej 4th February 2006 14th April 2006 BGEPBI h Xilinx Spartan3 XC35200 Notepad Microsoft Version 5 1 PCCOMP alpha 1 7 3 by Francesco Poderico 1 0 A Special Function Register for BGEPB1 9 eR ede dede de dede dee eee dee de dede dee dede RRE dee dededee eee dede de RRR ER ERE esee dee dede esee RE RR ER ER EERE desee dede ee see eee Parallel port ID define PO define P1 define P2L Zdefine P2H define P3 define P4 define P5 Serial Data define SBUF define TLBS Zdefine THBS define SCON Interrupt Service Rutine define IENO define IEN1 define ISCO Timer Service Rutine define TCON define TCO define TCL1 define TCH1 0x01 Port 0 8 bit I O SFR P0 HEX 01 DataBus 0x02 Port 1 8 bit I O SFR P1 HEX 02 Data I O 0x03 Port 2 8 bit O SFR P2L Low byte HEX 03 AddressBus 0x04 Port 2 8 bit O SFR P2H high byte HEX 04 AddressBus 0x05 Port 3 8 bit I O SFR P3 HEX 04 Data I O 0x06 Port 4 8 bit I O SFR P4 HEX 05 Data I O 0x07 Port 5 8 bit I O SFR P5 HEX 06 Data I O 0x08
18. Ci root of the computer Open the Notepad document named prog rom c and edit in the document from the CD if you wish to change something otherwise just save it and minimize the document Right click at the file named RUN bat and create a shortcut to the desktop Right click at the icon and rename it to Compile C to ASM code and afterwards chose Edit to change the location in the second line where it is described where the compiled file shall be copied to copy c pccomp prog_rom psm cAvhdABGEPB1 prog rom psm save and close the document and double click on the icon named Compile C to ASM code The C code will be compiled to ASM code with the PCCOMP compiler and copy to the BGEPB1 library Show in figure 7 2 if there are errors Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 43 Chapter 7 Software Setup Napier University Edinburgh in the code they will be listed numbered line codes it will be shown in the DOS shell along with the syntax problem EX Shortcut to run C XPCCOMP c Spccomp spccomp c 8 prog_rom c Picoblaze Compiler for PicobBlaze Version alpha 1 7 3 No errors CIAPCCOMP gt copY c pccomp prog rom psm c uhdl BGEPBi prog rom psm 1 filets copied IC PCCOMP gt PAUSE Press any key to continue Figure 7 2 PCCOMP C compiler run from DOS shell Open the library named BGEPB1 and make a shortcut to the file named RUN bat and copy this shortcut to the des
19. PORT_4 lt 7 gt InQut A5 BANKO A2 Expansion Connector 20 PORT_4 lt 6 gt InOut B5 BANKO A2 Expansion Connector 19 PORT_4 lt 5 gt InOu A4 BANKO A2 Expansion Connector 148 PORT_4 lt 4 gt InOut B4 BANKO A2 Expansion Connector 17 PORT_4 lt 3 gt InQut A3 BANKO A2 Expansion Connector 146 PORT_4 lt 2 gt InOu D10 BANK1 A2 Expansion Connector 15 PORT_4 lt 1 gt InQut D9 BANK1 A2 Expansion Connector 144 PORT_4 lt 0 gt InOut D8 BANKO A2 Expansion Connector 13 PORT 3 7 InOut K13 BANK3 Slider Switch SW7 PORT_3 lt 6 gt InQut K14 BANKS SliderSwtch SWO PORT 3 5 InOu J13 BANK3 Slider Switch SW5 PORT 3 4 InQut J14 BANKS3 SliderSwth SW4 Le LA be PORT 3 3 BANK2 Slider Switch SW3 MIA PORT_3 lt 2 gt BANK2 Slider Switch SW2 PE PORT_3 lt 1 gt BANK2 Slider Switch SW1 o Le oL Slider Switch SWO MEE PORT 2 15 Output K3 BANK6 A1 Expansion Connector 34 A15 AR Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 56 Appendix C Pin Option for FPGA and Development board Napier University Edinburgh VO Direction L PIN Bank Connector SRAM 73 1 lt 7 gt InOut BANK7 A1 Expansion Connector 19 PORT 1 6 BANK 7 A1 Expansion Connector 17 EE PORT Ow f C2 BANK A1 ExpansionComector 15 _ PORT 1 lt 4
20. a C code test program which is to test the communication between the C code language software and the Hardware description language This is to test the ports for receiving and transmitting data and the interrupt request system The C test program is written in Notepad and named prog rom c The code is compiled by the PicoBlaze C Compiler PCCOMP alpha version 1 7 3 which is running in a DOS shell The Program starts including the Spartan3 h file there is a part of the C compilers advanced function as read and write to I O ports to use this function named OUTCHAR and INCHAR The second file Included is the file named BGEPB1 h and this is the option file for the VHDL interface for the microcontroller Special Function Register for I O ports and interrupts service shown in appendix B page 55 IBi xi File Edit Format View Help Fg CCCII AAA AA OA OA TIC TINTE INN TN TRU TN J CUCOPYRIGHT BENJAMIN GRYDEHOEJ Www BG ELEKTRONIK DK 2006 TEST PROGRAM CC c CCP PCT IRE PIC TIC A O TREE PIC a TIC TIC TIC TIC AA TIC TN TIR TN Author Benjamin Grydehoej Create the 4th February 2006 Last update the 14th April 2006 File prom rom c Target Hardware xilinx Spartans xc3s200 Tool chain Notepad Microsoft version 5 1 compiler PCCOMP alpha 1 7 3 by Francesco Poderico Version 1 0 4 Test program for PicoBlaze BGEPBl Microcontroller The program test the I O ports and the Interrupt register HEEL LC LL LA LLL LL LL LL ED LEE LAE C d includ
21. code the only difference between them is the use other variable names and the variable TCO there is a 8 bit value for timer O and the variable TC1 is a 16 bit value for Timer 1 TimerO control begin if clk event if Timer0 TimerO TFO lt else TimerO TFO lt end if end 1f end process Timer 0 control Figure 4 2 VHDL code for the Timer 0 Counter Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 30 Chapter 4 Implementation of Timers Napier University Edinburgh Timer Register The timer register is built for controlling the Timer O Timer 1 and Timer 2 The timer 2 is not activated in version BGEPB1 but there is reserved space in the register for timer 2 to later version update The register TRO TR1 and TR2 Is for start timer to run with an active one and the TFO TF1 and TF2 is timer flag which will be set when the timer is running out this is equal to the set timer value and uses the flag for activate the interrupt too In figure 4 3 is the Timer Service Control Register TCON shown TCON Figure 4 3 Timer Service Control Register TCON TRO Enable Timer Run 0 to start counting If TRO 1 The Timer 0 will Rune TFO Read FLAG for Timer 0 If TFO 1 The Timer 0 is just count out The FLAG will be set and clear by Hardware TR1 Enable Timer Run 1 to start counting If TR1 1 The Timer 1 will Rune F1 T Read FLAG for Timer 1 If TF1 1 The Timer 1 is just
22. external interrupt 2 is disabled EX2 If ETO 0 the timer 0 interrupt is disabled Enables or disables the timer 1 overflow interrupt If ET1 O the timer 1 interrupt is disabled ET2 Enables or disables the timer 2 overflow interrupt If ET2 0 the timer 2 interrupt is disabled This bit is not used in this version iu If WDT 1 the timer is activate and can not disables with out hardware reset EA Enables or disables all interrupts If EA 0 no interrupt will be acknowledged ul If EA 7 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit Table 2 1 List over Special Function Register IENO IEN1 Figure 2 6 Special Function Register IEN1 Bit Function OOO Enables or disables Serial interrupt O If ESO 0 Serial interrupt O is disabled ECO Enables or disables CAN BUS interrupt O If ECO 0 CAN BUS interrupt O is disabled Table 2 2 List over Special Function Register IEN1 Note The hatch last six bits is reserve for next version Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering ES Chapter 2 Implementation of PicoBlaze TM with VO ports interface Napier University Edinburgh The Interrupt Service Control ISCO HEX OE sets a flag in this register If an interrupt is activate it will be controlled by hardware The flag is read and cleared by software in the Interrupt Service Routine it is cleared bitwis
23. gt InOut BANK5 A1 Expansion Connector 13 PORT 1 lt 3 gt Inout Ts BANKS At Expansion Comedor PORT Is f lnOw f R6 BANKS A1 Expansion Connector PORT 1 lt 1 gt InOut BANK5 A1 Expansion Connector 7 PORT 10 now N7 BANKS A1 Expansion Connectors PORT O 7 mOt D1 BANZ D7 PORT 0 6 InQut Et BANZ 3 D PORT 0 5 InOwt G2 BANK7 Ds PORT_0 lt 4 gt mOwt Ji BANKO D4 PORT 0 323 Ou Kt Banke D3 PORT 0 2 IOu M2 f BANK6e 1 1 D2 PORT_0 lt 1 gt InQu N2 Banke S PORT 0 0 InOut P2 BANK6 DO cok Input T9 BANKA4 50MHz IC4 NEN Top View 1 2 34 5 6 7 8 9 10 11 12 13 14 15 16 PAA T E LJL JL 2 8 pal a Oe Lug t pL 22 F Vash a r FE mE oe brews je TTF u AG Litre tr PA A Beed Bea e t ee B LIF A f AT Y 00 0 diio di t rr Arr etr tr com ER EN EN EN EN EN ADD U Zz Zr ACTA mmoQ 000 DW gt dD U Zz Zr AS IT 0 TMV O WO P 123 4 5 6 7 8 9 10 11 12 13 14 15 16 FPGA Ball Grid Array connections Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering a
24. ne P2H Port 2 Address Bus High byte HEX 04 2 P3 Port 3 HEX 05 2B oes P4 Port 4 HEX 06 29 P5 Port 5 HEX 07 30 ind SBUF Serial channel buffer register HEX 08 31 TLBS Timer Low BAUE Rate Serial HEX 09 32 THBS Timer HIGH BAUE Rate Serial HEX 0A 33 s SCON Serial channel control register HEX 0B 34 IENO Interrupt enable register 0 HEX OC 35 me IENI Interrupt enable register 1 HEX OD 36 ISCO Interrupt service control register HEX OE 37 TCON Timer service control register HEX OF 38 TCO Timer Count 0 HEX 10 39 TCL1 Timer Count Low 1 HEX 11 40 TCH1 Timer Count High 1 HEX 12 YI a i 42 Standard IEEE libraries US 0 i UR t UD p I NI URTEIL E a HQ UII UI BB IH III III II IH I I Itm 44 library IEEE 45 use IEEE STD LOGIC 1164 ALL 46 use IEEE STD LOGIC ARITH ALL 47 use IEEE STD LOGIC UNSIGNED ALL EE S 49 entity in out ports 15 50 Port CLK io in std logic 51 Reset io in std logic 52 WE io in std logic 53 RE io in std logic 54 ID io in std logic vector 7 downto 0 55 Data in io in std logic vector downto 0 56 Data out io out std logic vector 7 downto 0 57 Interrupt io out std logic 58 Interrupt ack io in std logic 59 rx data present in std logic 60 Port 0 io inout std logic vector downto 0 61 Port l io inout std logic vector 7 downto 0 62 Port 2 io out std logic vector 15 downto 0 63 Port 3 io inout std logic vector 7 down
25. page 8 are functions of VHDL code constructed from scats The process for the project will be implementation of the PicoBlaze core with Boot ROM and Serial UART and create and implemented an Input output interface with Interrupt control Two different timers a Timer O using an 8 bit counter and a Timer 1 which uses a 16 bit counter The last unit there will be create and implemented is the CAN bus UART which also will be build from nothing All the functions will be controlled by the Special Function Register showed in table 1 1 at page 9 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 10 Napier University Edinburgh Chapter 1 Introduction 1 6 Time Plan AUOT ESEP Avr dy uorsiaA 24 jeuorssajoig seuojse S U9A3 juauuuBissy uiuaju S9UOJSIN poued joefqns NYO 1eues uoissiuqns jode eut uonejuesalg BJO YSIA SJeulwUeXy EBUuJ9 X3 uonejuasaJg Jejsogd yoday uiJelu jaued 1o9eloJg eulaju Woday JUM n3119 y 159 WEJIBOId 159 e 3ye VOd4 ul uvonejuaua dul ubisep jo uone nuilS TGHA ut ufiseg n319 BuiuuegiBoJg X3 TOHA Buipeay punolbyoeg q Jeeps TII e Te EEE WO ovo WO O 5 D O O NS 9002 S00 JOSS9DOIGOJDIW a dulns jo Vo 2 ETT ES De PTT Y9d4 ue g 2u11 399013 sinouoH Hugg ASYL jo bed Benjamin Grydehoej 04007714 BEng Honours Electronic and Computer Engineering Tl Chapter 2 Implementatio
26. std signal X1 int std signal X2 int std begin process begin wait until CLK io event and CLK io logic logic logic logic logic logic logic logic _logic logic logic logic logic logic _logic logic logic logic XO int lt Port 3 io 0 X1 int lt Port 3 io 1 X2 int lt Port 3 io 2 Cy Read the Port 1 bit 0 value and save it in the Internal signal Read the Port 1 bit 1 value and save it in the Internal signal Read the Port 1 bit 2 value and save it in the Internal signal Page RESET This function set ports level after define the value for variables if Reset io 1 PORTS Port 0 io Port l io Port 2 io 2 then level after reset lt UDRZZALADBACi lt 22222222 lt X 0000 Set Set Set 51 Port O to Port l to Port 2 to high impedance level high impedance level Address 0 Hexadecimal Benjamin Grydehoey 04007714 BEng Honours Electronic and Computer Engineering Appendix A The VHDL code for VO Interface Napier University Edinburgh 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 193 194 195 196 197 198 199 200 201 202 203 204 C NvhdlMBGEPB1MIO Ports vhd GEL NES NER EL GENE Page Port 3 io lt 22222222 Set Port 3 to high impedance level Port 4 io lt ZZZZZZZZ Set
27. this project are the SFR used Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 2 37 Chapter 6 Design of CAN BUS Interface Napier University Edinburgh 6 2 Design of CAN BUS Hardware Interface The Hardware interface is build up on a Printed Circuit Board PCB and made out from the block diagram in figure 6 3 The interface board will be connected to the development board via an IDC header being the standard connector on the development board The Interface board will be supplied with 3 3 volt power from the development board and there will be transmitted and received data via this header The connection out to the world is a male 9 PINs SUB D connector there is mounted with UTP cable FPGA Development board Spartan 3 Starter kit Board Figure 6 3 Block diagram over CAN BUS Interface Interface The design use a MAX3053 for interfaces between the CAN protocol from the FPGA and the physical wires of the bus lines in a CAN The MAX3053 has three different modes of operation high speed slope control and shutdown High speed mode allows data rates up to 2Mbps In slope control mode data rates are between 40kbps and 500kbps so the effects of EMI are reduced and unshielded twisted or parallel cable may be used In shutdown mode the transmitter is switched off and the receiver is switched to a low current mode JP02 JUMPER IPO E E ml P ib 100n I ICO VCC CA
28. 007714 BEng Honours Electronic and Computer Engineering 46 Chapter 7 Software Setup Napier University Edinburgh Cancel the automatic saving of files from the VHDL project the program will automatically ask when it starts up The Boundary Scan has found two devices the XC3S200 FPGA and the XCFO2S Flash mounted on the development Spartan 3 Starter Kit Board If there is used another board the Boundary Scan will via the JTAG connection find these devices there are mount on this development board 3 untitled Configuration Mode iMPACT The search result for the Spartan 3 Starter T su iw SN Kit Board is show in figure 7 11 Boundary Scan Slave Serial SelectMAP Desktop Configuration Right click on the FPGA XC3S200 device in Right click device to select operations the program and chose Assign New Confirmation File Select the embedded bit Her File file in the library named BGEPB1 and done J PROGRESS END End Operation chose open Elapsed time O sec i Device 1 selected Right click on the FPGA device XC35200 Device 1 selected lt gt and chose Program and press OK for For Help press F1 Configuration Mode accepts programming of the device Figure 7 11 iMPACT Boundary Scan Note Make sure the Jumper JP1 is removed on the development Spartan 3 Starter Kit Board for program the FPGA Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 4
29. 200 The second part of the report is regarding the design of a CAN bus hardware interface for the development board and a CAN VHDL interface for transmitting data through the CAN bus level converter out on to the CAN bus The last part of the report is a setup guide for the software used to implemented and design new VHDL function Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering E Acknowledgement thank the following individuals for their contribution of PicoBlaze microcontroller Core and Development tool there are used for this project e Ken Chapman Xilinx Ltd Benchmark House PicoBlaze core and Serial UART e Xilinx Inc ISE Service Pack e Model Technology a Mentor Graphics Corporation ModelSim XE I Starter e Francesco Poderico PCCOMP PicoBlaze C Compiler Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 4 Table of Contents A mou MM M ME 2 BS i acetate O s DIM NIE EDU egt css odd ORE DK e Reate D 3 ATOW CA CCC a esto miei NA m E oos T m DN OB QUA DU DEUS MEL M ENS 4 Tae O CONOIS err en II Roto a orta de up Up aMUt casted 5 Chapter 1 Introduction LADOHETlIG PLOT da 7 1 2 1m OT LB e DEO TEC Eoooes cupa e rte eter esto iati is 7 Pe Project desctiDUO coded eee PIRE SU REY D EVI mdi 8 1 4 Requirement Spec 9 koe FOOL coo AAA ni iuto A aa ened tan ditte tetur d 10 His Le PIA oec ea hen ote neve A pter diuites oae deu T s veut 11 Chapter 2
30. 7 Chapter 8 Conclusion Napier University Edinburgh Chapter 8 Conclusion The project has more or less been successful in reaching the aim of this project The development of the PicoBlaze microprocessor core running in a new version of microcontroller named BGEPB1 created with a simplified Special Function Register whit controlled parallels I O ports serial UART timer and interrupts is complete as seen in the test results The project period compared with the time plan has not really been fulfilling After project week 16 where the development of the CAN bus started and the problem with programming in VHDL started for real a lot of data converting and manipulating of data vector this have given a lot of synthesize problems In the Xilinx Project Navigator This due to the project not just having an Implementation of a microprocessor in a FPGA but also there has been a new VHDL language to learn to be able to make the project Implementation of PicoBlaze Core The status for the Implementation of the PicoBlaze microprocessor in the microcontroller the BGEPB1 is complete in regards to the requirement given The microcontroller is ready to be used and it is easy to implement new function in the VHDL code e g more timers and extra interrupts The only thing which has not been tested and made is a C or ASM code example for the Interrupt control which reads the Interrupt and automatically sends an Interrupt acknowledge after end reading De
31. AX3053 pdf Bibliography Circuit Design with VHDL Volnei A Pedroni ISBN 0 262 16224 5 Microcomputer Components 8 Bit single Chip Family Siemens User s Manual 8 95 PicoBlaze 8 bit Embedded Microcontroller User Guide UG129 v1 1 June 10 2004 Xilinx s homepage http www xilinx com bvdocs userguides ug129 pdf PicoBlaze C compiler User s Manual 1 1 July 2005 Francesco Poderico Francesco Poderico s homepage http www poderico co uk opartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 Xilinx s homepage http www xilinx com bvdocs userguides ug130 pdf Software Xilinx Design tool Project Navigator ISE Service Pack 6 3 03i Windows Xilinx s homepage http www xilinx com xlnx xil sw updates home jsp Simulation program ModelSim XE ll Starter 5 8C Windows Xilinx s homepage http www xilinx com xlnx xil sw updates home jsp PicoBlaze C compiler PCCOMP DOS Francesco Poderico s homepage http www poderico co uk down html PicoBlaze Assembler compiler KCPSM3 DOS Xilinx s homepage http www xilinx com xInx xebiz designResources ip product details jsp sGlobalNavPickzPRODUC TS amp sSecondaryNavPick Design Tools amp key picoblaze S3 V2 Pro PicoBlaze Debugger pBlazIDE Windows Xilinx s homepage Mediatronix s homepage http www mediatronix com pBlazelDE htm Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 49
32. CO Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 18 Chapter 2 Implementation of PicoBlaze TM with I O ports interface Napier University Edinburgh The VHDL code for the Interrupt System and handling of external interrupts is show in figure 2 8 under this text to enable interrupts it is necessary at write to SFR HEX OC named IENO where EA Enable All activates the MSB and the interrupts which are needed example EXO and the value to the register will be HEX 81 to set MSB and LSB When there receives a interrupt on EXO the function in line 318 set a flag in the Interrupt service control register the PicoBlaze read the flag and clear the afterwards 273 274 INTERRUPT SYSTEM 2125 This program handle the Interrupt System there use the three register 276 named IENO Interrupt Enable 0 IEN 1 Interrupt Enable 2 and ISCO eat Interrupt Service Control Activate with help of the SFR the IENO 218 and IEN1 enables the interrupt and the ISCO show the status for the 219 interrupts 280 281 INTERRUPT ENABLES SFR IENO HEX 0C 282 283 m EA WDT ET2 ETi ETO EXZ EX1 EXO 284 A eee 285 elsif WE io 1 and ID io X 0C then 286 EA int lt
33. Data in io 7 Activate or deactivate all Interrupts EA 287 gt WDT int lt Data in io 6 Activate or deactivate WDT 288 ET2 int lt Data in io 5 Activate or deactivate Interrupts Timer 2 289 ET int lt Data in lo 4 Activate or deactivate Interrupts Timer 1 290 ETO int lt Data in lo 3 Activate or deactivate Interrupts Timer 0 291 EX2 int lt Data in io 2 Activate or deactivate External Interrupt 2 292 EX1 int lt Data in io 1 Activate or deactivate External Interrupt 1 293 EXO int lt Data in io 0 Activate or deactivate External Interrupt 0 294 INTERRUPT ENABLES SFR IEN1 HEX 0D 295 296 X X X X X ECO ESO 297 lt 2a SA A LSS a AAI 298 elsif WEeto I and ID lo X D then 299 N ECO int lt Data in 10 1 Activate or deactivate CAN BUS Interrupt 300 BESO int lt Data in io 0 Activate or deactivate Serial Interrupt 301 302 nate INTERRUPT SERVICE CONTROL SFR ISCO HEX OE 303 000 242 304 ICO 150 ITZ ITI ITTO Tee TXL EA 305 iie aids aiio m MER pei bubus Maii Maec A A RON EPA 306 elsif WE io 1 and ID io X 0E then 307 ICO int lt Data in io 7 Clear Interrupt FLAG for CAN BUS 308 IS int lt Data in io 6 Clear Interrupt FLAG for Serial 309 IT2 int lt Data in io 5 Clear Interrupt FLA
34. G for Timer 2 310 ITl int lt Data in io 4 Clear Interrupt FLAG for Timer 1 311 ITO int lt Data in io 3 Clear Interrupt FLAG for Timer 0 312 IX2 int lt Data in lo Z Clear Interrupt FLAG for External 2 313 IXl int lt Data in toll Clear Interrupt FLAG for External 1 314 IX int lt Data in io 0 Clear Interrupt FLAG for External 0 315 elsif RE 10 1 and ID io X OE then 316 Data out io lt ICO int amp ISO int amp IT2 int IT1l int amp ITO int amp IX2 int IX int amp IX int 317 External Interrupt Service Routine 318 elsif EXO int l and IX0 int 0 and X0 int 1 and EA int 1 then 319 IXO int lt 1 Set Interrupt FLAG 320 Interrupt io lt 1 Send Interrupt to PicoBlaze 321 elsif EXl int l and IXl int 0 and Xl int l and EA int 1 then 322 TAl inr lt 1 Set Interrupt FLAG 323 Interrupt io lt 1 Send Interrupt to PicoBlaze 324 elsif EX2 int l and IX2 int 0 and X2 int l and EA int l then 325 IX2 int lt 1 Set Interrupt FLAG 326 Interrupt io lt 1 Send Interrupt to PicoBlaze Figure 2 8 VHDL code for Interrupt System and external interrupts Benjamin Grydehoej 04007714 BEng Honours Electronic and Computer Engineering 19 Chapter 2 Implementation of PicoBlazeTM with I O ports interface Napier University Edinburgh 2 6 Test software in C code This part describes and gives an example on
35. Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 20 Chapter 4 Implementation of Timers Napier University Edinburgh 4 3 Simulation A simulation is made on timer O and timer 1 out from the C program in figure 4 4 The program set timer O with the loaded HEX value 19 which is 500nS and timer 1 is loaded to HEX value 32 being 1uS Afterwards the timers are started and the timer flag and interrupt flag is shown on port 4 and 5 The timer will run until the program is stopped iol xi File Edit Formak View Help T ANE A E E E e T ee S A E E e E EL E E M LU E COPYRIGHT BENJAMIN GRYDEHOEJ Www BG ELEKTRONIK DK 2006 TEST PROGRAM ES RR A A TRITT TC TN Author Benjamin Grydehoej Create the 4th February 2006 Last update the 14th april 2006 File prom raom c et Hardware xilinx spartans 035200 chain Notepad Microsoft version 5 1 Compiler PCCOMP alpha 1 7 3 by Francesco Poderico version 1 0 4 Test program for PicoBlaze BGEPB1 Microcontroller The program test the Timer and Timer 1 PR RR C RC O TIC TI RA A A A AA CCCII TI A Aa aa aaa aA TIC ACC RC CN include lib spartan3 h f f Include PicoBlaze compiler PCCOMP functions include BGEPBl h f Include BGEPS1 controller options SFRJ Add new variables for test program unsigned char Timer Flad unsigned char Interrupt status void mainitvald outchar TC 0x19 s Set count value for Timer Oo 500ns outchartTCLl
36. Honours Project FPGA Implementation of a Simple Microprocessor Napier University Edinburgh rE BGEPB1 MicroController for Spartan 3 PFGA ELEKTRONIK Hardware amp Software Development Title Page NAME Benjamin Grydehoej MATRICULATION NO 04007714 UNIVERSITY Napier University Edinburgh EDUCATION BEng Honours Electronic and Computer Engineering MODULE TITLE BEng Honours Project MODULE NO SE42201 PROJECT TITLE FPGA Implementation of a Simple Microprocessor SUPERVISOR Dr Thomas David Binnie SUBMISSION DATE 5 5 2006 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 2 Abstract This report covers implementation of a simple 8 bit microprocessor in a FPGA the design is made as an emulated standard 8051 microcontroller It is build based on the free PicoBlaze IP Core from Xilinx containing a Special Function Register which is specifically chosen for this microcontroller BGEPB1 is short for BG Electronic PicoBlaze version 1 The microcontroller is implemented with parallels input and output ports I O ports serial UART timers and interrupts The microcontroller interface is programmed in VHDL and the test programs for the microcontroller are made in C code language using the PCCOMP compiler by Francesco Poderico Tested in both ModelSim a simulating tool and in practical on the development board named Spartan 3 starter kit from Xilinx using the FPGA XC35
37. N BUS Interface Napier University Edinburgh Transfer Layer The Transfer layer handles the protocol for transmitting and receiving data via message transfer is manifested and controlled by four different frame types the specification for CAN protocol 2 0A is shown in figure 6 1 and stated in bullets point e Start of frame e The Arbitration field identifier the ID e The Control field consists of four bits Data length Code that identify how many Bytes there are in the data packet e The Data field consists of the data to be transferred e The Cyclic Redundancy Check CRC sequence is calculate from the Start Of Frame SOF field to and with the Data field with the polynomial X15 X14 X10 X8 X7 X4 X3 1 e The ACK field acknowledgment a valid message received correctly e End of frame CAN Protocol Specification 2 0A Control CRC 6 Bits 9 Bits ri rd DLC3 DLC2 DLC1 DLCO Reserved Data Length Code Figure 6 2 CAN protocol Specification 2 0A Object Layer The object layer handles the message filtering and the messages the message filtering checks that the data packets are valid there is a different between this function for either the transmitter or the receivers of the messenger The status handling 5 different error types named Bit Error Stuff Error CRC Error Form Error and Acknowledgment Error Application Layer The application layer handle the communication to the program code read and write to register in
38. NH 5 oe p e CANL 4 iS A 4 SHDN 7 SULAN gt RPO 4 2 8 HEADER RS GND C01 MAX3053 OL 9 Figure 6 4 Interface Circuit Diagram Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 239 Chapter 6 Design of CAN BUS Interface Napier University Edinburgh Peripherals components The circuit in figure 6 4 at page 38 is made out from an application note in the data sheet page 1 for the device named MAX3053 the peripherals components is the C02 there is a ceramic decouple capacitor removing noise from the power supply lines Potentiometer PRO1 and resister RO1 is place to adjust the value from 22KO to 172KQ the reason for making this adjustment is to get the line drivers to switch on and off as quickly as possible optimizing the limit of rise and fall slope of the data signal Example with a speed at 500Kbps the resistor value will be 24KQ shown in the data sheet page 4l The capacitor CO1 is mounted for hold the shutdown input pin high impended and the device will always be turned on to run If the shutdown pin is set to low the device will go in the shutdown mode The last features in the circuit is the jumper JP01 and the impedance resistor R02 at 1200 it the jumper is set the circuit will make an impedance termination for the CAN bus Design The circuit is made on a single side PCB using Surface Mount Devices SMD and designed in Protel Design Explore 99 SE there are a
39. P4 outechardP5 buffer status ff write buffer status to P5 Figure 3 6 Test program for serial UART 3 4 Test and result In practical the HyperTerminal is used as shown in nl xi File Edit View Call Transfer Help figure 3 7 to transmit and receive the test data For oel BI s watching the Interrupt flag and the buffer status the data analyzer is connected to port 4 and port 5 4 The Serial UART is tested with success Connected 0 00 46 Auto detect 1152008N 1 Figure 3 7 HyperTerminal Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering _28 Chapter 4 Implementation of Timers Napier University Edinburgh Chapter 4 Implementation of Timers 4 1 Introduction This chapter describes the two implemented timers in the BGEPB1 the Timer O which is an 8 bit timer and Timer 1 which is a 16 bit timer Both timers work as the count up with the clock frequency the timer interval depend on the clock frequency It is possible to start and stop the timer from the SFR named TCON and read the timer status in the same register with look on timer flag to check the timer is running The interrupt service routine can be active with the register IENO shown in chapter 2 I O ports interface at page 17 with use of the interrupt enable ETO and ET1 The register ISCO from same chapter page 18 uses Interrupt Service Control to clear the Interrupt in the C code program and when the timer is
40. Port 4 to high impedance level Port 5 io lt 22222222 Set Port 5 to high impedance level TIMER TBS uart lt X 0146 Set Baud Rate at 9600 dec 326 HEX 0146 TCO timer lt X FF Set Timer Value to 255 TCl timer lt X FFFF Set Timer Value to 65535 TRO timer lt O Clear Timer 0 Run Timer stop TRl timer lt D Clear Timer 1 Run Timer stop INTERRUPT SYSTEM Interrupt io lt O Set global Interrupt to zero IENO Interrupt Enables 0 EA int lt Clear Enable All Interrupts WDT int lt 0 Clear WDT Interrupt ET2 int lt O Clear Enable Timer 2 Interrupt ET int lt Q Clear Enable Timer 1 Interrupt ETO ant lt O Clear Enable Timer 0 Interrupt EX2 int lt D Clear Enable Extern 2 Interrupt EX1 int lt gts Clear Enable Extern 1 Interrupt EXO int lt O Clear Enable Extern 0 Interrupt IEN1 Interrupt Enables 1 ECO int lt T0 Clear Enable CAN Interrupt ESO int lt Q Clear Enable Serial Interrupt ISCO Interrupt Service Control ICO int lt 0 Clear FLAG CAN BUS Interrupt ISO int ge A Clear FLAG Serial Interrupt ITZ int lt TT Clear FLAG Timer Overflow 2 Interrupt IT int em ET Clear FLAG Timer Overflow 1 Interrupt ITO int lt Q Clear FLAG Timer Overflow 0 Interrupt IX2 int lt 0 Clear FLAG Extern 2 Interrupt IXl int lt TU Clear FLAG Extern 1 Interrupt
41. TFl1 timer amp TR1 timer amp TFO timer amp TRO timer em Timer Count 0 TCO HEX 10 elsif WE io 1 and ID io X 10 then Reload new value to timer 0 TCO timer lt Data in io Timer Count 1 TCL1 HEX 11 and TCH1 HEX 12 elsif WE io 1 and ID io X 11 then Reload new value to Timer 2 TC1 timer 7 DOWNTO 0 lt Data in io Set the low byte elsif WE io l and ID io X 12 then TC1_timer 15 DOWNTO 8 lt Data in io Set the high byte Timer Interrupt Service Routine elsif ETO int 1 and TFO timer 1 and ITO int 0 and EA int 1 then ITO int lt 1 Set Timer 0 Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze elsif ET1_int 1 and TFl timers 1 and IT1_int 0 and EA ints 1 then ITl int lt 1 Set Timer 1 Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze Relase Interrupt elsif Interrupt ack io 1 then When Interrupt ACK is active Interrupt io lt 0 Set global Interrupt to zero end if end process end in out ports Page 5 Benjamin Grydehoey 04007714 BEng Honours Electronic and Computer Engineering 54 Appendix B Special Function Register BGEPB I h Napier University Edinburgh Special Function Register BGEPB1 h EE eee dee dede de dede dee eee dee de dede dee dede dede de dee de dede e eee dede de dede jedesede dee esee RRR dee dee RE de dee sededee esee desee dede eese eee
42. a ELA MM M M MM M PP H 9 PAT EE LEE OE I I aa 419 SBUF Read and write to Comport SFR SBUF HEX 08 216 elsif WE io l and ID io X 08 then Write to Serial Buffer ES write to uart lt WE io Enable write to UART 218 data to uart lt Data in io Send Data to the UART buffer from 219 the SFR register named SBUF 220 elsif RE io 1 and ID io X 08 then Read to Serial Buffer 221 read from uart lt RE io Enable read to UART 222 Data out io data from uart Read Data from the UART buffer to 223 the SFR register named SBUF 224 Timer Baud rate serial low byte SFR TLBS HEX 09 225 elsif WE io l and ID io X 09 then Write the low byte 226 TBS uart 7 DOWNTO 0 lt Data in io Send the low data byte to the Timer 227 Baud rate Serial for BAUD rate timing 228 Timer Baud rate serial high byte SFR THBS HEX OA 229 elsif WE io 1 and ID io X 0A then Write the high byte 230 TBS uart 15 DOWNTO 8 lt Data in io Send the high data byte to the Timer 2 34 Baud rate Serial for BAUD rate timing 232 233 gt Serial Channel Control Register SFR SCON HEX OB 234 A RNR eR eS t tta TR t i Ei ant miam topi a im ti t do 235 Xx J X X BOF RBA REF TRH TBE 236 Sennen e o m 237 elsif RE io 1 and ID io X 0B then Read the status flag from Serial 238
43. amp control amp DATA 0 amp CRC amp CRC del amp ACK slot amp ACK del amp 0 ELSIF Data Length 2 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR 00 amp control amp DATA O amp DATA CRC amp CRC del amp ACK slot amp ACK del 4 O ELSIF Data Length 3 THEN Frame 94 downto 95 Frame Length lt O id amp RTR amp 00 amp control amp DATA amp DATAl amp DATA2 amp CRC amp CRC del amp ACK slot amp ACK del amp 0 ELSIF Data Length 4j THEN Frame 94 downto 95 Frame Length lt O amp id amp RTR amp 00 amp control amp DATA amp DATAl amp DATAZ amp CRC 4 CRC del amp ACK slot amp ACK del amp 0 j ELSIF Data Length 5j THEN Frame 94 downto 95 Frame Length lt O amp id amp RTR amp 00 amp control amp DATA O amp DATA amp DATAZ DATA3 amp DATA4 amp CRC amp CRC del amp ACK slot amp ACK del amp 0 ELSIF Data Length 6 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR amp 00 amp control amp DATA O amp DATA amp DATAZ amp DATA3 DATA4 amp DATA5 amp CRC 4 CRC del amp ACK slot amp ACK del amp 0 Jy ELSIF Data Length 7 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR amp 00 amp control amp DATA O amp DATA amp DATA2 amp DATA3 amp DATA4 amp DATA5 amp DATAG amp CRC
44. count out The FLAG will be set and clear by Hardware TR2 Enable Timer Run 2 to start counting If TR2 1 The Timer 2 will Rune This bit is not used in this version TF2 Read FLAG for Timer 2 If TF2 1 The Timer 2 is just count out The FLAG will be set and clear by Hardware This bit is not used in this version Table 4 1 List over Special Function Register TCON Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering NU Chapter 4 Implementation of Timers Napier University Edinburgh Calculation of timer value The timing depends on the clock frequency and in this case the FPGA runs with 50MHz and the maximum timer value created for the Timer O and Timer 1 is calculate to 5 1uS for Timer 0 and 1 3107mS for Timer1 showed in the equation under this text Timer0 value in Sec EM SN gt E DN 5 1uS Clock frequency ARE Timer0 value in dec 255 l l Timerl value _in_ Sec gt gt 1 3107m5 Clock frequency Epod SCENE Timerl value in dec 65535 This is an example to make a calculation of the timer value there is to be uploaded to the timer out from the expected time at 500uS The value will be 25000 as shown in the equation under this text and therefore it is necessary to use the timer 1 a 16 bit timer for this operation because of the high number Timerl value in dec Clock frequency Timerl_ value in Sec 50 000 000 500 uS 25000 Benjamin
45. e begin process begin F1 Ce UN amp QU Hi wait until t H 4 WO 0 J gt N9 O Ji 0 CO u Oy U1 da WN e NNN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 QN MND ho d 22222222 22222222 X 0000 22222222 22222222 22222222 CJ O q T O IDA Sa 2 4 O 0 D cr RRR UA A A Chote a tri m T O O Yj HU 0 rx Y EXE L e FON in WU N He Figure 2 3 VHDL code for reset data value for I O interface to default Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 15 Chapter 2 Implementation of PicoBlazeTM with I O ports interface Napier University Edinburgh Write and Read to I O ports The I O interface code looks at the Read or Write enable input and the ID input and uses Data in and Data out for transmit and receive data from this unit As an example for transmit data to Port O also called DataBus the programe uses the ID named ID io HEX 01 the Write Enable named WE io and the Data in named Data in io to write to Port 0 When the statement is true the processor will transmit the data value out on port 0 For receive data from Port O it is necessary to send a Read Enable named RE io and the processor can read the value The same in force for Port 1 Port 3 Port 4 and Port 5 but Port 2 is different because this is a 16 bit Address bus for sending data to this port it is necessar
46. e lib spartans h f f Include PicoBlaze C compiler PCCOMP functions include BaEePBl h f f Include BGEPSl controller options SFR Add new variables for test program unsigned char port testl unsigned char port test unsigned char Interrupt_walue void maintvoid poutchar IEND QOxS1 f f set Enable All and external interrupt outechar Isco xOQJ ff Clear the Interrupt service Control Register port testl 0 Set variable port test 1 to zero port test2 O f f set variable port test 2 to zero LE port tsest2 port test 1 Add one to the variable port test 2 port testl inchar P33 f Read HEX value on port 3 slide switch 0 on Board to variable outechari P2L Oxo f Send HEX value OL to the low byte of the AddressBus outchar P2H x 27 Af send HEX value 2 to the high byte of the AddressBus outchartPO port testl f write variable port testl value there are the input from port oO outchar Pl xffJ fo Write HEX value FF to Port 1 pBoutchar P5 part test2zj f f write variable port test value to port 5 Interrupt value inchar IsCU Read the interrupt value from ISCO register and save it in the ff variable interrupt value iFtrnterrupt value xOlj ff If the Interrupt value is equal to HEX OL External interrupt 0 outchar P4 port testl ff write the slide switch value to Port 4 for test Figure 2 9 C code for Test of I O ports and Interrupt System The Interrupt
47. e as the FPGA device which is used on the development board Left click with the mouse on the VHDL project General Options Configuration Options Startup Options Readback Options 2 ProperyName Vale source file in the Sources in project window and FPGA Start Up Clock Enable Internal Done Pipe a Done Output Events en chose in the Processes for Source window the Enable Outputs Output Events Release Write Enable Output Events BEES Generate Programming File and right click here Drive Done Pin High and chose properties in the menu The Process OK A poet Hj lp Properties window will appear and then chose Oox the menu named Startup Option and select the Aa function named FPGA Start Up Clock to JTAG Coon Fira Clock press OK As showed in figure 7 8 Right click on the Configure Device IMPACT and chose properties in the menu Select the Configuration Mode and chose this to Boundary Annuller Default Hj lp Scan Press OK For save the change show in figure 7 9 Fie Edit view Mode Operations Qu Right click on the Generate Programming File i and select Rerun all in the menu Make assured O c Li E Ea di that there are no warnings or errors in the compiled code Doublet click on the Configure Device IMPACT After the new program is open Figure 7 10 iMPACT IMPACT chose the function named Boundary ocan in the menu bar show in figure 7 10 Benjamin Grydehoe 04
48. e clear in worst case and these 6 clock cycles are also necessary to be taken care of in the C or ASM code timer programming 4 4 Test and result The program is tested on hardware by downloading the code to the development board and with help of the data analyzer it is possible to watch the timer flag and the status for the Interrupt Service Routine on port 4 and 5 But the timing is not exactly what is shown in the simulation because it takes a few extra clock cycles to write out on Port 4 and 5 But it gives an idea of how it should work correctly Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 34 Chapter 5 Implementation of Serial Flash ROM interface Napier University Edinburgh Chapter 5 Implementation of Serial Flash ROM interface 5 1 About serial interface The serial Flash PROM interface can be accessed through serial data communication from the FPGA via three data connections Serial Data from Flash Enable Serial Flash from FPGA and Clock signal from the FPGA The Flash PROM can only be used as Program ROM or for fixed data as Ethernet MAC ID ASCII data for display encryption codes etc All types are fixed values which are programmed into the flash via JTAG standard communication using the iMPACT tool from Xilinx Project Navigator which is programmed with the file formats named Object mcs or HEX hex The JATG is a serial bus made for in circuit test and programming us
49. e in the ISCO Special Function Register show in figure 2 7 ISCO ico wo m2 m mo we om vo Figure 2 7 Special Function Register ISCO 1X0 Read FLAG for external Interrupt O If XO 1 external interrupt O is set Clear the FLAG in Interrupt service routine with set bit IXO to O IX1 Read FLAG for external Interrupt 1 If IX1 1 external interrupt 1 is set Clear the FLAG in Interrupt Service Routine with set bit IX1 to O IX2 Read FLAG for external Interrupt 2 If IX2 1 external interrupt 2 is set Clear the FLAG in Interrupt Service Routine with set bit IX2 to O Read FLAG for Timer 0 overflow Interrupt If ITO 1 Timer O overflow Interrupt is set Clear the FLAG in Interrupt Service Routine with set bit ITO to O Read FLAG for Timer 1 overflow Interrupt If IT1 1 Timer 1 overflow Interrupt is set Clear the FLAG in Interrupt Service Routine with set bit IT1 to O Read FLAG for Timer 2 overflow Interrupt If IT2 1 Timer 2 overflow Interrupt is set Clear the FLAG in Interrupt Service Routine with set bit IT2 to O This bit is not used in this version Read FLAG for external Interrupt 2 If IX2 1 external interrupt 2 is set Clear the FLAG in Interrupt Service Routine with set bit IX2 to O ICO Read FLAG for external Interrupt 2 If IX2 1 external interrupt 2 is set Clear the FLAG in Interrupt Service Routine with set bit IX2 to O Table 2 3 List over Special Function Register IS
50. e timer will be HEX 0146 the low byte 0x46 and the high byte 0x01 This value is also the standard settings with reset of the system until there is reloaded a new value to the system via the special function register Calculation of the most common used baud rates with PC communication used on a FPGA with a clock frequency at 50MHz BAUD Rate Result Value in Integer Value in HEX Tolerance 9600 325 52 0146 0 147 19200 162 76 00A3 0 147 38400 81 38 0051 0 469 57600 54 25 0036 0 469 115200 27 12 001B 0 469 Table 3 1 List over standard BAUD Rate used in a FPGA there run with a frequency at 50MHz The HEX value for the baud rate timer is loaded via SFR value HEX 09 for the Low byte and OA for the high byte The value is loaded to the TBS uart variable in the VHDL code show in figure 3 3 from line 224 to line 230 at Page 25 The baud rate timer counter code in VHDL is showed in figure 3 4 at page 27 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering e Chapter 5 Implementation of serial UART Napier University Edinburgh Figure 3 4 VHDL code for Serial UART timer Serial Status Register The serial status register sets flag for the TX RT buffer and for the BDP flag for new receive data in the RX buffer The explanation of the flag function is shoved in table 3 2 SCON x X X 9e ses rer Ten Ter Figure 3 5 Special Function Register SCON Read FLAG Transmiss
51. ear Interrupt FLAG for External 1 IXO int lt Data in io 0 Clear Interrupt FLAG for External 0 elsif RE io 1 and ID io X OE then Data out io lt ICO int amp ISO int amp IT2 int amp IT1 int ITO int IX2 int amp IX 1 int amp IXO int External Interrupt Service Routine elsif EXO int 1 and IXO0 int O and X0 int l and EA int 1 then IXU int lt T Set Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze elsif EX1 int l and IX1 int O0 and X1 int 1 and EA int 1 then IX1 int lt ngt Set Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze elsif EX2 int 1 and IX2 int 0 and X2 int l and EA _int 1 then IX2 int 1 Set Interrupt FLAG Interrupt io lt 1 Send Interrupt to PicoBlaze This program function support the Timer option via the SFR TCON there start stop timer to run and the reading flag function for timer interrupt The supports also the reload value for Timer 0 and Timer 2 TIMER SERVICE CONTROL SFR TCON HEX OF X TZ TR THE TRI TEU TRO elsif WE io 1 and ID io X 0F then Write to TCON register for Start Stop TRO timer Data in io 0 Start timer 0 with set a 1l TR1 timer lt Data in io 2 Start timer 1 with set a 1 elsif RE io 1 and ID io X OF then Read status flag and which timer there are on Data out io lt 0000 amp
52. f how to setup a Test Bench mark and how to use it with ModelSim is explained in this section New Source To add a Test Bench Waveform in Xilinx Project le BMM File EU SE UE Navigator right click in the Sources in Project 9 MEM File File Name Ig Schematic jseeDagan Testibw window and chose New Source Select Test MU Location Bie ee CWiaEGEFET Bench Waveform in the menu to the left show in f VHDL Library V VHDL Module Laeta figure 7 4 and enter a name for the file Click next and chose the VHDL file you would like to test In and Output on in this example the embedded file i Annuller Hj lp Figure 7 4 Add New Test Bench Waveform Select show in figure 7 5 Click next and chose create The Project Navigator will open a window like the one which is shown in figure 7 6 in the bottom of Source File the page And you will be asked about clock embedded in_out_ports prog_rom ere frequency in this case it is set to 20nS and a duty cycle at 50 because this is the speed the Spartan 3 board runs at The blue colour shows output and yellow shows input The reset is set high in the beginning of the simulation and lt Tilbage Annuller Hj lp afterwards it is low Figure 7 5 Chose Source File for Test Bench For start simulation with ModelSim double click on the Simulation Behavioral Model and the program will start and run afterwards simulation f
53. f the CAN BUS is Layered Structure of CAN OSI model compared with the seven OSI model layer a showed in figure 6 1 The OSI layer is compress to four main layers for the CAN because some of the layer overlaps each other the four CAN layer is Physical Layer 4l Transfer Layer Object Layer and Application Layer these layer is describe in the four Signal Level and Bit Representation subjects under this text Figure 6 1 CAN layer amp OSI layer Physical Layer The physical layer is the hardware specifications for the CAN standard and use connector type as standard male 9 PINs SUB D connector and the cable is typical Shielded Twisted Pair STP or Un shielded UTP cables the characteristic for the line impedance is 120 Ohm common mode voltage ranges from 2 Volts on CAN L to 7 Volts on CAN H The balanced differential 2 wire CAN bus can transmitted signal up to 40 meters with a speed of 1Mbps and less at 1km up to 20Kbps The CAN standard bit encoding use the system called Non Return to Zero NRZ The CAN transmits data through a binary model of dominant bits and recessive bits where dominant is logic O and recessive is logic 1 The maximum bits there most been send subsequent is five dominant or recessive if more there will be set an extra bit there is reversed from the other bits Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 36 Chapter 6 Design of CA
54. full functional 30 days trial version of a professional PCB layout tool The layout result is showed in figure 6 5 for the bottom layer to the left the top over layer in the middle and the bottom over layer to the right T U e D U o ha TD n M eo eo ON Benjamin Grydehoej 04007714 BEng Honours Electronic and Computer Engineering 39 Chapter 6 Design of CAN BUS Interface Napier University Edinburgh 6 3 Design of CAN BUS VHDL interface for transmitting The CAN transmitter interface is designed as the VHDL part which has not been implemented in the BGEPB1 core at the moment because there is still missing some development But the corner stones have been built to be able to send data test packets from the VHDL interface The data packet is generated from the protocol the ID address set to HEX 200 and four data byte set to HEX AA FF 00 and 55 The CRC calculation is done manually and gives the HEX value 69 this is all fixt value for the data packet In this VHDL code the serial sequence is automatically generates as shown in figure 6 7 kh Q a gt gt c gt 0 Y S 7 Y Y gt o o E o o o o o o o x x O x T z Res iQ eiu io iE T O o Control Byte 0 Byte 1 Byte 2 Byte 3 CRC ioi cr Qr M T Control ByeO ji Byte iy Byte2 iy Bytes pie CRC HEX 200 HEX 4 HEX AA HEX FF HEX 00 HEX 55 HEX 69 Figure 6 7 Test Data packet for transmission via CAN The data value will be added toget
55. her in a vector chosen as the worst case value of 95 bit according to the CAN specification 2 0A When the data is received in this code example the values are set to fixed values the data would be added together chosen out after the value of bytes as shown in code line 138 to 155 in figure 6 8 at page 41 The unused bit in the vector is set to high and will be sending as high output to the CAN interface The loop from line 160 to 183 in the VHDL code is a loop that inserts the recessive and the dominant bit after every five identically bit The function in line 188 send data serial out to the CAN bus interface named TX CAN at the output on FPGA Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 40 Chapter 6 Design of CAN BUS Interface 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 158 160 161 162 163 164 165 l66 167 166 169 170 Lil 172 173 174 175 176 177 178 179 180 181 182 184 185 186 187 188 189 Napier University Edinburgh Chose the packet format between 0 to 8 byte data transmitting IF Data Length 0 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR amp OO amp control amp CRC amp CRC del amp ACK slot amp ACK del amp 0 ELSIF Data Length 1 THEN Frame 94 downto 95 Frame Length lt 0 amp id amp RTR amp 00
56. ing the four communications lines named Test Clock TCK Test Mode Select TMS Test Data In TDI and Test Data Out TDO connected to a external programming unit at the connector shown in the left side of figure 5 1 DIN XILINX CONFIGURATION XILINX FPGA PROM USERIO TCK TMS TDI Figure 5 1 Serial hardware interface The VHDL code for accessing the PROM information via the FPGA is available from Xilinx s homepage as free code The Serial Flash PROM is not used in this program because there is sufficient PROM for the code in the FPGA e XAPP694 Reading User Data from Configuration PROMs http www xilinx com xIlnx xweb xil publications display jsp sGlobalNavPick2 amp sSecondaryNav Pick amp category 1209899 amp iLanguagelD 1 or from the library Serial Flash on the CD ROM Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 35 Chapter 6 Design of CAN BUS Interface Napier University Edinburgh Chapter 6 Design of CAN BUS Interface 6 1 Introduction The Control Area Network CAN Bus interface is a serial asynchronous transmission scheme that uses a communication protocol which efficiently supports distribution of real time control with a very high level of security The specification is defined with the ISO 11898 OSI Model The CAN 2 0A is an extended message format defined in CAN 1 2 and CAN 2 0B describing both standard and extended message formats The Layer structure o
57. ion Buffer Full there is set by hardware in TX UART If TBF 1 Flag Transmission Buffer Full is set When the 16 byte FIFO buffer is full this output becomes active HIGH The host system should not attempt to write any new data until the serial transmission has been able to create a space Any attempt to write data will mean that the new data is ignored Read FLAG Transmission Buffer Half full there is set by hardware in TX UART If TBH 7 1 Flag Transmission Buffer Half full is set When the 16 byte FIFO buffer holds eight or more bytes of data waiting to be transmitted this output becomes active HIGH This is a useful indication to the host system that the FIFO buffer is approaching a full condition and that it would be wise to reduce the rate at which new data is being written to the macro Read FLAG Receiving Buffer Full there is set by hardware in RX UART If RBF 1 Flag Receiving Buffer Full is set When the 16 byte FIFO buffer is full this output becomes active HIGH The host system should rapidly respond to this condition by reading some data from the buffer so that further serial data is not lost Read FLAG Receiving Buffer Half full there is set by hardware in TX UART If RBH 7 1 Flag Receiving Buffer Half full is set When the 16 byte FIFO buffer holds eight or more bytes of data waiting to be read this output becomes active HIGH This is a useful indication to the host system that the FIFO buffer is approaching a full condi
58. ktop Rename the ICON to Compile ASM to VHDL Format Right click and chose Edit and change the location if it is different Double click on the icon Compile ASM to VHDL Format the program compile the ASM code to machine code in VHDL format with help of the PicoBlaze compiler named KCPSM3 showed in figure 7 3 If there are any errors in the ASM code the errors be list in the DOS shell PASS 7 Writing coefficient file prog rom coe PASS 8 Writing VHDL memory definition file pray rom uhd PASS 9 Writing Verilog memory definition file prag rom u PASS 10 Writing System Generator memory definition file prog_rom m PASS 11 Writing memory definition files prog rom mem KCPSM3 successful IKCPSM3 complete ICAUHDL gt EGEPB1 gt PAUSE F key to continue Figure 7 3 KCPSM3 ASM compiler run from DOS shell Recompile the project in Xilinx project Navigator and the project is ready to be tested in ModelSim Every time the c code is changed it is necessary to Compile C to ASM code afterwards Compile ASM to VHDL Format and recompile the project in Xilinx Project Navigator Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 44 Chapter 7 Software Setup Napier University Edinburgh 7 3 Simulation in ModelSim The easiest and most undemanding way to simulate in ModelSim is by adding a Test Bench Waveform to the project showed in this part The description o
59. l for BAUD rate timing Serial Channel Control Register elsif RE 1o and ID io X 0B he Read the status flag from Serial Channel Control Register SCON Data out io lt 000 amp BDP wart amp RBH uart amp REF uart amp TBH uart amp TBF uart Serial Interrupt handling elsif ESO ints l and ISO int 0 and rx data present 1 and EA int 1 then ISO int lt 1 Set Serial Interrupt FLAG Figure 3 3 VHDL code for Serial interface of UART Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 25 Chapter 5 Implementation of serial UART Napier University Edinburgh BAUD Rate Timing The baud rate timer is a 16 bit timer that is controlled by a low and high byte send to the SFR register via the Timer Low byte Baud rate Serial TLBS and Timer High byte Baud rate Serial THBS The baud rate is calculate out from the clock frequency on the FPGA board in this example the board is running with 50MHz and the baud rate is set to 9600Hz Calculation of value for BAUD Rate Timer Clock _ frequency E 50 000 000 Hz Timer value 7 16 BAUD RATE 16 9600 Hz 325 52 2 326 The nearest integer is 326 this will in excess of the required tolerance equivalent baud rate of 9586Hz which is just 0 15 Anything within 1 is really going to work as it allows for inaccurate clock rates and really poor switching in the serial lines The HEX value for the baud rat
60. m IRAE QUEE O te sede dms A CEU 35 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering _5 Chapter 6 Design of CAN BUS Interface O L InttOdUCUOD nie aM dM pis dl do EUER 36 6 2 Design of CAN BUS Hardware Interact as 38 6 3 Design of CAN BUS VHDL interface for transmitting ooooonnnnnccnnnnnnnnnnnnnnnnnononononannnnnnnnnnnnnnos 40 Od HU ATI OI Sce Les ea TE E dn emet demain inum let aep deua inti edes 42 OA 1 121810 Dee Toute desi UND ien ione eon mnt O o 42 6 5 estando 42 Chapter 7 Software Setup Teal MEME OGUIC OMS ERR di 43 Ta oseupor C and ASM Compiler sad 43 759 EMU EET amado CTS TS TET APA A A PO eiut item ia tened s reat E 45 7 4 Download to FPGA via IMPACT tool sssssssssseeeeee nennen emen eene nnns nini nnns 46 Chapter 03 Conclusion iiti bike emerat ba qula aseo bt ieod 48 Related Materials and References A P c etui edu dace det TERNI EDU IMS eMe d md Vues des ds 49 O A A ee 49 A Met A UM EMEN UE dd 49 Appendix A The VHDL code tot TO teta nieta Rita ert one ba t 50 Appendix B Special Function Reister BGEPE Lh nose bar OD EPI S I un bis heo dba pas eui usse np NR 55 Appendix C Pin Option for FPGA and Development board oocccccncnooonnncnononnnnnononononnnnnnnnnnononccnnnnnnnnnnnnocccnnnnnns 56 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 6 Chapter I Introduction Napier University Edinburgh Chapter 1 Int
61. mulation Peripherals 0 m O b and O Oo c ed a gt 7 4 o i o lt T i o ed P1 7 0 Serial Flash Rom Interface Serial Flash Rom Platform Flash Figure 1 1 Block diagram over BGEPB1 Emulated 8051 Microcontroller Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 8 Chapter I Introduction Napier University Edinburgh 1 4 Requirement specification The specification for the project is described in this paragraph and all the special function calls are made out from the list for Special Function Register SFR showed in table 1 1 The project consists of building an embedded microcontroller in a FPGA with a CAN Bus interface shown in the block diagram at page 8 figure 1 1 The specification of the project is listed in bullets point under this text e PicoBLAzE CORE AND Boot ROM Use the PicoBlaze features showed on page 13 e SERIAL UART RS232 Standard configuration 1 start bit 8 data bit no parity and 1 stop bit e CAN BUS UART Designed to ISO 11898 1 CAN 2 0A amp B support bit rates up to 1Mbit s e TIMER Timer 0 as 8 bit Timer and Timer 1 as 16 bit Timer e SERIAL FLASH ROM INTERFACE Controller interface or extern serial program store up to 2Mbit e SPECIAL FUNCTION REGISTER SFR The SFR control all the call to ports serial UART Timer etc e WATCHDOG TIMER Automatics reset of the microcontroller with problem
62. n of PicoBlazeTM with I O ports interface Napier University Edinburgh Chapter 2 Implementation of PicoBlaze with I O ports interface 2 1 Introduction This chapter descripts the PicoBlaze core and its features for the processor and how to implement the microcontroller core in a Spartan 3 FPGA with parallel Inputs and Outputs and interrupt service controller for external interrupt at I O pins This chapter will cover all the steps from the design of l O ports VHDL code and set the Xilinx project navigator up and make a C language test program for the I O ports to test the system in hardware 2 2 Background of PicoBlaze The PicoBlaze microcontroller is a compact core making it possible to download free version without IP license from Xilinx com after registration of user The microcontroller is an embedded 8 bit RISC core optimized for the Spartan 3 Virtex ll and Virtex ll Pro FPGA families The PicoBlaze microcontroller is optimized for efficiency and low development cost It occupies just 96 FPGA slices or 12 5 of an XC3S50 FPGA and performs a respectable 44 to 100 million instructions per second MIPS For development on the PicoBlaze microcontroller the tool named Xilinx project navigator version 6 3 03 is used This is a free software from Xilinx ready to download at Xilinx com and makes it possible to add I O ports serial UART timer etc To make C language test software for the microprocessor there are used two compilers one f
63. ompared with the signal shown in figure 6 7 Figure 6 10 Oscilloscope picture from transmission of CAN data packet Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 42 Chapter 7 Software Setup Napier University Edinburgh Chapter 7 Software Setup 7 1 Introduction This chapter is a short guide to setup the software and give an overview of the step for step development of a program in VHDL and C language for a PicoBlaze microcontroller ready to run in a Spartan 3 FPGA from Xilinx Download the Xilinx Design tool Project Navigator ISE WebPACK Service Pack 6 3 03 and the Simulation tool ModelSim XE ll 5 8C from xilinx com Install the software onto the computer and copy the project library named BGEPB1 from the CD ROM which has been attached at the last page in this report to the rood of you computer or in a folder with less at eight character 7 2 Setup of C and ASM Compiler HART Start the Xilinx Project Navigator and open the project from the library named BGEPB1 Compile the project with left click on the embedded connectivity embedded vhd as itis marked with a blue line in the Sources in Project window and after wards right click at the Synthesize XST and chose Rerun All in the Process for Source m window Figure 7 1 Xilinx Project Navigator Minimize the Project Navigator and copy the PicoBlaze C compiler named PCCOMP from the CD ROM to the
64. or the VHDL project Xilinx Project Navigator C vhdI BGEPBI BGEPB1_npl TEST thw File Edit View roject Source Process Options Window He Fil Edit i Proj S P Opti Wind Help D ag 27 m GE Emp amp M e i rx data mi wl 1610 2 RQ B BGEPB1 2 3 xc3s200 4ft256 3M embedded connectivity embedded vhd TEST TEST tbw embedded ucf 4 EE Module View a Snapshot View D Library View PORT 0 7 0 IPORT 3 7 0 IPORT_4 7 0 O AddExisting Source O Create New Source e View Behavioral Testbench ad ModelSim Simulator M Y Generate Expected Simulation Results M Simulate Post Translate HDL Model Figure 7 6 Test Bench Waveform Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 45 Chapter 7 Software Setup Napier University Edinburgh 7 4 Download to FPGA via IMPACT tool After complete compiling of the VHDL project without errors in Xilinx Project Navigator and the pin assignment is done the project ready to be downloaded to the FPGA But if it is the first time the project is downloaded to the FPGA there are some settings that needs to be checked but only once Right click on the project device in the Sources in Project Properties rope ame alue LI a Project window and chose properties In the xc3s200 Package ft256 Speed Grade 4 Project Properties check the right Device Family aia Device Package and speed Grade is chosen as Models the sam
65. or transmitting data via TX UART and receiving data via RX UART will the SFR value 08 be activated via the C language program that writes or reads via SBUF The VHDL code there interface this are showed in line 216 to 222 in figure 3 3 SERIAL DATA CONTROL This function co ols the Serial UART with write the option for the BAUD rate timing there control communication The Serial Channel Control register SCON do it possible to read the status flag for the receive and transmit bu sr and look after the status flag BDP for receive data SBUF Read and write to Comport SFR SBUF HEX 08 elsif WE io l and ID io X 08 then Write to Serial Buffer write to uart lt WE lo Enable write to UART data to uart Data in io Send Data to the UART buffer from 25 m the SFR register named SBUF elsif RE io 1 and ID io X 08 then Read to Serial Buffer read from uart lt RE io Enable read to UART Data out io lt data from uart Read Data from the UART buffer to the SFR register named SBUF Timer Baud rate serial low byte SFR TLBS HEX 09 elsif WE io l and ID io X 09 then Write the low byte TBS uart 7 DOWNTO 0 lt Data in io Send the low data byte 7 armed Baud rate Serial for Timer Baud rate serial high byte SFR THBS HEX OA elsif RE io 1 and ID io X 0A then Write the high byte TBS uart 15 DOWNTO 8 lt Data in io Send the high data byte to the Timer Baud rate Seria
66. roduction 1 1 About the project A microcontroller in a Field Programmable Gate Array FPGA is not world news but a free 8051 emulate core in a FPGA is not available on the marked at the moment There is an embedded microcontroller core on the market at the moment which matches the project though without Control Area Network CAN bus Interface It is the PB8051 Xilinx AllianceCORE to the price of 495 95 The embedded microprocessor cores for FPGA is split up in Hard core and Soft core processors a Hard core Processor is the IBM PowerPC 405 32 Bit RISC processor which run on Xilinx Virtex Il Pro and Virtex 4 The Soft core processor is a MicroBlaze 32 bit RISC core which runs up to 180MHz in a Virtex 4 with 166 MIPS build for complex systems networking telecommunication data communication and embedded systems All these microprocessor cores need a license to be used in a product Another free soft core processor from Xilinx is the PicoBlaze core which is an 8 Bit RISC processor this can be implemented on Virtex and Spartan series of FPGAs and CoolRunner IIl CPLDs This microprocessor is the one chosen for this project because it is free and makes it possible to run in a low cost Spartan 3 FPGA The purpose of this project is to make a cheap microcontroller core with peripherals like an 8051 standard microcontroller plus a CAN bus interface that makes it possible to customize the core for special projects 1 2 Aim of
67. rom Francesco Poderico s named PCCOMP a DOS version which compile the C language code to ASM code written in notepad The second compiler is from Xilinx and named KCPSMS3 which compile the ASM code to VHDL and making it ready to download to the FPGA after complete compiling of the project in the Xilinx project navigator Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering Ere Chapter 2 Implementation of PicoBlaze TM with I O ports interface Napier University Edinburgh Features The block diagram in figure 2 1 show the PicoBlaze microcontrollers supports the following features e 16 byte wide general purpose data registers e 1K instructions of programmable on chip program store automatically loaded during FPGA configuration e Byte wide Arithmetic Logic Unit ALU with CARRY and ZERO indicator flags e 64 byte internal scratchpad RAM e 256 input and 256 output ports for easy expansion and enhancement e Automatic 31 location CALL RETURN stack e Predictable performance always two clock cycles per instruction up to 200 MHz or 100 MIPS in a Virtex Il Pro FPGA e Fast interrupt response worst case 5 clock cycles e Optimized for Xilinx Spartan 3 Virtex ll and Virtex 1l Pro FPGA architectures just 96 slices and 0 5 to 1 block RAM e Assembler instruction set simulator support 1Kx18 Instruction PROM am Counter PC Scratchpad RAM gt OUT PORT ee Progr Flags INTERRUPT
68. s in the code e SYSTEM CLOCK Standard option is 50MHz run up to 200MHz or 100MIPS in a Virtex Il Pro FPGA e CONTROL Control signal for external Rom and RAM or other peripherals components e ADDRESS DECODER Address bus expander up to 16 bit wide e O PORTS Port 0 1 3 4 and 4 with external interrupts and Serial RS232 and CAN interface Symbol Name Address P0 PotO MEX HEX 02 Port 2 Address Bus low byte the lower 8 bit part of 16 bit HEX 03 H Port 2 Address Bus high byte the higher 8 bit part of 16 bit HEX 04 HEX 05 NN Table 1 1 List over Special Function Register Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 9 Chapter I Introduction Napier University Edinburgh 1 5 Problem solution The task concerns the building an embedded microcontroller in a FPGA with a CAN bus interface from the requirement specifications at page 9 The microprocessor used for this project is the Xilinx PicoBlaze microprocessor core and the task is to implement parallel Input Output port interfaces with Interrupts serial UART Timer and a CAN BUS interface It can be necessary to implement the VHDL code giving access to the Serial Flash ROM for more program space The PicoBlaze core the Instruction ROM and the serial UART is VHDL code which will be downloaded as free IP Core available from Xilinx com homepage The rest of the blocks in the block diagram in figure 1 1 at
69. service control flag is just test with an IF statement which looks on the flag and send the value to port 5 if the flag is set The reason that there is not used interrupt service routine in the test program is due to some problems with this function giving compiler errors when using the example from Francesco Poderico Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 20 Chapter 2 Implementation of PicoBlazeTM with I O ports interface Napier University Edinburgh 2 7 Simulation The VHDL code for the BGEPB1 system and the C code test program at page 20 is simulated in ModelSim with a view on Inputs and outputs which are accessed via the FPGA connections Read more about this option for the test bench simulation in chapter 7 3 at page 45 After reset of the FPGA the system will be initialized and will read and write to the ports as shown in figure 2 10 It is not possible to see the clock cycle in the simulation because one clock cycle is only 20nS and the simulation is shown from O to 25uS after 4uS are the first data write out to the 16 bit address bus and afterwards the other ports will be written out after the structure in the code Port 5 counts up shown in the bottom of the simulation and it will take only 6uS for each addition to the port Figure 2 10 Simulation of the program in ModelSim Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering ET
70. sif WE io 1 and ID io X 05 then Port 3 io lt Data_in_io Send data from Microcontroller to Port 3 elsif RE io 1 and ID io 4 05 then Data out io lt Port 3 io Send data from Port 3 to Microcontroller Port 4 I O SFR P4 HEX 06 elsif WE io l and ID io X 06 then Port 4 io lt Data in io Send data from Microcontroller to Port 4 elsif RE io l and ID io X 06 then Data out io lt Port 4 io Send data from Port 4 to Microcontroller Port 5 I O SFR P5 HEX 07 elsif WE io 1 and ID io X 07 then Port 5 io lt Data in io Send data from Microcontroller to Port 5 3 Benjamin Grydehoey 04007714 BEng Honours Electronic and Computer Engineering 52 Appendix A The VHDL code for VO Interface Napier University Edinburgh C vhd1 BGEPB1 IO Ports vhd 205 elsif RE io 1 and ID io X 07 then 206 Data out io lt Port 5 io Send data from Port 5 to Microcontroller 207 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 2 222 2 2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 208 SERIAL DATA CONTROL 209 This function controls the Serial UART with write and read via SBUF and 210 the option for the BAUD rate timing there control the speed for the serial 211 communication The Serial Channel Control register SCON do it possible to 212 read the status flag for the received and transmit buffer and look after 213 the status flag BDP for receive dat
71. sign of CAN bus The CAN bus interface is made in hardware and tested in transmit and receive mode and tested functional The lower Data Link Layer is made In VHDL controlling the 8 bit data packets which is send serial out with the encoding standard known as Non Return to Zero and inset the recessive and the dominant bit after every five identically bit The CAN bus is not finished The development is still missing functions as Cyclic Redundancy Check calculation and Error bit control The future development at the project The future plans for the project is to continue the development of the CAN bus interface and implementation this in the BGEPB1 microcontroller which will be available at the homepage www bg elektronik fpga Benjamin Grydehoej Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 48 Related Materials and References Napier University Edinburgh Related Materials and References References 1 Roman Jones Inc Emulate 8051 Microprocessor in PicoBlaze IP Core http www roman jones com PB8051Microcontroller htm 2 Xilinx com PicroBlaze 8 bit Embedded Microcontroller User Guide Page 13 14 http www xilinx com bvdocs userguides ug129 pdf 3 Xilinx com UART Transmitter and Receiver Macros Page 3 http www xilinx com bvdocs appnotes xapp223 pdf 4 Maxim ic com Data sheet Low Supply Current CAN Transceiver page 1 amp 4 http odfserv maxim ic com en ds M
72. the BAUD rate Since the transmitter can start sending this data at any time the receiver needs a method of identifying when the first LSB is being sent This is done with sending a Start bit as an active low start signal for the duration of one bit The receiver uses the falling edge from the Start bit to indicate that a new byte is ready to be received After the last data bit MSB is received check to see if the transmitted stop bit is high as expected in the confirmation for the UART Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering Oe Chapter 5 Implementation of serial UART Napier University Edinburgh 3 2 Implementation of serial UART The block diagram in figure 3 2 show the implementation of the serial UART connected via the I O interface block controlling the option of Special Function Register for serial data speed BAUD rate using the register named TLBS and THBS The serial interrupt for receiving data plus the serial status register flag SCON which looks on the buffer status Instruction ROM PicoBlaze Core 1Kx18 Block INSTRUCTION 17 0 4 OUT 17 0 ADDRESS 9 0 p ADDRESS 9 0 OUT PORT 7 0 IN PORT 7 0 PORT ID 7 0 WRITE STROBE READ STROBE RESET INTERRUPT gt INTERRUPT_ACK Data in io 7 0 DataBusPO 7 0 lt q gt Data_out_io 7 0 P1 7 0 ID_io 7 0 AddBus P2 15 0 P3 7 0 P4 7
73. the project The aim for this project is to get know how about FPGA and Very High Spe ed Integrated Circuit Hardware Description Language VHDL and to integrated PicoBlaze processor in the Spartan 3 FPGA with Input and Output for parallel and serial interfaces and finally simulate and test the project in practical Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering m Chapter 1 Introduction Napier University Edinburgh 1 3 Project description The block diagram in figure 1 1 shows the upcoming design of an emulated 8051 microcontroller consisting of the Xilinx PicoBlaze microprocessor with a instruction Read Only Memory ROM which makes it possible to run machine code from the ROM generate by assembly or C code compiler The machine code for the Instruction ROM is uploaded via the Xilinx program called Project navigator using the iMPACT tool The machine code is uploaded with the VHDL code for the project via Joint Test Action Group JTAG The size of the Instruction ROM is only 1K x 16 and very small and will only be used as a Boot or Monitor ROM with all necessary information for communication to the peripherals for more external ROM space available in the serial Flash which communicates via serial data control by the Serial Flash ROM interface Block Boot Rom Instruction Code 1KKx16 PicoBlaze Core Reset CLK 50MHz Serial UART CAN Bus UART Data 7 0 ADD 15 0 8051 E
74. tion and that it would be wise to read some data in the very near future Read FLAG for Receiving Buffer Data Present If BDP 1 Receiving Buffer Data Present is set When the internal buffer contains one or more bytes of received data this signal will become active HIGH and valid data will be available to read Table 3 2 List over Special Function Register SCON Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 297 Chapter 5 Implementation of serial UART Napier University Edinburgh 3 3 Simulation The simulation is made out form the test program in figure 3 6 which sends serial data out onto the comport with a baud rate at 115200 after having received a ASCI value s from e g a computer using the HyperTerminal The value s starts the transmission and the program sends the value HEY to the computer via serial communication With help from P4 and P5 it is possible to watch the Interrupt status and the buffer status The program is tested in ModelSim but it is not easy to show on paper because the transmission occurs over a lot of clock cycles and will not give much sense F prog rom Notepad BG x File Edit Format view Help a E EE E E E E E E r Pr E E E Er r E Er E Er Pr r r E Er E Er r E Er r YEr r E Er E Er r r r E Er r Er r E Er r YEr r E r E Er r Er r E Er r Er r Er E YEr r Er E Er Pr r r E r r r Yr COPYRIGHT BENJAMIN GRYDEHOEJ Www BG ELEKTRONIK DE 2006 TEST PROGRAM
75. to 0 64 Port 4 io inout std logic vector 7 downto 0 65 Port 5 io inout std logic vector 7 downto 0 66 TBS uart out std logic vector 15 downto 0 67 BDP uart in std logic 68 RBH uart in std logic Page 1 Benjamin Grydehoej 04007714 BEng Honours Electronic and Computer Engineering 50 Appendix A The VHDL code for W O Interface C vhd1 BGEPB1 IO Ports vhd read from data from writ dat in out ports Napier University Edinburgh RBF uart in std logic TBH uart in std logic TBF uart in std logic e to uart out std logic a to uart out std logic vector 7 downto 0 uart out std logic uart in std logic vector 7 downto 0 TRO timer inout std logic TFO timer in std logic TCO timer out std logic vector 7 downto 0 TR1 timer inout std logic TF1 timer in std logic TCl timer out std logic vector 15 downto 0 This program function is the handling of Input and Output control after the Special Function Register ports and option of Interrupt Service Routines and Timer control etc SFR for read and write to IENO RT UPS Enables 0 Variables Signal EA int std signal ET1 int std signal ETO int std signal EX2 int std signal EX1 int std signal EXO int std Signal ESO int std_ signal ICO int std signal ISO int std signal IT2 int std signal IT1_int std_ signal ITO int std signal IX2 int std signal IX1 int std signal IXO int std Interrupt Variables signal XO int
76. x323 f f set count value Low for Timer 1 lus autchartTCcHl Set Count value High for Timer 1 outchar IEN ff set Enable All Interrupt and Timer O aut char t TON ff Start Timer and Timer 1 whiletl Timer Flag inchar TOON Read value from Timer Flag Interrupt status inchar ISC Read value from Interrupt Flag outchariP4 Timer Flag ff write Timer Flag to P4 outchar P5 Interrupt status f f write Interrupt status to P5 Figure 4 4 Test program for timer 0 and 1 Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 33 aii Chapter 4 Implementation of Timers Napier University Edinburgh The simulation shows the timing Timer O sets a flag after 25 clock cycles which has a duration of 500nS this is shown as TFO Timer 1 set the first flag after 50 clock cycles on the timer 1 count shown in TF1 The timers raises one clock cycle every time the flag is set because there goes one clock cycle to clear the counter again This is not useful and it is necessary to change this in the VHDL code or take care of that in the C program The Interrupt goes high after the first Timer flag as is should but because there are problems with the Interrupt Service Routine in the C compiler It is not possible to auto clear the interrupt as expected with the Interrupt acknowledge If it worked as expected there should be calculates with a response up to 6 clock cycle before the flag would b
77. y to send the data in two parts First the low byte and second the high byte using the ID HEX 3 and HEX 04 This port can only transmit data and not receive anyone 05 na aata ri X 05 then X 06 then X 06 then Data in io i sana II POTU Figure 2 4 VHDL code for Transmit and Receive data to I O interface Benjamin Grydehoe 04007714 BEng Honours Electronic and Computer Engineering 16 Chapter 2 Implementation of PicoBlaze TM with VO ports interface Napier University Edinburgh Interrupt System The Interrupt system is used to control the external and internal interrupts build up after the principle from the 8051 microcontroller standard The register is modified and there are used different Special Function Register SFR value compared with an 8051 In figure 2 5 and 2 6 are the Interrupt Enable register IENO and IEN1 shown in this register it is possibility to activate and deactivate interrupts only the Watch Dog Timer WDT is not possible to disable after the enable The Enable All EA enables all interrupts or disables all interrupts IENO en Wer eu en em eu em en Figure 2 5 Special Function Register IENO If EXO 0 external interrupt O is disabled Bit Enables or disables external interrupt O X1 E Enables or disables external interrupt 1 If EX1 0 external interrupt 1 is disabled Enables or disables external interrupt 2 If EX2 0

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