Home

User Manual - ni2designs

Contents

1. E wi _Hardware ByteBlaster Mode JTAG T Progress ign Fil Program Blank 5 Device Design Files uli File Dene Che llseicode ecurity Software Files m Other Files ab 1 oldecoder decoder sof 1 507144 00011 0 0000007 x xi Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window 8 Currently selected hardware No Hardware g Available hardware items ary Hadwae Seve Port cnl p Add Hardware e Processing Total E Full Compilation Analysis amp Synthesis Fitter Assembler Timing Analyzer Step 19 In the opened window Click add hardware tab and select the hardware type as ByteBlasterMV or ByteBlaster Il and port as LPT1 f Quartus II c quartus demo decoder decoder decoder cdf a 18 Fie Edit View Project Assignments Processing Tools Window Help la x e hoe 89 60 Hardware ByteBlaster LPT1 we ha s Progress P Blank Securit Checksum Usercode m sede Conte rsof 507144 00011C00 0000007 Files Device Design Files Software Files Other Files Hardware Setup B iff x Hardw
2. AC I P Pin No Signal 1 Line 2 Neutral J P2 DC Pin No Signal 1 VDC 2 AGND Analog ground J P4 AC Line transformer Pin No Signal 1 Primaryl 2 Primary2 J P5 Step 100 Pin No Signal 1 Secondaryl 2 Common 3 Secondary2 J P8 Stepper Motor Pin No Signal 1 1 2 W2 3 W3 4 4 5 DGND digital ground J P6 Optically Isolated O Ps Pin No Signal 1 0 1 2 0 2 3 OP3 4 OP4 5 OP5 6 IGND Isolated ground 7 DGND Digital ground JP7 Relay1 J P9 Relay2 Pin No Signal Signal 1 Common Common 2 NO NC 3 NO NC 105 ni logic Pvt Ltd Pune USDP User Manual 12 IGBT Pin no Signal Description 1 G Gate 2 Collector 3 E Emitter J P10 FPGA Interface Pin No Signal Acex Spartan l Description 1 IP1 205 206 Isolated I P 1 2 IP2 203 205 Isolated I P 2 3 IP 3 202 204 Isolated I P 3 4 IP 4 200 202 Isolated I P 4 5 IP5 199 201 Isolated I P 5 6 RELAY1 198 199 Relay control 1 7 RELAY 2 197 195 Relay control 2 8 W2 196 194 Winding 2 control 9 W1 195 193 Winding 1 control 10 W4 193 192 Winding 4 control 11 W3 192 191 Winding 3 control 12 16 DGND Digital ground Note Connect power electronics module t
3. Apply Project Properties 7 G Module View Processes for Current Source Design Entry Utilities Empty Log ee tg re ee ee E ee ni logic P vt Ltd Pune USDP User Manual Step 4 Select VHDL source file name it decoder click next and enter entity 1 05 as Add en1 en2 en3 amp Y Define VHDL Source X Entity Name decoder Architecture Name E ehavioral iss in 2 0 2 jn Step 5 Write VHDL code for decoder Project Navigator E kit_test_projects USDP_Demo decoder decoder npl decoder 2 le File Edit View Project Source Process Window Help melo z 42 9 nsug eszs5sss mms e library IEEE use IEEE STD LOGIC 1164 LL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL decoder 22 61 x02s200 5pq208 XST VHDL V decoder decoder vhd entity decoder is Port Add in integer range 0 to 7 address i ps omo Y out bit vector 7 downto 0 decoder active end decoder B Module View g Snapshot View architecture Behavioral of decoder is Al xl Design Entry Utilities Y lt 00000001 s11 add when 1 0 and 2 0 and en3 1 else User Constraints others gt 0 Synthesize Implement Design Generate Programming File begin end Beh
4. Step 21 Now click the start programming button play symbol on the top LHS of the programming window keep the program configure option selected Quartus II c quartus demo decoder decoder decoder cdf E ax Fie Edit View Project Assignments Processing Tools Window Help 18 x 1028 55 960 898 BAY T 3 Compilation Hierarchies Hf decoder Check the design functionality on the board by applying signal from switches or other points 56 ni logic P vt Ltd Pune USDP User Manual Using Keil Compiler Designers can use compiler from Keil one of the compilers available in market Keil is a cross compiler Supporting the 8051 based architecture controllers from various vendors Compiler support the source codes written in C and assembly languages For starting up with USDP we have made a design flow guide for using the keil compiler but for more information users can surf the help index of keil compiler Install the Keil compiler from provided CD ROM you can use the evaluation version at start up which supports the program code upto 2KB which is sufficient for small development purposes Step 1 Run the keil compiler EXE which in turn will open the compiler Ble Edit View Project Debug Peripherals Tools SVCS Window Help Bsug 9e 2c s92 w d j jeja ums oemm xx
5. Edit view Project Debug Peripherals Tools SVCS Window Help New Poke Lal S o em Import pision1 Project Open Project Close Project Eile Extensions Books and Environment Targets Groups Files Select Device For Target Remove Options Clear Group and File Options Build target Rebuild all target Files S Translate Colt Stop build 1C Keil shail SWITCH uv2 2C Keil serial Uv2 57 ni logic P vt Ltd Pune USDP User Manual Step 3 In the opened window user has to give project name and select the folder for the project creation for example name it keil demo Click OK and in the next window you have to select the device to work on the vendor name is Philips and the device number is 8xC51RD2 The window will look like as below keil demo p ision2 Edit View Project Debug EUER Tools Svcs Window mm 9 zej w s a mi oemm Select Device for Target Target 1 Target 1 CPU Vendor Philips Device 8xC51RD2 Use Extended Linker LX51 instead of BL51 Family 5 51 Use Extended Assembler 551 instead of 51 Data base 8xC51MB2 8051 based CMOS Dual DPTR WDT 8 C51MC2 32 1 0 lines 3 Timers Cot 7 Interrupts 4 priority levels E 8 51 64 K ISP FLASH EPROM 256 256 Bites on chip RAM additional 768
6. Parallel Port Connector DB 25 Parl 206 10 192 2 205 11 191 Par3 204 Par12 188 Par4 202 13 187 5 201 14 203 199 15 200 Par7 195 Parl6 189 Par8 194 17 181 Par9 193 Pin 18 25 of DB 25 connector are ground Note Both the FPGAs share the above I Os User has to take care that no two pins are defined as output as in that case there would be short on the bus and may damage FPGA 1 05 User can define the following combination of FPGAs shared 1 05 FPGA1 FPGA2 Input Input Allowed Output Input Allowed Input Output Allowed Output Output Notallowed 22 ni logic P vt Ltd Pune USDP User Manual PIC 16F877 Micro controller Pin details Acex 1K Spartan ll Acex 1K Spartan ll 1 ANO RAO 36 34 A2 ANI RAI 37 35 AN2 RA2 40 41 4 AN3 RA3 41 42 A5 AN4 RA4 46 45 A6 AN4 RAS 47 46 A7 RDO 55 49 8 01 56 57 9 RD2 60 60 A10 RD3 61 61 11 RD4 65 67 12 RD5 67 68 A13 RD6 70 71 A14 RD7 71 73 15 MCLR 15 81 Acex Spartan ll Acex Spartan ll Bl RCO 38 36 B2 RC1 39 37 B3 RC2 44 43 B4 45 44 B5 RC4 53 47 B6 RC5 54 48 B7 RC6 57 58 B8 RC7 58 59 B9 RBO INT 63 62 B10 64 63 11 RB2 68
7. Baud Rate 3500 Device 8SC51RA2 E Erase all Flash Security Clks Hex File Browse Last Modified Unknown Size Unknown 4 9 Verify after programming Set Security Bit 1 Fill unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 g Execute clks cycle Your Training or Consulting Partner Embedded Systems Academy Erase block 0 0x0000 0 0FFF Erase block 1 0 1000 0 1 FFF WwWwW esacademy com The above software is been divided 5 sections 1 For device selection and settings 2 For program memory block erasure selection 3 Selection of HEX file 4 Programming options and security settings 5 Starting programming So one bye one we will look on all the sections and settings required to work on this particular controller module 70 ni logic Pvt Ltd Pune USDP User Manual Flash Magic File ISP Options Help Advanced Options 4 Reset 2 Baud Rate 9600 Device 89C51RD2Hxx 7 Erase block 4 OxCO00 OsF FFF i 11 059 4 Erase Flash Security Hex File Ltd ni2 Designs Almighty Kit Keil Demo serial_transmit hex Browse Last Modified 11 7 2003 4 14 11 PM Size 302 bytes Verify after programming Set Security Bit 1 Fill unused Flash Set Security Bit 2 Generate checksums Set Sec
8. Release Set Reset Output Events Release Write Enable Output Events Release DLL Output Events Drive Done Pin High Default 6 Default Default Help 42 ni logic P vt Ltd Pune USDP User Manual Step 12 Now run the Generate Programming File option which will in turn generate the programming file for FPGA configuration Left click on the Generate Programming File option which will show the programmer below named as Configure Devices IMPACT o FT Project Navigator test projects4USDP Demo decoder decoder npl decoder E E e 1 File Edit Project Source Process Window Help 18 p suam manm library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL Sources in Project decoder E Ed 25200 5 208 XST VHDL E V decoder decoder vhd decoder ucf ucf entity decoder is Port Add in integer range 0 to 7 address i ps enl in std logic active low enable en2 in std logic active low enable en3 in std logic active high enable out bit vector 7 downto 0 decoder active high end decoder E Module View Snapshot View D Library View architecture Behavioral of decoder is begin Processes for Curren
9. 27 ni logic Pvt Ltd Pune USDP User Manual 12 IGBT Pin no Signal Description 1 Gate 2 Collector 3 E Emitter J P10 FPGA Interface Pin No Signal Acex Spartan l Description 1 IP1 205 206 Isolated 1 2 203 205 Isolated I P 2 3 IP 3 202 204 Isolated I P 3 4 IP 4 200 202 Isolated I P 4 5 IP5 199 201 Isolated I P 5 6 RELAY1 198 199 Relay control 1 1 RELAY2 197 195 Relay control 2 8 W2 196 194 Winding 2 control 9 1 195 193 Winding 1 control 10 W4 193 192 Winding 4 control 11 W3 192 191 Winding 3 control 12 16 DGND Digital ground Note The above pin assignment is for the power electronics module cable provided along with USDP Kindly use the same cable to interface the power electronics module ni logic P vt Ltd Pune USDP User Manual Chapter 6 umpers and Headers Pin description and Settings In this chapter we will have a look on the jumper settings of all the USDP modules USDP Baseboard Clock J P1 Pin 1 Clock Pin2 GCK0 Pin 3 Ground To use the oscillator clock short pin 1 and 2 It is recommended to ground the GCK0 during programming J PDIS These four jumpers are used to disable the 7 segment displays J ust remove the jumpers to isolate to displays from FPGAs JPA JPB JPC amp JPD These jumpers are used to select the 1 0 mode of the LEDs Tota
10. LC5 LC6 9 LBO LB1 LB2 A11 LB4 LB5 A13 LAQ 1 A1 A14 and 1 14 are LEDs 100 to 1063 are general purpose bus the connector All cards are mapped on above layout kindly refer the below pin out detail for individual card layout ni logic P vt Ltd Pune USDP User Manual Add On Connector Layout Detail With Adaptor Module Connections PIC Memory LEDs PIC Memory LEDs 1 ANO RAO Al6 LDO A2 ANI RA1 Al7 LD1 AN2 RA2 18 LD4 4 AN3 RA3 DO LD5 A5 AN4 RA4 D1 LCO AN4 RA5 D2 7 RDO D3 LC4 8 RD1 D4 LC5 A9 RD2 D5 LBO A10 RD3 D6 11 RD4 D7 LB4 A12 RD5 RD LB5 A13 RD6 WR LAO 14 RD7 A19 1 15 MCLR A20 LA4 A16 LA5 ADC DAC ADC DAC A17 DO A18 D1 A19 D4 A20 D5 A21 D8 A22 D9 A23 A24 2 A25 DBO 26 DB1 A27 DB4 A28 DB5 A29 INT A30 RDY 89c51 89c51 A31 ADO A32 AD2 A33 AD4 A34 AD6 A35 A8 A36 A10 A37 12 A38 14 A39 PORT1 1 A40 PORT1 3 A41 PORT1 5 A42 PORT1 7 A43 INTO A44 INT1 A45 ALE A46 FRST A47 1060 A48 1061 Memory LEDs PIC Memory LEDs Bl RCO A0 LD2 B2 RCl Al
11. Set Security Bit 3 Execute Bolks cycle stat Erase block 3 FFF Erase block 4 O CODO O FFFF Erase all Flash Security Technical on line articles about 8051 and programming 73 ni logic P vt Ltd Pune USDP User Manual Step 7 In the 4 section set the Execute option and clear all other options This option is to execute the code after programming the controller Flash Magic File ISP Options Help 1 2 COM Port 1 Baud Rate 9600 2 Erase block 3 Q 8000 O BFFF Device 89 51 02 v Erase block 4 OxCO00 OsF FFF il 1 0592 Erase all Flash Security Hex File Ltd ni2 Designs 4lmighty Kit Keil Demo serial_transmit hex Browse Last Modified 11 7 2003 4 14 11 PM Size 302 bytes 4 9 Verify after programming Set Security Bit 1 Fil unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 z Execute 6clks cycle E Technical on line articles about 8051 and XA programming wwWw esacademy com fag docs EA Step 8 Now in the 5 section press the start button which in turn start the programming of controller After displaying of Finished message on the bottom side of window start working on your application Note If any modification is there in the source code then regenerate the HEX file and rep
12. DISP1 17 SLO 8 RLO 6 segB 31 DISP2 18 511 15 RL1 10 segC 30 DISP3 20 SL2 9 RL2 7 segD 29 DISP4 21 SL3 16 14 segE 27 segF 24 segG 23 segDP 22 Parallel Port Connector DB 25 Parl 206 10 192 2 205 11 191 Par3 204 Par12 188 Par4 202 13 187 5 201 14 203 199 15 200 Par7 195 Parl6 189 Par8 194 17 181 Par9 193 Pin 18 25 of DB 25 connector are ground Note Both the FPGAs share the above I Os User has to take care that no two pins are defined as output as in that case there would be short on the bus and may damage FPGA 1 05 User can define the following combination of FPGAs shared 1 05 FPGA1 FPGA2 Input Input Allowed Output Input Allowed Input Output Allowed Output Output Notallowed 83 ni logic P vt Ltd Pune USDP User Manual 3 Altera FPGA Module The Altera FPGA module contains an ACEX 1K family FPGA with a choice of 50 000 gates or 100 000 gates FPGA With a total pins 208 and maximum 147 user I O pins users can develop designs requiring high density and higher number of I Os There are total 96 1 0 pins brought down to the base bus for add on module connection User can use this bus for their application design with the add on mo
13. 1 MasterSerial 0 0 0 Mode selection jumpers J P4 J P5 J P6 J P7 Serial JTAG Short 1 2 Short 2 3 PROM BYPASS J 3 amp J 4 To Chain PROM To Bypass PROM Short 1 2 Short 2 3 Shorting 1 2 will bring the PROM in chain with FPGA In this case user can configure the PRO M and use for programming file storage Shorting 2 3 will remove the PROM from chain and only FPGA would be connected to programming port Global Clock Buffers Pin 1 GCK2 GCK3 Pin2 GND GND Note These buffers are extra from GCKO Altera FPGA Module Programming Mode selection jumpers J 3 J 8 MSEL1 MSELO Passive Serial PS 0 0 0 1 For logic low short 2 3 and for logic short 1 2 for logic High Mode selection jumpers J 4 J 5 6 J 7 Serial J TAG Short 2 3 Short 1 2 PROM BYPASS J 1 amp J2 To Chain PROM To Bypass PROM Short 1 2 Short 2 3 Shorting 1 2 will bring the PROM in chain with FPGA In this case user can configure the PROM and use for programming file storage Shorting 2 3 will remove the PROM from chain and only FPGA would be connected to programming port 30 nilogic Pvt Ltd Pune 89c51 Module Square Wave J 1 clock from RTC Pin2 Ground Interrupt Timer J P4 Pinl Interrupt 0 INTO I P Pin2 In
14. COM ports of relay Program the FPGA with the given source code and control the relays from the switches Source code name relay vhd Pin lock file name relay ucf 115 ni logic P vt Ltd Pune USDP User Manual Keypad Controller Code description This code is the 4x4 keypad controller Users can press the keys and see the key value on the 7 segment displays Further users can modify this code for their applications Working with code Inserthe FPGA module on USDP slot connect the keypad with the cable provided Program the FPGA with the given source code Press the keys of keypad and check the displayed value on the 7 segment displays Source code name keypad vhd Pin lock file name keypad ucf LCD Module Code description This code is generalized code written in C for message displaying on LCD module The code written is for 89c51RD2 controller At bottom of source code there is a dispstr function which displays the written message in its body on LCD Users can modify this text line to change the message to be displayed Working with code Insert the 89c51 module in USDP connect the LCD module to 89c51 through the general purpose PCB Program the 89c51 controller with the given HEX code and check the message displayed Source code name LCD USDP c Programming file name LCD USDP hex Access control application Code description Sample codes are provided along with USDP for access control application Sam
15. from several months to more than a year depending on the complexity of the device And if the device does not work properly or if the requirements change a new design must be developed The up front work of designing and verifying fixed logic devices involves substantial non recurring engineering costs or NRE These NRE costs can run from a few hundred thousand to several million dollars With programmable logic devices designers use inexpensive software tools to quickly develop simulate and test their designs Then a design can be quickly programmed into a device and immediately tested in a live circuit There are no NRE costs and the final design is completed much faster than that of a custom fixed logic device Another key benefit of using PLDs is that during the design phase customers can change the circuitry as often as they want until the design operates to their satisfaction That s because PLDs are based on re writable memory technology to change the design the device is simply reprogrammed Once the design is final customers can go into immediate production by simply programming as many PLDs as they need with the final software design file CPLDs and FPGAs The two major types of programmable logic devices are field programmable gate arrays FPGAs and complex programmable logic devices CPLDs Of the two FPGAs offer the highest amount of logic density the most features and the highest performance The largest FPGA provides
16. lt define TIMER1_RELOADL lt static volatile bit SEL static volatile bit SEL1 static volatile bit SEL2 static volatile bit SEL3 static volatile bit TEST UINT count UCHAR digit UINT digbuf 4 UCHAR 1141 iam 4 usdp 4 Cuns igned gt amp PORTC8 0 Cuns igned gt amp PORTCx8 1 Cuns igned gt amp PORTC8 2 Cuns igned gt amp PORTCx8 5 Cuns igned gt amp PORTCx8 4 void inithw lt void gt ADCON1 80x86 INTCON 8x88 OPTION 8x88 TRISC 8x88 TRISD 8x88 TMR1H TIMER1_RELOADH TMRiL TIMERi_RELOADL Line 27132 Col 1 Insert ow mode tility Display Hi Iam USDP on Requires FPGA as feed thr A l xl elp T Step 11 If the compilation process is over then the HEX will be generated in the project location on the name of source code If user wants to run the Make process then they can go to Make menu and select Make option This will create the HEX file on the project name E o ile dit Options Compile ake un DISP PIC C USDP Sample Code Display Hi Iam USDP on 7 segnent Requires FPGA as feed through in b lt pici687x h gt typedef unsigned int UINT typedef unsigned char UCHAR typedef unsigned long ULONG define TIMER1_RELOADH lt xfC gt define TIMER1_RELOADL 8x66 static volatile bit SEL 8 Cunsi static volatile bit SEL1 8 lt unsi static volatile bit SEL2 8 Cunsil static volatile bit SE
17. 05 E or x j a nga an Clock OSC SLOT3 o ER 9 101 o 001 Module en connectors slots mu 8 ARDT a NN E E M a 9 i LL 2 o 5 lt re tg D ce a x 7 seg Displays 8 wer CL USER AREA J0 JP1 CLOCK Ko GND KEY PAD QS Au PLD Connectors S lots C Q SLOT1 z Ei 4 v EDI Power Supply Programming PLD Selector SlotSelector header Port USDP Base Board Ident 80 ni logic Pvt Ltd Pune USDP User Manual 2 Xilinx FPGA Module The Xilinx FPGA module contains a Spartan Il family FPGA with a choice of 50 000 gates 200 000 gates FPGA With a total pins 208 and maximum 147 user I O pins Users can develop designs requiring high density and higher number of I Os with this FPGA There are total 96 I O pins brought down to the base bus for add on module connection User can use this bus for their application design with the add on module Also 32 bits out this bus are been shared with configurable 1 05 The bank 0 is been brought on 08 25 connector with its VREF pins Designers can use this bank for different voltage signaling Also this DB 25 connector can be used to interface with the PC s parallel port for communic
18. 69 B12 69 70 B13 RB4 73 74 B14 RB5 74 75 B15 RB6 86 83 B16 RB7 87 84 MCLR is active LOW reset R efer the device datasheet for pin description and functioning Note PIC micro controller and SRAM memory module share the same bus kindly use one module one ata time on the 3 slots ni logic P vt Ltd Pune USDP User Manual SRAM Module Pin details Acex Spartan ll Acex 1K Spartan ll Al Al6 36 34 A2 17 37 35 18 40 41 A4 DO 141 42 5 D1 46 45 A6 D2 47 46 AT D3 55 49 A8 04 56 57 9 05 60 60 10 06 61 61 11 07 65 67 12 RD 67 68 A13 WR 70 71 14 A19 71 13 A15 A20 75 81 Acex Spartan ll Acex Spartan ll Bl 0 38 36 B2 Al 39 37 B3 2 44 43 B4 45 44 B5 4 53 4 5 54 48 7 A6 57 58 B8 7 58 59 B9 A8 63 62 B10 A9 64 63 B11 10 68 69 B12 All 69 70 B13 Al2 73 74 B14 13 74 15 B15 A14 86 83 B16 15 87 84 R efer the device datasheet for pin description and functioning Note PIC micro controller and SRAM memory module share the same bus kindly use one module one ata time on the 3 slots ni logic P vt Ltd Pune USDP User Manual Acex Spartan ll
19. A3 40 41 4 41 42 B3 44 43 B4 45 44 A5 46 45 A6 47 46 B5 53 4 B6 54 48 7 55 49 8 56 57 57 58 8 58 59 9 60 60 10 61 61 B9 63 62 B10 64 63 11 65 67 12 67 68 11 68 69 12 69 70 13 70 11 14 71 13 13 73 14 B14 74 15 15 75 81 A16 85 82 15 86 83 16 87 84 17 92 87 18 90 86 B17 89 3 B18 88 4 A19 96 94 A20 95 90 B19 94 89 B20 93 88 21 101 98 22 100 97 B21 99 96 B22 97 95 A23 111 102 A24 104 101 B23 103 100 B24 102 99 A25 115 111 A26 114 110 B25 113 109 B26 112 108 A27 121 115 A28 120 114 B27 119 113 B28 116 112 A29 127 122 A30 126 121 29 125 120 B30 122 119 A31 133 127 A32 132 126 B31 131 125 B32 128 123 A33 139 134 A34 136 133 B33 135 132 B34 134 129 A35 143 139 A36 122 138 B35 141 136 B36 140 135 A37 149 146 A38 148 142 B37 147 141 B38 144 140 A39 159 150 A40 158 149 B39 157 148 B40 150 147 41 163 163 42 162 162 41 161 152 B42 160 151 A43 168 167 44 167 166 B43 166 165 B44 164 164 A45 173 174 A46 172 173 B45 170 172 B46 169 168 A47 177 179 48 176 178 47 175 176 48 174 175 Note Both the FPGAs share the bus on add on connector User has to take care that no two pins are defined as output as in that case there would be short on the bus and may damage FPGA 1 05 User can define the following combina
20. ADC and DAC kindly refer the datasheet provided along with the protoboard 87 ni logic Pvt Ltd Pune USDP User Manual Acex Spartan ll Spartan ll A17 DO 92 87 18 01 90 86 19 04 96 94 20 05 95 90 21 08 101 98 22 D9 100 97 23 EN1 111 102 A24 2 104 101 25 DBO 115 111 A26 DB1 114 110 27 DB4 121 115 A28 DB5 120 114 A29 INT 127 122 A30 RDY 126 121 Acex Spartan ll Acex Spartan ll B17 D2 89 3 B18 D3 88 4 B19 D6 94 89 B20 D7 93 88 B21 D10 99 96 B22 D11 97 95 23 0 103 100 24 Al 102 99 B25 DB2 113 109 B26 DB3 112 108 B27 DB6 119 113 B28 DB7 116 112 B29 CS 125 120 B30 RD 122 119 Header Details DAC J 1 Pinl DAC Channel 1 2 DAC Channel 2 Pin 3 Ground ADC 2 Pinl ADC Channel 1 Pin2 ADC Channel2 Pin3 ADC Channel 3 Pin4 ADC Channel 4 Pin5 Ground 2 This jumper is for setting the reference voltage This module has onboard reference voltage generation to use that short 2 3 Note ADC DAC work in linear monotonic format with VREF 00000000 and VREF 11111111 So take care of numbering system while designing the logic ni logic Pvt Ltd Pune USDP User Manual DAC O P Ji ADC I P DAC1 XDAC2 GND U
21. LD3 B3 2 06 4 LD7 B5 RC4 A4 LC2 B6 RC5 5 LC3 B7 RC6 A6 LC6 BB RC7 Al LC7 B9 RBO NT A8 LB2 10 RB1 LB3 B11 RB2 Al0 LB6 B12 All LB7 B13 RB4 Al2 2 RB5 A13 LA3 B15 RB6 A14 B16 RB7 A15 LA7 ADC DAC ADC DAC B17 D2 B18 D3 B19 D6 B20 D7 B21 010 B22 011 B23 A0 B24 A1 B25 DB2 B26 DB3 B27 DB6 B28 DB7 B29 CS B30 RD 89c51 89c51 B31 AD1 B32 AD3 B33 AD5 B34 AD7 B35 A9 B36 11 B37 Al3 B38 A15 B39 PORT1 2 B40 PORT1 4 B41 PORT1 6 B42 PORT1 8 B43 TO 44 B45 RD 51 B46 WR 51 B47 1062 B48 1063 PIC Memory LEDs share the connections ADC DAC Card connections 89c51 Card connections PIC Memory LEDs share the connections ADC DAC Card connections 89c51 Card connections ni logic P vt Ltd Pune USDP User Manual Chapter 5 Pin Assignment This chapter will go through the pin assignment of FPGAs with various add on modules The three PCI connectors on board share the bus All modules can be plugged on any one ofthe connector as the connectors are sharing the common bus Here is the add on connector pin out with Altera ACEX 1K FPGA and Xilinx Spartan ll FPGA Acex 1k Spartan ll Acex 1k Spartan ll Acex 1k Spartan ll Acex 1k Spartan Al 36 34 A2 37 35 Bl 38 36 B2 39 37
22. NYY YY YY YY Note For jumper header setting refer chapter jumper setting and for Altera Quartus flow refer chapter EDA tools 68 nilogic Pvt Ltd Pune USDP User Manual Slot selection There are total five slots on the baseboard of USDP The first two Slotl amp Slot2 are PLD connector slots where user can insert provided FPGA modules The remaining P CI based connector slots Slot3 Slot4 amp Slot5 are used for add on module insertion FPGA module can be inserted in Slotl amp Slot2 but for programming the FPGAs user has to select the Slot which he has used and the device vendor he intends to program this can be done by using the selector cards provided along with the USDP board The PLD selector card can be used to select the PLD vendor and the Slot selector card can be used to selectthe slot Refer the table below forthe combination PLD Selector Altera Xilinx 1 2 2 3 Slot Selector Slot1 Slot2 12 2 3 Programming Modes Both the PLD vendors Xilinx and Altera modules support various programming modes to download the configuration file in FPGA Here is the table for programming modes for Xilinx and Altera modules For Xilinx FPGA module Modes 0 M1 2 J TAG 1 0 1 Slave Serial 1 1 1 Master Serial 0 0 0 The same table is also printed on the module which the users can refer while programming To apply logic high and low on
23. PLD modules are available for different devices from vendors like Xilinx Altera etc The user can prototype upto 1 million 10 00 000 gate count designs Here is the listof PLD daughter add on cards and their feature set Features of PLD Modules Xilinx FPGA Card Supports Spartan ll device family of FPGA s On board Regulators for VCCINT and VCCIO generations User selectable configuration modes Facility to program through J TAG Slave serial and Master serial modes Onboard PROM support Support for different 1 0 Standards High speed interface with other add on cards Capability to use special clock management features of S partan ll A complete 1 0 bank for user VREF interface using DB25 connector Parallel port interface directly from add on card of FPGA Moo to xD MOS 943 220 5 97 P ix Xilinx PLD Family Architecture Device Available Package Spartan Il 2550 XC2S 100 25150 25200 0208 9 ni logic P vt Ltd Pune USDP User Manual Altera FPGA Card Supports ACEX 1K device family of FPGA s On board Regulators for VCCINT and VCCIO generations User selectable configuration modes Onboard PROM support High speed interface with other add on cards Parallel port interface directly from add on card of FPGA NIN YY C2 Altera PLD Family Architecture Device Available Package ACEX 1K EP1K50 1 100 0208 Note Customized daughter cards also available fo
24. TECH C PROFESSIONAL DEVELOPMENT SYSTEM Microchip PIC U8 82 11 Copyright lt C gt 1984 2663 HI TECH Software All Rights Reserved 62 nilogic Pvt Ltd Pune USDP User Manual Step 2 To create new project goto Make menu and select New project option dit Options Compile ake tility el o ile Line 1 1 Col 1 Insert C mode Step 3 After giving the project name and location you need to select the device The provided PIC module consists of 16F877 processor o 11 dit Options Compile ake un tilit el untitled Select Midrange processor lt 2 12F629 lt gt 16F627 lt 16F877 lt gt 12F675 lt gt 16F84 lt gt 16F877A gt 16084 lt gt 16F84A L OK Enter Cancel Esc gt Help Fi gt Line 1 1 11 Insert mode c 4 63 ni logic Pvt Ltd Pune USDP User Manual untitled Select float type lt 24 bit double float F2 32 bit double float it OK Enter J Help Fi gt untitled Select output file format Motorola S Record HEX Intel HEX Binary Image UBROF Tektronix HEX American Automation symbolic HEX Intel OMF 51 Bytecraft COD file Library Extended 51 A IVA AA A A A vvyvvvvvvv v L OK Enter J Cancel Esc gt 64 ni logic P vt Ltd Pune USDP User Manual Step 6 Select the compiler optimization according to your requirement by default you can select Glob
25. as the same name of entity decoder vwf Quartus II c quartus demo decoder decoder decoder vwf iri File Edit View Project Assignments Processing Tools Window Help laj x Dau DE 8999 3 Files H E Device Design Files Software Files Other Files Files Design Units 14 x Module Progress Ti Processing Total 00 00 Analysis amp Synthesis 00 00 Step 11 In Altera Quartus Il software you can perform Functional and Timing simulation For simulation mode settings go to assignments menu and click settings Quartus II c quartus demo decoder decoder decoder vwf TA Ele Project Assignments Processing Tools Window Igi x 98 YS Pisae Bao a a eee Tm Jis 15 0 ns Pointer 267 ps Interval 14 73ns End Files Settings Ctrl Shift E Device Design Files ps 10 0 ns 200 ns 30 0 ns 400 ns 50 0 ng Software Files Timing Wizard 150ns Other Files Compller Settings Wizard Simulator Settings Wizard B 5 Software Build Settings Wizard i AssignmentEdior Ctrl Shift A Remove Assignments Demote Assionments Hierarchies 0 Import MAX PLUS II Assignments
26. gives flexibility to interface the LCD with any one of the USDP modules J P6 LCD Header Pin No Signal Pin No Signal 1 GND 2 5V 3 NC 4 RS 5 NC 6 EN 7 8 D1 9 D2 10 D3 11 D4 12 D5 13 D6 14 D7 15 NC 16 NC LCD 5 Pin Signal Pin Signal 1 00 2 RS 3 D2 4 EN 5 D4 6 01 7 D6 8 D3 9 D7 10 D5 108 ni logic P vt Ltd Pune USDP User Manual aund 21507 8v Tv V ey 9 9 9 9 Aapea d31 8t Tr Ov ziar zn Ta quocp 9Tdr w asoduny eaauag g e zug 9 9 9262 eap ZI sereset OJA General Purpose PCB Board Ident ni logic Pvt Ltd Pune 109 cnn PESE IE USDP User Manual Chapter 11 Designing Application on USDP using provided modules Any electronic system is developed for an application solving a problem or giving ease to product usage A system can be defined as A group of independent but inter related elements comprising a unified whole Or A processing platform where all element work together for a goal with the given instructions An basic electronic system see figure below consists of a master which can be microprocessor or a microcontroller a memory store to the instructions or data analog circuitry to interface with the external worl
27. in isolated board High current capacity connectors Easily interfaced with motors and other circuits Optimum choice for Pulse Width Modulation PWM motion control line monitoring amp control applications 6 General Purpose Add On Card Free of charge General purpose layouts Helps in prototyping electronic circuits with FPGA interface Useful in mixed signals designs Other Accessories Provided 9 J TAG Cable for programming of FPGAs Serial cable for RS 232 communication from 89c51 PIC programming Cable PIC Serial Cable for RS 232 communication ADC DAC cables for interfacing external world signals SMPS 4x4 membrane keypad with cable 16x2 character LCD with cable User Manual with instructions reference designs examples sources codes and reference datasheets CD ROM containing user manual source codes reference designs and programming softwares Note The above modules comes in a package many modules can be optional to user ni logic Pvt Ltd holds the rights to modify the product features and specification without notice ni logic Pvt Ltd Pune USDP User Manual Chapter 3 Universal System Development Platform USDP Overview Universal System Development Platform USDP FPGA CPLD VHDL Verilog Multi Architecture Support Xilinx Altera etc on single platform Training Features Single board platform for all types of training courses on Embe
28. ll Acex Spartan ll B31 AD1 131 125 B32 AD3 128 123 B33 AD5 133 132 B34 AD7 134 129 B35 A9 141 136 B36 All 140 135 B37 13 147 141 B38 A15 144 140 B39 PORT1 2 157 148 40 PORT1 4 150 147 41 PORTI 6 161 152 B42 PORT1 8 160 151 B43 TO 166 165 44 T1 164 164 B45 RD 51 170 172 B46 WR 51 169 168 FRST is active HIGH reset Refer the device datasheet for pin description and functioning ni logic P vt Ltd Pune USDP User Manual Power Module Pin Detail Power module is independent of USDP baseboard and can me mapped to any of the 1 05 of the adaptors available Here by are the header details of the power module AC I P Pin No Signal 1 Line 2 Neutral J P2 DC Pin No Signal 1 VDC 2 AGND Analog ground J P4 AC Line transformer Pin No Signal 1 Primaryl 2 Primary2 J P5 Step 100 Pin No Signal 1 Secondaryl 2 Common 3 Secondary2 J P8 Stepper Motor Pin No Signal 1 1 2 W2 3 W3 4 4 5 DGND digital ground J P6 Optically Isolated O Ps Pin No Signal 1 0 1 2 0 2 3 OP3 4 OP4 5 OP5 6 IGND Isolated ground 7 DGND Digital ground JP7 Relay1 J P9 Relay2 Pin No Signal Signal 1 Common Common 2 NO NC 3 NO NC
29. millions of system gates the relative density of logic These advanced devices also offer features such as built in hardwired IP cores such as the IBM Power PC PCI cores microcontrollers peripherals etc substantial amounts of memory clock management systems and support for many of the latest very fast device to device signaling technologies FPGAs are used in a wide variety of applications ranging from data processing and storage to instrumentation telecommunications and digital signal processing CPLDs by contrast offer much smaller amounts of logic up to about 10 000 gates But CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications Low power CPLDs are also available and are very inexpensive making them ideal for cost sensitive battery operated portable applications such as mobile phones and digital handheld assistants 3 ni logic P vt Ltd Pune USDP User Manual The PLD Advantage Fixed logic devices and PLDs both have their advantages Fixed logic devices for example are often more appropriate for large volume applications because they can be mass produced more economically For certain applications where the very highest performance is required fixed logic devices may also be the best choice However programmable logic devices offer a number of important advantages over fixed logic devices including PLDs offer customers much more flexibility during the des
30. ni Logic Pvt Ltd ni2 Designs Almighty Kit Keil Demo serial_transmit c project Debug Peripherals Tools 505 Window Help A m5je mmoerm Icm This Program takes data from PORT 0 and sends it on the serial PORT 1 59 Target 1 The data is sent only when there is change on the port 0 data Source Group 1 This program runs with FPGA only This code is written for USDP serial transmit c include lt intrins h gt include lt reg52 h gt define TIMER RELOAD 921 typedef unsigned int UINT typedef unsigned char UCHAR typedef unsigned long ULONG UCHAR mult void serial void interrupt 4 using 2 if RI RI 0 void init hw void TMOD 0x21 IE 0x92 1001 0010 SCON 0 50 0101 0000 TLO TIMER_RELOAD THO S5 2e Fa 4 59 ni logic P vt Ltd Pune USDP User Manual Step 7 For building the program code or HEX code we need to set some parameters in the compiler Go to project options and click option for target New Project Import p ision1 Project Open Project Close Project Eile Extensions Books and Environment mp n Hs it on the serial PORT bn the port 0 data Target 1 5 3 Source Targets Groups Files Transl
31. r7 Ga BQO Compilation Report Analysis amp Synthesis Summary 23 Files amp B Legal Notice Device Design Files gE Fow Summary Software Files Flow Settings Other Files Flow Elapsed Time Analysis amp Synthesis Analysis amp Synthesis Summary 4B Analysis amp Synthesis Settings QBs Hierarchy Analysis amp Synthesis Resource Utilization by Er Cul amp Status Successful Mon Oct 20 23 57 50 2003 xb Analysis amp Synthesis Equations Compiler Setting Name decoder amp 2 Analysis amp Synthesis Messages Top level Entity Name decoder Hierarchies Files d Design Units Family ACEXIK Total logic elements 10 Total pins 14 Total memory bits 0 Total PLLs 0 4 Step 9 For performing simulation we need to create stimuli file from where we can apply input signals and watch the o p waveforms Goto file menu and click new file goto other files tab and select vector waveform file option Device Design Files Software Files Other Files AHDL Include File Block Symbol File Chain Description File Hexadecimal Intel Format File Memory Initialization File Signal ap II File Tcl Script File Text File Vector Waveform File Cancel 50 ni logic P vt Ltd Pune USDP User Manual Step 10 Add the entity signals in the waveform window and apply different sets of value to check the functionality Save the file
32. rectifier terminal headers as due to high voltage you may get shock so please use rubber glove while handling the power module Stepper motor controller Power module has onboard transistor based stepper motor driver circuit Designers can interface their un polar stepper motor on the provided terminal header J P8 This circuit can drive motors of 12V 0 5 amps User can apply phase control signals to the stepper motor I P pins in proper sequence to run the stepper motor The sequence of signal will determine the motor direction and stepping mode Note Connectthe motor winding the proper sequence else the motor won t rotate and will keep on vibrating Source codes for Power Module FPGA Relay section Source code name relay vhd Pin lock file name relay ucf Stepper motor section Source code name stepper vhd Pin lock file name stepper ucf Note Take extensive care while handling the power module in high voltages as there may be chance of shock in case of improper handling Check your design before connecting with the power module from your instructor ni logic will nottake responsibility in case of any damages due to false design practice and improper handling 104 ni logic P vt Ltd Pune USDP User Manual Power Module Pin Detail Power module is independent of USDP baseboard and can me mapped to any of the 1 05 of the adaptors available Here by are the header details of the power module
33. signal pins high to turn ON the optical isolator transistor The emitter of optical transistors are been shorted together and name as IGND user has to use all O Ps with this common signal Designer has to make digital ground DGND amp IGND common if he is working with the same reference voltage levels The collector amp IGND of optical transistors are brought on the terminal header J P6 from where user can interface his logic IGBT A high current rating IGBT is provided onboard for motor control or high current based applications The IGBT pins are brought on the terminal header J 2 from where user can interface his logic As the triggering logic varies from application to application we have not given the circuit onboard and user has to design and interface his own triggering logic to drive the IGBT ON OFF Note While designing the triggering logic of IGBT use optical isolator in between the FPGA uC and IGBT Do not short the analog ground AGND amp digital ground DGND directly instead use a fuse in between both ground to protect from over flow of current in digital ground 103 ni logic P vt Ltd Pune USDP User Manual High current rectifier A High current rectifier is provided onboard which can be used for rectifying AC lines upto 10 Amps of current Designer can apply AC P to rectifier from its terminal header J P1 and get the rectified DC O P from terminal header J P 3 Note Take care while handling the
34. temperature control applications Only a temperature sensor has to be interfaced along with its signal conditioning unit SCU to ADC After the digitization of temperature values user can manipulate the values and control the process using FPGA or the microcontroller cards Modules Can be used card 89C51 card FPGA card General Purpose card ADC DAC Card and power module Motion Control USDP is ideal for robotics applications development As Stepper motors are widely used and plays vital role in robotics environment for implementing arms handles moving rotating mechanisms With the use of external power module USDP can prove good platform for motion control applications With onboard stepper motor controller circuit AC line step down transformer relays optically isolated outputs etc power module makes USDP as a complete system development platform Modules used card 89C51 card FPGA card General Purpose PCB card Power module AC line monitoring Motor Control USDP Power Module Infrared Communication USDP is designed to meet a variety of application needs with distinct advantages that enable the embedded system designer to easily add infrared wireless connectivity IRDA IC s can be easily assembled on General purpose and data communication can be achieved using the micro controller or FP GA CPLD Modules Can be used PIC card 89C51 card FPGA card General Purpose PCB card IRDA IC s FPGA
35. to indicate that a filter is carried out by using convolution rather than recursion HDL Hardware Description Language A synthetic computer based language used for the formal description of electronic circuits An HDL can describe a circuits operation its design and a set of tests to verify circuit operation through simulation The two most popular digital HDLs are VHDL and Verilog An analog HDL called AHDL is under development by many vendors HDLs make it easier to develop very large designs through formal software engineering methods that define ways to divide a large team project into smaller modules that can be implemented by individual team members Hardware Software Codesign The simultaneous development of product hardware and software This design approach is more difficult than a serial design which first develops the hardware and then the software that will run on the hardware but the benefit is a reduced time to market To develop software before hardware is ready software developers often create a behavioral model of the hardware which can run the software and thus prove its function Interrupt An input to a processor that signals the occurrence of an outside event the processor s response to an interrupt is to save the current machine state and execute a predefined subprogram The subprogram restores the machine state on exit and the processor continues in the original program Joint Test Action Group TAG The J oint Test Ac
36. uC 852201 RDA module USDP 14 ni logic P vt Ltd Pune USDP User Manual Access control system Today many applications are developed for security and access controlling The basic applications of access control can be developed and prototyped on USDP The basic model consists of keypad interface for password entering solonoid for door open amp close which can be replaced with relays here user display for welcome notes menus and messages and protocol for security maintenance Modules Can be used PIC card 89C51 card FPGA card General X C PCB card LCD Power module and keypad Relays Power Module 4x4 Keypad PC based applications Today most of the applications are having PC communication or control For communication with PC USDP provides both serial and parallel communication P arallel port connector is provided on FP GA cards which can used to communicate with PC from its parallel port Also every microcontroller is equipped with RS 232 communication port for serial communication with PC Hence USDP is worth getting product for such PC controlled application development Modules Can be used PIC card 89C51 card FPGA card Parallel Comm USDP 8051 microcontroller based applications USDP can give excellent support of development and implementation of microcontroller based application The user gets two top of the line microcontroller development cards based on 89c51RD2 and PIC 16F877 Using th
37. use the power supply supplied with the trainer only FPGA modules Insert the module vertically in the slots 2 Do nottouch the FPGA while handling the module as it may get damage due to static charge on your body 2 Do program the FPGA as per the Configuration chapter While stacking both FP GA modules do not make the same pin location bus as outputs Memory module 2 As the memory module shares the bus with PIC controller it is recommended not to use PIC controller while using memory module Power Electronics module If working on the high voltages then it is recommended to use gloves while handling module Keep the hands off the terminal blocks AC amp DC as you may get shock from it Do notexceed the ratings of devices else it may cause damage to them ADC DAC module Apply the analog signals in the range of specifications Stepdown the high voltage current signals 34 ni logic Pvt Ltd Pune USDP User Manual Chapter 8 Using EDA tools USDP can works on various technologies altogether The currently supported technologies are VLSI micro controller and DSP All these technologies have different design flows and software tools for development purposes For VLSI technology USDP works on Altera and Xilinx devices right now and RISC amp 89c51 controllers To work on the following provided devices this chapter will cover the design flow and methodology of EDA tools required for building applications on USD
38. used for his ease of use and enriched features All the 1 05 of controller have been brought on the edge connector and are connected with the FPGAs user can program the uC and use it with the FPGA The interrupt pins are brought on the separate headers which can be used to interface with the external world The module also contains on board RTC which user can use for his application Procedure for using module Write source code in C or assembly language in compiler Generate the HEX file Connectthe PIC parallel cable Turn on the USDP power supply Program the microcontroller using the PIC PRO programmer provided also use the 18V adaptor Remove the 18V adaptor after programming the PIC Configure the FPGA for microcontroller interface logic Reset the controller through FPGA Check the application wy N 5 55 535 559 59 C2 We have provided a sample program which runs message on the 7 segment display though the FPGA All the control is from PIC controller and the FPGA 15 working like a feed through circuit For further information on PIC 16F 877 kindly refer the datasheet provided along with the protoboard Source code for FPGA Source code name feed_PIC vhd Pin lock file name feed_PIC ucf Source code for PIC Source code name disp_pic c Programming file name disp_pic hex Note For further information on using compiler and PIC PRO software kindly refer the chapters Using EDA tools amp Configuration 95 n
39. 181 Da ki v Stop Processing Ctri Shift C e eE Analyze Current Eile courier New d 6517 start nig Eb Compilation Report Ctrl R pes Start Compilation amp Simulation 8 Device Design Files LL Software Files Start Simulation p ALL Other Files Simulation Debug E Simulation Report CtrieShift R i Bis er range to 7 address i ps Start Software Build Ctri Q ogic active low enable ae ae ogic active low enable fee ur logic active high enable out bit 7 downto 0 decoder o p active high end decoder architecture Behavioral of decoder is begin lt 00000001 sll add when eni O and en2 0 and en3 1 else others gt 0O Processing Total Initialization B Simulator Total Netlist Builder Simulator end Behavioral b Simulate 4 Quartus II c quartus demo decoder decoder decoder Compilation Report Fie Edit View Project Assignments Processing Tools Window Help lal x namja rce xempaBe 0 099 228 589i alx 6S SB Legal Notice Flow Summary Flow settings Flow Elapsed Time Analysis amp Synthesis Fitter Fitter Summary OEE Fitter Settings Fitter Device Options Fitter Equations EB Floorplan view Flow Status Successful Tue Oct
40. 21 00 11 23 2003 a Compiler Setting Name decoder 2 NEUE Top level Entity Name decoder 2 Family Assembler Assembler Summary Device 0 144 3 Assembler Settings Total logic elements 10 2880 1Z Assembler Generated Files Total pins 14 102 13Z Assembler Device Options decoder sof Total memory bits 0 40 960 0 8m Assembler Device Options decoder pof Total PLLs 0 1 0 5 Assembler Messages Sa Timing Analyzer am Timing Analyzer Settings Timing Analyzer Summary Minimum amp 3 Timing Analyzer Messages Cu Files Device Design Files CJ Software Files E Other Files Processing Total E Full Compilation Analysis amp Synthesis Fitter Assembler Timing Analyzer 54 nilogic Pvt Ltd Pune USDP User Manual Step 18 Now we need to program CPLD for this goto tools menu and click programmer Which will open the programmer the software will automatically add the programming file decoder pof In the opened window select the program configure option Now we need to select the programming hardware for which click the hardware tab on the top LHS of programming window 4 Quartus II c quartus demo decoder decoder decoder cdf 4 p laj xj File Edit View Project Assignments Processing Tools Window Help lal x 4 5
41. 4 LAO 87 LBO 69 LCO 58 LDO 45 7 Segments Display Enable Keypad Header segA 31 15 SLO 8 RLO 3 segB 30 DISP2 16 511 13 RL1 11 segC 29 DISP3 17 SL2 9 RL2 7 segD 28 DISP4 18 SL3 14 RL3 12 segE 27 segF 26 segG 25 segDP 24 Parallel Port Connector DB 25 Parl 205 10 193 2 203 11 192 Par3 202 12 191 Par4 200 Par13 190 Par5 199 Parl4 189 Par6 198 Parl5 187 Par7 197 Parl6 186 8 196 Parl7 179 Par9 195 Pin 18 25 of DB 25 connector are ground Note Both the FPGAs share the above 1 05 User has to take care that no two pins are defined as output as in that case there would be short on the bus and may damage FPGA 1 05 User can define the following combination of FPGAs shared 1 05 FPGA1 FPGA2 Input Input Allowed Output Input Allowed Input Output Allowed Output Output Notallowed 86 ni logic Pvt Ltd Pune USDP User Manual 4 ADC DAC Module The ADC DAC module provided along with the USDP has 4 channel ADC 2 channel DAC on board This module is directly connected to the FP GAs and does nothave direct connections with other modules To use this module user has to design ADC DAC controller in the FPGA to get the da
42. 7 a e LL a gt LL a gt us Jes Irs log c Pvt Ltd ADC DAC Pune ni ADC DAC Card Board Ident 89 ni logic Pvt Ltd Pune USDP User Manual MAX154 ADC Pin out our1 1 e 18 OUT2 2 Veer IN GND Vpp 1 MSB 4 Apz544A BIT 12 LSB BIT2 5 BIT 11 BIT 3 6 BIT 10 BIT 4 BIT 9 BIT 5 8 BIT 8 BIT 6 9 BIT 7 ADC7541A DAC Pin out 90 ni logic Pvt Ltd Pune USDP User Manual 5 89c51RD2 Module This module is based on renowned industry standard 8051 architecture based controller The uC is 89c51RD2 controller from Philips which is In System Programmable ISP All the 1 05 have been brought on the edge connector and are connected with the FPGAs user can program the uC and use it with the FPGA The timer amp interrupt pins are brought on the separate headers which can be used to interface with the external world The module also contains on board RTC and EEPROM which user can use for his application Procedure for using module Write source code in C or assembly language in keil compiler or some other compiler Generate the HEX file Connect the serial cable Turn on the USDP power supply Program the microcontroller using the Flash Magic programmer Configure the FPGA for microcontroller interface logic Reset the controller through FPGA Check the application 3 ON N 0623 02 5 5 9 C2 We have provided
43. A hardware description language developed by Gateway Design Automation now partof Cadence in the 1980s which became very popular with ASIC and IC designers VHDL VHSIC Hardware Description Language A hardware description language developed in the 1980s by IBM Texas Instruments and Intermetrics under US government contract for the Department of Defense s VHSIC Very High Speed Integrated Circuit program VHDL enjoys a growing popularity with ASIC designers as VHDL development tools mature 119 ni logic P vt Ltd Pune USDP User Manual Chapter 15 Troubleshooting Errors while programming FPGA There may be errors while programming FPGA this may be due to many reasons kindly check the following Steps to recover the error FPGA modules should be properly inserted Check the jumper settings of FPGA module Check the programming mode selection settings See that the programming cable is properly inserted The PLD amp slot selector cards are in proper position Ground the clock GCK0 I P during programming use it after programming the FPGA In case of Xilinx open the IMPACT programmer with selected programming mode only The parallel portof PC should be in ECP EPP mode else there would be connection errors NI YY yy yy C2 Errors while programming 89c51 There may be errors while programming 89c51 kindly check the following steps to recover the error Module should be properly inserted 2 The RS 232 programming cable
44. Ar A Complete Design Platform User Manual Version 2 ni logic Pvt Ltd 25 B 5 Bandal Complex Bhusari Colony Paud Road Kothrud Pune 411 038 Maharashtra India Ph 91 20 5286948 www ni2designs com USDP User Manual Table of Contents l Introduction a Introduction to VLSI and PLDs b Basics about kits and required features 2 AboutUSDP a Productintroduction b ProductFeatures Technical specification of all modules 3 ProductOverview applications and examples 4 System Diagrams a USDP board connectivity b 1 0 Connections C Add on connector detail 5 Pin Assignments a FPGA pin assignment b Add on Module pin assignment 6 Jumper and Headers P in description and settings 7 Using EDA tools a PLD Design Flow 89c51 controller design flow PIC controller design flow Using Xilinx ISE software Using Altera Quartus Il software Using keil compiler 8 Precautions 9 Configuration a Configuring Xilinx amp Altera Devices b Slotselection Programming Modes d Jumper setting for mode selection e Programming 89c51RD2 microcontroller f Programming PIC16F877 controller Using Add on Modules a Xilinx FPGA Module Altera FPGA Module ADC DAC Module 89c51RD2 Module PIC uC Module SRAM Memory Card Power Electronics Module h General Purpose PCB 11 Designing Application on USDP using provided modules 12 An application implementation on USDP 13 Sample codes 14 Glossar
45. Bytes X 8 51 8xC51RB2 8 519 2 8xC5IRC2 as SAASB45HL SAA5647HL A anonn Bre S 08 Step 4 Click ok on the above window and the project would be created Now the user has to add or create the Source code for the controller For example for now designer can use the source code provided along with the USDP code examples So right click on Source group and click add files to group demo pVision2 File Edit View Project Debug Peripherals TA Svcs SCS Window TIT E er m Select Device For Target Target 15 Options for Group Source Group 1 Open File Rebuild target Ej Build target Translate File Stop build Targets Groups Files Remove Group Source Group 1 and it s Files 58 ni logic P vt Ltd Pune USDP User Manual keil demo uYision2 Project Debug Peripherals Tools Svcs Window Heb josag relse o ae eee Files to Group Source Group 1 Target 1 Cx Source Group 1 Look in C3 Keil Demo z er EM File name serial transmit Files of type c Source file zi Chose Bre S Us Step 6 User can have a look on the demo source code which takes data from Port 0 and sends it serially to PC The source code is in C language users can also use assembly code for designing demo 2 E
46. D RAO ANO 2 4 RB6 PGC RA1 AN1 3 RB5 RA2 AN2 VREF 4 gt RB4 RA3 AN3 VREF 5 RB3 PGM RAA TOCKI 6 RB2 RAS AN4 SS 7 er 4 RB1 REO RD AN5 8 N RBO INT RE1ANRIANG 0 J 4 voo RE2 CS AN7 4 vss VDD 7 TE 4 RD7 PSP7 5 co 4 RD6 PSP6 OSC1 CLKIN 7 gt gt RD5 PSP5 OSC2 CLKOUT 7 a gt RD4 PSP4 RCO T1OSO T1CKI C RC7 RX DT RC1 T1OSI CCP2 4 RC6 TX CK RC2 CCP1 11 RC5 SDO RC3 SCK SCL 4 RC4 SDI SDA RDO PSPO 4 RD3 PSP3 RD1 PSP1 20 4 RD2 PSP2 PIC 16F877 Controller Pin out ni logic P vt Ltd Pune USDP User Manual 7 SRAM Memory Card User gets SRAM memory module along with the USDP This has the total 2MB of data storage The SRAM module contains four 512K x 8 memory chips which user can use according to his application requirement All the 1 05 of memories are brought on the edge connector sharing with the PIC slot bus This creates choice for user for inserting a memory card or PIC card in any 3 of the slots User should not insert both the SRAM module and PIC module together on the board as there may be conflict on the bus SRAM module contains on board address decoder for generatin
47. DP for power electronics based applications The module is be divided in 6 sections Relays 2 Step down transformer Isolated O Ps 2 IGBT High current rectifier Stepper motor controller We would describe individual section usage further designer can join the parts together depending on their application Relay section Two optically isolated relays have been provided onboard User can turn relays ON by applying logic high on the given control I P pins The relay pins are taken out on terminal headers from where user can interface his circuit for mechanical switch operation For example user can connect light bulb heater buzzer etc for visual demonstration Stepdown transformer A divide by 100 transformer is been provided onboard which user can use for line monitoring applications User can connect the AC line to its I P header J P4 which in turn get a divided by 100 O P voltage on its secondary winding header J P5 The secondary winding is center tapped that means user will get the divide by 100 voltage on the outer pins of winding the center tap can be used as a reference point User can connect this divided O P voltage to ADC and use the digitized signal for the processing of AC line signal For example designer can use for frequency measurement of AC line voltage measurement line monitoring etc applications Isolated O Ps Five optically isolated O Ps are provided onboard User can drive the I P
48. EDA tools Tool type Tool name Design entry synthesis lt None gt Simulation lt None gt Timing analysis lt None gt Board level lt None gt Formal verification lt None gt Resynthesis lt None gt r Tool settings Tool type Design entry synthesis Tool name lt None gt 71 Run this tool automatically ta synthesize the current design Settings Adyanced Finish Cancel Step 3 Select ACEX1K device family in the next window Click next New Project Wizard Device Family page 4 of 6 43 x Which device family do you wish to target Do you want to assign a specific device Yes No want to allow the Compiler to choose a device Back Net Finish Cancel 47 ni logic P vt Ltd Pune USDP User Manual New Project Wizard Select a Target Device page 5 of 6 Use the Filters settings to control the devices that are displayed in the Available devices list Select a device in the list and click Next to continue Available devices EPIK301C144 3 n 1 50 256 1 Filters EP1K50F1256 2 Pin count Speed grade EP1K50FC484 3 Voltage 25V EP1K5001208 2 EP1K500C208 3 EPIK50TC144 1 EPIK50TC144 2 rn1wchT 1447 Back Finish Cancel Step 5 Click Finish And the new project would be created Now we need to make and add new design file in the projec
49. IC Testsidecoder bit done Device 1 selected Device 1 selected 1 Loading file F USDP Demo CodesWPIC Testsidecoder bit done Device 1 selected E For Help press F1 Configuration Mode Boundary Scan Parale PC3 P Step 17 Programming would start after clicking OK if the programming is successful then the message would display on the screen 2 untitled Configuration Mode iMPACT File Edit Mode Operations Operations Options Output View Help Dc MSs zr cu CE E S C Sj V Boundary Scan Slave Serial Select Map Desktop Configuration 25200 decoder bit TDO Programming Succeeded PROGRESS END End Operation 21 Elapsed 4 sec Device 1 selected PROGRESS_START Starting Operation Validating chain Boundary scan chain validated successfully 1 Programming device done 11 Programmed successfully PROGRESS_END End Operation Elapsed time 9 sec L Now check the functionality on the board and verify it by applying diffe rent inputs 45 nilogic Pvt Ltd Pune USDP User Manual Design Flow for Quartus ll series of software of Altera Install Quartus Il version 3 0 amp above software on your machine the supported platforms are windows NT XP 2000 We take the same decoder example for implementing on the Altera ACEX1K FPGA Step 1 Start Quartus Il version 3 0 amp above software Step 2 For new project c
50. IEEE STD_LOGIC_1164 ALL use IEEE STD_LOGIC_ARITH ALL use IEEE 5TD_LOGIC_UNSIGNED ALL entity decoder is Port Add in integer range 0 to 7 address i ps enl in std logic active low enable 9 en2 in std_logic active low enable 10 en3 in std logic active high enable 11 Y out bit vector 7 downto 0 decoder active high 12 end decoder 13 14 architecture Behavioral of decoder is 15 48 begin 17 J Design Entry Utilities 18 Y lt 00000001 sll add when enl 0 and 2 0 and en3 l else User Constraints 18 others gt 0 HQ Synthesize ay Implement Design E end Behavioral a Generate Programming File aut Updating B Process View kx Completed process Generate Post Place amp Route Static Timing Place amp Route Module decoder PAR command line par w ol 2 t 42 decoder_map ned decoder ncd decoder pcf PAR completed successfully Find in Files Step 11 In the opened window go to startup options and select J TAG clock in FPGA Start Up Clock option This in turn will generate the programming file for J TAG mode programming To program the FPGA in Slave Serial mode user has to select CCLK clock instead of J TAG Clock in the startup options Process Properties General Options Configuration options Startup options Readback options Property Name ied Internal Done Pipe Enable Outputs Output Events 00000
51. L3 8 lt unsi static volatile bit TEST 8 lt unsi UINT count bit secflag UCHAR digit UINT digbuf 4 UCHAR 1141 4 41 void inithw lt void gt lt ADCON1 8x06 INTCON 8x88 OPTION 8x88 TRISC 0 0 TRISD 8x88 TMRiH TIMER1_RELOADH TMRiL TIMER1_RELOADL Line 27132 Col 1 Insert mode Users can now use this HEX code to program the PIC software tility t elp controller using provided PROGPIC programming ni logic Pvt Ltd Pune USDP User Manual Chapter 9 Configuration This chapter covers the configuration process required for the programming configuration of FPGAs and micro controllers USDP supports multiple FPGA stacking with the PLD connectors Slotl and 5100 This gives the flexibility for implementing multiple FPGA based designs or users can also use FPGA independently Users can use the following combination of FPGAS Stacking Options Slot 1 Slot 2 Choice 1 Xilinx Choice 2 Altera Choice 3 Xilinx Xilinx Choice 4 Altera Altera Choice 5 Xilinx Altera Note Both the PLD slots share the bus users has to take care about the pin mode while using the both slots together No two pins should be output else there may be chances of hardware short Till now the user is familiar with the Xilinx and Altera EDA tools for development of HDL based designs Now further m
52. OM Port open Verify after programming Set Security Bit 1 Fill unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 v Execute Bclks cycle n Line training classes for microcontrollers and embedded networking and Internetworking www esacademy com fag classes In case there is problem in connecting the device then change the T1 amp T2 values by 50 amp 100 respectively Step 4 In the main window for the 1st section use the following settings COM port COMI Baud rate 9600 Device 89C51RD2Hxx Oscillator Freq MHz 11 0592 Flash Magic E Ble xj File ISP Options Help COM Port com 1 0 0 0000 0 1 Erase block 1 0 2000 0 Baud Rate 9600 Erase block 2 0x4000 0 7FFF Erase block 3 0 8000 0 89C51AD2Hxx 89 61 2 Erase block 4 0 00 0 88C51RB2Hxx 89051 RC2Hxx Device Oscillator Freg MHz 3 Hex File Erase all Flash Security Browse Last Modified 33C658 Size Unknown Verify after programming Set Security Bit 1 Fil unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 Execute 8clks cycle Microcontrollers from Philips Semiconductors Main web page at nilogic Pvt Ltd Pune USDP User Manual Step 5 In the 2 4 section select the number of bl
53. P We will cover the design flow following technologies PLD design flow Micro controller design flow 35 ni logic Pvt Ltd Pune USDP User Manual Design Entry Implementation PLD Design Flow HDL Verilog VHDL Hardware Description Language Very High speed Integrated circuit HDL Verilog having C based constructs Functional Verification Functional simulation of the design No timings are considered Process for converting design specifications into gate level netlist Needs synthesis library containing target technology information Combined name for processes like for translation floorplanning mapping place amp route bit file generation For locking input and output signal to the particular pins of the device user must write UC F User Constraint File before implementation Output of implementation is BIT for FPGA and J ED file for CPLD which can be directly program into the target device Dynamic timing analysis Functional simulation of the design running it on the desired operating frequency Timings are considered This is the process by which user can physically download the design programming files from P C to target device using programming cable To program CPLD select Boundary scan JTAG mode To program FPGA select Boundary scan slave serial mode or Master serial Mode ni logic P vt Ltd Pune USDP User Manual Microcontroller Design Flow Source Code High lev
54. PGA based product designs training and for experimental purposes All of them posses features towards programming of FPGAs and just few user input output facilities Very few protoboards offer a complete solution for integration of various user modules with ease With the advancement in the system requirements and specifications designers are finding difficulty in development of FPGA based designs As the FPGA designs accounts the integration of dense memories analog interface DSP microprocessors and microcontrollers many vendors are unable to provide a platform where a designer can integrate all kinds of modules with the FPGA With increase in use and demand of FPGAs in the communication telecom power electronics motion control and educational industries the protoboards are in huge demand thus ni logic took initiative to provide an excellent prototyping platform for these industries Our R amp D arm ni2 designs have come out with the complete solution towards the problems of trainer kits in DSP VLSI and Microprocessors ni2 designs have designed prototyping protoboards with the concept of backplane interface of various modules giving a complete solution for the platform integration of VLSI DSP microprocessors and power electronics applications With this product ni logic is aiming to give the industry a product that can be used in various applications thus solving the problems of designers for high speed designs and platform integrati
55. Progre Processing Total ER pes colair poorne Initialization 00 Ej Timing Closure Floorplan E Simulator Tota BM 2 chip Ector EB 9 LogicLockRegions Window amp Import LogicLock Regions g Export LogicLock Regions 51 ni logic P vt Ltd Pune USDP User Manual Step 12 Now goto simulator setting then to mode and in the right hand side window select the simulation mode to Functional Settings x Category Files amp Directories Add Remove User Libraries Toolset Directories HDL Input Settings VHDL Input Verilog HDL Input EDA Tool Settings Default Logic Option Settings Default Parameter Settings Timing Settings Clocks Other Requirements amp Options Timing Analysis Reporting Select the simulation mode Changes apply to Simulator settings decoder Simulation mode Timing Description Functional fully compiled netlist that includes actual timing information You can use Tcl commands and scripts to control simulation and to provide vector stimuli You can also provide vector stimuli in a Vector Waveform File vwf a text based Vector File vec or a Power Input File pwf This type of simulation also allows you to check setup and hold times detect glitches and check simulation coverage the ratio of nodes simulated to the total number of nodes in the design C
56. Pune
57. REF interface using DB25 connector Parallel port interface Easily accessible user I Os 3 on board 120 pin connector for Add on card interface Stacking of maximum three Add on card modules possible of different technologies 89c51 Microcontroller card for traditional 8051 applications with ISP support PIC Microcontroller card for industrial based applications Memory Card for data intensive applications High performance ADC DAC add on card Power module for motion control and electro mechanical applications Intensive user manual support with various examples and source codes And many more ni logic P vt Ltd Pune USDP User Manual Backplane features Supports interface with dual daughter PLD cards Supports FPGAs from reputed PLD vendors like Xilinx Altera etc Stacking of maximum two PLD daughter cards possible with on board chaining circuit 3 PCI connector based application specific add on cards 64 bit bus sharing between application add on cards and PLD daughter cards 77 bit bus sharing between PLD daughter cards 32 Digital I Ps and O Ps each can be configured as input or output giving flexibility to designers On board system reset circuit Four seven segment Multiplexed display 4x4 switch matrix keyboard interface header On board crystal oscillator socket user can select his desired oscillators High performance backplane PCB 2 55 53 023 023 5 5 03 0639 9 PLD Daughter cards Available Different
58. Spartan ll A17 DO 92 87 18 01 90 86 19 04 96 94 20 05 95 90 21 08 101 98 22 D9 100 97 23 EN1 111 102 A24 2 104 101 25 DBO 115 111 A26 DB1 114 110 27 DB4 121 115 A28 DB5 120 114 A29 INT 127 122 A30 RDY 126 121 Acex Spartan ll Acex Spartan ll B17 D2 89 3 B18 D3 88 4 B19 D6 94 89 B20 D7 93 88 B21 D10 99 96 B22 D11 97 95 23 0 103 100 24 Al 102 99 B25 DB2 113 109 B26 DB3 112 108 B27 DB6 119 113 B28 DB7 116 112 B29 CS 125 120 B30 RD 122 119 ADC header Detail DAC OP 1 Pinl DAC Channel 1 Pin2 DAC Channel 2 Pin3 Ground ADC IP 2 Pinl ADC Channel 1 Pin2 ADC Channel2 Pin3 ADC Channel 3 Pin 4 ADC Channel 4 Pin5 Ground R efer the device datasheet for pin description and functioning ni logic P vt Ltd Pune USDP User Manual 89c51 Module Pin Detail Acex Spartan ll Acex Spartan ll A31 ADO 133 127 A32 AD2 132 126 A33 AD4 139 134 A34 AD6 136 133 A35 A8 143 139 A36 A10 142 138 A37 A12 149 146 A38 A14 148 142 A39 PORT1 1 159 150 A40 PORT1 3 158 149 41 PORT1 5 163 163 42 PORT1 7 162 162 A43 INTO 168 167 A44 167 166 45 ALE 173 174 A46 FRST 172 173 Acex Spartan
59. UT p59 N A UTPUT p34 JTPUT p83 UTPUT 82 NIA JTPUT pat N A UTPUT p75 JTPLIT p74 UTPUT p73 UTPUT pni Pad Groups 100 Configuration Options GroupName Create Group 2 Pad to Setup Prohibit 1 0 Locations Select Group X Clock to Pad INET add lt 1 gt LOC p69 NET add lt 0 gt LOC p70 INET en3 LOC p59 INET y lt 0 gt LOC p84 UCF Constraints read write UCF Constraints read only Source Constraints read only For Help press F1 Step 9 Save the UCF file and come back to project navigator Now selecting the decoder design file run the synthesis process there after Implementation which in turn will place and route the design on the target FPGA Project Navigator it_test_projects USDP_Demo decoder decoder npl decoder File Edit View Project Source Process Window gt lal x psug egzs esmjmxmete ee cm 49 9 5 m library IEEE Sources in Project use IEEE STD LOGIC 1164 ALL 5 decoder use IEEE STD LOGIC ARITH ALL sc2s200 5pq208 XST VHDL use IEEE STD LOGIC UNSIGNED ALL decoder vi decoder ucf ucf entity decoder is Port Add in integer range 0 to 7 address i ps enl in std logic active low enable 9 en2 in std logic active low enable 10 en3 in std logic active high enable 11 out
60. ________ USDP User Manual PROM BYPASS J 3 amp J 4 To Chain PROM To Bypass PROM Short 1 2 Short 2 3 Shorting 1 2 will bring the PROM in chain with FPGA In this case user can configure the PROM and use for programming file storage Shorting 2 3 will remove the PROM from chain and only FPGA would be connected to programming port Global Clock Buffers Pin 1 GCK2 GCK3 Pin2 GND GND Note These buffers are extra from GCKO DB 25 connector Regulator d FPGA 2 3 Mode selection switch TDI TMs PROMBYPASS PROM Configuration Reset key CONFIGURATION RESET Xilinx FPGA Adaptor Board Ident a nilogic Pvt Ltd Pune USDP User Manual Spartan Ill FPGA Pin detail Device XC2Sxx PQ208 Clock and Reset Clock GCKO 80 GCK2 182 GCK3 185 Reset 5 Note Resetis active LOW Configurable 1 05 LA7 34 LB7 45 LC7 60 LD7 71 LAG 35 LB6 46 LC6 61 LD6 73 LA5 36 LB5 47 LC5 62 LD5 74 LA4 37 LB4 48 LC4 63 LD4 75 LA3 41 LB3 49 LC3 67 LD3 81 LA2 42 LB2 57 LC2 68 LD2 82 LA1 43 LB1 58 LC1 69 LD1 83 LAO 44 LBO 59 LCO 70 LDO 84 7 Segments Display Enable Keypad Header segA 33
61. a sample program which takes data from FP GA on one port and sends it serially through the RS 232 port For further information on 89c51RD2 kindly refer the datasheet provided along with the protoboard Source code for FPGA Source code name feed_89c51 vhd Pin lock file name feed 89c51 ucf Source code for 89c51 Source code name serial transmit c Programming file name serial transmit hex Note For further information on using Keil compiler and Flash Magic software kindly refer the chapters Using EDA tools amp Configuration 91 ni logic P vt Ltd Pune 89c51 Module Pin Detail Acex Spartan ll Acex Spartan ll A31 ADO 133 127 A32 AD2 132 126 A33 AD4 139 134 A34 AD6 136 133 A35 A8 143 139 A36 A10 142 138 A37 A12 149 146 A38 A14 148 142 A39 PORT1 1 159 150 A40 PORT1 3 158 149 41 PORT1 5 163 163 42 PORT1 7 162 162 43 INTO 168 167 A44 167 166 45 ALE 173 174 A46 FRST 172 173 Acex Spartan ll Acex Spartan ll B31 AD1 131 125 B32 AD3 128 123 B33 AD5 133 132 B34 AD7 134 129 B35 A9 141 136 B36 All 140 135 B37 13 147 141 B38 A15 144 140 B39 PORT1 2 157 148 40 PORT1 4 150 147 41 PORTI 6 161 152 B42 PORT1 8 160 151 B43 TO 166 165 44 T1 164 164 B45 RD 51 170 172 B46 WR 51 169 168 J umper amp Heade
62. aillSWITCH uv2 3 2 if RI RI 0 void init_hw void TMOD 0x21 0x92 1001 0010 SCON 0x50 0101 0000 TLO TIMER_RELOAD Fil DFTNAN B Files of This will generate the HEX file in the project folder which you can use to program the controller using the provided Flash Magic programming software 61 nilogic Pvt Ltd Pune USDP User Manual Using PIC C Lite Compiler Designers can use PIC C Lite compiler from HI TECH Software one of the compilers available in market PIC C Lite is a DOS based cross compiler supporting Microchip PIC microcontrollers Compiler support the source codes written in C and assembly languages and works on Win 98 2000 platforms The choice of compiler is solely dependent on the user they can also use the compilers available from other vendors like MPLAB or others For starting up with USDP we have made a design flow guide for using the PIC C Lite compiler but for more information users can surf the help index of the compiler Install the PIC C Lite compiler from provided CD ROM you can use the evaluation version at start up which Supports the program code upto 2KB which is sufficient for small development purposes Step 1 Run the PIC C Lite compiler EXE which in turn will open the compiler o ile dit Options Compile ake un tilit el untitled Insert C mode 4 SN NA S S ACCC HI
63. al Optimization E o ile dit Options Compile ake un tilit el untitled Line Select compiler optimizations Select optimizations X Global optimization 1 Peephole optimization 1 Assembler optimization D0 Global optimization level 1 95 8 Full optimization F gt TTG Cancel Esc gt Help F1 gt Click here or press Enter when done 1 1 Col 1 Insert C mode 18 T 4 Step 7 Now user has to select mapping and symbol file option User can select the options according to his requirement or select for source level debug info untitled Set map and symbol file options X Source level debug info F4 1 Sort map by address F5 1 Suppress local symbols F6 1 Fake local symbols F7 Click here or press Enter when done Cancel Esc gt ni logic Pvt Ltd Pune USDP User Manual Step 8 Now add the source files in the project Right now add the provided disp_pic c source file provided along with the USDP Browse to the folder by pressing FILE option and add the said source file in the list TL PITIES lt 0 ile dit Options Compile tilit el untitled t Source Files a 1 DONE ESC gt DELETE F gt INSERT Fig gt ABS 7REL F2 gt gt FILE F8 gt YANK 1 9 gt PUT Ctrl F1 New entry Pathnames relative 4 Step 9 Now the project has been created User can edit the
64. ame 55 control ucf Source code for 89c51 Source code name access control c Header file name LCD_routine c Programming file name access_control hex Note Save the LCD routine c file in your project folder while compiling the access_control c file 113 ni logic P vt Ltd Pune USDP User Manual Chapter 13 Sample Codes Here is the list of sample codes provided along with the USDP ADC DAC Module Code description This code works as feed through circuit between the ADC and DAC The data coming from ADC is stored in latch and given to DAC for reconstruction of signal Working with code User has to insert ADC DAC module connect the analog signal on the ADC1 channel and CRO probe to DAC1 channel user can modify the code for channel selection Program the Xilinx Altera FPGA module for the given VHDL source code and pin constraint file After programming the FPGA check the waveforms on the CRO which would be nearly the same analog signal the difference would be due to sampling interval and amplitude difference due to resolution of ADC and DAC Source code for FPGA Source code name ADC DAC feed vhd Pin lock file name ADC DAC feed ucf 89c51 Module Code description The 89 51 source code takes data from PORTO and transmits it to serially to PC whenever there is change on the port data Working with code Program the 89c51 with the given HEX file there after program the FPGA with the provided feed through cir
65. are Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window oi TCR Available Hardware type ByteBlasterMV or ByteBlaster II 7 Hardw Port LPT1 Y EE Processing Total El Full Compilation 100 Analysis amp Synthesis Fitter 100 Assembler 100 Timing Analyzer 55 ni logic P vt Ltd Pune USDP User Manual Quartus c quartus demo decoder decoder decoder cdf File Edit View Project Assignments Processing Tools Window Help l x ETA EEr Hardware ByteBlaster Poges 0 21 Files Device Design Files Software Files E Other Files 1 oldecoderldecoder sof EP1K50T144 00011 00 00000071 Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware No Hardware Available hardware items Select Hardware Add Hardware Remove Hardware bh e gt BREEU XE t E Processing Total B Full Compilation Analysis amp Synthesis Fitter Assembler Timing Analyzer
66. ate Logic Pvt Ltd ni2 Designs Almighty Kit Keil Demo serial_transmit c 56 Stop build m 1 E ni Logic Pvt Ltd ni2 DesignslAlmighty Kit Keil Demolkeil demo uv2 2 CAWeilishaillSWITCH uv2 3 C Keil serial Uv2 if RI RI 0 void init hw void TMOD 0 21 TE 0x92 1001 0010 SCON 0 50 0101 0000 TLO TIMER_RELOAD THO TIMFD DFTNAN 55 Step 8 In the opened window go to target tab and in the window set the Xtal frequency as 11 0592 MHz options for Target zx Target Output Listing c51 A51 BL51 Locate BL51 Misc Debug Philips 8xC51RD2 Xtal MHz fi 1 0592 Use On chip ROM 0x0 OxFFFF Memory Model 5 variables in DATA 7 Code Rom Size Use multiple DPTR registers perating system Use On chip XRAM 00 0 2 r ff chip Code memory Off chip Xdata memory Start Size Start Size Eprom 1 Ram Eprom ia Ram z z Code Banking Start End far memory type support Banks 2 71 Bank Area 00000 040000 Save address tension SER interrupts Cancel Defaults Pe nilogic Pvt Ltd Pune USDP User Manual Step 9 Now goto output tab and set the name of executable file as serial transmit set the option create executable and set create HEX file option Finally click OK on the bottom side and com
67. ation We have provided a sample program which implements the hardware of 3 8 decoder IC 74xx238 which is active high decoder with 3 enable signals Here is the procedure for using the above code with this FP GA module Procedure for using module Write source code in VHDL Verilog using the Xilinx ISE series software Pin lock the entity 1 05 with configurable 1 05 Run the FPGA design flow from synthesis to implementation of design on FPGA Set the programming mode J TAG or slave serial in generate programming file option Generate the BIT file Insertthe FPGA module on slot 1 or slot 2 Setthe PROM bypass jumpers to position 2 3 Setthe programming mode in J TAG or slave serial Setthe jumper position of configurable 1 05 for input or output for e ntity pins Connectthe programming cable Turn on the USDP power supply Run the programming tool impact Program the FPGA Check the application NON lt 5 lt 5 023 023 0620 0620 062 yy yy C2 Source code for FPGA Source code name decoder vhd Pin lock file name decoder ucf Note For further information on Xilinx S partan Il FPGAs kindly refer the device datasheet umper Settings Programming Mode selection Switch U7 Modes 0 M1 M2 J TAG 1 0 1 Slave Serial 1 1 1 Master Serial 0 0 0 Mode selection jumpers J P4 J P5 J P6 J P7 Serial JTAG Short 1 2 Short 2 3 81 ni logic Pvt Ltd Pune _
68. avioral Bee Ooo enl in std logic active low enable en2 in std logic active low enable en3 in std logic active high enable high JHDPARSE VHDL Verilog Parser ISE 5 11 Copyright c 1995 2002 Xilinx Inc All rights reserved Scanning decoder yhd Scanning decoder vhd Writing decoder jhd JHDPARSE complete 0 errors 0 warnings 39 ni logic P vt Ltd Pune USDP User Manual Step 6 Create new source file for implementation constraint file Name it decoder_UCF and associate with the corresponding design file Schematic File Name VHDL Package decoder ucf VHDL Test Bench BMM File Location MEM File Implementation Constraints File JE kittest_projects USDP_Der e State Diagram Add to project cot _ Step 7 To assign the pin location of the design entity open the UCF file which in turn will open the constraint editor where we have to lock the 1 05 of design to a particular pin number e FP Project Navigator E kit test projects USDP Demo decoder decoder npl decoder jaj File Edit View Project Source Process Window Help 2 la xj 00 6 _4 E uuu 2 use IEEE STD LOGIC 1164 ALL decoder 3 use IEEE STD LOGIC ARITH ALL 5 3 xc2s200 5pq208 XST VHDL 4 use IEEE STD LOGIC UNSIGNED ALL Ei V decoder decoder vhd 5 entity de
69. bit vector 7 downto 0 decoder o p active high 12 end decoder 13 TR Module View Dur ven 14 architecture Behavioral of decoder is 15 16 begin 17 Design Entry Utilities 18 Y lt 00000001 sll add when enl 0 and en2 0 and en3 1 else J User Constraints is others gt 0 Cof Synthesize Qe Implement Design a Generate Programming File end Behavioral decoder Completed process Generate Post Place amp Route Static Timing Place amp Route Module decoder PAR command line par w ol 2 E decoder map ncd decoder ncd decoder pcf P R completed successfully 41 ni logic P vt Ltd Pune USDP User Manual Step 10 Now we need to generate the programming file to configure the FPGA The Xilinx FPGA supports J TAG Slave serial and Master serial through PROM for configuration User has to set proper mode during the programming file generation else FPGA won t be configured For this rightclick on the Generate Programming File option and click properties on the opened menu project Navigator E kit_test_projects USDP_Demo decoder decoder npl decoder m8 X File Edit Project Source Process Window Help 8 x PEE FE decoder B E xc2s200 5pq208 XST VHDL E decoder decoder vhd U decoder ucf ucf aid AHHH library IEEE use
70. coder New Source Port Add in integer range 0 to 7 address i ps Add Source Insert enl in std logic active low enable Add Copy of Source Shift Insert en2 in std logic active low enable Remove Delete en3 in std logic active high enable y out bit vector 7 downto 0 decoder o p active high Move to Library ttt ven Se ew Toggle Paths Properties end decoder architecture Behavioral of decoder is begin Processes for Current Source User Constraints Y lt 00000001 sll add when 1 0 and en2 0 and en3 1 else 19 others gt 0 end Behavioral Process View JHDPARSE VHDL Verilog Parser ISE 5 11 Copyright 1995 2002 Xilinx Inc All rights reserved Scanning decoder vhd Scanning decoder vhd Writing decoder jhd JHDPARSE complete 0 errors varnings Open the selected source 22 Col 35 EI 40 ni logic P vt Ltd Pune USDP User Manual Step 8 Once the constraint editor is opened goto ports tab and assign the pins by referring the Pin assignment chapter Eg net add lt 0 gt loc 84 36 Xilinx Constraints Editor Ports decoder ngd decoder ucf ucf File Edit View Window Help x al 2e E I INPUT p68 Ni INPUT p57 NIA INPUT p58 INP
71. cuit between switch and 89c51 After programming FPGA change the position of LD7 to LDO to observe the changes on the serial port of PC To the read he data from serial port of PC users can write a program in C or can use the COM port reader software provided along with USDP Source code for FPGA Source code name feed 89c51 vhd Pin lock file name feed_89c51 ucf Source code for 89c51 Source code name serial_transmit c Programming file name serial transmit hex PIC Module Code description This source code has a message displaying program This displays HI lam USDP on the 7 segment displays Users can use this code for their reference or modify according to their requirement 114 ni logic P vt Ltd Pune USDP User Manual Working with code All the PIC 1 05 are shared with the LEDs also so remove all the jumpers of switches so that there is no conflict after programming the controller Now Program the PIC microcontroller using the provided programmer software Use the HEX file provided with the USDP There after program the FPGA with the provided feed through circuit VHDL code This VHDL code acts like the feed through between the reset switch and the 7 segment displays After programming the FPGA reset the controller and check the message display on the 7 segment displays Note As the memory module also shares the same bus with PIC so remove the memory module while using the PIC module Source code for FPGA So
72. d digital logic to process the data at high speed and power electronics components to control high voltage current peripherals Master Digital Logic Communication Interface Microprocessor Microcontroller FPGAs CPLDs Serial parallel high speed fiber communication Analog Circuitry Power Electronics Memory Sensors Buffers amplifiers SCRS optical isolators SRAM FLASH DRAM ADC DAC relays IGBT Block diagram of electronic system With the above basic components designer can develop an electronic system for any application More or less few components can be added or removed but with the today s market scenario and product requirement designers need the above system blocks to be in their system Now we need to see that what are the design steps through which a system passes before getting into the market or its deployment Design Flow steps Finalize the specifications of system hardware and software Prepare the schematic diagram of hardware Write the software program for microcontroller microprocessor Design the digital logic hardware in HDL for FPGA CPLD 12 Prototype system schematic nilogic Pvt Ltd Pune USDP User Manual Test the hardware with the specifications check the microcontroller microprocessor programs with hardware 0 Design printed circuit board PCB of schematic y y The above flow contains the basic steps which are majorly followed in industry Loo
73. dded and VLSI Suitable for both Advanced and Beginner Courses Trainings and workshops Easy customization of board for training needs of different architectures in VLSI Embedded Easy and Simple to use with very User friendly interface making learning the platform operation easy for students beginners Exhaustive Students manual and Instructors guide available with solved examples covering basic and advanced topics High Speed Board PCB Interconnect with Signal Integrity 2P C Embedded SoC Multi Architecture Support 89c51 PIC etc on single platform igi Analog ADC DAC Power Opto isolated IGBT Relay Pluggable memory 512 KB and more General Purpose Breadboard Development Features Single Board Platform for complete system design covering all parts in the system like FPGA CPLD P 2C Embedded SoC on a single platform Multi architecture support for FPGA ICPLD P C allowing evaluation of design performance on different devices like Xilinx Altera etc in VLSI and 89c51 PIC etc in embedded High speed and reliable System Interconnection Bus with proper signal integrity and low skew capable of board system level data transfer upto 80 MHZ reliably Specially mounted High speed gold plated and shielded connectors for signal integrity Specially designed Clock network for low board level skew between components Specially des
74. dule Also 32 bits out this bus are been shared with configurable 1 05 Few 1 05 also brought on DB 25 connector Designers can use this connector to interface with the PC s parallel port for communication We have provided a sample program which implements the hardware of 3 8 decoder IC 74xx238 which is active high decoder with 3 enable signals Here is the procedure for using the above code with this FPGA module Procedure for using module Write source code in VHDL Verilog using the Altera Quartus series software Pin lock the entity 1 05 with configurable 1 05 Run the FPGA design flow from synthesis to implementation of design on FPGA Generate the BIT file for TAG or serial mode Insertthe FPGA module on slot 1 or slot 2 Setthe programming mode in J TAG or slave serial Setthe PROM bypass jumpers to position 2 3 2 Setthe jumper position of configurable 1 05 for input or output for entity pins 2 Connectthe programming cable Turn on USDP power supply Program the FPGA 2 Check the application Source code for FPGA Source code name decoder vhd Pin lock file name decoder ucf Note For further information on Altera ACEX 1K FPGAs kindly refer the device datasheet umper Settings Programming Mode selection jumpers J 3 J 8 MSEL1 MSELO Passive Serial PS 0 0 JTAG 0 1 For logic low short 2 3 and for logic short 1 2 for logic High Mode selectio
75. e BERG pins for stacking which are unable to perform at high frequencies Easy user interface Designers have always faced problems now and then in attaching external world signals with the protoboards When it comes to external design module interface the problems increases as the interface is poor and testing becomes a headache Easy user interface has always the key point in designing these protoboards for this manufacturers provide options of D type connectors BERG connector or other connectors These connectors have problems like limitation on number of 1 05 poor signal integrity and hassle of wires Up gradation Looking at the customer needs the products are continuously up graded or redesigned The system should be capable of up grading the system components and giving the product some added features to compete in the market Generally protoboards don t have this kind of feature with them After couple of project completions the designers find their existing protoboards old and difficult to upgrade Where as to be in market the protoboards should posses the ability to upgrade themselves with the latest FPGAs CPLDs increase in number of user 1 05 interface with new technologies replacement of existing FPGA with higher speed device etc 6 ni logic P vt Ltd Pune USDP User Manual Chapter 2 About USDP Overview of Universal System Development Protoboard VLSI trainer protoboards or kits are extensively used in prototyping of F
76. e button to start programming the device After display of OK on the activity window start working on your application Note The above program works on windows 98 to work on windows 2000 XP install the provided DiportlO driver The above sample program works in conjunction with FPGA so after programming the PIC controller configure the FPGA with the sample code provided for it For more information refer the chapter Using Add on Modules 1 ni logic P vt Ltd Pune USDP User Manual Chapter 10 Using Add on Modules In this chapter user will cover the basics on using the add on modules provided along with the USDP The motive of chapter is to let the user know about the module executions steps block diagrams and details for using the modules Here is the list of modules to be covered under this chapter USDP Base Board Xilinx FPGA Module Altera FPGA Module ADC DAC Module 89c51RD2 Module PIC uC Module SRAM Memory Card Power Electronics Module General Purpose PCB 78 nilogic Pvt Ltd Pune USDP User Manual 1 USDP Base Board USDP baseboard is used to interface the various modules with each other Designers can use this baseboard for developing their application with switches segment displays keypad and connectors provided umper and Header settings Clock J P1 Pin 1 Clock Pin2 GCKO Pin 3 Ground To use the oscillator clock short pin 1 and 2 It is recommended to gro
77. e out of the window Options for Target Target 1 Target Listing C51 51 151 Locate BL51 Misc Debug Select Folder for Objects Name of Executable serial_transmi Create Executable serial_transmit Debug Information Browse Information Create HEX File Format 02051 Create Library serial_transmit LIB r After Make Beep When Complete Start Debugging Run User Program 1 Browse Run User Program 2 Browse OK Defaults Step 10 Now to build the HEX file goto project menu and click the build target option f demo p ision2 E ni Logic Pvt Ltdni2 Designs Almighty Kit Keil Demo serial_transmit c E lal x File Edit View Project Debug Peripherals Tools SVCS Window lal xj ter Poe Import pVision1 Project Open Project Close Project Eile Extensions Books and Environment ds it on the serial PORT pn the port 0 data 5 63 Source C 8 seri Targets Groups Files Select Device for Target Target 1 Remove File serial_transmit c Options For Target Target 1 Clear Group and File Options amp Translate Logic Pvt Ltd ni2 Designs Almighty Kit Keil Demolserial transmit c Stop build 1 1 Pvt Ltd ni2 Designs Almighty KitlKeil Demolkeil demo uv2 2 C MKeillsh
78. eat steps 6 to 8 The above program works on windows 98 2000 XP platforms The above sample program works in conjunction with FPGA so after programming the 89c51 controller configure the FPGA with the sample code provided for it For more information refer the chapter Using Add on Modules 74 ni logic Pvt Ltd Pune USDP User Manual Programming PIC 16F877 controller Using the ProgPIC programmer designers can program the PIC 16F 877 controller module After building the HEX file from compiler designers can refer the below shown steps to program the controller Insert the controller module on baseboard connect the serial cable provided to module and P C s parallel port Connect the 18V adaptor to Casio plug on the module This adaptor is used to generate high voltage pulse to reset the PIC remove this adaptor after programming the PIC controller Turn ON the power supply now run the EXE of ProgPIC programmer on your PC The below shown window will open up PIC16Fxxx Programmer TEST E a n File Port Erase Options Help Action Controller Read all v White Code v IV Write Data DEV ID Write Write Config Word Erase bef Write Config Verify Code Low olt Prog Current File Activity Exit The designer needs to set the programming port device configuration word and couple of option to use the above programmer once looking atthe pictorial steps below it wi
79. el language program description fin Hig guage prog p Using assembly or C language i Converters the object code to low level E i Build xo Builds the programming hex file ma Step by step execution of program Program the controller using ISP external Pr gt 37 nilogic Pvt Ltd Pune a USDP User Manual Using Xilinx ISE Series Software In this section we will see how a project can be created in Xilinx and Altera EDA tools and how we can proceed to use USDP to perform our experiments using FPGAs We take the example of 3 8 decoder with enable inputs and implement on both vendor devices Design flow for Xilinx ISE series softwares Step 1 Open ISE webpack software Step 2 Create new project Project Name Project Location decoder JE kit_test_projects USDP_Demo me Project Device Options Property Name Device Family Spartan2 25200 Package Speed Grade eg Design Flow XST VHDL Cancel Step 3 Go to project menu and select new source P Project Navigator E kit_test_projects USDP_Demo decoder decoder npl File Edit View Project Source Process Window Help Josue Add Source Insert Add Copy of Source Shift Insert z 9 Sources in Proje Cleanup Project Files B decoder Toggle Paths Archive Take Snapshot Make Snapshot Current
80. els are essential for accurate simulations Synchronous A digital circuit where all of the operations occur in lock step to a master clock signal A mode of transmission in which the sending and receiving terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means An operation or operatons that are controlled or synchronized by a clocking signal Synthesis also Logic Synthesis A computer process that transforms a circuit description from one level of abstraction to a lower level usually towards some physical implementation Synthesis is to hardware design what compilation is to software development In fact logic synthesis was originally called hardware compilation System on a Chip SoC Combining several chips with different functions onto one single chip pin used to supply clocks to the TAP Controller d Data In a TAP pin used to shift the test data in to the TAP Controller ciu Out a TAP pin used to shift the test data out from the TAP Controller TMS Test Mode Select a TAP pin that provides the stimulus to change the state of the TAP Controller USDP Universal Development Platform a integrated platform where designers can put different technology modules all together for their system design User Constraints File UCF A user created ASCII file for storing timing constraints and location constraints for a design implementation Verilog
81. ese controller cards the designer gets the choice for selecting the controller depending on the application requirement As 89c51 is based on 8051 architecture the students feels comfortable and gets the exposure for practical design development and also the PIC 16F877 which is RISC based architecture gives them a real learning experience Other Digital experiments and Practicals Design of 8 16 24 32 bit counters amp shift registers Adders and subtractors 4 bit and 8 bit ALUs Timer designs 1 8254 amp IC8253 8255 PPI design Micro processor design development using HDL All digital logic gates and functions 15 ni logic Pvt Ltd Pune USDP User Manual Chapter 4 System Diagrams This chapter has the required system diagrams of USDP 32 Add on connectors PLD connectors Slot5 lot 4 Sit 3 4 7 seg Display Slot 2 Keyboard Header Configurable user I O Slot1 USDP Base board connectivity 16 nilogic Pvt Ltd Pune USDP User Manual Add on Parallel Port Header connectors 17 PIC Memory 32 32 Gen PCB FPGA Power Module Slot5 Slot4 Slot3 4 7 seg Display Keyboard Header Configurable user I O Note General purpose PCB and power module can be mapped anywhere on the addon connectors FPGA Connectivity 17 ni logic Pvt Ltd Pune USDP User Manual Add On Connector Pin Out Table Al LDO LD1 LD2 104 LD5 LD6 A5 LCO LC1 LC2 A7 1 4
82. g chip select for four memory chips this makes the module more easier in use by just providing the address lines and control signals for data transfer I 512KB SRAM Memory Module 99 nilogic Pvt Ltd Pune USDP User Manual SRAM Module Pin details Acex Spartan ll Acex 1K Spartan ll Al Al6 36 34 A2 17 37 35 18 40 41 A4 DO 141 42 5 D1 46 45 A6 D2 47 46 AT D3 55 49 8 04 56 57 9 05 60 60 10 06 61 61 11 07 65 67 12 RD 67 68 A13 WR 70 71 14 A19 71 13 A15 A20 75 81 Acex Spartan ll Acex Spartan ll Bl 0 38 36 B2 Al 39 37 B3 2 44 43 B4 45 44 B5 4 53 4 5 54 48 7 A6 57 58 B8 7 58 59 B9 A8 63 62 B10 A9 64 63 B11 10 68 69 B12 All 69 70 B13 Al2 73 74 B14 13 74 15 B15 A14 86 83 B16 15 87 84 100 ni logic P vt Ltd Pune USDP User Manual Eta K6T4008C1C logic sp vt ni K6T4008C1C K6T4008C1C K6T4008C1C SRAM Module SRAM Memory Module Board Ident 101 ni logic Pvt Ltd Pune USDP User Manual K6T4008C1C SRAM K6T4008C 1C SRAM Memory Pin out 102 ni logic P vt Ltd Pune USDP User Manual 8 Power Electronics Module Power Electronics Module is external module provided along with US
83. ght then the relay will turn ON and LCD will display Password OK If the password is wrong then the relay will remain OFF and a LED will be glown indicating false password and LCD will display Password Not Matched This is a simple access control system further user can modify the given source codes to make it more complex in terms of number of trials buzzer O P s and change of password etc Password will be 143 Control Logic Block diagram of Access Control System 112 ni logic Pvt Ltd Pune USDP User Manual Beginning with application User has to get together the modules specified and use them to run the application on USDP Here is the procedure to be followed to begin with application Insert 89 51 Module on USDP Program it with the given programming file access control hex Turn offthe USDP power supply Insert general purpose PCB in USDP amp make connections with LCD module Interface the USDP with power module and keypad Now insert the Xilinx FPGA module in USDP and program it with the given source code access control vhd Resetthe system and check the application NON 023 02 C2 Designers can use the sample codes provided along with USDP The list of codes to be used for this application is listed below User can refer these codes for their other applications and modify accordingly to their requirements Source code for FPGA Source code name access control vhd Pin lock file n
84. ign cycle because design iterations are simply a matter of changing the programming file and the results of design changes can be seen immediately in working parts PLDs do not require long lead times for prototypes or production parts the PLDs are already on distributor s shelf and ready for shipment PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets PLD Suppliers incur those costs when they design their programmable devices and are able to amortize those costs over the multi year lifespan of a given line of PLDs PLDs allow customers to order just the number of parts they need when they need them allowing them to control inventory Customers who use fixed logic devices often end up with excess inventory which must be scrapped or if demand for their product surges they may be caught short of parts and face production delays PLDs be reprogrammed even after a piece of equipment is shipped to a customer Conclusion The value of programmable logic has always been its ability to shorten development cycles for electronic equipment manufacturers and help them get their product to market faster As PLD suppliers continue to integrate more functions inside their devices reduce costs and increase the availability of tme saving IP cores programmable logic is certain to expand its popularity with digital designers 4 ni logic P vt Ltd Pune USDP User Manual Prototyping kits for Prog
85. igned High current capacity power supply for High Speed system ni logic P vt Ltd Pune USDP User Manual Advantages of Universal System Development Platform over other protoboards Here are the technological advantages of USDP with other protoboards 2 Easy system design and development Good learning and design implementation platform Single platform for multiple technologies Stacking of multiple FPGAs which makes multiple FPGA designs development possible Higher performance Long chain of Add on modules for all type of applications Capable for future advancement and up gradation with new technologies Large number of user interface General purpose PCB for user circuit interface N 29 03 02 0623 0623 062 02 Applications of USDP Prototyping of FPGA designs Research and development of high speed FP GA designs Design and development of FP GA based DSP designs and algorithms Understanding of various FP GA architectures Totrain designers how to exploit architectural features of F P GAs from different vendors Performing a wide range of experiments by actually downloading the designs into FPGA Understanding the basics of HDL s and digital logic interface Robotics and Motion control applications Mictrocontroller based applications 2 controlled design development 13 nilogic Pvt Ltd Pune USDP User Manual Examples Temperature controller USDP is ideal for
86. ilogic Pvt Ltd Pune USDP User Manual PIC 16F877 Micro controller Pin details Acex 1K Spartan ll Spartan ll 1 ANO RAO 36 34 A2 ANIRAI 37 35 AN2 RA2 40 41 4 AN3 RA3 41 42 A5 AN4 RA4 46 45 A6 AN4 RAS 47 46 A7 RDO 55 49 8 01 56 57 9 RD2 60 60 A10 RD3 61 61 11 RD4 65 67 12 RD5 67 68 A13 RD6 70 71 A14 RD7 71 73 15 MCLR 15 81 Acex Spartan ll Acex Spartan ll Bl RCO 38 36 B2 RC1 39 37 B3 RC2 44 43 B4 45 44 B5 RC4 53 47 B6 RC5 54 48 B7 RC6 57 58 B8 RC7 58 59 B9 RBO INT 63 62 B10 64 63 11 RB2 68 69 B12 69 70 B13 RB4 73 74 B14 RB5 74 75 B15 RB6 86 83 B16 RB7 87 84 J umper amp Header Settings Programming jumper JP9 JP10 amp JP11 are programming selection jumpers User has to short 1 2 during programming and after programming the PIC controller short 2 3 JP1 JP1 J P2 JP3 Pinl 1Hz clock from RTC Pinl Ra4 Pinl PCRX Pin2 Ground Pin 2 RbO int Pin2 PCTX Pin3 Ground Pin3 Ground RX2 J P5 Port RC7 is used for RX channel of RS 232 also this port pin is shard with base bus and by removing this jumper you can isolate the 5 232 from the base bus TX J P6 Port RC6 is used for TX channel of RS 232 also thi
87. king at the above steps the most problematic stages are prototyping the system schematic and testing the hardware which consumes the maximum amount of time As the prototyping is generally done on breadboards or the general purpose PCB this takes intensive care on making it and many times there are errors in building the circuit Also during testing designers should be given flexibility to modify the schematic instantly and to carry various tests for the available schematic And it is hectic task to design with these traditional steps also they don t offer f lexibility and designers don t get the privilege to market product in short span of time Now here USDP gives the advantage over traditional methods of design and other protoboards available As it is universal platform and provided nearly all the modules for system design designers can just plug the required modules and design verify their application in very short span of time USDP also serves as a very good platform to train students on concept of electronic system designing As all the basic technology platforms are integrated on USDP VLSI Microcontroller power electronics communication etc students can work on projects where they can have real life practical experience for system design This will make them more mature about practical concepts of electronics and give them chance to learn real life project development Also the modules are independent to each other and do n
88. l 32 configurable 1 05 are provided on USDP baseboard To configure them as I P user has to insert jumper in between and remove the jumper to make them as O P The switch configured as input to FPGA should not be connected to pin which is configure as output in FPGA else there would be a hardware short and may cause damage to the device User has to take this care during VHDL coding and pin assignment Power Headers 8 amp 9 There are power supply headers users can connect the SMPS to any one of these headers Two headers are provided just for the sake of convenience for connecting the SMPS from any of the directions SLOT SEL J P3 This is slot selector header User can use the provided selector card for selecting the slot Slot1 Slot 2 Short 1 2 Short 2 3 PLD SEL J P2 This is PLD vendor selector header User can use the provided selector card for selecting the PLD vendors Xilinx Altera Short 1 2 Short 2 3 7 Keypad Pin No Signal Pin No Signal 1 VCC 2 GND 3 513 4 512 5 511 6 SLO 7 RL3 8 RL2 9 RLI 10 RLO Programming Port J 6 User has to connect provided programming cable to this port and P C s parallel for programming of FPGAs 29 ni logic Pvt Ltd Pune USDP User Manual Xilinx FPGA module Programming Mode selection Switch U7 Modes 0 M1 2 JTAG 1 10 1 Slave Serial 1 1
89. ll become more easy to use the programmer Step 1 Go to Port menu and select the PP 0378H option to use the parallel port for programming PIC16Fxxx Programmer TEST E ial File Port Erase Options Help PP 0278 Controller PP 0 Write Code BC71 COMI Write Data v COM2 White Config Word DEVAD rite Contig Wor com4 Erase bef Write Config COMS PES pn Low Volt Prag 3FFF Activity ee ae Exit 75 nilogic Pvt Ltd Pune USDP User Manual Step 2 Now go to File menu and click open file option there after you have to browse to your programming HEX file You can select the sample program provided along with the USDP disp PIC hex PIC16Fxxx Programmer TEST File Port Erase Options Help Close File Controller EX j 17 Wite Code riciecr v Write Data DEVAD ex Write Write Config word Erase bef Write Config Verify Code Low Volt Prog 3FFF Current File Activity Exit Step 3 Go to Controller option on main window and select PIC partnumber as 16F877 16 Programmer TEST File Port Erase Options Help Action Read all IV Write Code IV Write Data Write Write Config word Erase bef Write 41 Verity Code bowSoltProg Current File Activity disp_PIC HEX 76 ni logic Pvt Ltd Pune USDP User Manual Step 4 The PIC con
90. log signal Sample to a digital representation suitable for digital processing and switching Asynchronous Asynchronous system computer circuit device is one in which events are not executed in a regular time relationships They are timing independent Each event or operation is performed upon receipt of a signal generated by the completion of a previous event or operation or upon availability of the system resources required by the event or operation C Common programming language used in science engineering and DSP Also comes in the more advanced CH Concurrency The ability of an electronic circuitto do several or at least two different things at the same time Contrast with computer programs which usually execute only one instruction at a time unless the program is running on a processor with multiple concurrent execution units Combinational Logic Combinational logic is purely functional logic which does not maintain any internal state Thus it will provide the same result for the same input no matter what sequence the input is sent CPLD Complex Programmable Logic Device A programmable IC which is more complex than the original Programmable Logic Devices such as AMD s originally MMI s PALs but somewhat less complex than Field Programmable Logic Arrays Digital Signal Processor DSP A processor system specialized for the computation of signal processing algorithms It usually consists of many programmable processor elemen
91. logic Pvt Ltd Pune USDP User Manual Technology Interface As the FPGA designs accounts the integration of dense memories analog interface DSP microprocessors and microcontrollers many vendors are unable to provide a platform where a designer can integrate all kinds of modules with the FPGA High speed performance Integration of other technology modules is not only the issue with complex FPGA designs The most important part in FPGA designs is to achieve the target speed of operation Many designs are required to operate more than 60MHz and how many actually guarantee this speed of operation with bad PCB designs congested boards bad connectors and poor power supplies Generally the vendors use the berg connectors for the user interface and FPGA attachment which cannot perform more that 20 30 MHz the signals get deteriorated and poor single integrity of design is the outcome FPGA stacking Also an FPGA designer needs a freedom to use any FPGA for his application i e he may opt to use FPGAs from different vendors according to the design requirements and project needs Most of the vendors have failed to give this kind of feature FPGA stacking feature is most demanding one in the design of an FPGA protoboard which means a designer can interface more than one FPGA together and that too from different vendors Even if the foreign vendors have come with feature of FPGA stacking there is limitation on number of FPGAs and generally they us
92. n jumpers J 4 J 5 J 6 J 7 Serial J TAG Short 2 3 Short 12 PROM BYPASS J 1 amp J 2 To Chain PROM To Bypass PROM Short 1 2 Short 2 3 Shorting 1 2 will bring the PROM in chain with FPGA In this case user can configure the PROM and use for programming file storage Shorting 2 3 will remove the PROM from chain and only FPGA would be connected to programming port 84 nilogic Pvt Ltd Pune USDP User Manual E c B 8 amp 5 lt B a o a LL gt lt lt MODE SELECT 5H ALTE zz oo BE J6 TDI DIN ms NCONFIG J5 TCK DCLK J CF DONE enm 2 4 5 a m mw ww esset eri j BYPASS CHAIN Mode selection jumpers T Coe 4 5 mo 5 5 a 5 z X 5 g a all a 9 o om a ACEX FPGA Adaptor Board Ident DB 25 connector Regulators FPGA PROM ni logic Pvt Ltd Pune USDP User Manual ACEX1K FPGA Pin detail Device PQ208 Clock amp Reset Clock 79 Reset 180 Note Resetis active LOW Configurable 1 05 LA7 70 LB7 60 LC7 46 LD7 36 LA6 71 LB6 61 LC6 47 LD6 37 LA5 73 LB5 63 LC5 53 LD5 38 LA4 74 LB4 64 LC4 54 LD4 39 LA3 75 LB3 65 LC3 55 LD3 40 2 85 LB2 67 LC2 56 LD2 41 LA1 86 LB1 68 LC1 57 101 4
93. o FPGA with the provided cable only Gate 1 IGBT 1MB60D Circuit Schematic Collector 2 3 Emitter 1 6 2 5 3 2 PIN 1 ANODE 2 CATHODE 3 NO CONNECTION 4 EMITTER 5 COLLECTOR 6 BASE Opto coupler MCT2E Pin out ni logic P vt Ltd Pune USDP User Manual 402 ON IN ON IN 32 9 J QN9U SPUPH pas xeN Yano i uoq d o 24 iE9NINSUM al 39 A J8T141328M e 1 11841 mmi T lat 3NI3 29 U J04 SUe 4 in 8 JI T 83 x d angy rat un zu ot sn L1 zu K anga pp b QN9I an 1 a nee ae 0 o 5 E 9n o D gt 0 9 on 240 2 u en Ca a m ul m a 9 fm ca mje o zn CJ n zm amp B N un a wa m a SONO Dx 9 0 4315 A 9944 st 1 z Zar Bid Power Module Board Ident ni logic P vt Ltd Pune 107 USDP User Manual 9 General Purpose PCB General Purpose PCB can be used for glue logic design analog circuit or any other custom circuit interface with the USDP modules The LCD header provided on the PCB can be used to drive the LCD module provided along with USDP The header J P6 connects with the LCD module and the LCD 1 05 header J P13 can be connected to the general 1 05 provided on board This
94. ock to be erased generally up till block 1 or 2 are needed for small code of program These are code memory locks which needs to be erased to over write the new program on to them Flash Magic File ISP Options Help COM Port com 1 Erase block 0 0 0000 0 5 ble 1 Baud Rate 9600 Erase bl Erase block 3 0 8000 Device B9C51RD2Hxx Erase block 4 0 000 0 Oscillator Freq MHz E 1 0532 Hex File Browse Last Modified Unknown Size Unknown Verify after programming Set Security Bit 1 Fill unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 v Execute Start Technical on line articles about 8051 and programming Erase all Flash Security WwWw esacademy com fag docs Step 6 the 3 section you have to give the programming HEX file so browse to the folder containing the HEX file and click OK You can browse for sample HEX file provided along with the USDP serial transmithex Flash Magic File ISP Options Help 1 Port v Baud Rate s v Device B9CS1RD2Hxx v Oscillator Freg MHz 11 0592 Hex File Ltd ni2 Designs Almighty Kit Keil Demo serial_transmit he4 Browse Last Modified 11 7 2003 4 14 11 Size 302 bytes Verify after programming Set Security Bit 1 Fill unused Flash Set Security Bit 2 Generate checksums
95. ompiler Settings Simulator Settings General Mode Options Time Vectors Software Build Settings Stratix GX Registration Step 13 After clicking OK come back to main window and goto processing window and click start simulation the Quartus Il will start the simulation the result would appear in couple of minutes Observe the results if found bugs then change VHDL code and start simulation again 1 Quartus II cquartus demo decoder decoder decoder Simulation Report E E lal x amp File Edit View Project Assignments Processing Tools Window Help 81 x Osa S oR cw tro989e660 xempageeeeoe7 d 9 BR Simulation Waveforms Files amp B Legal Notice Device Design Files E Software Files E Other Files summary Simulator Settings Simulation Waveforms amp 3 Messages Processing Time A fal en d x 2 m Em Processing Total Initialization El Simulator Total Netlist Builder Simulator 52 ni logic P vt Ltd Pune USDP User Manual Step 14 Once the simulation results are found correct then we need to implement the design in the target device For this we need to lock our design 1 05 with the Kit I O pin details Goto assignment menu click assign pin option Quartus c quartusdemo decoder decoder decoder Simulati
96. on With this unique idea product ni logic will stand ahead in market segment of PLD products and will prove with its sales figures in coming years 7 ni logic Pvt Ltd Pune USDP User Manual Features of USDP 9 Os MOD MOD AS C MOS 2 52 52 023 52 2 2 5 03 00239 623 023 03 023 023 03 5 2 2 Easy to use and implement system designs Slot cards for FPGA from Altera Xilinx and other vendors with package support up to F G256 Stacking of multiple FP GAs can be of different vendors 64 bit general purpose bus interface with FPGA 77 bit bus sharing between FPGAs High performance backplane good frequency response upto 80MHz designs One of the fastest protoboards available in India On board TAG circuit for downloading Multiple configuration options with J TAG chaining of devices User selectable configuration modes using either FLASH PROM TAG 32 Digital I P s and O Ps each can be configured as input or output giving flexibility to designers On board system reset circuit Configuration reset circuit Four seven segment Multiplexed display 4x4 membrane keypad On board crystal oscillator socket user can select his desired oscillators Generalpurpose user area for interface of user clock circuit Ability to use Clock management circuits of FPGAs Proper configuration of FPGAS with high speed clocks through special scheme SMPS Support for different 1 0 Standards A complete 1 0 bank for user V
97. on Report File Edit View Project Assignments Processing Tools Window Help 1 SIL TE X 73 mmm EL Assign Pins Fe x 22 EDA Tool Settings 24 Files Settings CtrleShift E Device Design Files E Software Files Timing Wizard Other Files Compiler Settings Wizard Simulator Settings Wizard Software Build Settings Wizard Assignment Editor Ctrl Shift A Remove Assignments EA Demote Assianments Back Annotate Assignments Import MAX PLUS II Assignments 7 amp Last Compilation Floorplan 60 Timing Closure Floorplan 52 Chip Editor Processing Total LogicLock Regions Window Alt L Initialization E Simulator Total Netlist Builder Simulator 8 Import LogicLock Regions 58 Export LogicLock Regions Step 15 Looking at the pin assignment chapter lock the ACEX 1K FPGA 1 0 with the particular pin no for this Select the 1 0 number on the LHS name the design 1 0 in the bottom pin name option and then click add the particular signal will be locked to that pin number Assign Pins Select a device pin and the type of assignment you wish to make You can also make pin assignments in the Assignment Editor and the Floorplan Editor Y
98. ore we will cover the necessary steps required to configure the devices Xilinx FPGAs Select the configuration mode and generate the programming file accordingly Set the mode selection switch position on Xilinx module with reference to your selected programming mode Check the PROM jumper setting for using or bypassing the PROM Set the jumper selection for TAG serial mode Inset the Xilinx module on any one of the PLD slots 5101 or Slot2 Connect the programming cable Short the 1 2 connections of PLD sel header on the baseboard to select the Xilinx programmer Select the slot you want to program Turn on the board supply Run the programmer on the Xilinx ISE series software WYN YY 59 9 39 5 59 Note For jumper header setting refer chapter umper Setting and for Xilinx ISE flow refer chapter EDA tools 2 Altera FPGAs Select the configuration mode and generate the programming file accordingly Set the mode selection jumpers on Altera module with reference to your selected programming mode Check the PROM jumper setting for using or bypassing the PROM Set the jumper selection for TAG serial mode Inset the Altera module on any one of the PLD slots 51011 or Slot2 Connect the programming cable Short the 2 3 connections of PLD sel header on the baseboard to select the Altera programmer Select the slot you want to program Turn on the board supply Run the programmer on the Altera Quartus series software 9
99. ot depend on the base board thus any further modules which ni logic will introduce can be plugged on existing system and up gradation of USDP can be easily done Only the designer has to take care thatthe all the modules are connected with FPGA independently thus user has to included FPGA in their designs but further after verifying logic they can exclude it while g oing for final product design 111 ni logic Pvt Ltd Pune USDP User Manual Chapter 12 An Application Implementation on USDP In this chapter we take an example for developing a real life example on USDP Application Access control system Today many applications are developed for security and access controlling The basic applications of access control can be developed and prototyped on USDP The basic model consists of keypad interface for password entering solenoid for door open amp close which can be replaced with relays here user display for welcome notes menus and messages displays Modules to be used 89C51 module Xilinx FPGA module LCD module general purpose PCB Power module and keypad 4x4 Keypad Application description We keep the example very simple user reaches to gate and reads the message Enter the Password then he has to enter the 3 digit password 0 9 to open the gate relay will indicate the gate opening after entering the password he has to enter the F1 key which in turn will take the password If the p assword is ri
100. ou can reserve unused pins on a device wide basis with the Unused Pins tab in the Device amp Pin Options dialog box You must perform a smart compilation on the design before routing SignalProbe signals Changes apply to Compiler settings decoder Available Pins amp Existing Assignments 0 LVTTL LVC m V0 Off 5 0 Row 1 0 Off 3 0 LVTTLALVC Row 1 0 Off 0 LVTTLALVC Row 1 0 Off 0 LYTTL LYC Rowl D Off 0 LYTTLALVC Row 10 Show current and potential SianalProbe pins Show no connect pins Lime lose 1 0 Standard SignalProbe SouceName Enabled Staus Cral Assignment SignalProbe enable 1 G standard vs in ACEX1K 71 Reserve pin even if it does not exist in the design file as input tri stated Register Pin name end SianalProbe source E Clock E sw Delete Enable All SianalProbe Routing Disable All SignalProbe Routing cove ni logic Pvt Ltd Pune USDP User Manual Step 16 Once the pin assignment is over come back to main window Now we need to implement the design on the particular device So goto processing menu and click start compilation process Which will place amp route the design in FPGA and generate the programming file 4 Quartus II cquartus demo decoder decoder decoder vhd File Edit View Project Assignments Processing Tools Window Help
101. ound Note Both the FPGAs share the above I Os User has to take care that no two pins are defined as output as in that case there would be short on the bus and may damage FPGA 1 05 Also tri state the unused pins of FPGA by changing settings of your EDA tool while pin locking User can define the following combination of FPGAs shared 1 05 FPGA1 FPGA2 Input Input Allowed Output Input Allowed Input Output Allowed Output Output Notallowed 21 ni logic P vt Ltd Pune USDP User Manual Spartan ll FPGA Pin detail Device XC2Sxx PQ208 Clock and Reset Clock GCKO 80 GCK2 182 GCK3 185 Reset 5 Note Resetis active LOW Configurable 1 05 LA7 34 LB7 45 LC7 60 LD7 71 LAG 35 LB6 46 LC6 61 LD6 73 LA5 36 LB5 47 LC5 62 LD5 74 LA4 37 LB4 48 LC4 63 LD4 75 LA3 41 LB3 49 LC3 67 LD3 81 LA2 42 LB2 57 LC2 68 LD2 82 LA1 43 LB1 58 LC1 69 LD1 83 LAO 44 LBO 59 LCO 70 LDO 84 7 Segments Display Enable Keypad Header segA 33 DISP1 17 SLO 8 6 segB 31 DISP2 18 SL1 15 RL1 10 segC 30 DISP3 20 SL2 9 RL2 7 segD 29 DISP4 21 SL3 16 14 segE 27 segF 24 segG 23 segDP 22
102. ples are provided for FPGA and 89c51 controller The FPGA consists the control logic and controller has the LCD logic Working with code Insert the 89c51 module in USDP connect the LCD module to 89c51 through the general purpose PCB Connect the keypad to its header make connections with the power electronics module through general purpose PCB Program the 89c51 controller with the programmer provided turn OFF the power supply insert the FPGA module amp program it with the given source code and pin lock file Source code for FPGA Source code name access control vhd Pin lock file name 55 control ucf Source code for 89c51 Source code name access control c Header file name zLCD routine c Programming file name access control hex 116 ni logic P vt Ltd Pune USDP User Manual Chapter 14 Glossary of Terms ASIC Application Specific Integrated Circuit A custom integrated circuit designed specifically for one end product or a closely related family of end products Analog Digital and Mixed Signal A circuit used to count the number of events is generally digital Sometimes chip are called mixed signal chips which means that they contain both analog and digital circuits Analog to Digital Converter ADC An electronic circuit that converts a continuously varying signal temperature pressure voltage etc into digital zeroes and ones that can be processed by a microprocessor or microcontroller Converts an ana
103. plex and available with inbuilt hard wired microprocessors PCI cores peripherals etc Thus their protoboards kits also need to be designed accordingly so as to exploit the complete architecture and feature set of PLDs a designer needs some basic specifications on the protoboards The most demanding feature set of any PLD Protoboard is as follows Ability to program the PLD in circuit User inputs and output Displays like 7 segmentand LCDs Keyboard Clock circuit Power ON Reset User interface 1 05 On board power supply Any bus interface 10 Easy to use and operate 11 etc Needs of today s protoboards VLSI trainer protoboards or kits are extensively used in prototyping of FPGA based product designs training and for experimental purposes All of them posses feature set towards programming of FPGAs and just few user input output facilities Very few protoboards offer a complete solution for integration of various user modules with ease With the advancement in the system requirements and specifications designers are finding difficult in development of FP GA based designs The increase in complexity of design has made a significant change in FP GA architecture With Virtex ll pro device from Xilinx and Stratrix Excalibur from Altera designers can integrate a complete system in them With millions of system gate capacity and inbuilt microprocessors they give flexibility to designers to develop smaller and more complex designs 5 ni
104. r other devices List of Application Add on modules Here is the list of add on modules that are supported by Universal System Development Platform All cards are made on edge connector of 120 pins 1 Micro controller Card Philips 89C51 RD2 controller RS 232 interface On board serial EEPROM On board serial RTC In system serial programmable ISP All the I Os are accessible to FPGA with connector in between Available with standard codes of 12C timers data transfer etc OY 03 5 9 YY 35 2 PIC Micro controller Card Microchip 16F877 PIC microcontroller In system Programmable Onboard and RS 232 Interface 2 Interrupt port All ports accessible through edge connector 3 Memory Add On Card Add on module for Memory intensive applications Total 2MB data storage capacity Four512KBx2SRAM Direct high speed interface with FP GA modules 70 5 of access time 10 ni logic Pvt Ltd Pune USDP User Manual 4 ADC DAC Add On card 9 4 channel ADC 2 channel DAC Sampling rate upto 400 KSPS 8 bit ADC resolution 12 bit DAC resolution 0 5V or 2 5V input voltage 5 Power Electronics module 59 53 023 55 063 0623 5 02 359 IGBT based drive with current rating upto 10Amps Dual high current relays Stepper motor controller circuit 5 optically isolated O P s Step down transformer 100 for line monitoring applications Separately available
105. r settings Square Wave J Pinl 1Hz clock from RTC Pin2 Ground Interrupt Timer J P4 Pinl Interrupt 0 INTO I P Pin 2 Interrupt 1 INT 1 I P Pin3 Timer 1 O P Pin4 Timer 0 O P JP1 amp P2 JP Portl 1 SDA Portl 2 SCLK USDP User Manual JP1 amp 2 are selection jumper for serial clock and data from RTC and EEPROM Both these signals Shared with the base bus of USDP So if you are these two ports of 89c51 with the base bus then remove the jumpers from the J P1 amp J P2 to isolate them from the base bus ni logic Pvt Ltd Pune USDP User Manual O Cos 5V Interupt Timer v a l RTC Ltd 2 3 3 o a 7 ic Pvt dia ni log Pune Indi 89c51 Microcontroller Card Board Ident ni logic Pvt Ltd Pune USDP User Manual IN LINE PACKAGE 89c51RD2Hxx Pin out Vcc PO 0 ADO PO 1 AD1 P0 2 AD2 PO A ADA P0 5 AD5 P0 6 AD6 PO 7 AD7 EA Vpp ALE PROG PSEN P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 ni logic P vt Ltd Pune USDP User Manual 6 PIC uC Module This module use RISC based architecture controller The PIC16F 877 controller is from Micro Chip which is In System Programmable ISP This is leading controller used in industries for product design and is widely
106. rammable Logic devices With the advent of any programmable device whether it be an EEPROM PAL PLA microcontroller microchip or a FPGA the need of programmer was mandatory The application or usage of programmer was just to download the programming file in the device Butthe FPGAs were exceptional case Applications like prototyping product development and learning of VLSI converted the programmers of FPGA into a more complex protoboards where the designers can program the FPGAs develop and verify the design and finally can go for production after satisfactory results Manufacturing of these trainer protoboards was earlier done by foreign companies and were costlier but day by day Indian manufacturers developed their own protoboards for the Indian market and thus VLSI designers engineers and educational industry of India got easy access to these protoboards They are available in a wide range depending on type of device used Applications of FPGA CPLD protoboards are 1 ASIC prototyping Product development Verification of designs in CPLDs and FPGAs Helping users to exploit architectural features of CPLDs and FPGAs Performing a wide range of experiments by actually downloading the designs into physical devices Understanding use of HDL s FPGAs and CPLDs have seen an exponential rise in their architectures and hence their applications In mid 90s PLDs were used in packing of digital logic into them but today devices are much more com
107. reation go to File option and select new project wizard In the opened window specify project location and design and entity name For eg Entity name decoder and top design name also decoder Click next New Project Wizard Directory Name and Top Level Entity page 1 of 6 What is the working directory for this project This directory will contain design files and other related files associated with this project If you type a directory name that does not exist Quartus can create it for you c quartus demo decoder xn What is the name of this project If vou wish you can use the name of the project s top level design entity What is the name of the top level design entity in your project The Quartus II software will automatically create Compiler and Simulator settings for the top level entity you specify in this wizard After you create a project you can add more top level entities and create Compiler and Simulator settings for them with commands on the Assignments menu 46 ni logic Pvt Ltd Pune USDP User Manual Step 3 Click next button till you reach EDA tool settings window there keep all options as none which in default will select the inbuilt design tools and softwares for the de sign processing Click next New Project Wizard EDA Tool Settings page 3 of 6 Specify the other EDA tools in addition to the Quartus II software that you will use on this project
108. ription and numbering Also this P CB contains headers for 45V 5V and ground signals onboard J P6 LCD Header Pin No Signal Pin No Signal 1 GND 2 5V 3 NC 4 RS 5 NC 6 EN 7 DO 8 D1 9 D2 10 D3 11 D4 12 D5 13 D6 14 D7 15 NC 16 NC LCD I Ps Pin No Signal Pin No Signal 1 00 2 RS 3 D2 4 EN 5 D4 6 D1 7 D6 8 D3 9 D7 10 D5 Note The LCD module pins are brought ona separate header J P1 users can interface LCD module to any of the modules 1 05 with the provided cable 33 nilogic Pvt Ltd Pune USDP User Manual Chapter 7 Precautions Please follow the guidelines below while using USDP and take the mentioned precautions General 2 Verify the power ON LED status after applying power to the trainer 2 Connectthe 25 pin D connector of the cable to the trainer only after confirming the above Insert the modules vertically in the slots slowly and with care as inserting the modules in angular form will cause damage to connector pins Donotpress the modules after inserting them on board else this can cause damage to connector pins During downloading make sure that the jumper selections are proper Before implementation it is necessary to lock the pins in user constraint file UCF as per the mode selected 2 For downloading the bit stream the downloading circuit requires a stable supply hence it is recommended to
109. rm for all programmable logic ICs including PLAs programmable logic arrays PALs CPLDs complex PLDs and FPGAs field programmable gate arrays Pipelining Splitting the CPU into a number of stages which allows multiple instructions to be executed concurrently PROM Programmable Read Only Memory An integrated circuit that store programs and data in many embedded systems PROM stores and retains information even when the power is off but it can only be programmed or initialized once 118 ni logic Pvt Ltd Pune USDP User Manual RTL Register Transfer Level or Register Transfer Logic A register level description of a digital electronic circuit Registers store intermediate information between clock cycles in a digital circuit so an RTL description describes what intermediate information is stored where it is stored within the design and how that information moves through the design as it operates Simulation Modeling of an electronic circuit or any other physical system using computer based algorithms and programming Simulations can model designs at many levels of abstraction system gate transistor etc Simulation allows engineers to test designs without actually building them and thus can help speed the development of complex electronic systems However the simulations are only as good as the mathematical models used to describe the systems inaccurate models lead to inaccurate simulations Therefore accurate component mod
110. s Window DG 8 i B 0 Stop Processing Gtri Shift C xe NADELA lee Start Compilation 8 gt 236 Current File pores Ss T ajx gem m jl Start Fitter LIRE Start Compilation amp Simulation di Device Design Files rb start Assembler 00 Software Fes cicada ba Start Timing Analyzer Ctrl Shift L Other Fies Simulation Debug TEE amp Start EDA Netlist Writer 5 simulation Report Ctrl Shift R 5 Start Design Assistant address i ps E eens 22 lov enable Start Incremental Fitting active low enable Compile Current File kj Start SignalProbe Compilation Ctrl Shift 5 active high enable ie b Statt Assignment Analysis decoder o p active high Te Hierarchies B Fies Design Units eee cee Start Mrimum Thing Analyst xi architecture Beha Start VOM Writer Modde Progess7 Tine begin Start Test Bench Template Writer Start EDA Resynthesis Y lt 00000001 SII add when enis and enz U and en3 1 else othersz 0 end Behavioral 49 ni logic P vt Ltd Pune USDP User Manual Step 8 Read the synthesis reports Quartus II c quartus demo decoder decoder decoder Compilation Report File Edit View Project Assignments Processing Tools Window Help 181 S sreo gt ens eeou
111. s port pin is shard with base bus and by removing this jumper you can isolate the 5 232 from the base bus SDA J P7 Port RC4 is used for serial data for RTC also this port pin is shard with base bus and by removing this jum per you can isolate the RTC from the base bus SCLK J P8 Port RC3 is used for clock for RTC also this port pin is shard with base bus and by removing this jumper you can isolate the RTC from the base bus 9 10 amp 11 During programming the PIC controller short pins 2 3 and after programming the controller short pins 1 2 for using with FPGA 96 ni logic Pvt Ltd Pune USDP User Manual Analog 5 Header for inbuilt ADC I Ps for PIC controller o c lt 2 122 lt lt L L L L lt L lt 1 lt 1 lt D ea cx eo lt io S S S S S S S S a a a a 340g 9044 zxy zL 1 a npoy JN Jid ni logic Pvt Ltd Pune eipu aung pq 191 a z t o Ad3llU8 8 a L 2719 H v O m I 16 877 Microcontroller Board Ident EZI zt Z I Z 14008 oia Butwwesboug 28349 97 USDP User Manual MCLR Vpp 1 4 RB7 PG
112. should be properly inserted Check the Flash Magic programmer settings refer chapter configuration Errors while programming PIC controller There may be errors while programming PIC16F 877 kindly check the following steps to recover the error Module should be properly inserted The programming cable should be properly inserted Check the P rogP IC programmer settings refer chapter configuration Check the jumper settings of PIC module Plug in the 18V adaptor on the plug socket of module NYY YN C2 Controller modules not working properly After programming of 89c51 amp PIC controllers you have reset them from FPGA or from keys else they won tfunction properly sometimes 2 Check the I O connections properly 2 Check the reset logic 2 Check the source code thoroughly there may be infinite loop or some other problem in code ADC DAC Module not working properly Insert the module properly Check the analog signal connections Check the channel is properly selected Check the ADC amp DAC logic wy 120 ni logic P vt Ltd Pune USDP User Manual Disclaimer ni logic pvt Ltd Pune takes the liability to replace the module product for any design fault from our side ni logic pvt Ltd Pune does not take any responsibility of failures or damages caused to product due to incorrect design practices misuse improper handling and not following the datasheet specifications of devices 121 ni logic P vt Ltd
113. source file in the editor or check the code EIE o ile dit Options Compile tilit el DISP PIC C USDP Sample Code Display Hi Iam USDP on segment displays Requires FPGA as feed through in between display and PIC lt 68 7 gt typedef unsigned int UINT typedef unsigned char UCHAR typedef unsigned long ULONG define TIMER1_RELOADH lt xfC gt y define TIMER1_RELOADL 8x66 static volatile bit SEL Cunsigned amp PORTC 8 0 static volatile bit SEL1 8 Cunsigned gt amp PORTC8 1 static volatile bit SEL2 8 Cunsigned gt amp PORTC 8 2 static volatile bit SEL3 8 Cunsigned gt amp PORTC 8 5 static volatile bit TEST 8 Cunsigned gt amp PORTC 8 4 UINT count bit secflag UCHAR digit UINT digbuf 41 UCHAR 1141 41 41 void inithw lt void gt lt ADCONL 0x86 INTCON 8x08 OPTION 8x88 TRISC 8x88 TRISD 8x88 TIMER1_RELOADH TMRiL TIMER1_RELOADL Line 27132 Col 1 Insert C mode 66 nilogic Pvt Ltd Pune USDP User Manual Step 10 The next step is to compile the source code For compilation and linking the source code go to Compile menu and select Compile and Link option o 11 dit Options Compile ake un DISP_PIC C USDP Sample Code include lt 1687 gt typedef unsigned int UINT typedef unsigned char UCH typedef unsigned long ULOJ define TIMER1_RELOADH
114. t So goto File menu and click New and select VHDL File in the device design files tab Click OK Device Design Files Software Files Other Files AHDL File Block Diagram 5 chematic File EDIF File Verilog HDL File Cancel 48 nilogic Pvt Ltd Pune USDP User Manual Step 6 Write the VHDL code for 3 8 decoder and save the file as deoder vhd 2 Quartus II c quartus demo decoder decoder decoder vhd fee Fie Edt View Project Assignments Processing Tools Window Help 1 gt Ma ixempasgBe 89999 7228 Courier New EE LE SIDE 2 2 xl library IEEE use IEEE STD LOGIC 1164 ALL C3 Device Design Files use IEEE STD LOGIC ARITH ALL C Software Files use IEEE STD LOGIC UNSIGNED LL E Other Files entity decoder is Port Add in integer range 0 to 7 address i ps enl in std logic active low enable 2 in std logic active low enable in std logic active high enable T out bit vector 7 downto 0 decoder active high end decoder Hierarchies E Files d Design Units xl architecture Behavioral of decoder is begin Y lt 00000001 sll add when eni 0 and en2 0 and en3 1 else others 0 end Behavioral 3t File View Project Assignments Processing Tool
115. t Source Design Entry Utilities Y lt 00000001 211 add when 1 0 and 2 0 and 3 1 else d User Constraints others gt 0 Synthesize Qe Implement Design Qe Generate Programming File E A Programming File Generation Report E Generate PROM ACE or JTAG File Configure Device iMPACT end Behavioral 0 8 8 E EH Wi Process View Launching Application for process Configure Device iMPACT Launching Application for process Configure Device iMPACT For Heln nress F1 ln 16 Cal 36 Step 13 Open the properties of IMPACT programmer and set the port as LPT1 configuration mode as Boundary Scan for TAG or PROM configuration Slave Serial for serial programming Leave the other options in default and click OK and come back to main window Process Properties iMPACT Programming Tool Properties Part to be used Configuration Mode Configuration Filename 43 nilogic Pvt Ltd Pune USDP User Manual Step 14 Run the IMPACT programmer z untitled Configuration Mode IMPACT File Edit Mode Operations Operations Options Output View Help D S H 50 Desktop Configuration Right click to Add Device or Initialize JTAG chain Device 1 selected Device 1 selected PROGRESS_START Starting Operation Validating chain Boundary scan chain valida
116. ta from ADC and to put data on DAC channels DA EC ee UK tee M cp ec EO ES SETTE ADCIDAC Controller DAC Data l I Signal DACI processing D DAC2 Signal processing Control Logic FPGA ADC DAC Module Block diagram of the ADC The above diagram shows how the interconnection can be done with the ADC DAC module The sampled data from ADC would be latched inside the FPGA and as the module has on board latches for DAC designer can control these latches and store data over there for DAC conversion Designer can use the sampled value from ADC for his signal processing and after that he can reconstruct the wave by storing the data in the on board latches for DAC We have provided a sample controller for ADC DAC module that works as feed though circuit between ADC and DAC User can use this source code for the check of module Procedure for using module Add the provided source code Xilinx ISE or Altera Quartus series software Run the procedure for using FPGA module refer previous pages Insert the ADC DAC module in Slot 3 Slot4 or Slot 5 Connect the signal generator or analog source to ADC s channel 0 Connect the CRO probe to DAC s channel 0 Turn on the USDP power supply Program the FPGA Check the application 5 3 5 3 lt 3 vy yyy C2 Source code for FPGA Source code name ADC DAC feed vhd Pin lock file name ADC DAC feed ucf For further working of
117. ted successfully l Programming device done 1 Programmed successfully PROGRESS_END End Operation Elapsedtime 9 sec gt Step 15 Right click to add the device programming file browse to your project folder and select the currently generated BIT file untitled Configuration Mode iMPACT File Edit Mode Operations Operations Options Output View Help i ee J eae La Boundary Scan Slave Serial Select Map Desktop Configuration Add Device E zii Lookin CX PIC Tests File name decoder bit Programming device done Files of type Jal Design Files Cancel 11 Programmed successfully PROGRESS_END End Operation Elapsed time 9 sec 1 Loading file F 1_USDP_Demo_Codes PIC_Tests decoder hit done 2 Device 1 selected Device 1 selected gt al 2 nilogic Pvt Ltd Pune USDP User Manual Step 16 Select the device file the color would go green Right click on the device file and select program option 2 untitled Configuration Mode iMPACT E ni x File Edit Mode Operations Operations Options Output View SR SRSRsA Haano Boundary Scan Slave Serial Select Map Desktop Configuration Program Verify Get Device ID Get Device Signature Usercode IDCODE Looping xe2s200 decoder bit TDO Assign New Configuration File 1 Loading file F USDP Demo CodesiP
118. terrupt 1 INT1 I P Pin3 Timer 1 O P Pin4 Timer 0 O P JP1 amp JP2 Porti 1 SDA JP2 Portl_2 SCLK USDP User Manual JP1 amp 2 are selection jumper for serial clock and data from RTC and EEPROM Both these signals Shared with the base bus of USDP So if you are these two ports of 89c51 with the base bus then remove the jumpers from the J P1 amp P2 to isolate them from the base bus ni logic P vt Ltd Pune USDP User Manual PIC Microcontroller Module Programming jumper 9 JP10 amp JP11 are programming selection jumpers User has to short 1 2 during programming and after programming the PIC controller short 2 3 JP1 Pinl 1Hz clock from Pin2 Ground JP2 Pinl Ra4 Pin2 RbO int Pin3 Ground JP3 Pinl PCRX Pin2 PCTX Pin3 Ground RX2 J P5 Port RC7 is used for RX channel of RS 232 also this port pin is shard with base bus and by removing this jumper you can isolate the RS 232 from the base bus TX J P6 Port RC6 is used for TX channel of RS 232 also this port pin is shard with base bus and by removing this jumper you can isolate the RS 232 from the base bus SDA J P7 Port RC4 is used for serial data for RTC also this port pin is shard with base bus and by removing this jumper you can isolate the RTC from the base bus SCLK J P8 Port RC3 is
119. the mode pins users have to use the DIP switch provided By turning ON the switch will apply logic HIGH on the mode pin and by turning OFF the switch position will put logic LOW on the mode pins Note The fourth switch is Not Connected NC and is notin use For Altera FPGA Module MSEL1 MSELO Passive Serial PS 0 0 JTAG 0 1 Users can use the selection jumpers J 3 amp J 8 provided on module to select the configuration mode For logic LOW short 2 3 and for logic short 1 2 for logic HIGH Jumper setting for mode selection Apart from mode selection pin settings user also has to selectthe programming pins for programming For Xilinx FPGA module J umpers Serial JTAG P4 P5 P6 P7 Short1 2 Short 2 3 For Altera FPGA Module Jumpers Serial JTAG 4 5 6 7 Short2 3 Short 1 2 69 ni logic Pvt Ltd Pune USDP User Manual Programming 89c51RD2 microcontroller Using the Flash Magic programmer designers can program the 89c51 controller After building the HEX file from compiler designers can refer the below shown steps to program the controller Insert the controller module on baseboard connect the serial cable provided to module and PC s serial port Turn ON the power supply now run the EXE of Flash Magic programmer on your PC The below shown window will open up Flash Magic File ISP Options Help 1 2 COM Port com 1
120. tion Group This group created the foundation for the IEEE work Set of specifications that enable board and chip level functional verification of a board during production Committee that established the Test Access Port TAP and boundary scan architecture defined in IEEE Standard 1149 1 1990 Liquid Crystal Display LCD The screen technology commonly used in notebook and smaller computers Logic The sequence of functions performed by hardware or software Hardware logic is made up of circuits that perform an operation Software logic is the sequence of instructions in a program Moore s Law An empirical law developed and later revised by Intel s Gordon Moore which predicts that the IC industry is capable of doubling the number of transistors on a silicon chip every 18 months originally every year resulting in declining IC prices and increasing performance Most design cycles in the electronics industry including embedded system development firmly rely on Moore s law Net List A computer file sometimes a printed listing containing a list of the signals in an electronic design and all of the circuit elements transistors resistors capacitors ICs etc connected to thatsignal in th e design PLCC Plastic Leaded Chip Carrier A low cost IC package usually square PLCCs have interconnection leads on either two usually only for memory chips or all four sides for logic and ASIC chips PLD Programmable Logic Device The generic te
121. tion of FPGAs shared 1 05 1 FPGA2 Input Input Allowed Output Input Allowed Input Output Allowed Output Output Not allowed ni logic P vt Ltd Pune USDP User Manual ACEX1K FPGA Pin detail Device PQ208 Clock amp Reset Clock 79 Reset 180 Note Resetis active LOW Configurable 1 05 LA7 36 LB7 46 LC7 60 LD7 70 37 LB6 47 LC6 61 LD6 71 LAS 38 LB5 53 LC5 63 LD5 73 LA4 39 LB4 54 LC4 64 LD4 74 LA3 40 LB3 55 LC3 65 LD3 75 LA2 41 LB2 56 LC2 67 LD2 85 LA1 44 LB1 57 LC1 68 LD1 86 LAO 45 LBO 58 LCO 69 LDO 87 7 Segments Display Enable Keypad Header segA 31 DISP1 18 SLO 8 3 segB 30 DISP2 16 511 13 RL1 11 segC 29 DISP3 17 SL2 9 RL2 7 segD 28 DISP4 15 SL3 14 RL3 12 segE 27 segF 26 segG 25 segDP 24 Parallel Port Connector DB 25 Parl 205 10 193 2 203 11 192 Par3 202 12 191 Par4 200 Par13 190 Par5 199 Parl4 189 Par6 198 15 187 197 16 186 8 196 Parl7 179 Par9 195 Pin 18 25 of DB 25 connector are gr
122. troller works on the configuration word setting the configuration word can be modified by clicking the change button on the Config option This will open a new window for setting the configuration word For the sample program the configuration word value is 3D32 in HEX which you can fill in the window and press write to write in the controller User can also make changes according to their design for changing the configuration word Config Word 11 1 DEBUG Bit Bit 3 PWRTE Bit 10 v Bit amp BODEN Bit2 WDTE Bit 13lv CPI 9 WRT Bit5 Iv CPI Bit1 M FOSCI Bit 12 v CPO Bit8 cpp Bit 4 v Bit 0 FOSCO Hex Value 3434 Read Write ID s 100 101 102 103 fo fo Read write Note The configuration word can also be included in the source code Step 5 Press Done on the above window and come back to main window Here set the following option Shown in the bottom picture Write code write data write config word Erase before write PIC16Fxxx Programmer TEST File Port Erase Options Action Controller Read all v Write Code 6F877 z v Write Data DEVAD 51 Write Write Config word Erase bef Write Config Verify Code Low Volt Prog 3032 Current File Activity HEX Exit Now the required settings are made to program the PIC microcontroller Now press the writ
123. ts interconnected via networks to each other and to memory sensors displays and other external devices It is often distinguished from general purpose or data processors in that is must operate in real time it often has a much higher data input rate and it usuall y must perform a higher percentage of mathematical often floating point operations Digital to Analog Converter DAC A circuit that translates a signal from a numeric digital representation used by microprocessors and microcontrollers into an analog signal Converts a digital word to an analog value EDIF Electronic Design Interchange Format A standard representation format for describing electronic circuits used to allow the interchange of circuit design information between EDA tools FPGA Field Programmable Gate Array An integrated circuit containing a large number of logic cells or gates that can be programmably configured after the IC has been manufactured Some FPGAs use fuses for this programming and others store the configuration in an on chip EEPROM or RAM memory Fuse programmed parts cannot be reprogrammed so they can only be configured once EEPROM based FPGAs can be erased and reprogrammed so they can be configured many times RAM based FPGAs can be reconfigured quickly even while the circuit is in operation 117 ni logic P vt Ltd Pune USDP User Manual Finite Impulse Response FIR An impulse response that has a finite number of nonzero values Often used
124. und the GCKO during programming J PDIS These four jumpers are used to disable the 7 segment displays J ust remove the jumpers to isolate to displays from FPGAs JPA JPB JPC amp JPD These jumpers are used to select the 1 0 mode of the LEDs Total 32 configurable 1 05 are provided on USDP baseboard To configure them as I P user has to insert the jumper in between and remove the jumper to make them as O P Power Headers J 8 amp J 9 There are power supply headers users can connect the SMPS to any one of these headers Two headers are provided just for the sake of convenience for connecting the SMPS from any of the directions SLOT SEL J P3 This is slot selector header User can use the provided selector card for selecting the slot Slot 1 Slot 2 Short 1 2 Short 2 3 PLD SEL J P2 This is PLD vendor selector header User can use the provided selector card for selecting the PLD vendors Xilinx Altera Short 1 2 Short 2 3 J7 Keypad Pin No Signal Pin No Signal 1 VCC 2 GND 3 SL3 4 SL2 5 SL1 6 SLO 7 RL3 8 RL2 9 RLI 10 RLO Programming Port J 6 User has to connect provided programming cable to this port and P C s parallel for programming of FPGAs 79 ni logic Pvt Ltd Pune USDP User Manual Board Idents In this section idents of all boards are shown users can refer this section for any component listing Configurable 1
125. urce code name feed_PIC vhd Pin lock file name feed_PIC ucf Source code for PIC Source code name disp_pic c Programming file name disp_pic hex Power Electronics Module Stepper Motor Controller Section Code description This source code can control uni polar stepper motors The code can control the direction speed and stepping of motor This can be done with the help of switches provided on board Working with code Insert he FPGA module on USDP slot connect the power module interface cable with FPGA through the parallel port connector provided Connect the stepper motor winding on the header J P8 while connecting connect the winding the same phase as mentioned on the motor Program the FPGA with the given source code and control the motor signals from the switches Source code for FPGA Stepper motor section Source code name stepper vhd Pin lock file name stepper ucf Relay section Code description This source code can control the relays provided on the power module User can turn ON the relay by providing logic High on the relay I P pins Working with code Insert he FPGA module on USDP slot connect the power module interface cable with FPGA through general purpose PCB or the parallel port connector provided In this case user has to take care of pin assignment Connect your application signals on the relay headers 7 amp JP9 while connecting take care for Normally Open NO Normally Close NC and Common
126. urity Bit 3 Execute 6 clks cycle Start On Line training classes for microcontrollers and embedded networking and Internetworking waw esacademy com fag classes Step 2 In the opened window go to communications tab and set the option High Speed Communication and 6 clock part _iFlash Magic ES File ISP Options Help Advanced Options mm x Communications Hardware Config Security Just In Time Code Misc Os High Speed Communications B clock part 12 clock part 3 Half duplex Communications Verify after programming Set Security Bit 1 Fil unused Flash Set Security Bit 2 Generate checksums Set Security Bit 3 Execute 5 clks cycle Stait On Line training classes for microcontrollers and embedded networking and Internetworking wWwWw esacademy com fag classes ni logic Pvt Ltd Pune a USDP User Manual Step 3 Now go to hardware config tab and set the option Use DTR and RTS to control RST and PSEN Also set the value by 100 ms and T2 by 200 ms now click OK and go back to main window Flash Magic ioj xj File ISP Options Help Communications Hardware Config Security Just In Time Code Misc Use DTR and RTS to control RST and PSEN Os Keep ATS asserted while COM Port open 3 We E 00 ms T2 200 ms He Asset and ATS while C
127. used for clock for RTC also this port pin is shard with base bus and by removing this jumper you can isolate the RTC from the base bus Analog 1 Header for inbuilt ADC I Ps for PIC controller Pinl ANO Pin2 AN1 Pin3 AN2 Pin4 AN3 Pin5 AN4 AN5 Pin7 AN6 Pin8 AN7 Pin9 Ground JP9 J P10 amp JP11 During programming the PIC controller short pins 2 3 and after programming the controller short pins 1 2 for using with FPGA 32 ni logic Pvt Ltd Pune USDP User Manual ADC DAC Module DAC O P J 1 Pinl DAC Channel 1 Pin2 DAC Channel 2 Pin3 Ground ADC I P J 2 Pinl ADC Channel 1 Pin2 ADC Channel2 Pin3 ADC Channel 3 Pin 4 ADC Channel 4 Pin5 Ground JP2 This jumper is for setting the reference voltage This module has onboard reference voltage generation to use that short 2 3 Power Electronics Module As there is no settings in this module for pin description and header information please refer pin assignment chapter General purpose PCB All the 1 05 of base bus are brought on this PCB User can build their custom circuit on the board and interface with any of the module pins with the help of headers provided on the PCB The I O numbering has been indicated nearby the headers users can refer the pin assignment chapter for further information about the bus desc
128. y 15 Troubleshooting Disclaimer Device Overview amp Datasheets 3 1 2 ni logic P vt Ltd Pune USDP User Manual Chapter 1 Introduction to Programmable Logic What is Programmable Logic In the world of digital electronic systems there are three basic kinds of devices memory microprocessors and logic Memory devices store random information such as the contents of a spreadsheet or database Microprocessors execute software instructions to perform a wide variety of tasks such as running a word processing program or video game Logic devices provide specific functions including device to device interfacing data communication signal processing data display timing and control operations and almost every other function a system must perform Fixed Logic versus Programmable Logic Logic devices can be classified into two broad categories fixed and programmable As the name suggests the circuits in a fixed logic device are permanent they perform one function or set of functions once manufactured they cannot be changed On the other hand programmable logic devices PLDs are standard offthe shelf parts that offer customers a wide range of logic capacity features speed and voltage characteristics and these devices can be changed at any time to perform any number of functions With fixed logic devices the time required to go from design to prototypes to a final manufacturing run can take

Download Pdf Manuals

Related Search

Related Contents

Brennenstuhl 1170200001 energy-saving lamp    アクリルシーリングライト・61W（M-FL61A）取扱説明書PDF  よくあるご質問  GermanMAESTRO MS-B1GA loudspeaker  À l`attention des : Distributeurs, personnels de bloc  Consulter le Manuel - Lacrosse Technology  

Copyright © All rights reserved. Failed to retrieve file