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1. lease ELECTMAP_D15 P d V GROUND gt 10_LOP_18 St SHECIMAP DIA 425V 25V Fixe 2 5 GROUND gt 1O_LON_18 AB6 SELECTMAP_Di3 9 10_11P_18 AB7 ___SELECTMAP_Di2 J43 aeons ieee AAS SELECTMAP_D11 S E ABS Dio R1335 1 Do Not Connect 2 MICTOR_CS15 GROUND gt IO_L2N_18 ACT SELECTMAP_D9 4 7K 3 t pes 4 MICTOR_CS14 10_L3P_18 Fany SELECTMAP D8 MICTOR_CLK_LO 5 3 GND 41 MICTOR_CLK AT 10_13N_18 yg SELECTMAP_D7 R1325 SELECTMAP_D15 7 5 ix cue 6 Ta 10_L4P_18 yg SELECTMAP_D6 4 7K SELECTMAP_D14 g ma D15 8 40 _MIGTOR DONE 10_L4N_VREF_18 apa SELECTMAP D5 SELECTMAP_D13 711 10 42 MICTOR_CCLK ORT TOLLSE 18 Fans SELECTMAP_D4 SELECTMAP_D12 13 1 12 74 MICTOR PROGn GROUND gt IO_L5N_18 Faag SELECTMAP D3 SELECTMAP_DT1i_ 15 13 14 6 CONFIG_EXTRATI 10_L6P_18 v7 SELECTMAP_D2 SELECTMAP_D10 12 16 8 CONFIG_EXTRATO e 10_L6N_18 ADS SELECTMAP_D1 SELECTMAP_D9 49 1 18 29 CONFIG_EXTRA9 10_17P_18 aes SELECTMAP DO SELECTMAP D8 24 19 20 Faz E GROUND gt 10_17N18 Hwe RS232 Ax SELECTMAP_D7 23 2 22 24 CONFIG_EXTRA7 GROUND gt 1O_L8P_CC_18 yg RS232_1X z SELECTMAP D6 25 23 24 Ts 7 1 00 IO L8NCC_18 HAE7 FPGA USER_RESETMA SELECTMAP_D5 27 25 26 28 CONFIG_EXTRAS ar 10_L9P_CC_18 Fare FPGA USER RESET E SELECTMAP D4 29 27 28 30 10_L9N_CC_18 FPGA USER RESETn ELEC TMAP_D3 29 30 ONFIG_EXTRA Se GROUN
2. 7 5 246 45 735 239 665 95 265 239 665 173 265 226 965 201 735 239 665 251 265 239 665 304 5 246 e e e oe o O e 4 45 735 49 165 201 735 251 265 49 165 0 0 267 75 149 801 25 298 815 144 555 266 185 115 195 263 75 101 75 x 304 5 3 4 The holes except for the SEAM mounting holes are 3mm They are all attached to gound on the board The back side clearance is 14mm The front side clearance is 1 75 The board thickness is 0 063 DNV6F6PCIE User Manual Page 69 173 265 239 665 123 735 239 665 304 5 246 251 265 239 665 201 735 239 665 173 265 226 965 95 265 239 665 45 735 239 665 7 5 246 ev o e e Y Le h L Ei 7 11 Tees a 45 735 144 415 i ke HER j A 267 75 149 29 131 301 25 298 815 144 555 2 065 135 445 Pl o 0 o iE A o 0 45 122 297 25 S a 266 185 115 195 0 85 3948 263 75 101 75 _ 0 Sau el 304 5 3 4 251 265 49 165 201 735 45 735 49 165 0 0 The above diagram is the same one as the one above it except that this one is reversed 3 24 POWER text 3 24 1 Power Headers There are two ingress points for power on the board They are both compatible with the so called PCI Express graphic
3. FPGA F im E 2 The SFP connector also has some low speed sideband signals which also attach to the FPGA These signals are fixed at 2 5V A dedicated oscillator is provided that has a random variety pack of frequencies You can select between these frequencies using the frequency select pins of the oscillator which are attached to the FPGA If the frequencies provided in the variety pack aren t appropriate you have one of the following options which I ve listed after this photo oon OO WT dddl dddl 2 44 23010 ORAS ARLE Al a 1 Replace the oscillator with a better one We will help you do this if you want 2 Use the CLK_MGT network The CLK_MGT network can be driven from a frequency synthesizer that can hit any frequency that the world has ever known The disadvantage is that then the entire CLK_MGT network must run at this frequency possibly limiting your options for the FPGA to FPGA interconnect 3 19 1 IIC There are sideband signals on the SFP They are attached to the FPGA You are expected to figure out what to do with them DNV6F6PCIE User Manual Page 62 3 20 ROCKETIO HEADER Brand new in Virtex 6 just for you we invented a new type of header the GTX Expansion Header Interface abbreviated S E A M There are three of these on
4. There is a block diagram of the NMB bus architecture above It is physically point to point from each FPGA to the configuration FPGA Each point to point connection consists of a 40 pin signal wire which are used as 20 LVDS pairs These pairs are further divided into 10 signals in each direction with 1 clock signals 1 control signal and 8 data signals The clock frequency of the interface happens to be 1GHz 500 MHz clock with DDR capture The theoretical throughput is therefore 1GB sec in both directions simultaneously to all 6 FPGAs simultaneously The protocol supports four channels demand mode bursts interrupts link detection some FIFO flags and maybe some other stuff The data to from the FPGA is stored in buffers in the DRAM of the Marvell processor 3 4 2 User Interface An HDL module is provided in the support package around here D FPGA_Rererence_designs code common nmb nmb_target_interface v There is hopefully a PDF in that directory that gives a much better description of how to actually use the interface But more or less the interface provides a simple Address DataIn DataOut type interface You should think of the interface as a memory space On the C side of the NMB there are simple functions like nmb_read address buffer size that can be used to view this memory space The code for this is found in the support package here D Host_software_applications Emu EmuLib dnapi h DNV6F6PCIE User Manual Page
5. 3 10 11 Marvel to NMB Bridge The NMB interface connects each user FPGA to the config FPGA The data that goes to and from the FPGA winds up in the Marvell CPU s DRAM Since the config FPGA has a PCI Express link to the Marvell Processor it is able to directly manipulate memory in the Marvell s DRAM The config FPGA has a DMA controller inside of it that pushes data directly from the FPGAs to the Marvell DRAM DNV6F6PCIE User Manual Page 52 Marvell Configuration PCI Express There is a bunch of detail about how to use this DMA controller that you don t need to know FPGA MAGIC NMBUS NMBUS NMBUS NMBUS NMBUS NMBUS FPGAA FPGA B FPGA C FPGA D FPGA E FPGA F documented in the PCIE DMA user manual PDF document You should not read this document 3 11 RS232 There is a pair of signals RX and TX for RS232 Serial communication to the FPGAs DNV6F6PCIE User Manual Page 53 AETR rA tle sdaas UART CPU and CF FPGA RS232 501 0200 0000 REV 1 CPU J31 1 2 3 ae 5 aN Led Es aL 9 10 TSM 136 01 T DV XXXX 50V 12V_R BW HSA Configuration FPGA RS232_MCU_TX RS232_TXD1 avion y PG MCU i 12V_ 1 2 63 RS232 MCU_TX lt R5232 CFPGA TX RS232_1XD 3 4 RS232 MCU_RX O ABU OD 7 3 MCU RS232_RXD1 45V 7 8 63 RS232_MCU_RX lt C Rs232 CFPGA RX AS232 RXD2 o x 10 DNI
6. SOP65P640X120 24N f GND vod Se CS854057 TSSOP20 FPGA C SRC The FPGA C should drive the signal CLK_USER_LEFT_OUTCp n differentially FPGAESRC The FPGA E should drive the signal CLK_USER_LEFT_OUTEp n differentially FPGAF SRC The FPGA F should drive the signal CLK_USER_LEFT_OUTFp n differentially SMA The user should supply a clock single ended or differential into the SMAs J5 and or J6 located near the top left corner of the board Voltage levels up to 2 5V are acceptable DNV6F6PCIE User Manual Page 21 IICA ON e PPIG i By OO eG UC tally AA ae so j et Stel dl 10 8000 851000 a Pida 3 3 7 Frequency only networks Frequency only networks are networks that are provided to all six FPGAs but do not guarantee low skew between the inputs to the FPGAs These networks should not be used for fully synchronous communication between FPGAs at least not without phase adjustment 3 3 7 1 MGT The MGT clock network delivers a very low jitter high precision frequency source to the MGT GTP GTX HTX tiles of all six FPGAs This clock is intended to be used only for the RocketIO interconnect between FPGAs however the clock is accessible for other types of logic inside the FPGA The MGT network can be driven at one of four different frequencies You can select the desired frequency from EMU Additionally you can run the MGT network at the same frequency as global clock GO This will allow you to
7. voltages driven by the hard drive will exceed 2 5V which is the maximum allowable voltage The pin out was selected because the cable is easy to obtain not because the FPGA is compatible with ATA 3 13 USER LEDS The FPGAs are all connected to LEDs which have the ON and OFF capability Some of them go through FETs q O ee tails ker a TEFAL PT af SS e n REEFS ORA ome 41153 3 E 3 3 3 g J ALN shinni ant alii ahini a MICARRAY a ds a Wer Diiverdbci There is not a lot to say aboa LEDs USER DEFINED LEDS 1 8mA 2 5V o Q16 LED Aro LED_Aq0 BSS138 3 2 SOT 23N_GSD 1 LED_AO Q17 LED_Ar1 LED Aq BSS138 3 2 SOT 23N_GSD 1 LED_A1 Q18 LED_Ar2 LED_Ag2 BSS138 3 2 LED_0603 SOT 23N_GSD 1 LED_A2 DS49 Q25 LED_Ar3 YELLOW LED_Ag3 BSS138 3 2 LED_0603 SOT 23N_GSD 1 LED_A3 DS50 Q32 LED_Ar4 YELLOW LED_Ag4 BSS138 3 2 LED_0603 SOT 23N_GSD 1 LED_A4 If you pulse a signal to them then they will be varying levels of brightness They are sort of yellow in color Other yellow items include sunflowers and fire 3 14 FPGA to FPGA ROCKETIO Most of the Rocket IO or MGT or GTP or GTX signals on the FPGA devices just connect to other FPGAs DNVe6F6PCIE User Manual Page 56 FPGA FPGA FPGA F E D Vitex Vitex Vitex LX240T LX365T LX240T LX365T 7 LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1 759 FF1759 FF1759 FPGA FPGA FPGA C B Virtex 6 Virtex4 V
8. Error Objects cannot be created from editing field codes Figure 2 Install Daughter card step 2 Mating can be started from either end Locate and match the connector s A1 position marking triangle for both the Plug and Receptacle Markings are located on the long side of the housing Rough alignment is required prior to connector mating as misalignment of gt 0 8mm could damage connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the plug housing with the Small alignment key of the receptacle housing and the large alignment slot with the large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by feel and when the receptacle keys start into the plug slots push down on one end and then move force forward until the receptacle cover flange bottoms on the front face of the plug Like mating a connector pair can be unmated by pulling them straight apart However it requires less effort to un mate if the force is originated from one of the slot key ends of the assembly Reverse procedure from mating Mating or un mating of the connector by rolling in a direction perpendicular to alignment slots keys may cause damage to the terminal contacts and is not recommended DNV6F6PCIE User Manual Page 39 3 7 10 Clocking Methods A wide variety of clocking topologies were considere
9. However you are not expected encouraged or allowed to understand any of the workings of this stack of software Host PC Virtex 6 FPGA Marvell CPU Config FPGA nimb_target_interface Some Software Linux DMA Some HDL Ethernet a driver PCI Engine Some HDL USB DMA Express driver Engine PCI Express Soret Virtex 6 FPGA nmb_target_ interface Clocks ON Some HDL DNV6F6PCIE On the host PC side you are expected to understand and use the interface provided by the file diniapi h found in the user package On the FPGA side you are expected to understand and use the interface provided by the file nmb_target_interface v The layers of software and hardware in between should operate transparently For no particular reason details are given here DNV6F6PCIE User Manual Page 87 1 Your C code calls nmb_write function in the diniapi h interface 2 The emulib library determines which of the three interfaces the board is connected on Let s assume ethernet 3 The emulib library creates a packet of data with a header and the data you supplied 4 Emulib sends the packet to the ip address of the board 5 On the board a program called DiniCmos is listening to that very same IP address It takes the data in the packet and drops it in the DRAM of the marvel 6 Over PCI Express the DiniCmos program sets some registers in the DMA controller in the configure FPGA 4 4 Marvel Environment The Marvell CPU is running a complete Linu
10. LX240T LX365T SX315T LX550T SX475T FF1 759 FPGA A Vitex LX240T LX365T SX315T LX550T SX475T FF1759 xew gor WAWIGOS yda DDR3 SODIMM 4GB Max The SODIMM interface is also potentially usable as an expansion interface for custom daughter cards DNV6F6PCIE User Manual Page 28 i ee eee p a mk FPGA cat ew T i 3 6 1 Memory Interface Generator The provided reference design uses a memory controller that is based on the memory controller that is produced by the Memory Interface Generator MIG part of the ISE software However it has been modified The modifications allow the use of dual rank DIMMs and also set some parameters automatically such are RAS and CAS latencies and total DIMM density Some of the signals that are connected between the SODIMM connector and the FPGA are not used by MIG These include the SODIMM NC no connect pins the upper two address pins the EVENTn pin Additionally the feedback clock is not used by MIG or the DDR3 controller provided by Dini Group If you want to use MIG you should use the HDL files produced by MIG and use the UCF file provided by Dini Group removing the unused signals 3 6 2 IO Standards The DIMM interface is voltage selectable When using DDR3 memory it is suggested to use the 1 5V IO voltage When using this voltage signals to the SODIMM should be of the IO Standard SSTL_I _18_DCI or SSTL_I_18_DIFF_DCI The nece
11. Use a CR2012 type battery in the socket RadioShack type 365 In order to change the battery without the loss of the encryption key you can attempt one of the following feats of daring Page 66 DNV6F6PCIE User Manual 1 Switch the battery out while the board is powered on 2 Switch the battery out while the board is plugged into the PCI Express slot of a computer that is plugged in but powered down 3 Attach some sort of external power supply to test point TP41 4 Switch the battery out in less than 10 seconds 5 Reprogram the encryption key after changing the battery 3 22 JTAG The FPGA JTAG chain of the Virtex 6 FPGAs is available for your use It isn t used by any other circuit on the board It just connects right up to a header that the Xilinx programmer cable connects to FPGA FPGA FPGA F E D Virtex 6 Virtex 6 Vinex S LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1759 FF1759 FF1759 FPGA FPGA FPGA JTAG C B A HEADER Virtex 6 Virtex 6 Virtex 46 LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1759 FF1759 FF1759 The order of the FPGAs on the chain is A B C D E F The configuration FPGA is not attached to the same chain as the user FPGAs Note that if you have ordered the board with fewer than six FPGAs the JTAG chain will remain unbroken however there will be a missing FPGA
12. 25 Hopefully there is also a PDF there that describes how to use it 3 4 3 Memory Spaces You should probably read the PDF describing dnapi h instead of this document D Host_Software emu Documents Emu_Manual pdf But here it goes The memory space is 64 bit Each address represents a single byte however the data is required to be read and written in blocks of 32 bit Addresses supplied to the interface must be divisible by 4 Therefore the bottom 2 bits of the address space are stupid Additionally since there are no chip selects on the NMB bus it is necessary to pre allocate address ranges for devices on the bus On this board there are six devices and the NMB address ranges that they are able to respond to on the bus are given here Target Starting Address End Address FPGA A 0x00000000_00000000 Ox00FFFFFF_FEFFFEFEF FPGA B 0x01000000_00000000 0x01 FFFFFF_FFFFEFFF FPGA C 0x02000000_00000000 Ux02 EEE RE EEE EEEEEEE FPGA D 0x03000000_00000000 0x03FFFFFF_FFFFFFFF FPGA E 0x04000000_00000000 0x04FFFFFF_FFFFEEFF FPGA F 0x05000000_00000000 Ox05FFFFFF_FFFFEFEFFF 3 44 Error Conditions Exist 3 5 FPGA Interconnect Most of the I O on the FPGA are used to connect each FPGA to other FPGAs Most interconnect is routed point to point between FPGAs in a nearest neighbor topology The exact topology is shown in the diagram below DNV6F6PCIE User Manual Page 26 FPGA FPGA FPGA F 58 E D Virtex6 Virtex 6 Vintex 6 E a A sin ao ne a le 65T
13. BOT HA a ET Ls ON Bit this is not reliable E a 62 63 AST_CPU_MPP13n lt lt a 4 3a y To00pF R1037 id riots ES Toco before POR ues one resent z aie ud A fe ae AST Porn Tey y f A Aon N la SUPERVISORY Or 4 MR qa seo A To CPU ross py om gasto 63 JTSASTM o C1893 2 6 Tavcacomcr EOF ono voo terr 180P65P400X130 8N Soa F i927 T foo 7 2 KAST PORN 69 Lo x LE To Spartan co CPU Only reset Y button Reset Push Button Changed aa agav sto from ve Used for R ar CFPGA First Oy mos scheme 64 AST_PEXOn_CPu lt R1025 68 RST CFPGA OUT lt lt Dni The SYS_RSTn button does not cause the power supplies to power down or the power up sequence to be repeated Here is a photo showing the location of the SYS_RSTn button 3 26 4 User Reset There is another reset button on the board called the USER RESET button It is located as shown below Stir Dee SE ey FPGA CICR a This button has nothing to do with the power monitors or power on All it does is assert the USER_RESETn signal to the FPGAs It can be used as a general purpose pushbutton by the user in the FPGA DNV6F6PCIE User Manual Page 76 The USER_RESETn signal to the FPGA is also automatically asserted by the configuration FPGA while it is configuring FPGAs After an FPGA is configured the config FPGA will de assert the USER_RESETn signal For this reason it is useful for the purpose of resetting your lo
14. CLK_USER_R FPGA E FPGA F FPGA B FPGA A CLK_USER_L FPGA D SMA 250MHZ 450MHZ CLK_MGT 312MHZ 156MHZ Synthesizer 2KHZ 700MHZ CLK_GO Configurable Synthesizer 2KHZ 700MHZ CLK_G1 Configurable Synthesizer 2KHZ 700MHZ Configurable CLK_G2 CLK_25 25MHZ Each of them is suitable for synchronous communication between FPGAs 3 3 3 Clocks G0 G1 G2 The clocks GO G1 and G2 are from a synthesizer that can produce any frequency from 2KHz to 700MHz with a 50ppm tolerance or better 25 25V as Ride TOOR ME A stront Fal il P BNI LECT ono vec ea cme cua fon General CLK Multiplier G0 LVDS Rita zame s Iw a o LVDS mos Ms nus 4 1 SYNTH XA G0 6 28 CLK Gop 100R 16 14 CLK G0 7 OND ps TALA YA CKOUTI o cuK o A LVDS cno BE yap pe STE e e ckouti He 1 clk nao ER E ae J TA 2EEONO TDOppm 1 PECL H Z a ao a A err ee of Feu g CLK GO C428 OtuF CLK GOp_r 16 34 join 9 o E A Aaa 1H ckints CKOUTZ RIS B noz H 9 CLKCGO Bn 44 FROM CONFIG FPGA sE saya bale sor zo wer clock 47K SE 3S Cuca a wi nos CLK GO Cn A A oea metwor AO ye os A SS beep 4 SS ckIN2 a E nag E CLIC On A2 voo os 60 FROM CONFIG FPGA ay il A muero Re 7 He v00 nos H SS clicoo es 44 Riba a RAD 3 PLL Loss Indicator T Yoo o G SS ELGO e R080 47K
15. LX550T SX475T 20 LX550T SX475T LX550T SX475T FF1759 FF1759 FF1759 o FPGA FPGA B A Vitex Vitex Vitex LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T MESA SX315T LX550T SX475T LX550T SX475T MESA LX550T SX475T FF1759 FF1759 i zd FF1759 40 40 ha 40 w Note that the interconnect that is drawn in a gold color in the diagram is only available when both connected FPGAs are either the LX550T device or the SX475T device If either FPGA is a small FPGA device then the signals are not usable This is because the small FPGA devices do not allow the use of all of the pins of the FPGA as I O 3 5 1 I O protocol The protocol for the use of the I O is user defined The VCCO pin of the FPGA on each bank that is used for interconnect is 2 5V This means that LVCMOS25 and LVDS are both reasonable choices for the IOSTANDARD attribute The board features necessary to use terminated standards such as LVDCI or SSTL are not provided on the board and so DCI cannot be used for FPGA to FPGA communication When using LVDS you can still use the DIFF_TERM attribute to terminate signals Since the global clocks on the board are delivered to each FPGA with low skew any of the global clocks are suitable for use for FPGA interconnect 3 5 2 High Speed interconnect The interconnect between FPGAs are divided into banks A single bank on one FPGA always connected to a single bank on one other FPGA This pairing u
16. R1435 pp 0R RST PEXON CPU c RST PEXn CPU 67 To battery x R1436 Yap DNI RST PEXON POR RST PEXAPOR 67 KEY B12 HCSL B13 neo Ace al CLK PEXO p0 e PEXO R p0 B14 C Gli CLK PEXO n0 PEXO_R_n0 B15 FEIRO REFUS d B16 La PEXO Tp0c C515 O tuF PEXO T pO PEX PRSNTn1 Bi7 GND PERPO PEXO T n0 c C516 O 1uF PEXO T n0 Big PRSNT2 PERNO PEXO R p1 B19 GND GND PEXO R ni B20 PETp1 RSVD B21 Ram ol _O 1uF PEX T pt B22 ene BENEI PEXO T mi 0 1uF PEXO Tni PEXO R p2 B23 SNE AND PEXO R_n2 B24 p B25 PETn2 GND PEXO T p2 c C519 0 1uF PEXO T p2 B26 GND PERp2 PEXO T n2 c C520 0 1uF PEXO T n2 ETE 827 GND PERn2 PEXO_R_n3 B28 EL ae J B29 PEXO T p3 c C521 O 1uF PEXO T p3 B30 oN pene PEXO T n3 c C522 0 1uF PEXO T n3 PEX PRSNTn4 B31 BSVD_ ne PRSNT2 GND 4 32 GND RSVD PCI_EXPRESS X 4 PCI_EXPRESS_X_4 Ea Note Use multiple power VIA s to connect 3 3V 12V to the voltage planes on the PCB The power pins on the PCI Express edge connector are left unused This is because they are super weak 3 24 2 Distribution Chart Power for the board is all derived from 12V Lower voltages are generated either directly by converting 12V DC input or by down converting another voltage that was down converted from 12V DNV6F6PCIE User Manual Page 72 Other 33y 5 5Ain DCF DCE DCD 2A 2A 2A2A 2A2A FANS g in xine iin 3Ax2V DIMMF DIMMD 3Ax2V 3Ax24 DIMMC DIMMA sax 1 1V_CPU 2 5V 222
17. REG_DC_RESET_IN eiin our H DAUGHTERCARD_RESET_POWERg 1p SS DALGHTERCARO RESET POWER Bee REG_DC_RESEJ ADJ 5 SHDNSENSE ADJ 2 Le Sid ELSIS C614 ce 3 4 R353 T 4 76 12V 0 1uF 6 GND NG ja 6 8K c3 c5 mene 4 7uF 0 1uF R372 LT1963AES8 508 6 04K Requires a GND area fill for thermal performance reference the datasheet 3 7 4 Power The DNV6F6 supplies power to the daughtercard at two voltages 12V and 3 3V Each pin of the Meg connector can supply no more than 1A of current so the effective power limit of the daughtercard is 2A x 12V 3A x 3 3V 33 9W It is strongly recommended that daughter cards provide a means of isolating series resistor their power net with the host board and provide a means of bypassing the power input with an external power connector On other Dini Group boards the pins C1 and H1 may be power pins On the DNV6F6 these pins are no connects The daughtercard should never be capable of supplying current back onto the host board on the 12V or 3 3V nets This could potentially damage the host board 3 7 5 VCCO Power The FPGA I O power pins are connected directly to the meg array daughtercard interface The intention of this design is for the daughtercard to drive the necessary I O voltage back onto the host board There are linear voltage regulators on the DNV6F6 that bias these power rails to 1 2V however it is not recommended that you use these to power the daughtercard I O These regulato
18. a tachometer The frequency of operation in revolutions per minute can be read from the EMU host software 5 0V Cooling Fan 2 5V Q C1391 FAN_TACH_ A R888 22 27 2031 22 23 2031 3 iia If your fans start to make noise they need to be replaced We will send you new ones 3 25 3 Temperature Sensors Each FPGA has a temperature sensor attached to it to measure the temperature of the FPGA code die temperature Since correct operation of the FPGA is not guaranteed by Xilinx when the core temperature increases above 80 degrees we helpfully reset the FPGA for you when the temperature hits 80 This behavior can be changed if you want but you ll have to call and ask us how 3 26 RESET There is a board wide reset circuit called SYS_RESET or SYS_RSTn or some flavor It s purpose is two and a half fold 1 Cause power supplies to come up in a particular order 2 Cause each device on the board to get a reset pulse after power is applied as required by the device datasheet with the minimum pulse width specified in the datasheet 3 Prevent the user from using the board if any power supply is off by even a little bit 4 Allow the user a way to reset the board to a repeatable state without having to power the board down and back up 3 26 1 Particular order The power supplies are allowed to supply voltage in a particular order DNV6F6PCIE User Manual Page 74 MONITOR e 10 Daughtercards DIMMS as E
19. are not installed the test will fail Before running the test may ask for the path to the bit files used to program the FPGAs A directory with an appropriate structure is provided on the user package in this location D FPGA_Reference_Designs Programming_Files DNV6F6PCIE User Manual Page 85 After the test s complete the program will print out a message like this NESHOT rocketio field test PASSED PARAR AAA ARA AAA EE HEHE HEF NESHOT CUSTOM TEST COMPLETE ocketio field test PASS KKXKKKKKXKXKKKXKXKKXKXXKXAKKXXKKKXKXKKKKXAkk USTOM TEST REP 1 1 PASSED NO200 DNV6F6PCIE 1003019 18 18 02 5 26 2010 GI GQ b OHO wow If the test stops or fails you may need to hit the q key to regain control of the EMU program 4 1 6 Command Line version The EMU program compiles into two versions The GUI version and the command line version Both versions can run in Windows or in Linux UST_CD DNY6F6PCIE Host_Software emu App Bin emu_ cmd wil Emu Version 1 0 9 compiled May 24 2616 Initializing HAHHAA EMU TEXT BASED UTILITY IEEE Compiled May 24 2616 Version 1 0 9 SELECTED BOARD NONE IEEE EEE EEEE EEEE EEEE EEEE EEE HHHH Main Menu HHOODOOODODODOODOODOODODODOOODOOODODODODOODODOOOOOODOOOADE Board Menu FPGA Menu Clocks Temps Menu Data Menu Test Menu Map Quit Enter selection The menu options in the command line version and in the GUI
20. not physically fit onto your Dini Group host board If you cannot fit your daughter card design in this form factor then you must examine the physical dimensions of the target host board to determine the maximum dimensions available For a larger vertical clearance between the host and daughter cards a vertical extender board is available The diagram below shows the vertical clearance when used with an extender DNV6F6PCIE User Manual Page 38 GND SIG Component Side j DAUGHTER CARD 5 5 5 Solder Side POX ES T Pin1 Meg Array Ema Receptacle 14mm p Meg Array Pin 1 Plug Pin 2 Lars 26mm Cll isl amy ra Pin2 Pin 1 Meg Array Receptacle 14mm PAS Array Jem P A pinz Solder Side DN9200K10PCIE8T Component Side GND FpcaA SG 3 7 9 Insertion and removal Due to the small dimensions of the very high speed Meg Array connector system the pins on the plug and receptacle of the Meg Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the Meg Array line up BEFORE applying pressure to mate the connectors Error Objects cannot be created from editing field codes Figure 1 Daughter card installation step 1 Place it down flat then press down gently
21. oe 2 5V MONITOR i 4 1 0V_CPU gt MONITOR 2 1 1V_CPU 2 3 3V MONITOR gt Button 43 1 8v JUMP Button MPP13 SYSRST Button gt PCIE Reset This diagram seems topical 3 26 2 Power supply failure detection There is a circuit on the board to detect when any of the voltages on the board falls below some minimum voltage 3 3V_SEQ 3V 12V_R o DS27 R315 a R441 19 1K GINA LT6700 3 RED 4 7K FAIL_3 3V FAIL_3 3V it PL TUF Bilal cura li _3 3V _3 3V q ae 2 e 5v Raso C695 0 1 F S 7 a If this happens the result is identical to holding down the SYS RST button A red LED comes on and the board won t work at all even lt lt SEQ_DISABLE_CPU_PWR 58 INB eav gt OUTB GND LT6700 3 SOT95P280 6N 3 26 3 Reset Button The SYS_RSTn button asserts the same signal that the power fail button does So hopefully it returns the board to the same state that a power on does DNV6F6PCIE User Manual Page 75 Power Supply Sequencer RESET saav seo Reset Circuit A Om gan seo gan seo azsa agav sea cim ee psss 2mA gles RED 4 3 3V_SEQ A Rr0a6 Ri0325 aro R1030 x E thi ft Recovery jumper in San MN one saav sea of verything alter ce spev cru st PWR FAULTn E Yee 7 RST EXT TPE a ur os adr een bon SPST PE
22. on t ZAI sensed E EDHI Testrowr PCle Power Cable 4A pin GN A Sense GND a accepts 6 pin or 8 pin T74 5558 0002 8A om connector al MOLEX 45558 0002 UPDATED TESTPOINT D2 DNI ps protection a Pow 7 rl Note Reverse polarity gu Ton oe protection qu Silkscreen 12V T a So you could use gt c53 CA TesronTt H2V_R ote UA ia BOE a only one cable GA _ Silkscreen 12v A place kind of far apart A La i c57 TESTPOINT from each other 1 inch or Tee A more Above is a schematic clipping to make this section seem more complete From it you can see that the power connector connects the power AN Aini Pate DNV6F6PCle A por ar a FPGA E omi a If you weren t able to locate the connectors on the board using the previously recommended look on the board method I have drawn a diagram above with big red circles around them DNV6F6PCIE User Manual Page 71 PCI Express Edge Connector DNI FUSE_0429 P4 B1 PEX PRSNTn R268 yy 0R PEX PRSNTn4 3 7mA Tse 12V PRSNT1 R269 YN DNI PEX PRSNTn1 Ba 12V 12V 4 3 3V LBS av 12V DS76 o U GND No A4 R263 B5 S G PEX LED A AA Bg SMCLK TCK VS B6 PEXO_TDIO 7 OMDAT mo 475R RED 4 55 GND TDO 3 3V_PEXO Bs Na Po LED_0603 P B TRST 43 3V 3 3V_PEX0 Silkscreen PWR FAIL 8 3 3VAUX_PEXO H QQ VAUX 33V Bit Save pN PROPER
23. select any frequency that exists in the world 3 3 7 2 CCLK The CCLK pin on the FPGA or the configuration clock is used by the config FPGA to send configuration bitstreams to the FPGA over the selectmap bus It is not a free running clock but has a minimum period of 20ns It can be used in the FPGA in conjunction with the STARTUP_V6 primitive This clock is not configurable DNVO6F6PCIE User Manual Page 22 3 3 8 Local Networks Local networks are networks that are only delivered to a single FPGA 3 39 CLK_TO_ Some FPGAs have signals that connect from on FPGA to another FPGA s global clock input pin These signals are single ended and are called clk_to_ where is either A B C D E or F These can be used for forward a clock from one FPGA to another without having to use local routing within the FPGA The utility of this does not exceed 3 utils 3 3 10 Spartan TP There is a test point connected to at least on clock input of each FPGA There is no known use 3 3 11 Daughtercard Feedback Each FPGA that has a daughter card connector also has a signal that loops back from an FPGA output to a clock input of that same FPGA The routing length of this signal is the same as the routing length of the I O signals to the daughter card The purpose of this is so that it is possible to have a clock in the FPGA that is phase aligned to a clock arriving at the daughter card The signal is called DC _FEEDBACK_P N 3 3 12 DIMM Feedback S
24. to 5PM from Monday through Friday excluding USA federal holidays Support is available in English Support for boards purchased through distributors can additionally be provided by the distributor Distributors are listed in the ordering information section Telephone USA 858 454 3419 Formal technical support support dinigroup com Expertise Name Email Ext WoW Class Level Schematic David Palmer dpalmer dinigroup com 30 Jester 30 Verilog Jack Fan jack dinigroup com 22 Rogue 14 Sales Mike Dini mdini dinigroup com 11 Barbarian 8 Production Dela tats Cruz dela dinigroup com 15 Sorceress 44 Quantum Physics Ivan Yulaev ivany dinigroup com 12 Wizard 19 Host Software Neal Harder nharder dinigroup com 28 Paladin 21 Marvell Software David Palmer dpalmer dinigroup com 30 Jester 30 DNV6F6PCIE User Manual Page 6 14 Errata The circuit board is currently in revision number 02 Errata exists for revision 01 of the circuit board Issue IDE connector doesn t physically fit on the ACCESS A header Solution You must cut the key off your cable connector Issue Real Time clock does not keep time between power down cycles Solution None Issue Board may not power on immediately after powering off When this condition occurs the board will remain in a reset condition and will be unusable Solution You may need to wait up to 5 seconds after powering down the board before it can be powered on again DNV6F6PC
25. 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 etc 3 21 ENCRYPTION The Virtex 6 FPGA allows the use of encrypted bit files You would want to encrypt a bit file 1f you want some person to pay you for the use of your IP per instance or something I don t know why DNVe6F6PCIE User Manual Page 65 In order to support encryption we have provided the necessary battery on the board This battery supplies voltage to the VBATT pin of the FPGA even when the board is off It also provides power to the VBAT pin of the real time clock on the board Note that the real time clock does not work on revision 01 of the circuit board The above photo shows where one might install a battery on the DNV6F6PCIE Backup Battery Linear Regulator 2 5V Y 1uA ov R891 DNI D13 BAS40 05 SOT23 VBATT SOT96P240X110 3N U78 9 3 VBATT_PRE i 4 ify our ES VBATT_BAT A VBATT_EXT C1369 2 en A al a 1 Fa m 4 7ul 2 GND GND 4 el 64 3 3VAUX_PEXO lt lt D12 i TPS78225 SOT23 5 a a eel BAS40 05 SOT23 E yal SOT95P280X110 5N all am SOT96P240X1 10 3N i TESTPOINT L KEYSTONE 3001 ale Silkscreen VBATT_EXT Silkscreen CR1220 i Accepts 3V Laser BR1220 1 This circuit makes the section look more complete
26. 1 8V_CPU 4Ain AMPS 1 0V_CPU Intercon 1 0V_V5T a Above I have provided a chart that shows where the current comes from for each power supply I doubt there is any reason for you to use this chart 3 25 HEAT This board gets very hot 3 25 1 Total thermal performance The heat sinks that were installed on the board before you removed them were each capable of dissipating one Watt for every degree in Celsius that the FPGA under it raises above the ambient temperature For example if you are using the board in a room at 25 degrees and you configure one of the FPGAs with a design that uses 31 Watts the core temperature of the FPGA will rise by 31 degrees for a total temperature of 56 degrees You can use the Xpower tool in Xilinx to determine how much power your FPGA design uses The amount of power that your FPGA uses may limit the maximum ambient temperature that your board can operate in The FPGA is not guaranteed to function properly at core temperatures above 80 degrees C For example if you put the board in a computer case with the lid closed and the temperature inside the computer case is 65 degrees C then the maximum power that your FPGA design can use and still operate reliably is 15 Watts Note that ambient air near the board temperature measurements must be taken at full power DNV6F6PCIE User Manual Page 73 3 25 2 FANS The fans that are sitting on top of the heat sink are plugged into the board for power They have
27. 1801 J26 J29 1 HEADER 5 84 J27 1 USB Type B 1156 J28 1 10 88 1201 JTAG 20Pin_WITH_SHROUD 994 J33 1 JOG 0059NL RJ45 2517 J34 1 TENTH_INCHES 2150 J39 3 SEAM 20 03 5 S 08 2 A 2723 J40 J41 J42 1 2 767004 2 1149 J43 3 31 CHARACTARIZATION REPORTS 3 31 1 PCI Express Speed 3 31 2 Ethernet Speed 3 31 3 Interconnect Speed 3 31 4 Rocket IO Speed 3 31 5 DDR3 Speed 3 31 6 SATA Speed 3 31 7 USB Speed 3 31 8 Marvel CPU Speed Floating point 1 3 GFLOPS DNV6F6PCIE User Manual Page 80 3 31 9 NMB Speed 3 32 UNUSABLE PINS text 3 32 1 configuration dedicated 3 32 2 VREF 3 32 3 no connect 3 32 4 dci this is some text DNV6F6PCIE User Manual Page 81 4 Software Using the board requires configuring FPGAs setting board controls such as clock frequency settings and transferring data on and off board For these purposes software has been provided The best place to find details about the Emu software and programming API is in the user package here D Host_software_programs Emu Documents Emu_manual pdf 4 1 Emu host software In the user support package here D Host_Software emu App There is a program called EMU It can be used on Windows or Linux PCs This program allow you to control the board USER_L 0 000 FPGA A SRC USER_R 259 799 FPGA C SRC MGT 312 519 312 MHZ Dir Group EMU loj x File Board FPGA Clocks Temps Data Test Help Auto Update I Board Interface _ Refresh DNO200_DNV6F
28. 32 The config FPGA passes through the user s RS232 signals to the RS232 buffer 3 10 4 Count Clocks All of the boards global clocks are connected to the config FPGA The config FPGA measures the frequency so that software can report it 3 10 5 JTAG The config FPGA has a dedicated JTAG chain and connector that can be used with the IMPACT program from Xilinx It has no purpose 3 10 6 Device Bus The config FPGA has a device bus interface connected between it and the Marvell CPU In this way the CPU can access the config FPGA as a memory mapped device This interface serves no purpose on this board 3 10 7 Blink LEDs The config FPGA is connected to 6 green LEDs It blinks these LEDs incessantly The LEDs have no purpose or meaning 3 10 8 Controlling Clocks The control signals for the global clock synthesizer chips and the multiplexer chips are conncted to the config FPGA Software is able to set these control siganls 3 10 9 Clock MUX The config FPGA serves as one stage of multiplexers for the clocking network On the schematic you may see that clocks GO G1 and G2 come from the config FPGA The config FPGA drives out clock signals coming from the user FPGAs on the TO_SPARTAN wires depending on software settings 3 10 10 Configuring the FPGAs The configuration FPGA is connected to the selectmap configuration bus of the six user FPGAs It uses this bus to configure and read back the configuration data of the user FPGAs
29. 6PCIE 1003019 Ethernet MT RE CLOCKS ra Hs FE co gt 100 005 DAVEE SC DIME RT bo E Synthesizer Ps gt d i Gl 100 003 a gt 1 Synthesizer El Al Gz 200 013 7 e i Synthesizer Clear Save Text FullScreen Auto Scroll Vv Welcome to Emu DNV6F6PCIE User Manual Page 82 The window shown above the main window of EMU ca kirin CUST_CD DN 6F6PCIE Host_Software emu App Bin emu_cmd_ wi Emu Version 1 6 9 compiled May 24 2616 Initializing ASOC EMU TEXT BASED UTILITY IEH EEE Compiled May 24 2616 Version 1 0 9 SELECTED BOARD NONE HAHAHAHA HHHH Main Menu HH Board Menu FPGA Menu Clocks Temps Menu Data Menu Test Menu Map Quit Enter selection There is also a command line version of EMU 4 1 1 Selecting a board To connect to a board using the EMU program make sure the board is connected to the computer either over Ethernet USB or PCI Express If the board is connected to Ethernet make sure the network supports DHCP or else you may not be able to connect to the board When using USB on Windows a USB driver must be installed before the EMU program can detect the board The Windows USB driver is located here Host_Software emu Drivers win32_usb You are expected to know how to install a windows driver using device manager Linux does not require a USB driver When using PCI Express on Windows a PCI Express driver must be installed before the EMU pro
30. As When one or more of the FPGA locations is populated with a LX360T LX240T or SX315T the some features of the board become unavailable This is because these three FPGAs have fewer I O than physically exist on the 1759 pin BGA package The on board devices that the unused physical package pins are connected to cannot be used if the populated FPGA is one of these small FPGAs On the product block diagram signals that may be unusable due to small FPGAs are colored orange Below there is a copy of the block diagram with all orange signals removed The block diagram below represents the features available on a board even if small FPGAs are selected 128Mb 128Mb Flash Flash 96 z 96 ES 96 ps ES e E E E ES A 4 GTX FPGA FPGA FPGA F E D Header Synchronous Clock SATA II Networks device host GTX Expansion User selectable source and frequency HUN 130 Virtex 6 Virtex6 Virtex 6 LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T SX315T DDR3 SODIMM 4GB Max xew gor WWIGOS sya FF1759 FF1759 FF1759 FPGA Q Virtex 5 Config FPGA 1 X19 12 130 xen gor WINIGOS Haa FPGA Cc en PCI Express 23 100 A os Virtex 6 Vi B x6 PEA Virtex 6 1Gb an LX240T LX365T LX240T LX365T LX240T LX365T Ethernet y Marvell go SX315T SX315T SX315T
31. D gt IO_L10P_CC_18 ae a 2 3 31 32 2 s E 3 EX amp crou D 0_L10N_CC_18 we FPGA USER RESEM E SELECTMAP DT 35 33 34 36 od 1O_L11P_CC_18 y7 FPGA_USER_RESEIn F SELECTMAP_DO 37 35 36 38 CONFIG _EXTRA0 ES m 10 L11N7CC_18 MARS FAN TACH A 37 Do DH 38 GROUND gt 10_L12P_VRN_18 AGs FAN TACH BT l 10_L12N_VRP_18 i TACHI a GND LOC ax E 101187718 ii FAN TACH E D gt CONFIG_EXTRA 11 0 3 68 41 GND GND a no 10_L13N_18 GND GND 8 113N_18 AH7 FANCTACHO Esa 10_114P_18 FaqG7 FAN TACHF 2 767004 2 10_L14N_VREF_18 Wio FANTACH_CFPGA CONN_MICTOR38 ar 1O_L15P_18 W9 FAN TACH CPU 10 115N_18 aj7 wICTOR CLK Li gm IOLLteP i8 HAR MCTR CSES GROUND 0_L16N_18 yg MICTOR CST4 ES 10_L47P_18 NE HI o 10_117N_18 Ak7 MICTOR RDWR ma 10_118P_18 Aks MICTOR DONE UN GROUND 40_L18N_18 y3g MICTOR_CCLK an 10_L19P_18 yg MICTOR_PROGn 10_L19N_18_ veco_is Hace ee VCCO_18 agg VCCO_18 XC5VLX50T 85T 110T SX50T SX95T vu FPGA A 10_LOP_GC_24 A IO LON GC 24 W30 I1O_L1P_GC_24 aga IO LIN_GC_24 Aggy SELECTMAP_D15 1O_L2P_D15_24 AF31 SELECTMAP D74 1O_L2N_D14_24 T30 SELECTMAP D13 1O_L3P_D13_24 R30 SELECTMAP_D12 1O LSN D1224 Lay Dit 10_L4P_D11_24 Fara SELECTMAP D10 10_L4N_VREF_D10_24 0 LSP Do 24 1 N39 SELECTMAF DY l0_L5P_D9_24 p33 SELECTMAP_D8 IO L5N D8 24 FAJ33 7 1O_L6P_D7_24 aHag SELECTMAP_D6 10_L6N_D6_24 P32 SELECTMAP_D5 10_L7P_D5_24 R33 SELECTMAP D4 10_L7N_D4_24 Fe
32. Dm Algorithm Acceleration Logic Emulation SIC Verification User Manual DNWoF6PCIE DNV6F6PCIE User Manual DOCUMENT PATH C work dncvs Boards DN0200_DNV6F6PCIE Documents Manual DN V6F6PCIE_manual_rev02 docx LAST SAVED BY dpalmer on FULLSAIL LAST SAVE DATE 8 2 2010 12 32 00 PM Contents 1 INTRODUCTION ccsesssesssconesasecsvesssnensectvassvssavusesadapedveacavsssesesssccnsvassasnsrsdendessavensvanendrivscansesecsesssaesserdseassssseensy 5 1 1 AUDIENCE vas diia 5 1 2 CONVENTIONS cisse cies ides ssdassicchyadavdaidetcoa dardo dd irlanda dnd teria ica 5 1 3 AS cestuundlveselienes aade a aara dad eaaa aai onai aaro daai sates 5 2 QUICK START GUIDE icsssssissescencssassvesssacencsseconvesanccsedssvasasdcenseasceendesessssdecnsdscscausscocsassdecsedesdsassiesdadsssecdenteseseatss 8 2 1 STEPS iO ROLLOW tes tech oa Soalee et O O O E 8 3 NR cevseteasseask aacseccseaces seuss ceeseeasedessdcaeseccveacssdenescasscuates 15 3 1 OVERVIEW csi ini id 15 3 2 VIRTEX OPA uti e a ia 16 3 3 ELOEK RESOURCES rara nia ci a E tae ad 18 3 4 N MIB BUS cvs la E el teuandia decayed deaiedesdaecaehadbeancbete vaved iaceecasdaasieeldcayabadaesaanteas 24 3 5 FPGA INTERCONNECT secsscarvccusvenseeidcasaiadsedcedsegdesaaasevegs causa dn adaa eaaa a aaa le ada dde cata 26 3 6 SODIMM DDR3 CONNECTORS un soeerocesiionk ue riaenian nena n EE odeus cavdsbun sev svaehcen ovenesau savedvensisevsuavevedeledevesaxevgedsedtvee 28 3 7 DAUGHTER CARDS vecscisisscswctevsci
33. FPGA A FLASH 128Mbit FLASH_A QINr R1021 i 100R pas 1K R1022 A R983 4 7K FLASH_A DOUT FLASH_A_CLK 2 5V 0 FLASH_A_CSN 4 7K_FLASH_A_WP 4 7K_ FLASH_A HOLD M25P128 5016 SOIC127P1030X265 16N The interface is SPI The SPI signals are at 2 5V levels DNV6F6PCIE User Manual Page 58 FPGA F Virtex 6 LX240T LX365T SX315T LX550T SX475T 9 FF175 FPGA C Virtex 6 LX240T LX365T SX315T LX550T SX475T FF1 759 FPGA E Virtex4 LX240 T LX365T SX315T LX550T SX475T FF1759 FPGA B Virtex4 LX240T LX365T SX315T LX550T SX475T FF1759 FPGA D Virtex6 LX240T LX365T SX315T LX550T SX475T FF1759 FPGA A Vitex LX240T LX365T SX315T LX550T SX475T FF1759 If this block diagram is correct there are four SPI flash chips at your disposal The part datasheet provided is a fascinating read 3 16 USER TEST POINTS Each FPGA has a single test point attached to it They are located on the SELECT_MAP page of the schematic It has no known function 3 17 Mictor Connector There is a Mictor connector on the back side of the board It can be used for logic analyzers The only signals that you can actually drive from an FPGA are SELECTMAP 8 SELECTMAP 15 The rest of them cannot be used because they are driven from the config FPGA at all times DNVO6F6PCIE User Manual Page 59 Confi iei FPGA g Open drain Config Mictor
34. IE User Manual Page 7 2 Quick Start Guide This section will walk through an example session using the board 2 1 Steps to Follow Follow them 2 1 1 Examine Contents of Box The box containing the product should have come with the following units O DNV6F6PCIE board O RS232 serial Cable O DB9 to IDC cable adapter O Two PCI Express power cable adapters O USB Stick containing user support package DNVe6F6PCIE User Manual Page 8 O USB Stick containing FPGA bit files and a shell script CJ PSU starter device 2 1 2 Before you power on Place the board on a clear desk with static control padding You can use the silver colored bag the board comes wrapped in as a static control surface Make sure you neutralize the static in your fingers with the surface before every time you contact the board 2 1 3 Install the board in a PCI Express slot This step is optional During the course of your project if you intend to control the board using PCI Express then you should complete this step The board fits into any 4x 8x or 16x PCI Express slot Make sure the computer is powered off when you install the board into it It is recommended that you have the computer laying down so that the DNV6F6 is oriented vertically to reduce physical stresses on the board 2 1 4 Connect Ethernet Cable This step is optional During the course of your project if you intend to use Ethernet to control the board then you should complete this s
35. K Ea R96 TK E Reserved pins no defined behavior 25 1 10_CC_PO 1OZCCANO 5 o 3 1OZCCANI 10742 107N2 107P3 10783 107P4 107N4 107P5 107N5 10776 107N6 10747 107N7 RESERVEDI RESERVED RESERVED RESERVEDO Host must accept these as clock Required PLL is okay ORCC undefined VECO tolerant Nobody may drive signals above this voltage Host board drives pover rails Unregulated Voltage 120 nominal YX is deiven fcom Host bowed Mo caps on Host boscd 2 E 2 RX Ap RCASn REFCLK_A0p REFCLK_A0n REFCLK Alp REFCLK_AIn TK_BOp TCBON RX_B0p RXCBOn TKBIp TBI RX Bip RXBIn TK B2p DCBIn RX_B2p RXCB2n TK_B3p DBn Ex is deiven from Host bowed Mo cops on Most hosed RX_B3p RICB3n REFCLK_80p REFCLK B n REFCLK_B1p REFCLK Bin GND GND GND FPGA A u0 36 COV240T S60T_FFI759 4 A NH momo 118 MGTTXNOL118 i T SENKA FH MGTRXPO_116 MGTRXNO_116 GTP SEMA Ae m MGTIXP1_116 MGTTXN1_110 SE NS motexe1_t1s MGTREFCLKIP_116 H MGTRXN1_116 MGTREFCLKIN_116 5 GTE SEMAT tH morne2_116 MGTTXN2_116 Sr SEA Re H morrxe2_118 moTREFCLKOP_116 HMB MGTRXN2_116 MGTREFCLKON_116 TP_SEAMA DU s0 CTE SEAM DOE E MOTIFS 116 MGTTANS116 MAR SH MO
36. LDO G2___ gt p auGHTERCARD_RESET_POWER 36 39 DCDCO_CAP co K20 VCCO_CAP RSTn_3 3_ TOLERANT da gt gt DAUGHTERCARD_RESETn 36 39 C59 1uF I PLUG MEG_400_Plug_Stratix3_30 3 7 2 IO Electrical The part number of the connector part installed on the DNV6F6 is 84520102LF from FCI It is intended that the part number that will be used to connector to this board is the FCI 74390 101 part The part 84520102LF is called the plug and the 74390 101 is called the receptacle The DNV6F6 is the host side of the interface The mating card is called the daughtercard All signals from the FPGA to the connector are length matched to each other with a minimum tolerance of 50ps on all Dini Group host boards All Dini host boards route the FPGA I O signals as 50 ohm transmission lines It is recommended that daughter cards provide a bypass capacitor between the pins BO0_VCCO B1_VCCO B2_VCCO B3_VCCO B4_VCCO and ground close to the connector pin on the daughter card Note that Virtex 6 is incompatible with 3 3V I O signaling completely 2 5V is the maximum supported I O voltage If you require 3 3V I O you must use voltage translation devices 3 7 2 1 _V pins Any pin name that ends in the string _V is a VREF pin DNV6F6PCIE User Manual Page 33 For some settings of the FPGA I O attribute IOSTANDARD you are required to supply a 1 2 VCCO voltage onto the VREF pins of the FPGA If a daughtercard requires one of these IOSTANDARD s
37. NV6F6PCIE User Manual Page 96 7 ORDERING INFORMATION text 7 1 Part Number text 7 2 Howto Order text 7 2 1 International Offices China Rm505 R amp D Complex Qing Hua Xin Xi Gang Nan Shan S amp T Industrial Park Shenzhen China TEL 86 755 8618 6718 FAX 86 755 8618 6700 Email sales Oe elements com TEL 86 10 82757632 FAX 86 10 82756745 Europe Name Address Phone Email India Intrinsic Solutions 2145 17th Main 2nd Cross HAL 2nd Stage Indiranagar Bangalore 560008 TEL 9 1 80 41 15 1400 FAX 91 80 41 15 0797 E mail sales intrinsic in http www intrinsic in Indonesia DNV6F6PCIE User Manual Page 97 Advinno Technologies http www advinno com Israel ISROTECH The FPGA and SoC House Office 972 0_72 2342181 Mobile 972 0 54 4 805 791 Fax 972 1538 9285271 Email info Oisrotech com Web www isrotech com Japan Applistar Corporation 3050 Okada Atsugi AXT Main Tower 3F Atsugi 243 0021 Japan TEL 81 46 227 3288 FAX 81 46 220 2901 http www applistar com Korea MDS Technology 82 2 2106 6000 15Fl Kolon Bilant 222 7 Guro3 dong Seoul Korea 152 777 http www mdstec com Singapore E Elements Technology Pte Ltd 21 Science Park Road 03 16A The Aquarius Singapore Science Park II Singapore 117628 TEL 65 6777 2240 FAX 65 6777 2249 Email sales e elements com Svalbard Knytte et tau rundt en elg Knytte den andre enden rundt din hals Skremme
38. Project files and batch script files that use DNV6F6PCIE User Manual Page 5 ISE to build the designs are also provided These example files can be use to quickly create working bit files for the FPGS The reference design implements every feature on the board including DDR3 memory RocketI O and others You are free to adopt any of the device controllers used in this reference design For most customers the most interesting part of the reference design will probably be the UCF file which contains a list of all the usable signals connected to the FPGA and the correct IOSTANDARD attribute to use with each 1 3 4 Schematics and Netlist This user manual fails to list specifications for all of the devices connected to the FPGAs and so to correctly use them you will have to refer to the device datasheet and the schematic The schematic is provided in PDF format If you need a machine readable format you can use the provided ASCII netlist of the board The ASCII netlist contains only nets on the DNV6F6PCIE that are connected to usable I O on the FPGA 1 3 5 Device Datasheet Library There is a PDF datasheet provided for every part used on the board It is in the user support package 1 3 6 Xilinx Questions about the use of Virtex 6 FPGAs or ISE that aren t specific to the DNV6F6PCIE should be directed to Xilinx 1 3 7 Board Models 1 3 8 EMAIL AND Telephone Technical support Phone support is available pacific standard time from 9AM
39. S 10_L10P_MRCC_25 DCD Bo Po H3_ 80_N8_GCC_BUS 10_L10N_MRCC_25 DCD BONS G4 B0_P9 10_L11P_SRCC_25 DCD_B0_P10 H5 80_N9 10_L11N_SRCC_25 DCD BO NTO Gs 80_P10 10_L12P_25 DeD Bo Pn H7 B0_Nt0 10_L12N_25 DCD BO NTT G8 Bo_P11 10_L13P_25 DCD_B0_P12 Ho B0_N11 10_L13N_25 15 Go 80 P12 10_L14P_25 1 DNI DCD_BO P13 CC H11 BO_N12 10_L14N_VREF_25 J DCD BO NIT CC 612 B0 P13_CC 10_L15P_25 DCD_B0_P14 H13 80_N13_CC 10_L15N_25 50R 3 DCD BO NTF G14 B0_P14 10_L16P_VRN_25 50R DCD B0 P15 H15 80_N14 H42 10_L16N_VRP_25 YM DCD BONIS Gig BO_P15 Jag VCCO_25 10_117P_25 N31 DCD BO NTZ DCD_B0 P16 H17 BO_N15 K36_ VOCO_25 10_L17N_25 J42 DCD B0 P8 GCC BUS DCD_B0 N16 Gig B0_P16 L33 VCCO 25 10 L18P_GC_25 f k42 DCD B0 N8 GCC_BUS DCD_B0_P17 Hig_ 80_N16 m30 VCCO_25 10_L18N_GC_25 P30 DCD B0 PO GCC DN DCD_BO_Ni7 G20 BO_P17 728 VCCO_25 10_L19P_GC_25 P31 DCD B0 NO GCCDN B0_N17 VCCO_25 10_L19N_GC_25 a XC6VLX240T 5501_FF1759 2 DCD_BO_VGCO 33 4 a a AS Bo veco C846 Le C731 C684 C640 C639 C683 c46 NX eu 7 iuF 4 7uF 4 7uF 4 7uF 4 7uF 4 7uF 4 7uF ur MEG_400_Plug_Stratix3_30 L E R478 100R DCD B0 P8 GCC BUS g R479 AN 100R R481 100R pan MS DCD B0 N8 GCC BUS R480 100R R455 An 100R J DCD B0 PO GCC DN R486 Yap 1008 R484 100R DCD BO NO GCC DN J R485 WYN 100R pl 3 7 7 Net Lengths All daughtercard signals are matched between 60mm and 80mm This corresponds to a maximum signal
40. S69 DS70 DS71 DS74 DS76 7 BLUE 1929 DS55 DS56 DS57 DS58 DS59 DS60 DS75 8 GREEN 1928 DS61 DS62 DS63 DS64 DS65 DS66 DS72 DS73 DNVO6F6PCIE User Manual Page 77 3 29 TEST POINT REFERENCE LIST The following is a list of all test points on the board in order of when I thought of them Reference Comnection Description Designator TP1 TP74 TP10 12V Used to connected 12V rails on board into single large super 12V rail You should not use this for any reason TP15 CLK_USER_LEFT Used to measure frequency of global clock TP57 CLK_25 Used to measure frequency of global clock TP31 CLK_MGT_INTERCON _ Used to measure frequency of global clock TP41 VBATT_EXT Used to insert external backup power for encryption and real time clock TP42 VBATT Power Should be 2 5V TP58 1 0V_C Power Should be 1 0V TP53 1 0V_B Power Should be 1 0V TP63 SYS_RSTn Main reset of the board Low is active TP54 1 0V_MGT_AD Do not use this for any reason TP65 CLK_G2 Used to measure frequency of global clock TP66 CLK_G1 Used to measure frequency of global clock TP68 CLK_G1 Used to measure frequency of global clock TP70 CLK_GO Used to measure frequency of global clock TP60 1 0V_A Power Should be 1 0V TP13 1 0V_F Power Should be 1 0V TP14 1 0V_E Power Should be 1 0V TP16 2 5V Power Should be 2 5V TP61 RST_CPU For probing the CPU reset Should be the same as SYS_RST DNV6F6PCIE User Manual Page 78 TP81 ETH_TSTP Unknown pur
41. SYNTH INC G0 20 cae od lio 18 O er ero Ua R107 yy ATK SYNTH DEC GO 19 NC 18 SYNTH LOL GO ZA _SYNTH_LOL_G0r SND OT ras AN FROM CONFIG FPGA DEC tot GND no CLKCGOZCFPOAR 68 sel RED a Dur GF GE 1esensos AS FROM CONFIG FPGA loo LED_0603 SOPO5PO40X120 24N RIE AIK SYNTH CMODE 6038 S04 SD Silkscreen Peco LoL RIE VVK YNTE A o 2e 0 2 A ne H RIET NVA YATE A D3 Ne 19mA FROM CONFIG FPGA TEEN E ESZCA NC pag Ale NC PE vn RSU A 5 25 SYNTH oo Rioga 317 SND veo E tempem tr cant ane SND oan vs A o pl Lir Cuert Note Serial Port set for 12C mode F TIFN F Foie CS_CA O Select CKIN1 CM DE 0 120 Mode OF NSOPE0OXB00XS0 37N I2C A 2 0 1101 000 DNV6F6PCIE User Manual Page 19 The synthesizer used is a high performance low jitter high precision clock generator chip the Si5326 To change the clock frequency you can use the EMU software The clocks GO G1 and G2 can also be set to come from the config FPGA The config FPGA in turn can be set to source this clock from the FPGAs In this way FPGAs can drive the frequency onto the global clock networks This can be useful for controlled clocks and step clocks It can also be useful when a local clock for an FPGA needs to be delivered to all 6 FPGAs with zero delay G0 can be sourced from FPGA A or FPGA D The signal that the FPGA should drive when this mode is used is called CLK_TO_SPARTAN_Ap and CLK_TO_SPARTAN_Dp respectively G1 can be sources from FPGA B or FPGA E The signal
42. TRXP3_116 MGTRXN3_116 18 CLK _REFCLK SEAMA AOp 24 In 40 CLK_REFCLK_SEAMA Alp on H GTP_SEAMA TE it MGTTXPO_117 MGTTXNO_117 s GTP SEAMA pato i Jero 117 MGTRXNO_117 TI AMA Txt tt Heri H moner 417 MOTIXN Z117 a SHEA Re ES votexei_ti7 moTRercikie_ti7 HEIO MGTRXNIL1 MGTREFCLKINCI7 e E EH more 117 MGTTXN2_117 ig on E MGTRXP2_117 MOTREFCLKOP_117 80 MGTRXN2_117 MGTREFCLKDN_117 yo GTP_SEAMA Disp EH umes 17 MGTTXAN3_117 He ST SENEE ES MoTRxPS_117 MGTRANIZ117 145 CLK_REFCLK_SEAMA BOp 0 37 137 a CB VCD TEST FFITED 121 CLK_REFCLK_SEAMA Bip 113 TA 28 2a 30 Here is a schematic clipping showing the connection between the FPGA and the SEAM card The connection is electrically straight through The low speed I O is fixed at 2 5V signaling levels Three voltages are provided to the SEAM card 3 3V 12V and VCCO The VCCO supply is fixed at 2 5V however the daughter card designer should keep in mind that future Dini Boards may chose to supply a different probably lower fixed voltage here such as 1 8V DNV6F6PCIE User Manual Page 64 3 3V 2 12V 2 3 3V 1 veco 2 VCCO 2 3 3W 1 12V 2 3 3W 2 The pin out is designed for extreme high speed like you can t fathom 3 20 1 Mechanical The connector on the DNV6F6PCIE is a Samtec SEAM 20 03 5 S 08 2 A The connector that you should use on a daughter card is Samtec SEAF 20 03 5 S 08 2 A The connection scheme like all sane connection schemes is 1
43. TSM 136 01 T DV 1 8V_CP y 1 8V_CPU is 1 8V_CPU R247 py 4 7K_RS232 ON RS232 SW pion AS232 CAP_C2290 _0 1uF 10uH c2291 C2298 i O 1uF 1uF RS232_VDD RS232_VEE gt CTC2804 1 SSOPT6 SOP64P601X175 16N_REC c2304 C2299 1uF 1uF RS232 is only available to FPGAs A B and E If you need access to it from other FPGAs you will have to forward signals between FPGAs to accomplish this 3 12 GPIO ACCESS HEADER FPGA A has a few connections to a simple tenth inch header DNV6F6PCIE User Manual Page 54 This header is perfect for probing Note that on revision 01 of the circuit board it is located too close to the stiffener bar for a standard IDC cable with a key to plug into it You can either flip the cable around backward or cut the key off or use a welding torch to burn away one millimeter of aluminum O KEY GND GND GND IO Single GND O _ 10 j IO Single TENTH_INCHES HDR2x20 The signals connect straight to the FPGA I O pins Note the signals are fixed at 2 5V They are not 3 3V tolerant If you connect a 3 3V device like a hard drive then FPGA A will likely be destroyed The pin out is the same as a Ultra ATA cable The Ultra ATA cable is capable of high speed relative to a standard IDC cable This cable would be ideal to connect two boards to each other Recall how I said that connecting a hard drive will damage the FPGA This is because the DNV6F6PCIE User Manual Page 55
44. ULTn_DIMMA gt 10K_0 1 2 5V 2 37K Each SODIMM interface has an isolated regulator that allows you to independently select the voltage There is a header next to each SODIMM where you can install jumpers to affect the output voltage of this regulator To change the voltage remove all jumpers currently installed on the header and install a jumper next to the silkscreen text showing that voltage that you want Be sure to probe the DIMM_VDD test point once you have completed the change DNV6F6PCIE User Manual Page 30 REEEELLLL et wa dd 1 a gt ATT Y A je F Se o oO Se o oO a gt Ww a2 740 98 eee 501 0200 0000 REV 1 3 6 4 Daughter cards If you want to make your own custom daughter card for use in the SODIMM sockets you are encouraged to download the complete schematic and layout files for one of our existing custom modules These are available on our website with no restrictions on use The signals on the DNV6F6PCIE circuit board are routes as 50 ohm impedance Every signal connecting to the DIMM is length matched including the feedback clock Check this webpage to see existing DIMMs and to access the schematic and layout files for existing DIMMs http dinigroup com index php page DNSODM204 3 6 5 Net Length Report The length of all signals from the FPGA to the SODIMM are length and delay matched 3 7 Daughter Card Connectors The primary means of interfa
45. a 10_L8P_SRCC_24 dez 10_L8N_SRCC_24 730 10_L9P_MRCC_24 Fang IO LON MRCC_24 paz 10 L10P_MRCC_24 Agg IQ_L1ON_MRCC_24 gap 10_L11P_SRCC_24 732 IO_L11N_SRCC_24 args SECEOTMAP DS lt lt CLK_TO_SPARTAN Ap 68 10_112P_D3_24 ay 32 SELECIMAP D2 10_L12N_D2 FS2 24 537 a 10_L13P_D1_FS1_24 U31 SECECTMAP DO 10_L13N_D0_FS0_24 FAn3o 10_L14P_FCS B 24 AJ30 RS232 TX D_L14N_VREF_FOE_B_MOSI_24 Hya 10_L15P_FWE_B 24 10_Li5N_RS1_24 10_L16P_RSO_24 10_L16N_CSO_B_24 VCCO 24 10 L17P_VRN_24 VCCO_24 10 L17N_VRP_24 VCCO_24 10_L18P_24 VCCO_24 10_L18N_24 VCCO_24 10_L19P_24 VCCO_24 10_L19N_24 XC6VLX240T 550T_FF1759 mee FPGA_USER_RESETn_A The mictor can also be used to configure a daughtercard if the daughtercard has FPGAs on it Note that the mictor connector has all of the required SELECTMAP signals on it for configuration The EMU software supports configuring an FPGA using this method 3 18 USER SATA FPGA F has two SATA connectors attached to its MGTs These can be used to make a SATA interface One of the connectors can only be used when the FPGA is acting as a device One of the DNV6F6PCIE User Manual Page 60 connectors can only be used when the FPGA is acting as a controller In this way we prevent customers from emulating a raid controller There is a dedicated oscillator connected to an appropriate REFCLK input The frequency select pins of the oscillator are connected to the FPGA so that the user can select an a
46. a Socnscdedeaauiws dude sans apes aanccnvauadsapesnagcthdaygaainedndaausaunsdecenaassassnasaabedubediansuanodgaenaneen 95 6 TROUBLESHOOTING AA oo a r O a A eaa N RNET ENES 96 6 1 BOARD S DEAD rioei anaa ea oeae re EEEa Ena Aaa Ka Aaa aa A Ea asia EAA CAAO AEEA A EAN aia 96 6 2 DOES NOT RESPOND OVER PCI EXPRES Sinsin a a T aa A a 96 6 3 MY DESIGNACTS WEIRD crescita nerina ae E AA EEA ARE OEV ONETAN ia aE O a EA a aad ceed 96 6 4 IT WORKS ON ONE FPGA AND NOT OTHERS 00sseeeeeceeeeesseeeccceecueesseceeeseceusnsceccccesueusnececceessuaesseceeeeeesuensueceeeeeneaes 96 6 5 PACEMAKER STOPS WORKING 6 6 SIGNALS LOOKS CRAZY ON SCOPE ieroci eoeueoo aeia naaie aaan aa aaa ENa aTa siaaa aara EDETEN sind 96 6 7 DEM DOESNOT LOCK eiisiads decsiccvasscavasscasstted dis 96 6 8 DESIGN DOESN T RESPOND OVER NMB ooocccccccccccccnccancnanonanonononononononononononononononononononononononononononononononenenenenenenenenos 96 6 9 FPGAS WILL NOT PROGRAM iveco acia 96 6 10 DOES NOTBOO Titan dit aa 96 7 ORDERING INFORMATION sisiscccecciscccecssncccacscecsecckeacccecstecvonckseccsonscacnsasssuchsssdeccsoacusucsoccdeasbascabvcswacsscseansescsease 97 7 1 PART NUMBER Guatavaiaians OE O 7 2 HOW TO ORDER 7 3 BOARD OPTIONS 7 4 COMPATIBLE PRODUCTS 7 5 WARRANTY ccccccescceseeeseeeseseseeesecs 7 6 COMPLIANCE INFORMATION 8 INDEX A OT 101 9 GLOSSARY sencsasssesssecccescsssueesesencsascensusescvoscossdonseseucvasuausassesecusiauuoussaseseusesaseassadond enosussesestssddcvads
47. al wide An interface that has more than two endpoints An interface PCIE PCI Express RGMII This is an interface specification used for Ethernet physical interface SGMII devices RocketIO In this guide these all refer interchangeably to the 6Gbs high speed serial GTP transceivers available on Virtex 6 devices GTX MGT RS232 This could refer to one of the following DNV6F6PCIE User Manual Page 103 Serial Port The serial port on a computer The connector on the DNV6F6 that is intended to connecting to a computer s serial port SEAM These refer to three connectors attached to FPGAs A C and D These Serial Daughtercard connectors carry high speed serial signals from the Virtex 6 FPGAs SEAM refers to the name of the Samtec brand connector series that were selected for this board FGPA F that is intended for eel Ethernet A nn on e in various places These all refer interchangeably to the four SODIMM connectors attached to FPGA A C D and F These connectors are intended for memory modules to attach Source Synchronous This refers to a clocking strategy that involves introducing a controlled amount of clock skew to devices with respect to each other Precisely what I mean each time I type it varies the protocol used for the serial Flash on this board SSTL These are all signaling standards They each require certain voltage levels LVDS and termination schemes LVCMOS HCSL HSTL CML LVTTL LVDS_EXT System Sy
48. ard warp does not absorb the force of the insertion 3 3 Clock Resources The board provides clocks Clocks are one of the features that board provides There are clocks on the board You can use the clocks that are on the DNV6F6 for clocking 3 3 1 Clock pins on the FPGA The Virtex 6 has many fewer global clock GC pins that previous generations Instead there are Clock Capable CC pins that have restrictions on how they are used Only some of the global clock networks on the DNV6F6 are connected to GC pins on the FPGA The rest are connected on clock capable pins A clock capable pin might be a MRCC multiple region clock capable or SRCC single region clock capable You will have to consult a datasheet to tell the difference The use of each type of pin MRCC SRCC GC result in different effects on timing Also banks 10 18 have different timing than banks 20 38 All global clock pins on the DNV6F6 are connected to banks 20 38 It would be difficult and misleading if I tried to explain how clocks worked internally in a Virtex 6 so you will need to consult the data book We tried to connect them to make them as useful and flexible as possible 3 3 2 Global Networks The global clocks are the clocks that are provided to all 6 FPGAs with low skew between the arrival of the clock pulses at each FPGA There are 6 such networks USER_R USER_L GO Gl G2 and CLK_25 DNV6F6PCIE User Manual Page 18 SMA FPGA C
49. at D FPGA_Reference_designs common nmb DNV6F6PCIE User Manual Page 84 The main ref reference design provided here D FPGA_Reference_designs Fpga_programming_files user_fpga main_ref Correctly implements an NMB endpoint You can load these test files into one or more FPGAs and use the EMU s nmb read and nmb write functions to send data to the reference design 4 1 5 Hardware Tests To detect hardware failures the EMU program is capable of testing the board If you want to run a complete hardware test of the board select the board in emu From the Test Menu select Selected Tests This window will appear OneShot Custom Settings R FACTORY TESTS single_header_test J rocketio_Factory_test D FIELD TESTS temperature_test J clock_field_test J nmb_blockram_test J dram_test E single_intercon_test J rocketio_field_test single_intercon_fast J lvds_intercon_test nmb_spi_flash_test J TEST OPTIONS Pause On Error v Automated Mode Y Set Clocks Iv Repetitions 1 Cancel All of the check boxes are tests on the board that can be run independently The items in the Factory Tests area all require test fixture hardware to pass so they will be of limited use to users for testing the board The tests in the field tests area can all pass without special test fixtures Note that the DRAM Test requires that there is a DDR3 SODIMM any density installed in all 4 SODIMM slots on the board If they
50. ating a frequency from an FPGA and then using that new frequency across the board This is just like USER_L except there are different choices for the inputs TPB acca Clock MUXes LVDS DNI LVDS R511 sv Rasi ee CLK USER_RIGHT jes GLK USER RIGHT TP he 425V R456 2 16 R523 16 14 47K 60 CLK_USER_RIGHT_OUTCK gLKop cop 15 CIR USERCRIGATA 100R J 15 sue ae El a z TP toe 60 CLK_USER_RIGHT OUTCK cion pa a bi CLK_USER_RIGHT Ap 9 R494 7 a LVDS av nat Ho CLK USER RIGHT An 9 CONN_SMA 47K 60 CLK_USER_RIGHT_OUTEpK lt g CLK Ip a2 Fa 22 CLK_USER RIGHT Bp 44 LIGHTHORSE_SASF546 P26 X1 m R533 naz Fg e EOR RREN Bes 2 60 CLK_USER_RIGHT_OUTErK lt CLKIn a3 22 CLK_USER_RIGHT Cp 45 de 78 7 CLK USER RIGHT Cn 45 hd BUF USER RIGHT OF 22 nos X USER 3 4 45 CLK_USER_RIGHT_OUTF Xe CLK2p oe as H GLK_USER_RIGHT Dp 42 3 7 vr sv i nod 23 CUCUSER RIGHT Dn 42 To s 4 45 CLK_USER_RIGHT_OUTFIK CLK2n k vop Q5 CLK USER RIGHT Ep 47 all CLK_SMA USER VDD nas ge CHCUSER RIGHT EN 47 SEER tee 84 CLKap 20 0D 06 CLK USER RIGHT Fp 45 FPGAs CONN_SMA cme FRE CEP Td 187 CLK Se co e TIGHTHORSE SATFSG REE GIA ZSMA USER LEFT 17 Clin e Jono a7 24 SS Gl Usen MIGHT Op 68 6 KA GND nQ7 55 GLKUSER RIGHT On 68 3 4 4 3 CLK_USER_RIGHT MUX SELO lt SELO E 3 CLK USER RIGHT MUX SELI amp En Seu eee icant Ks d 2k y 10 enD voo He Fes
51. ce that some of the interconnect on the board is colored gold instead of black The yellow interconnect is only available for use if both of the two FPGAs to which it connects is a large package FPGA namely LX550T or SX475T To connect to other systems or off board I O there are three daughtercard connectors provided In the block diagram these appear as yellow rectangles unless you are colorblind then they are grey DNV6F6PCIE User Manual Page 15 The user is expected to buy a daughter card that contains the I O interface that is required or to design their own Four DDR3 sockets red rectangles are on the board to provide bulk memory for use in the FPGA You can use standard off the shelf laptop memory SODIMM or you can use one of the many memory technology DIMMs that the Dini Group provides Getting data on and off the board is accomplished through the Marvell CPU It provides USB Ethernet PCI Express interfaces It connected to the user FPGAs through the NMB interface which is fast enough to sustain a full speed x4 PCI Express connection to all FPGAs simultaneously The interface inside the FPGA and on the host PC is very simple because all of the software and hardware between has already been designed proven and optimized 3 2 Virtex 6 FPGA Virtex 6 is the most slightly better than Virtex 5 FPGA in the world You will definitely want six of them 3 2 1 Stuffing Options Each of the six main FPGA locations can be i
52. cing to the FPGA with external IO are through the 400 pin MEG Array expansion connectors There are three of these high speed high density connectors on the board DNV6F6PCIE User Manual Page 31 connected to FPGAs D E and F The FPGA connection to each of the three connectors is the same The physical layout requirements of each of the three connectors is the same FPGA FPGA FPGA F E D Virtex4 LX240T LX365T SX315T LX550T SX475T FF1759 Virtex4 LX240T LX365T SX315T Virtex6 LX240T LX365T SX315T LX550T SX475T FF1 759 LX550T SX475T FF1759 FPGA C Virtex6 LX240T LX365T SX315T LX550T SX475T FF1 759 FPGA B Vinex S LX240T LX365T SX315T LX550T SX475T FF1759 FPGA Vitex LX240T LX365T SX315T LX550T SX475T FF1759 They are located on the back side of the board in order to leave plenty of flexibility for the mechanical layout of the board s z ARMA thee te eae T N DNV6F6PCIE User Manual Page 32 3 7 1 Electrical Spec FPGA 2 2 36 38 38 38 38 192 F3 P1241 5A 12V_R LZ a FUSE_0429 9 DCDVFUSED pr a 60 DCD_CLK_DN_IN P FF CLK_DN_2 5 P 12V Al 1 me 60 DCD_CLK_DN_IN_N lt 7 CLK_DN_2 5 N lt 12V DCDSVD 42 DCD_CLK_UP_OUT_P lt 4 CLK_UP_2 5 P RSVD_PWR a 1 S B5 MA PNT re 43 3V gt 42 DCD_CLK_UP_OUT_ NX CLK_UP_2 5_N gt RSVD_PWR FUSE 0429 9 DCD3VFUSED a 5 3 3v HZ 3 3V 2 5V_
53. clock synthesizers and configure FPGAs The software that comes pre loaded on the Marvel processor is running the Linux operating system For this section it is assumed that you have a working understanding of Linux 3 9 1 RS232 The console output of Linux is directed to an RS232 port In order to connect a terminal to this port you will need to set the terminal settings to 19200 baud 8bit no parity no flow control 1 stop bit DNV6F6PCIE User Manual Page 46 aan 9 e s oe 8 Li oiga il 111334 501 0200 0000 REV 1 The Linux console is connected to a shell so you can interact with the system however the main purpose of the console is to receive kernel debugging messages so it is recommended that you instead use a telnet terminal as this shell will be much less chatty In order to interact with the boot loader or see output from the boot process you must use the RS232 console you cannot use telnet for these purposes 3 9 2 PCI Express The Marvell device natively contains a PCI Express device The PCI express pins of the Marvell a ina SS Vaso i OF DNV6F6PCIE User Manual Page 47 The device appears as three 1MB memory regions to the host machine You are expected to use the Emu software to interface with PCI Express There is no description available of the function of DNV6F6 as a PCI Express device 3 9 3 SATA The Marvell device contains natively two SATA host ports In the pre installed soft
54. computer without the power connected to the board then the board will not be accessible over PCI Express 2 1 7 Power on the board Turn on the power supply If the power supply is sitting on a desktop then the power supply will not turn on without a PSU starter device One has been provided for you The board has a self boot process that takes approximately one minute 2 1 8 Using a USB pen drive to brutally control the board The board is provided with a USB pen drive that has on it a Linux shell script If you plug the USB stick into the board then the board will automatically run the shell script The shell script on the provided pen drive will cause the FPGAs to load with the reference design bit files You can tell that the bit files are loading because after each FPGA configures a blue LED will appear on the board 2 1 9 Host Software Whether the board is connected to a computer using USB PCI Express or Ethernet the board is controlled using a program that Dini Group has provided called Emu The Emu program is provided in source and as binaries on the user support package The rest of this guide will assume you are using a Windows computer however you can also use Linux If you are using Linux the instructions may be slightly different If you are using PCI Express then you need to install a PCI Express driver This can be done in Windows using the device manager The driver files are provided in the support package D Hos
55. d some special feature then we could potentially add it For example single step clocks clocks from FPGA to FPGA 3 4 NMB Bus The NMB bus is the primary means you will use to get high quantities of data on and off the board If you want to use the provided software EMU to push data to the board over USB Ethernet and PCI Express then you are required to interface to NMB in your FPGA design 3 4 1 Protocol You are expected to know nothing about the protocol of NMB and only interface to it using the provided HDL interface wrapper in your FPGA on one end and in the EMU C code on the other end However the marketing material constantly makes reference to the inner workings of the underlying hardware and software so I feel obligated to sort of describe it a little This short section describes the implementation of the interface I recommend you skip this protocol section It is useless to know anything here DNVO6F6PCIE User Manual Page 24 FPGA E Virtex 4 LX240T LX365T SX315T LX550T SX475T FF1 759 FPGA Q Virtex 5 En Config FPGA FPGA C Virtex 6 LX240T LX365T SX315T LX550T SX475T FF1 759 Ethernet E 10 w O POTEXPRESS FPGA E Virtex6 LX240T LX365T SX315T LX550T SX475T FF1759 FPGA B Vitex LX240T LX365T SX315T LX550T SX475T FF1759 FPGA D Vintex 6 LX240T LX365T SX315T LX550T SX475T FF1759 FPGA A Vintex 6 LX240T LX365T SX315T LX550T SX475T FF1759
56. d when designing the MEG interface There should be at least one clocking method possible that will meet your needs A list of reasonable clocking methods are listed and diagramed below 3 7 10 1 Manual phase alignment You can use a PLL inside the FPGA to manually align the phase of a clock that you send from the FPGA to a MEG card 3 7 10 2 Synchronous with daughter card You may need to have a clock with edges that arrive simultaneously to the FPGA and to the MEG daughter card Each FPGA with a MEG interface has a feedback path that can be used to align a clock going to the MEG with one going to the FPGA Meg Array Connector Daughter Card ONV6F6PCIE4 Your Board Base Board Virtex 6 FPGA DC_FEEDBACK flip flop Input flip flop This allows a device on operate fully synchronously with the FPGA 3 7 10 3 Forwarding a global synchronous clock If you need a device on the MEG card to operate fully synchronously to all FPGAs on the DNV6F6 then you can use a PLL in the FPGA as shown in the diagram DNV6F6PCIE User Manual Page 40 Other Virtex 6 FPGAs Meg Array Connector Your Board DNWBFEPCIE4 Vcc Card Base Board PLL Matched Length Device Output flip flop Input flip flop This circuit will delay a copy of a global clock to the MEG card such that the phase will arrive at the MEG card at the same time that it arrives at all of the FPGAs 3 7 10 4 Source Synchronous inputs Since the signa
57. daughter cards DNVO6F6PCIE User Manual Page 44 3 7 13 1 Ensuring backward compatibility In order to build a daughter card that is compatible with all Dini Group host boards you should use the following guidelines 1 Use the standard 2 75 x 4 25 form factor 2 Use the same I O voltage for all I O pins on the daughter card 3 Supply VO voltage from the daughter card on all 6 VCCO pins 4 Do not use CC pins 5 Only use differential signaling standards for clocks that drive to the base board 6 Do not use the 5 0V power pin if one is present 7 If VREF is needed it must be driven onto all VREF pins of the entire MEG interface 3 8 FPGA CONFIGURATION 3 8 1 Select map ge i r ais Yas POS 3 9 Marvell CPU The clock networks off board I O NMB and configuration is controlled by a Marvell ARM CPU This section describes the hardware attached to the Marvell processor For information about programming the Marvell and the software running on the Marvell see the software section of the manual DNV6F6PCIE User Manual Page 45 Clock Networks Virtex 5 Config FPGA 1Gb Ethernet x1 USB 2 x3 Linux Environment SATA 2 x2 The primary purpose of the Marvell processor is to pump data from a host interface PCI Express Gigabit Ethernet SATA Flash or USB to and from the user s design in the FPGA Additionally these host interfaces can also be used to control the settings of the board s resources like
58. e screen for your intense pleasure 2 1 13 Hardware Verification Test To run the hardware test from the Test menu select selected tests OneShot Custom Settings iied d FACTORY TESTS single_header_test I rocketio_Factory_test D FIELD TESTS temperature_test JW clock_field_test Vv nmb_blockram_test JW dram_test j single_intercon_test IV rocketio_field_test IV single_intercon_Fast IV lvds_intercon_test Y nmb_spi_flash_test JW TEST OPTIONS Pause On Error v Automated Mode Y Set Clocks IV Repetitions 1 Cancel The tests that you can run now are the temperature test clock test blockram test intercon test lvds test and flash test Let s skip the DRAM test and the factory tests for now After you hit the OK button the program will ask you to locate the bit file directory This is where the test FPGA load files are stored There is a bit file directory on the provided user support package in D FPGA_Reference_designs bitfiles DNV6F6PCIE User Manual Page 13 Once the test runs the Emu window will indecisively print PASS or FAIL DNVO6F6PCIE User Manual Page 14 3 Hardware This section more than any other describes the board hardware 3 1 Overview Below is a block diagram of the board SFP E or pa SFP as E g Synchronous Clock SATA Il x Networks device o gt FPGA FPGA User selectable source and Q frequency g
59. e serial terminal to the board 2 Power on the board You should see u boot boot messages in the terminal At some point u boot should print Hit any key to stop autoboot 3 At this step press any key You will then recieve a u boot prompt like this gt gt 3 Type this u boot command DNV6F6PCIE User Manual Page 90 protect off 1 0 63 U boot will print this Un Protect Flash Sectors 0 63 in Bank 1 4 boot into linux by typing this u boot command boot 5 Once linux is done booting you will receive a command prompt like this sh 6 Type the following command mount t tmpfs tmpfs mnt ram o size 32M 7 Type the following command cd mnt ram 8 Get the update files from the dini group website Put these files on the board If you have the board connected to an internet enabled network you can use the wget command wget http dinigroup com marvellfiles ulImage If you do not have access to the internet then you will need to use some other method to transfer files to the board You can use a USB key a network mount or any other linux trick you know 9 Type this command cat ulmage gt dev partition spi This command updates the Linux kernel If this command fails the recovery procedure is still possible but is more complicated 10 Type this command reboot It is important that you use the reboot command and do not simply power cycle the board If you power cycle the board then the SPI flas
60. e telent DNV6F6PCIE User Manual Page 88 4 4 3 Running EMU in the terminal You can run EMU from the linux terminal From here you can configure FPGAs set clocks and send data to and from FPGAs The command is emu_mv Using the program is identical to using the command line version on the EMU program on the host You should connect to board by 1p address at address 127 0 0 1 If you really want you can also control other boards from this board over Ethernet 4 4 4 Compiling code on the Marvell The compiler GCC and standard C headers and libraries are installed on the board You can compile standard C and C programs that run in user space 4 4 5 Kernel Space If you want to run code on the Marvell Processor in kernel space the complete kernel code is required The kernel code is not installed on the board so compiling kernel mode code for the board cannot be done on the board For this you will need a build environment Likewise to modify the kernel itself also requires a separate build environment We can provide a VMWare virtual machine with a cross compiler installed that is capable of building the kernel and kernel modules When modifying the kernel you should maintain your code as diff files because if and when Dini Group modifies the kernel we will not provide you with a change list and you will have to re port your changes to the new kernel source Alternately you can develop the kernel changes you require and provide the c
61. ection Have a computer network In order to be able to access the board over the network the network must support DHCP Otherwise the board will fail to have a usable IP address Connect the RJ45 connector on the DNV6F6 to your network 2 1 5 Connect USB Cable This step is optional During the course of your project if you intend to control the board directly from a computer over USB then you should complete this step Connect a USB cable from the host computer to the USB type B connector on the board If the board is plugged into PCI Express the computer that connects to the board with USB does not necessarily need to be the same computer 2 1 6 Connect power cables You need a computer power supply to supply power to the DNV6F6 If the DNV6F6 is installed inside a computer in a PCI Express slot then you can use the power supply that powers the rest of the computer system Alternately the power supply can be sitting on a desktop The board requires two PCI Express Power cables to be plugged in to operate If you only use a single cable the board will fail to power up properly Most modern computer power supplies have at least two PCI Express power cables If your power supply does not you can use the provided adapter cables that plug into the hard drive power cables DNV6F6PCIE User Manual Page 9 When the board is plugged into a PCI Express slot the two PCI Express power connectors are still required If you power on the
62. elgen Taiwan E Elements Technology Co 6F 3 No 160 Sec 6 MinChuan E Rd Taipei Taiwan R O C TEL 886 2 2791 8139 FAX 886 2 2792 6942 Email sales e elements com http www e elements com DNV6F6PCIE User Manual Page 98 7 3 Board Options text 7 4 Compatible Products text 7 4 1 Dini Group Hardware 7 4 2 Third Party Hardware SFP module DIMM 7 5 Warranty 7 6 Compliance Information text 7 6 1 EFCC We are willing to obtain an FCC certification for volume production 7 6 2 CE Mark 7 6 3 Junior Miss Canada My daughter was 3rd place 2003 7 6 4 UL It might pass as a paperwieght DNV6F6PCIE User Manual Page 99 7 6 5 ROHS We can obtain a certification if necessary for volume production 7 6 6 Participation Awards I just got my 3 month chip 7 6 7 PCI SIG The board passes our internal PCI Express compliance test If you need the board added to the PCI SIG integrator s list for some reason I can t fathom This can be done 7 6 8 Export Control 7 6 9 ISO 9001 2000 DNV6F6PCIE User Manual Page 100 Index DNV6F6PCIE User Manual Page 101 9 Glossary You can expect this manual marketing materials diagrams emails and source code from Dini Group to contain a lot of shorthand and imprecise phraseology Instead of ensuring that we re consistent and precise I ve made a list of terms and words that we made up below Word that exists bit file Load file Config
63. ettings it must generate the VREF voltage and drive it back on the _V pins of the daughtercard There are no stuff capacitor locations on the host board attached to all VREF pins that can be populated with capacitors if this is required by your electrical analysis Note that installing these capacitors will negatively impact the switching speed of these signals when used as regular I O 3 7 2 2 _CC pins Any pin whose name ends in _CC is a CC pin CC pins and _MRCC pins are connected to CC pins or MRCC pins on the host board s FPGA You should see the Virtex 6 SelectIO user guide for the implications of this But in general these pins are suitable for I O clocks driven from the daughtercard to the host FPGA The CC pins are able clock I O in other FPGA banks in some cases For this capability there are requirements that the banks have certain physical relationships to each other on the silicon die of the FPGA device During the assignment of FPGA banks to the daughtercard no provisions were made to restrict the bank selection to make cross bank clocking consistent from one daughtercard header to the next It is recommended that is CC pins are required that a separate copy of the clock is driven to each FPGA bank that requires it and do not rely on multi clock regions 3 7 2 3 VRP and VRN Pins On all FPGA banks that are connected to the daughtercard VRP and VRN pins are correctly connected to allow DCI to be used with the da
64. gic 3 27 SYSTEM MONITOR Each Virtex 6 FPGA has an internal block called the system monitor The system monitor is enabled on the DNV6F6PCIE however none of the recommended power supply filtering for the A to D converter are provided so there may be unknown amounts of error caused in the A to D because of this The VP and VN analog inputs of the FPGA are connected to a small 0 1 test point You will have to connect with wires to the board in order to use them ADC s enabled but FPGAA ATT not high precision 9 0 38 FPGA_VP_A AA22 ADC IN VBAT 1 0V 2 5V R10 R947 33A FPGA VNA AB21 VP 0 VES 2 5V VBATT_O AH10 EPGA_VFS_A R80 DNI WNLO AVDD 2 5V Abe Lee FPGA_AVDD A R84 100R 12mA a R1002 oR 42 5V Recommended FSR q 1 25v AB22 FRGA VREFP_A R1001 475R ov VREFEO Anat R1010 YA _475R Aeee D o TEMPERATURE 100uA C1886 pan les C1887 C21 DXNO DIODE 1uF 1uF AVSS_0 LY2i y You can also read back the voltages on these pins the FPGA temperature and the VCCINT and VCCAUX voltages using IMACT and the JTAG chain 3 28 LED REFERENCE LIST location color meaning 37 YELLOW 1930 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS18 DS19 DS20 DS21 DS22 DS823 DS24 DS37 DS38 DS39 DS40 DS41 DS46 DS47 DS48 DS49 DS50 DS51 DS52 DS53 24 RED 1927 DS25 DS26 DS27 DS28 DS29 DS30 DS31 DS32 DS33 DS34 DS35 DS36 DS42 DS43 DS44 DS45 DS54 DS67 DS68 D
65. gram can detect the board The Windows PCI Express driver is located here Host_Software emu Drivers win32_pci You are expected to know how to install a windows driver using device manager When using PCI Express on Linux a driver is required The Linux PCI Express driver is located here Host_Software emu Drivers linux86_pci There is also provided a shell script that will load the kernel module and create suitable device nodes on the file system You must have root privileges to run this shell script In Emu from the Board menu select Board gt Select Board DNV6F6PCIE User Manual Page 83 Selection Requested 2 x Select Board A drop down menu will appear allowing you to select which board you wish to control and over which interface If you have multiple boards connected to the system you can only control one at a time using each instance of the Emu program After you have selected the board the main window will update to show a picture of the board you are using Note that it may take about a minute from the time a board is powered on until when it becomes selectable from the EMU window This is the time it takes the Marvell CPU to boot into Linux 4 1 2 Configuring FPGAs To configure and FPGA you can select the option FPGA gt ConfigureFPGA from the menu bar Or you can click on the photo of the board near one of the FPGA labels and select configure FPGA from the pop up window The program will ask for the path
66. h may not get written completely due to write buffering DNV6F6PCIE User Manual Page 91 4 4 9 2 Installing a RFS update This procedure will result in the loss of user data on the Linux file system Back up your data To check the version number of your root file system you can type this Linux command cat root image date 1 Connect the serial terminal to the board 2 Power on the board You should see u boot boot messages in the terminal At some point u boot should print Hit any key to stop autoboot 3 At this step press any key You will then receive a u boot prompt like this gt gt 3 At the prompt type this command run spi_boot_recoveryfs 5 Once Linux is done booting you will receive a command prompt like this sh 6 At the command prompt type this Linux command sh root recover sh 7 The recovery process takes about 10 minutes plus longer for the 180MB download from dinigroup com Wait patiently 8 When the recovery script is complete Type this at the shell prompt reboot 4 4 9 3 Installing a U boot update A failure during this process will cause the board to be un recoverable Please consult Dini Group before starting this process There is normally no reason for the user to use this procedure To check your current version of u boot you can check the boot messages for this line The compile date of mv _main c is May 14 2010 1 Connect the serial terminal to the board 2 Power on the board You shou
67. hange list to Dini Group and we will mainline your changes Note that you may not need to make kernel modifications at all We have provided a device located at dev mem That gives user mode programs read write access to the CPUO memory space If the only thing you need to do is access protected kernel memory we recommend you just use this method 4 4 6 Boot Sequence When the board powers on the CPU executes in place address 0xF60000 of the SPI device In this case the SPI device is an ATMEL data flash The data flash contains code that initializes DRAM and loads the last 512KB of memory from the data flash into DRAM The last 512KB of flash contains a u boot bootloader image When u boot runs it reads a set of environment variables off the flash It runs the u boot command defined by the bootemd variable That command will copy the entire contents of the data flash image from address 0x0 of the data flash to address 0x2000000 of DRAM At address 0x0 in the data flash is a compressed linux binary image u boot uncompresses the image and jumps to it U boot can pass a single string of information to the linux image called the boot arguments The value of these boot arguments can be modified using u boot environment variables DNV6F6PCIE User Manual Page 89 Linux boots setting up all the devices including NAND flash The NAND flash shows up as four MTD block devices representing four different regions in the NAND flash As the last
68. imilarly each FPGA that has a DIMM interface has a signal that is looped back from an output of the FPGA to a clock input of the FPGA The routing length of this feedback is equal to the routing length of the signals to the DIMM connector In this way it is possible to have a clock inside the FPGA that is phase aligned with the arrival of the clock at the DIMM The signal is called DIMM _FB_P N DIMM_FBpin All signals matched length FPGA gt sopimm Clock input pin Clock input pin All signals matched length MEG ARRAY DC_FBp n DNV6F6PCIE User Manual Page 23 3 3 13 From SEAM connector The SEAM daughter card provides four clock inputs delivered to the MGT GTP GTX HTX tiles of the connected FPGA This clock is intended to be used for RocketlO communication with the SEAM interface however it can be used in the FPGA for other types of logic 3 3 14 NMB The NMB interface includes one clock signal running at xxxxxx MHz This clock is free running and is not configurable It is received by each FPGA at the same frequency however the phase relationship between the arrival of the clock at each FPGA is indeterminate 3 3 15 Generating clocks from FPGAs Notice how earlier I said that some of the clock networks can be driven from FPGAs Well that means you can do all of your frequency generation in an FPGA 3 3 16 Clocking features not implemented Four of the networks can be driven from the configuration FPGA If you nee
69. in the chain So if you have only FPGA C E and F on the board then the chain will appear to only have three FPGAs on it DNV6F6PCIE User Manual Page 67 This photo gives an idea to you where the header of JTAG lies TEON 2 5V a 25V 2 5V JTAG 2 Platform g 3 Cable USB II R914 Silkscreen JTAG V6 1K R918 R932 1K 1K J21 x iks NC GND 13 To J JTAG TDI A x 13 t TE a Al JTAG_TDO F 8 rd FPGAs JTAG TDO TCK 6 mo NO 5 JTAG TDO TMS 4 TMS GND d VREF GND R923 87832 1420 1K 87332 1420 lt Goes that way 3 J To C1609 1uF FPGAs JTAG TCK A R976 33R__JTAG_TCK Ar A JTAG TCK B R97 33R__JTAG_TCK Br JTAG TCK C RIZANA 33R__JTAG_TCK Cr 1CS553 SOIC127P600 8N To FPGAs lt Goes that way JTAG TCK D R597 33R JTAG TCK Dr JTAG TCK E R599 Ap 33R JTAG TCK Er JTAG TCK F R598 33R JTAG_TCK Fr 1CS553 SOIC 127P600 8N This schematic clipping more than any other in this document shows the JTAG connector DNV6F6PCIE User Manual Page 68 3 23 MECHANICAL If you wish to build a plate of aluminum with M3 holes pre drilled to act as a base plate for the board then the diagram below will be very helpful to you 45 735 144 415 29 131 2 065 135 445 45 122 085 3948 7 5 4 8 123 735 239 665 173 265 239 665
70. itex LX240T LX365T LX240T LX365T Z LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1 759 FF1759 FF1759 Here is the connection topology shown in a diagram format Note how some of the connections are drawn in a gold color The signals that are represented in gold are only available when both FPGAs attached by them are big FPGAs that is LX550T or SX475T U0 33 ut 37 ma Trxpo_112 HABS ao E6 MGTRXN3 117 MGTTXNO_112 MGTRXP3 117 MGTRXPO_112 HANS EEN eeaeee EEH MTN 117 MGTRXNO_112 OS rx 3117 merner112 ENS HOT ABS EB MGTRXN2 117 MGTREFCLKON_117 89 gt gt 2CLK_MGT_INTERCON_B117n 23 MGTIXN 17112 MGTRXP2 117 MGTREFCLKOP 117 2 0 SSCLK MGT INTERCON_B117p 23 OAKS MGTREFCLKIP_112 MGTRXP1_112 HAMI HOEN S2 MGTIXN2 117 DAH MGTREFCLKIN 112 MGTAXN1_112 MGTTXP2_117 maTrxp2_112 Ave HOT AER G6 MGTRXN1_117 MGTREFCLKIN_117 HES MGTTXN2_112 MGTRXP1_117 MGTREFCLK1P_117 gt ALS MGT BAn2 H4 AL6 MGT_BAp2 H3 MGTTXN1_117 AKE MGTREFCLKOP_112 MGTRXP2_112 DAKZ MGTREFCLKON 112 MGTRXN2 112 MGTTXP1_117 marnes_112 HiH m H8 MGTRXNO_117 MGTTXN3_112 YA VGTRXP0 117 MGTRXP3_112 ae HOEN s2 MGTTXNO_117 MGTRXN3_112 MGTTXP0_117 ACGVEXZAOTSSOT EF 1759 XC6VLX240T 550T_FF1759 This is a schematic clipping making this section of the manual look much more complete 3 14 1 REFCLK Clocking There is a single c
71. ld see u boot boot messages in the terminal At some point u boot should print Hit any key to stop autoboot 3 DNV6F6PCIE User Manual Page 92 At this step press any key You will then receive a u boot prompt like this gt gt 3 Type this u boot command protect off 1 0 63 U boot will print this Un Protect Flash Sectors 0 63 in Bank 1 4 boot into Linux by typing this u boot command boot 5 Once Linux is done booting you will receive a command prompt like this sh 6 Type the following command mount t tmpfs tmpfs mnt ram o size 32M 7 Type the following command cd mnt ram 8 Get the update files from the Dini group website Put these files on the board If you have the board connected to an internet enabled network you can use the wget command wget http dinigroup com marvellfiles u boot db78200 MP bin 7 6 iles update_uboot a es iles ulmage wget http dinigroup com marvel wget http dinigroup com marvel If you do not have access to the internet then you will need to use some other method to transfer files to the board You can use a USB key a network mount or any other Linux trick you know 9 Type this command chmod 500 update uboot 10 Type this command update_uboot DNV6F6PCIE User Manual Page 93 11 Type this command diff new contents bin u boot db78200 MP bin The file new_contents bin contains the current contents of the SPI flash This co
72. lock network on the board CLK_MGT that can be used with the FPGA to FPGA interconnect This is the only clock network that can be used You might be able to use a REFCLK that is sourced from the FPGA internally GREFCLK however you may not be able to achieve excessively high data rates using this method In order to instantiate the MGT tile in your HDL you must connect a REFCLK signal to the MGT tile Only certain REFCLK inputs can be used with certain MGT inputs and outputs DNV6F6PCIE User Manual Page 57 REFCLK 125 250 312MHZ XXX EA 117 116 115 114 113 112 ERE 110 pan E Mia F A EA pan 117 116 115 114 113 112 ERE 1o Mia 117 116 115 114 113 112 ERE 1o 110 111 112 113 114 115 116 117 118 110 111 112 113 114 115 116 117 118 110 111 112 113 114 115 116 117 118 FPGA A AS C FPGA B REFCLK 125 250 312MHZ Therefore the CLK_MGT network connects to multiple clock inputs on each FPGA The above diagram shows how each REFCLK input on each FPGA is connected For example on FPGA E if you want to use MGT tile number 114 you have to use the REFCLK input on tile 115 Tile 118 117 and 116 all share the single REFCLK input that is on tile 117 Does that make sense Whatever 3 15 SPI FLASH Three of the user FPGAs namely FPGA A B E and F have a serial flash device attached to them for the storage of warez 2 5V 2 5V o 0 so SPI Flash for spPisSerial
73. lowing are methods that don t work 3 7 11 1 Hold time violation The following diagram shows a method that potentially violates hold time on the device on the MEG card DNV6F6PCIE User Manual Page 43 Meg Array Connector 3 7 11 2 PLL cascade When using PLLs in the FPGA make sure that there is not another PLL anywhere in the feedback loop of the PLL or it will result in an unreliable phase output 3 7 12 Compatibility with older Dini Boards The MEG interface has been included on Dini Group board since 2005 with the Virtex 4 series of boards however the features provided by the interface have changed since then Any daughter card that meets the following criteria will be compatible with the DNV6F6PCIE Designed for use with a Dini Group Xilinx FPGA board not Altera Uses only a single voltage for the whole daughter card Does not use I O signal levels above 2 5V Uses the reset signals as an input only Does not require the use of the 5 0V power pin Uses no differential signals All Virtex 6 boards provide the same features on all MEG interfaces so any daughtercard designed for use on a Virtex 6 board will work on any MEG connector on any Virtex 6 board that Dini Group sells 3 7 13 How to make a daughter card It is recommended that you start with one of the Dini Group daughter cards as a design template The ORCAD schematic and layout files are all provided on the Dini Group website for several
74. ls to the daughter card are length matched you can rely on a tight timing relationship between the clock and data that you send from the daughtercard to the FPGA Since the FPGA has a zero hold time input sending a clock from the MEG card whose rising edges are aligned with the data transitions on your data lines will result in reliable communication with the FPGA DNV6F6PCIE User Manual Page 41 Meg Array Connector Virtex 6 Daughter Card FPGA Your Board y DNV6FEPCIE4 Base Board BUFR Optional Matched Length GC Pin or BUFIO Optional CC pin Input Internal flip flop flip flop Q D 3 7 10 5 Source synchronous outputs You can repeat this setup in the opposite direction as long as the hold time on the device on the CLK_OUT DATA_OUT MEG card is zero or negative Meg Array Connector Daughter Card ONV6FEPCIE4 Your Board Base Board gt Virtex 6 Zero hold time Device 3 7 10 6 Skewed Clocks The I O on the FPGA can be used on either rising or falling edges of a clock so it is easy to invert the clock on the FPGA device so that it operates 180 degrees out of phase with the daughter card Of you can invert the clock as you output it to the daughter card The maximum frequency of the interface when using this method is effectively reduced by half DNV6F6PCIE User Manual Page 42 Daughter Card Meg Array Connector 3 7 11 Incorrect Clocking Methods The fol
75. mmand is to make sure that the update was written successfully to the SPI flash If this diff fails shows the files are different then something went wrong with the update and you should not turn off you board If you turn off the board at this time the board will never boot again and you will have to send it back to the factory for re programming 12 Was the diff clean If not then stop here 13 Type this command cat ulmage gt dev partition spi This command updates the Linux kernel If this command fails the recovery procedure is still possible but is more complicated 12 Type this command reboot It is important that you use the reboot command and do not simply power cycle the board If you power cycle the board then the SPI flash may not get written completely due to write buffering DNV6F6PCIE User Manual Page 94 3 REFERENCE DESIGN text what is the reference design why does it exist text 5 1 Diagram 5 2 NMB Space Map text 5 3 Things Tested 5 4 Compiling this is text DNV6F6PCIE User Manual Page 95 6 TROUBLESHOOTING Text 6 1 text 6 2 test 6 3 6 4 6 5 6 6 6 7 text 6 8 text 6 9 text board is dead does not respond over PCI Express My design acts weird It works on one FPGA and not others Pacemaker stops working Signals looks crazy on scope DCM does not lock design doesn t respond over NMB fpgas will not program 6 10 does not boot text D
76. nchronous A clocking strategy where each device receives a low skew clock In this guide I often use this word as shorthand for using one of the provided global clock networks I used this as shorthand for the set of place and route constraints that you input into ISE These are all special purpose I O pins on the Virtex 6 FPGA For each section that mentions one of these pins you are expected to know the purpose and usage of each XAPP These refer to reference documents produced by Xilinx UG DNV6F6PCIE User Manual Page 104 1OREVISION HISTORY RCS file Ivarlib cvs dncvs Boards DN0200 DNV6F6PCIE Documents Manual DNV6F6PCII nual_rev01 docx v Working file DNVOFOPCIE manual rev01 docx head 1 2 branch locks strict access list symbolic names keyword substitution bx total revisions 2 selected revisions 2 description E ma revision 1 2 date 2010 05 28 23 44 59 author dpalmer state Exp lines 100916 18154 kopt bx commitid ab84c0055796eb8 filename DNVOF6PCIE manual rev01 docx took out the most offensive jokes like the race jokes I m about half way through the hardware section revision 1 1 date 2010 02 19 03 20 26 author dpalmer state Exp kopt bx commitid 5Sab44b7e0379ab40 filename DNV6F6PCIE manual rev01 docx empty log message DNV6F6PCIE User Manual Page 105
77. nstalled with any compatible density of FPGA or not installed at all in any combination In this way you only will have to pay the significant FPGA cost for the FPGAs that you will actually use Below there is a table that describes the major differences between the available FPGAs Only FPGAs that Xilinx sells in the FF1159 package are compatible with this board FPGA Speed Flip flops Equivalent All Board 25x18 Memory Grades ASIC Gates Features multipliers bits LX240T 1L 1 2 3 301 440 1 7M N 768 15 0M SX475T 1L 11 2 595 200 3 4M Y 2016 38 3M SX315T IL 1 2 3 394 000 2 3M N 1344 25 3M Each LX550T FPGA can emulate approximately 4 million ASIC gates reasonably however I just made this number up It is strongly recommended that you synthesize your actual ASIC design mapping to FPGA technology to get an accurate FPGA utilization estimate 3 2 2 Speed Grades Xilinx FPGAs usually come in three speed grades There is no rule of thumb to estimate which speed grade you will need to run your design at your target frequency You will only know this once you have run a synthesis with FPGA place and route targeting the actual FPGA device skew that you will be using DNV6F6PCIE User Manual Page 16 3 2 3 Upgrades If you would like to install only some FPGAs when you order the board and later add FPGAs or upgrade FPGAs to larger parts this is possible however you should request this before ordering the board 3 2 4 Small FPG
78. over ethernet DNVO6F6PCIE User Manual Page 50 3 9 12 Multi CPU The Marvell Processor has two CPUs The first CPUO is used by the Linux operating system Since Linux does not support symmetric multi processing the second CPU CPU1 must be operated in un hosted mode in its own area of DRAM without accessing devices I O must be accomplished through CPUO under Linux The use of PCI Express and the DMA engine in the configuration FPGA is possible Interrupts may also be used by CPU1 3 10 Config FPGA The seventh FPGA on the board the config FPGA FPGA Q is not really intended for the user It is a cleanup FPGA that controls all the clock circuits on the board configures the other FPGAs and multiplexed the NMB bus from the Marvell CPU to the user FPGAs You don t need to know anything about it or how it works You are encouraged to skip this section 3 10 1 PCI Express The config FPGA is connected to the Marvell processor through a PCI Express interface The config FPGA is a PCI Express endpoint and the Marvell acts as a root port 3 10 2 Configuring the Config FPGA The configuration signals of the config FPGA are connected to the Marvell CPU The Marvell CPU gets the bit file for configuring the config FPGA off of the NAND flash The config FPGA also DNV6F6PCIE User Manual Page 51 has a SPI flash attached to the configuration signals that can be used to store configuration data however it is unused 3 10 3 RS2
79. p of banks allows the use of some of the high speed features of the Virtex 6 such as BUFR clocking and ISERDES and OSERDES Every bank of interconnect contains at least one LVDS pair in each direction that goes to a clock capable pin on the FPGA This pair can be used as a clock to input all of the bits on that bank The net name of this pair ends in _CC in the schematic DNVO6F6PCIE User Manual Page 27 To achieve the highest switching rates on the interconnect banks you must use the LVDS IOSTANARD 3 5 3 Signal net length report The shortest FPGA to FPGA interconnect signals is 40mm long The longest is 290mm long This corresponds to a skew of about 2ns Within any single bus the greatest skew is 75mm This corresponds to 0 5 ns of skew 3 6 SODIMM DDR3 Connectors For memory expansion the DNV6F6PCle has four socket connectors connected to four of the user FPGAs The sockets accept standard off the shelf DDR3 laptop memory The interface and reference design is compatible with any density or organization of memory These sockets can also be used for types of memory other than DDR3 DRAM Dini Group has a variety of modules that are compatible with the DNV6F6PCle including synchronous SRAM and others FPGA F Virtex 6 LX240T LX365T SX315T LX550T SX475T FF1 759 FPGA D Virtex4 LX240T LX365T SX315T LX550T SX475T F 4GB Max xen gor WAWIdOS gyda A O a fe a a F1759 FPGA C Virtex 6
80. pose TP85 SATA_USB_TP Unknown purpose TP86 CPU_PEX_TP Unknown purpose U TP55 TP67 TP7 GND Jsed for physically securing SODIMM modules TP28 TP32 TP33 TP35 GND sed for physically securing the board TP64 TP72 TP73 TP82 3 30 Connector Reference List The following is a list of the connectors on the board It will allow you to find the datl got bored GOMPF_9456 0285LC 2767 BRAKI MOUNTING_HOLES REMOVE_FROM_BOM M1 M2 M3 STIFFENER_DN200_NORTH 2766 MP1 STIFFENER_DN200_SOUTH 2712 MP2 1 3 1 1 12 TST PNT DNI TP3 TP7 TP28 TP32 TP33 TP35 TP55 TP64 TP67 TP72 TP73 TP82 20 TESTPOINT 892 TP6 TP8 TP9 TP11 TP13 TP14 TP16 TP17 TP51 TP56 TP58 TP59 TP60 TP61 TP62 TP75 TP77 TP79 TP80 TP83 25 FBAO3HA450AB 00 2720 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP29 TP30 TP34 TP37 TP38 TP39 TP40 TP43 TP45 TP46 TP47 TP48 TP49 TP50 TP52 1 SHUNT_JUMPER 2056 TP78 5 TP_THOS DNI TP81 TP84 TP85 TP86 TP87 3 ACM2012 2602 T1 T2 T3 DNVO6F6PCIE User Manual Page 79 1 3001 1398 BT 1 PCI_EXPRESS X 4 P4 3 MEG_400_Plug_Stratix3_30 1157 P10 P11 P12 1 Header_1x2 84 JP1 1 1367073 579 J1 5 CONN_SMA 1377 J2 J5 J6 J20 J36 6 TSM 136 01 T DV 83 J3 J4 J16 J31 J32 J37 2 45558 0002 1827 J8 J7 6 22 27 2031 431 J9 J10 J11 J17 J18 J19 4 CONN_DDR3_SODIMM204 2516 J12 J13 J22 J24 4 67800 5005 2589 J14 J15 J30 J35 2 87832 1420 511 J38 J21 2 USB Type B 2628 J25 J23 2 53047 0310 3
81. ppropriate REFCLK frequency for SATA I or SATA IL FPGA F 25y_QuIEr usas warms 116 METRES sa ASAT RSE Rsa ae Sam S ATK ae mermas z 4 clk SEP SOURCEO Colo O1UECK SFP SOURCED M7 0 OSC SFP ESO y VAN TA e MOTREFOLON 116 oso seroe el no oso SF No 28y our 3 ano von j D og SEISTE cias Cue FBI MASE OLIN 118 du Le a NGTREFGLKIP is Faros Ohm 1 Mu 14 ohm DC u m ACEVIEAOTISOT FF1750 E gt FEMH 1608HM102 T SATA A Tere 289 pp QUE SATA A TeP1 z 3 1 7 a big E oe 9 CAPCTODN ca SATA A RxN1 c C1025 j _0 1uF SATA A AxN1 7a E TAA RPTE C103 I CARE TOBAT A TAFT 3 8X y CAPE TOON Bie 5 GND A Hum MH G a mo 0 7 MOLEX 67800 005 7_ UPDATE us SATA A meo e C1222 1 oe SATA A Tupo Hoo B TEATRE aan CARE IEA H 5 CAPE TOON i 5 SATA_A RENO c C1254 11 O tuF SATA A RENO qn TAA REPTE tees ARETORA A EPT rapes t CAPE TOON 718 m Elo 2 mu m n f 4 MOLEX 67800 005 7_UPDATE The below photo shows the location of the SATA connectors 3 19 SFP AND ETHERNET FPGA F is also attached to an SFP connector SFP connectors are useful for Fibrechannel or Ethernet Since the FPGA is only capable of serial speeds up to 6Gbs SFP modules probably can t be used DNV6F6PCIE User Manual Page 61 SFP connector one Channel
82. r Manual Page 102 U0 Spartan V5 GND This refers to both a net on the DNV6F6 and to the absolute potential of Ground that net at any given time When an absolute voltage is given in this manual it should be interpreted as a voltage relative to this net IOSTANDARD attribute This is an attribute of the I O buffer primitive These are each software programs provided by Xilinx LOC constraint This is a constraint type that controls which physical pin on the FPGA device an I O will be mapped to Megabyte Usually 1 000 000 bytes but sometimes 1 048 576 bytes Kilobyte Usually 1 000 bytes but sometimes 1 024 bytes Mega b its divided by seconds Mega T ransfers per second These are used interchangeably with MHz to avoid any possible confusion when dealing with DDR interfaces MEG Array There are several types of user available connectors on this board Usually Daughtercard Connector the daughtercard connector refers to one of the three Meg Array connectors attached to FPGA D E and F MV78200 The on board processor manufactured by Marvell CPU MCU Processor uP These interchangeably refer to a physical wire on the printed circuit board A net on the circuit board is all points that are electrically shorted together NMB These interchangeably refer to the 40 signal bus between each FPGA and Main Bus the configuration FPGA This word can mean any one of the following An interface that is more than one sign
83. rs can supply up to 1A of current If you build a daughter card that drives current back to the host board it must be able to supply the current not only for the daughter card I O but also for the I O current requirements of the host board DNV6F6PCIE User Manual Page 35 If you forget to include voltage regulators for VCCO on the daughtercard you can rework the DNV6F6 bias regulators to output your required voltage so only as the combined current requirements of the FPGA banks and the daughtercard do not exceed 1A per bank Note that the 5 voltage regulators on the host board are not set up to evenly share current loads and that each must be individually load limited to 1A P3 There is a row of test points next to each daughtercard header allowing the easy probing of the 5 voltage rails on the daughtercard interface gt gt DCD_B0_VCCO 31 Arrogantly assumes more pe Capacitance is on bank LT1963AES8 SO8 SOIC 127P600X175 8N 36 39 DAUGHTERCARD_RESETn lt lt This is the bias regulator There is one for each of the 5 banks on each daughtercard interface 3 7 6 Clock Pins The clock pins El F1 E3 F3 are always connected to 2 5V I O on the FPGA They are connected to clock input pins near the center of the FPGA making them suitable for sending a clock from the daughter card to the host FPGA They are not externally terminated on the board but you can use DIFF_TERM in the FPGA if you are using differen
84. s power connector This connector has 6 pins and is increasingly common on power supplies There are also some 8 pin version of PCI Express graphic power connectors on some power supplies These can be plugged into the DNV6F6PCIE as well with the extra two pins dangling uselessly off to the side Both power connectors must be installed on the board for it to operate properly The current pulled from each connector can exceed 15A at 12V which is already more than the connector is designed to supply There are three jumper points on the board that can connect the two 12V halves of the board together in case you really really want to run the board with one cable There is also a jumper point that allows you to connect the 12V of the DNV6F6PCIE to the PCI Express edge connector 12V if you want to power the board without any cables at all This is not recommended because if you draw more than say 40W of power off the finger connector it could burn the valuable gold plating off the connector DNV6F6PCIE User Manual Page 70 7 5 4 8 From 300W PCI Express es Specification R352 1 2mA AA 124 WARN_R PCIe Power Cable 4A pin 10K_0 1 RED accepts 6 pin or 8 pin 1ED_0608 connector Dsas R351 rrd 1 2mA 12V WARN L 4 place LED near PCI place LED near PCI UA Express power Express power TED 0500 connector connector a7 Pi a E 8A
85. scssccctceascectacsaccaeceascectacsnccatedacaccvacesccawencabacancaueavauveatacauevavecavavanadaveaeeavauveata cavevevasaueaans ca 77 3 27 LED REFERENCE LS a dias 77 3 28 TEST POINT REFERENCE LIS Tics cescessdssicesecdencestasance sevececetarechechavexaconds ecacchavececsharecacchavecacends echcchavechconanectectevedia 78 3 29 CONNECTOR REFERENCE UIST ccoo id e ce 79 3 30 CHARACTARIZATION REPORTS lt ccoocoi noionocicocivononsancnioronoci solados donaron aladdin AAEREN a KARNEKA ANSA KUIEREN RENA KEk 80 3 31 UNUSABLE PINS wesescessesoczcevetsccceeesacccedens tananana aan taraa AAA AAE ia AAA AAA AAE a VAa AAAA AE AR AA Aa AE a AR AANA aaa 81 4 SOFTWARE vevcsscesccnsscoscsssccncnsescsesecdsccnsedoncsvssdsentescdenecesensssincnussesesnsvsssnsestsensseizconssdesndvsetndesesensssdasendsssesnsesssases 82 DNV6F6PCIE User Manual Page 3 4 1 EMU HOST SOFTWARE iecssssccnsdateasusdsssciecdasncsedbassacnadsaandasswantsnsdasiessuaue ide sGlvaayssaueisastauaseassaueiaes ao aeaa aa 4 2 WRITING YOUR OWN SOFTWARE 4 3 HOW EMULIB WORKS sis c is cc ccctosadsacecccccestuesaadstacad devia otaa banaue dead ei ceba 4 4 MARVEL ENVIRONMENT siss2scccudainesscsasacdacdasaqsadsasaccanda in cai cid 5 REFERENCE DESIGN iisssssesciscecccccisscocscessecctcnsacactsactouctcacnusctsasuecssashes A ae a a dens senucsbensceenssanteavsasuesasanens 95 5 1 DIAGRAM iaa AE E AE di ici 95 5 2 NMB SPACE MAP siii acu catala 95 5 3 A ooo O 95 5 4 COMPILING 32s sscstsdiceions ans
86. skew of 180ps in addition to the skew caused by the FPGA device 3 7 8 Physical Spec Daughter cards are mounted on the back or solder side of the PCB opposite the FPGAs This allows for maximum vertical mechanical flexibility The vertical clearance of components on the reverse side of the DNV6F6 is 3mm The board to board clearance between the daughtercard and the host board is 14mm Therefore the daughtercard may have 10mm components on its side facing the base board leaving 1mm of clearance The front or component side of the daughtercard is the face that points away from the host board Therefore the back or solder sides of the host and daughter cards face toward each other The position and size of four mounting holes through the DNV6F6 PCB with respect to each daughtercard interface is fixed Every Dini Group product with 400 pin MEG interfaces has at least four mounting holes with this offset DNVO6F6PCIE User Manual Page 37 View Top Side 400 Pin Receptacle on Back P N 74390 101 5 000 TIT gt it In the above diagram a daughtercard is designed that has holes matching the position of the holes on the base board so that a 14mm M3 size standoff can be used to stabilize it onto the base board The dimensions of the daughtercard above are guaranteed to physically fit onto any Dini Group host board while that board is installed inside a PC case Boards larger than the above given dimensions may
87. ssary board features to make SSTL work properly are provided DNV6F6PCIE User Manual Page 29 The EVENTn pin is also voltage selectable It will be the same voltage as the rest of the DIMM There are some LED signals on the FPGA that are connected to the DIMM bank The IOSTANDARD attribute of these signals must be changes to match the voltage of the DIMM The IIC signals SDA and SCL are fixed at 2 5V and should use a 2 5V standard 3 6 3 Voltage Selection Off the shelf DDR3 DRAM always uses 1 5V core power and IO signaling levels If you are using DRAM then you would never need to change the voltage output of the DRAM interfaces However when using alternate memory modules from Dini Group or when designing your own daughter cards you may need to supply a different voltage to the SODIMM and to the attached pins of the FPGA 5 0V G Silkscreen F R1192 1K T opty This 1 35 nd inet all for 2 5V duplicated R1193 R1180 1K DNI u91 1 J32 on other VA REG DIMMA TRACK Et rack Fg 62 REG_DIMMA FB REG_DIMMA_FB135 R1371__ 30K pages 2 4 FBT5_R1370 VV13 7K REG DIMMA RUN D1 6 REG DIMMA FB18 R1369 6 8K R1191 oR RUN SS 8 REG_DIMMA_FB25_R1368 19 1K R1146 REG_DIMMA_COMP Gi l A l DN COMP B3_ REG _DIMMA_SWO R1171 F1 W B4 i E TSM 136 01 T DV s BNI paddb sw PLATEA 5 6 7 59 SEQ_DISABLE_VCCO X ESATO ee DNI 12V 10K 1 35V 7 25K 2TV 21K 15V 5 76K nal 1 8V 4 02K 59 PWR_FA
88. st Help Auto Update J Board Interface _ Refresh DNO200_DNV6F6PCIE 1003019 Ethernet pi CLOCKS co 100 008 Synthesizer Gl 100 002 Synthesizer GZ 200 010 Synthesizer USER_L 0 000 FPGA A SRC USER_R 252 363 FPGA C SRC MGT 312 500 312 MHZ Ry Clear Save Text Full Screen Auto Scroll V Welcome to Emut Emu Is Ready A 2 1 11 Configure an FPGA You can configure and FPGA by clicking on the image of it in EMU and selecting configure from the pop up window There are some example bit files that you can use in the support package located at D FPGA_reference_designs bitfiles Be sure to choose bit files that are compiled for the correct type of FPGA that you have installed on the board to avoid humiliation and ridicule After the FPGA successfully configures a blue dot will appear next to any configured FPGA DNVO6F6PCIE User Manual Page 12 2 1 12 Setting board controls and options The primary board settings that you will need to modify are the clock settings There are six clocks on the board that have modifiable options Let s change the clock frequency of GO for kicks In the EMU window click on the right side where the says CLOCKS GO A pop up menu will allow you to change the frequency of clock GO You can also change the frequency using the Clocks Temps menu in the menu bar The clock frequency of the six main clocks is constantly measured and displayed on th
89. step of booting it mounts a JFFS2 file system from one device specified in the boot arguments Before starting a shell for the user linux will run a shell script on the filesystem called startup sh This script loads the software that Dini Group wrote that controls the FPGAs and other function of the board This program is called DiniCmos and runs in the background You don t need to worry about it 4 4 7 Compiling U boot Like the kernel compiling u boot requires the virtual machine It is not recommended that you do this Instead submit your change request to Dini Group so that we can mainline your changes 4 4 8 Creating the Root File system There is no root file system build process Instead we maintain a golden image in the form of a tar file containing the contents of the root file system on the Marvell Changes have to be made to the tar file manually Updating utilities are done manually 4 4 9 Update the software Updating the software on the Marvell board takes a long time 4 4 9 1 Installing a kernel update To get the your current version of the Linux kernel you can check the boot messages for this line Booting image at 02000000 Image Name Linux 2 6 22 18 Created 2010 04 02 1 27 51 ULC Image Type ARM Linux Kernel Image uncompressed Data Size 2840632 Bytes 2 7 MB Load Address 00008000 Entry Point 00008000 Verifying Checksum OK Check the Created date 1 Connect th
90. t host Ez F D del os Virtex6 Virtex 6 Virtex 6 53 gt on LX240T LX365T LX240T LX365T LX240T LX365T Du on SX315T SX315T SX315T zo fs LX550T SX475T LX550T SX475T LX550T SX475T EJE E FF1759 FF1759 Fl 3 FPGA Q TEE Virtex 5 Config FPGA 26 26 73 73 FPGA xen gor WINIGOS syaa PCI Express r A oz Virtex 6 Virtex 6 Virtex 6 1Gb a LX240T LX365T LX240T LX365T LX240T LX365T Ethernet y Marvell go SX315T SX315T SX315T i mv70200 Mi da ca y 128M x 64 USB 2 PERS x3 d Linux 128Mb 2 Environment ae ee A DMA 4x Em GTX Expansion demo GTX Expansion SATA 2 Header Header x2 Boot 4 lanes PCIEXPRESS Above is a block diagram of the board The board contains six Xilinx Virtex 6 FPGAs in the FF1759 package There are 5 different Xilinx part numbers that come in this package All 5 of these are compatible with this board The board can come with any number from 1 to 6 of FPGAs installed leaving the unused chip positions vacant The Virtex 5 Config FPGA is not intended for your use so you should think of it as more of a NMB master controller bus switch Interconnect between the FPGAs is fixed and routed in a point to point fashion The interconnect is represented in the block diagram as arrows between the FPGAs All of the interconnect is user defined Noti
91. t CLK_USER_LEFT_Cp 45 14 i BUF USER LEFT OE 22 nas Fe gt CLK USER_LEFT Cn 45 To 44 CLK_USER_LEFT_OUTBp lt lt 13 CLK2p OE Qs ts gt gt CLK_USER_LEFT Dp 42 all 2 V2 42 5V 17 nQs gt CLK_USER_LEFT_Dn 42 44 CLK_USER_LEFT_OUTBn lt lt CLK2n fo 19 VDD 05 5 gt gt CLK_USER_LEFT Ep 47 FPGAs 19 zg VDD nQs 5 gt CLK_USER_LEFT En 47 3 CLK_USER_LEFT_SPARTANp lt lt 18 CLK3p VDD f gt gt CLK_USER_LEFT Fp 45 477 VT3 18 nQ6 haz 22 CLK_USER_LEFT Fn 45 3 CLK_USER_LEFT SPARTANn lt lt CLK3n A A a 21 GND Q7 Foz 22 CLK_USER_LEFT_Qp 68 6 GND nQ7 gt CLK_USER_LEFT_On 68 3 CLK USER LEFT MUX SELO lt lt 5 SELO C127 C139 C128 SS 3 CLK_USER_LEFT MUX SELI lt lt SEL1 O4uF 0 1uF 0 1uF 1CS85408 i che wo E L SOP65P640X120 24N GND VDD T cs 1C5854057 T550P20 0 1uF DNV6F6PCIE User Manual Page 20 The following list are the available sources for the clock USER_L FPGA A SRC The FPGA A should drive the signal CLK_USER_LEFT_OUTAp n differentially FPGA B SRC The FPGA B should drive the signal CLK_USER_LEFT_OUTBp n differentially FPGA D SRC The FPGA D should drive the signal CLK_USER_LEFT_OUTDp n differentially SMA The user should supply a clock single ended into the SMA P36 located on the bottom right of the board Voltages up to 2 5V are acceptable MGT The clock will be the same frequency as the MGT clock This has a dubious and unknown use 3 3 6 USER_R These come from a USER FPGA They are used for gener
92. t_controller_software emu drivers pci_win32 Search the internet if you are unsure how to install a driver from device manager If you are using USB then you will need to install a USB driver This can be done in Windows using the device manager The driver files are provided in the support package D Host_controller_software emu drivers usb_win32 Search the internet if you are unsure how to install a driver from the device manager Ethernet does not require a driver 2 1 10 Selecting a board Run the provided emu program located in the user support package here D Host_software_applications Emu App Bin Emu_gui_win32 exe This window will appear DNV6F6PCIE User Manual Page 10 A alaLx File Board FPGA Clocks Temps Data Test Help Auto Update J Board Interface Refresh No board selected No interface selected No Board SeLected Welcome to Emu DISCONNECTED From the Board menu chose select board If you are connected to the board over PCI Express USB and Ethernet simultaneously then there will be three options in the pull down menu Each interface is treated like a separate board From the pull down menu you can see the serial number of each board The serial number in this menu should match the serial number located on a sticker near DIMM D of your board Once you have selected a board your window should look like this DNV6F6PCIE User Manual Page 11 lol File Board FPGA Clocks Temps Data Te
93. that the FPGA should drive when this mode is used is called CLK_TO_SPARTAN_Bp and CLK_TO_SPARTAN_Ep respectively G2 can be sourced from FPGA C or FPGA F The signal that the FPGA should drive when this mode is used is called CLK_TO_SPARTAN_Cp and CLK_TO_SPARTAN_Fp respectively 3 34 CLK_25 This clock network is fixed at 25Mhz You cannot change it try as you might Fixed Frequency TP57 DNI i 68 CLK_25 SOURCEp lt lt 68 CLK_25 SOURCEn lt lt gt CLK_25 Ap gt gt CLK_25_An 60 gt gt CLK_25 Bp 60 From Spartan gt gt CLK_25 Cn 60 LVDS SS CLK_25_Dn 60 To S gt CLK_25 Ep 60 all S gt CLK_25 Fp 60 FPG gt gt CLK_25 Fn 60 gt gt CLK_25 CONFIGp 68 gt gt CLK_25_CONFIGn 68 C394 C386 C385 0 tuF 0 tuF 0 tuF gt 1CS85408 SOP65P640X120 24N 3 3 5 USER_L This clock has no frequency synthesizer but can come from a variety of sources TP15 DNI R570 LVDS U26 eb U25 LVDS 100R 2 16 CLK_USER_LEFTp R564 16 14 CLK USER_LEFT_TPp 42 CLK_USER_LEFT_OUTAp lt lt 3 rad eee 15 CLK_USER_LEFINn 100R J 15 oe E 3 CLK USER LEFT IPn 1 42 CLK_USER_LEFT_OUTAn lt lt CLKOn ase Qi hy 2 CLK_USER_LEFT_Ap 9 nQi CLK_USER_LEFT_An 9 60 CLK_USER_LEFT_OUTDp lt lt t CLKtp LVDS ae Q2 2 SS CLK USER_LEFT Bp 44 S R548 na2 Fg SS CLK_USER_LEFT Bn 44 60 CLK_USER_LEFT_OUTDn lt lt CLKin ATK Qs gt g
94. the DNV6F6PCIE attached to FPGAs A C and D Header GTX Expansion FPGA FPGA FPGA F E D Virtex 6 Vitex Virtex 6 LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1 759 FF1759 FF1759 FPGA FPGA FPGA C B Virtex 6 Virtex 6 Vitex LX240T LX365T LX240T LX365T LX240T LX365T SX315T SX315T SX315T LX550T SX475T LX550T SX475T LX550T SX475T FF1 759 FF1759 FF1759 GTX Expansion Header GTX Expansion Header We don t have any off the shelf SEAM daughter cards yet so you are expected to design your own Send a request to sales Odinigroup com to see what we are willing to do for you Each SEAM provides 8 channels of high speed serial data to the FPGA There are four REFCLK signals from the SEAM connector to the FPGA making four independent interfaces on one SEAM connection feasible Additionally for the purpose of control there are 16 low speed I O that go to the FPGA regular I O pins DNV6F6PCIE User Manual Page 63 AN Here is a photo of the SEAM connector on the SEARAY Connector back side of the board 60 SEAMA 10_DOp_CC 42 SEAMAIO_DIn CC a 80 SEAMA10_0 7 60 SEAMAIO_D2n fr 80 SEAMAIO_D3p oH 60 SEAMAIO_D3n 2 1 60 SEAMAIO_Ddp wo 60 SEAMACIO D n 81 42 SEAMA IO_DBp 9 4 PFA 42 SEAMAIO_D n gt l 42 SEAMAIO_D7p gt Sy 42 SEAMAIO_D7n C Reg 1K SEAMA RESERVEDO 73 RID 1K 84 Rot 1
95. tial signaling In addition to these two clocks there is a variable voltage clock input to the host FPGA This signal BO_P1 _GCC_TERM is located on bank 0 The input levels will be determined by the bank 0 voltage and the IOSTANDARD settings of the I O in the FPGA There exists external end termination resistors on the host board terminating to a voltage of VCCO 2 This termination scheme will result in a high current on the signal DNV6F6PCIE User Manual Page 36 FPGA D Ra Meg Array Connector K33 DCD B0 P17 IOL LOP 25 DCD BO N17 P12 2 1O_LON_25 LZ PLUG 9 01 N2 pop Bo Fo eee PNAS Bo Po GCC_DN 10_L2P_25 oe ee B4 B0_NO_GCC_DN 10_L2N_25 DCD BO NT VREF Be BO_P1 10_L3P_25 50 P2 A7 B0_N1_VREF 10_L3N_25 DCD BO N2 VREF B8 Bo_P2 10_L4P_25 DNI DCD BO P3 A9 B0_N2_VREF 1O_L4N_VREF_25 i DCD BONS B10 B0_P3 10_L5P_25 DCD BO P4 CC Ait B0_N3 10 L5N_25 DCD_BO_N4_CC B12 80_P4_CC 10_L6P_25 DTD Bo PS A13 BO_N4_ CC 1O_L6N_25 DCD_Bo_N5 B14 BO_PS 10_L7P_25 DCD BO P6 A15 BO_NS 10_L7N_25 Dco Bo Ne Bte 8B0 P6 10_L8P_SRCC_25 DCD B0 P7 A17 BONG 10_L8N_SRCC_25 DCD_BO_N7 Big BO_P7 10_L9P_MRCC_25 22 DCD_FEEDBACKp 42 DCD B0 Ps GCC BUS Es B0_N7 1O_L9N_MRCC_25 gt gt DCD_FEEDBACKn 42 DCD B0 N8 GCC BUS F5 80_P8_GCC_BU
96. to the bit file that you wish to use When the FPGA is done being configured a blue dot will appear next to any FPGA that has been configured The dot will stay blue until you clear the FPGA Also note that a blue LED will light on the board itself You can clear an FPGA by clicking on it and selecting clear from the pop up window 4 1 3 Clocks There are 6 global clock networks on the board that have user controllable settings Each of those clocks has it s frequency continually monitored and displayed on the main EMU window on the right side of the board photo To change the settings of the clocks you can click on the text displaying that clock s frequency A pop up window will display options for the clock Each clock may have different options and all options may not be available for all clocks For example clocks GO G1 and G2 can be set to a user specified frequency but USER_L and USER_R can not 4 1 4 Sending data to and from the FPGA The EMU program can also be used to transfer data to and from the FPGAs The name of the interface on the FPGA that can be accessed from EMU is called NMB The NMB interface can be thought of as an address space The EMU program can read and write to addresses on that space Select either NMB read or NMB write from the Data menu In order to transfer data to your FPGA your design must implement an NMB endpoint The code necessary to implement an NMB endpoint is provided on the user package
97. two wire serial interface The installed software will poll these IIC interfaces and measure the temperature of the FPGAs If the FPGAs are not within a specified temperature range the software will automatically clear the overheated FPGA both to alert the user to the problem and to prevent damage to the FPGAs 3 9 8 ICE There is an interface for running a hardware debugger on the Marvell processor It is not expected that anyone will use this interface and so details are omitted here DNV6F6PCIE User Manual Page 49 3 9 9 SDRAM The Marvell environment has 1GB of DRAM managed by Linux 3 9 10 SPI Bus Flash The linux kernel and uboot bootloader are contained on a SPI flash device The marvell boots by running instructions from address 0x0 of the SPI flash device There is a 4 pin SPI programming header attached to this SPI flash In order to program the flash device the Marvell must be continually held in reset to prevent interference with the SPI programming process 3 9 11 Ethernet The Marvell Processor natively contains three gigabit Ethernet port Only one of these three ports are enabled The ethernet port is managed by linux You are expected to use standard Linux programming APIs to access these ports from the Marvell side of the link and to write you own software for the host side of the link Several ports are used by the provided Emu software and you can use the communication framework provided to interact with your board
98. ughtercard Note that there is still the Virtex 6 I O rule that only a single type of DCI may be used per bank of the FPGA This requirement may limit the use of DCI on the daughter card The requirement is too complicated to describe here so you may need to run a test place and route of your design to determine whether your desired pin out is acceptable 3 7 3 Reset Signal The signal RSTn_3 3V_TOLERANT is valid when 2 5V_LDO is above 0 7V At all times when the signal RSTn_3 3V_TOLERANT is valid and has a voltage measuring below 0 7V then all boards using this interface host and daughtercard must tri state all I O signals connected to the interface Daughter cards that fail to tri state signals until the de assertion of RSTn_3 3V_TOLERANT may risk damaging the DNV6F6 board The DNV6F6 will weakly pull up this signal to 2 5V A daughter card is free to also pull up this signal weakly to any voltage between 0 7V and 3 3V DNV6F6PCIE User Manual Page 34 2 5V 2 5V o 0 TP2 DNI 14 TESTPOINT R4 R6 2 0K_0 1 DNI MON_DG_ADJ po 1 1 6 ADJ1 vec a J MON DC ADJZ zou A RST gt gt DAUGHTERCARD_RESETn 36 39 ie K MON_DC_TMR 1K 1K 7 MA c2 j DNI acia TMR tt male R347 g 4 R2 p DNI__MON_DC_SEL gs EF ono 4 E 10K_0 1 162909 c4 i lj 0 1uF HOR DC Linear Power Supply 2 5V 1mA 12v Current Pi Limits to RESC1005N 20mA u22 Dt
99. uration file Bitstream BUFG BUFH BUFIO BUFR DCM IDDR IDELAY ISERDES MMCM ODDR ODELAY OSERDES Thing that word means All of these words interchangeably refer to the file containing the data for the SRAM configuration bits for the FPGA This file is generated by the Xilinx bitgen program Each of these are primitive HDL modules available in the Virtex 6 FPGA It is assumed that the reader is familiar with the behavior and use of any primitives mentioned in each section Please see the Virtex 6 user guide for the behavior of these modules These words refer interchangeably to HDL code Digitally controlled impedance It refers to the ability of the FPGA to output optimally terminated signals DIFF_TERM Attribute that can be set on differential inputs to differentially end terminate them Digital clock manager Delay locked loop Phase locked loop something something clock manager These words are incorrectly used interchangeably in this guide Usually means double data rate meaning that a signal s value is significant on both rising and falling edges of a clock Sometimes this guide also uses DDR to refer to DRAM just to add confusion DRIVE attribute This refers to the ability of the FPGA to produce a variety of output Drive strength impedaces on its I O FPGA Q Config FPGA NMB Bridge There words are all used interchangeably to refer to the smaller Virtex 5 FPGA on the DNV6F6 DNV6F6PCIE Use
100. version are identical The command line version lends itself well to scripting 4 1 7 Scripting with EMU The command line version of EMU uses stdin and stdout for input and output and so it is possible to write scripts that interact with it In this way you potentially can use the board without ever having to write any software of your own If you the program with the c switch then the menu system is collapsed into one single monolithic menu and there is less output produced on stdout With this switch scripting is much easier DNV6F6PCIE User Manual Page 86 In the user package there is an example script that interfaces well with the command line version of EMU 4 1 8 Emu on the Marvell Linux environment The command line version of EMU is also installed on the Linux system that is installed on the Marvell CPU This allows EMU commands to be issued to the board using the RS232 terminal or over a telnet session to the board 4 2 Writing your own software To write your own software it is recommended that you start by attempting to compile the existing gui or command line version on Emu There is a Emu software manual that describes the process in the support package D Host_software_applications emu 4 3 How EmuLib works The Emu program and EmuLib communicate to the board through a tall stack of software linking the host PC to the Marvell processor the Marvell processor to the FPGA I Os and the FPGA I Os to your HDL
101. vesnsscswentsatatecnsacawcnssscascnendcteenashsueveveVevavessns AEE EEA AANE a EAV A ANARA 31 3 8 FPGA CONFIGURATION sesvssvesssxissscesescegand cseseas shat vatts teica ad in da 45 3 9 MARVELL CPU cosida 45 3 10 MARVEL TO NMB BRIDGE aiccen aeaea iseinean E EE AAEE EEE daa 51 E A A i O ON 53 3 12 GPIO ACCESS HEADER cascns sarirane Sasaki inorena araara ara EEE aa AE decasendaacstaadenestaa dined nad canechatecncaten cand andeeineanal cxacenavedin 54 3 13 WSER LEDS NN 56 3 14 FRGA TO FPGA ROGKETIO oi ds 56 3 15 SPU IELAS A Gectceas ccchaews goatee sacdadeend beateves ca daeseate daceanagavaui ecaueed E E E E 58 3 16 USER TEST POINTS ia a oros 59 3 17 MICTOR CONNECTOR sas ssdescvesives tees cnees Giuchaeaaes ends adanan o aa a aa SAAE DEE EA aKa a LEEA a aE EEEE A aKa a LEE REE 59 3 18 USER SATA wissecseecsssccntensccedendecasdenscadvensacasdensceatenssecsuitvans AAA EA AAE EAEE CAAA ANEA AAA AAA AR AEA CA VAARA AAA AAAA CAR AA 60 3 19 SFP AND ETHERNET ics ccctescas ccceonce devctiesnciicnnac desis vat cade onde deaeteaneddesesevneasasaed cand ANENE ada iaa darnos adan 61 3 20 ROCKETIO HEADER sssssessssshessetsaacesfscbeasdocasds a a aa Aaaa E AEAEE A AAE A AUAA OAE AAEE aa ia 63 3 21 ENCRYPTION vtsvoinsse ocd lectusetieassabsaseess eases soee decease eavecnssbawseyssuaniaes aaa a a a a a alias ds 65 A icare e a a aa e ai e a a a aa 67 3 23 MECHANICAL E E E ET 69 3 24 POWER Social rd a a 70 3 25 RESEW E E A E A E A A A A iris 74 3 26 SYSTEM MONITOR wiccc
102. vsusuvdanucaveisess 102 10 REVISION HISTORY cc iii olaa ebavn anak levedact ica EEE 105 DNV6F6PCIE User Manual Page 4 1 INTRODUCTION text 1 1 Audience This product is marketed and sold to engineers who are familiar with circuit board design physically probing AC waveforms programming FPGAs wiring HDL code reading device data sheets reading C source code and writing software The provided support material all assumes that the user already has these skills 1 2 Conventions text here 1 3 Resources The following list includes the resources that you are expected to make use of 1 3 1 Website The product page for this product is on the internet here http dinigroup com index php product DN V6F6PCle This page contains Block Diagram of the board Marketing Product description List supported features Latest Errata Latest software and firmware update package Latest version of this document 1 3 2 Product Package The board comes with a USB memory stick with files on it On the root directory there is a file called Support Package Contents pdf that describes the contents and the directory structure This package contains the software installed on the board as well as the software that should be installed on your host computer 1 3 3 Reference Design The product package contains a set of FPGA designs written in Verilog HDL that produce working configurations files for the FPGAs on the DNV6F6PCIE
103. ware these ports are managed by Linux and you are not intended to directly interact with SATA hardware Instead when a device is installed it is automatically mounted as a storage device with a filesystem From that point you should use Linux scripts and programs to interact with the mounted filesystem 3 94 DEV Bus NAND The root file system of the Linux installation is contained on the NAND Flash device connected to the Marvell s device bus The NAND is 256MB in size with the first 100MB already assigned to the Linux installation 3 9 5 DEV Bus FPGA The Marvell device bus is also attached to the config FPGA This connection has no purpose 3 9 6 USB The Marvell device natively provides a USB host and peripheral device The two host devices are managed by Linux You are not expected to interact directly with the host ports Instead when a device is detected Linux automatically mounts the devices as storage devices with filesystems You should write linux scripts and programs to interact with the mounted filesystems DNV6F6PCIE User Manual Page 48 The single device interface is intended to be used as a connection to a host PC that will be used with the provided EMU software You are expected to use the EMU controller library to interact with this device 3 9 7 TIC Bus Temperature Sensors The temperature sensors for the user FPGAs for the Marvell processor and for the config FPGA are connected to the Marvell s
104. x operating system Most standard Linux applications and utilities are already installed You are able to program the Marvell processor with your own code so that the board can operate as a stand alone device without the need for a host computer in production environments 4 4 1 Linux Provided The Linux kernel on the board is version 2 6 22 18 as of this writing There is no particular name for the distribution on the board however many of the common Linux utilities are provided by busybox 4 4 2 Operating from the shell terminal You can get a linux shell terminal by using telnet to access the board The board will register its host name with the dhcp server if the dhcp server supports dns The host name of the board will be in the form dnv6f6pcie xxxxxxx where xxxxxxx is the 7 digit serial number of the board The serial number can be found on the serial number sticker under the DIMM D memory socket You can also access a terminal using the RS232 connector located near the lower right corner of the board labeled Marvell Serial This connector is a standard computer serial port 2 x 5 connector can be used with the provided IDC to DB9 adapter cable The terminal settings are Baud 19200 Data Bits 8 Parity None Stop Bits 1 Flow Control OFF Emulation VT200 The RS232 output is also the system console so you will also see system messages on your terminal in addition to the shell output If this bothers you you need to us
105. x1 MV78200 a FF1759 FF1759 FF1759 Uzor 128M x 64 USB 2 6 x3 g Linux CPU CPU 129Mb Environment Boot FlasH DM A 4x GTX Expansion 128Mb GTX Expansion 128Mb SATA 2 Hea FLASH Peier fah x2 Evo 4 lanes RTC PCI EXPRESS 3 2 5 Safe Handling of FPGAs There are three easy ways to break the FPGAs 1 Static electricity Make sure you keep the board on a static controlled surface and that you neutralize your body with that surface before handling the board Especially sensitive are the FPGA I Os These are exposed on the daughter card headers and also everywhere else 2 High Voltage The FPGA I O can only withstand voltages below and up to the VCCO power supply When interfacing the board to some external I O make sure your I O signals are driven at levels that do not exceed VCCO If you do not know what VCCO is then you probably should not be interfacing the DNVO6F6PCIE User Manual Page 17 board to some external I O Note that the maximum allowable VCCO on Virtex 6 is 2 5V If you are interfacing with a 3 3V device then you automatically lose 3 Board warp If the board undergoes mechanical stress the FPGA pins balls can separate from the PCB and result in non connected signals The only way I have seen people doing this is by installing and removing connectors Make sure that when installing a connector you are supporting the connector from the opposite side so that bo

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