Home
Brown DE2 Labs
Contents
1. SIGNAL slow count STD LOGIC VECTOR 24 DOWNTO 0 SIGNAL hr 1 hr 0 min 1 min 0 sec 1 sec 0 STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL mod hr 0 STD LOGIC VECTOR 3 DOWNTO 0 used to change hour LSB from 19 to 20 or 22 to 00 SIGNAL E sec 0 E sec 1 E min 0 E min 1 E hr 0 E hr 1 STD LOGIC BEGIN Create a 1Hz 4 bit counter First a large counter to produce a 1 second approx enable PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 THEN slow count lt slow count 1 END IF END PROCESS 6 digit clock display modulo R M CLOCK 50 Resetn L E 0 E sec 0 lt 1 WHEN slow count 0 ELSE 0 seconds 0 modulo PORT MAP 0000 1001 CLOCK 50 KEY 3 0 E sec 0 sec 0 E sec 1 lt 1 WHEN sec 0 9 AND E sec 0 1 ELSE 0 seconds 1 modulo PORT MAP 0000 0101 CLOCK 50 KEY 3 0 E sec 1 sec 1 E min O lt 1 WHEN sec 1 5 AND E sec 1 1 ELSE 0 minutes 0 modulo PORT MAP SW 3 DOWNTO 0 1001 CLOCK 50 KEY 3 NOT KEY 0 E min 0 min 0 E min 1 lt 1 WHEN min 0 9 AND E min 0 1 ELSE 0 minutes 1 modulo PORT MAP SW 7 DOWNTO 4 0101 CLOCK 50 KEY 3 NOT KEY 0 E min 1 min 1 E hr 0 lt 1 WHEN min 1 5 AND E min 1 1 ELSE 0 mod hr 0 lt 0011 WHEN hr 1 2 ELSE 1
2. ER EC EC E E EC TOR 15 DOWNTO 0 TOR 3 DOWNTO 0 TOR O TO 6 CTOR 15 DOWNTO 0 CTOR 15 DOWNTO 0 TOR 15 DOWNTO 0 TOR 15 DOWNTO 0 KEYO is resetn KEY1 is the clock for reg A ENTITY part5 IS PORT SW IN STD LOGIC V KEY IN STD LOGIC V HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC V END part5 ARCHITECTURE Behavior OF part5 IS COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT COMPONENT regne PORT R IN STD LOGIC VE Clock Resetn IN STD LOGIC Q OUT STD LOGIC VE END COMPONENT SIGNAL A B STD LOGIC VECTOR 15 DOWNTO 0 BEGIN regne R Clock Resetn En Q A reg regne PORT MAP SW KEY 1 KEY 0 A B lt SW drive the displays through 7 seg decoders digit 7 hex7seg PORT MAP A 15 DOWNTO 12 HEX7 digit 6 hex7seg PORT MAP A 11 DOWNTO 8 HEX6 digit 5 hex7seg PORT MAP A 7 DOWNTO 4 HEX5 digit 4 hex7seg PORT MAP A 3 DOWNTO 0 HEX4 digit 3 hex7seg PORT MAP B 15 DOWNTO 12 HEX3 digit 2 hex7seg PORT MAP B 11 DOWNTO 8 HEX2 digit 1 hex7seg PORT MAP B 7 DOWNTO 4 HEX1 digit 0 hex7seg PORT MAP B 3 DOWNTO 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS PORT R IN STD LOGIC VECT Clock Resetn IN STD LOGIC Q OUT STD LOGIC VECT END regne ARCHITECTURE Behavior OF regne IS
3. ayed on HEX5 HEX4 S2 Sl SO is displayed on HEX2 HEX1 HEXO PORT SW IN STD LOGIC VECTOR 15 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 7 segs HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 7 segs END part6 ARCHITECTURE Behavior OF part6 IS COMPONENT bcd7seg PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Al A0 Bl BO STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL 52 STD LOGIC SIGNAL 51 SO STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL Z1 Z0 STD LOGIC VECTOR 3 DOWNTO 0 used for BCD addition SIGNAL T1 TO STD LOGIC VECTOR 4 DOWNTO 0 used for BCD addition SIGNAL C1 C2 STD LOGIC used for BCD addition BEGIN Al lt SW 15 DOWNTO 12 AO lt SW 11 DOWNTO 8 Bl lt SW 7 DOWNTO 4 BO lt SW 3 DOWNTO 0 add lower two bcd digits Result is five bits C1 50 TO lt 0 amp AO 0 amp BO PROCESS TO BEGIN IF TO gt 01001 THEN Z0 lt 0110 we will add 6 instead of 10 Cl lt 11 ELSE ZO lt 0000 we will add 6 instead of 10 Cl lt 0 END IF END PROCESS SO lt TO 3 DOWNTO 0 20 using 4 bits 6 is same as 10 add upper two bcd digits plus C1 Tl lt O 8 Al O amp Bl Cl PROCESS T1 BEGIN IF T1 gt 01001 THEN Z1 lt 0110 we will add 6 instead of 10 C2 lt VAN
4. END hex7seg part2 vhd ARCHITECTURE Behavior OF hex7seg IS BEGIN e 0 m Si 6 4 12 gt 3 PROCESS hex BEGIN CAS ex zzzzzzzzzzzzzzzr I Ej EJ EH EJ Dd Ed DH EJ Dd BH EJ bd p EJ op p zu zzz zz zz ee Eu o S OT END CASE END PROCESS END Behavior disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 y F F F p r r f F i y LS p Page 2 part3 vhd Page 1 This code instantiates a 32 x 8 memory n the Cyclone II FPGA on the DE2 board inputs KEYO is the clock SW7 SWO provides data to write into memory SW15 SW11 provides the memory address SW17 is the memory Write input outputs 7 seg displays HEX7 HEX6 display the memory addres HEX5 HEX4 displays the data input to the memory and HEX1 HEXO show the contents read from the memory LEDGO shows the status of Write LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic arith all USE ieee std logic unsigned all ENTITY part3 IS PORT
5. ARCHITECTURE Behavior OF flip flop IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt 0 ELSIF E 1 THEN Q lt R END IF END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 5 11 m 6 J 12 3 PROCESS hex PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 Page 3 part7 vhd BEGIN CASE hex IS Ge 0000 WHEN 0001 WHEN 0010 WH EN 0 0 1 WHEN 0100 WHEN 0101 WHEN 0110 WHI EN 0 1 1 WHEN 1000 WHEN 1001 WHEN 1010 WH EN 1 0 1 WHEN 1100 WH EN 1 1 01 WHEN 171710 WHEN OTHERS END CASE END Behavior END PROCESS disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 00011 00 0001000 1100000 0110001 1000010 0110000 0111000 P F r T p y r F F f E Fr FK E Page 4 Laboratory Exercise 9 A Simple Processor Figure 1 shows a digital syst
6. END PROCESS the read address counter PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Read address lt OTHERS gt 0 ELSIF slow count 0 THEN Read address lt Read address 1 END IF END IE END PROCESS Address lt Write address WHEN Write 1 ELSE Read address instantiate LPM module module ramlpm address clock data wren q m32x8 ramlpm PORT MAP Address Clock Dataln Write DataOut display the data input data output and address on the 7 segs digit0 hex7seg PORT MAP DataOut 3 DOWNTO 0 HEX0 digitl hex7seg PORT MAP DataOut 7 DOWNTO 4 HEX1 digit2 hex7seg PORT MAP Read address 3 DOWNTO 0 HEX2 digit3 hex7seg PORT MAP 000 amp Read address 4 HEX3 digit4 hex7seg PORT MAP DataIn 3 DOWNTO 0 HEX4 digit5 hex7seg PORT MAP DataIn 7 DOWNTO 4 HEX5 digit6 hex7seg PORT MAP Write Address 3 DOWNTO 0 HEX6 digit7 hex7seg PORT MAP 000 amp Write Address 4 HEX7 LEDG 0 lt Write END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF CLock EVENT AND Clock
7. proc vhd Page 3 ELSE Sum lt A BusWires END IF END PROCESS reg G regn PORT MAP Sum Gin Clock G define the internal processor bus Sel lt Rout amp Gout amp DINout busmux PROCESS Sel RO R1 R2 R3 R4 R5 R6 R7 G DIN BEGIN IF Sel 1000000000 THEN BusWires lt RO ELSIF Sel 0100000000 THEN BusWires lt R1 ELSIF Sel 0010000000 THEN BusWires lt R2 LSIF Sel 0001000000 THEN BusWires lt R3 LSIF Sel 0000100000 THEN BusWires lt R4 LSIF Sel 0000010000 THEN BusWires lt R5 LSIF Sel 0000001000 THEN BusWires lt R6 ELSIF Sel 0000000100 THEN BusWires lt R7 LSIF Sel 0000000010 THEN BusWires lt G LSE BusWires lt DIN END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic signed all ENTITY upcount IS PORT Clear Clock IN STD LOGIC Q OUT STD LOGIC VECTOR 1 DOWNTO 0 END upcount ARCHITECTURE Behavior OF upcount IS SIGNAL Count STD LOGIC VECTOR 1 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Clear 1 THEN Count lt 00 ELSE Count lt Count 1 END IF END IF F END PROCESS Q lt Count END Behavior LIBRARY ieee USE ieee std logic 1164 all proc vhd Page 4 ENTITY dec3to8 IS PORT IN STD LOGIC VECTOR 2 DOWNTO 0 n IN STD LOGIC O
8. 58 END CASE END PROCESS PROCESS BEGIN TF ll V Jg Ow Own A E a A a a ZO Zoya 2 Ei zj ZH iD Ei E r4 Ed Ed r4 bd Dd H4 pd Dd n3 b bd n3 p pd Q OA Mp UO lt S2 1 lt 83 rir lt S4 ED lt 55 vn lt 56 rt lt 87 8 state table Clock Clock IF Resetn y_Q lt SG ELSE LO y_Q lt Y_D END END IF END PROCESS IF EVENT AND Clock THEN UL THEN lt S4 lt 5 lt S6 lt ST lt 58 synchronous clear state outputs PROCESS y 0 BEGIN pipe select CASE y Q IS WHEN SO gt WHEN S1 gt WHEN S2 gt WHEN S3 gt WHEN S4 gt WHEN S5 gt WHEN S6 gt WHEN S7 gt WHEN S8 gt END CASE END PROCESS SONS FSM FSM FSM FSM FSM FSM FSM FSM FSM char lt char char char char char char char char se x me one lI UJ UJ UJ O E E Ed Sa s pipe select lt state output pipe_input lt FSM_char WHEN egne R Clock Resetn UO U1 U2 U3 UA U5 U6 U7 EXO EX1 EX2 EX3 EX4 modio oon regne regne regne regne regne regne regne regne PORT PORT PORT PORT N PORT I PORT PORT PORT lt piped lt pipel lt pipe2 lt pipe3 lt pipe4 pi pi pi pi pi pi p
9. H OUT STD LOGIC VECTOR 0 TO 6 END bcd7seg ARCHITECTURE Structure OF bcd7seg IS BEGIN part2 vhd Page 2 B H 0 0000001 1 1001111 2 0010010 3 0000110 4 1001100 5 0100100 6 1100000 7 0001111 8 0000000 9 0001100 H 0 lt B 2 AND NOT B 0 OR NOT B 3 AND NOT B 2 AND NOT B 1 AND B 0 H 1 lt B 2 AND NOT B 1 AND B 0 OR B 2 AND B 1 AND NOT B 0 H 2 lt NOT B 2 AND B 1 AND NOT B 0 H 3 lt NOT B 2 AND NOT B 1 AND B 0 OR B 2 AND NOT B 1 AND NOT B 0 OR B 2 AND B 1 AND B 0 H 4 lt NOT B 1 AND B 0 OR NOT B 3 AND B 0 OR NOT B 3 AND B 2 AND NOT B 1 H 5 lt B 1 AND B 0 OR NOT B 2 AND B 1 OR NOT B 3 AND NOT B 2 AND B 0 H 6 lt B 2 AND B 1 AND B 0 OR NOT B 3 AND NOT B 2 AND NOT B 1 END Structure part3 vhd 4 bit ripple carry adder LIBRARY ieee USE ieee std logic 1164 all ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 7 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 7 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 4 DOWNTO 0 END part3 ARCHITECTURE Structure OF part3 IS COMPONENT fa PORT a b ci IN STD LOGIC S CO OUT STD LOGIC END COMPONENT SIGNAL A B S STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL C STD LOGIC VECTOR 4 DOWNT
10. WHEN 100 gt 1d Rx Ry WD lt 0 do nothing wait cycle for synchronous memory WHEN OTHERS gt st Ryl Rx Rout lt Xreg DOUTin lt 1 WD lt 1 END CASE WHEN OTHERS gt define T5 CASE I IS WHEN 010 gt add Gout lt 1 Rin lt Xreg Done lt 1 WHEN 011 gt sub Gout lt 1 Rin lt Xreg Done lt 1 WHEN 100 gt 1d Rx Ry DINout lt 1 Rin lt Xreg Done lt 1 WHEN OTHERS gt st Ryl Rx Done lt 1 wait cycle for synhronous memory END CASE END CASE END PROCESS reg_0 regn PORT MAP BusWires Rin 0 Clock RO reg 1 regn PORT MAP BusWires Rin 1 Clock R1 reg_2 regn PORT MAP BusWires Rin 2 Clock R2 reg_3 regn PORT MAP BusWires Rin 3 Clock R3 reg 4 regn PORT MAP BusWires Rin 4 Clock R4 reg 5 regn PORT MAP BusWires Rin 5 Clock R5 reg_6 regn PORT MAP BusWires Rin 6 Clock R6 R7 is program counter pc count R Resetn Clock E L 0 pc po count PORT MAP BusWires Resetn Clock pc inc Rin 7 R7 reg A regn PORT MAP BusWires Ain Clock A reg DOUT regn PORT MAP BusWires DOUTin Clock DOUT reg ADDR regn PORT MAP BusWires ADDRin Clock ADDR reg IR regn GENERIC MAP n 9 PORT MAP DIN 15 DOWNTO 7 IRin Clock reg W flipflop PORT MAP W D Resetn Clock W alu alu PROCESS AddSub A BusWires BEGIN IF AddSub 0 THEN Sum lt A Bus
11. if wl w0 11 decrement count by 1 drive count to digit HEXO ENTITY part4 IS PORT SW IN STD LOGIC VECTOR 2 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part4 ARCHITECTURE Behavior OF part4 IS COMPONENT bcd7seg PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn STD LOGIC SIGNAL w STD LOGIC VECTOR 1 DOWNTO 0 TYPE State type IS A B C D E F G H I J SIGNAL y 0 Y D State type SIGNAL Count STD LOGIC VECTOR 3 DOWNTO 0 BEGIN Clock lt KEY 0 Resetn SW 0 w 1 DOWNTO 0 IE SW 2 DOWNTO 1 PROCESS w y Q state table BEGIN CASE y Q IS WHEN A gt CASE w IS WHEN 00 gt Y D lt A WHEN 01 gt Y D lt B WHEN 10 gt Y D lt C WHEN 11 gt Y D lt J END CASE WHEN B gt CASE w IS WHEN 00 gt YD lt B WHEN 01 gt YD lt C WHEN 10 gt YD lt D WHEN 11 gt YD lt A END CASE WHEN C gt CASE w IS WHEN 00 gt YD lt C WHEN 01 gt YD lt D WHEN 10 gt YD lt E WHEN 11 gt YD lt B END CASE WHEN D gt CASE w IS WHEN 00 gt YD lt D WHEN 01 gt YD lt E WHEN 10 gt YD lt F WHEN 11 gt YD lt C END CASE WHEN E gt CASE w IS WHEN 00 gt YD lt E WHEN 01
12. state flip flops BEGIN END PROCESS assignments for output z and the LEDs END Behavior Figure 3 Skeleton VHDL code for the FSM Implement your circuit as follows 1 2 Create a new project for the FSM Select as the target chip the Cyclone II EP2C35F672C6 Include in the project your VHDL file that uses the style of code in Figure 3 Use the toggle switch SW y on the Altera DE2 board as an active low synchronous reset input for the FSM use SW as the w input and the pushbutton KEY as the clock input which is applied manually Use the green LED LEDG y as the output z and use nine red LEDs LEDRg to LEDRo to indicate the present state of the FSM Assign the pins on the FPGA to connect to the switches and the LEDs as indicated in the User Manual for the DE2 board Before compiling your code it is possible to tell the Synthesis tool in Quartus II what style of state as signment it should use Choose Assignments gt Settings in Quartus II and then click on the Analysis and Synthesis item on the left side of the window As indicated in Figure 4 change the parameter State Machine Processing to the setting Minimal Bits To examine the circuit produced by Quartus II open the RTL Viewer tool Double click on the box shown in the circuit that represents the finite state machine and determine whether the state diagram that it shows properly corresponds to the one in Figure 2 To see the state codes used for your FSM o
13. 0 THEN Y D lt B ELSE Y D lt G END IE WHEN G gt IF w 0 THEN Y D lt B ELSE Y D lt H END IE WHEN H gt IF w 0 THEN Y D lt B ELSE Y_D lt 1 END IF WHEN I gt IF w 0 THEN Y D lt B ELSE Y D lt 1 END IF WHEN OTHERS gt Y D lt A END CASE END PROCESS state table PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear y_0 lt A ELSE y Q lt Y D FND IF END IF part2 vhd Page 2 END PROCESS z lt 1 WHEN y O E OR y_Q I ELSE 0 LEDG 0 lt z PROCESS y 0 drive the red LEDs for each state BEGIN LEDR lt 000000000 case y 0 IS WHEN A gt LEDR lt 000000001 WHEN B gt LEDR lt 000000010 WHEN C gt LEDR lt 000000100 WHEN D gt LEDR lt 000001000 WHEN E gt LEDR lt 000010000 WHEN F gt LEDR lt 000100000 WHEN G gt LEDR lt 001000000 WHEN H gt LEDR lt 010000000 WHEN I gt LEDR lt 100000000 END CASE END PROCESS LEDs END Behavior part3 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all a sequence detector FSM using a shift register SWO is the active low synchronous reset SWL is the w input and KEYO is the clock The z output appears on LEDGO and the shift register FFs appear on LEDR3 0 a sequence detector shi
14. 1001 THEN sec 0 lt 0000 IF sec 1 1001 THEN sec 1 lt 0000 IF min O 1001 THEN min 0 lt 0000 IF min 1 1001 THEN min 1 lt 0000 ELSE min 1 lt min 1 1 END IF ELSE min 0 lt min 0 1 END IF ELSE sec 1 lt sec 1 1 END IF ELSE sec 0 lt sec 0 1 END IF END IF END IF END PROCESS EVENT AND CLOCK 50 1 THEN 0 THEN 0000 0 0 0 T drive the displays blank the unused displays digit7 bcd7seg PORT MAP 1111 HEX7 digit6 bcd7seg PORT MAP 1111 HEX6 digit5 bcd7seg PORT MAP 1111 HEX5 digit4 bcd7seg PORT MAP 1111 HEX4 digit3 bcd7seg PORT MAP min 1 HEX3 digit2 bcd7seg PORT MAP min 0 HEX2 digitl bcd7seg PORT MAP sec 1 HEX1 digit0 bcd7seg PORT MAP sec 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY regne IS PORT R Clock Resetn E IN STD LOGIC Q OUT STD LOGIC END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Q lt 0 Page 2 part3 vhd ELSIF E 1 THEN O lt R END IF END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT bcd IN STD LOGIC VECTOR 3 display OUT STD LOGIC VECTOR 0 END bcd7seg ARCHITECTU
15. BEGIN DB latch input Clk Ul D latch PORT MAP END Structural LIBRARY ieee USE ieee std logic 1164 all D input SW 1 is the level sensitive Clk STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC VECTOR O TO 0 OF top IS IN STD LOGIC OUT STD LOGIC z D Output O SW 1 SW 0 LEDR 0 all A gated D latch described the hard way ENTITY D latch IS PORT Clk D IN STD LOGIC Q OUT STD LOGIC END D latch ARCHITECTURE Structural SIGNAL R Rg S9 Q ATTRIBUTE keep boole ATTRIBUTE keep of R BEGIN R lt NOT D S g lt NOT D AND Clk Rg lt NOT R AND Clk Qa lt NOT S g AND Qb Ob lt NOT R g AND Qa Q lt Qa END Structural OF D latch IS a Ob STD LOGIC an Rg S g Qa Ob signal is true i LEDR 0 28 Q Page 1 part3 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all SW 0 is the flip flop s D input SW 1 is the edge sensitive Clock LEDR O is Q ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 0 TO 0 END part3 ARCHITECTURE Structural OF part3 IS COMPONENT D latch PORT Elk D IN STD LOGIC Q OUT SID LOGIC END COMPONENT SIGNAL Om Os STD LOGIC BEGIN gt D latch input Clk D output 0 Ul D latch PORT MAP NOT SW 1 SW 0 Qm U2 D latch PORT MAP SW 1 Qm Qs LEDR 0 lt Qs END Structural
16. IN STD LOGIC OUT STD LOGIC VECTOR O TO 6 ARCHITECTURE Behavior OF part4 IS COMPONENT bcd7seg PORT bcd END COMPONENT SIGNAL bcd STD LOGIC V SIGNAL slow count BEGIN IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 ECTOR 3 DOWNTO 0 STD LOGIC VECTOR 24 DOWNTO 0 SIGNAL digit flipper STD LOGIC VECTOR 3 DOWNTO 0 Create a 1Hz 4 bit counter First a large counter to produce a 1 second approx from the 50 MHz Clock PROCESS CLOCK 50 BEGIN IF CLOCK 50 EV slow count lt slow count 1 END IF END PROCESS ENT AND CLOCK 50 1 THEN four bit counter that uses a slow enable for selecting digit PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENI IF slow count IF digit fl AND CLOCK 50 1 THEN 0 THEN lipper 1001 THEN digit flipper 0000 ELSE digit flipper lt digit flipper 1 END IF END IF END IF END PROCESS bcd lt digit flipper drive the display through a 7 seg decoder digit 0 bcd7seg PORT MAP bcd HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT bcd display END bcd7seg IN STD LOGIC VEC OUT STD LOGIC VECT ARCHITECTURE Behavior OF bcd7seg IS BEGIN OR 3 DOWNTO 0 TOR O TO 6 Page 1 part4 vhd 6 1 Ec 4
17. LED LED Delay Save address of next Nested delay Decrement R4 jnz Inner Decrement R3 jnz Outer Restore regs Read switch valuatio Save address of next inst mem mif Page 3 END
18. R1 addr lt 1 WHEN Addr 001 ELSE 0 R2 addr lt 1 WHEN Addr 010 ELSE 0 R3 addr lt 1 WHEN Addr 011 ELSE 0 R4 addr lt 1 WHEN Addr 100 ELSE 0 R5 addr lt 1 WHEN Addr 101 ELSE 0 R6 addr lt 1 WHEN Addr 110 ELSE 0 R7 addr lt 1 WHEN Addr 111 ELSE 0 reg R0 regne PORT MAP Data Clock Resetn Sel AND RO Addr RO reg R1 regne PORT MAP Data Clock Resetn Sel AND R1 Addr R1 reg R2 regne PORT MAP Data Clock Resetn Sel AND R2 Addr R2 reg R3 regne PORT MAP Data Clock Resetn Sel AND R3 Addr R3 reg R4 regne PORT MAP Data Clock Resetn Sel AND R4 Addr RA reg R5 regne PORT MAP Data Clock Resetn Sel AND R5 Addr R5 reg R6 regne PORT MAP Data Clock Resetn Sel AND R6 Addr R0 reg R7 regne PORT MAP Data Clock Resetn Sel AND R7 Addr R7 HEX7 lt RO HEX6 lt R1 HEX5 lt R2 HEX4 lt R3 HEX3 lt R4 HEX2 lt R5 HEX1 lt R6 HEXO lt R7 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS GENERIC n INTEGER 7 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock seg7 scroll vhd Page 2 BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Q lt OTHERS gt 0 ELSIF E rL THEN Q lt END
19. bin6 3 DOWNTO 0 1000 40 00101000 11011000 add 8 LSIF bin6 111100 THEN bcd h lt 0101 bed 1 lt bin6 3 DOWNTO 0 1110 50 00110010 11001110 add 14 LSE bcd h lt 0110 bcd 1 lt bin6 3 DOWNTO 0 0100 60 00111100 11000100 add 4 END IF END PROCESS drive the displays digiti bcd7seg PORT MAP bcd h HEX1 digit0 bcd7seg PORT MAP bcd 1 HEX0 blank the adjacent displays digit3 bcd7seg PORT MAP 1111 HEX3 digit2 bcd7seg PORT MAP 1111 HEX2 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS part7 vhd PORT bed IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 END bcd7seg ARCHITECTURE Behavior OF bcd7seg IS BEGIN 0 5 fil 6 Ap 12 s 3 PROCESS bcd BEGIN CASE bcd IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN OTHERS gt display lt 1111111 END CASE END PROCESS END Behavior TO 6 Page 2 La
20. y Q 7 Y D 8 y Q 7 OR y Q 8 AND w U8 flipflop PORT MAP Y D 8 Clock Resetn 1 y Q 8 z lt y Q 4 OR y Q 8 LEDR 8 DOWNTO 0 lt y Q 8 DOWNTO 0 LEDG 0 lt z END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Clock Resetn Setn IN STD LOGIC Q OUT SID LOGIC END flipflop ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt 0 partl vhd ELSIF Setn 0 THEN Q et ELSE Q lt D END IF END IF END PROCESS END Behavior synchronous set Page 2 partlb vhd LIBRARY ieee USE ieee std logic 1164 all Page 1 A sequence detector FSM using one hot encoding SWO is the active low synchronous reset SWl is the w input and KEYO is the clock The z output appears on LEDGO and the state FFs appear on LEDR8 0 ENTITY partl IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 8 DOWNTO 0 END partl ARCHITECTURE Behavior OF partl IS COMPONENT flipflop PORT D Clock Resetn IN STD LOGIC Q OUT STD LOGIC END COMPONENT SIGNAL Clock Resetn w Z STD LOGIC SIGNAL y 0 YD STD LOGIC VECTOR 8 DOWNTO 0 BEGIN Clock lt KEY 0
21. 1110001 T WHEN 011 gt display lt 1110001 Pt WHEN 100 gt display lt 0000001 Lar WHEN 101 gt display lt 1111111 se MM WHEN 110 gt display lt 1111111 gt s WHEN OTHERS gt display lt 1111111 END CASE END PROCESS END Behavior Laboratory Exercise 6 Clocks and Timers This is an exercise in implementing and using a real time clock Part I Implement a 3 digit BCD counter Display the contents of the counter on the 7 segment displays HEX2 0 Derive a control signal from the 50 MHz clock signal provided on the Altera DE2 board to increment the contents of the counter at one second intervals Use the pushbutton switch KEY to reset the counter to 0 1 Create a new Quartus II project which will be used to implement the desired circuit on the DE2 board 2 Write a VHDL file that specifies the desired circuit 3 Include the VHDL file in your project and compile the circuit 4 Simulate the designed circuit to verify its functionality 5 Assign the pins on the FPGA to connect to the 7 segment displays and the pushbutton switch as indicated in the User Manual for the DE2 board 6 Recompile the circuit and download it into the FPGA chip 7 Verify that your circuit works correctly by observing the display Part II Design and implement a circuit on the DE2 board that acts as a time of day clock It should display the hour from 0 to 23 on the 7 segment disp
22. 4 Enable 5 lt Count 4 AND Enable 4 TFF5 ToggleFF PORT MAP Enable 5 Clock Resetn Count 5 Enable 6 lt Count 5 AND Enable 5 TFF6 ToggleFF PORT MAP Enable 6 Clock Resetn Count 6 Enable 7 lt Count 6 AND Enable 6 FF7 ToggleFF PORT MAP Enable 7 Clock Resetn Count 7 Enable 8 lt Count 7 AND Enable 7 TFF8 ToggleFF PORT MAP Enable 8 Clock Resetn Count 8 Enable 9 lt Count 8 AND Enable 8 TFF9 ToggleFF PORT MAP Enable 9 Clock Resetn Count 9 Enable 10 lt Count 9 AND Enable 9 FF10 ToggleFF PORT MAP Enable 10 Clock Resetn Count 10 Enable 11 lt Count 10 AND Enable 10 FF11 ToggleFF PORT MAP Enable 11 Clock Resetn Count 11 Enable 12 lt Count 11 AND Enable 11 TFF12 ToggleFF PORT MAP Enable 12 Clock Resetn Count 12 Enable 13 lt Count 12 AND Enable 12 TFF13 ToggleFF PORT MAP Enable 13 Clock Resetn Count 13 Enable 14 lt Count 13 AND Enable 13 FF14 ToggleFF PORT MAP Enable 14 Clock Resetn Count 14 Enable 15 lt Count 14 AND Enable 14 FF15 ToggleFF PORT MAP Enable 15 Clock Resetn Count 15 partl vhd drive the displays digit3 hex7seg PORT MAP Count 15 DOWNTO 12 HEX3 digit2 hex7seg PORT MAP Count 11 DOWNTO 8 HEX2 digitl hex7seg PORT MAP Count 7 DOW
23. 7 DOWNTO 0 END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn Write Write sync STD LOGIC SIGNAL Write address Write address sync STD LOGIC VECTOR 4 DOWNTO 0 SIGNAL Read address Address STD LOGIC VECTOR 4 DOWNTO 0 Read address cycles from addresses 0 to 31 at one second per address SIGNAL slow count STD LOGIC VECTOR 24 DOWNTO 0 SIGNAL Dataln DataIn sync DataOut STD LOGIC VECTOR 7 DOWNTO 0 BEGIN Resetn lt KEY 0 Clock lt CLOCK 50 synchronize all asynchronous inputs to the clock R1 flip flop PORT MAP SW 17 Clock Resetn 1 Write sync R2 flip flop PORT MAP Write sync Clock Resetn 1 Write R3 regne GENERIC MAP N gt 5 PORT MAP SW 15 DOWNTO 11 Clock Resetn 1 Write address sync R4 regne GENERIC MAP N gt 5 PORT MAP Write address sync Clock Resetn 1 Write address part6 vhd Page R5 regne GENERIC MAP N gt 8 PORT MAP SW 7 DOWNTO 0 Clock Resetn 1 Dataln sync R6 regne GENERIC MAP N gt 8 PORT MAP Dataln sync Clock Resetn 1 Dataln one second cycle counter Create a 1Hz 5 bit address counter A large counter to produce a 1 second approx enable PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN slow count lt slow count 1 END IF
24. B 7 DOWNTO 4 HEX5 B 3 DOWNTO 0 HEX4 15 DOWNTO 12 HEX3 11 DOWNTO 8 HEX2 7 DOWNTO 4 HEX1 3 DOWNTO 0 HEXO P P P P D LOGIC VECTOR 3 DOWNTO 0 ID LOGIC VECTOR 0 TO 6 ARCHITECTURE Behavior OF hex7seg IS BEGIN Page 1 part3 vhd 0 gt 3 PROCESS hex BEGIN CASE hex IS WHEN 000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 0 0 L WHEN 1010 WHEN 1 0 11 WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 i f r f f F r F r F r i Page 2 Laboratory Exercise 4 Latches Flip flops and Registers The purpose of this exercise is to investigate latches flip flops and registers Part I Altera FPGAs include flip flops that are available for implementing a user s circuit We will show how to make use of these flip flops in Parts IV to VII of this exercise But first we will show how storage elements can be created in an
25. CLOCK_50 slow_count END IF END PROCESS STD LOGIC V ST Create a 1Hz 4 bit counter a large counter to produce a 1 second CLOCK 50 EVENT AND CLOCK 50 lt slow count vq Yu ECTOR 24 DOWNTO 0 D LOGIC VECTOR 3 DOWNTO 0 approx enable THEN 3 digit BCD counter that uses a slow enable PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 IF KEY 3 0 THEN bcd 0 lt 0000 bcd 1 lt 0000 bcd 2 lt 0000 ELSIF slow count 0 THEN IF bcd 0 1001 THEN bcd 0 lt 0000 IF bcd 1 1001 THEN bcd 1 0000 IF bcd 2 1001 THEN bcd 2 0000 ELSE bed 2 lt bed 2 1 END IF ELSE bed 1 lt bed 1 1 END IF ELSE bcd 0 lt bcd 0 1 END IF END IF END IF END PROCESS drive the displays digit2 bcd7seg PORT MAP bcd 2 HEX2 digiti bcd7seg PORT MAP bcd 1 HEX1 digit0 bcd7seg PORT MAP bcd 0 HEX0 blank the adjacent display digit3 bcd7seg PORT MAP 1111 HEX3 END Behavior THEN Page 1 partl vhd LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT bcd display END bcd7seg IN STD LOGIC VECTOR 3 OUT STD LOGIC VECTOR 0 ARCHITECTURE Behavior OF bcd7seg IS BEGIN 0 5 1 G 4 2 sues 3 PROCESS bcd BEGIN CASE bcd IS WHEN 0000 WHEN 0001 WHEN 0
26. Create a new Ouartus II project for your BCD adder You should use the four bit adder circuit from part III to produce a four bit sum and carry out for the operation A B A circuit that converts this five bit result which has the maximum value 19 into two BCD digits 5150 can be designed in a very similar way as the binary to decimal converter from part II Write your VHDL code using simple assignment statements to specify the required logic functions do not use other types of VHDL statements such as IF ELSE or CASE statements for this part of the exercise Use switches SW7 4 and SW3_o for the inputs A and B respectively and use SW for the carry in Connect the SW switches to their corresponding red lights LEDR and connect the four bit sum and carry out produced by the operation A B to the green lights LEDG Display the BCD values of 4 and B on the 7 segment displays HEX6 and HEX4 and display the result 5150 on HEX and HEXO Since your circuit handles only BCD digits check for the cases when the input A or B is greater than nine If this occurs indicate an error by turning on the green light LEDG 3 Include the necessary pin assignments for the DE2 board compile the circuit and download it into the FPGA chip Test your circuit by trying different values for numbers A B and c jn Part V Design a circuit that can add two 2 digit BCD numbers A1 Ao and B By to produce the three digit BCD sum 525150 Use two instan
27. ELSE Z1 lt 0000 we will add 6 instead of 10 G2 lt 10 s END IF END PROCESS S1 lt T1 3 DOWNTO 0 Z1 using 4 bits 6 is same as 10 S2 2023 Page 1 part6 vhd drive the displays through 7 seg decoders digit7 bcd7seg PORT digit6 bcd7seg PORT digit5 bcd7seg PORT digit4 bcd7seg PORT digit2 bcd7seg PORT digitl bcd7seg PORT digit0 bcd7seg PORT HEX3 1111111 END Behavior LIBRARY ieee USE ieee std logic 1164 ENTITY bcd7seg IS PORT X bcd display END bcd7seg ARCHITECTURE Behavior O BEGIN 0 av 5 11 6 ms I A4 12 S Il 3 PROCESS bcd BEGIN CASE bcd IS HEN 0000 gt HEN 0001 gt HEN 0010 gt HEN 0011 gt HEN 0100 gt z gt ES G Eri 0101 gt HEN 0110 gt HEN 0111 gt HEN 1000 gt HEN 1001 gt HEN OTHERS gt END CASE END PROCESS END Behavior MAP Al HEX7 MAP AO HEX6 MAP Bl HEX5 MAP BO HEX4 MAP 000 amp S2 HEX2 MAP S1 HEX1 MAP SO HEXO turn off HEX3 all IN STD LOGIC VECTOR 3 DOWNTO 0 OUT STD LOGIC VECTOR 0 TO 6 F bcd7seg IS display lt 0000001 display lt 1001111 display lt 0010010 display lt 0000110 display lt 1001100 display lt 0100100 display lt 1100000 display lt 0001111 display lt 0000000 display lt 000110
28. HEX0 DataOut 7 DOWNTO 4 HEX1 DataIn 3 DOWNTO 0 HEX4 DataIn 7 DOWNTO 4 HEX5 Address 3 DOWNTO 0 HEX 000 amp Address 4 HEX7 OR N 1 DOWNTO 0 GENERIC N integer 7 PORT R IN STD LOGIC VECT Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECT END regne ARCHITECTURE Behavior OF regne IS TOR N 1 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF CLock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear O lt OTHERS gt 0 ELSIF E 1 THEN O lt R END IF END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flip flop IS PORT R Clock Resetn E Q END flip flop IN STD LOGIC IN STD LOGIC OUT STD LOGIC ARCHITECTURE Behavior OF flip flop IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear 9 lt 10 Page 2 part4 vhd END ELSIF Q E E lt END IF END IF LIBRARY ieee USE ieee std_logic_1164 all END PROCESS Behavior ENTITY hex seg IS hex display PORT END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEG IN R 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN 1010 WHEN 1
29. SW7 SWO provides data to SW17 is the memory Write input 7 seg displays HEX7 displays the data input to the memory from the memory LEDGO shows the status of Write SRAM ADDR provides the external SRAM chip address input output for the RAM SRAM OE N ee USE ieee std logic 1164 all ENTITY par t4 IS SRAM UB N and HEX1 HEX6 display the memory addres HEXO show the contents read HEX5 HEX4 SRAM DO is the data and the SRAM control signals are SRAM WE N and SRAM LB N PORT KEY IN STD LOGIC VECTOR 1 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 SRAM ADDR OUT STD LOGIC VECTOR 17 DOWNTO 0 SRAM DO INOUT STD LOGIC VECTOR 15 DOWNTO 0 SRAM WE N BUFFER STD LOGIC SRAM CE N SRAM OE N OUT STD LOGIC SRAM UB N SRAM LB N OUT STD LOGIC END part4 ARCHITECTURE Behavior OF part4 IS COMPONENT flip flop PORT R IN STD LOGIC Clock Resetn E STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT BEGIN COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO
30. implements a 3 bit wide 8 to 1 multiplexer ENTITY mux_3bit_8tol IS PORT Ss M Gl G2 END mux 3bit 8tol G3 G4 G5 G6 G7 ARCHITECTURE Behavior OF mux 3bit 8tol IS SIGNAL m 0 m 1 m 2 STD LOGIC V BEGIN 8 to 1 multiplexer for bit 0 m_0 1 lt NOT S 0 AND G1 0 OR m_0 2 lt NOT S 0 AND G3 0 OR m_0 3 lt NOT S 0 AND G5 0 OR m_0 4 lt NOT S 0 AND G7 0 OR m_0 5 lt NOT S 1 AND m_0 1 O m_0 6 lt NOT S 1 AND m_0 3 O M 0 lt NOT S 2 AND m_0 5 OR 8 to 1 multiplexer for bit 1 m_1 1 lt NOT S 0 AND G1 1 OR m_1 2 lt NOT S 0 AND G3 1 OR m_1 3 lt NOT S 0 AND G5 1 OR m_1 4 lt NOT S 0 AND G7 1 OR m_1 5 lt NOT S 1 AND m_1 1 O m_1 6 lt NOT S 1 AND m_1 3 O M 1 lt NOT S 2 AND m_1 5 OR 8 to 1 multiplexer for bit 2 m_2 1 lt NOT S 0 AND G1 2 OR m 2 2 x NOT S 0 AND G3 2 OR m_2 3 lt NOT S 0 AND G5 2 OR m_2 4 lt NOT S 0 AND G7 2 OR m_2 5 lt NOT S 1 AND m_2 1 O m_2 6 lt NOT S 1 AND m_2 3 O M 2 lt NOT S 2 AND m_2 5 OR END Behavior LIBRARY ieee G8 ECTOR 1 TO 6 to drive the hex displays ECTOR 2 DOWNTO 0 ECTOR 2 DOWNTO 0 IN STD LOGIC V OUT STD LOGIC V intermediate multiplexers part6 vhd Page 3 USE ieee std logic 1164 all Converts 3 bit input code on C2 0 into 7 bit code that pro
31. red LEDs LEDG OUT STD LOGIC VECTOR 7 DOWNTO 0 green LEDs END part2 ARCHITECTURE Structure OF part2 IS SIGNAL Sel STD LOGIC SIGNAL X Y M STD LOGIC VECTOR 7 DOWNTO 0 BEGIN LEDR lt SW X lt SW 7 DOWNTO 0 Y lt SW 15 DOWNTO 8 Sel lt SW 17 M 0 lt NOT Sel AND X 0 OR Sel AND Y 0 M 1 lt NOT Sel AND X 1 OR Sel AND Y 1 M 2 lt NOT Sel AND X 2 OR Sel AND Y 2 M 3 lt NOT Sel AND X 3 OR Sel AND Y 3 M 4 lt NOT Sel AND X 4 OR Sel AND Y 4 M 5 lt NOT Sel AND X 5 OR Sel AND Y 5 M 6 lt NOT Sel AND X 6 OR Sel AND Y 6 M 7 lt NOT Sel AND X 7 OR Sel AND Y 7 LEDG 7 DOWNTO 0 lt M END Structure Page 1 part3 vhd Page 1 Implements a 3 bit wide 5 to 1 multiplexer inputs SW14 0 represent data in 5 groups U Y SW17 15 selects one group from U to Y PASO LEDR17 0 show the states of the switches LEDG2 0 displays the selected group LIBRARY ieee USE ieee std logic 1164 all Simple module that connects the SW switches to the LEDR lights ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 red LEDs LEDG OUT STD LOGIC VECTOR 2 DOWNTO 0 green LEDs END part3 ARCHITECTURE Structure OF part3 IS SIGNAL m 0 m 1 m 2 STD LOGIC VECTOR 1 TO 3 m 0 is used for 3 in
32. 1 carries for row that ANDs with B2 SIGNAL C b3 STD LOGIC VECTOR 3 DOWNTO 1 carries for row that ANDs with B3 partial products from row that ANDs with Bl SIGNAL PP1 STD LOGIC VECTOR 5 DOWNTO 2 partial products from row that ANDs with B2 SIGNAL PP2 STD LOGIC VECTOR 6 DOWNTO 3 BEGIN A lt SW 11 DOWNTO 8 B lt SW 3 DOWNTO 0 P 0 lt A 0 AND B 0 f Gay Dy Cl Sy Co bl a0 fa PORT MAP A 1 AND B 0 A 0 AND B 1 O P 1 C b1 1 bl al fa PORT MAP A 2 AND B 0 A 1 AND B 1 C b1 1 PP1 2 C b1 2 bl a2 fa PORT MAP A 3 AND B 0 A 2 AND B 1 C b1 2 PP1 3 C b1 3 bl a3 fa PORT MAP O A 3 AND B 1 C b1 3 PP1 4 PP1 5 fa ka 5 Gi 8 Go b2 a0 fa PORT MAP PP1 2 A 0 AND B 2 0 P 2 C b2 1 b2 al fa PORT MAP PP1 3 A 1 AND B 2 C_b2 1 PP2 3 C b2 2 b2 a2 fa PORT MAP PP1 4 A 2 AND B 2 C b2 2 PP2 4 C b2 3 b2 a3 fa PORT MAP PP1 5 A 3 AND B 2 C b2 3 PP2 5 PP2 6 fa a D Ci S CO b3 a0 fa PORT MAP PP2 3 A 0 AND B 3 O P 9 C LIEN b3 al fa PORT MAP PP2 4 A 1 AND B 3 C b3 1 P 4 C b3 2 b3 a2 fa PORT MAP PP2 5 A 2 AND B 3 C b3 2 P 5 C b3 3 b3 a3 fa PORT MAP PP2 6 A 3 AND B 3 C b3 3 P 6 P 7 drive the display through a 7 seg decoder digit 7 hex7seg PORT MAP 0000 HEX7 digit 6 hex7seg PORT MAP A HEX6 digit 5 hex7seg PORT MAP 0000 HEX5 digit 4 hex7
33. 1 THEN IF Resetn 0 THEN synchronous clear Q lt OTHERS gt 0 ELSIF E 1 THEN part6 vhd Page 3 p e END IF END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flip flop IS PORT R IN STD LOGIC Clock Resetn E IN STD LOGIC Q OUT STD LOGIC END flip flop ARCHITECTURE Behavior OF flip flop IS BEGIN PROCESS Clock BEGIN IF CLock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt 0 ELSIF E 1 THEN O lt R END IF END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN m 0 51 1 6 4 2 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 part6 vhd WHEN 1001 WHEN 1010 WHEN 1011 WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTH END
34. 1 HELLO 1 8 O ELLO H 1 0 1 LLO HE ae 1 1 9 LO HEL Ld E O HELL inputs SW17 15 provide the multiplexer select lines SW14 0 provide five different codes used to select characters outputs LEDR shows the states of the switches m HEX7 HEXO displays the characters LIBRARY ieee USE ieee std logic 1164 all ENTITY part6 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part6 ARCHITECTURE Structure OF part6 IS COMPONENT mux 3bit 8tol PORT S Gl G2 G3 G4 G5 G6 G7 G8 IN STD LOGIC VECTOR 2 DOWNTO 0 M OUT STD LOGIC VECTOR 2 DOWNTO 0 END COMPONENT COMPONENT char seg PORT E IN STD_LOGIC_VECTOR 2 DOWNTO 0 Display OUT STD LOGIC VECTOR O TO 6 END COMPONENT SIGNAL Ch Sel Ch1 Ch2 Ch3 Ch4 Ch5 Blank STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL H7 Ch H6 Ch H5 Ch H4 Ch STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL H3 Ch H2 Ch H1 Ch HO Ch STD LOGIC VECTOR 2 DOWNTO 0 BEGIN LEDR lt SW Ch Sel lt SW 17 DOWNTO 15 Chl lt SW 14 DOWNTO 12 Ch2 lt SW 11 DOWNTO 9 Ch3 lt SW 8 DOWNTO 6 Ch4 lt SW 5 DOWNTO 3 Ch5 lt SW 2 DOWNTO 0 Blank lt 111 used to blank a 7 seg display see module char 7seg insta
35. 3 AND B 0 OR NOT B 3 AND B 2 AND NOT B 1 H 5 lt B 1 AND B 0 OR NOT B 2 AND B 1 OR NOT B 3 AND NOT B 2 AND B 0 H 6 lt B 2 AND B 1 AND B 0 OR NOT B 3 AND NOT B 2 AND NOT B 1 END Structure part2 vhd Page 1 bcd to decimal converter LIBRARY ieee USE ieee std logic 1164 all ENTITY part2 IS PORT SW IN STD LOGIC VECTOR 3 DOWNTO 0 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 7 segs END part2 ARCHITECTURE Structure OF part2 IS COMPONENT bcd7seg PORT B IN STD LOGIC VECTOR 3 DOWNTO 0 H OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL V M STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL B STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL z STD LOGIC BEGIN V lt SW EJ gt Circuit A z lt V 3 AND V 2 OR V 3 AND V 1 Cee gases B B 2 lt V 2 AND V 1 B 1 lt V 2 AND NOT V 1 B 0 lt V 1 AND V 0 OR V 2 AND V 0 multiplexers M 3 lt NOT z AND V 3 M 2 lt NOT z AND V 2 OR z AND B 2 M 1 lt NOT z AND V 1 OR z AND B 1 M 0 lt NOT z AND V 0 OR z AND B 0 CLECU1t D Circuit D bcd7seg PORT MAP M HEXO Circuit E HEX1 lt 1 NOT Z NOT z amp 1111 display a blank or the digit 1 END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT B IN STD LOGIC VECTOR 3 DOWNTO 0
36. 4 3 Augment your VHDL code to include circuit B in Figure 1 as well as the 7 segment decoder Change the inputs and outputs of your code to use switches SW3 0 on the DE2 board to represent the binary number V and the displays HEX and HEXO to show the values of decimal digits d and do Make sure to include in your project the required pin assignments for the DE2 board 4 Recompile the project and then download the circuit into the FPGA chip 5 Test your circuit by trying all possible values of V and observing the output displays Comparator Circuit B 7 segment decoder Figure 1 Partial design of the binary to decimal conversion circuit Part HI Figure 2a shows a circuit for a full adder which has the inputs a b and c and produces the outputs s and c Parts b and c of the figure show a circuit symbol and truth table for the full adder which produces the two bit binary sum cos a b cj Figure 2d shows how four instances of this full adder entity can be used to design a circuit that adds two four bit numbers This type of circuit is usually called a ripple carry adder because of the way that the carry signals are passed from one full adder to the next Write VHDL code that implements this circuit as described below a FA b b Co Co a Full adder circuit b Full adder symbol bac es bs 43 c b 45 c b e bo 49 Cin 000 0 0 001 01 010 01 011 10 FA FA FA FA 100 01 101 10 110 10 lllj 11
37. 4 respectively The result P Ax B isto be displayed on HEX3 0 Part III Change your VHDL code to implement the 8 x 8 multiplier by using the pm mult module from the library of parameterized modules in the Quartus II system Complete the design steps above Compare the results in terms of the number of logic elements LEs needed Copyright 2006 Altera Corporation partl vhd Page 1 LIBRARY ieee USE ieee std 1 USE ieee std I logic 1164 all logic unsigned all Input two 4 bit numbers using the SW switches and display the numbers on one digit of the two 2 digit 7 seg displays Multiply and display the product on the two digits of the 4 digit 7 seg display ENTITY partl IS PORT SW IN STD LOGIC VECTOR 15 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END partl ARCHITECTURE Structure OF partl IS COMPONENT fa PORT b ci IN STD LOGIC S CO OUT STD LOGIC END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL A B STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL P STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL C bl STD LOGIC VECTOR 3 DOWNTO 1 carries for row that ANDs with B1 SIGNAL C b2 STD LOGIC VECTOR 3 DOWNTO
38. 43 0011010000000000 44 0000000001110000 45 1010001010000000 46 0010110000000000 47 0001000000000000 48 1010100110000000 49 0100100010000000 4A 0010110000000000 4B 0011111111111111 4C 0001011110000000 instruction 4D 0011000000000000 4E 0000000000101100 4F 1000000000000000 50 0000001110000000 instruction 51 0111000010000000 52 1101110000000000 53 0110110010000000 54 1101111010000000 55 0011010000000000 56 0000000001110000 57 1000001010000000 58 0011110000000000 59 0000000000000111 60 0000000000000000 61 7 111111111111 62 111111111111 63 111111111111 64 111111111111 63 amp AT111LI1L4LT EL here bet H H H H Se se Se Se Ne Ne r F r r F r F r r r E r r r r r r r F r r r F r r r F r r r r r F 66 0000000001000010 67 0000000000110000 68 0000000000010010 69 s LLITATITILITTULE GA ot TEDLIILITIITIIITI 6B 1111111181111111 6C 111111111111111 6D 111111111111111 Pp FF ja se se me me 70 0000000000000000 71 0000000000000000 END r F r r r F oo oo o A de oe oe oe de ao e oO oe oo oe oO oe oO oO oO oe oe oe oe A de de oe oe A oe oe o de de oe oe oO oO oO Skip mvi sub mvnz sub sub add mv Cont mvi st mvi st add Outer mvi ld
39. 6 END COMPONENT SIGNAL Resetn Clock Write CE STD LOGIC SIGNAL Address STD LOGIC VECTOR 4 DOWNTO 0 SIGNAL DataIn DataOut STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL Dataln reg STD LOGIC VECTOR 15 DOWNTO 0 Resetn KEY 0 Clock lt KEY 1 Write lt SW 17 R1 flip flop PORT MAP NOT Write Clock Resetn 1 SRAM WE N Address lt SW 15 DOWNTO 11 R2 regne GENERIC MAP N gt 5 PORT MAP Address Clock Resetn l SRAM_ADDR 4 DOWNTO 0 SRAM_ADDR 17 DOWNTO 5 lt 0000000000000 Dataln lt SW 7 DOWNTO 0 R3 regne GENERIC MAP N gt 8 PORT MAP Dataln Clock Resetn l Dataln reg 7 DOWNTO 0 Dataln reg 15 DOWNTO 8 lt 00000000 SRAM DO lt Dataln reg WHEN SRAM WE N 0 ELSE ZZZZZZZZZZZZZZZZ Page 1 part4 vhd hold CE N to 1 at power up R4 flip flop PORT MAP 1 Clock Resetn 1 SRAM CE N lt NOT CE SRAM OE N lt 0 SRAM UB N lt 0 SRAM LB N lt 0 DataOut lt SRAM DO 7 DOWNTO 0 display the data input digit0 hex7seg PORT MAP digitl hex7seg PORT MAP HEX2 1111111 HEX3 lt 1111111 digit4 hex7seg PORT MAP digit5 hex7seg PORT MAP digit6 hex7seg PORT MAP digit7 hex7seg PORT MAP LEDG 0 Write END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS to avoid an accidental write CBE data output and address on the 7 segs DataOut 3 DOWNTO 0
40. 6 PP1 7 C b1 7 bl a7 fa PORT MAP 0 A 7 AND B 1 C b1 7 PP1 8 PP1 9 fa a b ci S co b2 a0 fa PORT MAP PP1 2 A 0 AND B 2 0 P 2 C b2 1 b2 al fa PORT MAP PP1 3 A 1 AND B 2 C b2 1 PP2 3 C b2 2 b2 a2 fa PORT MAP PP1 4 A 2 AND B 2 C b2 2 PP2 4 C b2 3 b2 a3 fa PORT MAP PP1 5 A 3 AND B 2 C b2 3 PP2 5 C b2 4 Page 2 part2 vhd c4 Cd 0 sf LO OP 4 c4 CN O sf 10 Or CN c4 Cd 00 TO OK M A1iNM NDSR STE ERDE PF Gs Ge GN Au Ch pes o ui UE try 015 0 MINEN COMO ETE TRT MP MD SS uy t uy WC EC A0 16 SS NO XO XO LO XO LO LO ANO TM SO es 22222220 Q Q Q Q O O Q 22222220 O Q Q O Q OA Ss ee NAA l TT TT la l I II I l l I I lla l ll as Fi ES BE SG q a a qa VDOVUDVODODOA OOOOOOOnD OOOOOOOnR OOOOOOOUOn 29939292993 LVUUA lt amp d S E ug x O OV OO OU A M E EN Gee Ae es Sk Kees amp w w w lt SR O Aa Or ON CO lt at no OD lt LO XO OO 0 ri ri ORM scr O0 O3 c mn mn na ws S GN SS m m m m m
41. ADDR DOUT Done loaded into the memory on an active clock edge This type of memory unit is usually called a synchronous random access memory synchronous RAM Figure 8 also includes a 16 bit register that can be used to store data from the processor this register might be connected to a set of LEDs to allow display of data on the DE2 board To allow the processor to select either the memory unit or register when performing a write operation the circuit includes some logic gates that perform address decoding if the upper address lines are A 15 414413412 0000 then the memory module will be written at the address given on the lower address lines Figure 8 shows n lower address lines connected to the memory for this exercise a memory with 128 words is probably sufficient which implies that n 7 and the memory address port is driven by Ag Ao For addresses in which 415414413412 0001 the data written by the processor is loaded into the register whose outputs are called LEDs in Figure 8 Processor Clock Resetn Run Figure 8 Connecting the enhanced processor to a memory and output register 1 Create a new Quartus II project for the enhanced version of the processor 2 Write VHDL code for the processor and test your circuit by using functional simulation apply instructions to the DIN port and observe the internal processor signals as the instructions are executed Pay careful attention to the timing of signals between
42. C 0 Display 6 lt NOT NOT C 2 AND NOT C 1 AND NOT C 0 OR NOT C 2 AND NOT C 1 AND C 0 END Behavior Laboratory Exercise 2 Numbers and Displays This is an exercise in designing combinational circuits that can perform binary to decimal number conversion and binary coded decimal BCD addition Part I We wish to display on the 7 segment displays HEX3 to HEXO the values set by the switches SW15 0 Let the values denoted by SW15 12 SW11 8 gt SW7_4 and SW3 o be displayed on HEX3 HEX2 HEXI and HEXO respectively Your circuit should be able to display the digits from 0 to 9 and should treat the valuations 1010 to 1111 as don t cares 1 Create a new project which will be used to implement the desired circuit on the Altera DE2 board The intent of this exercise is to manually derive the logic functions needed for the 7 segment displays You should use only simple VHDL assignment statements in your code and specify each logic function as a Boolean expression 2 Write a VHDL file that provides the necessary functionality Include this file in your project and assign the pins on the FPGA to connect to the switches and 7 segment displays as indicated in the User Manual for the DE2 board The procedure for making pin assignments is described in the tutorial Quartus II Introduction using VHDL Design which is available on the DE2 System CD and in the University Program section of Altera s web s
43. CASE END PROCESS END Behavior ERS displ disp displ disp displ disp disp Lay Lay Lay Lay Lay Lay Lay 0001100 0001000 1100000 0110001 1000010 0110000 0111000 r E p F F E Page 4 part7 vhd Page 1 This code implements a pseudo dual port memory by using a multiplexer for the write and read address and using external SRAM inputs CLOCK 50 is the clock KEYO is the reset SW7 SWO provides data to write into memory SW15 SW11 provides the memory address SW17 is the memory Write input outputs 7 seg displays HEX7 HEX6 display the memory addres HEX5 HEX4 displays the data input to the memory and HEX1 HEXO show the contents read from the memory LEDGO shows the status of Write SRAM ADDR provides the external SRAM chip address SRAM DO is the data input output for the RAM and the SRAM control signals are SRAM WE N SRAM CE N SRAM OE N SRAM UB N and SRAM LB N LIBRARY ieee USE ieee std logic 1164 a11 USE ieee std logic unsigned all ENTITY part7 IS PORT CLOCK 50 IN STD LOGIC KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 SRAM ADDR OUT STD LOGIC VECTOR 17 DOWNTO 0 SRAM DO INOUT STD LOGIC
44. END IF WHEN S3 gt IF Tick 1 THEN Y D lt S4 ELSE Y D lt S3 END IF WHEN S4 gt IF Tick 1 THEN Y D lt S5 ELSE Y D lt 54 END IF WHEN S5 gt IF Tick 1 THEN Y D lt S6 ELSE Y D lt S5 END IF WHEN S6 gt IF Tick 1 THEN Y D lt S7 ELSE Y D lt S6 END IF WHEN S7 gt IF Tick 1 THEN Y D lt 88 ELSE Y D lt 57 END IF WHEN S8 gt YD lt S8 END CASE END PROCESS state table PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear y 0 lt 50 ELSE y 0 lt Y D END IE END IE END PROCESS PROCESS y 0 state outputs BEGIN pipe select lt 0 FSM char lt M o part7 vhd CASE y 0 IS WHEN SO gt FSM char lt H WHEN S1 gt FSM char lt E WHEN S2 gt FSM char lt L WHEN S3 gt FSM char lt L WHEN S4 gt FSM char lt O WHEN S5 gt FSM char lt Blank WHEN S6 gt FSM char lt Blank WHEN S7 gt FSM char lt Blank WHEN 58 gt pipe select lt 1 END CASE END PROCESS state output pipe input lt FSM char WHEN pipe select 0 ELSE pipe regne R Clock Resetn E Q UO regne PORT MAP pipe input Clock Resetn Tick pipe0 Ul regne PORT MAP pipe0 Clock Resetn Tick pipel U2 regne PORT MAP pipel Clock Resetn Tick pipe2 U3 regne PORT MAP pipe2 Clock Resetn Tick pipe3 U4 regne PORT M
45. For this part you are to manually derive an FSM circuit that implements this state diagram including the logic expressions that feed each of the state flip flops To implement the FSM use nine state flip flops called ys yo and the one hot state assignment given in Table 1 State Code Name ys8y7Y6Y5sY4Y3Y2YLYO 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 m gt Table 1 One hot codes for the FSM Reset Figure 2 A state diagram for the FSM Design and implement your circuit on the DE2 board as follows 1 Create a new Quartus II project for the FSM circuit Select as the target chip the Cyclone II EP2C35F672C6 which is the FPGA chip on the Altera DE2 board Write a VHDL file that instantiates the nine flip flops in the circuit and which specifies the logic expressions that drive the flip flop input ports Use only simple assignment statements in your VHDL code to specify the logic feeding the flip flops Note that the one hot code enables you to derive these expressions by inspection Use the toggle switch SW on the Altera DE2 board as an active low synchronous reset input for the FSM use SW as the w input and the pushbutton KEY as the clock input which is applied manually Use the green LED LEDG as the output z and assign the state flip flop outputs to the red LEDs LEDR g to LEDRo Include the VHDL file in your project and assign the pins on the
46. HEXO OUT STD LOGIC VECTOR 0 TO 6 END part2 ARCHITECTURE Behavior OF part2 IS COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn Enable STD LOGIC SIGNAL Count STD LOGIC VECTOR 3 DOWNTO 0 BEGIN Clock lt KEY 0 Resetn lt SW 0 Enable lt SW 1 PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Count lt OTHERS gt 0 ELSIF Enable 1 THEN Count lt Count 1 END IF END IF END PROCESS drive the displays digit0 hex7seg PORT MAP Count 3 DOWNTO 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN STD LOGIC VE display OUT STD LOGIC V END hex7seg E A OR 3 DOWNTO 0 CTOR 0 TO 6 el ARCHITECTURE Behavior OF hex7seg IS BEGIN Page 1 part2 4bits vhd 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN 1010 WHEN 1011 WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay l
47. IF END IF END PROCESS END Behavior Ag inst mem mif EPTH IDTH gt g ONTENT EGIN Wav oe oe 128 16 DDRESS RADIX HEX ATA RADIX BIN 00 0010000000000000 01 0000000000000001 02 0000010000000000 03 0011100000000000 04 0000000001100110 05 0010100000000000 06 0000000000000000 07 0001011100000000 08 0011000000000000 09 0010000000000000 OA 1000111010000000 OB 1010111000000000 0C 0101010010000000 OD 0101000010000000 OE 1000111010000000 OF 1010111000000000 10 0101010010000000 11 0101000010000000 12 1000111010000000 13 1010111000000000 14 0101010010000000 15 0101000010000000 16 1000111010000000 17 1010111000000000 18 0101010010000000 19 0101000010000000 IA 1000111010000000 1B 1010111000000000 1C 0101010010000000 1D 0101000010000000 1E 1000111010000000 IF 1010111000000000 20 0101010010000000 21 0101000010000000 22 1000111010000000 23 1010111000000000 24 0101010010000000 25 0101000010000000 26 1000111010000000 27 1010111000000000 28 0111100000000000 29 0011010000000000 2A 0000000001100000 2B 0011000000000000 2C 0000000000110110 2D 0111011100000000 2E 1101111000000000 2F 0101100010000000 30 0101100010000000 31 0011010000000000 32s TTI DS E 1115 33 011101
48. KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 END part3 ARCHITECTURE Behavior OF part3 IS COMPONENT hex7seg PORT X hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Write STD LOGIC SIGNAL Address Address reg INTEGER RANGE 0 to 31 SIGNAL Address STD STD LOGIC VECTOR 4 DOWNTO 0 SIGNAL Dataln DataOut STD LOGIC VECTOR 7 DOWNTO 0 declare memory array TYPE mem IS ARRAY 0 TO 31 OF STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL memory array mem BEGIN Clock lt KEY 0 Write lt SW 17 Dataln lt SW 7 DOWNTO 0 Address STD lt SW 15 DOWNTO 11 Address lt CONV INTEGER Address STD infer RAM module PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Write 1 THEN memory array Address lt Dataln END IE Address reg lt Address END IF END PROCESS DataOut lt memory array Address reg display the data input data output and address on the 7 segs digit0 hex7seg PORT MAP DataOut 3 DOWNTO 0 HEXO digitl hex7seg PORT MAP DataOut 7 DOWNTO 4 HEX1 HEX2 lt 1111111 HEX3 lt 1111111 digit4 hex7seg PORT MAP Dataln 3 DOWNTO 0 HEX4 digit5 h
49. LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B4 SIGNAL C b5 STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B5 SIGNAL C b6 STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B6 SIGNAL C b7 STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B7 partial products from row that ANDs with Bl SIGNAL PP1 STD LOGIC VECTOR 9 DOWNTO 2 partial products from row that ANDS with B2 SIGNAL PP2 STD LOGIC VECTOR 10 DOWNTO 3 partial products from row that ANDs with B3 SIGNAL PP3 STD LOGIC VECTOR 11 DOWNTO 4 partial products from row that ANDs with B4 SIGNAL PP4 STD LOGIC VECTOR 12 DOWNTO 5 partial products from row that ANDs with B5 SIGNAL PP5 STD LOGIC VECTOR 13 DOWNTO 6 partial products from row that ANDs with B6 SIGNAL PP6 STD LOGIC VECTOR 14 DOWNTO 7 BEGIN A lt SW 15 DOWNTO 8 B lt SW 7 DOWNTO 0 P 0 lt A 0 AND B 0 fa a b ci s co bl a0 fa PORT MAP A 1 AND B 0 A O AND B 1 O PET GC Dit bl al fa PORT MAP A 2 AND B 0 A 1 AND B 1 C b1 1 PP1 2 C b1 2 bl a2 fa PORT MAP A 3 AND B 0 A 2 AND B 1 C b1 2 PP1 3 C b1 3 bl a3 fa PORT MAP A 4 AND B 0 A 3 AND B 1 C b1 3 PP1 4 C b1 4 bl a4 fa PORT MAP A 5 AND B 0 A 4 AND B 1 C b1 4 PP1 5 C b1 5 bl a5 fa PORT MAP A 6 AND B 0 A 5 AND B 1 C b1 5 PP1 6 C b1 6 bl a6 fa PORT MAP A 7 AND B 0 A 6 AND B 1 C b1
50. LPM module from the Library of Parameterized Modules as we saw in Part I The other is to define the memory reguirement by using a suitable style of VHDL code from which the Ouartus II compiler can infer that a memory block should be used Ouartus II Help shows how this may be done with examples of VHDL code search in the Help for Inferred memory Perform the following steps 1 Create a new project which will be used to implement the desired circuit on the DE2 board 2 Write a VHDL file that provides the necessary functionality including the ability to load the RAM and read its contents as done in Part II 3 Assign the pins on the FPGA to connect to the switches and the 7 segment displays 4 Compile the circuit and download it into the FPGA chip 5 Test the functionality of your design by applying some inputs and observing the output Describe any differences you observe in comparison to the circuit from Part II Part IV The DE2 board includes an SRAM chip called IS61LV25616AL 10 which is a static RAM having a capacity of 256K 16 bit words The SRAM interface consists of an 18 bit address port A 170 and a 16 bit bidirectional data port I O 5 o It also has several control inputs CE OE WE UB and LB which are described in Table 1 Name Purpose CE Chip enable asserted low during all SRAM operations OE Output enable can be asserted low during only read operations or during all operations WE Write
51. Resetn lt SW 0 w lt SW 1 Three changes are needed from the version that uses the traditional one hot code 1 Change equation for YO to YO 1 2 Change logic equations for Y1 and Y5 to use NOT YO 3 Change flipflops to not have reset input Y D 0 lt 1 UO flipflop PORT MAP Y D 0 Clock Resetn Q 0 5 Y D 1 lt NOT y Q 0 OR y Q 5 OR y Q 6 OR am OR y Q 8 AND NOT w Ul flipflop PORT MAP Y D 1 Clock Resetn O 15 Y_D 2 lt y_Q 1 AND NOT w U2 flipflop PORT MAP Y D 2 Clock Resetn y Q 2 Y D 3 lt y Q 2 AND NOT w U3 flipflop PORT MAP Y D 3 Clock Resetn y Q 3 Y D 4 lt y Q 3 OR y Q 4 AND NOT w U4 flipflop PORT MAP Y D 4 Clock Resetn y Q 4 Y D 5 lt NOT y Q 0 OR y Q 1 OR y Q 2 OR OR y Q 4 AND w U5 flipflop PORT MAP Y_D 5 Clock Resetn Q 5 5 Y D 6 lt y Q 5 AND w U6 flipflop PORT MAP Y D 6 Clock Resetn y 0 6 Y D 7 lt y Q 6 AND w U7 flipflop PORT MAP Y D 7 Clock Resetn y Q 7 Y D 8 y Q 7 OR y Q 8 AND w U8 flipflop PORT B Y D 8 Clock Resetn y Q 8 z lt y Q 4 OR y Q 8 LEDR 8 DOWNTO 0 lt y Q 8 DOWNTO 0 LEDG 0 lt z END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Clock Resetn IN STD LOGIC Q OUT STD LOGIC END flipflop ARCHITECT
52. VECTOR 15 DOWNTO 0 SRAM WE N BUFFER STD LOGIC SRAM CE N SRAM OE N OUT STD LOGIC SRAM UB N SRAM LB N OUT STD LOGIC END part7 ARCHITECTURE Behavior OF part7 IS COMPONENT flip flop PORT R IN STD LOGIC Clock Resetn E STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Resetn Clock Write n sync CE CE 1 CE 2 STD LOGIC SIGNAL Write address Write address sync STD LOGIC VECTOR 4 DOWNTO 0 IGNAL Read address STD_LOGIC_VECTOR 4 DOWNTO 0 Read address cycles from addresses 0 to 31 at one second per address SIGNAL slow count STD LOGIC VECTOR 24 DOWNTO 0 SIGNAL DataIn DataIn sync DataOut STD LOGIC VECTOR 7 DOWNTO 0 BEGIN Resetn lt KEY 0 Clock lt CLOCK 50 synchronize all asynchronous inputs to the clock R1 flip flop PORT MAP NOT SW 17 Clock Resetn 1 Write n sync R2 flip flop PORT MAP Write n sync Clock Resetn 1 SRAM WE N R3 regne GENERIC MAP N gt 5 PORT MAP SW 15 DOWNTO 11 Clock Resetn 1 Write address sync R4 regne GENERIC MAP N gt 5 PORT MAP Writ
53. code from the RAM and observing the 7 segment displays Part V Add to your circuit from Part IV another module called port n that allows the processor to read the state of some switches on the board The switch values should be stored into a register and the processor should be able to read this register by using a Id instruction You will have to use address decoding and multiplexers to allow the processor to read from either the RAM or port n units according to the address used 1 Draw a circuit diagram that shows how the port n unit is incorporated into the system 2 Create a Quartus II project for your circuit write the VHDL code and write a MIF file that demonstrates use of the port n module One interesting application is to have the processor scroll a message across the 7 segment displays and use the values read from the port n module to change the speed at which the message is scrolled 3 Test your circuit both by using functional simulation and by downloading it and executing your processor code on the DE2 board Suggested Bonus Parts The following are suggested bonus parts for this exercise 1 Use the Ouartus II tools to identify the critical paths in the processor circuit Modify the processor design so thatthe circuit will operate at the highest clock freguency that you can achieve 2 Extend the instructions supported by your processor to make it more flexible Some suggested instruction types are logic instructions
54. counter QUEpuUES HEXO HEX3 hex segment displays ENTITY partl IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part1 ARCHITECTURE Behavior OF partl IS COMPONENT ToggleFF PORT T Clock Resetn IN STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn STD LOGIC SIGNAL Count Enable STD LOGIC VECTOR 15 DOWNTO 0 BEGIN 16 bit counter based on T flip flops Clock KEY 0 Resetn SW 0 Enable 0 lt SW 1 TFFO ToggleFF PORT MAP Enable 0 Clock Resetn Count 0 Enable 1 lt Count 0 AND Enable 0 TFF1 ToggleFF PORT MAP Enable 1 Clock Resetn Count 1 Enable 2 lt Count 1 AND Enable 1 FF2 ToggleFF PORT MAP Enable 2 Clock Resetn Count 2 Enable 3 lt Count 2 AND Enable 2 TFF3 ToggleFF PORT MAP Enable 3 Clock Resetn Count 3 Enable 4 lt Count 3 AND Enable 3 TFF4 ToggleFF PORT MAP Enable 4 Clock Resetn Count
55. designed circuit is given in Figure 3 It shows the value 2000 being loaded into IR from DIN at time 30 ns This pattern represents the instruction mvi RO D where the value D 5 is loaded into RO on the clock edge at 50 ns The simulation then shows the instruction mv RI RO at 90 ns add RO R1 at 110 ns and sub RO RO at 190 ns Note that the simulation output shows DIN as a 4 digit hexadecimal number and it shows the contents of IR as a 3 digit octal number Create a new Ouartus II project which will be used for implementation of the circuit on the Altera DE2 board This project should consist of a top level entity that contains the appropriate input and output ports for the Altera board Instantiate your processor in this top level entity Use switches SW 15 0 to drive the DIN input port of the processor and use switch SW to drive the Run input Also use push button KEY for Resetn and KEY for Clock Connect the processor bus wires to LEDR 5 9 and connect the Done signal to LEDR17 Add to your project the necessary pin assignments for the DE2 board Compile the circuit and download it into the FPGA chip Test the functionality of your design by toggling the switches and observing the LEDs Since the processor s clock input is controlled by a push button switch it is easy to step through the execution of instructions and observe the behavior of the circuit LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic sign
56. dual port memory by using a multiplexer for the write and read address and using M4K for the memory inputs CLOCK 50 is the clock KEYO is Resetn SW7 SWO provides data to write into memory SW15 SW11 provides the memory write address SW17 is the memory Write input outputs 7 seg displays HEX7 HEX6 display the memory addres HEX5 HEX4 displays the data input to the memory and HEX1 HEXO show the contents read from the memory LEDGO shows the status of Write LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY part6 IS PORT CLOCK 50 IN STD LOGIC KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 END part6 ARCHITECTURE Behavior OF part6 IS COMPONENT flip flop PORT R IN STD LOGIC Clock Resetn E STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT COMPONENT ramlpm PORT address IN STD LOGIC VECTOR 4 DOWNTO 0 clock IN STD LOGIC data IN STD LOGIC VECTOR 7 DOWNTO 0 wren IN STD LOGIC 1 q OUT STD LOGIC VECTOR
57. enable asserted low during a write operation UB Upperbyte asserted low to read or write the upper byte of an address LB Lower byte asserted low to read or write the lower byte of an address Table 1 SRAM control inputs The operation of the IS61LV25616AL chip is described in its data sheet which can obtained from the DE2 System CD thatis included with the DE2 board or by performing an Internet search The data sheet describes a number of modes of operation of the memory and lists many timing parameters related to its use For the purposes of this exercise a simple operating mode is to always assert set to 0 the control inputs CE OE UB and LB and then to control reading and writing of the memory by using only the WE input Simplified timing diagrams that correspond to this mode are given in Figure 4 Part a shows a read cycle which begins when a valid address appears on A17_o and the WE input is not asserted The memory places valid data on the 7 O 150 port after the address access delay t44 When the read cycle ends because of a change in the address value the output data remains valid for the output hold time tor A TOHA 17 0 a SRAM read cycle timing law E WE tsp t typ b SRAM write cycle timing Figure 4 SRAM read and write cycles Figure 4b gives the timing for a write cycle It begins when WE is set to 0 and it ends when WE is set back to 1 The address has to be vali
58. gave the RAM module the name 32x8 Complete the final steps in the Wizard MegaWizard Plug In Manager ALTSYNCRAM page 7 of 8 Do you want to specify the initial content of the memory C No leave it blank r Yes use this file for the memory content data You can use a Hexadecimal Intel format File hex or a Memory Initialization File mif Browse File name a 3 3 gt 3 data 7 0 address 4 0 wren D IV Allow In System Memory Content Editor to capture and update content FE i independently of the system clock clock The Instance ID of this RAM is 3248 Block Type MAK E 32 Word s RAM Resource Estimate TVER Documentation Cancel lt Back Next gt Finish 1 sid mod ram rom Figure 6 Configuring altsyncram for use with the In System Memory Content Editor 2 Write a VHDL file that instantiates your memory module Include in your design the ability to scroll through the memory locations as in Part V Use the same switches LEDs and 7 segment displays as you did previously 3 Before you can use the In System Memory Content Editor tool one additional setting has to be made In the Ouartus II software select Assignments gt Settings to open the window in Figure 7 and then open the item called Default Parameters under Analysis and Synthesis Settings As shown in the figure type the parameter name CYCLONEII SAFE WRITE and assign the value RESTRUCTURE This parameter allo
59. gj R_g Qa and Qb 2 Select as the target chip the Cyclone II EP2C35F672C6 and compile the code Use the Technology Viewer tool to examine the implemented circuit 3 Verify that the latch works properly for all input conditions by using functional simulation Examine the timing characteristics of the circuit by using timing simulation 4 Create a new Quartus II project which will be used for implementation of the gated D latch on the DEZ board This project should consist of a top level entity that contains the appropriate input and output ports pins for the DE2 board Instantiate your latch in this top level entity Use switch SW y to drive the D input of the latch and use SW as the Clk input Connect the Q output to LEDR9 5 Recompile your project and download the compiled circuit onto the DE2 board 6 Test the functionality of your circuit by toggling the D and Clk switches and observing the Q output Part III Figure 5 shows the circuit for a master slave D flip flop Master Slave Clock Figure 5 Circuit for a master slave D flip flop Perform the following 1 Create a new Quartus II project Generate a VHDL file that instantiates two copies of your gated D latch entity from Part II to implement the master slave flip flop 2 Include in your project the appropriate input and output ports for the Altera DE2 board Use switch SW y to drive the D input of the flip flop and use SW as the Clock input Connect the Q o
60. input use KEY for Resetn use KEY for MClock and use KEY for PClock Connect the processor bus wires to LEDR 150 and connect the Done signal to LEDR17 5 Compile the circuit and download it into the FPGA chip 6 Test the functionality of your design by toggling the switches and observing the LEDs Since the circuit s clock inputs are controlled by push button switches it is easy to step through the execution of instructions and observe the behavior of the circuit MegaWizard Plug In Manager ALTSYNCRAM page 1 of 8 Currently selected device family Cyclone Il v How will you be using the altsyncram With one read port ROM mode C With one read write port Single port mode C Wilh one read port and one write port Simple dual port mode C With two read write ports True dual port mode inst mem address 4 0 q How do you want to specify the memory size 32 Word s RAM As a number of words Block Type AUTO C As a number of bits Resource Estimate Tran Figure 5 ALTSYNCRAM configuration MegaWizard Plug In Manager ALTSYNCRAM page 7 of 8 No tb Initialize memory content data to XX on power up In simulation inst_mem E to which ports dimensions Block Type AUTO Figure 6 Specifying a memory initialization file MIF Enhanced Processor It is possible to enhance the capability of the processor so that the counter in Figure 4 is no longer needed and so that the process
61. lt 0110001 WHEN 1101 gt display lt 1000010 WHEN 1110 gt display lt 0110000 WHEN OTHERS gt display lt 0111000 END CASE END PROCESS Page 2 partl vhd Page 3 END Behavior part2 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Input two 4 bit numbers using the SW switches and display the numbers on one digit of the two 2 digit 7 seg displays Multiply and display the product on the two digits of the 4 digit 7 seg display ENTITY part2 IS PORT SW IN STD LOGIC VECTOR 15 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part2 ARCHITECTURE Structure OF part2 IS COMPONENT fa PORT a b ci IN STD LOGIC S CO OUT STD LOGIC END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL A B STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL P STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL C bl STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B1 SIGNAL C b2 STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B2 SIGNAL C b3 STD LOGIC VECTOR 7 DOWNTO 1 carries for row that ANDs with B3 SIGNAL C b4 STD
62. lt S2 lt 53 lt 54 S55 lt 6 lt S1 lt 58 lt 58 VUVUUUUUUUU A ll KKK KK KK KK PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear y 0 lt 80 ELSE y_Q lt Y D part5 vhd END END IF END PROCES IF S PROCESS y_Q State outputs BEGIN pipe select lt 0 FSM char lt ns CASE y Q IS WHEN SO gt FSM char lt H WHEN Sl gt FSM char lt E WHEN S2 gt FSM char lt L WHEN S3 gt FSM char lt L WHEN S4 gt FSM char lt O WHEN S5 gt FSM char lt Blank WHEN S6 gt FSM char lt Blank WHEN S7 gt FSM char lt Blank WHEN 58 gt pipe select lt 1 END CASE END PROCESS state output pipe input lt FSM char WHEN pipe select 0 ELSE pipe regne R Clock Resetn E Q U0 regne PORT MAP pipe input Clock Resetn pipe0 Ul regne PORT MAP pipe0 Clock Resetn pipel U2 regne PORT MAP pipel Clock Resetn pipe2 U3 regne PORT MAP pipe2 Clock Resetn pipe3 U4 regne PORT MAP pipe3 Clock Resetn pipe4 U5 regne PORT MAP pipe4 Clock Resetn pipe5 U6 regne PORT MAP pipe5 Clock Resetn pipe6 U7 regne PORT MAP pipe6 Clock Resetn pipe 7 HEXO lt pipe HEX1 pipel HEX2 lt pipe2 HEX3 pipe3 HEX4 lt pipe4 HEX5 lt piped HEX6 l
63. lt lt lt lt lt lt KG lt lt SF SINFGA OANMPINOGOR SINATRA SANQNMPINOr SANQNMPINOR Snop Sans SRR Se Glosli Skins ES AAA aa KG lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt KG lt lt lt lt lt lt lt KG lt lt lt lt lt KG lt KG lt lt lt lt lt lt lt EE ie de s SE um EAE Se AR UE ER Be eS GRE SEES RS Ue a EO A eae eS Ge do WU FE PE RR O sa On AAA Orr CY CN CC NO sr oro o aM lt h L0 XO 00 O ri lt lt LO XO OO OA 0 XO OO AAA ROR ODA n n 7 CD OO n n n na AAA Onnnnanaana 9mmmmmmmm ua s sn s s sd Cn 10 10 n 10 10 D O xo vo vo xo xo xo to to Qi Qi Qi Au Op Qu n n Qi Qi A A O Q4 Qu n n n n AA O Qu Q4 n n n pp A O Q4 n n n n n n n O Q4 Qu n n Qi Qi A ni Qi Qi Qi n On Qi Qi Qi Qi AA nm n n n n Qi n n A u n n i Qu pi ninin n n n n n n n n PP ni Qu n Qu n n S SZ e Ke ene sm ss Rss ae ae a pss Poets ee a A A ss s sa 109 un N uo 109 ddda ddddddas duddddds daddddads dddddada dddddddd x x 2 gt gt Z TARZ 2222 dada gt gt gt qe ee gt gt gt gt gt gt ge gt gt gt HEHHE E4 Ed EH E4 EH EA EH EH HHHHHHHH HHHHHHHE HHHHHHHH HHHHHHHH m m mx mx n c m t6 m m m 6 ga m n n m mn m m n n t6 m t5 5 mx 0G t6 6 t6 m m mx aa n c6 t6 m n m 6 OOOO 200000000 400000000 400000000 400000000 2
64. m m o lt lt OSPOSP MP MP MP I LO LO LO LO LO LO LO LO NO XO XO XO XO XO LO LO R OO O e rm mn mn na NANA Qi n n n n n n Qi n n n n n A Ma n n n n n n Shi Se _ s s Aa Qs A fa Q4 Qi n i n ni n ini n PP n n n n n A PP n i Qu n AA n PP n Qi n n n n Q4 Qi n in Qu n in n EEE Ev dii TES ic AEG s A e che 9 VE A e A es 8 ET ET TN PS NE ER ES SNI ANO STW SO D lt NM 10 SO ANO lt AD PD c4 Cd 0 si try VO ANO SW OO P MD CO See IR A nl ASA NR s AS x m m m m m m x lt lt lt Ow ws sf sq 10 LO LO LO LO LO WH lt XO LO LO LO LO XO LO SS 15 E Ee IPS TP lt C QU QN QN 0000000 20020200 9924222 9942222 992222 222 0 SAR ball S IIIi L4 dd d d o Ill lI lI TN I e ud Wes edes A ie rt OOOOOUOO OOOOOOCO OOOOOUOO UO DOO ODO OOOOOOO amp dec M s VES dig Je as cde eec ys ag Be es Aj SE RS O deo ORG OR AE WEE OR ag gy HA CTS lll lll ll DS c e c Oo e e e o lt sh lt h s lt sh lt sh lt LO LO LO LO LO LO LO LO NO NO O LO XO LO XO to TS TT p Eo EES AAA a ERA Bee RS O A SMS ACE A A rd mmmmmmmm mmmmmmmm mmmmmmmm mmmmmmmm mmmmmmmm mmmm CY CAC Al E C 2 AB O A AAA a EH AA A A 0208 E icy dX Ae A A A GMA ea GO 8 aaaa 2a LAU EE p Z 2 Z e uw Eu uu 222222 e a Su KG KG lt lt lt lt lt lt KG lt lt lt lt lt KG lt KG lt lt KG lt lt lt lt lt lt lt KG lt lt lt
65. ns Resetn Clock Run E DIN 0000 Done regnreg IRIQ 00 X 100 X M0 y 20 300 upcountTstepl K 00 X UT x 00 01 x 00 X 01 X 10 X 11 X 00 01 X 10 X 11 X 00 regnireg OG 0000 z regnieg 118 0005 regneg AQ o KS OS 0004 regnireg GIO 0000 Buswires 0000 2000 X 0005 401 0005 x406408 0008 x 0004 He OO 0000 2 El gt gt El El El gt Figure 3 Simulation of the processor Part II In this part you are to design the circuit depicted in Figure 4 in which a memory module and counter are connected to the processor from Part I The counter is used to read the contents of successive addresses in the memory and this data is provided to the processor as a stream of instructions To simplify the design and testing of this circuit we have used separate clock signals PClock and MClock for the processor and memory Processor Memory Counter Bus addr data Done MClock PClock Resetn Run Figure 4 Connecting the processor to a memory and counter 1 Create a new Ouartus II project which will be used to test your circuit 2 Generate a top level VHDL file that instantiates the processor memory and counter Use the Ouartus II Mega Wizard Plug In Manager tool to create the memory module from the Altera library of parameterized modules LPMs The correct LPM is found under the storage category and is called ALTSYNCRAM Follow the instructions provided by the
66. pipe3 pipe4 pipe5 pipe6 pipe STD LOGIC VECTOR O TO 6 SIGNAL var count Modulus STD LOGIC VECTOR 3 DOWNTO 0 used to implement a variable delay SIGNAL var count sync STD LOGIC SIGNAL slow count STD LOGIC VECTOR 22 DOWNTO 0 CONSTANT H STD LOGIC VECTOR 0 TO 6 1001000 CONSTANT E STD LOGIC VECTOR 0 TO 6 0110000 CONSTANT L STD LOGIC VECTOR 0 TO 6 1110001 CONSTANT O STD LOGIC VECTOR 0 TO 6 0000001 CONSTANT Blank STD LOGIC VECTOR 6 DOWNTO 0 1111111 SIGNAL KEY1 vector KEY1 sync STD LOGIC VECTOR 0 TO 0 For synchronizing KEY SIGNAL KEY2 vector KEY2 sync STD LOGIC VECTOR O TO 0 For synchronizing KEY SIGNAL Fast vector Slow vector STD LOGIC VECTOR 0 TO 0 Needed so we can use the regne function with N 1 for a simple part7 vhd Page 2 flipflop VHDL type checking BEGIN Clock lt CLOCK 50 Resetn KEY 0 KEY1 vector 0 lt NOT KEY 1 SYNCFAST1 regne GENERIC MAP N gt 1 PORT MAP KEY1 vector Clock Resetn 1 KEYI sync SYNCFAST2 regne GENERIC MAP N gt 1 PORT MAP KEY1 sync Clock Resetn 1 Fast vector Fast lt Fast vector 0 silly VHDL type checking KEY2 vector 0 lt NOT KEY 2 SYNCSLOW1 regne GENERIC MAP N gt 1 PORT MAP KEY2 vector Clock Resetn 1 KEY2 sync SYNCSLOW2 regne GENERIC M
67. the processor has the ability to perform read and write operations using memory or other devices You will add three new types of instructions to the processor as displayed in Table 3 The Id load instruction loads data into register RX from the external memory address specified in register RY The st store instruction stores the data contained in register RX into the memory address found in RY Finally the instruction mvnz move if not zero allows a mv operation to be executed only under a certain condition the condition is that the current contents of register G are not equal to 0 Operation Function performed ld Rz Ry Ra Ry st Rx Ry Ry Ra mvnz Rz Ry if G 0 Ra Ry Table 3 New instructions performed in the processor A schematic of the enhanced processor is given in Figure 7 In this figure registers RO to R6 are the same as in Figure 1 of Laboratory Exercise 9 but register R7 has been changed to a counter This counter is used to provide the addresses in the memory from which the processors instructions are read in the preceding lab exercise a counter external to the processor was used for this purpose We will refer to R7 as the processor s program counter PC because this terminology is common for real processors available in the industry When the processor is reset PC is set to address 0 At the start of each instruction in time step 0 the contents of PC are used as an address to read an instru
68. 0 display lt 1111111 Page 2 part7 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all input six bits using SW toggle switches and convert to decimal 2 digit bcd ENTITY part7 IS PORT SW IN STD LOGIC VECTOR 5 DOWNTO 0 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR O TO 6 7 segs END part7 ARCHITECTURE Behavior OF part7 IS COMPONENT bcd7seg PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL bcd h bcd 1 STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL bin6 STD LOGIC VECTOR 5 DOWNTO 0 BEGIN bin6 lt SW Check various ranges and set bcd digits Note that we work with bin6 3 DOWNTO 0 just to prevent compiler warnings about bit size truncation This is not really necessary PROCESS bin BEGIN IF bin6 001010 THEN bcd h lt 0000 bcd 1 lt bin6 3 DOWNTO 0 ELSIF bin6 010100 THEN bcd h lt 0001 bcd 1 lt bin6 3 DOWNTO 0 0110 10 00001010 11110110 add 6 LSIF bin6 011110 THEN bcd h 0010 bcd 1 lt bin6 3 DOWNTO 0 1100 20 00010100 11101100 add 12 LSIF bin6 101000 THEN bcd h lt 0011 bed 1 lt bin6 3 DOWNTO 0 0010 30 00011110 11100010 add 2 LSIF bin6 110010 THEN bcd h lt 0100 bed 1 lt
69. 00 0110001 1000010 0110000 0111000 r r p y F r F y F F Page 3 parti 4bits vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all inputs KEYO manual clock SW0 active low reset SW1 enable signal for the counter outputs HEXO hex segment display ENTITY partl IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part1 ARCHITECTURE Behavior OF partl IS COMPONENT ToggleFF PORT T Clock Resetn IN STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn STD LOGIC SIGNAL Count Enable STD LOGIC VECTOR 3 DOWNTO 0 BEGIN 4 bit counter based on T flip flops Clock lt KEY 0 Resetn lt SW 0 Enable 0 lt SW 1 TFFO ToggleFF PORT MAP Enable 0 Clock Resetn Count 0 Enable 1 lt Count 0 AND Enable 0 TFF1 ToggleFF PORT MAP Enable 1 Clock Resetn Count 1 Enable 2 lt Count 1 AND Enable 1 TFF2 ToggleFF PORT MAP Enable 2 Clock Resetn Count 2 Enable 3 lt Count 2 AND Enable 2 TFF3 ToggleFF PORT MAP Enable 3 Clock Resetn Count 3 drive the displays digit0 hex7seg POR
70. 000 WHEN J gt Count lt 1001 END CASE END PROCESS state output digit0 bcd7seg PORT MAP Count HEX0 END Behavior LIBRARY ieee part4 vhd USE ieee std logic 1164 all USE ieee std logic signed all ENTITY bcd7seg IS PORT bcd IN STD LOGIC VECTOR 3 display OUT STD LOGIC VECTOR 0 END bcd7seg ARCHITECTURE Behavior OF bcd7seg IS BEGIN 0 a NE 5 11 6 gt s Aj 12 3 PROCESS bcd BEGIN CASE bed IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN OTHERS gt display lt 1111111 END CASE END PROCESS END Behavior DOWNTO 0 TO 6 7 Page 3 part5 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all scrolls the word HELLO across the 7 seg displays An FSM inserts the display values into a pipeline that drives the 8 displays inputs KEYO is the manual clock and SWO is the reset input outputs 7 seg displays HEX7 HEXO ENTITY part5 IS PORT SW IN STD LOG
71. 0000 HEX1 lt 0000000 HEXO lt 0000000 LEDG lt 000000000 synchronize the Run input Ul flipflop PORT MAP SW 17 STD LOGIC q z z 2 1 I E O B B UFFER STD_LOGIC UT STD LOGIC VECTOR 0 TO 6 O O IN STD LOGIC VECTOR 15 DOWNTO 0 IN STD LOGIC OUT STD LOGIC VECTOR 15 DOWNTO 0 OUT STD LOGIC VECTOR 15 DOWNTO 0 OUT STD LOGIC BUFFER STD LOGIC OGIC VECTOR 6 DOWNTO 0 OGIC OGIC VECTOR 15 DOWNTO 0 OGIC 1 te LOGIC VECTOR 15 DOWNTO 0 TD LOGIC VECTOR n 1 DOWNTO 0 TD LOGIC TD LOGIC VECTOR n 1 DOWNTO 0 IN STD LOGIC UT STD LOGIC O LED_reg_cs STD_LOGIC IGNAL DIN LED_reg STD_LOGIC_VECTOR 15 DOWNTO 0 KEY 0 Clock Sync U2 flipflop PORT MAP Sync KEY 0 Clock Run proc DIN Resetn Clock Run DOUT ADDR W Done they The HEX0 HEX7 and LEDG are driven STD LOGIC VECTOR 0 DOWNTO 0 STD LOGIC VECTOR 17 DOWNTO 17 T STD LOGIC VECTOR 15 DOWNTO 0 UFFER STD LOGIC VECTOR 15 DOWNTO 0 UT STD LOGIC VECTOR 8 DOWNTO 0 Page 1 part3 vhd U3 inst mem cs lt inst mem U4 proc PORT MAP address inst mem PORT MAP DIN KEY 0 Clock Run l WHEN ADDR 15 DOWNTO 12 clock data wren q ADDR 6 DOWNTO 0 Clock DOUT 0000 Page 2 DOUT ADD
72. 000000 50 0000001110000000 instruction 51 0111000010000000 e ld oO 3 lt Inner sub oe oe 52 1101110000000000 mvnz 53 0110110010000000 sub 54 1101111010000000 mvnz 55 0011010000000000 mvi 56 0000000001110000 57 1000001010000000 ld 58 0011110000000000 mvi 59 0000000000000111 60 0000000000000000 Alpha 1 61 1111111111111111 Alpha 62 2 T TTILTLETIILITTLIL 63 ILTLITITDULILILTIL 64 1111111111111111 65 1111111111111111 66 0000000001000010 Beta 67 0000000000110000 68 0000000000010010 69 s ATLLITITETLTTITI 6A 111111111111111 6B 111111111111111 6C 111111111111111 6D 111111111111111 oO oe oe oO oO amp da Beta l E 2 Pp pi P gt sai IS Ws S oe oe oO 70 0000000000000000 71 0000000000000000 Temp Temp oO R5 RO R5 R4 R5 R7 R6 R6 R5 R5 R5 RO R5 RO R3 R2 R2 R3 R5 RO R4 RO R4 R7 R3 R7 R5 RO R7 R1 R5 Beta 1 Co R6 R4 RI RI RO R1 R5 R5 LE R3 RI R7 SW RO R7 R1 RO R1 R5 T R5 Lo nt 1111111111111111 mp D 11111111111111 mp op Page 2 Q Beta 1 N Q Beta 1 Save reg LED reg address
73. 0000000000 34 0101010010000000 oe oe oo oe oO oe o oo de oo oe oe A oo oe oe ao A de oe A oo oe o oo de oe oe A oe oe A de oe oe oe oe oo oO oe oe oe oe oe oe oO in register R2 on the red LEDs Loop mvi mv mvi mvi id st add add id st add add id st add add id st add add ld st add add ld st add add ld st add add ld st sub mvi mvnz add add sub add RO 1 Ri RO R6 tBeta R2 0 R5 R6 R4 4H address R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R5 R1 R4 R1 R3 R5 R3 R4 R6 RO R5 fAlpha l RA Skip R5 R6 R7 R4 RO R RO R R5 1111111111111111 R5 RO RS RI This code scrolls back and forth the letters dE2 across the 7 segment displays and also displays a count K 1 Q lt D LED Q Alpha 1 N Q lt Alphatl Page 1 inst mem mif 35 0000001010000000 36 0011010000000000 37 0000000001100111 38 0011000000000000 39 0000000001000011 3A 0111011100000000 3B 1101111000000000 3C 0111100010000000 3D 0111100010000000 3E 0011010000000000 3F 1111111111111111 40 0111010000000000 41 0101010010000000 42 0000001010000000
74. 001 hour 0 modulo PORT MAP SW 11 DOWNTO 8 mod hr 0 CLOCK 50 KEY 3 NOT KEY 0 E hr O hr 0 E hr 1 lt 1 WHEN hr 1 2 AND hr 0 3 OR hr 0 9 AND E hr 0 11 ELSE 0 hour 1 modulo PORT MAP SW 15 DOWNTO 12 0010 CLOCK 50 KEY 3 NOT KEY 0 E hr 1 hr 1 part2 vhd Page 2 drive the displays digit7 bcd7seg PORT MAP hr 1 HEX7 digit6 bcd7seg PORT MAP hr 0 HEX digit5 bcd7seg PORT MAP min 1 HEX5 digit4 bcd7seg PORT MAP min 0 HEX4 digit3 bcd7seg PORT MAP sec 1 HEX3 digit2 bcd7seg PORT MAP sec 0 HEX2 blank the adjacent display digiti bcd7seg PORT MAP 1111 HEX1 digit0 bcd7seg PORT MAP 1111 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY modulo IS PORT R M IN STD LOGIC VECTOR 3 DOWNTO 0 Clock Resetn L E IN STD LOGIC Q OUT STD LOGIC VECTOR 3 DOWNTO 0 END modulo ARCHITECTURE Behavior OF modulo IS SIGNAL Count STD LOGIC VECTOR 3 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Count lt 0000 ELSIF L 1 THEN Count lt R ELSIF E 1 THEN IF Count M THEN Count 0000 ELSE Count lt Count 1 END IF END IF END IF END PROCESS Q lt Count END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT bc
75. 010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN OTHERS END CASE END PROCESS END Behavior display lt 0000001 display lt 1001111 display lt 0010010 display lt 0000110 display lt 1001100 display lt 0100100 display lt 1100000 display lt 0001111 display lt 0000000 display lt 0001100 display lt 1111111 DOWNTO 0 TO 6 7 Page 2 part2 vhd LIBRARY ieee USE ieee std logic 1164 USE ieee std I Real time settable clock representing hours Load initial time by pressing KEY 3 ENTITY part2 IS PORT END part2 ARCHITECTURE C S K H valt logic unsigned all Set SW 15 DOWNTO 8 Set SW 7 DOWNTO 0 Page 1 switches to 2 digit BCD number to 2 digit number representing minutes COMPONENT modulo R M PORT Clock Resetn Q END COMPONENT COMPONENT bcd7seg PORT bcd display END COMPONENT L IN E Behavior OF part2 IS IN IN OUT LOCK 50 IN STD LOGIC W IN STD LOGIC VECTOR 15 DOWNTO 0 EY IN STD LOGIC VECTOR 3 DOWNTO 0 EX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX HEXO OUT STD LOGIC VECTOR 0 TO 6 STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC VECTOR 3 DOWNTO 0 OUT STD LOGIC VECTOR 0 TO 6
76. 011 WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior LL THEN IN STD LOGIC VECTOR 3 DOWNTO 0 OUT STD LOGIC VECTOR 0 TO 6 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 Page 3 part5 vhd This code implements a simple dual port memory inputs CLOCK 50 is the clock KEYO is Resetn write into memory SW15 SW11 provides the memory address SW17 is outputs 7 seg displays HEX7 HEX6 display the displays the data input to the memory and HEX1 using an M4K block SW7 SWO provides data to the memory Write input memory addres HEX5 HEX4 HEXO show the contents read from the memory LEDGO shows the status of Write LIBRARY ieee USE ieee std 1 USE ieee std 1 logic 1164 all logic unsigned all ENTITY part5 IS PORT CLOCK 50 IN STD LOGIC KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 END part5 ARCHITECTURE Beh
77. 10010000000 add R5 R1 P 25 0101000010000000 add R4 R1 HO 26 1000111010000000 ld R3 R5 P 27 1010111000000000 st R3 R4 HO lt P 28 0111100000000000 sub R6 RO Q lt Q K 29 0011010000000000 mvi R5 Alpha 1 2A 0000000001100000 2B 0011000000000000 mvi RA Skip 2C 0000000000110110 2D 0111011100000000 sub R5 R6 Q Alpha 1 2E 1101111000000000 mvnz R7 R4 No 2F 0101100010000000 add R6 R1 30 0101100010000000 add R6 R1 Q Alpha 1 31 0011010000000000 mvi R5 1111111111111111 32 amp 43 Lal kar pa T laz 33 0111010000000000 sub R5 RO inst mem mif 34 0101010010000000 add 35 0000001010000000 mv 36 0011010000000000 Skip mvi 37 0000000001100111 38 0011000000000000 mvi 39 0000000001000011 3A 0111011100000000 sub 3B 1101111000000000 mvnz ae 0111100010000000 sub 3D 0111100010000000 sub 3E 0011010000000000 mvi 3F TATILDA TA AL 40 0111010000000000 sub 41 0101010010000000 add 42 0000001010000000 mv 43 0011010000000000 Cont mvi 44 0000000001110000 45 1010001010000000 st 46 0010110000000000 mvi 47 0001000000000000 48 1010100110000000 st 49 0100100010000000 add 4A 0010110000000000 mvi 4B 0011111111111111 4C 0001011110000000 mv instruction 4D 0010000000000000 Outer mvi n 4E 0011000000000000 4F 1001000000
78. 2 3 PROCESS bcd BEGIN CASE bed IS WHEN 0000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN OTHERS END CASE END PROCESS END Behavior disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay 0000 1001 0010 00001 10011 01001 1100 00011 0000 00011 11111 001 010 Page 2 part5 vhd LIBRARY ieee USE ieee std 1 USE ieee std I scans the word HELLO across the 7 seg displays IS CLOCK ENTITY part5 PORT K logic 1164 all logic unsigned all 50 EY x H END part5 KEY 3 EX7 HEX6 HEX5 H EX4 HEX3 HEX2 HEX1 HEXO is resetn ARCHITECTURE Behavior OF part5 COMPONENT hello7seg PORT END COMPON SIGNAL seg 7 STD LOGIC VEC SIGNAL slow count SIGNAL digit flipper BEGIN a large counter to produce a s CLOCK 50 PROCESS BEGIN IF END IF CLOCK 50 slow count lt slow count IS I I N N KEY3 causes a reset STD LOGIC STD LOGIC VEC OR 3 DOWNTO 0 OUT STD LOGIC VECTOR 0 TO 6 char IN STD LOGIC VECTOR 2 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 ENT seg7 6 seg7 5 seg7 4 seg7 3 seg 2 seg7 1 seg7 0 OR 2 DOWNTO 0 END PRO
79. 2Y1Y0 000000000 000000011 000000101 000001001 000010001 000100001 001000001 010000001 100000001 HAr g gt Table 2 Modified one hot codes for the FSM Part II For this part you are to write another style of VHDL code for the FSM in Figure 2 In this version of the code you should not manually derive the logic expressions needed for each state flip flop Instead describe the state table for the FSM by using a VHDL CASE statement in a PROCESS block and use another PROCESS block to instantiate the state flip flops You can use a third PROCESS block or simple assignment statements to specify the output z A suggested skeleton of the VHDL code is given in Figure 3 Observe that the present and next state vectors for the FSM are defined as an enumerated type with possible values given by the symbols A to I The VHDL compiler determines how many state flip flops to use for the circuit and it automatically chooses the state assignment LIBRARY ieee USE ieee std logic 1164 all ENTITY part2 IS END part2 PORT define input and output ports E ARCHITECTURE Behavior OF part2 IS declare signals TYPE State type IS A B C D E E G H D SIGNAL y 0 Y D State type y_Q is present state y D is next state BEGIN PROCESS w y Q state table BEGIN case y_Q IS WHEN A IF w 0 THEN Y_D lt B ELSE Y_D lt F END IF other states END CASE END PROCESS state table PROCESS Clock
80. 7seg PORT MAP seg 3 HEX3 digit 2 hello7seg PORT MAP seg7 2 HEX2 digit 1 hello7seg PORT MAP seg7 1 HEX1 digit 0 hello7seg PORT MAP seg 7 0 HEX0 END Behavior three bit counter with parallel load and enable LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all part5 mod count vhd Page 2 scans the word HELLO across the 7 seg displays KEY 3 causes a reset ENTITY upcount IS PORT R IN STD LOGIC VECTOR 2 DOWNTO 0 Resetn Clock L E IN STD LOGIC Q OUT STD LOGIC VECTOR 2 DOWNTO 0 END upcount ARCHITECTURE Behavior OF upcount IS SIGNAL Count STD LOGIC VECTOR 2 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Count lt 000 ELSIF L 1 THEN Count lt R ELSIF E 1 THEN Count lt Count 1 END IF END IF END PROCESS Q lt Count END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hello7seg IS PORT char IN STD_LOGIC_VECTOR 2 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hello7seg ARCHITECTURE Behavior OF hello7seg IS BEGIN 0 c m 5 1 6 4 2 m 3 PROCESS char BEGIN CASE char IS WHEN 000 gt display lt 1001000 TE WHEN 001 gt display lt 0110000 Im WHEN 010 gt display lt
81. 800000000 Qu Qu Qu A fu Qi n Qu n Qu Qu nm Q4 Q4 Q4 Qu Qi Qu i i u Qi n Qu n n Qu fu i Q4 Q4 Qi Qi Qu Qu i Ai Qi Q4 Qu Qu Qu Qu A a lt G d G mg G d G G G G G G G G d G TV G G G G G d G G G G G G 0 hv vo 0 G G G G G G G uq Uu4 H Uu TY IH IH IH ya Hg H TY H IH H H H H H H H IH IH H H HS H Uu IH IH IH H H H 03 TY IH IH IH H H HA H VOR uc SM s Od amp O r qJ QO mn CN 0 sr 010 SO H QO mn C 00 sr 10 VO re q OO CN 00 st 10 SO VOANDO str tO CC EUM a a kt KA muntre E EET ME iF sl a a CN CN CN CN co 02 0 00 00 00 0 0 Lots PAO LO LO LO LO LO LO LO XO XO XO XO LO XO XO LO KE bI E PE 22220 1202222222 0200020000 1202222222 90000000 12022222220 drive the display through a 7 seg decoder drive the display through a 7 seg decoder em on en en m 5d RO wot f XX XX ID E E Aa E mu m ou n SS S lt lt N E v i A o O O C ere E EE HH a Za Za O OO QUO A aa AA LO K Rm A lt lt mm A da da d SS 29 HH BB H m m m c m OO Q Oo O A A A n A o o Oo oo U O oO nn nn N RR pp M x w xx x oo 0 O oO ip gS GG e jo Y H A AAA A o o o AA AAA A oo OO HO part2 vhd digit 2 hex7seg PORT MAP P 11 DOWNTO 8 HEX2 digit 1 hex7seg PORT MAP P 7 DOWNTO 4 HEX1 digit 0 hex7seg PORT MAP P 3 DOWNTO 0 HEX0 END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY fa IS PORT a b ci IN ST
82. AND OR etc shift instructions and branch instructions You may also wish to add support for logical conditions other than not zero as supported by mvnz and the like 3 Write an Assembler program for your processor It should automatically produces a MIFfile from assembler code Copyright 2006 Altera Corporation proc vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic signed all ENTITY proc IS PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC DOUT OUT STD LOGIC VECTOR 15 DOWNTO 0 ADDR OUT STD LOGIC VECTOR 15 DOWNTO 0 W OUT STD_LOGIC Done BUFFER STD_LOGIC END proc ARCHITECTURE Behavior OF proc IS COMPONENT upcount PORT Clear Clock IN STD LOGIC Q OUT STD LOGIC VECTOR 2 DOWNTO 0 END COMPONENT COMPONENT pc count PORT R IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock E L IN STD LOGIC Q OUT STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT dec3to8 PORT W IN STD LOGIC VECTOR 2 DOWNTO 0 En IN STD LOGIC Y OUT STD LOGIC VECTOR 0 TO 7 END COMPONENT COMPONENT regn GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END COMPONENT COMPONENT flipflop PORT D Resetn Clock IN STD LOGIC Q OUT STD LOGIC END COM
83. AP N gt 1 PORT MAP KEY2 sync Clock Resetn 1 Slow vector Slow lt Slow vector 0 needed for silly VHDL type checking state machine that produces a variable delay Each state will produce an output value that is used to modulo a counter value Speed 5 gives the lowest modulo value and hence the smallest delay while Speed 1 gives the largest modulo value and hence the largest delay There is a synchronization state before each Speed state so that we can wait for the slow switch pressing to end PROCESS yV 0 Fast Slow state table speed BEGIN CASE yV 0 IS WHEN Sync5 gt IF Slow 1 OR Fast 1 THEN YV D lt Sync5 wait for any depressed key to be released ELSE YV D lt Speed5 END IF WHEN Speed5 gt IF Slow 0 THEN YV D lt Speed5 fastest speed ELSE YV D lt Sync4 change to slower speed END IF WHEN Sync4 gt IF Slow 1 OR Fast 1 THEN YV D lt Sync4 wait for a depressed key to be released ELSE YV D lt Speed4 END IF WHEN Speed4 gt IF Slow 0 AND Fast 0 THEN YV D lt Speed4 keep this speed ELSIF Slow 1 THEN YV D lt Sync3 change to slower speed ELSE YV D lt Sync5 change to faster speed END IF WHEN Sync3 gt IF Slow 1 OR Fast 1 THEN YV D lt Sync3 wait for a depressed key to be released ELSE YV D lt Speed3 END IF WH
84. AP pipe3 Clock Resetn Tick pipe4 U5 regne PORT MAP pipe4 Clock Resetn Tick pipe5 U6 regne PORT MAP pipe5 Clock Resetn Tick pipe6 U7 regne PORT MAP pipe6 Clock Resetn Tick pipe HEXO lt pipe HEX1 pipel HEX2 pipe2 HEX3 pipe3 HEX4 lt pipe4 HEX5 lt piped HEX6 lt pipe6 HEX7 lt pipe END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear O lt OTHERS gt 1 ELSIF E 1 THEN O lt R END IE END IF END PROCESS END Behavior Page Laboratory Exercise 8 Memory Blocks In computer systems it is necessary to provide a substantial amount of memory If a system is implemented using FPGA technology it is possible to provide some amount of memory by using the memory resources that exist in the FPGA device If additional memory is needed it has to be implemented by connecting external memory chips to the FPGA In this exercise we will examine the general issues involved in implementing such memory A diagram of the random access memory RAM module that we will implement is shown
85. B 3 AND NOT B 2 AND NOT B 1 END Structure part5 vhd implements a two digit bcd adder S2 S1 SO SW15 8 Al A SW7 0 Bl BO Al AO is dis Bl BO is dis inputs outputs 0 played on HEX7 HEX6 played on HEX5 HEX4 LIBRARY ieee USE ieee std logic 1164 all ENTITY part5 IS PORT SW IN SI HEX7 HEX6 HEX5 HEX4 OUT S HEX3 HEX2 HEX1 HEXO OUT S END part5 ARCHITECTURE Structure OF part5 IS COMPONENT part4 PORT A B IN STD LOGIC VEC Cin IN STD LOGIC si OUT STD_LOGIC S0 OUT STD LOGIC VEC END COMPONENT COMPONENT bcd7seg PORT B H END COMPONENT IN OUT BO S SIGNAL A1 SIGNAL Cl BEGIN Al AO B1 BO AO C2 Bl S2 15 DOWNTO 12 11 DOWNTO 8 7 DOWNTO 4 3 DOWNTO 0 ETT part4 A B Cin BCD 0 part4 PORT MAP BCD 1 part4 PORT MAP S2 lt C2 drive the displays digit7 bcd7seg PORT digit6 bcd7seg PORT digit5 bcd7seg PORT digit4 bcd7seg PORT digit2 bcd7seg PORT digitl bcd7seg PORT digit0 bcd7seg PORT HEX3 1111111 END Structure LIBRARY ieee USE ieee std logic 1164 one digit BCD adder S ENTITY part4 IS PORT A B IN Cin IN Sd OUT S0 OUT END part4 STD LOGIC VEC I S2 S1 S0 is displayed on HEX2 HEX1 HEXO D LOGIC V D LOGIC VE EC E mi ala Al AO Bl BO TOR 15 DOWNTO 0 FOR 0 TO 6 D LOGIC V O
86. BEGIN PROCESS Clock Resetn BEGIN IF Resetn 0 THEN Q lt OTHERS gt 0 ELSIF Clock EVENT AND Clock 1 THEN O lt R END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex7seg IS Page 1 part5 vhd PORT hex IN STD LOGIC V display OUT STD LOGIC VECTOR 0 END hex7seg T ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 5 Jl 6 Ap 12 s 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt disp WHEN 0001 gt disp WHEN 0010 gt disp WHEN 0011 gt disp WHEN 0100 gt disp WHEN 0101 gt disp WHEN 0110 gt disp WHEN 0111 gt disp WHEN 1000 gt disp WHEN 1001 gt disp WHEN 1010 gt disp WHEN 1011 gt disp WHEN 1100 gt disp WHEN 1101 gt disp WHEN 1110 gt disp WHEN OTHERS gt disp END CASE END PROCESS END Behavior lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001 111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 ECTOR 3 DOWNTO 0 TO 6 Page 2 Laboratory Exercise 5 Counters This is an exercise in using counters Part I Consider the circuit in Figure 1 It is a 4 bit synchronous counter which uses four T type flip flops T
87. CESS 3 bit counter that uses a slow enable for selecting digit STD LOGIC VEC STD LOGIC V EVENT AND CLOCK 50 1 PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 IF KEY 3 0 THEN digit flipper lt 000 ELSIF slow count 0 THEN digit flipper lt END IF END IF END PROCESS seg 7 lt digit flipper seg 6 lt digit flipper 001 seg 5 lt digit flipper 010 seg 4 lt digit flipper 011 seg 3 lt digit flipper 100 seg 2 lt digit flipper 101 seg 1 lt digit flipper 110 seg 0 lt digit flipper 111 drive the display through a 7 seg nt te T to and 1 1 digit 7 hello7seg PORT MAP seg7 7 digit 6 hello7seg PORT MAP seg7 6 digit 5 hello7seg PORT MAP seg7 5 digit 4 hello7seg PORT MAP seg7 4 digit 3 hello7seg PORT MAP seg7 3 digit 2 hello7seg PORT MAP seg7 2 digit 1 hello7seg PORT MAP seg 7 1 digit 0 hello7seg PORT MAP seg7 0 END Behavior LIBRARY ieee 733 ve ru 11 E E E E E J Fj p FJ Ei Dd x lt x 1 J x x digit_flipper OrRPNWAOO I OR 23 DOWNTO 0 ECTOR 2 DOWNTO 0 low enable THEN THEN gts Page 1 decoder designed specifically for letters part5 vhd USE ieee std logic 1164 all ENTITY hello7seg IS PORT char IN STD_LOGIC_V display OUT STD LOGIC V
88. D Behavior inst mem mif EPTH IDTH gt g ATA 325 16 DDRESS RADIX HEX RADIX BIN ONTE EGIN 00 01 02 03 04 05 06 07 08 09 OA OB OC 0 OE 0 Wav UD YHHOQNWPYLGOMMIMURUNKOHE END NT 0010000000000000 0000000000000101 0000010000000000 0100000010000000 0110000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Page 1 Laboratory Exercise 10 An Enhanced Processor In Laboratory Exercise 9 we described a simple processor In Part I of that exercise the processor itself was designed and in Part II the processor was connected to an external counter and a memory unit This exercise describes subseguent parts of the processor design Note that the numbering of figures and tables in this exercise are continued from those in Parts I and II in the preceding lab exercise Part III In this part you will extend the capability of the processor so that the external counter is no longer needed and so that
89. D LOGIC S CO OUT STD LOGIC END fa ARCHITECTURE Structure OF fa IS SIGNAL a xor b STD LOGIC BEGIN a xor b lt a XOR b s lt a xor b XOR ci co lt NOT a xor b AND b OR a xor b AND ci END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY hex7seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 aes 5 11 se 6 me D 12 ue 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN 1010 gt display lt 0001000 WHEN 1011 gt display lt 1100000 WHEN 1100 gt display lt 0110001 WHEN 1101 gt display lt 1000010 WHEN 1110 gt display lt 0110000 WHEN OTHERS gt display lt 0111000 END CASE Page 3 part2 vhd Page 4 END PROCESS END Behavior part3 vhd LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Input two 8
90. DOUT ADDR W Done inst mem cs lt 1 WHEN ADDR 15 DOWNTO 12 0000 ELSE 0 inst mem address clock data wren q U4 inst mem PORT MAP ADDR 6 DOWNTO 0 Clock DOUT inst mem cs AND W inst mem q part5 vhd Page 2 PROCESS inst mem g SW reg inst mem cs BEGIN IF inst mem cs 1 THEN DIN lt inst mem q ELSE DIN lt SW reg END IF END PROCESS ED reg cs lt 1 WHEN ADDR 15 DOWNTO 12 0001 ELSE 0 regn R Rin Clock 0 U6 regn PORT MAP DOUT LED reg cs AND W Clock LED reg LEDR 15 DOWNTO 0 lt LED reg 15 DOWNTO 0 LEDG lt 000000000 seg7 cs lt 1 WHEN ADDR 15 DOWNTO 12 0010 ELSE 0 U5 seg7 scroll PORT MAP DOUT 6 DOWNTO 0 ADDR 2 DOWNTO 0 seg7 cs AND W KEY 0 Clock HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO regn R Rin Clock Q U7 regn PORT MAP SW 15 DOWNTO 0 1 Clock SW reg END Behavior inst mem mif Page 1 EPTH 128 IDTH 16 DDRESS RADIX HEX DATA RADIX BIN CONTENT BEGIN gt g This code scrolls back and forth the letters dE2 across the 7 segment displays and also displays a count in register R2 on the red LEDs The speed of scrolling and counting is controlled by the 16 bit value r
91. E E E Ha HAHAHA O o O Or O 0 0 0 ZZ ZZ nn Z O Z G Z O 3G O o Aa a A a y CQ s Aos Aa C 4 ZAZAZAZZZOUO Z OZ OZ K lt w lt lt Tan lt Q AO m e O HO E E Ds ADA O E O zS F O E OD OD 0 0 20 Z Za ZAR N N N N Na N N n OB Bm E ee E LUZUZUZUZZUOANZLOAZUOM d E E Oo HO Pp ORORORORAO RO RO 10 Asa ama TZHHzHHzeE 9 O O 0 OO ZO 20 Z HAHA a an an AQHA O 02020202202202 20 E Z lt Z lt Z lt Z lt lt Z lt lt Z lt lt lt O AH AH Oo Y oO iG y form OOHUNOTOOZOUOOU Q0H DE Da ES AR MEE DEE DEE DER rd TOTOvO TOO TOO TOO TO gt HEHZHZAZBZHZZAZZAZS n n n n n n n Q A A A A A d m amp d A A 3 A A a El part6 vhd Page 1 Implements a circuit that can display different 5 letter words on the eight 7 segment displays The character selected for each display is chosen by a multiplexer and these multiplexers are connected to the characters in a way that allows a word to be scrolled across the displays from right to left as the multiplexer select lines are changed through the sequence 000 001 111 000 001 etc Using the four characters H E L O where means blank the displays can scroll any 5 letter word using these letters such as HELLO as follows SW 17 16 15 Displayed characters 0 0 0 HELLO 0 0 1 HELLO 0 1 0 HELLO QO X
92. ECTOR 0 TO 6 END COMPONENT SIGNAL slow count STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL second STD LOGIC VECTOR 24 DOWNTO 0 SIGNAL sec 1 sec 0 min 1 min 0 STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL pseudo STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL start pseudo 0 STD LOGIC BEGIN regne R Clock Resetn E Q pseudo 0 lt 1 WHEN pseudo 0 ELSE 0 reg start regne PORT MAP 1 CLOCK 50 KEY 3 AND KEY 0 pseudo 0 start LEDR 0 lt start A large counter to produce a 1 sec second approx enable PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 THEN second lt second 1 END IE END PROCESS A large counter to produce a 1 msec second approx enable PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 THEN slow count lt slow count 1 END IF END PROCESS Pseudo random delay counter loads SW switches and counts down PROCESS CLOCK 50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 THEN IF KEY 3 0 OR KEY 0 0 THEN pseudo SW ELSIF second 0 THEN pseudo lt pseudo 1 END IF END IF END PROCESS part3 vhd 4 digit BCD counter that uses a slow enable PROCESS CLOCK 50 BEGIN IF CLOCK 50 IF KEY 0 sec 0 lt sec 1 lt 0000 min 0 lt 0000 min 1 lt 0000 ELSIF slow count 0 AND start 1 THEN IF sec 0
93. EN Speed3 Modulus 0011 WHEN Sync2 gt var count sync lt 0 WHEN Speed2 Modulus 0110 WHEN Syncl gt var count sync lt 0 WHEN Speedl gt Modulus lt 1100 END CASE END PROCESS state table LEDG 3 DOWNTO 0 lt Modulus A large counter to produce a PROCESS Clock BEGIN IF Clock EVENT AND Clock slow count lt slow count END IF END PROCESS 25 second approx enable called Tick Counter that provides a variable delay PROCESS BEGIN Clock part7 vhd Page 4 IF Clock EVENT AND Clock 1 THEN IF var count sync 0 THEN var count lt OTHERS gt 0 ELSIF slow count 0 THEN IF var count Modulus THEN var count lt OTHERS gt 0 ELSE var count lt var count 1 END IF END IF END IF END PROCESS Tick advances the scrolling letters when var count slow count 0 The var count sync is used to prevent scrolling when a Fast or Slow key is being held down Tick lt 1 WHEN var count 0 AND slow count 0 AND var count sync 1 ELSE 0 PROCESS y 0 Tick state table BEGIN CASE y 0 IS WHEN SO gt IF Tick 1 THEN Y D lt Sl ELSE Y D lt S0 END IF WHEN S1 gt IF Tick 1 THEN Y D lt S2 ELSE Y D lt S1 END IF WHEN S2 gt IF Tick 1 THEN Y D lt S3 ELSE Y D lt S2
94. EN Speed3 gt IF Slow 0 AND Fast 0 THEN YV D lt Speed3 keep this speed ELSIF Slow 1 THEN YV D lt Sync2 change to slower speed ELSE YV D lt Sync4 change to faster speed END IF WHEN Sync2 gt IF Slow 1 OR Fast 1 THEN YV D lt Sync2 wait for a depressed key to be released part7 vhd Page 3 ELSE YV D lt Speed2 END IF WHEN Speed2 gt IF Slow 0 AND Fast 0 THEN YV D lt Speed2 keep this speed LSIF Slow 1 THEN YV D lt Syncl change to slower speed LSE YV D lt Sync3 change to faster speed END IF WHEN Syncl gt IF Slow 1 OR Fast 1 THEN YV D lt Syncl wait for a depressed key to be released ELSE YV D lt Speedl END IF WHEN Speedl gt IF Fast 0 THEN YV D lt Speed keep this speed ELSE YV D lt Sync2 change to faster speed END IF END CASE END PROCESS state table PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear yV 0 lt Speed3 ELSE yV 0 lt YV Db END IF END IF END PROCESS PROCESS yV 0 BEGIN state outputs speed Modulus lt var count sync lt 1 CASE yV 0 IS WHEN Sync5 gt var count sync lt 0 WHEN Speed5 Modulus 0000 WHEN Sync4 gt var count sync lt 0 WHEN Speed4 Modulus 0001 WHEN Sync3 gt var count Sync lt 0 WH
95. END hello7seg ARCHITECTURE Behavior OF hello7seg IS BEGIN 0 S X 4 2 E 3 PROCESS char BEGIN CASE char IS WHEN 000 gt display lt 1001000 WHEN 001 gt display lt 0110000 WHEN 010 gt display lt 1110001 WHEN 011 gt display lt 1110001 WHEN 100 gt display lt 0000001 WHEN 101 gt display lt 1111111 WHEN 110 gt display lt 1111111 WHEN OTHERS gt display lt 1111111 END CASE END PROCESS END Behavior DOWNTO 0 TO 6 Page 2 part5 mod count vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all scans the word HELLO across the 7 seg displays KEY 3 causes a reset KEY 0 loads the proper counter values ENTITY part5 IS PORT CLOCK 50 IN STD LOGIC KEY IN STD LOGIC VECTOR 3 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part5 ARCHITECTURE Behavior OF part5 IS COMPONENT upcount PORT R IN STD LOGIC VECTOR 2 DOWNTO 0 Resetn Clock L E IN STD LOGIC Q OUT STD LOGIC VECTOR 2 DOWNTO 0 END COMPONENT COMPONENT hello7seg PORT 4 char IN STD LOGIC VECTOR 2 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL seg7 7 seg 6 seg7 5 seg7 4 seg7 3 seg7 2 seg 7 1 seg7 0 S
96. FPGA chip To perform eguivalent operations using the external SRAM chip you can use a special capability of the DE2 board called the DE2 Control Panel Chapter 3 of the DE2 User Manual shows how to use this tool The procedure involves programming the FPGA with a special circuit that communicates with the Control Panel software application which is illustrated in Figure 11 and using this setup 10 to load data into the SRAM chip Subseguently you can reprogram the FPGA with your own circuit which will then have access to the data stored in the SRAM chip reprogramming the FPGA has no effect on the external memory Experiment with this capability and ensure that the results of read and write operations to the SRAM chip can be observed both in the your circuit and in the DE2 Control Panel software DEZ DEZ Control Panel Open Help About PS2 amp 7 SEG SDRAM Random Access Address n wDATA 10000 DATA 0000 te Read Sequential Write Address 0 Length fo File Length EE GSE AN Seguential Read Address Length p Entire Sdram jt IRAM Content t Figure 11 The DE2 Control Panel software Copyright 2006 Altera Corporation 11 partl vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all LPM RAM module inputs Clock Address Write asserted to perform a write Dataln data to be written Outputs DataOut data read ENTITY partl IS PORT Clock Wr
97. FPGA to connect to the switches and the LEDs as indicated in the User Manual for the DE2 board Compile the circuit Simulate the behavior of your circuit Once you are confident that the circuit works properly as a result of your simulation download the circuit into the FPGA chip Test the functionality of your design by applying the input seguences and observing the output LEDs Make sure that the FSM properly transitions between states as displayed on the red LEDs and that it produces the correct output values on LEDG o Finally consider a modification of the one hot code given in Table 1 When an FSM is going to be im plemented in an FPGA the circuit can often be simplified if all flip flop outputs are O when the FSM is in the reset state This approach is preferable because the FPGA s flip flops usually include a clear input port which can be conveniently used to realize the reset state but the flip flops often do not include a set input port Table 2 shows a modified one hot state assignment in which the reset state A uses all Os This is accom plished by inverting the state variable yo Create a modified version of your VHDL code that implements this state assignment Hint you should need to make very few changes to the logic expressions in your circuit to implement the modified codes Compile your new circuit and test it both through simulation and by downloading it onto the DE2 board State Code Name YaY7Y6Y5Y4Y3Y
98. FPGA without using its dedicated flip flops Figure 1 depicts a gated RS latch circuit A style of VHDL code that uses logic expressions to describe this circuit is given in Figure 2 If this latch is implemented in an FPGA that has 4 input lookup tables LUTSs then only one lookup table is needed as shown in Figure 3a R Rg Oa Q Clk Qb S S_g Figure 1 A gated RS latch circuit A gated RS latch desribed the hard way LIBRARY ieee USE ieee std_logic_1164 all ENTITY part IS PORT Clk R S IN STD_LOGIC Q OUT STD LOGIC END partl ARCHITECTURE Structural OF part1 IS SIGNAL R_ g S_g Qa Ob STD LOGIC ATTRIBUTE keep boolean ATTRIBUTE keep of R_ g S_g Oa Ob SIGNAL IS true BEGIN R g lt R ANDCIk S_g lt S AND Clk Qa lt NOT R_g OR Qb Qb lt NOT S_g OR Qa Q lt Qa END Structural Figure 2 Specifying the RS latch by using logic expressions Although the latch can be correctly realized in one 4 input LUT this implementation does not allow its internal signals such as R g and S g to be observed because they are not provided as outputs from the LUT To preserve these internal signals in the implemented circuit it is necessary to include a compiler directive in the code In Fig ure 2 the directive keep is included by using a VHDL ATTRIBUTE statement it instructs the Ouartus II compiler to use separate logic elements for each of the signals R 9 S 9 04 and Qb Compiling
99. IC Done BUFFER STD LOGIC BusWires BUFFER STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT inst mem PORT address IN STD LOGIC VECTOR 4 DOWNTO 0 clock IN STD LOGIC q OUT STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT count5 PORT Resetn Clock IN STD LOGIC Q OUT STD LOGIC VECTOR 4 DOWNTO 0 END COMPONENT SIGNAL Resetn PClock MClock Run Done STD LOGIC SIGNAL DIN BusWires STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL pc STD LOGIC VECTOR 4 DOWNTO 0 BEGIN Resetn KEY 0 PClock KEY 1 MClock KEY 2 Run lt SW 17 proc DIN Resetn Clock Run Done BusWires Ul proc PORT MAP DIN Resetn PClock Run Done BusWires LEDR 15 DOWNTO 0 lt BusWires LEDR 17 lt Done se U2 inst mem PORT MAP pc MClock DIN U3 count5 PORT MAP Resetn MClock pc END Behavior LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY count5 IS PORT Resetn Clock IN STD LOGIC Q OUT STD LOGIC VECTOR 4 DOWNTO 0 END count5 ARCHITECTURE Behavior OF count5 IS SIGNAL Count STD LOGIC VECTOR 4 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Count lt 00000 part2 vhd Page 2 ELSE Count lt Count 1 END IF END IF END PROCESS Q lt Count EN
100. IC TYPE State type IS SO Sl S2 S3 S4 S5 56 S7 S8 SIGNAL y Q Y D State type SIGNAL FSM char STD LOGIC VECTOR 0 TO 6 input to pipeline regs comes from FSM char for the first 8 clock cycles and then comes from the pipeline s last stage HELLO travels in a loop SIGNAL pipe select STD LOGIC SIGNAL pipe input STD LOGIC VECTOR 0 TO 6 SIGNAL pipe0 pipel pipe2 pipe3 pipe4 pipes pipe6 pipe7 STD LOGIC VECTOR 6 DOWNTO 0 SIGNAL slow count STD LOGIC VECTOR 23 DOWNTO 0 CONSTANT H STD LOGIC VECTOR 0 TO 6 1001000 CONSTANT E STD LOGIC VECTOR O TO 6 0110000 CONSTANT L STD LOGIC VECTOR 0 TO 6 1110001 CONSTANT O STD LOGIC VECTOR 0 TO 6 0000001 CONSTANT Blank STD LOGIC VECTOR 6 DOWNTO 0 1111111 BEGIN Clock lt CLOCK 50 Resetn KEY 0 A large counter to produce a 1 second approx enable called Tick PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN slow count lt slow count 1 END IF END PROCESS Tick lt 1 WHEN slow count 0 ELSE 0 PROCESS y Q Tick state table BEGIN CASE y Q IS WHEN SO gt Tick 1 THEN Y D lt Sl LSE Y D S0 Tick 1 THEN Y D lt S2 LSE Y D lt S1 ND IF I E E WHEN Sl gt I E E I WHEN S2 gt F Tick 1 THEN Y D lt 83 Page 1 part6 vhd WHEN 54 S7
101. IC VECTOR 0 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part5 ARCHITECTURE Behavior OF part5 IS COMPONENT regne PORT R IN STD LOGIC VECTOR 6 DOWNTO 0 Clock Resetn STD LOGIC Q OUT STD LOGIC VECTOR 6 DOWNTO 0 END COMPONENT SIGNAL Clock Resetn STD LOGIC TYPE State type IS S0 S1 S2 S3 54 S5 56 S7 58 SIGNAL y Q Y D State type SIGNAL FSM char STD LOGIC VECTOR 0 TO 6 input to pipeline regs comes from FSM char for the first 8 clock cycles and then comes from the pipeline s last stage HELLO travels in a loop SIGNAL pipe select STD LOGIC SIGNAL pipe input STD LOGIC VECTOR 6 DOWNTO 0 SIGNAL pipe0 pipel pipe2 pipe3 pipe4 pipes pipe6 pipe7 STD LOGIC VECTOR 6 DOWNTO 0 CONSTANT H STD LOGIC VECTOR CONSTANT E STD LOGIC VECTOR CONSTANT L STD LOGIC VECTOR CONSTANT O STD LOGIC VECTOR CONSTANT Blank STD LOGIC VE BEGIN TO TO 0 1001000 0 0 TO 0 T 0110000 1110001 0000001 TO 6 121111117 Oy OY OY OY TO OR 0 Clock lt KEY 0 Resetn lt SW 0 PROCESS y 0 state table BEGIN CASE y Q IS WHEN SO gt HEN Sl gt HEN S2 gt HEN S3 gt HEN S4 gt HEN S5 gt HEN S6 gt HEN S7 gt HEN S8 gt END CASE END PROCESS state table lt Sl
102. IN STD LOGIC data IN STD LOGIC VECTOR 15 DOWNTO 0 wren IN STD LOGIC 1 q OUT STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT regn GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END COMPONENT COMPONENT flipflop PORT D Resetn Clock IN STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT seg7 scroll PORT Data IN STD LOGIC VECTOR 0 TO 6 Addr IN STD LOGIC VECTOR 2 DOWNTO 0 Sel Resetn Clock IN STD LOGIC HEX HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR O TO 6 END COMPONENT SIGNAL Sync Run inst mem cs LED reg cs segl cs STD LOGIC SIGNAL DIN LED reg inst mem q STD LOGIC VECTOR 15 DOWNTO 0 BEGIN synchronize the Run input Ul flipflop PORT MAP SW 17 KEY 0 Clock Sync U2 flipflop PORT MAP Sync KEY 0 Clock Run proc DIN Resetn Clock Run DOUT ADDR W Done U3 proc PORT MAP DIN KEY 0 Clock Run DOUT ADDR W Done inst mem cs lt 1 WHEN ADDR 15 DOWNTO 12 0000 ELSE 0 inst mem address clock data wren q U4 inst mem PORT MAP ADDR 6 DOWNTO 0 Clock DOUT inst mem cs AND W inst mem q part4 vhd U5 KEY 0 END Behavior ED reg cs lt 1 WHEN ADD
103. KEY and KEY switches are debounced and will produce exactly one low pulse when pressed However there is no way of knowing how long a switch may remain depressed which means that the pulse duration can be arbitrarily long A good approach for designing this circuit is to include a second FSM in your VHDL code that properly responds to the pressed keys The outputs of this FSM can change appropriately when a key is pressed and the FSM can wait for each key press to end before continuing The outputs produced by this second FSM can be used as part of the scheme for creating a variable time interval in your circuit Note that KEY 2 and KEY are asynchronous inputs to your circuit so be sure to synchronize them to the clock signal before using these signals as inputs to your finite state machine The ticker tape should operate as follows When the circuit is reset scrolling occurs at about one second intervals Pressing KEY repeatedly causes the scrolling speed to double to a maximum of four letters per second Pressing KEY repeatedly causes the scrolling speed to slow down to a minimum of one letter every four seconds Implement your circuit on the DE2 board and demonstrate that it works properly Copyright 2006 Altera Corporation partl vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all A sequence detector FSM using one hot encoding SWO is the active low synchronous reset SWl is the w input and KEYO is the clock The z out
104. LIBRARY ieee USE ieee std logic 1164 all A gated D latch described the hard way ENTITY D latch IS PORT Clk D IN STD LOGIC Q OUT STD LOGIC END D latch ARCHITECTURE Structural OF D latch IS SIGNAL R Rg S 9 Qa Ob STD LOGIC ATTRIBUTE keep boolean ATTRIBUTE keep of R Rg S g Qa Ob signal is true BEGIN R NOT D S g lt NOT D AND C Rg lt NOT R AND C Qa NOT S g AND Qb Ob lt NOT R g AND Qa LK Lk r r Q lt Qa END Structural part4 vhd LIBRARY ieee USE ieee std logic 1164 all inputs Clk manual clock D data input outputs Qa gated D latch output Ob positive edge triggered Qc negative edge triggered ENTITY part4 IS PORT Clk D IN Qa Ob Qc OUT END part4 ARCHITECTURE Behavior OF part4 BEGIN gated D latch PROCESS D Clk BEGIN IF Clk 1 THEN Oa lt D END IF END PROCESS PROCESS CIk BEGIN IF CIk EVENT AND Clk Ob lt D END IF END PROCESS PROCESS Clk BEGIN IF C1k EVENT AND Clk Oc lt D END IF END PROCESS END Behavior D flip flop output D flip flop output STD LOGIC STD LOGIC IS 1 THEN 0 THEN Page 1 part5 vhd LIBRARY ieee USE ieee std logic 1164 all
105. LOGIC VECTOR 17 DOWNTO 0 END partl ARCHITECTURE Behavior OF partl IS COMPONENT proc PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC Done BUFFER STD LOGIC BusWires BUFFER STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT SIGNAL Manual Clock Resetn Run Done STD LOGIC SIGNAL DIN BusWires STD LOGIC VECTOR 15 DOWNTO 0 BEGIN Resetn lt KEY 0 Manual Clock lt KEY 1 Note can t use name Clock because this is defined as the 50 MHz Clock coming into the FPGA from the board DIN lt SW 15 DOWNTO 0 Run lt SW 17 proc DIN Resetn Clock Run Done BusWires Ul proc PORT MAP DIN Resetn Manual Clock Run Done BusWires LEDR 15 DOWNTO 0 lt BusWires LEDR 16 lt 0 LEDR 17 lt Done END Behavior part2 vhd Page 1 Reset with KEY 0 Clock counter and memory with KEY 2 Clock each instuction into the processor with KEY 1 SW 17 is the Run input Use KEY 2 to advance the memory as needed before each processor KEY 1 clock cycle LIBRARY ieee USE ieee std logic 1164 all ENTITY part2 IS PORT KEY IN STD LOGIC VECTOR 2 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 17 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 END part2 ARCHITECTURE Behavior OF part2 IS COMPONENT proc PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOG
106. Laboratory Exercise 1 Switches Lights and Multiplexers The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices We will use the switches SW17 0 on the DE2 board as inputs to the circuit We will use light emitting diodes LEDs and 7 segment displays as output devices Part I The DE2 board provides 18 toggle switches called SW17 0 that can be used as inputs to a circuit and 18 red lights called LEDR17 0 that can be used to display output values Figure 1 shows a simple VHDL entity that uses these switches and shows their states on the LEDs Since there are 18 switches and lights it is convenient to represent them as arrays in the VHDL code as shown We have used a single assignment statement for all 18 LEDR outputs which is equivalent to the individual assignments LEDR 17 lt SW 17 LEDR 16 lt SW 16 LEDR 0 lt SW 0 The DE2 board has hardwired connections between its FPGA chip and the switches and lights To use SW 17 0 and LEDR17 0 it is necessary to include in your Quartus II project the correct pin assignments which are given in the DE2 User Manual For example the manual specifies that SW is connected to the FPGA pin N25 and LEDR is connected to pin AE23 A good way to make the required pin assignments is to import into the Quartus II software the file called DE pin assignments csv which is provided on the DE2 Sy
107. MPONENT SW Lu IN STD LOGIC VEC ID LOGIC VEC OUT STD LOGIC VECT OUT SI TOR 3 DOWNTO 0 OR 0 TO 6 drive the displays through 7 seg decoders digit3 digit2 digitl digit0 bcd7seg PORT MAP bcd7seg PORT MAP bcd7seg PORT MAP bcd7seg PORT MAP END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT B IN STD H OUT STD I END bcd7seg ARCHITECTURE Structure OF bcd7seg IS BEGIN 0 5 1 6 4 2 lt 3 B H 0 0000001 1 1001111 2 0010010 3 0000110 4 1001100 0100100 6 1100000 7 0001111 8 0000000 9 0001100 H 0 lt B 2 AND NOT B 0 OR NOT B 3 AND NOT B 2 LOGIC VECTOR LOGIC VECTOR SW 15 DOWNTO 12 AND NOT B 1 HEX3 SW 11 DOWNTO 8 HEX2 SW 7 DOWNTO 4 SW 3 DOWNTO 0 HEX1 HEXO 3 DOWNTO 0 0 TO 6 AND B 0 using the SW OR 15 DOWNTO 0 OR 15 DOWNTO 0 OR 0 TO 6 Page 1 red LEDs 7 segs partl vhd Page 2 H 1 lt B 2 AND NOT B 1 AND B 0 OR B 2 AND B 1 AND NOT B 0 H 2 lt NOT B 2 AND B 1 AND NOT B 0 H 3 lt NOT B 2 AND NOT B 1 AND B 0 OR B 2 AND NOT B 1 AND NOT B 0 OR B 2 AND B 1 AND B 0 H 4 lt NOT B 1 AND B 0 OR NOT B
108. N IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC DOUT OUT STD LOGIC VECTOR 15 DOWNTO 0 ADDR OUT STD LOGIC VECTOR 15 DOWNTO 0 W OUT STD LOGIC Done BUFFER STD LOGIC END COMPONENT COMPONENT inst mem PORT address IN STD LOGIC VECTOR 6 DOWNTO 0 clock IN SID LOGIC data IN STD LOGIC VECTOR 15 DOWNTO 0 wren IN STD LOGIC 114 q OUT STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT regn GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END COMPONENT COMPONENT flipflop PORT D Resetn Clock IN STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT seg7 scroll PORT Data IN STD LOGIC VECTOR O TO 6 Addr IN STD LOGIC VECTOR 2 DOWNTO 0 Sel Resetn Clock IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Sync Run inst mem cs LED reg cs seg 7 cs STD LOGIC SIGNAL DIN LED reg SW reg inst mem q STD LOGIC VECTOR 15 DOWNTO 0 BEGIN synchronize the Run input Ul flipflop PORT MAP SW 17 KEY 0 Clock Sync U2 flipflop PORT MAP Sync KEY 0 Clock Run proc DIN Resetn Clock Run DOUT ADDR Wy Done U3 proc PORT MAP DIN KEY 0 Clock Run
109. ND Clock 1 THEN IF Clear 1 THEN Count lt 00 ELSE Count lt Count 1 END IF END IF END PROCESS Q lt Count END Behavior Figure 2c Subcircuit entities for use in the processor LIBRARY ieee USE ieee std logic 1164 all ENTITY dec3to8 IS PORT W IN STD LOGIC VECTOR 2 DOWNTO 0 En IN STD LOGIC Y OUT STD LOGIC VECTOR 0 TO 7 END dec3to8 ARCHITECTURE Behavior OF dec3to8 IS BEGIN PROCESS W En BEGIN IF En 1 THEN CASE W IS WHEN 000 gt Y lt 10000000 WHEN 001 gt Y lt 01000000 WHEN 010 gt Y lt 00100000 WHEN 011 gt Y lt 00010000 WHEN 100 gt Y lt 00001000 WHEN 101 gt Y lt 00000100 WHEN 110 gt Y lt 00000010 WHEN 111 gt Y lt 00000001 END CASE ELSE Y lt 00000000 END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regn IS GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD_LOGIC BUFFER STD LOGIC VECTOR n 1 DOWNTO 0 END regn ARCHITECTURE Behavior OF regn IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Rin 1 THEN Q lt R END IF END IF END PROCESS END Behavior Figure 2d Subcircuit entities for use in the processor Simulation Waveforms Master Time Bar Ops Pointer D ps Interval D ps Start 40 0 ns 80 0 ns 120 0 ns 160 0 ns 200 0 ns 240 0
110. ND V 1 B 1 lt V 2 AND NOT V 1 B 0 lt V 1 AND V 0 OR V 2 AND V 0 multiplexers M 3 lt NOT z AND V 3 M 2 lt NOT z AND V 2 OR z AND B 2 M 1 lt NOT z AND V 1 OR z AND B 1 M 0 lt NOT z AND V 0 OR z AND B 0 END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd7seg IS PORT B IN STD LOGIC VECTOR 3 DOWNTO 0 H OUT STD LOGIC VECTOR 0 TO 6 END bcd7seg ARCHITECTURE Structure OF bcd7seg IS BEGIN w hb w N HS ae a ETT a9 IG PO RD Fa 1 O1 6 END Str 0000001 1001111 0010010 00001 Z O lt NOT lt I ucture AND NOT AND NOT AND NOT B 1 T B 2 T B 2 NOT NOT B 1 AND AND B 0 B B 0 B 2 B 1 AND NOT AND B 1 AND NOT B AND B 0 AND OR 1 AND B 2 AND NOT B 2 AND B 1 B AND I NOT B 1 0 OR B 0 B 0 OR OR B 2 B 3 AND B 3 AND B 0 AND B 1 B 0 OR OR AND NOT 1 AND I B 2 AND NOT B 1 Page 3 part6 vhd implements a two digit bcd adder S2 S1 SO Al AO Bl BO inputs SW15 8 Al AO SW7 0 B1 BO outputs Al A0 is displayed on HEX7 HEX6 Bl BO is displ LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY part6 IS
111. NTO 4 HEX1 digit0 hex7seg PORT MAP Count 3 DOWNTO 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all T Flap flop ENTITY ToggleFF IS PORT T Clock Resetn IN STD LOGIC Q OUT STD LOGIC END ToggleFF ARCHITECTURE Behavior OF ToggleFF IS SIGNAL T out STD LOGIC BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN T out lt 0 ELSIF T 1 THEN T out lt NOT T out END IF END IF END PROCESS Q lt T out END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex7seg IS PORT X hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 im 5 1 6 E 4 2 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 partl vhd WHEN 0101 WHEN 0110 WHEN 011 T WHEN 1000 WHEN 1001 WHEN 1010 WHEN TOLL WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay 0100100 1100000 0001111 0000000 0001100 0001000 11000
112. O 1 BEGIN A lt SW 7 DOWNTO 4 B lt SW 3 DOWNTO 0 bit0 fa PORT MAP bitl fa PORT MAP bit2 fa PORT MAP bit3 fa PORT MAP r Dose tJ WNHO 0 1 2 3 r s Display the inputs LEDR lt SW LEDG lt C 4 amp S END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY fa IS PORT a b ci IN STD LOGIC Sp C OUT STD LOGIC END fa ARCHITECTURE Structure OF fa IS SIGNAL a xor b STD LOGIC BEGIN a xor b lt a XOR b s lt a xor b XOR ci co lt NOT a xor b AND b OR a xor b AND ci END Structure Page 1 part4 vhd Page 1 one digit BCD adder S1 SO A B Cin inputs SW7 4 A SW3 0 B outputs A is displayed on HEX6 B is displayed on HEX4 S1 S0 is displayed on HEX1 HEX LIBRARY ieee USE ieee std logic 1164 all ENTITY part4 IS PORT SW IN STD LOGIC VECTOR 8 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 8 DOWNTO 0 red LEDs LEDG OUT STD LOGIC VECTOR 8 DOWNTO 0 red LEDs HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 7 segs HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 7 segs END part4 ARCHITECTURE Structure OF part4 IS COMPONENT fa PORT a b ci IN STD LOGIC S CO OUT STD LOGIC END COMPONENT COMPONENT bcd decim
113. OT V 1 B 0 lt V 1 AND V 0 OR V 2 AND V 0 multiplexers M 3 lt NOT z AND V 3 M 2 lt NOT z AND V 2 OR z AND B 2 M 1 lt NOT z AND V 1 OR z AND B 1 M 0 lt NOT z AND V 0 OR z AND B 0 END Structure LIBRARY ieee 1111 7 segs 19 Sl should be a 1 when Page 2 display blank or 1 part4 vhd Page 3 USE ieee std logic 1164 all ENTITY bcd7seg IS PORT B IN STD LOGIC VECTOR 3 DOWNTO 0 H OUT STD LOGIC VECTOR 0 TO 6 END bcd7seg ARCHITECTURE Structure OF bcd7seg IS BEGIN 0 5 11 64 gt 4 2 se 3 B H 0 0000001 L 1001111 2 0010010 3 0000110 4 1001100 5 0100100 6 1100000 0001111 8 0000000 9 0001100 H 0 lt B 2 AND NOT B 0 OR NOT B 3 AND NOT B 2 AND NOT B 1 AND B 0 H 1 lt B 2 AND NOT B 1 AND B 0 OR B 2 AND B 1 AND NOT B 0 H 2 lt NOT B 2 AND B 1 AND NOT B 0 H 3 lt NOT B 2 AND NOT B 1 AND B 0 OR B 2 AND NOT B 1 AND NOT B 0 OR B 2 AND B 1 AND B 0 H 4 lt NOT B 1 AND B 0 OR NOT B 3 AND B 0 OR NOT B 3 AND B 2 AND NOT B 1 H 5 lt B 1 AND B 0 OR NOT B 2 AND B 1 OR NOT B 3 AND NOT B 2 AND B 0 H 6 lt B 2 AND B 1 AND B 0 OR NOT
114. PONENT SIGNAL Rin Rout STD LOGIC VECTOR O TO 7 SIGNAL BusWires Sum STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL Clear IRin ADDRin DINout DOUTin Ain Gin Gout AddSub STD LOGIC SIGNAL Tstep Q STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL I STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL Xreg Yreg STD LOGIC VECTOR 0 TO 7 SIGNAL RO R1 R2 R3 R4 R5 R6 R7 A G STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL IR STD LOGIC VECTOR 1 TO 9 SIGNAL Sel STD LOGIC VECTOR 1 to 10 bus selector SIGNAL pc inc WD Z Z D STD LOGIC BEGIN Clear lt NOT Resetn OR Done OR NOT Run AND NOT Tstep Q 1 AND NOT Tstep Q 0 Tstep upcount PORT MAP Clear Clock Tstep 0 I lt IR 1 TO 3 decX dec3to8 PORT MAP IR 4 TO 6 1 Xreg decY dec3to8 PORT MAP IR 7 TO 9 1 Yreg Instruction Table pue 000 mv Rx Ry Rx Ry 001 mvi Rx D Rx lt D gt 010 add Rx Ry Rx lt Rx Ry 011 sub Rx Ry Rx lt Rx Ry R7 100 ld Rx Ry RE lt Ry 101 SE Rx Ry gt By lt Rx 110 mvnz Rx Ry 2 ir le 1 Rx lt Ry OPCODE format III XXX YYY UUUUUUU where III instruction XXX Rx YYY Ry and U unused bit For mvi a second word of data is read in the following clock cycle is the program counter controlsignals PROCESS Tstep 0 I Xreg Yreg Z Run BEGIN Done lt 0 Ain lt 0 Gin lt 0 Gout lt 0 AddSub lt 0 IRin lt 0 DINout lt 0 DOUTin lt 0 ADD
115. R AND C 1 AND C 0 T NOT C 2 AND NOT C 1 AND NOT C AND NOT C 1 AND C 0 OR AND C 1 AND NOT C 0 OR NOT C 2 C NOT C 2 AND NOT C 1 AND NOT C AND NOT C 1 AND C 0 OR AND C 1 AND NOT C 0 OR NOT C 2 T NOT C 2 AND NOT C 1 AND NOT C AND NOT C 1 AND C 0 The characters are toggle switches red LEDs 7 seg display inverted OR 0 OR 0 OR OR 0 OR AND C 1 AND C 0 0 OR AND C 1 AND C 0 0 OR Page 1 part5 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all Implements a circuit that can display different 5 letter words on five 7 segment displays The character selected for each display is chosen by a multiplexer and these multiplexers are connected to the characters in a way that allows a word to be rotated across the displays from right to left as the multiplexer select lines are changed through the sequence 000 001 010 011 100 000 etc Using the four characters H E L O the displays can scroll any 5 letter word using these letters such as HELLO as follows SW 17 16 15 Displayed characters Q D O HELLO P 0 0 1 ELLOH 0 1 0 LLOHE gt 0 1 1 LOHEL 1 0 0 OHELL inputs SW17 15 provide the multiplexer select lines SW14 0 provide five 3 bit codes used to select characters outputs LEDR shows the states of the switches HEX4 HEXO di
116. R W Done ELSE 0 inst mem cs AND W DIN ED reg cs lt 1 WHEN ADDR 15 DOWNTO 12 0001 ELSE 0 Fegn R Rin Clock 0 U6 regn PORT MAP DOUT LED reg cs AND W Clock LED reg LEDR 15 DOWNTO 0 LED reg 15 DOWNTO 0 END Behavior flipflop vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY flipflop IS PORT D Resetn Clock IN STD LOGIC Q OUT STD LOGIC END flipflop ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Q lt 0 ELSE Q lt D END IF END IF END PROCESS END Behavior inst mem mif EPTH 128 IDTH 16 DDRESS RADIX HEX ATA RADIX BIN ONTENT EGIN gt g Wav 04 0010110000000000 05 0001000000000000 06 1010100110000000 07 0100100010000000 08 0010110000000000 Q9 amp ILIITIITTITITTT1 OA 0001011110000000 instruction OB 0011000000000000 OC 0000000000010100 OD 0000001110000000 instruction 12 0011110000000000 13 0000000000000100 END OE 0111000010000000 OF 1101110000000000 10 0110110010000000 11 1101111010000000 This code displays a count 00 0010010000000000 01 0000000000000001 02 0010100000000000 03 0000000000000000 oe oe oo oe oe oO oO oe oe oO in register Loop Outer Tn
117. R 3 DOWNTO 0 STD LOGIC VECTOR 0 TO 6 p olg SO TD LOGIC F Sis S0 A0 BO Al Bl Yi tu CL CL C2 through A1 AO B1 BO EX7 EX6 EX5 EX4 000 amp S2 S1 HEX1 SO HEXO MAP gt gt rm turn off HEX3 all 1 50 A B Cin STD LOGIC VEC STD LOGIC STD LOGIC STD LOGIC V OR 3 El STD_LOGIC_V SO S1 7 seg decoders HEX2 DOWNTO 0 EC CTOR 3 DOWNTO 0 OR 0 TO 6 OR 3 DOWNTO 0 OR 3 DOWNTO 0 ECTOR 3 DOWNTO 0 qJesegs 7 segs Page 1 part5 vhd ARCHITECTURE Structure OF part4 IS COMPONENT fa PORT b co ci IN STD LOGIC OUT STD LOGIC a S END COMPONENT COMPONENT bcd decimal PORT V IN STD z BUFFER STD LOGIC M OUT STD LOGIC VEC END COMPONENT OR 3 DOWNTO 0 LOGIC VECTOR 3 DOWNTO 0 7 segs SIGNAL C STD LOGIC VECTOR 4 DOWNTO 1 SIGNAL S S0 M STD LOGIC VECTOR 3 DOWNTO 0 modified SO for sums gt 15 SIGNAL S1 M STD LOGIC used because S1 has to be modified for sums 15 BEGIN bit0 fa PORT MAP A 0 B 0 Cin S 0 C 1 bitl fa PORT MAP A 1 B 1 C 1 S 1 C 2 bit2 fa PORT MAP A 2 B 2 C 2 S 2 C 3 bit3 fa PORT MAP A 3 B 3 C 3 S 3 C 4 convert the sum to BCD BCD S bcd decim
118. RE Behavior OF bcd7seg IS BEGIN 0 5 11 6 e ap 12 e 3 PROCESS bcd BEGIN CASE bed IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN OTHERS gt display lt 1111111 END CASE END PROCESS END Behavior DOWNTO 0 TO 6 Page 3 Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines Part I We wish to implement a finite state machine FSM that recognizes two specific sequences of applied input sym bols namely four consecutive Is or four consecutive Os There is an input w and an output z Whenever w 1 or w 0 for four consecutive clock pulses the value of z has to be 1 otherwise z 0 Overlapping sequences are allowed so that if w 1 for five consecutive clock pulses the output z will be equal to I after the fourth and fifth pulses Figure 1 illustrates the required relationship between w and z Clock Figure 1 Required timing for the output z A state diagram for this FSM is shown in Figure 2
119. RT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END regn ARCHITECTURE Behavior OF regn IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Rin 1 THEN Page 5 proc vhd Page 6 Q lt R END IF END IF END PROCESS END Behavior td part3 vhd Reset with KEY 0 SW 17 is Run The DOUT ADDR W and Done outputs are just for simulation aren t connected to any DE2 resources to constant values because letting them float causes some of the LEDs to flash on and off for this cxrcuxt LIBRARY ieee USE ieee std logic 1164 all ENTITY part3 IS PORT KEY SW Clock LEDR DOUT ADDR W Done HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO LEDG END part3 ARCHITECTURE Behavior OF part3 IS COMPONENT proc PORT DIN Resetn Clock Run DOUT ADDR W Done END COMPONENT COMPONENT inst mem PORT address IN STD L clock IN STD L data IN STD TE wren IN STD L q OUT STD END COMPONENT COMPONENT regn GENERIC n INTEGER 16 PORT R s IN S Rin Clock IN S Q OUT S END COMPONENT COMPONENT flipflop PORT D Resetn Clock Q END COMPONENT SIGNAL Sync Run inst mem cs S ili N HEX7 lt 0000000 HEX6 lt 0000000 HEX5 lt 0000000 HEX4 lt 0000000 HEX3 lt 0000000 HEX2 lt 000
120. RY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY part IS PORT KEY IN STD LOGIC VECTOR 2 DOWNTO 0 CLOCK 50 IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 3 DOWNTO 0 END part7 ARCHITECTURE Behavior OF part7 IS COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT SIGNAL Clock Resetn Tick STD LOGIC SIGNAL Fast Slow STD LOGIC Variable tick interval controls Names of states for changing a counter value for implementing a variable tick delay TYPE Var Delay State type IS Sync3 Speed3 Sync4 Speed4 Sync5 Speed5 Syncl Speedl Sync2 Speed2 SIGNAL yV Q YV D Var Delay State Type This is the state machine that it used to implement a variable tick interval Names of states for the pipeline control machine TYPE State type IS S0 S1 S2 S3 54 S5 56 S7 S8 SIGNAL y Q YD State type SIGNAL FSM char STD LOGIC VECTOR 0 TO 6 input to pipeline regs comes from FSM char for the first 8 clock cycles and then comes from the pipeline s last stage HELLO travels in a loop SIGNAL pipe select STD LOGIC SIGNAL pipe input STD LOGIC VECTOR 0 TO 6 SIGNAL pipe0 pipel pipe2
121. Rin lt 0 WD lt 0 Rin lt 00000000 Rout lt 00000000 pc inc lt 0 CASE Tstep 0 IS WHEN 000 gt fetch the instruction Rout lt 00000001 R7 is program counter pc ADDRin lt 1 pc inc lt Run to increment pc WHEN 001 gt wait cycle for synchronous memory in case the instruction turns out to be mvi read memory Rout lt 00000001 R7 is program counter pc ADDRin lt 1 WHEN 010 gt store DIN in IR IRin lt 1 WHEN 011 gt define signals in T3 CASE I IS WHEN 000 gt mv Rx Ry Rout lt Yreg Rin lt Xreg Done lt 1 WHEN 001 gt mvi Rx D data is available now on DIN DINout lt 1 Rin lt Xreg pc inc lt 1 Done lt 1 WHEN 010 gt add Rout lt Xreg Ain lt 1 WHEN 011 gt sub Rout lt Xreg Ain lt 1 WHEN 100 gt 1d Rx Ry Rout lt Yreg ADDRin lt 1 WHEN 101 gt st Ry Rx Rout lt Yreg ADDRin lt 1 WHEN OTHERS gt mvnz Rx Ry IF Z 0 THEN Rout lt Yreg Rin lt Xreg ELSE Rout lt 00000000 Rin lt 00000000 END IF Done lt 1 END CASE WHEN 100 gt define signals T4 CASE I IS WHEN 010 gt add Rout lt Yreg Gin lt 1 WHEN 011 gt sub Page 2 proc vhd Rout lt Yreg AddSub lt 1 Gin lt 1
122. T MAP Count 3 DOWNTO 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all E Flip flop ENTITY ToggleFF IS PORT d T Clock Resetn IN STD LOGIC Q OUT STD LOGIC END ToggleFF ARCHITECTURE Behavior OF ToggleFF IS SIGNAL T out STD LOGIC BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN T out lt 0 ELSIF T 1 THEN T out NOT T out Er partl 4bits vhd END IF END IF END PROCESS Q lt T out END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex7seg IS PORT hex IN STD LOGIC VECTOR 3 display OUT STD LOGIC VECTOR 0 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 5 11 ES 6 c A4 12 ae 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN 1010 gt display lt 0001000 WHEN 1011 gt display lt 1100000 WHEN 1100 gt display lt 0110001 WHEN 1101 gt d
123. TD LOGIC VECTOR 2 DOWNTO 0 SIGNAL slow count STD LOGIC VECTOR 23 DOWNTO 0 SIGNAL Enable STD LOGIC BEGIN a large counter to produce a slow enable PROCESS CLOCK_50 BEGIN IF CLOCK 50 EVENT AND CLOCK 50 1 THEN slow count lt slow count 1 END IE END PROCESS Enable lt 1 WHEN slow count 0 ELSE 0 upcount R Resetn Clock L E 0 up7 upcount PORT MAP 000 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 7 up6 upcount PORT MAP 001 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 6 up5 upcount PORT MAP 010 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 5 up4 upcount PORT MAP 011 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 4 up3 upcount PORT MAP 100 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 3 up2 upcount PORT MAP 101 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 2 upl upcount PORT MAP 110 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 1 up0 upcount PORT MAP 111 KEY 3 CLOCK 50 NOT KEY 0 Enable seg7 0 drive the display through a 7 seg decoder designed specifically for letters Ut re et ro and digit 7 hello7seg PORT MAP seg7 7 HEX7 digit 6 hello7seg PORT MAP seg 7 6 HEX digit 5 hello7seg PORT MAP seg7 5 HEX5 digit 4 hello7seg PORT MAP seg7 4 HEX4 digit 3 hello
124. URE BEGIN Behavior OF flipflop IS partlb vhd Page 2 PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt 0 ELSE Q lt D END IE END IE END PROCESS END Behavior part2 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all A sequence detector FSM SWO is the active low synchronous reset SWl is the w input and KEYO is the clock The z output appears on LEDGO and the state is indicated on LEDR8 0 ENTITY part2 IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 8 DOWNTO 0 END part2 ARCHITECTURE Behavior OF part2 IS SIGNAL Clock Resetn w z STD LOGIC TYPE State type IS A B C D E F G H I SIGNAL y 0 Y D State type BEGIN Clock KEY 0 Resetn SW 0 w lt SW 1 PROCESS w y 0 state table BEGIN CASE y Q IS WHEN A gt IF w 0 THEN Y D lt B LSE YD lt F END IF WHEN B gt IF w 0 THEN Y D lt C ELSE Y D lt E END IF WHEN C gt IF w 0 THEN Y D lt D ELSE Y D lt F END IE WHEN D gt IF w 0 THEN Y D lt E ELSE Y D lt F END IF WHEN E gt IF w 0 THEN Y D lt E ELSE Y D lt F END IF WHEN F gt IF w
125. UT STD LOGIC VECTOR 0 TO 7 Hp zx END dec3to8 ARCHITECTURE Behavior OF dec3to8 IS BEGIN PROCESS W En BEGIN IF En 1 THEN CASE W IS WHEN 000 gt Y lt 10000000 WHEN 001 gt Y lt 01000000 WHEN O10 gt Y lt 00100000 WHEN 011 gt Y lt 00010000 WHEN 100 gt Y lt 00001000 WHEN 101 gt Y lt 00000100 WHEN 110 gt Y lt 00000010 WHEN 111 gt Y lt 00000001 END CASE ELSE Y lt 00000000 END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regn IS GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC Q BUFFER STD LOGIC VECTOR n 1 DOWNTO 0 END regn ARCHITECTURE Behavior OF regn IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Rin 1 THEN Q lt R END IF END IF END PROCESS END Behavior partl vhd Page 1 KEY 0 is the reset input and KEY 1 is the clock SW15 0 are the instructions and SW 17 is the Run input The processor bus appears on LEDR15 0 and Done appears on LEDR17 This code instantiates a 32 x 8 memory n the Cyclone II FPGA on the DE2 board LIBRARY ieee USE ieee std logic 1164 all ENTITY partl IS PORT KEY IN STD LOGIC VECTOR 1 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD
126. WNTO 0 SIGNAL I STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL Xreg Yreg STD LOGIC VECTOR 0 TO 7 SIGNAL RO R1 R2 R3 RA R5 R6 R7 A G STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL IR STD LOGIC VECTOR 1 TO 9 SIGNAL Sel STD LOGIC VECTOR 1 to 10 bus selector BEGIN High lt 1 Clear lt NOT Resetn OR Done OR NOT Run AND NOT Tstep Q 1 AND NOT Tstep 0 0 Tstep upcount PORT MAP Clear Clock Tstep 0 I lt IR 1 TO 3 decX dec3to8 PORT MAP IR 4 TO 6 High Xreg decY dec3to8 PORT MAP IR 7 TO 9 High Yreg Instruction Table 000 mv 001 mvi 010 add 011 Sub Rx Ry a Rx lt Ry Rx D s Rx lt D Rx Ry Rt lt RE RY Rx Ry Rx lt Rx Ry OPCODE format III XXX YYY where III instruction XXX Rx and YYY Ry For mvi a second word of data is loaded from DIN controlsignals BEGIN Done lt 0 IRin lt 0 CASE Tstep 0 WHEN 00 IRin lt PROCESS Tstep O I Xreg Yreg Ain lt 0 Gin lt 0 Gout lt 0 AddSub lt 0 DINout lt 0 Rin lt 00000000 Rout lt 00000000 TS gt store DIN in IR as long as Tstep 0 0 VS as proc vhd WHEN 01 gt define signals in time step T1 CASE I IS WHEN 000 gt mv Rx Ry Rout lt Yreg Rin lt Xreg Done lt 1 WHEN 001 gt mvi Rx D data is required to be on DIN DINout lt 1 Rin lt Xreg Don
127. Wires ELSE Sum lt A BusWires END IF END PROCESS reg G regn PORT MAP Sum Gin Clock G Z D lt 1 WHEN G 0 ELSE 0 reg Z flipflop PORT MAP Z D Resetn Clock Z Page 3 IR proc vhd define the internal processor bus Sel lt Rout amp Gout amp DINout busmux PROCESS Sel RO R1 R2 R3 R4 R5 R6 R7 Gp DIN BEGIN IF Sel 1000000000 THEN BusWires lt RO ELSIF Sel 0100000000 THEN BusWires lt R1 ELSIF Sel 0010000000 THEN BusWires lt R2 LSIF Sel 0001000000 THEN BusWires lt R3 LSIF Sel 0000100000 THEN BusWires lt R4 LSIF Sel 0000010000 THEN BusWires lt R5 LSIF Sel 0000001000 THEN BusWires lt R6 LSIF Sel 0000000100 THEN BusWires lt R7 ELSIF Sel 0000000010 THEN BusWires lt G LSE BusWires lt DIN END IF END PROCESS END Behavior LIBRARY ieee USE ieee std 1 USE ieee std 1 logic 1164 all logic signed all ENTITY upcount IS PORT C Q END upcount lear Clock IN STD LOGIC OUT STD LOGIC VECTOR 2 DOWNTO 0 ARCHITECTURE Behavior OF upcount IS SIGNAL Count STD LOGIC VECTOR 2 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Clear 1 THEN Count lt 000 ELSE Count lt Count 1 END IF END IF END PROCESS Q lt Count END Behavior LIBRARY ieee USE iee
128. _OE_N SRAM_UB_N SRAM_LB_N DataOut lt display digit0 he digitl he digit2 digit3 he digit4 he digit5 he digit6 he digit7 he LEDG 0 lt END Behavior LIBRARY ieee USE ieee std 1 ENTITY regne GENERIC PORT R C NOT CE lt Ot lt 0 lt vgs SRAM DQ 7 DOWNTO 0 the data input data output and address on the 7 segs x7seg PORT MAP DataOut 3 DOWNTO 0 HEXO x7seg PORT MAP DataOut 7 DOWNTO 4 HEX1 hex7seg PORT MAP Read address 3 DOWNTO 0 x7seg PORT MAP 000 amp Read address 4 x7seg PORT MAP Dataln 3 DOWNTO 0 HEX4 x seg PORT MAP Dataln 7 DOWNTO 4 HEX5 x7seg PORT MAP Write Address 3 DOWNTO 0 x7seg PORT MAP 000 amp Write Address 4 SRAM WE N logic 1164 all IS N integer 7 IN STD LOGIC VECTOR N 1 DOWNTO 0 IN STD LOGIC lock Resetn part7 vhd Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear O lt OTHERS gt 0 ELSIF E 1 THEN O lt R END IF END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flip flop IS PORT R IN STD LOGIC Clock Resetn E IN STD LOGIC Q OUT STD LOGIC END flip flop
129. al PORT V IN STD LOGIC VECTOR 3 DOWNTO 0 Zz BUFFER STD LOGIC M OUT STD LOGIC VECTOR 3 DOWNTO 0 7 segs END COMPONENT COMPONENT bcd7seg PORT B IN STD LOGIC VECTOR 3 DOWNTO 0 H OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL A B S STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL Cin STD LOGIC SIGNAL C STD LOGIC VECTOR 4 DOWNTO 1 SIGNAL SO STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL 50 M STD LOGIC VECTOR 3 DOWNTO 0 modified SO for sums gt 15 SIGNAL S1 STD LOGIC BEGIN A lt SW 7 DOWNTO 4 B lt SW 3 DOWNTO 0 Cin lt SW 8 bit0 fa PORT MAP A 0 B 0 Cin S 0 C 1 bitl fa PORT MAP All Bil C 1 SU C 2 bit2 fa PORT MAP A 2 B 2 C 2 S 2 C 3 bit3 fa PORT MAP A 3 B 3 C 3 S 3 C 4 Display the inputs LEDR SW LEDG 4 DOWNTO 0 lt C 4 amp S Display the inputs H 6 bcd7seg PORT MAP A HEX HEX7 lt 1111111 display blank H 4 bcd7seg PORT MAP B HEX4 HEX5 lt 1111111 display blank Detect illegal inputs display on LEDG 8 LEDG 8 lt A 3 AND A 2 OR A 3 AND A 1 OR B 3 AND B 2 OR B 3 AND B 1 LEDG 7 DOWNTO 5 000 part4 vhd Display the sum bed decimal V z M BCD S bcd decimal PORT MAP S S1 SO S is really a 5 bit with the carry out the lower four bit sums 00 15 has to be modified in the cases that carry
130. al PORT MAP S S1M SO M S is really a 5 bit with the carry out but bcd decimal handles only the lower four bits sums 00 15 To account for sums 16 17 18 19 SO has to be modified in the cases that carry out 1 Use multiplexers S0 3 lt NOT C 4 AND SO M 3 OR C 4 AND SO M 1 S0 2 lt NOT C 4 AND SO M 2 OR C 4 AND NOT SO M 1 SO 1 lt NOT C 4 AND SO M 1 OR C 4 AND NOT SO M 1 S0 0 lt SO M 0 S is really a 5 bit t but bcd decimal works for only the lower four bits sums 00 15 To account for sums 16 17 18 19 S1 should be a 1 when the carry out is a 1l S1 lt SI M OR C 4 END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY fa IS PORT b co ci IN STD LOGIC OUT STD LOGIC a S END fa ARCHITECTURE Structure OF fa IS SIGNAL a_xor_b STD LOGIC BEGIN a xor b lt a XOR b s lt a xor b XOR ci co lt NOT a xor b END Structure AND b OR LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd decimal IS a xor b AND ci PORT V IN STD LOGIC VECTOR 3 DOWNTO 0 Z BUFFER STD LOGIC M OUT STD LOGIC VECTOR 3 DOWNTO 0 END bcd decimal ARCHITECTURE Structure OF bcd decimal IS SIGNAL B STD LOGIC VECTOR 2 DOWNTO 0 BEGIN gu rct 7 segs Page 2 part5 vhd z lt V 3 AND V 2 OR V 3 AND V 1 Circuit B B 2 lt V 2 A
131. avior OF part5 IS COMPONENT flip flop PORT R IN STD LOGIC Clock Resetn E STD LOGIC Q OUT STD LOGIC END COMPONENT COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT COMPONENT ramlpm PORT clock IN STD LOGIC data IN STD LOGIC VECTOR 7 DOWNTO 0 rdaddress IN STD LOGIC VECTOR 4 DOWNTO 0 wraddress IN STD LOGIC VECTOR 4 DOWNTO 0 wren IN STD LOGIC 11 q OUT STD LOGIC VECTOR 7 DOWNTO 0 END COMPONENT COMPONENT hex7seg PORT hex display END COMPONENT SIGNAL Clock Resetn SIGNAL Write address STD LOGIC VECTOR 4 IN Write Write sync Write address sync DOWNTO 0 STD LOGIC VECTOR 3 DOWNTO 0 OUT STD LOGIC VECTOR 0 TO 6 STD LOGIC Read address Read address cycles from addresses 0 to 31 at one second per address SIGNAL slow count SIGNAL Dataln Dataln sync BEGIN Resetn lt KEY 0 STD LOGIC VECTOR 24 DOWNTO DataOut ODF STD_LOGIC_VECTOR 7 DOWNTO 0 Write sync 1 Write Write address sync Clock lt CLOCK 50 synchronize all asynchronous inputs to the clock R1 flip flop PORT MAP SW 17 Clock Resetn 1 R2 flip flop PORT MAP Write sync Clock Resetn R3 regne GENERIC MAP N gt 5 PORT MAP SW 15 DOWNTO 11 Clock Resetn 1 R4 regne GENERIC MAP N gt 5 PORT MAP Write address s
132. ay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 E F T f f r F r F f r r r Page 2 part3 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Inputs KEYO manual clock SW0 active low reset SW1 enable signal for the counter Outputs HEXO HEX3 hex segment displays ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part3 ARCHITECTURE Behavior OF part3 IS COMPONENT lpm count PORT clock IN STD LOGIC cnt en IN STD LOGIC sclr IN STD LOGIC O q UT STD LOGIC VECTOR 15 DOWNTO 0 END COMPONENT COMPONENT hex7seg PORT X hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Resetn Enable STD LOGIC SIGNAL Count STD LOGIC VECTOR 15 DOWNTO 0 BEGIN 16 bit counter based on T flip flops Clock lt KEY 0 Resetn lt SW 0 Enable lt SW 1 16 bit counter lpm count clock ent en selt q Ul lpm count PORT MAP Clock Enable NOT Resetn Count drive the displays digit3 he
133. be loaded by the next active clock edge into register 4 A system like this is often called a processor It executes operations specified in the form of instructions Table 1 lists the instructions that the processor has to support for this exercise The left column shows the name of an instruction and its operand The meaning of the syntax RX RY is that the contents of register RY are loaded into register RX The mv move instruction allows data to be copied from one register to another For the mvi move immediate instruction the expression RX D indicates that the 16 bit constant D is loaded into register RX Operation Function performed mv Rz Ry Ra Ry mvi Ra HD Ra D add Rx Ry Rz Ra Ry sub Rx Ry Rx Ra Ry Table 1 Instructions performed in the processor Each instruction can be encoded and stored in the IR register using the 9 bit format IIIXXXYYY where III represents the instruction XXX gives the RX register and YYY gives the RY register Although only two bits are needed to encode our four instructions we are using three bits because other instructions will be added to the processor in later parts of this exercise Hence IR has to be connected to nine bits of the 16 bit DIN input as indicated in Figure 1 For the mvi instruction the Y YY field has no meaning and the immediate data D has to be supplied on the 16 bit DIN input after the mvi instruction word is stored into IR Some instr
134. bit numbers using the SW switches and display the numbers on the 2 digit 7 seg displays Multiply and display the product on the 4 digit 7 seg display ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 15 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part3 ARCHITECTURE Behavior OF part3 IS COMPONENT hex7seg PORT hex IN STD_LOGIC_VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT COMPONENT 1pm mult16 PORT dataa IN datab IN result END COMPONENT STD LOGIC VECTOR 7 DOWNTO 0 STD LOGIC VECTOR 7 DOWNTO 0 OUT STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL A B STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL P STD LOGIC VECTOR 15 DOWNTO 0 BEGIN A lt SW 15 DOWNTO 8 B lt SW 7 DOWNTO 0 lpm mult16 dataa datab result ul lpm mult16 PORT MAP A B P drive the display through a 7 seg decoder digit 7 hex7seg PORT MAP digit 6 hex7seg PORT MAP digit 5 hex7seg PORT MAP digit 4 hex7seg PORT MAP digit 3 hex7seg PORT MAP digit 2 hex7seg PORT MAP digit 1 hex7seg PORT MAP digit 0 hex7seg PORT MAP END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN S display OUT SI END hex7seg A 7 DOWNTO 4 HEX7 A 3 DOWNTO 0 HEX6
135. boratory Exercise 3 Multipliers The purpose of this exercise is to design a combinational circuit that can multiply two unsigned numbers First you will design the multiplier by writing VHDL code that describes the desired circuit Then you will use a predefined subcircuit for the multiplier from Altera s library of parameterized modules LPMs and compare the results achieved To make the design task more manageable start with a simple case of 4 bit numbers Part I Figure la gives an example of the traditional paper and pencil multiplication P A x B where A 12 and B 11 We need to add two summands that are shifted versions of A to form the product P 132 Part b of the figure shows the same example using four bit binary numbers Since each digit in B is either 1 or O the summands are either shifted versions of A or 0000 Figure 1c shows how each summand can be formed by using the Boolean AND operation of A with the appropriate bit in D a3 a a ag 1100 x b b bi bo 12 x1011 x E 1100 asb by ab ayb 12 1100 asb a b ab agb E dn asb a b a b ayb 132 1100 10000100 b bd NEM P7 Ps Ps P4 P3 P2 Py Po a Decimal b Binary c Implementation Figure 1 Multiplication of binary numbers A four bit circuit that implements P A x B is illustrated in Figure 2 Because of its regular structure this type of multiplier circuit is usually called an array multiplier The shaded areas in the circuit correspond to
136. ces of your circuit from part IV to build this two digit BCD adder Perform the steps below 1 Use switches SW15 s and SW7_ to represent 2 digit BCD numbers Ag and B Bo respectively The value of A Ap should be displayed on the 7 segment displays HEX7 and HEX6 while B Bo should be on HEX5 and HEX4 Display the BCD sum 525150 on the 7 segment displays HEX2 HEX and HEXO Make the necessary pin assignments and compile the circuit Download the circuit into the FPGA chip and test its operation Part VI In part V you created VHDL code for a two digit BCD adder by using two instances of the VHDL code for a one digit BCD adder from part IV A different approach for describing the two digit BCD adder in VHDL code is to specify an algorithm like the one represented by the following pseudo code 1 To Ao Bo 2 if Zo gt 9 then 3 Zo 10 4 C1 1 5 else 6 Zo 0 7 Cj 0 8 endif 9 So To Zo 10 Ti A1i B1i c1 11 if 7 gt 9 then 12 Z 10 13 c2 1 14 else 15 Zi 0 16 C2 0 17 endif 18 S Ti Z4 19 Sa Ca It is reasonably straightforward to see what circuit could be used to implement this pseudo code Lines 1 9 10 and 18 represent adders lines 2 8 and 11 17 correspond to multiplexers and testing for the conditions Ty gt 9 and Ti gt 9 requires comparators You are to write VHDL code that corresponds to this pseudo code Note that you can perform addition operations in you
137. compile the circuit and download it into the FPGA chip MH ON a A Test the functionality of your design by applying some inputs and observing the output display Part V For this part you are to design a circuit for the DE2 board that scrolls the word HELLO in ticker tape fashion on the eight 7 segment displays HEX7 0 The letters should move from right to left each time you apply a manual clock pulse to the circuit After the word HELLO scrolls off the left side of the displays it then starts again on the right side Design your circuit by using eight 7 bit registers connected in a queue like fashion such that the outputs of the first register feed the inputs of the second the second feeds the third and so on This type of connection between registers is often called a pipeline Each register s outputs should directly drive the seven segments of one display You are to design a finite state machine that controls the pipeline in two ways 1 For the first eight clock pulses after the system is reset the FSM inserts the correct characters H E L L 0 into the first of the 7 bit registers in the pipeline 2 After step 1 is complete the FSM configures the pipeline into a loop that connects the last register back to the first one so that the letters continue to scroll indefinitely Write VHDL code for the ticker tape circuit and create a Quartus II project for your design Use KEY 9 on the DE2 board to clock the FSM and pipeline
138. count gets to 0 Run Resetn Bus 16 Counter R7 Multiplexers Control unit 3 Figure 7 An enhanced version of the processor Figure 7 shows two registers in the processor that are used for data transfers The ADDR register is used to send addresses to an external device such as a memory module and the DOUT register is used by the processor to provide data that can be stored outside the processor One use of the ADDR register is for reading or fetching in structions from memory when the processor wants to fetch an instruction the contents of PC R7 are transferred across the bus and loaded into ADDR This address is provided to memory In addition to fetching instructions the processor can read data at any address by using the ADDR register Both data and instructions are read into the processor on the DIN input port The processor can write data for storage at an external address by placing this address into the ADDR register placing the data to be stored into its DOUT register and asserting the output of the W write flip flop to 1 Figure 8 illustrates how the enhanced processor is connected to memory and other devices The memory unit in the figure supports both read and write operations and therefore has both address and data inputs as well as a write enable input The memory also has a clock input because the address data and write enable inputs must be
139. ction from the memory The instruction is stored in IR and the PC is automatically incremented to point to the next instruction in the case of mvi the PC provides the address of the immediate data and is then incremented again The processor s control unit increments PC by using the incr PC signal which is just an enable on this counter It is also possible to directly load an address into PC R7 by having the processor execute a mv or mvi instruction in which the destination register is specified as R7 In this case the control unit uses the signal R7 in to perform a parallel load of the counter In this way the processor can execute instructions at any address in memory as opposed to only being able to execute instructions that are stored in successive addresses Similarly the current contents of PC can be copied into another register by using a mv instruction An example of code that uses the PC register to implement a loop is shown below where the text after the on each line is just a comment The instruction mv R5 R7 places into R5 the address in memory of the instruction sub R4 R2 Then the instruction mvnz R7 R5 causes the sub instruction to be executed repeatedly until R4 becomes 0 This type of loop could be used in a larger program as a way of creating a delay mvi R2 1 mvi R4 10000000 binary delay value mv R5 R7 save address of next instruction sub R4R2 decrement delay count mvnz R7 R5 continue subtracting until delay
140. d IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END bcd7seg ARCHITECTURE Behavior OF bcd7seg IS BEGIN part2 vhd PROCESS bcd BEGIN CASE bcd IS END CASE END PROCESS END Behavior WHEN 0000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN OTHERS disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay 0000 10011 0010 00001 10011 01001 1100 0001 0000 00011 11111 001 000 000 Page 3 part3 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Press KEY 0 to reset After a delay seconds set by the SW 7 DOWNTO 0 switches LEDR 0 turns on and the timer starts Stop the timer by pressing KEY 3 ENTITY part3 IS PORT CLOCK_50 IN STD_LOGIC SW IN STD LOGIC VECTOR 7 DOWNTO 0 KEY IN STD LOGIC VECTOR 3 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 0 TO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part3 ARCHITECTURE Behavior OF part3 IS COMPONENT regne PORT R Clock Resetn E IN STD LOGIC Q OUT SID LOGIC END COMPONENT COMPONENT bcd7seg PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC V
141. d for the address setup time t aw and the data to be written has to be valid for the data setup time tsp before the rising edge of W E Table 2 lists the minimum and maximum values of all timing parameters shown in Figure 4 Parameter Min Max TAA 10 ns toHA 3 ns taw 8 ns tsD 6 ns tHA 0 tsa 0 tHD 0 Table 2 SRAM timing parameter values You are to realize the 32 x 8 memory in Figure la by using the SRAM chip It is a good approach to include in your design the registers shown in Figure 1b by implementing these registers in the FPGA chip Be careful to implement properly the bidirectional data port that connects to the memory 1 Create a new Quartus II project for your circuit Write a VHDL file that provides the necessary functionality including the ability to load the memory and read its contents Use the same switches LEDs and 7 segment displays on the DE2 board as in Parts II and III and use the SRAM pin names shown in Table 3 to interface your circuit to the IS61LV25616AL chip the SRAM pin names are also given in the DE2 User Manual Note that you will not use all of the address and data ports on the IS61LV25616AL chip for your 32 x 8 memory connect the unneeded ports to O in your VHDL entity SRAM port name DE2 pin name A17 0 SRAM_ADDR 0 VO15 0 SRAM_DQ15 0 CE SRAM CE N OE SRAM OE N WE SRAM WE N UB SRAM_UB_N LB SRAM LB N Table 3 DE2 pin names for the SRAM chip 2 C
142. duces a character on a 7 segment display The conversion is defined by C 210 Char 000 gt 0 9 1 na 01 0 Ep O A Eg 1 9 0 Blank 10 1 1 Blank 110 Blank L SE dl Blank Codes 100 101 110 are not used ENTITY char 7seg IS PORT C IN STD LOGIC VECTOR 2 DOWNTO 0 Display OUT STD LOGIC VECTOR 0 TO 6 END char 7seg 0 RE Si 1 Gu TE 4 2 S 3 ARCHITECTURE Behavior OF char 7seg IS BEGIN the following equations describe display functions in inverted cannonical SOP form Display 0 lt NOT NOT C 2 AND NOT C 1 AND C 0 OR NOT C 2 AND C 1 AND C 0 Display 1 lt NOT NOT C 2 AND NOT C 1 AND NOT C 0 OR NOT C 2 AND C 1 AND C 0 Display 2 lt NOT NOT C 2 AND NOT C 1 AND NOT C 0 OR NOT C 2 AND C 1 AND C 0 Display 3 lt NOT NOT C 2 AND NOT C 1 AND C 0 OR NOT C 2 AND C 1 AND NOT C 0 OR NOT C 2 AND C 1 AND C 0 Display 4 lt NOT NOT C 2 AND NOT C 1 AND NOT C 0 OR NOT C 2 AND NOT C 1 AND C 0 OR NOT C 2 AND C 1 AND NOT C 0 OR NOT C 2 AND C 1 AND C 0 Display 5 lt NOT NOT C 2 AND NOT C 1 AND NOT C 0 OR NOT C 2 AND NOT C 1 AND C 0 OR NOT C 2 AND C 1 AND NOT C 0 OR NOT C 2 AND C 1 AND
143. e characters that are displayed on a 7 segment display Using the 7 segment decoder from Part IV this circuit can display any of the characters H E L O and blank The character codes are set according to Table by using the switches SW14 0 and a specific character is selected for display by setting the switches SW17 15 An outline of the VHDL code that represents this circuit is provided in Figure 8 Note that we have used the circuits from Parts III and IV as subcircuits in this code You are to extend the code in Figure 8 so that it uses five 7 segment displays rather than just one You will need to use five instances of each of the subcircuits The purpose of your circuit is to display any word on the five displays that is composed of the characters in Table 1 and be able to rotate this word in a circular fashion across the displays when the switches SW 17 15 are toggled As an example if the displayed word is HELLO then your circuit should produce the output patterns illustrated in Table 2 7 segment decoder Figure 7 A circuit that can select and display one of five characters LIBRARY ieee USE ieee std logic 1164 all ENTITY part5 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part5 ARCHITECTURE Behavior OF part5 IS COMPONENT mux 3bit_5to1 PORT S U VW X Y IN STD LOGIC VECTOR 2 DOWNTO 0 M OUT STD LOGIC VECTOR 2 DOWNTO 0 END COMPONENT COMPONENT char 7s
144. e lt 1 WHEN 010 gt add Rout lt Xreg Ain lt 1 WHEN 011 gt sub WHEN OTHERS gt sub Rout lt Xreg Ain lt 1 WHEN OTHERS gt END CASE WHEN 10 gt define signals in time step T2 CASE I IS WHEN 010 gt add Rout lt Yreg Gin lt 1 WHEN 011 gt sub WHEN OTHERS gt sub Rout lt Yreg AddSub lt 1 Gin lt 1 WHEN OTHERS gt END CASE WHEN 11 gt define signals in time step T3 CASE 1 IS WHEN 010 gt add Gout lt 1 Rin lt Xreg Done lt 1 WHEN 011 gt sub WHEN OTHERS gt sub Gout lt 1 Rin lt Xreg Done lt 1 WHEN OTHERS gt END CASE END CASE END PROCESS reg 0 regn PORT MAP BusWires Rin 0 Clock RO reg 1 regn PORT MAP BusWires Rin 1 Clock R1 reg_2 regn PORT MAP BusWires Rin 2 Clock R2 reg_3 regn PORT MAP BusWires Rin 3 Clock R3 reg_4 regn PORT MAP BusWires Rin 4 Clock R4 reg 5 regn PORT MAP BusWires Rin 5 Clock R5 reg_6 regn PORT MAP BusWires Rin 6 Clock R6 reg 7 regn PORT MAP BusWires Rin 7 Clock R7 reg_A regn PORT MAP BusWires Ain Clock A reg_IR regn GENERIC MAP n gt 9 PORT MAP DIN 15 DOWNTO 7 alu alu PROCESS AddSub A BusWires BEGIN IF AddSub 0 THEN Sum lt A BusWires IRin Clock Page 2 TR
145. e address sync Clock Resetn 1 Write address part7 vhd R5 regne Page 2 GENERIC MAP N gt 8 PORT MAP SW 7 DOWNTO 0 Clock Resetn 1 Dataln sync R6 regne GENERIC MAP N gt 8 PORT MAP DataIn sync Clock Resetn 1 Dataln one second cycle counter Create A large a 1Hz 5 bit address counter counter to produce a 1 second approx enable PROCESS Clock BEGIN IF Cl OCk EVENT AND Clock 1 THEN slow count lt slow count 1 END IF END PROCES the rea PROCESS C BEGIN IF Cl S d address counter lock ock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Read address lt OTHERS gt 0 ELSI F slow count 0 THEN Read address lt Read address 1 END END IF END PROCES SRAM ADDR ELSE SRAM DQ lt hold CE R7 flip f IF S lt 0000000000000 amp Write address WHEN SRAM WE N 0 0000000000000 amp Read address 00000000 amp Dataln WHEN SRAM WE N 0 ELSE Z22ZZZZZZZZZZZZZZZ N to I for two clock cycles after power up to avoid an accidental write lop PORT MAP 1 Clock Resetn 1 CE 1 R8 flip f 2 R9 flip f Z E op PORT MAP CE 1 Clock Resetn 1 C op PORT MAP CE 2 Clock Resetn 1 C an EE T SRAM_CE_N SRAM
146. e instances of the circuit in Figure 4a 000 u 001 y 010 w 011 x 100 y 101 y 1101 y ay b Truth table c Symbol Figure 4 A 5 to 1 multiplexer Figure 5 A three bit wide 5 to 1 multiplexer Perform the following steps to implement the three bit wide 5 to 1 multiplexer 1 Create a new Ouartus II project for your circuit 2 Create a VHDL entity for the three bit wide 5 to 1 multiplexer Connect its select inputs to switches SW17 15 and use the remaining 15 switches SW 44 o to provide the five 3 bit inputs U to Y Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG 2 9 3 Include in your project the required pin assignments for the DE2 board Compile the project 4 Download the compiled circuit into the FPGA chip Test the functionality of the three bit wide 5 to 1 multiplexer by toggling the switches and observing the LEDs Ensure that each of the inputs U to Y can be properly selected as the output M Part IV Figure 6 shows a 7 segment decoder module that has the three bit input cac co This decoder produces seven outputs that are used to display a character on a 7 segment display Table 1 lists the characters that should be displayed for each valuation of cac co To keep the design simple only four characters are included in the table plus the blank character which is selected for codes 100 111 The seven segments in the display are ide
147. e std I USE ieee std I T logic 1164 all logic signed all ENTITY pc count IS PORT R Resetn Clock Q END pc count IN STD LOGIC V L IN STD LOGIC OUT STD LOGIC V ECTOR 15 DOWNTO 0 ECTOR 15 DOWNTO 0 Page 4 proc vhd ARCHITECTURE Behavior OF pc count IS SIGNAL Count STD LOGIC VECTOR 15 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN Count lt OTHERS gt 0 ELSIF L 1 THEN Count lt R LSIF E 1 THEN Count lt Count 1 END IF END IF END PROCESS Q lt Count END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY dec3to8 IS PORT END dec3to8 Hp IN n IN OU ARCHITECTURE BEGIN PROCESS W En BEGIN IF En 1 THEN CASE W IS WHEN 000 WHEN 001 WHEN 010 WHEN 011 WHEN 100 WHEN 101 WHEN 110 WHEN 111 END CASE ELSE Y lt 0000000 END IF END PROCESS END Behavior LIBRARY ieee f y STD LOGIC VECTOR 2 DOWNTO 0 STD LOGIC T STD LOGIC VECTOR 0 TO 7 non H ow H H VVVVV V HH HH HR HH HR i 0 Behavior OF dec3to8 IS lt 10000000 lt 01000000 lt 00100000 00010000 lt 00001000 lt 00000100 lt 00000010 lt 00000001 USE ieee std logic 1164 all ENTITY regn IS GENERIC n INTEGER 16 PO
148. e subsequent page and accept the default settings to use a single clock for the RAM s registers and then advance again to the page shown in Figure 3 On this page deselect the setting called Read output port s under the category Which ports should be registered This setting creates a RAM module that matches the structure in Figure 1b with registered input ports and unregistered output ports Accept defaults for the rest of the settings in the Wizard and then instantiate in your top level VHDL file the entity generated in ramlpm vhd Include appropriate input and output signals in your VHDL code for the memory ports given in Figure 15 MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Cyclone Il ing Select a megafunction from the list below ng i 8 amp Installed Plug Ins Which type of output file do you want to create A Altera SOPC Builder C AHDL fl arithmetic e Z ARM Based Excalibur ee E gates Verilog HDL xA 1 0 2 B BS 9 88 memory compiler What name do you want for the output file rowse 1 FAU Program UP_Digital_Logic Exercise8 partl ramlpm SignalT ap Il Logic Analyzer fi storage Generate clear box netlist file instead of a default wrapper file A ALT3PRAM for use with supported EDA synthesis tools only Return to this page for another create operation ALTSHIFT TAPS Note To compile a project successfully in the Quartus so
149. ead from switches SW15 0 00 0010000000000000 mvi RO 1 K 01 0000000000000001 02 0000010000000000 mv R1 RO 1 03 0011100000000000 mvi R6 Beta Q lt D 04 0000000001100110 05 0010100000000000 mvi R2 0 LED 06 0000000000000000 07 0001011100000000 Loop mv R5 R6 P lt Q 08 0011000000000000 mvi RA H7 address 09 0010000000000000 OA 1000111010000000 ld R3 R5 P 0B 1010111000000000 st R3 R4 H7 P OC 0101010010000000 add R5 R1 P OD 0101000010000000 add R4 R1 H6 OE 1000111010000000 ld R3 R5 P OF 1010111000000000 st R3 R4 H6 P 10 0101010010000000 add R5 R1 P 11 0101000010000000 add R4 R1 H5 12 1000111010000000 ld R3 R5 P 13 1010111000000000 st R3 R4 H5 lt P 14 0101010010000000 add R5 R1 P 15 0101000010000000 add R4 R1 H4 16 1000111010000000 ld R3 R5 P 17 1010111000000000 st R3 R4 H4 P 18 0101010010000000 add R5 R1 P 19 0101000010000000 add R4 R1 H3 IA 1000111010000000 ld R3 R5 P 1B 1010111000000000 st R3 R4 H3 lt P 1C 0101010010000000 add R5 R1 P 1D 0101000010000000 add R4 R1 H2 1E 1000111010000000 ld R3 R5 P 1F 1010111000000000 st R3 R4 H2 lt P 20 0101010010000000 add R5 R1 P 21 0101000010000000 add R4 R1 H1 22 1000111010000000 ld R3 R5 P 23 1010111000000000 st R3 R4 H1 lt P 24 01010
150. ed all ENTITY proc IS PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC Done BUFFER STD LOGIC BusWires BUFFER STD LOGIC VECTOR 15 DOWNTO 0 END proc ARCHITECTURE Behavior OF proc IS declare components declare signals BEGIN High lt 1 Clear lt Tstep upcount PORT MAP Clear Clock Tstep_Q I lt IRI TO 3 decX dec3to8 PORT MAP IR 4 TO 6 High Xreg decY dec3to8 PORT MAP IR 7 TO 9 High Yreg Figure 2a Skeleton VHDL code for the processor controlsignals PROCESS Tstep Q I Xreg Yreg BEGIN specify initial values CASE Tstep QIS WHEN 00 gt store DIN in IR as long as Tstep_Q 0 IRin lt 1 WHEN 01 gt define signals in time step T1 CASE I IS END CASE WHEN 10 gt define signals in time step T2 CASE I IS END CASE WHEN 11 gt define signals in time step T3 CASE I IS END CASE END CASE END PROCESS reg 0 regn PORT MAP BusWires Rin 0 Clock RO instantiate other registers and the adder subtracter unit define the bus END Behavior Figure 2b Skeleton VHDL code for the processor LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic signed all ENTITY upcount IS PORT Clear Clock IN STD LOGIC OUT STD LOGIC VECTOR 1 DOWNTO 0 END upcount ARCHITECTURE Behavior OF upcount IS SIGNAL Count STD LOGIC VECTOR 1 DOWNTO 0 BEGIN PROCESS Clock BEGIN IF Clock EVENT A
151. eg PORT C IN STD LOGIC VECTOR 2 DOWNTO 0 Display OUT STD LOGIC VECTOR O TO 6 END COMPONENT SIGNAL M STD LOGIC VECTOR DOWNTO 0 BEGIN MO mux 3bit 5t01 PORT MAP SW 17 DOWNTO 15 SW 14 DOWNTO 12 SW 11 DOWNTO 9 SW 8 DOWNTO 6 SW 5 DOWNTO 3 SW 2 DOWNTO 0 M HO char 7seg PORT MAP M HEXO END Behavior LIBRARY ieee USE ieee std logic 1164 all implements a 3 bit wide 5 to 1 multiplexer ENTITY mux 3bit 5to1 IS PORT S U V W X Y IN STD LOGIC VECTOR DOWNTO 0 M OUT STD LOGIC VECTOR 2 DOWNTO 0 END mux 3bit 5tol ARCHITECTURE Behavior OF mux 3bit 5tol IS code not shown END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY char 7seg IS PORT C IN STD LOGIC VECTOR 2 DOWNTO 0 Display OUT STD LOGIC VECTOR O TO 6 END char 7seg ARCHITECTURE Behavior OF char 7seg IS code not shown END Behavior Figure 8 VHDL code for the circuit in Figure 7 SW17 SWig SWis Character pattern 000 H E L L O 001 E L L O H 010 L L OH E 011 L O H E L 100 O H E L L Table 2 Rotating the word HELLO on five displays Perform the following steps 1 Create a new Quartus II project for your circuit 2 Include your VHDL entity in the Quartus II project Connect the switches SW 17 15 to the select inputs of each of the five instances of the three bit wide 5 to 1 multiplexers Also connect SW 14 0 to each instance of the multiplexers as reguired to produce the patterns of cha
152. em that contains a number of 16 bit registers a multiplexer an adder subtracter unit a counter and a control unit Data is input to this system via the 16 bit DIN input This data can be loaded through the 16 bit wide multiplexer into the various registers such as R0 R7 and A The multiplexer also allows data to be transferred from one register to another The multiplexer s output wires are called a bus in the figure because this term is often used for wiring that allows data to be transferred from one location in a system to another Addition or subtraction is performed by using the multiplexer to first place one 16 bit number onto the bus wires and loading this number into register A Once this is done a second 16 bit number is placed onto the bus the adder subtracter unit performs the reguired operation and the result is loaded into register G The data in G can then be transferred to one of the other registers as required Clock DIN Control unit Run Resetn m L Figure 1 A digital system The system can perform different operations in each clock cycle as governed by the control unit This unit determines when particular data is placed onto the bus wires and it controls which of the registers is to be loaded with this data For example if the control unit asserts the signals RO out and A n then the multiplexer will place the contents of register RO onto the bus and this data will
153. etting Yes use this file for the memory content data and specify the filename ramlpm mif To learn about the format of a memory initialization file MIF see the Quartus II Help You will need to create this file and specify some data values to be stored in the memory Finish the Wizard and then examine the generated memory module in the file ramlpm vhd MegaWizard Plug In Manager ALTSYNCRAM page 7 of 8 Do you want to specify the initial content of the memory C No leave it blank r Yes use this file for the memory content data You can use a Hexadecimal Intel format File hex or a Memory Initialization File mif Browse File name a data 7 0 Poma gt wraddress 4 0 re i wen TA Block Type MMK Resource Estimate T E Documentation Cancel lt Back Next gt Finish Figure 5 Specifying a memory initialization file MIF 2 Write a VHDL file that instantiates your dual port memory To see the RAM contents add to your design a capability to display the content of each byte in hexadecimal format on the 7 segment displays HEX1 and HEX0 Scroll through the memory locations by displaying each byte for about one second As each byte is being displayed show its address in hex format on the 7 segment displays HEX3 and HEX2 Use the 50 MHz clock CLOCK 50 on the DE2 board and use KEY as a reset input For the write address and corresponding data use the same switches LEDs and 7 segment dis
154. ex7seg PORT MAP Dataln 7 DOWNTO 4 HEX5 digit6 hex7seg PORT MAP Address STD 3 DOWNTO 0 HEX6 digit7 hex7seg PORT MAP 000 amp Address STD 4 HEX7 LEDG 0 lt Write part3 vhd END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex display END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN 0 5 1 sues 4 2 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN 1010 WHEN 1 0 dll WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior IN STD LOGIC V OUT STD LOGIC VECTOR 0 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 ECTOR 3 DOWNTO 0 TO 6 Page 2 part4 vhd inputs outputs LIBRARY ie SRAM CE N KEYO is the reset write into memory SW15 SW11 provides the memory address KEY1 is the clock This code implements a single port memory using the external SRAM chip
155. flops Connect the LEDs register in Figure 8 to LEDR 150 so that you can observe the output produced by the processor 6 Compile the circuit and download it into the FPGA chip 7 Test the functionality of your design by executing code from the RAM and observing the LEDs Part IV In this part you are to connect an additional I O module to your circuit from Part III and write code that is executed by your processor Add a module called seg7 scroll to your circuit This module should contain one register for each 7 segment display on the DE2 board Each register should directly drive the segment lights for one 7 segment display so that the processor can write characters onto these displays Create the necessary address decoding to allow the processor to write to the registers in the seg7 scroll module 1 Create a Quartus II project for your circuit and write the VHDL code that includes the circuit from Figure 8 in addition to your seg7 scroll module 2 Use functional simulation to test the circuit 3 Add appropriate timing constraints and pin assignments to your project and write a MIF file that allows the processor to write characters to the 7 segment displays A simple program would write a word to the displays and then terminate but a more interesting program could scroll a message across the displays or scroll a word across the displays in the left right or both directions 4 Test the functionality of your design by executing
156. ft register inputs Resetn is ENTITY part3 IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 7 DOWNTO 0 END part3 ARCHITECTURE Behavior OF part3 IS SIGNAL Clock Resetn w z STD LOGIC SIGNAL 54 Os STD LOGIC VECTOR 1 TO 4 shift register for recognizing 4 Os SIGNAL S4 1s STD LOGIC VECTOR 1 TO 4 shift register for recognizing 4 1s BEGIN Clock KEY 0 Resetn SW 0 w lt SW 1 PROCESS Clock BEGIN TF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear 54 Os lt 1111 54 1s lt 0000 ELSE S4 Os 1 lt w S4 0s 2 lt S4 0s 1 54 0s 3 lt SA 0s 2 54 0s 4 lt SA 0s 3 S4 1s 1 lt w S4 1s 2 lt SA 1s 1 S4 1s 3 lt 54 1s 2 54 1s 4 lt SA 1s 3 END IF END IF END PROCESS z lt 1 WHEN 54 Os 0000 OR 84 ls 1111 ELSE 0 LEDR 3 DOWNTO 0 lt 84 Os LEDR 7 DOWNTO 4 lt 84 1s LEDG 0 lt z END Behavior part4 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all A mod 10 counter inputs SWO is the active low synchronous reset and KEYO is the clock SW2 SW1 are the wl w0 inputs output if wl w0 00 keep count the same if wl w0 01 increment count by 1 if wl w0 10 increment count by 2
157. ftware ALTSYNCRAM your design files must be in the project directory in the global user LPM FF libraries specified in the Options dialog box Tools menu or user library specified in the User Libraries page of the Settings dialog LPM FIFO box Assignments menu LPM LATCH LPM RAM DP Your current user library directories are LPM RAM DP LPM RAM DQ LPM ROM LPM SHIFTREG 88 IP MegaStore Cancel lt Back Next gt Figure 2 Choosing the altsyncram LPM MegaWizard Plug In Manager ALTSYNCRAM page 7 of 10 Which ports should be registered data wraddress and wren E rdaddress and rden More Options Read output port s q Create one clock enable signal for each clock signal More Options Create an acl asynchronous clear MESURE Block Type AUTO for the registered ports P Resource Estimate T zy E Documentation Cancel lt Back Next gt Finish Figure 3 Configuring input and output ports on the altsyncram LPM 3 Compile the circuit Observe in the Compilation Report that the Quartus II Compiler uses 256 bits in one of the M4K memory blocks to implement the RAM circuit 4 Simulate the behavior of your circuit and ensure that you can read and write data in the memory Part II Now we want to realize the memory circuit in the FPGA on the DE2 board and use toggle switches to load some data into the created memory We also want to displa
158. gt gt 0 1 0 Pig 6 1 1 or 1 9 9 Blank 1 0 1 Blank 110 1 Blank Je Xo Blank mE Codes 100 101 ENTITY char 7seg IS PORT 4 C Display END char_7seg IN SI OUT S Do Do 110 are not used IS LOGIC V LOGIC V E E ECTOR 1 TO 3 DV DX AND m 1 D Y 1 CTOR 2 DOWNTO 0 CTOR 2 DOWNTO 0 Page 2 intermediate multiplexers 1 1 2 5 to 1 multiplexer output input code on C2 0 into 7 bit code that produces a 7 segment display The conversion is defined by LOGIC VE LOGIC V E el OR 2 DOWNTO 0 CTOR 0 TO 6 Page 3 part5 vhd g IS ARCHITECTURE Behavior OF char se BEGIN E Ge A O un Al E E te D oO C ke O O 0 p Q Q y z Z 0 lt lt gt fag fag fag fag fag O O ARO AO A A A oO oO a e x E A A O o o O o ao no 2 aA O O O lt O lt O O gt E E o E AE AE A O O O ARO AO p O zZ O ZA NZ NZ El A A A A A O0 DA d JA Z lt H lt lt lt lt lt ER ER O O gt pes ss hais 9 AM a DQ A A t t6 t n O O DO OOOOOOU O
159. gt YD lt F WHEN 10 gt YD lt G WHEN 11 gt YD lt D END CASE part4 vhd Page 2 WHEN F gt CASE w IS WHEN 00 gt YD lt F WHEN 01 gt Y_D lt G WHEN 10 gt Y_D lt H WHEN 11 gt YD lt E END CASE WHEN G gt CASE w IS WHEN 00 gt YD lt G WHEN 01 gt YD lt H WHEN 10 gt YD lt I WHEN 11 gt YD lt F END CASE WHEN H gt CASE w IS WHEN 00 gt YD lt H WHEN 01 gt YD lt I WHEN 10 gt YD lt J WHEN 11 gt Y_D lt G END CASE WHEN I gt CASE w IS WHEN 00 gt YD lt I WHEN 01 gt YD lt J WHEN 10 gt Y_D lt A WHEN 11 gt YD lt H END CASE WHEN J gt CASE w IS WHEN 00 gt YD lt J WHEN 01 gt YD lt A WHEN 10 gt YD lt B WHEN 11 gt YD lt I END CASE END CASE END PROCESS state table PROCESS Clock BEGIN DR Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear y_0 lt A ELSE y_Q lt Y D END IF END IE END PROCESS PROCESS y 0 state outputs BEGIN CASE y Q IS WHEN A gt Count lt 0000 WHEN B gt Count lt 0001 WHEN C gt Count lt 0010 WHEN D gt Count lt 0011 WHEN E gt Count lt 0100 WHEN F gt Count lt 0101 WHEN G gt Count lt 0110 WHEN H gt Count lt 0111 WHEN I gt Count lt 1
160. he circuit and download it into the FPGA chip 5 Test the functionality of your design by toggling the switches and observing the output displays Copyright 2006 Altera Corporation partl vhd A gated RS latch described the hard way LIBRARY ieee USE ieee std logic 1164 all ENTITY partl IS PORT Clk R S IN STD LOGIC Q OUT STD LOGIC END partl ARCHITECTURE Structural OF partl IS SIGNAL R g S g Qa Ob STD LOGIC ATTRIBUTE keep boolean ATTRIBUTE keep of Rg S_g Qa Ob signal is true BEGIN Rg lt R AND Clk Sg lt S AND Clk Qa lt NOT R g OR Qb Ob lt NOT 5 g OR Qa se se Q lt Qa END Structural Page 1 D latch vhd LIBRARY ieee USE ieee std logic 1164 all A gated D latch described the hard way ENTITY D latch IS PORT Clk D IN STD LOGIC Q OUT STD LOGIC END D latch ARCHITECTURE Structural OF D latch IS SIGNAL R Rg S 9 Qa Ob STD LOGIC ATTRIBUTE keep boolean ATTRIBUTE keep of R Rg S g Qa Ob signal is true BEGIN R NOT D S g lt NOT D AND C R_g lt NOT R AND Cl Qa lt NOT S g AND Ob Ob lt NOT R g AND Qa Lk lk e r Q lt Qa END Structural Page 1 top vhd LIBRARY ieee USE ieee std logic 1164 SW 0 is the latch s ENTITY top IS PORT SW LEDR IN OUT END top ARCHITECTURE Structural COMPONENT D_latch PORT Clk D Q END COMPONENT
161. he counter increments its count on each positive edge of the clock if the Enable signal is asserted The counter is reset to 0 by using the Reset signal You are to implement a 16 bit counter of this type Enable Clock Clear Figure 1 A 4 bit counter 1 Write a VHDL file that defines a 16 bit counter by using the structure depicted in Figure 8 and compile the circuit How many logic elements LEs are used to implement your circuit What is the maximum freguency Fmax at which your circuit can be operated 2 Simulate your circuit to verify its correctness 3 Augment your VHDL file to use the pushbutton KEY as the Clock input switches SW and SWo as Enable and Reset inputs and 7 segment displays HEX3 0 to display the hexadecimal count as your circuit operates Make the necessary pin assignments and compile the circuit 4 Implement your circuit on the DE2 board and test its functionality by operating the implemented switches 5 Implement a 4 bit version of your circuit and use the Ouartus II RTL Viewer to see how Ouartus II software synthesized your circuit What are the differences in comparison with Figure 8 Part II Simplify your VHDL code so that the counter specification is based on the VHDL statement A lt O 1 Compile a 16 bit version of this counter and compare the number of LEs needed and the Fmax that is attainable Use the RTL Viewer to see the structure of this implementation and comment on the differe
162. i peo pel pe2 pe3 pe4 pe5 pe6 CY CX CY X C Y 2 pipe E 0 lock lock lock lock lock lock lock lank lank lank Lt select Resetn Resetn Resetn Resetn Resetn Resetn Resetn 0 ELSE pipe pipe input Clock Resetn Tick pipe0 Tick pipel Tick pipe2 Tick pipe3 Tick pipe4 Tick pipe5 Tick pipe6 Tick pipe r e r r r Page 2 part6 vhd Page 3 HEX5 lt pipe5 HEX6 lt pipe6 HEX7 lt pipe END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF CLock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear O lt OTHERS gt 1 ELSIF E 1 THEN Q lt R END IF END IE END PROCESS END Behavior part7 vhd Page 1 scrolls the word HELLO across the 7 seg displays An FSM inserts the display values into a pipeline that drives the 8 displays each display is driven for about I second before changing to the next character inputs 50 MHz clock KEYO is reset input KEY1 doubles the speed of the display KEY2 halves the speed outputs 7 seg displays HEX7 HEXO LIBRA
163. in Figure la It contains 32 eight bit words rows which are accessed using a five bit address port an eight bit data port and a write control input We will consider two different ways of implementing this memory using dedicated memory blocks in an FPGA device and using a separate memory chip The Cyclone II 2C35 FPGA that is included on the DE2 board provides dedicated memory resources called M4K blocks Each M4K block contains 4096 memory bits which can be configured to implement memories of various sizes A common term used to specify the size of a memory is its aspect ratio which gives the depth in words and the width in bits depth x width Some aspect ratios supported by the MAK block are 4K x 1 2K x 2 IK x 4 and 512 x 8 We will utilize the 512 x 8 mode in this exercise using only the first 32 words in the memory We should also mention that many other modes of operation are supported in an M4K block but we will not discuss them here Address 8 32 x 8 RAM Data Write a RAM organization Address Dataln 32 x 8 RAM DataOut Write Clock b RAM implementation Figure 1 A 32 x 8 RAM module There are two important features of the M4K block that have to be mentioned First it includes registers that can be used to synchronize all of the input and output signals to a clock input Second the M4K block has separate ports for data being written to the memory and data being read from the memory A reguirement for us
164. ing the M4K block is that either its input ports output port or both have to be synchronized to a clock input Given these requirements we will implement the modified 32 x 8 RAM module shown in Figure 15 It includes registers for the address data input and write ports and uses a separate unregistered data output port Part I Commonly used logic structures such as adders registers counters and memories can be implemented in an FPGA chip by using LPM modules from the Quartus II Library of Parameterized Modules Altera recommends that a RAM module be implemented by using the altsyncram LPM In this exercise you are to use this LPM to implement the memory module in Figure 15 1 Create a new Quartus II project to implement the memory module Select as the target chip the Cyclone II EP2C35F672C6 which is the FPGA chip on the Altera DE2 board 2 You can learn how the MegaWizard Plug in Manager is used to generate a desired LPM module by reading the tutorial Using Library Modules in VHDL Designs This tutorial is provided in the University Program section of Altera s web site In the first screen of the MegaWizard Plug in Manager choose the altsyncram LPM which is found under the storage category As indicated in Figure 2 select VHDL HDL as the type of output file to create and give the file the name ramlpm vhd On the next page of the Wizard specify a memory size of 32 eight bit words and select M4K as the type of RAM block Advance to th
165. isplay lt 1000010 WHEN 1110 gt display lt 0110000 WHEN OTHERS gt display lt 0111000 END CASE END PROCESS END Behavior DOWNTO 0 TO 6 Page 2 part2 vhd LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Inputs KEYO manual clock SW0 active low reset SW1 enable signal for the counter Outputs HEXO HEX3 hex segment displays ENTITY part2 IS PORT 1 SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part2 ARCHITECTURE Behavior OF part2 IS COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display END COMPONENT SIGNAL Clock Resetn Enable OUT STD LOGIC VECTOR 0 TO 6 STD LOGIC SIGNAL Count STD LOGIC VECTOR 15 DOWNTO 0 BEGIN 16 bit counter based on T flip flops Clock lt KEY 0 Resetn lt SW 0 Enable lt SW 1 PROCESS Clock BEGIN IF Clock EVENT AND Clock IF Resetn 0 THEN Count lt OTHERS gt Q ELSIF Enable 1 THEN 1 THEN 15 DOWNTO 12 HEX3 11 DOWNTO 8 HEX2 7 DOWNTO 4 HEX1 3 DOWNTO 0 HEX0 TOR 3 DOWNTO 0 Count lt Count 1 END IF END IF END PROCESS drive the displays digit3 hex7seg PORT MAP Count digit2 hex7seg PORT MAP Count dig
166. ite 3 Compile the project and download the compiled circuit into the FPGA chip 4 Test the functionality of your design by toggling the switches and observing the displays Part II You are to design a circuit that converts a four bit binary number V v3v2v19 into its two digit decimal equiv alent D dido Table 1 shows the required output values A partial design of this circuit is given in Figure 1 It includes a comparator that checks when the value of V is greater than 9 and uses the output of this comparator in the control of the 7 segment displays You are to complete the design of this circuit by creating a VHDL entity which includes the comparator multiplexers and circuit A do not include circuit B or the 7 segment decoder at this point Your VHDL entity should have the four bit input V the four bit output M and the output z The intent of this exercise is to use simple VHDL assignment statements to specify the required logic functions using Boolean expressions Your VHDL code should not include any IF ELSE CASE or similar statements Binary value Decimal digits 0000 0 0 0001 0 1 0010 0 2 1001 0 9 1010 1 0 1011 1 1 1100 1 2 1101 1 3 1110 1 4 1111 1 5 Table 1 Binary to decimal conversion values Perform the following steps 1 Make a Quartus II project for your VHDL entity 2 Compile the circuit and use functional simulation to verify the correct operation of your comparator multi plexers and circuit
167. ite IN STD_LOGIC Dataln IN STD LOGIC VECTOR 7 DOWNTO 0 Address IN STD LOGIC VECTOR 4 DOWNTO 0 DataOut OUT STD LOGIC VECTOR 7 DOWNTO 0 END parti ARCHITECTURE Behavior OF parti IS COMPONENT ramlpm PORT lt address IN STD LOGIC VECTOR 4 DOWNTO 0 clock IN STD LOGIC data IN STD LOGIC VECTOR 7 DOWNTO 0 wren IN STD LOGIC 1 q OUT STD LOGIC VECTOR 7 DOWNTO 0 END COMPONENT BEGIN instantiate LPM module module ramlpm address clock data wren q m32x8 ramlpm PORT MAP Address Clock Dataln Write DataOut END Behavior part2 vhd Page 1 This code instantiates a 32 x 8 memory n the Cyclone II FPGA on the DE2 board inputs KEYO is the clock SW SWO provides data to write into memory SW15 SW11 provides the memory address SW17 is the memory Write input outputs 7 seg displays HEX7 HEX6 display the memory addres HEX5 HEX4 displays the data input to the memory and HEX1 HEXO show the contents read from the memory LEDGO shows the status of Write LIBRARY ieee USE ieee std logic 1164 all ENTITY part2 IS PORT KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 END part2 ARCHITECTURE Behavior OF part2 IS COMPONENT ramlpm PORT add
168. ite Address 3 DOWNTO 0 HEX6 digit7 hex7seg PORT MAP 000 amp Write Address 4 HEX7 LEDG 0 lt Write END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY regne IS GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END regne ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear O lt OTHERS gt 0 ELSIF E 1 THEN part5 vhd Page 3 p e END IF END IF END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY flip flop IS PORT R IN STD LOGIC Clock Resetn E IN STD LOGIC Q OUT STD LOGIC END flip flop ARCHITECTURE Behavior OF flip flop IS BEGIN PROCESS Clock BEGIN IF CLock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt 0 ELSIF E 1 THEN O lt R END IF END IE END PROCESS END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN m 0 51 1 6 4 2 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt di
169. itl hex7seg PORT MAP Count digit0 hex7seg PORT MAP Count END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex7seg IS PORT hex IN STD LOGIC VECT display OUT STD LOGIC VEC END hex7seg ARCHITECTURE BEGIN Behavior OF hex7seg IS OR 0 TO 6 Page 1 part2 vhd S 3 PROCESS hex BEGIN CASE hex IS WHEN 000 WHEN 0001 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 0 0 L WHEN 1010 WHEN 1 0 LE WHEN 1100 WHEN 1 L 0 T WHEN 1110 WHEN OTHERS END CASE END PROCESS END Behavior 0 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 r E pF r r r F F r Fr rd p F Page 2 part2 4bits vhd LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Inputs KEYO manual clock SW0 active low reset SW1 enable signal for the counter gt Outputs HEXO HEX3 hex segment displays ENTITY part2 IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0
170. lays HEX7 6 the minute from 0 to 60 on HEX5 4 and the second from 0 to 60 on HEX3 2 Use the switches SWis o to preset the hour and minute parts of the time displayed by the clock Part III Design and implement on the DE2 board a reaction timer circuit The circuit is to operate as follows 1 The circuit is reset by pressing the pushbutton switch KEY 2 After an elapsed time the red light labeled LEDR turns on and a four digit BCD counter starts counting in intervals of milliseconds The amount of time in seconds from when the circuit is reset until LEDR y is turned on is set by switches SW7 0 3 A person whose reflexes are being tested must press the pushbutton KEY3 as quickly as possible to turn the LED off and freeze the counter in its present state The count which shows the reaction time will be displayed on the 7 segment displays HEX2 0 Copyright 2006 Altera Corporation partl vhd LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all r A 3 digit BCD counter ENTITY partl IS PORT CLOCK 50 IN STD LOGIC KEY IN STD LOGIC VECTOR 3 DOWNTO 0 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END partl ARCHITECTURE Behavior OF partl IS COMPONENT bcd7seg PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL slow count SIGNAL bcd 0 bcd 1 IN bed 2 BEG First PROCESS BEGIN IF
171. ments for the DE2 board as discussed above Compile the project 4 Download the compiled circuit into the FPGA chip Test the functionality of the circuit by toggling the switches and observing the LEDs Part II Figure 2a shows a sum of products circuit that implements a 2 to 1 multiplexer with a select input s If s 0 the multiplexer s output m is equal to the input x and if s 1 the output is equal to y Part b of the figure gives a truth table for this multiplexer and part c shows its circuit symbol X P M y a Circuit S m 0 E x 0 m 1 y y 1 b Truth table c Symbol Figure 2 A 2 to 1 multiplexer The multiplexer can be described by the following VHDL statement m lt NOT s AND x OR s AND y You are to write a VHDL entity that includes eight assignment statements like the one shown above to describe the circuit given in Figure 3a This circuit has two eight bit inputs X and Y and produces the eight bit output M If s 0 then M X while if s 1 then M Y We refer to this circuit as an eight bit wide 2 to 1 multiplexer It has the circuit symbol shown in Figure 3b in which X Y and M are depicted as eight bit wires Perform the steps shown below 47 37 X 0 6 Mg Y6 1 M US X 0 mo Yo 1 a Circuit b Symbol Figure 3 An eight bit wide 2 to 1 multiplexer 1 Create a new Quartus II project for your circuit 2 Include your VHDL file for the eight bit wide 2 to 1 multi
172. mux 3bit 5tol PORT MAP Ch Sel Ch5 Ch1 Ch2 Ch3 Ch4 HO Ch instantiate char 7seg C Display H7 char 7seg PORT MAP Blank HEX7 H6 char 7seg PORT MAP Blank HEX H5 char 7seg PORT MAP Blank HEX5 H4 char 7seg PORT MAP H4 Ch HEX4 part5 vhd H3 char 7seg PORT MAP H3 Ch HEX3 H2 char 7seg PORT MAP H2 Ch HEX2 Hl char 7seg PORT MAP H1 Ch HEX1 HO char 7seg PORT MAP HO Ch HEXO END Structure LIBRARY ieee USE ieee std logic 1164 all Implements a 3 bit wide 5 to 1 multiplexer ENTITY mux 3bit 5tol IS PORT Se Ur V W X Y M END mux 3bit 5tol ARCHITECTURE Behavior OF mux 3bit 5tol IN STD 1 OUT STD SIGNAL m 0 m 1 m 2 STD LOGIC V BEGIN 5 to 1 multiplexer for bit 0 m O 1 lt NOT S 0 AND U 0 OR S m 0 2 lt NOT S 0 AND W 0 OR S m 0 3 lt NOT S 1 AND m 0 1 OR M 0 lt NOT S 2 AND m 0 3 OR S 5 to 1 multiplexer for bit 1 m 1 1 lt NOT S 0 AND U 1 OR S m 1 2 lt NOT S 0 AND W 1 OR S m 1 3 lt NOT S 1 AND m 1 1 OR M 1 lt NOT S 2 AND m 1 3 OR S 5 to 1 multiplexer for bit 2 m 2 1 lt NOT S 0 AND U 2 OR S m 2 2 lt NOT S 0 AND W 2 OR S m 2 3 NOT S 1 AND m 2 1 OR M 2 lt NOT S 2 AND m 2 3 OR S END Behavior LIBRARY ieee USE ieee std logic 1164 all Converts 3 bit a character on C210 Char 000 yr 0 9 1
173. mv Inner sub mvnz sub mvnz mvi ld mvi Alpha l Alpha Beta jk Beta 1 E 124 Temp Temp RO R5 R4 R5 R7 R6 R6 R5 R5 R5 RO R5 RO R3 R2 R3 R5 R4 RO RO R4 R7 R3 R7 R5 RO R7 R5 R6 R4 RI RI R5 R3 RL R7 RO R7 R1 RO R1 RS T R5 Beta 1 Cont 1111111111111111 LED 11111111111111 101100 mp Loop Page 2 Q Beta 1 N Q Beta 1 Save reg LED reg address LED LED Delay Save address of next Inner loop delay nop Save address of next Decrement R4 jnz Inner Decrement R3 jnz Outer Restore regs part5 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all Reset with KEYO SW17 is Run The processor executes the instructions in the file inst mem mif ENTITY part5 IS PORT KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 0 Clock IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDR OUT STD LOGIC VECTOR 15 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 8 DOWNTO 0 DOUT ADDR BUFFER STD LOGIC VECTOR 15 DOWNTO 0 W Done BUFFER STD LOGIC END partd5 ARCHITECTURE Behavior OF part5 IS COMPONENT proc PORT DI
174. nces with the design from Part I Part III Use an LPM from the Library of Parameterized modules to implement a 16 bit counter Choose the LPM options to be consistent with the above design i e with enable and synchronous clear How does this version compare with the previous designs Part IV Design and implement a circuit that successively flashes digits O through 9 on the 7 segment display H E X0 Each digit should be displayed for about one second Use a counter to determine the one second intervals The counter should be incremented by the 50 MHz clock signal provided on the DE2 board Do not derive any other clock signals in your design make sure that all flip flops in your circuit are clocked directly by the 50 MHz clock signal Part V Design and implement a circuit that displays the word HELLO in ticker tape fashion on the eight 7 segment displays HE X7 0 Make the letters move from right to left in intervals of about one second The patterns that should be displayed in successive clock intervals are given in Table 1 Clock cycle Displayed pattern 0 HE L L O 1 H E L L O 2 H E L L O 3 H E L L O 4 E L L O H 5 L L O H E 6 L O H E L 7 O H E LL 8 H L L O and so on Table 1 Scrolling the word HELLO in ticker tape fashion Copyright 2006 Altera Corporation partl vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all inputs KEYO manual clock SW0 active low reset SW1 enable signal for the
175. ner mvi mvi mvi st add mvi ub vnz ub vnz mvi R2 R2 R3 R2 R2 R3 R5 R4 RO R4 R7 R3 R7 R7 on the red LEDs 1 0 0001000000000000 R3 R1 1111111111111111 R7 10100 R7 R1 RO R1 R5 Loop Page 1 1 LED LED reg address LED LED Delay Save address of next Nested delay Save address of next Decrement R4 jnz Inner Decrement R3 jnz Outer part4 vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all Reset with KEYO SW17 is Run Set delay using SW15 0 ENTITY part4 IS PORT KEY IN STD LOGIC VECTOR 0 DOWNTO 0 SW IN STD LOGIC VECTOR 17 DOWNTO 17 Clock IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 LEDR OUT STD LOGIC VECTOR 15 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 8 DOWNTO 0 DOUT ADDR BUFFER STD LOGIC VECTOR 15 DOWNTO 0 W Done BUFFER STD LOGIC END part4 ARCHITECTURE Behavior OF part4 IS COMPONENT proc PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC DOUT OUT STD LOGIC VECTOR 15 DOWNTO 0 ADDR OUT STD LOGIC VECTOR 15 DOWNTO 0 W OUT STD LOGIC Done BUFFER STD LOGIC END COMPONENT COMPONENT inst mem PORT address IN STD LOGIC VECTOR 6 DOWNTO 0 clock
176. ntiate module mux 3bit 8tol S Gl G2 G3 G4 G5 G6 G7 G8 M to create the multiplexer for each hex display M7 mux 3bit 8tol PORT MAP Ch Sel Blank Blank Blank Chl Ch2 Ch3 Ch4 Ch5 H7 Ch M6 mux 3bit 8tol PORT MAP Ch Sel Blank Blank Ch1 Ch2 Ch3 Ch4 Ch5 Blank H6 Ch M5 mux 3bit 8tol PORT MAP Ch Sel Blank Ch1 Ch2 Ch3 Ch4 Ch5 part6 vhd Blank Blank H5 Ch M4 mux 3bit 8tol PORT MAP Ch Sel Blank Blank H4 Ch M3 mux 3bit 8tol PORT MAP Ch Sel Blank Ch1 H3 Ch M2 mux 3bit 8tol PORT MAP Ch Sel Chl Ch2 H2 Ch M1 mux 3bit 8tol PORT MAP Ch Sel Ch2 Ch3 H1 Ch MO mux 3bit 8tol PORT MAP Ch Sel Ch3 Ch4 HO Ch char 7seg char 7seg char 7seg char 7seg char 7seg char 7seg char 7seg char 7seg END Structure LIBRARY ieee USE ieee std_logic_1164 all instantiate module char seg PORT MAP PORT MAP PORT MAP PORT MAP PORT MAP PORT MAP PORT MAP PORT MAP 7 ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Ch xx KK gt x KO O P N Q F GOO JS EH p Ed El Db E D Es r r pF r Chl Ch2 Ch3 Ch4 Ch5 Disp Se Se Ne Ne Ne Ne Ne Ne Ch2 Ch Ch4 Ch5 Blank Page 2 Ch3 Ch4 Ch5 Blank Ch4 Ch5 Blank Blank Ch5 Blank Blank Blank Blank Blank Blank Chl Blank Blank Chl Ch2 lay
177. ntified by the indices 0 to 6 shown in the figure Each segment is illuminated by driving it to the logic value 0 You are to write a VHDL entity that implements logic functions that represent circuits needed to activate each of the seven segments Use only simple VHDL assignment statements in your code to specify each logic function using a Boolean expression Ca i 7 segment decoder Co Figure 6 A 7 segment decoder cocico Character 000 001 010 011 100 101 110 111 orm a Table 1 Character codes Perform the following steps 1 Create a new Quartus II project for your circuit 2 Create a VHDL entity for the 7 segment decoder Connect the cac co inputs to switches SW o and connect the outputs of the decoder to the HEXO display on the DE2 board The segments in this display are called HEX05 HEX01 HEXOs corresponding to Figure 6 You should declare the 7 bit port HEXO OUT STD LOGIC VECTOR 0 TO 6 in your VHDL code so that the names of these outputs match the corresponding names in the DE2 User Manual and the DE pin assignments csv file 3 After making the required DE2 board pin assignments compile the project 4 Download the compiled circuit into the FPGA chip Test the functionality of the circuit by toggling the SW2 o switches and observing the 7 segment display Part V Consider the circuit shown in Figure 7 It uses a three bit wide 5 to 1 multiplexer to enable the selection of fiv
178. o SQ Cout 53 52 51 50 c Full adder truth table d Four bit ripple carry adder circuit Figure 2 A ripple carry adder circuit 1 Create a new Quartus II project for the adder circuit Write a VHDL entity for the full adder subcircuit and write a top level VHDL entity that instantiates four instances of this full adder 2 Use switches SW7_4 and SW3_0 to represent the inputs A and B respectively Use SW for the carry in Cin Of the adder Connect the SW switches to their corresponding red lights LEDR and connect the outputs of the adder Cout and S to the green lights LEDG 3 Include the necessary pin assignments for the DE2 board compile the circuit and download it into the FPGA chip 4 Test your circuit by trying different values for numbers A B and cin Part IV In part II we discussed the conversion of binary numbers into decimal digits It is sometimes useful to build circuits that use this method of representing decimal numbers in which each decimal digit is represented using four bits This scheme is known as the binary coded decimal BCD representation As an example the decimal value 59 is encoded in BCD form as 0101 1001 You are to design a circuit that adds two BCD digits The inputs to the circuit are BCD numbers 4 and B plus a carry in Cin The output should be a two digit BCD sum 5150 Note that the largest sum that needs to be handled by this circuit is 5150 9 9 1 19 Perform the steps given below 1
179. ompile the circuit and download it into the FPGA chip 3 Test the functionality of your design by reading and writing values to several different memory locations Part V The SRAM block in Figure 1 has a single port that provides the address for both read and write operations For this part you will create a different type of memory module in which there is one port for supplying the address for a read operation and a separate port that gives the address for a write operation Perform the following steps 1 Create a new Quartus II project for your circuit To generate the desired memory module open the MegaWiz ard Plug in Manager and select again the altsyncram LPM in the storage category On Page 1 of the Wizard choose the setting With one read port and one write port simple dual port mode in the category called How will you be using the altsyncram Advance through Pages 2 to 5 and make the same choices as in Part II On Page 6 choose the setting don t care in the category Mixed Port Read During Write for Single Input Clock RAM This setting specifies that it does not matter whether the memory outputs the new data being written or the old data previously stored in the case that the write and read addresses are the same Page 7 of the Wizard is displayed in Figure 5 It makes use of a feature that allows the memory module to be loaded with initial data when the circuit is programmed into the FPGA chip As shown in the figure choose the s
180. or has the ability to perform read and write operations using memory or other devices These enhancements involve adding new instructions to the processor and the programs that the processor executes are therefore more complex Since these steps are beyond the scope of some logic design courses they are described in a subsequent lab exercise available from Altera Copyright 2006 Altera Corporation proc vhd LIBRARY ieee Page 1 USE ieee std logic 1164 all USE ieee std logic signed all ENTITY proc IS PORT DIN IN STD LOGIC VECTOR 15 DOWNTO 0 Resetn Clock Run IN STD LOGIC Done BUFFER STD LOGIC BusWires BUFFER STD LOGIC VECTOR 15 DOWNTO 0 END proc ARCHITECTURE Behavior OF proc IS COMPONENT upcount PORT Clear Clock IN STD LOGIC Q END COMPONENT BUFFER STD LOGIC VECTOR 1 DOWNTO 0 COMPONENT dec3to8 PORT W En Y END COMPONENT COMPONENT regn IN STD LOGIC VECTOR 2 DOWNTO 0 IN STD LOGIC OUT STD LOGIC VECTOR 0 TO 7 GENERIC n INTEGER 16 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Rin Clock IN STD LOGIC 0 BUFFER STD_LOGIC_VECTOR n 1 DOWNTO 0 END COMPONENT SIGNAL Rin Rout STD LOGIC VECTOR O TO 7 SIGNAL Sum STD LOGIC VECTOR 15 DOWNTO 0 SIGNAL Clear High IRin DINout Ain Gin Gout AddSub STD LOGIC SIGNAL Tstep OQ STD LOGIC VECTOR 1 DO
181. out SO M 3 lt NOT C 4 AND S0 3 OR C 4 AND SO 1 SO M 2 lt NOT C 4 AND S0 2 OR C 4 AND NOT SO SO M 1 lt NOT C 4 AND SO 1 OR C 4 AND NOT SO SO M 0 lt S0O 0 H 0 bcd7seg PORT MAP S0 M HEXO but bcd decimal To account for sums 16 Ls E 1 1 hand LT 18 es only 19 SO Use multipl LOXOIS S is really a 5 bit but bcd decimal works for only the lower four bits 18 sums 00 15 To account for sums 16 17 the carry out is a 1 HEX1 lt 1 amp NOT S1 OR C 4 amp NOT S1 OR C 4 HEX2 lt 1111111 display blank HEX3 lt 1111111 display blank END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY fa IS PORT ar b ci IN STD LOGIC S CO OUT STD LOGIC END fa ARCHITECTURE Structure OF fa IS SIGNAL a xor b SID LOGIC BEGIN a xor b lt a XOR b s lt a xor b XOR ci co lt NOT a xor b AND b OR a xor b AND ci END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY bed decimal IS PORT V IN STD LOGIC VECTOR 3 DOWNTO 0 z BUFFER STD LOGIC M OUT STD LOGIC VECTOR 3 DOWNTO 0 END bcd decimal ARCHITECTURE Structure OF bcd decimal IS SIGNAL B STD LOGIC VECTOR 2 DOWNTO 0 BEGIN G Lreuit A z lt V 3 AND V 2 OR V 3 AND V 1 Circuit B B 2 lt V 2 AND V 1 B 1 lt V 2 AND N
182. pen the Compilation Report select the Analysis and Synthesis section of the report and click on State Machines Simulate the behavior of your circuit 6 Once you are confident that the circuit works properly as a result of your simulation download the circuit into the FPGA chip Test the functionality of your design by applying the input seguences and observing the output LEDs Make sure that the FSM properly transitions between states as displayed on the red LEDs and that it produces the correct output values on LEDG o 7 In step 3 you instructed the Quartus II Synthesis tool to use the state assignment given in your VHDL code To see the result of changing this setting open again the Quartus II settings window by choosing Assignments gt Settings and click on the Analysis and Synthesis item Change the setting for State Machine Processing from Minimal Bits to One Hot Recompile the circuit and then open the report file select the Analysis and Synthesis section of the report and click on State Machines Compare the state codes shown to those given in Table 2 and discuss any differences that you observe Settings part2 Category General Analysis amp Synthesis Settings Files User Libraries Current Project Specify options for analysis amp synthesis These options control Quartus Integrated Synthesis and Device do not affect VOM or EDIF netlists unless WYSIWYG primitive resynthesis is enabled Timing Requirements amp Option
183. plays as in the previous parts of this exercise Make sure that you properly synchronize the toggle switch inputs to the 50 MHz clock signal 3 Test your circuit and verify that the initial contents of the memory match your ramlpm mif file Make sure that you can independently write data to any address by using the toggle switches Part VI The dual port memory created in Part V allows simultaneous read and write operations to occur because it has two address ports In this part ofthe exercise you should create a similar capability but using a single port RAM Since there will be only one address port you will need to use multiplexing to select either a read or write address at any specific time Perform the following steps 1 Create a new Ouartus II project for your circuit and use the MegaWizard Plug in Manager to again create a single port version of the altsyncram LPM For Pages 1 to 6 of the Wizard use the same settings as in Part 1 On Page 7 shown in Figure 6 specify the ramlpm mif file as you did in Part V but also make the setting Allow In System Memory Content Editor to capture and update content independently of the system clock This option allows you to use a feature of the Ouartus II CAD system called the In System Memory Content Editor to view and manipulate the contents of the created RAM module When using this tool you can optionally specify a four character Instance ID that serves as a name for the memory in Figure 7 we
184. plexer in your project Use switch SW 17 on the DE2 board as the s input switches SW _o as the X input and SWi5 g as the Y input Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG 7 0 3 Include in your project the required pin assignments for the DE2 board As discussed in Part I these assignments ensure that the input ports of your VHDL code will use the pins on the Cyclone II FPGA that are connected to the SW switches and the output ports of your VHDL code will use the FPGA pins connected to the LEDR and LEDG lights 4 Compile the project 5 Download the compiled circuit into the FPGA chip Test the functionality of the eight bit wide 2 to 1 multiplexer by toggling the switches and observing the LEDs Part III In Figure 2 we showed a 2 to 1 multiplexer that selects between the two inputs x and y For this part consider a circuit in which the output m has to be selected from five inputs u v w x and y Part a of Figure 4 shows how we can build the required 5 to 1 multiplexer by using four 2 to 1 multiplexers The circuit uses a 3 bit select input 595150 and implements the truth table shown in Figure 4b A circuit symbol for this multiplexer is given in part c of the figure Recall from Figure 3 that an eight bit wide 2 to 1 multiplexer can be built by using eight instances of a 2 to 1 multiplexer Figure 5 applies this concept to define a three bit wide 5 to 1 multiplexer It contains thre
185. put appears on LEDGO and the state FFs appear on LEDR8 0 ENTITY partl IS PORT SW IN STD LOGIC VECTOR 1 DOWNTO 0 KEY IN STD LOGIC VECTOR 0 DOWNTO 0 LEDG OUT STD LOGIC VECTOR 0 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 8 DOWNTO 0 END partl ARCHITECTURE Behavior OF parti IS COMPONENT flipflop PORT D Clock Resetn Setn IN STD LOGIC Q OUT STD LOGIC END COMPONENT SIGNAL Clock Resetn w Zz STD LOGIC SIGNAL y 0 Y D STD LOGIC VECTOR 8 DOWNTO 0 BEGIN Clock lt KEY 0 Resetn lt SW 0 w lt SW 1 Y D 0 lt Q s UO flipflop PORT MAP Y D 0 Clock 1 Resetn y Q 0 Y D 1 lt y Q 0 OR y Q 5 OR y Q 6 OR y Q 7 OR y Q 8 AND NOT w Ul flipflop PORT MAP Y D 1 Clock Resetn 1 y Q 1 Y D 2 lt y Q 1 AND NOT w U2 flipflop PORT MAP Y D 2 Clock Resetn 1 y Q 2 Y D 3 lt y Q 2 AND NOT w U3 flipflop PORT MAP Y D 3 Clock Resetn 1 y Q 3 Y D 4 lt y Q 3 OR y Q 4 AND NOT w U4 flipflop PORT MAP Y D 4 Clock Resetn 1 y Q 4 Y D 5 lt y Q 0 OR y Q 1 OR y Q 2 OR y Q 3 OR y Q 4 AND w U5 flipflop PORT MAP Y D 5 Clock Resetn 1 y Q 5 Y D 6 lt y Q 5 AND w U6 flipflop PORT MAP Y D 6 Clock Resetn 1 y 0 6 Y D 7 lt y Q 6 AND w U7 flipflop PORT MAP Y D 7 Clock Resetn 1
186. r VHDL code instead of the subtractions shown in lines 9 and 18 The intent of this part of the exercise is to examine the effects of relying more on the VHDL compiler to design the circuit by using IF ELSE statements along with the VHDL gt and operators Perform the following steps 1 Create a new Ouartus II project for your VHDL code Use the same switches lights and displays as in part V Compile your circuit 2 Use the Ouartus II RTL Viewer tool to examine the circuit produced by compiling your VHDL code Com pare the circuit to the one you designed in Part V 3 Download your circuit onto the DE2 board and test it by trying different values for numbers A Ap and B Bo Part VII Design a combinational circuit that converts a 6 bit binary number into a 2 digit decimal number represented in the BCD form Use switches SW5_pg to input the binary number and 7 segment displays HEX and HEXO to display the decimal number Implement your circuit on the DE2 board and demonstrate its functionality Copyright 2006 Altera Corporation partl vhd Display digits from 0 to 9 on the 7 segment displays toggle switches as inputs LIBRARY i eee USE ieee std logic 1164 all ENTITY pa PORT END partl rti IS SW LEDR HEX3 HEX2 HEX1 HEXO r ARCHITECTURE Structure OF partl IS COMPON POR td E EGIN LEDR lt ENT bcd7seg T B IN STD LOGIC V H OUT STD LOGIC VEC ND CO
187. racters shown in Table 2 Connect the outputs of the five multiplexers to the 7 segment displays HEX4 HEX3 HEX2 HEXI and HEXO 3 Include the reguired pin assignments for the DE2 board for all switches LEDs and 7 segment displays Compile the project 4 Download the compiled circuit into the FPGA chip Test the functionality of the circuit by setting the proper character codes on the switches SW14 0 and then toggling SW17 15 to observe the rotation of the characters Part VI Extend your design from Part V so that is uses all eight 7 segment displays on the DE2 board Your circuit should be able to display words with five or fewer characters on the eight displays and rotate the displayed word when the switches SW17 15 are toggled If the displayed word is HELLO then your circuit should produce the patterns shown in Table 3 SW17 SWig SW15 Character pattern 000 H E L L O 001 H E L LO 010 H E L L O 011 H E L L O 100 E L L O H 101 LLO H E 110 L O H E L 111 O H E LL Table 3 Rotating the word HELLO on eight displays Perform the following steps 1 Create a new Quartus II project for your circuit and select as the target chip the Cyclone II EP2C35F672C6 2 Include your VHDL entity in the Quartus II project Connect the switches SW 17 15 to the select inputs of each instance of the multiplexers in your circuit Also connect SW 14 0 to each instance of the multiplexers as required to produce the patterns of character
188. registers and use SW as a synchronous active low reset input Write VHDL code in the style shown in Figure 3 for your finite state machine Compile your VHDL code download it onto the DE2 board and test the circuit Part VI For this part you are to modify your circuit from Part V so that it no longer requires manually applied clock pulses Your circuit should scroll the word HELLO such that the letters move from right to left in intervals of about one second Scrolling should continue indefinitely after the word HELLO scrolls off the left side of the displays it should start again on the right side Write VHDL code for the ticker tape circuit and create a Quartus II project for your design Use the 50 MHz clock signal CLOCK 50 on the DE2 board to clock the FSM and pipeline registers and use KEY as a synchronous active low reset input Write VHDL code in the style shown in Figure 3 for your finite state machine and ensure that all flip flops in your circuit are clocked directly by the CLOCK 50 input Do not derive or use any other clock signals in your circuit Compile your VHDL code download it onto the DE2 board and test the circuit Part VII Augment your design from Part VI so that under the control of pushbuttons KEY 2 and KEY the rate at which the letters move from right to left can be changed If KEY is pressed the letters should move twice as fast If KEY is pressed the rate has to be reduced by a factor of 2 Note that the
189. regn R U6 regn PORT MAP DOUT Li EDR 15 DOWNTO 0 lt LI EDG lt 000000000 seg cs lt seg scroll PORT MAP DOUT DIN lt inst mem q R 15 DOWNTO Rin Clock 0 l WHEN ADDR 15 DOWNTO 12 Clock HEX7 HEX6 HEX5 6 DOWNTO 0 12 0001 0010 ED reg cs AND W Clock ED reg 15 DOWNTO 0 ELSE ADDR 2 DOWNTO 0 ELSE LED reg tots Vetus HEX4 HEX3 H seg cs AND W EX2 H EX1 H EXO Page 2 seg7 scroll vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all Data written to registers RO to R7 are sent to the HEX digits ENTITY seg7 scroll IS PORT Data IN STD LOGIC VECTOR 0 TO 6 Addr IN STD LOGIC VECTOR 2 DOWNTO 0 Sel Resetn Clock IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END seg scroll ARCHITECTURE Behavior OF seg7 scroll IS COMPONENT regne GENERIC n INTEGER 7 PORT R IN STD LOGIC VECTOR n 1 DOWNTO 0 Clock Resetn E IN STD LOGIC Q OUT STD LOGIC VECTOR n 1 DOWNTO 0 END COMPONENT SIGNAL RO R1 R2 R3 R4 R5 R6 R7 STD LOGIC VECTOR 0 TO 6 SIGNAL RO addr R1 addr R2 addr R3 addr R4 addr R5 addr R6 addr R7 addr STD LOGIC BEGIN RO addr lt 1 WHEN Addr 000 ELSE 0
190. ress IN STD LOGIC VECTOR 4 DOWNTO 0 clock IN STD LOGIC data IN STD LOGIC VECTOR 7 DOWNTO 0 wren IN STD LOGIC 1 q OUT STD LOGIC VECTOR 7 DOWNTO 0 END COMPONENT COMPONENT hex7seg PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Clock Write STD LOGIC SIGNAL Address STD LOGIC VECTOR 4 DOWNTO 0 SIGNAL Dataln DataOut STD LOGIC VECTOR 7 DOWNTO 0 BEGIN Clock lt KEY 0 Write lt SW 17 Dataln lt SW 7 DOWNTO 0 Address lt SW 15 DOWNTO 11 instantiate LPM module module ramlpm address clock data wren q m32x8 ramlpm PORT MAP Address Clock Dataln Write DataOut display the data input data output and address on the 7 segs digit0 hex7seg PORT MAP DataOut 3 DOWNTO 0 HEX0 digitl hex7seg PORT MAP DataOut 7 DOWNTO 4 HEX1 HEX2 lt 1111111 blank HEX3 lt 1111111 blank digit4 hex7seg PORT MAP Dataln 3 DOWNTO 0 HEX4 digit5 hex7seg PORT MAP DataIn 7 DOWNTO 4 HEX5 digit6 hex7seg PORT MAP Address 3 DOWNTO 0 HEX6 digit7 hex7seg PORT MAP 000 amp Address 4 HEX7 LEDG 0 lt Write END Behavior LIBRARY ieee USE ieee std logic 1164 all the B input blanks the display when B 1 ENTITY hex7seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6
191. riate logic expressions in your design to produce the output z Make a Quartus II project for your design and implement the circuit on the DE2 board Use the switches and LEDs on the board in a similar way as you did for Parts I and II and observe the behavior of your shift registers and the output z Answer the following question could you use just one 4 bit shift register rather than two Explain your answer Part IV We want to design a modulo 10 counter like circuit that behaves as follows It is reset to 0 by the Reset input It has two inputs w and wo which control its counting operation If w wo 00 the count remains the same If w wo OL the count is incremented by 1 If w wo 10 the count is incremented by 2 If wiw 11 the count is decremented by 1 All changes take place on the active edge of a Clock input Use toggle switches SW gt and SW for inputs w and wo Use toggle switch SW as an active low synchronous reset and use the pushbutton KEY as a manual clock Display the decimal contents of the counter on the 7 segment display HEXO 1 Create a new project which will be used to implement the circuit on the DE2 board 2 Write a VHDL file that defines the circuit Use the style of code indicated in Figure 3 for your FSM 3 Include the VHDL file in your project and compile the circuit Simulate the behavior of your circuit Assign the pins on the FPGA to connect to the switches and the 7 segment display Re
192. s EDA Tool Settings Optimization Technique Auto Global Options MAX Devices Only Compilation Process Settings Speed V Analysis amp Synthesis Settings gir F VHDL Input Verilog HDL Input C Area Iv Default Parameters A Synthesis Netlist Optimizations Create debugging nodes for IP cores Fitter Settings I IV Auto Open Drain Pins Assembler IV Auto ROM Replacement I Timing Analyzer 3 E Design Assistant IV Auto RAM Replacement J Auto Shift Register Replacement SignalT ap II Logic Analyzer Ww Iv Power Up Don t Care Logic Analyzer Interface DSP Block Balancing ae v SignalProbe Settings Simulator Settings State Machine Processing Minimal Bits v PowerPlay Power Analyzer Settings Software Build Settings Restructure Multiplexers Auto SZ HardCopy Settings PowerPlay power optimization Normal compilation HDL Message Level Level X More Settings Description Specifies the processing style used to compile a state machine You can use your own User Encoded style or select One Hot Minimal Bits or Auto Compiler selected encoding Cancel Figure 4 Specifying the state assignment method in Quartus II Part HI For this part you are to implement the sequence detector FSM by using shift registers instead of using the more formal approach described above Create VHDL code that instantiates two 4 bit shift registers one is for recog nizing a sequence of four Os and the other for four 1s Include the approp
193. s shown in Table 3 Hint for some inputs of the multiplexers you will want to select the blank character Connect the outputs of your multiplexers to the 7 segment displays HEX7 HEXO 3 Include the required pin assignments for the DE2 board for all switches LEDs and 7 segment displays Compile the project 4 Download the compiled circuit into the FPGA chip Test the functionality of the circuit by setting the proper character codes on the switches SW14 0 and then toggling SW17 15 to observe the rotation of the characters Copyright 2006 Altera Corporation partl vhd Page 1 LIBRARY ieee USE ieee std logic 1164 all Simple module that connects the SW switches to the LEDR lights ENTITY partl IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 red LEDS END partl ARCHITECTURE Structure OF partl IS BEGIN LEDR lt SW END Structure part2 vhd Implements eight 2 to 1 multiplexers inputs SW7 0 represent the 8 bit input X and SW15 8 represent Y m SW17 selects either X or Y to drive the output LEDs outputs LEDR17 0 show the states of the switches LEDG7 0 shows the outputs of the multiplexers LIBRARY ieee USE ieee std_logic_1164 a11 Simple module that connects the SW switches to the LEDR lights ENTITY part2 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0
194. s the window in Figure 8 To specify the connection to your DE2 board click on the Setup button on the right side of the screen In the window in Figure 9 select the USB Blaster hardware and then close the Hardware Setup dialog In System Memory Content Editor eo 3 000000 000016 2x8 IT 27 72 22 DE 79 TE 9 33 97 39 72 37 QT 9 9 TP TV Y 9W PI MT03T312021230 02007230 JTAG Chain Configuration JTAG ready 2 x Hardware USB Blaster USB 0 y Setup Device 21 EP2C35 0x020B40DD v Scan Chain File E 27 VP Ve 27 Fr 77 3 Instance 0 32x8 Word 0x000000 Bit 0x000007 Figure 8 The In System Memory Content Editor window Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware USB Blaster USB 0 Available hardware items Hardware fewer Pot Add Hardware ByteBlaster USB Blaster Figure 9 The Hardware Setup window Instructions for using the In System Memory Content Editor tool can be found in the Quartus II Help A simple operation is to right click on the 32x8 memory module as indicated in Figure 10 and select Read Data from In System Memory This action causes the contents of the memory to be displayed in the bottom part of the window You can then edit any of the displayed values by
195. seg PORT MAP B HEX4 digit 3 hex7seg PORT MAP 0000 HEX3 digit 2 hex7seg PORT MAP 0000 HEX2 partl vhd digit 1 hex7seg PORT MAP P 7 DOWNTO 4 HEX1 digit 0 hex7seg PORT MAP P 3 DOWNTO 0 HEXO END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY fa IS PORT a b ci IN STD LOGIC Sy CO OUI STD LOGIC END fa ARCHITECTURE Structure OF fa IS SIGNAL a xor b STD LOGIC BEGIN a xor b lt a XOR b S lt a xor b XOR ci co lt NOT a xor b AND b OR a xor b AND ci END Structure LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN Sp 0 E 5 1 SE 4 2 eis 3 PROCESS hex BEGIN CASE hex IS WHEN 0000 gt display lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 WHEN 1001 gt display lt 0001100 WHEN 1010 gt display lt 0001000 WHEN 1011 gt display lt 1100000 WHEN 1100 gt display
196. splay lt 0000001 WHEN 0001 gt display lt 1001111 WHEN 0010 gt display lt 0010010 WHEN 0011 gt display lt 0000110 WHEN 0100 gt display lt 1001100 WHEN 0101 gt display lt 0100100 WHEN 0110 gt display lt 1100000 WHEN 0111 gt display lt 0001111 WHEN 1000 gt display lt 0000000 part5 vhd WHEN 1001 WHEN 1010 WHEN 1011 WHEN 1100 WHEN 1101 WHEN 1110 WHEN OTH END CASE END PROCESS END Behavior ERS displ disp displ disp displ disp disp Lay Lay Lay Lay Lay Lay Lay 0001100 0001000 1100000 0110001 1000010 0110000 0111000 r E p F F E Page 4 ramlpm mif Page 1 EPTH 32 IDTH 8 DDRESS RADIX HEX ATA RADIX BIN ONTENT EGIN D OQ U gt SEO 00 00000000 01 00000001 02 00000010 03 00000011 04 00000100 05 00000101 06 00000110 07 00000111 08 00001000 09 00001001 OA 00001010 OB 00001011 0C 00001100 OD 00001101 OE 00001110 OF 00001111 10 00010000 11 00010001 12 00010010 13 00010011 14 00010100 15 00010101 16 00010110 LT 900101115 18 00011000 19 00011001 1A 00011010 1B 00011011 1C 00011100 ID 3 000211014 1E 00011110 1F 00011111 END part6 vhd Page 1 This code implements a pseudo
197. splays the characters HEX7 HEX5 are set to blank ENTITY part5 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 HEX7 HEX6 HEX5 HEX4 OUT STD LOGIC VECTOR 0 TO 6 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part5 ARCHITECTURE Structure OF part5 IS COMPONENT mux 3bit 5tol PORT S V W X Y IN STD LOGIC VE M OUT STD LOGIC V END COMPONENT COMPONENT char seg PORT C IN STD LOGIC VECTOR 2 DOWNTO 0 Display OUT STD LOGIC VECTOR 0 TO 6 END COMPONENT SIGNAL Ch Sel Ch1 Ch2 Ch3 Ch4 Ch5 Blank STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL H4 Ch H3 Ch H2 Ch H1 Ch HO Ch STD LOGIC VECTOR 2 DOWNTO 0 BEGIN LEDR lt SW E Q OR 2 DOWNTO 0 CTOR 2 DOWNTO 0 el Ch Sel lt SW 17 DOWNTO 15 Ch1 lt SW 14 DOWNTO 12 Ch2 lt SW 11 DOWNTO 9 Ch3 lt SW 8 DOWNTO 6 Ch4 lt SW 5 DOWNTO 3 Ch5 lt SW 2 DOWNTO 0 Blank lt 111 used to blank a 7 seg display see module char 7seg instantiate mux 3bit 5tol S Ur V W X Y M M4 mux 3bit 5tol PORT MAP Ch Sel Chl Ch2 Ch3 Ch4 Ch5 H4 Ch M3 mux 3bit 5tol PORT MAP Ch Sel Ch2 Ch3 Ch4 Ch5 Ch1 H3 Ch M2 mux 3bit 5tol PORT MAP Ch Sel Ch3 Ch4 Ch5 Ch1 Ch2 H2 Ch M1 mux 3bit 5tol PORT MAP Ch Sel Ch4 Ch5 Chl Ch2 Ch3 HL Ch MO
198. stem CD and in the University Program section of Altera s web site The procedure for making pin assignments is described in the tutorial Quartus II Introduction using VHDL Design which is also available from Altera It is important to realize that the pin assignments in the DE pin assignments csv file are useful only if the pin names given in the file are exactly the same as the port names used in your VHDL entity The file uses the names SW 0 SW 17 and LEDR 0 LEDR 17 for the switches and lights which is the reason we used these names in Figure 1 note that the Quartus II software uses square brackets for array elements while the VHDL syntax uses round brackets LIBRARY ieee USE ieee std_logic_1164 all Simple module that connects the SW switches to the LEDR lights ENTITY part1 IS PORT SW IN STD LOGIC VECTOR 17 DOWNTO 0 LEDR OUT STD LOGIC VECTOR 17 DOWNTO 0 red LEDs END parti ARCHITECTURE Behavior OF part1 IS BEGIN LEDR lt SW END Behavior Figure 1 VHDL code that uses the DE2 board switches and lights Perform the following steps to implement a circuit corresponding to the code in Figure 1 on the DE2 board 1 Create a new Ouartus II project for your circuit Select Cyclone II EP2C35F672C6 as the target chip which is the FPGA chip on the Altera DE2 board 2 Create a VHDL entity for the code in Figure 1 and include it in your project 3 Include in your project the reguired pin assign
199. t pipe6 HEX7 lt pipe END Behavior LIBRARY ieee USE ieee std 1 ENTITY regne PORT END regne R C Q IS logic 1164 all lock Resetn IN STD LOGIC VECTOR 6 DOWNTO 0 IN STD LOGIC OUT STD LOGIC VECTOR 6 DOWNTO 0 ARCHITECTURE Behavior OF regne IS BEGIN PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Q lt OTHERS gt 1 ELSE O lt R END IE END IE END PROCESS END Behavior Page 2 part6 vhd LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all scrolls the word HELLO across the 7 seg displays An FSM inserts the display values into a pipeline that drives the 8 displays each display is driven for about 1 second before changing to the next character inputs 50 MHz clock KEYO is reset input outputs 7 seg displays HEX7 HEXO ENTITY part6 IS PORT lt KEY IN STD LOGIC VECTOR 0 DOWNTO 0 CLOCK 50 IN STD LOGIC HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEXO OUT STD LOGIC VECTOR 0 TO 6 END part6 ARCHITECTURE Behavior OF part6 IS COMPONENT regne GENERIC N integer 7 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Clock Resetn E STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT SIGNAL Clock Resetn Tick STD LOG
200. ter to display mE SW210 Char 000 m 0071 E 0 1 0 ATA m g 1 1 oO 1 0 O Blank T p m Blank 1 10 1 Blank 111 Blank outputs LEDR2 0 show the states of the switches HEXO displays the selected character LIBRARY ieee USE ieee std logic 1164 all ENTITY part4 IS PORT SW LEDR HEXO END part4 IN STD LOGIC VEC OUT STD LOGIC VEC OUT STD LOGIC VEC ARCHITECTURE Structure OF part4 IS SIGNAL C BEGIN LEDR SW C 2 DOWNTO 0 the following equations 0 5 1 se 6 4 2 3 Cannonical HEX0 0 lt NOT NOT C 2 HEXO 1 lt NO NOT C 2 HEX0 2 lt NO NOT C 2 HEXO 3 lt NO NOT C 2 NOT C 2 HEX0 4 lt NO NOT C 2 NOT C 2 HEXO 5 lt NO NOT C 2 NOT C 2 HEXO 6 lt NO NOT C 2 e END Structur STD_LOGIC_V lt SW 2 DOWNTO 0 OR 2 DOWNTO 0 OR 2 DOWNTO 0 OR 0 TO 6 ECTOR 2 DOWNTO 0 describe display functions in SOP form NOT C 2 AND NOT C 1 AND C 0 AND C 1 AND C 0 T NOT C 2 AND NOT C 1 AND NOT C AND C 1 AND C 0 T NOT C 2 AND NOT C 1 AND NOT C AND C 1 AND C 0 T NOT C 2 AND NOT C 1 AND C 0 AND C 1 AND NOT C 0 O
201. termediate multiplexers to produce the 5 to 1 multiplexer M 0 m 1 is for M 1 and m 2 is for M 2 SIGNAL S U V W X Y M STD LOGIC VECTOR 2 DOWNTO 0 M is the 3 bit 5 to 1 multiplexer BEGIN 342 so 0 lt SW 17 DOWNTO 15 U lt SW 2 DOWNTO 0 V lt SW 5 DOWNTO 3 W lt SW 8 DOWNTO 6 X lt SW 11 DOWNTO 9 Y lt SW 14 DOWNTO 12 LEDR lt SW 5 to 1 multiplexer for bit 0 m 0 1 lt NOT S 0 AND U 0 OR S 0 AND V 0 m 0 2 lt NOT S 0 AND W 0 OR S 0 AND X 0 m 0 3 lt NOT S 1 AND m 0 1 OR S 1 AND m 0 2 M 0 lt NOT S 2 AND m 0 3 OR S 2 AND Y 0 5 to 1 multiplexer output 5 to 1 multiplexer for bit 1 m 1 1 lt NOT S 0 AND U 1 OR S 0 AND V 1 m 1 2 lt NOT S 0 AND W 1 OR S 0 AND X 1 m 1 3 lt NOT 5 1 AND m 1 1 OR 5 1 AND m 1 2 M 1 lt NOT S 2 AND m 1 3 OR S 2 AND Y 1 5 to 1 multiplexer output 5 to 1 multiplexer for bit 2 m 2 1 lt NOT S 0 AND U 2 OR S 0 AND V 2 m 2 2 lt NOT S 0 AND W 2 OR S 0 AND X 2 m 2 3 lt NOT S 1 AND m 2 1 OR 5 1 AND m 2 2 M 2 lt NOT S 2 AND m 2 3 OR S 2 AND Y 2 5 to 1 multiplexer output LEDG 2 DOWNTO 0 lt M END Structure part4 vhd Implements a circuit that can display five characters on a 7 segment display inputs SW2 0 selects the let
202. the shaded columns in Figure 1c In each row of the multiplier AND gates are used to produce the summands and full adder modules are used to generate the required sums az a 03 a 4 dg qd a b 0 b b3 y Po Ps P4 P3 P2 P Po Figure 2 An array multiplier circuit Use the following steps to implement the array multiplier circuit 1 2 Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2 board Generate the reguired VHDL file include it in your project and compile the circuit Use functional simulation to verify that your code is correct Augment your design to use switches SW11 3 to represent the number A and switches SW o to represent B The hexadecimal values of A and B are to be displayed on the 7 segment displays HEX6 and HEX4 respectively The result P A x B is to be displayed on HEX and HEXO Assign the pins on the FPGA to connect to the switches and 7 segment displays as indicated in the User Manual for the DE2 board Recompile the circuit and download it into the FPGA chip Test the functionality of your design by toggling the switches and observing the 7 segment displays Part II Extend your multiplier to multiply 8 bit numbers and produce a 16 bit product Use switches SW 15 to represent the number A and switches SW o to represent B The hexadecimal values of A and B are to be displayed on the 7 segment displays HEX7 6 and HEX5
203. the code produces the circuit with four 4 LUTs depicted in Figure 3b R Clk a Using one 4 input lookup table for the RS latch Qa Q Clk b Using four 4 input lookup tables for the RS latch Figure 3 Implementation of the RS latch from Figure 1 Create a Ouartus II project for the RS latch circuit as follows 1 Create a new project for the RS latch Select as the target chip the Cyclone II EP2C35F672C6 which is the FPGA chip on the Altera DE2 board 2 Generate a VHDL file with the code in Figure 2 and include it in the project 3 Compile the code Use the Ouartus II RTL Viewer tool to examine the gate level circuit produced from the code and use the Technology Viewer tool to verify that the latch is implemented as shown in Figure 3b 4 Create a Vector Waveform File vwf which specifies the inputs and outputs of the circuit Draw waveforms for the R and S inputs and use the Quartus II Simulator to produce the corresponding waveforms for R g S g Qa and Ob Verify that the latch works as expected using both functional and timing simulation Part II Figure 4 shows the circuit for a gated D latch Qa Q Qb Figure 4 Circuit for a gated D latch Perform the following steps 1 Create a new Quartus II project Generate a VHDL file using the style of code in Figure 2 for the gated D latch Use the keep directive to ensure that separate logic elements are used to implement the signals R S
204. ts D and Clock as indicated in Figure 6 Use functional simulation to obtain the three output signals Observe the different behavior of the three storage elements LIBRARY ieee USE ieee std logic 1164 all ENTITY latch IS PORT D Clk IN STD LOGIC Q OUT STD LOGIC END latch ARCHITECTURE Behavior OF latch IS BEGIN PROCESS D CIk gt BEGIN IF Clk 1 THEN Q lt D END IF END PROCESS END Behavior Figure 7 A behavioral style of VHDL code that specifies a gated D latch Part V We wish to display the hexadecimal value of a 16 bit number A on the four 7 segment displays H EX7 4 We also wish to display the hex value of a 16 bit number B on the four 7 segment displays HE X3 0 The values of A and B are inputs to the circuit which are provided by means of switches SW 15 0 This is to be done by first setting the switches to the value of A and then setting the switches to the value of B therefore the value of A must be stored in the circuit 1 Create a new Ouartus II project which will be used to implement the desired circuit on the Altera DE2 board 2 Write a VHDL file that provides the necessary functionality Use KEY as an active low asynchronous reset and use KEY as a clock input Include the VHDL file in your project and compile the circuit 3 Assign the pins on the FPGA to connect to the switches and 7 segment displays as indicated in the User Manual for the DE2 board 4 Recompile t
205. typing over them To actually write the new value to the RAM right click again on the 32x8 memory module and select Write All Modified Words to In System Memory Experiment by changing some memory values and observing that the data is properly displayed both on the 7 segment displays on the DE2 board and in the In System Memory Content Editor window Instance Manager T EM E Ready to acquire x Index Instance ID Status width Depth Type Mode ENO 328 8 RAM ROM _ Read Write JTAG Chain Configuration TAG r Hardware USB Blaster USB 0 0x0208 Not running Read Data from In System Memory Continuously Read Data from In System Memory F6 Write Data to In System Memory FZ a 328 000000 22 22 27 27 22 22 27 7 I 000016 22 22 22 22 22 Import Data from File Export Data to File Instance Status Help Figure 10 Using the In System Memory Content Editor tool Part VII For this part you are to modify your circuit from Part VI and Part IV to use the IS61LV25616AL SRAM chip instead of an M4K block Create a Ouartus II project for the new design compile it download it onto the DE2 boards and test the circuit In Part VI you used a memory initialization file to specify the initial contents of the 32 x 8 RAM block and you used the In System Memory Content Editor tool to read and modify this data This approach can be used only for the memory resources inside the
206. uctions such as an addition or subtraction take more than one clock cycle to complete because multiple transfers have to be performed across the bus The control unit uses the two bit counter shown in Figure I to enable it to step through such instructions The processor starts executing the instruction on the DIN input when the Run signal is asserted and the processor asserts the Done output when the instruction is finished Table 2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1 Note that the only control signal asserted in time step O is IR in so this time step is not shown in the table T T Ts mv lo RYout RXin Done mvi 5 DIN out RXin Done add Ij RX out Ain RY outs Gin Gout RXin Done sub 13 RX out Ain RY out Gin Gout RXin AddSub Done Table 2 Control signals asserted in each instruction time step Part I Design and implement the processor shown in Figure I using VHDL code as follows 1 Z Create a new Quartus II project for this exercise Generate the required VHDL file include it in your project and compile the circuit A suggested skeleton of the VHDL code is shown in parts a and b of Figure 2 and some subcircuit entities that can be used in this code appear in parts c and d Use functional simulation to verify that your code is correct An example of the output produced by a functional simulation for a correctly
207. utput to LEDR o 3 Compile your project 4 Use the Technology Viewer to examine the D flip flop circuit and use simulation to verify its correct oper ation 5 Download the circuit onto the DE2 board and test its functionality by toggling the D and Clock switches and observing the Q output Part IV Figure 6 shows a circuit with three different storage elements a gated D latch a positive edge triggered D flip flop and a negative edge triggered D flip flop D D Q Q Clock cik Q Qa hia Q Q a Circuit Clock b Timing diagram Figure 6 Circuit and waveforms for Part IV Implement and simulate this circuit using Ouartus II software as follows 1 Create a new project 2 Write a VHDL file that instantiates the three storage elements For this part you should no longer use the keep directive that is the VHDL ATTRIBUTE statement from Parts I to III Figure 7 gives a behavioral style of VHDL code that specifies the gated D latch in Figure 4 This latch can be implemented in one 4 input lookup table Use a similar style of code to specify the flip flops in Figure 6 3 Compile your code and use the Technology Viewer to examine the implemented circuit Verify that the latch uses one lookup table and that the flip flops are implemented using the flip flops provided in the target FPGA 4 Create a Vector Waveform File vwf which specifies the inputs and outputs of the circuit Draw the inpu
208. wizard to create a memory that has one 16 bit wide read data port and is 32 words deep The first screen of the wizard is shown in Figure 5 Since this memory has only a read port and no write port it is called a synchronous read only memory synchronous ROM Note that the memory includes a register for synchronously loading addresses This register is reguired due to the design of the memory resources on the Cyclone II FPGA account for the clocking of this address register in your design To place processor instructions into the memory you need to specify initial values that should be stored in the memory once your circuit has been programmed into the FPGA chip This can be done by telling the wizard to initialize the memory using the contents of a memory initialization file MIF The appropriate screen of the MegaWizard Plug In Manager tool is illustrated in Figure 6 We have specified a file named inst mem mif which then has to be created in the directory that contains the Ouartus II project Use the Ouartus II on line Help to learn about the format of the MIF file and create a file that has enough processor instructions to test your circuit 3 Use functional simulation to test the circuit Ensure that data is read properly out of the ROM and executed by the processor 4 Make sure your project includes the necessary port names and pin location assignments to implement the circuit on the DE2 board Use switch SW17 to drive the processor s Run
209. ws the Quartus II synthesis tools to modify the single port RAM as needed to allow reading and writing of the memory by the In System Memory Content Editor tool Click OK to exit from the Settings window S 4 Compile your code and download the circuit onto the DE2 board Test the circuit s operation and ensure that read and write operations work properly Describe any differences you observe from the behavior of ettings part Category General Files User Libraries Current Project Device Timing Requirements amp Options EDA Tool Settings Compilation Process Settings Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Netlist Optimizations E Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap II Logic Analyzer SignalProbe Settings Simulator PowerPlay Power Analyzer Settings Software Build Settings HardCopy Settings Default Parameters Specify the default settings for the parameters used in your project Assignments in design files or assignments made in the Assignment Editor will override these defaults Parameter Name EYCLONEIL SAFE WRITE Delete Default setting RESTRUCTURE Delte Existing parameter settings Change Name Setting CYCLONEILSAFE W RESTRUCTURE Figure 7 Setting the CYCLONEII SAFE WRITE parameter the circuit in Part V 5 Select Tools gt In System Memory Content Editor which open
210. x7seg PORT MAP Count 15 DOWNTO 12 HEX3 digit2 hex7seg PORT MAP Count 11 DOWNTO 8 HEX2 digitl hex7seg PORT MAP Count 7 DOWNTO 4 HEX1 digit0 hex7seg PORT MAP Count 3 DOWNTO 0 HEX0 END Behavior LIBRARY ieee USE ieee std logic 1164 all ENTITY hex seg IS PORT hex IN STD LOGIC VECTOR 3 DOWNTO 0 display OUT STD LOGIC VECTOR 0 TO 6 END hex7seg ARCHITECTURE Behavior OF hex7seg IS BEGIN PROCESS hex BEGIN CASE hex IS zzzzzzzzzzzzzzz FJ Ei Bd Bd Ed Bd Ed Ed Ed Bd Ed Bd Bd Ed Bd E z z 0000 0001 0010 001 0100 010 O110 011 0 1000 10 PR GOO END CASE END PROCESS END Behavior 00 0 1110 OTHERS disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay lay 0000001 1001111 0010010 0000110 1001100 0100100 1100000 0001111 0000000 0001100 0001000 1100000 0110001 1000010 0110000 0111000 i F E pF F r F F F F Fr Fr r p Page 2 part4 vhd uses a 1 digit bcd counter enabled at 1Hz LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all ENTITY part4 IS PORT CLOCK 50 HEXO END part4
211. y the contents of the RAM on the 7 segment displays 1 Make a new Ouartus II project which will be used to implement the desired circuit on the DE2 board 2 Create another VHDL file that instantiates the ramlpm module and that includes the reguired input and output pins on the DE2 board Use toggle switches SW7_o to input a byte of data into the RAM location identified by a 5 bit address specified with toggle switches SW15 11 Use SW17 as the Write signal and use KEY as the Clock input Display the value of the Write signal on LEDG Show the address value on the 7 segment displays HEX7 and HEX6 show the data being input to the memory on HEXS and HEX4 and show the data read out of the memory on HEX1 and HEXO 3 Test your circuit and make sure that all 32 locations can be loaded properly Part III Instead of directly instantiating the LPM module we can implement the reguired memory by specifying its struc ture in the VHDL code In a VHDL specified design it is possible to define the memory as a multidimensional array A 32 x 8 array which has 32 words with 8 bits per word can be declared by the statements TYPE mem IS ARRAY 0 TO 31 OF STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL memory array mem In the Cyclone II FPGA such an array can be implemented either by using the flip flops that each logic element contains or more efficiently by using the M4K blocks There are two ways of ensuring that the M4K blocks will be used One is to use an
212. ync Clock Resetn 1 Write address Page 1 part5 vhd Page R5 regne GENERIC MAP N gt 8 PORT MAP SW 7 DOWNTO 0 Clock Resetn 1 Dataln sync R6 regne GENERIC MAP N gt 8 PORT MAP Dataln sync Clock Resetn 1 Dataln one second cycle counter Create a 1Hz 5 bit address counter A large counter to produce a 1 second approx enable PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN slow count lt slow count 1 END IF END PROCESS the read address counter PROCESS Clock BEGIN IF Clock EVENT AND Clock 1 THEN IF Resetn 0 THEN synchronous clear Read address lt OTHERS gt 0 ELSIF slow count 0 THEN Read address lt Read address 1 END IF END IF END PROCESS instantiate LPM module module ramlpm clock data rdaddress wraddress wren q m32x8 dual ramlpm PORT MAP Clock Dataln Read address Write address Write DataOut display the data input data output and address on the 7 segs digit0 hex7seg PORT MAP DataOut 3 DOWNTO 0 HEX0 digitl hex7seg PORT MAP DataOut 7 DOWNTO A HEX1 digit2 hex7seg PORT MAP Read address 3 DOWNTO 0 HEX2 digit3 hex7seg PORT MAP 000 amp Read address 4 HEX3 digit4 hex7seg PORT MAP DataIn 3 DOWNTO 0 HEX4 digit5 hex7seg PORT MAP DataIn 7 DOWNTO 4 HEX5 digit6 hex7seg PORT MAP Wr
213. your processor and external memory account for the fact that the memory has registered input ports as we discussed for Figure 8 3 Create another Ouartus II project that instantiates the processor memory module and register shown in Fig ure 8 Use the Quartus II Mega Wizard Plug In Manager tool to create the ALTSYNCRAM memory module Follow the instructions provided by the wizard to create a memory that has one 16 bit wide read write data port and is 128 words deep Use a MIF file to store instructions in the memory that are to be executed by your processor 4 Use functional simulation to test the circuit Ensure that data is read properly from the RAM and executed by the processor 5 Include in your project the necessary pin assignments to implement your circuit on the DE2 board Use switch SW to drive the processor s Run input use KEY for Resetn and use the board s 50 MHz clock signal as the Clock input Since the circuit needs to run properly at 50 MHz make sure that a timing constraint is set in Quartus II to constrain the circuit s clock to this frequency Read the Report produced by the Quartus II Timing Analyzer to ensure that your circuit operates at this speed if not use the Quartus II tools to analyze your circuit and modify your VHDL code to make a more efficient design that meets the 50 MHz speed requirement Also note that the Run input is asynchronous to the clock signal so make sure to synchronize this input using flip
Download Pdf Manuals
Related Search
Related Contents
Home Accents Holiday 7407036HO Instructions / Assembly Thermador PCS364GL User's Manual Montage- Bedienungsanleitung 1762-IN013A-DE-P, MicroLogix™ 1200 Thermoelement/mV English - Dilon Diagnostics Istruzioni per l`uso 1391B-ES AC Servo Controller User Manual Document Update Nobo Clip Frame 700x1000mm Impulse Series Camera Copyright © All rights reserved.