EGG 1232 Microlok Interlocking Simulation System Design Gudielines
Contents
1. iv NON VITAL ADDRESS SILOS tf EIGHTUNF IELD MISS CONFIGURATION SAT CB CPU 10 MKII MASTER MP1 M36 S M35L M38 19200 37 19200 19200 19200 19200 13200 13200 19200 13200 19200 1 MS M8 M11 M14 M18 CPU 1 CPU 2 CPU 3 CPU 4 CPU 5 CPU 6 9600 9600 9600 9600 9600 C2 LOCATION ADDRESS M MISS CePatch PORT NUMBER M16 M19 M22 M25 M28 P mer sob e VITAL ADDRESS M MASTER S SLAVE MKII MICROLOKII RailCorp Issued November 2012 UNCONTROLLED WHEN PRINTED Page 36 of 38 Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 6 3 Appendix C MISS Circuits2. mmm 1 n mun ers mmm o 7 d mum o EST 96MAU2R 96CT 96SAU2R 96CT 96SAU3R EM K 96SAU3R 91MBUR 91SBUR 91ATUR 94SBU2R 94MB U2R 91AT Table 8 Track Timer Indications Track Timer lights are provided in the vicinity of the associated track circuit This indication displays a red light when the relevant timing function bit is set An example of the logic associated with the Track Timer Indication is as shown in Figure 19 GridMap Bitmap Color Displays Eed In CH az Default Bitmap Logic Element NIB Logic Element substitute When i set Substitute Zi When GEET JR is sel Figure 19 Track Timer Indication 2 5 3 13 Miscellaneous Indications and Controls Miscellaneous indications and controls may be provided on the Control Panel as required Particular consideration will need to be given to the interfaces of the interlocking boundaries and to how these interfaces are to be tested or simulated Miscellaneous indications such as Power Supplies Lamp Failure or Hot Standby indications may be required on the Control Panel for testing purposes All miscellaneous indication bits however may also be tested using the I O Display Screen as discussed further in the document 2 5 4 UO Display Screen When MISS is running sub windows associated with each Bit List file are available to be opened and interrogated during testing These windows display the status of all the input RailCorp Page 27 of 38 I
3. The testing shall be performed using the approved Signalling Plan Control Tables Circuit Books and other documentation deemed necessary to complete the work Particular attention shall be made to the signalling interfaces to ensure the required input and output functionality has been provided and tested The Test Engineer shall liaise with the Design Engineer prior to commencement of testing to ensure familiarisation with the testing configuration provided and the systems in place for diagnostic support Where the MISS design allows the design integrity testing may include the aspect sequence testing This testing may not remove the requirement to complete a formal aspect sequence test on site Any testing that cannot be carried out utilising MISS shall be carried out during the signal commissioning The testing Engineer shall ensure these tests are incorporated into the commissioning test plan 9 RUNNING MISS 5 1 Folder Structure The files created for a MISS project are to be provided in a certain structure both for consistency and correct operation of MISS This folder structure to be followed on the MISS computer is as follows e My Computer e Local Disk C MISS folder contains a folder for each MISS project o Project Location Name folder contains the following files and 2 folders m Control Panel mdb m Track Panel mdb m Misscom mdb o Microlok Data folder contains all Microlok data o Location Name folder
4. g um rncelssentcssaudipea eaeteecseenecescecee 5 2 2 Hardware Configuration esmas incisos icon barrica tiro 6 2 2 1 A 6 2 2 1 1 Microlok Master slave Style Configurations 0000nnnnnnn00annnnnnnnneannnnnnnnnn 6 2 2 1 2 Microlok Peer to Peer Configurations oooonccncccononccnncnnnanconnononancononenonanenos 6 2 2 2 eo A A 6 2 2 2 1 RailCorp Testing Facltes 7 2 3 Software Confguraton sise 7 2 3 1 EE 7 2 3 2 Solis ON FIE RE 8 232A ai 8 AN MISSCOM A nn 8 23 20 CONTROL PANELMOAb cio 8 2 2 TRACK PANEL IE eee 10 2925 PORTEINFO Visions arteria 10 23 2 6 E ern Be 11 PP 19 2 3 3 Ato CAIN Ul NOV Mees acess TRO 14 2 3 3 1 Signal Auto Configuration Funchons 14 2 3 3 2 Trainstop Auto Configuration Funchons 14 2 3 3 3 Track Auto Configuration Funchons 15 2 3 3 4 Points Auto Configuration Funchons 15 2 3 4 Hot Standby Configurations 16 2 4 Miscellaneous Te 17 2 5 Screen Design Trakplan eXe tee geet Eeer 18 2 5 1 Ca T T 18 2 5 2 BFE MT Im 18 2 5 3 EE EE ee 19 POM MEU Ge 19 A MEE C Eie Tm 20 2039 el EE 21 See Dile CNRC 21 E COOP ATOS me ee en doce 22 2 5 3 0 Points Control ei ue e 22 2 5 3 7 OCS Route Control Funchons eene 23 2 5 3 8 NX Route Control Functions ss 24 220 909 E ele A ue Wed Lal E 25 2 5 3 10 Automatic Re clearing ss 25 20311 TECNICOS Se nina ten dessinateur 26 RailCorp Page 3 of 3
5. contains the following files Bit List csv Port Info csv RailCorp Page 31 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 ePatch csv Date log Automatically created by MISS Date alm Automatically created by MISS 5 2 Shortcut MISS exe Error Objects cannot be created from editing field codes A shortcut is generally provided on the desktop of the MISS computer to run the MISS software for a particular project With the project being provided with a relevant name and folders having been created for that project an existing shortcut on the desktop can be copied and modified as required The shortcut would then be required to be name changed and the 2 fields Target and Start in will also need to be modified The full Target description is C Program Files Union Switch amp Signal Pty Ltd Microlok Interlocking Simulation System Miss exe Project Name The Start in description is C MISS Project Name Stevetown Properties General shortcut Compatibility 5 3 Alarms 4 An alarm file is automatically IN stevetown created to record the alarms are generated while MISS is Target type Application running This file can be Target location Microlok Interlocking Simulation System referred to during the initial Target king Simulation
6. 27 4HDR 27 4DR D D 6 OUT 27 AYNP 5 D 27 4VR 27 AYNRLINK D D 7 OUT 27 AVRP 6 D 27 4VR 27 AVRRLINK D D 8 OUT 102HZ 7 D D D g OUT 102HDZ 8 D D D 10 OUT 25 7 HZ g D D D 11 OUT L17 1AT 10 1 D D 12 OUT L19 80T 11 1 D D 13 OUT 27 AAT 12 1 D D 14 OUT 25 7 BT 13 1 D D 15 OUT SPARE 14 0 D D 16 QUT SPARE 15 D D D 17 IN 27 AHR D D D 18 IN 27 4HDR 2 D D D 18 IN 27 ADR 3 D D D 20 IN 27 AVR 4 O D D 21 IN 27 4VCSR 5 D D D 22 IN 25 5ABTPR B 0 D D 23 IN 26 7 ATPR 7 D D D 24 NM 26 1ABTPR 8 D D D 25 IN SPARE g D D D 26 NM SPARE 10 D D D 27 Figure 7 Bit List file The Direction field defines the bit as an input received from the MISS computer or an output sent to the MISS computer The Bit Name field defines the bit name usually taken from the Microlok data and is the name to be used if required in the MISS panel logic The Bit Offset field defines the order of the bits the bit offset is started from 1 for both the inputs and outputs The Bit Value field defines the output bit value as 1 or 0 at start up Input bits must have a value of O The Auto Config Bit field allows logic to be provided for the setting or clearing of that bit value This field requires standard Microlok Boolean syntax any bits defined in the Bit List files may be used Note that the Auto Config Bit field does not ese exactly the same Boolean syntax as the other values in that it must not contain spaces and does not support exclusive or XOR
7. Design Guidelines EGG 1232 30 07 04 REV 05 MMUNICATI BS O STANDARD IEC CONNECTOR ePATCH RS422 TYPE 2 EIN UNIT 4 RJ45 NOT CONNECTED CONFIG Ll gt 41612 RJ45 eent 1 lt El CPUI 41618 RJ45 2 gt lt Fe 41618 RJ45 CPUe 41618 RJ45 2 gt lt E4 41612 RJ45 CPU3 41618 RJ45 2 B lt E6 DIN41612 RJ45 1 3 E7 CPUA DIN41612 RJ45 2 lt _E8 5 eX Zw L Q DIN41612 RJ45 xx m 1 4 E9 D CPUS DIN41612 RJ45 2 gt lt E10 41618 RJ45 1 E E11 CPU6 41618 RJ45 e Fie 4 IDC40 TXD RXD RIBBON DIN41612 RJ45 EXP I P 4 gt lt E13 B d IDC40 CPU7 ETS ZCTS RIBBON DIN41612 RJ45 gt 2 E14 EXP I P TXD RXD DIN41612 RJ45 1 gt 4 E15 EXP OZP CPUS r DIN41612 RJ45 cig RTS CTS 2 a DN EXP Dap MISS ports 49 64 CONT FROM SHT 0005 NOTE ALL RJ45 CONNECTOR WIRING TO 568A STANDARD UNLESS OTHERWISE STATED RailCorp Issued November 2012 UNCONTROLLED WHEN PRINTED Page 38 of 38 Version 1 2
8. E9 V V CPU13 PC port PC port 183 DINA1612 RJAS A gt lt E10 DIN41612 RJ45 DIN41612 RJ45 3 E E10 3 E E10 CPUA CPUS DIN41612 RJ45 DIN41612 RJ45 DIN41612 RJ45 3 gt lt SU A E lt E11 4 lt E11 CPU14 DIN41612 RJ45 4 gt lt Ele RJ45 RJ45 Ges i RJ45 RJASH HS DC An DC A0 CYCLADES PORT 5 lt on CYCLADES PORT 11 DARDO RIBBU un Apr RIBBO PC poet 7 EXP I P PC port 13 EXP I P gt EXP PRE 7 N PC 3 E13 pInatele P Ruas RJ45 RJASH DC40 IDC40 4 gt lt E13 RTS CTS CYCLADES PORT 12 gt lt E13 RTS CTS RIBBD RTS CTS RIBBD CPUS EXP I P PC port 14 EXP I P E14 EXP I P DIN41612 RJ45 L 4 gt lt E14 IDC40 ei gie ESE RJ45 S Gen DC A0 4 IDC40 TXD RXD RIBBON Hos TXD RXD RIBBO TXD RXD RIBBD EXP D P d PC port 15 EXP D P e E15 EXP D P A RJ45 RJ45 Q CONT UN CYCLADES PORT 6 lt Ela IDC40 E15 DC40 A DC40 SHT 0006 Re 8 T RTS CTS RIBBON RTS CTS RIBBD Ex RTS CTS RIBB J p p CYCLADES PORT 7 Mig a E16 EXP O 7 E16 EXP HZ EXP OZP PC port 9 m MISS ports 1 16 MISS ports 17 32 MISS ports 33 48 2 B amp B 42eCFCR RS422 RS232 CONVERTOR DBeS CONECTURS EACH SIDE NOTE ALL RJ45 CONNECTOR WIRING TU 568A STANDARD UNLESS OTHERWISE STATED RailCorp Issued November 2012 UNCONTROLLED WHEN PRINTED Page 37 of 38 Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS
9. System Miss exe STEVETOWN MISS set up of the project this information helps to identify any e Start in ICSMISSSSTEVETDVNS errors or aids fault finding during the design process Shortcut key None The Alarms file name Run Normal window includes the date that the file IS Was created and a new file is created for the new day to record any alarms raised Find Target Change Icon Advanced during that day 5 4 Logging Cancel A log file is automatically created when MISS is running This file can be referred to during the simulation testing to view the change of status of the data bits within the Bit List files The MISS log may be accessed during testing by selecting the Data Log View from the Tools menu The log file includes the bit name the status of the bit and the time of the status change The file name includes the date that the file was created and a new file is created for each new day that MISS is running RailCorp Page 32 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 6 APPENDIX 6 1 Appendix A Application Data Modified for MISS MICROLOK I PROGRAM SP1 LOCATION INTERFACE LOCAL BOARD OUT SLOT1 ADJUSTABLE ENABLE 1 TYPE OUT16 OUTPUT HOR 1VCSR 416ALZR SPARE SPARE SPARE SPARE SPARE SPARE SPAR
10. sub section of the data is to be instated The simulation data provided for the serial link in the COMM sub section is then to be commented out The application data is then to be checked as per the relevant procedures prior to the commissioning 4 TESTING PROCEDURES 4 1 Introduction The MISS allows for the simulation and testing of the Microlok ll application data This process is to check the integrity and to evaluate the performance of the interlocking logic RailCorp Page 29 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 Additional testing will be required prior to or during the signal commissioning to prove a complete through test and correct operation of the field equipment and the control of this equipment from the Control System including all interfaces to the interlocking A separate desk top computer running the Microlok Il tools software is available to be used during testing if there is a requirement to interrogate the bit status of any boolean bit or serial data bit within the application logic of any Microlok I CPU card Additional computers may be provided if there is a requirement to interrogate more than one CPU card at any time The MISS I O Display Screen may be referred to if there is a requirement to interrogate the status of any MISS bit as defined in the Bit List files Ref
11. yellow indication for shunt route set Substitute Bitmap Substitute Color arid ap Bitmap Color Displays in EI az Default Bitmap Logic Element Calor Logic Element Substitute When i set Substitute n When 3BATK Is set Bitmap Logic Element Color Logie Element Substitute when iz sel Substitute C When 86TK 3EMAUR 81 MEUAR ts set Bitmap Lagic Element Color Logic Element Substitute when Ir oc Substitute 3 when 9BATK SBSALIR BTSBUMBE is set Figure 18 Track Indications The indications for the tracks over Points do not flash with loss of point detection An example of the logic associated with the Track Circuit Indications is as follows Intermediate bits are required where track route lights are to be provided These intermediate bits are defined in the Control Panel Bit List file The intermediate bit names shall follow the typical NX panel circuits as shall be the logic associated with these bits An example of the logic associated with the Track route light indications is in Table 8 Bit Direction Bit Name Off PL AutoConfigBit S Value RailCorp Page 26 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 5 3 12 EXERCITIUM icc e pe PETERS E Tra ir seni And ali 2r eO 4 substitute Bitmap Substitute Color
12. 00 8 None 1 DISABLE 4 PCSIM CONTROL PANEL master 999 15 19200 8 None 1 DISABLE 5 PCSIM ATRICS slave 50 4 9600 8 None 1 DISABLE E PCSIM SP27 4 V master 93 5 9600 8 Mone 1 DISABLE PCSIM SP26 8 master an 6 9600 8 None 1 DISABLE 8 PCSIM SP118 master 86 7 9600 8 None 1 DISABLE 9 PCSIM SP107 Vmaster 83 a 9600 8 None 1 DISABLE 10 PCSIM sP91 master 8n g 9600 8 None 1 DISABLE 11 PCSIM SP81 V master 76 10 9600 8 None 1 DISABLE 12 PCSIM SP69 V master 73 11 9600 8 None 1 DISABLE 13 PCSIM SP61 master 70 12 9600 8 None 1 DISABLE 14 PCSIM SP55 LEIGHTONFIELD master 43 13 9600 8 None 1 DISABLE Figure 5 PORT INFO csv file RailCorp Page 10 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 The From Processor field is generally always PCSIM simulation PC The To Processor field includes the names of the Bit List files that have been created for the simulation configuration The entry ePatch is a standard requirement The Protocol field describes the communication protocol of that serial link For example Vmaster defines a Microlok Master protocol and master defines a Genisys Master protocol ePatch defines the protocol for the ePatch link Note that the Protocol field is the protocol used at the OTHER end of the link Vmaster means the Microlok on the other en
13. 30 07 04 REV 05 MLOK III SERIAL COMMUNICATIONS INTERCONNECTIONS SHI 0005 REG N ATSEF 000326 STANDARD STANDARD STANDARD IEC CONNECTOR IEC CONNECTOR IEC CONNECTOR ePATCH RS232 TYPE 3 PIN ePATCH RS232 TYPE 3 PIN ePATCH RS232 TYPE 3 PIN UNIT 1 UNIT 2 UNIT 3 RJ45 RJ45 1 l gt RJ45 E ze RJ45 240V CYCLADES PORT 1 lt CONFIG ePatch gt 240V GPO 2 NOT CONNECTED lt CONFIG gt 240V GPO 3 NOT CONNECTED 4 CUNFIG CPO 4 PC port 3 m E DIN41612 RJ45 DIN41612 RJ45 DIN4 Be E RJ45 3 E E1 3 E E1 1 2 0 El CPUI CPU6 CPUS DIN41612 RJA4S DIN41612 RJ45 DIN41612 rn RJ45 4 E lt lt Ee 4 Ee e E 0 2 0 Ee DIN41612 RJ45 RJ45 RJ45 1 DIN41612 RJ45 CYCLADES PORT 2 lt E3 CYCLADES PORT 8 gt lt ES 3 gt lt E3 PC port 4 PC poet 105 CPU10 DIN41612 RJ45 DIN41612 RJ45 DIN41612 RJ45 4 gt lt E4 3 lt E4 3 E E4 CPUe CPU7 RJ45 RJ45 DIN41612 RJ45 DIN41612 RJ45 4 lt ES 4 E ES 3 EN A ES CPUIL DIN41612 RJ45 RJ45 RJ45 1 RJ45 RJ45 1 4 gt lt E6 CYCLADES PORT 3 lt E6 CYCLADES PORT 9 gt lt E6 PC port 5 PL port 10 DIN41612 RJ45 DIN41612 RJ45 DIN41612 RJ45 3 gt lt ET 3 E E7 3 E E7 CPUIe CPU3 CPU8 DIN41612 RJ45 DIN41612 RJ45 A DIN41612 RJ45 in 4 lt E8 i 4 E E E8 4 E E8 Es ES Y ES Y ES M Zt be Z ER o Z YM RS lt FD Es lt x Es S G e DIN41612 RJ45 a x a RJ45 RJ45 No RJ45 RJ45 1 v 3 gt lt E9 0 CYCLADES PORT 4 gt lt ES be CYCLADES PORT 10 gt lt
14. 8 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 5 3 12 Track Timer Indications iii 27 2 5 3 13 Miscellaneous Indications and Controls sannnannennnannonnnennoennennnennnennne 27 2 5 4 D A 27 3 MICROLOK IT APPLICATION DAT A 1 eee nhu uuu na uuu nhuuauhuuau nuu aauuun 28 3 1 EL M uu 28 3 2 Application Data Modifications for MIr 29 3 2 1 Jet GSI GM IPPO oo oie 29 3 2 2 Pre commMmissioning asec eels Paice van 29 4 TESTING PROCEDURES setxerkskEKKKEKKKEKRKEENKER NEEN KEEERKERN NEEN REENKKEENRKEER nana nan KEEN nnne 29 4 1 Tags elt eo PE pad EN E 29 4 2 EEN RENE TN TI 30 4 3 ATOS SAS RTT 30 5 RUNNING MISS RETE DE S IET 31 5 1 FOIOS SUCIO una TN Xm 31 5 2 SOC MISS EXE j E 32 5 3 AE ER 5 4 LOGOO ENT TETTE E mm 32 6 APPENODIXA qem 33 6 1 Appendix A Application Data Modified for MIGG 33 6 2 Appendix B MISS Configuration Example nnne 36 6 3 Appendix C MISS CGreuts nennen nnn nnns nnn nnn nsn nana nnn nnn 37 RailCorp Page 4 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Inte
15. E SPARE SPARE SPARE f BOARD IN_SLOT2 ADJUSTABLE ENABLE 1 TYPE IN16 Ges INGPZ 1VNP 1VRP 420HZ 420HDZ 1ALSZ 1 3ALSZ 407FT 420AT 12DT 120VPOP BOARD NVIN32 SLOT3 ADJUSTABLE ENABLE 1 TYPE NV IN32 NV INPUT RailCorp Page 33 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 TEMPORARY SERIAL DATA FOR MISS COMMUNICATIONS LINK PORT 2 LINK COMM2 ADJUSTABLE ENABLE 1 PROTOCOL MICROLOK MASTER FIXED PORT 2 ADJUSTABLE POINT POINT 1 ADJUSTABLE BAUD 19200 FIXED STOPBITS 1 FIXED PARITY NONE FIXED KEY ON DELAY 12 FIXED KEY OFF DELAY 12 ADJUSTABLE MASTER TIMEOUT 100 MSEC ADJUSTABLE POLLING INTERVAL 50 MSEC ADJUSTABLE STALE DATA TIMEOUT 4 SEC ADDRESS 33 ADJUSTABLE ENABLE 1 OUITIPUT JEseses 2 2 POHI2OUIPUIS 1HDR 1VCSR 416ALZR SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE INPUT 25222222222 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 POHT 2 INPUTS 1HDP 1NGPZ 1VNP 1VRP 420HZ 420HDZ 1ALSZ 1 3ALSZ 407FT 420AT 12DT 120VPOP A DLC A MAIN A DIV B DLC RailCorp Page 34 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signal
16. ED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 3 2 4 TRACK PANEL mdb The TRACK PANEL mdb file is created where the testing configuration requires a Track oide Panel for the simulation of the trackside equipment and where required the indication of signal aspects etc This file can be modified using the TrakPlan exe program An example of a Track Side Panel is shown in Figure 4 ET TOSERTON LEIGHTONFIELD SBDIT e NORMAL e NORMAL MORAL REVERSE REVERSE REVERSE EOL EOL EOL Figure 4 Track Side Panel 2 3 2 5 PORT INFO csv The PORT INFO csv file comma separated variable file provides a description of the serial port connections and protocols for each of the links that are required in the simulation configuration The information required in this file is taken directly from the Microlok data and the MISS configuration drawing designed for the interlocking under test An example of an interlocking MISS configuration drawing can be found in the appendix An example of this file is shown in Figure 5 EN File Edit View Insert Format Tools Data Window Help T B E E A A E NA A A AA From Processor To Processor Protocol Station Address PC Port Number Baud Rate Data Bits Parity Stop Bits Rts Mode 1 2 PCSIM ePatch ePatch 399 3 S600 8 None 1 DISABLE 3 PC8IM TRACK PANEL master 999 14 192
17. Engineering Guideline Signals EGG 1232 MICROLOK INTERLOCKING SIMULATION SYSTEM MISS DESIGN GUIDELINES Version 1 2 Issued November 2012 Owner Chief Engineer Signals and Control Systems Approved by Warwick Allison Authorised Paul Szacsvay Chief Engineer by Principal Engineer Signals amp Control Systems Signal Research amp Development Disclaimer E Er 2 O O E St D S O LLI This document was prepared for use on the RailCorp Network only RailCorp makes no warranties express or implied that compliance with the contents of this document shall be sufficient to ensure safe systems or work or operation It is the document user s sole responsibility to ensure that the copy of the document it is viewing is the current version of the document as in use by RailCorp RailCorp accepts no liability whatsoever in relation to the use of this document by any party and RailCorp excludes any liability which arises in any manner by the use of this document Copyright The information in this document is protected by Copyright and no part of this document may be reproduced altered stored or transmitted by any person without the prior consent of RailCorp v M y ALVA Transport e NSW RailCo ro UNCONTROLLED WHEN PRINTED Page 1 of 38 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 Document control ES NE Summa
18. L DETECTION will set EguMRLIMK RES Emulates Pushbutton I Menu String Logic Bit BREAK REVERSE DETECTION will set E amp VRRLINK ME Emullates Pushbutton Menu String Logic Bit MAKE REVERSE DETECTION will set SEVRRLINK HISA Emulates Pushbutton I Figure 11 Example of menu logic for Train Stop NOTE The train stop normal or reverse detection functions are toggled setting the link bit true or false depending on the menu item selected 2 5 3 3 Signals The true form of the signal can be shown on the Track Panel including the appropriate aspects This allows the testing to include full aspect sequence simulation CSN The logic behind each signal aspect indication is as per the standard signal operating logic utilising the signal control bits from the Bit List files When using the trackplan csv file the correctness of the logic needs to be reviewed by a correspondence test before using for the function test 2 5 3 4 Tracks Track indications are shown on the Track Panel as grey for track un occupied and red for track occupied depending on the status of the track circuit bit When clicking on a section of the track a drop down menu will appear to provide the option to pick or drop that particular track circuit This will toggle the track circuit output bit Route lights are not shown on the Track Panel RailCorp Page 21 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Gu
19. RailCorp Page 13 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 The Off Delay and On Delay fields are used to create a slow to clear or slow to set functions if they are required to be applied to that bit For example point setting 2 3 3 Auto Configuration The Auto Configuration function is applied to various functions to allow for the simulation of the operation and indication of the field equipment The control bits normally used as outputs to operate field equipment relays are used in the Auto Config Bit field of the Bit List files to manipulate the inputs back into the signal interlocking automatically simulating the operation of the field equipment Where there is a requirement for a disconnect point or link for testing purposes such as breaking Points detection etc an intermediate bit is created to simulate a link These bits are defined in a separate Bit List file Track Panel csv It is recommended that a separate Bit List file be created for both the Track Panel and the Control Panel 2 3 3 1 Signal Auto Configuration Functions To simulate the operation of relay driven signals the signal control bits that would normally drive the output relays are used in turn around logic and brought back into the interlocking Data is provided in the Auto Config Bit field for each inp
20. S Track Panel produced for a Hot Standby configuration would be as normal due to the testing only being required to single slave processors RailCorp Page 16 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 4 Miscellaneous Tips a Ensure the same version of Microsoft Access running on the MISS computer is used when creating the required database files Otherwise there will need to be a requirement to convert the databases before MISS will run MS ACCESS 97 It is recommended that the Design Engineer copies and modifies the MISS files of an existing project rather than designing from new blank files The file extension mdb should be included on the file names specified in the MISSCOM mdb file Consider assigning CPS STATUS to LED 8 where not already used in the Microlok Il application data to allow the tester to more easily confirm the CPU functionality Consider assigning the MISS port status bits to LEDs 1 4 as provided in the Microlok II application data The Track Plan panel would normally be designed first and copied and renamed to the Control Panel Copying the track panel to make the control panel does not save very much time in preparation One must return to the control map for every grid map item and change the logic This presents the risk that some of the en
21. bits are created in the Track Panel Bit List file as shown in Table 3 OUT HABRINK ji JD eet S Table 3 NOTE The Bit Value is set at 1 due to the link or switch being normally closed The manipulation or opening of this link is carried out via a drop down menu on the Track Panel 2 3 3 3 Track Auto Configuration Functions To simulate the operation of Track Circuits the input bit that is brought into the interlocking is manipulated or opened and closed via a drop down menu on the Track Panel The entry in the Bit Value field is set at 1 to ensure all tracks are simulated as un occupied at the start up of the interlocking The data is created in the Bit List file as shown in Table 4 Bit Bit On Off or BT IL LD et EC our 08 II 0 O0 our mu t j In Table 4 2 3 3 4 Points Auto Configuration Functions To simulate the operation of Points the control bits that would normally drive the Points output relays NWR RWR amp IR are used in turn around logic and brought back into the interlocking Data is provided in the Auto Config Bit field for each input associated with the Points as shown in Table 5 Bit Bit On Off GUT S25aNKR o 82SNWZRGESANUNK O o OUT Loan Jo 225RWZR 225ARLNK 0 0 OUT 22senkR o 225NWZR225BNLINK o 0 on zeserkr o 22sRWZR 22sBRLINK O o on eso fr In Table 5 To simulate the operation of the EOL the input b
22. command Drop down menus may be created to allow the manipulation of the bits defined in the Bit List files This is carried out utilising the Control Map command Text may be placed on the screen using the Text command The text may be inserted in any font style size or colour as required Clicking the mouse on the screen and selecting the Text command will allow the placement of text on the screen Note that the text will be placed from the point that the mouse was clicked on the screen and aligned to the left 2 5 2 Bitmaps Bitmaps are drawings of individual symbols that may be placed on a grid of the Track Panel or Control Panel screen design Multiple bitmaps may be placed on the same grid to form a more complex symbol This is referred to as a Grid Map For example a signal symbol on the Track Panel is made up of separate bitmaps one bitmap for each signal lamp and others for the signal post etc The bitmaps are created and modified using the Microsoft Paint software The MISS bitmaps are stored in a separate folder Bitmaps on the simulation computer The bitmap drawings are generally numbered from 100 1000 and any spare number may be used for a new bitmap drawing It is essential that Design Engineers do not create duplicate bitmaps or bitmaps with identical filenames for different projects For this reason it is proposed that a master bitmap folder be provided on the network to ensure only standard bitmaps are used a
23. d is the Master end of a vital link i e the MISS slave The same situation applies for the non vital links Normally the interlocking is a Genisys slave of the control system so the PORT INFO needs to state slave even though the MISS is the Master of the link The Station Address field describes the serial link address for that particular serial link as provided in the Microlok data Where an address of 999 is shown this number may be any number below 999 that has not been used in the simulation configuration The PC Port Number field describes the MISS PC port number used for that communication link Port numbers 1 and 2 may not be used and port number 3 is generally always used for the ePatch units Reference would need to be made to the MISS circuits for the port numbers available for use These circuits can be found in the appendix The Baud Rate Data Bits Parity and Stop Bits fields describes the appropriate value for each communication link Where the link is not related to the Microlok data directly a value of 9600 or 19200 may be used The Rts Mode is generally set to DISABLE for all communication links 2 3 2 6 ePatch csv The ePatch csv file defines the ePatch port connections for each serial link in the testing configuration that is required to pass through the ePatch units It is recommended that a MISS configuration drawing as shown in the appendix is produced for each interlocking under test Thi
24. e commence button changes to steady white when the correct track and locking conditions are true and the normal lock relay de engerised If the finish button operation is not successful the flashing outline of the commence button is extinguished The following figure shows an example of a push button layout on a NX route panel Figure 15 Example of a push button layout on a NX route panel RailCorp Page 24 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 The colour of the symbols on the buttons configured for Commence and Finish functions are shown with the following colours when set to true e Yellow for Down Main direction routes e Blue for Up Main routes e Hed for shunt routes 2 5 3 9 Signal Indications A Signal repeater is provided for each controlled signal on the Control Panel The signal repeater will indicate red or green depending on the value of the indication bits received from the interlocking The signal repeater may flash red ALSR function or flash green LPR function where required Note that a signal should show grey when no indication is received 2 5 3 10 Automatic Re clearing An A button is provided adjacent to the signal repeaters for the control an indication where the Auto Re clearing function is required Clicking on this A bu
25. e is no requirement for this panel the field shall be blank Once a project folder is created the files to which MISSCOM refers are located within that folder This prevents them from becoming confused with the files of other projects If default names are used for all files MISSCOM mdb never requires to be edited However should it be necessary to edit the MISSCOM mdb file Microsoft ACCESS 97 must be used for the editing 2 3 2 3 CONTROL PANEL mdb The CONTROL PANEL mdb file is created where the testing configuration requires a Control Panel for the sending of controls and displaying of indications to simulate the final Control Panel This file can be modified using the TrakPlan exe program NOTE Where the final Control Panel is ATRICS it would be preferred that an ATRICS PC is used when testing the interlocking during FAT However where the ATRICS design is not available the MISS Control Panel will be required RailCorp Page 8 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 An example of a Control Panel is shown in Figure 3 o V 75BT TO SEFTON CHESTER 53 x LEIGHTOMFIELD 360T LE ME MEE As LE ME MEE As VR ME MEL Ee 1 ka ka ka e 215 POINTS 216 POINTS 218 POINTS 220 POINTS Figure 3 Control Panel RailCorp Page 9 of 38 Issued November 2012 UNCONTROLL
26. er to section 2 5 5 for further information related to the I O Display Screen The MISS log file may also be referred to during testing if required Refer to section 5 4 for further information related to the MISS logging Reference shall be made to the FAT Plan that is produced for the project to confirm the specific tests to be carried out Prior to the commencement of the testing the Design Engineer is to carry out the set to work process to ensure the correct configuration and settings required for simulation Following the set to work check the through testing and design integrity testing shall be carried out 4 2 Set to Work The set to work shall be carried out by the Design Engineer and include the following tests e All CPU cards are loaded with the correct executive version and correct version of application data e All serial links are functioning as required and as per the configuration drawing e All routes correctly set and indicated with signals clearing for each route e All signals correctly cancel and automatically normalise if required e All points can be operated normal reverse and free and are correctly indicated and detected normal and reverse e he signal Auto Re clearing controls and indication function correctly where provided e hecorrect route lights and track occupied indications are displayed when a train is simulated through each route e Miscellaneous testing of various unique or unusual interlock
27. he application program to the Microlok Il central processing unit CPU card For the comprehensive procedures to create the complete Microlok Il application program reference should be made to the US amp S Microlok II System Application Logic Programming Guide SM 6800D manual The application logic is to be designed in accordance with the Signal Design Quality Procedures QSDP16 Microlok File Control Microlok Data Design and Factory Acceptance Testing QSDP31 Retesting of Microlok Data QSDP33 Checking of Microlok Circuits and Data Designs RailCorp Page 28 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 As the MISS cubicle does not include the facility to install the final Microlok cardfile configuration the application data is required to be modified accordingly The application data is to be modified with minimal change allowing the application data to be simulated as closely as possible to the final configuration To achieve this the Interface section of the application data is only to be modified The Design Engineer preparing the application data shall establish the proposed method of testing the application data prior to the commencement of the initial data design Where the MISS is to be utilised for testing the data the initial design is to include the provisions for MISS te
28. ideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 5 3 5 Control Panels Where there is a requirement to simulate the Signal Box control panel for design testing a Control Panel may be designed using the Trakplan exe software The design of the panel for a completely new interlocking should allow for indication and control in a similar way to a conventional OCS panel When there is a project that is required to interface with an existing NX panel the design should be made to simulate the NX style of panel These panels should include the layout of the track arrangements points signal repeaters track timers platforms and track circuits Additional indications can be provided such as warnings or alarms auto re clearing and hot standby functions 2 5 3 6 Points Control Functions Points detection Points in Transit and Points Free are indicated on the Control Panel for each set of Points A yellow indication is displayed when the detection is made a green indication is displayed when the Points are free and a red indication is displayed when the Points are in transit Note the Points transit indication does not flash 225 POINTS An arrow in the centre of the indication set shows the position of the Points Key or the last command that was sent to be displayed By clicking on the arrow a drop down menu will be displayed which gives the option to set the Points normal reverse or cen
29. ing functions or features for example points sequencing level crossing and warning light operation The set to work tests need not be comprehensive and shall not be considered proof of the integrity of the interlocking 4 3 Through Testing The through testing shall be carried out to ensure individual functions are correctly passed through the serial links and the application data The through testing shall include the following e Correspond all controls from the Control System serial link that are inputs into the signal interlocking to the relevant function RailCorp Page 30 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 e Correspond all outputs from the signal interlocking to the field equipment e Correspond all inputs from the field equipment to the relevant functions within the signal interlocking or to the Control System serial link Generally this testing is carried out by the Design Engineer and the tests are recorded in the FAT document for that project Design Integrity Testing to Control Tables The design integrity testing shall be carried out in accordance with the Inspection and Testing of New and Altered Signalling Works Inspection and testing procedures SPG 0711 4 An accredited Engineer that is independent to the interlocking design process shall carry out this testing
30. it List file The command Find and Replace can be used to separate the I O bits into RailCorp Issued November 2012 Page 17 of 38 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 separate lines For example find and replace with l control L will replace the comma separation with line returns k A blank bitmap can be placed in position on the screen design for the route indication aspects of signals and this blank bitmap is substituted with a route indication character when the bit Shunt HR is true 2 5 Screen Design Trakplan exe 2 5 1 General The screen design is to be carried out using the Trakplan exe program This software may be used to create and modify the Track Panel and or Control Panel depending on the testing configuration and requirements The screen design may be carried out on any desk top PC or laptop loaded with the required software The screen design includes the production of a screen layout using individual bitmap drawings These are symbols created specifically for this purpose A grid may be turned on or off as required to aid the screen design Logic may be applied to individual symbols on the screens to either change the colour or shape of the symbol depending on the value of the bit assigned to that symbol This is carried out utilising the Indication Map
31. it that is brought into the interlocking is manipulated or opened and closed via a drop down menu on the Track Panel The entry in the Bit Value field is set at 1 to ensure the EOL is simulated as closed at the start up of the interlocking RailCorp Page 15 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 To simulate the operation of the Points Isolation Relay the control bit that would normally drive the IR output relay is used in turn around logic and brought back into the interlocking NOTE The logic in the Auto Config Bit field for the NKR and RKR functions include link intermediate bits These bits are used to enable the breaking of the Point detection for testing purposes These bits are created in the Track Panel Bit List file as shown in Table 6 ivit OUT ESNUN h 0 am mue D sa Fois E Table 6 NOTE The Bit Value for the ANLINK and ARLINK is set at 1 to simulate the links or switches being normally closed The manipulation or opening of these links is carried out via a drop down menu on the Track Panel Similarly for the BNLINK and BRLINK An On Delay of 3000 milliseconds has been applied to the NWZR and RWZR bits to simulate the transition of the points operation to be more closely simulated NOTE that it is necessary to test each end of each de
32. lation System MISS Design Guidelines EGG 1232 Note When commencing a new simulation known versions of MISS exe and Trakplan exe shall be used and the version recorded in the test results The latest versions should be used where possible to maximise the features and functionality 2 3 2 Configuration Files 2 3 2 1 General The following configuration and data base files are required to run the simulation system MISSCOM mdb CONTROL PANEL mdb TRACK PANEL mdb PORT_INFO csv ePATCH csv BIT LIST csv 2 3 2 2 MISSCOM mdb The MISSCOM mdb file is a data base file that includes a table called MissStatn Tbl is used An example of this table is shown in Figure 2 EB File Edit View Insert Format Records Tools Window Help Station ID Station Name Db File Name Mimic Db Name Track Db Name m 1 LEIGHTONFIELD ANYNAME mdb LEIGHTONFIELDCP MDB LEIGHTONFIELDTP MDB Ed AutoMurmber x Figure 2 MissStatn table Generally the Station ID field will always remain as 1 The Station Name field is to be the name of the interlocking location The Db File Name field is generally not used but requires an entry in the field so ANYNAME mdb is recommended The Mimic Db Name field contains the name of the data base file created for the Mimic Control Panel If there is no requirement for this panel the field shall be blank The Track Db Name field contains the name of the data base file created for the Track Panel If ther
33. m allows the testing of the functional characteristics of each interlocking in an office test room environment It also allows for the evaluation of the performance of the interlocking logic The system includes a simulation computer running the MISS software and two specially designed Microlok II cardfiles There is no provision for Microlok Il I O cards in the MISS hardware so there is a requirement to modify the Microlok II application logic of the vital processors to re route the I O from the physical cards to the serial communication ports to allow this I O to be simulated RailCorp Page 5 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 2 2 2 1 2 2 1 1 2 2 1 2 2 2 2 Wherever possible turn around logic is to be provided in the MISS configuration files to allow data bits to be automatically generated from an output to an input as required This document describes a level of simulation functionality that is required for all projects Reduced functionality such as lack of coloured route set lines or tabulated IO instead of geographically arranged I O are not acceptable Additionally MISS data is to be suitable for control and replay purposes as required by QSDP68 Hardware Configuration General Microlok Master slave Style Configurations The MISS hardware includes a simulati
34. menu will be displayed where the Train Stop normal or reverse detection can be opened or closed An example of the indication logic for the Train Stop is as shown in Figure 10 T substitute Brtmap Sobstitote Color Delete DE Cancel ex AA GridM ap Bitmap Color CO Displays In D as Default Bitmap Logic Element Color Logie Element Substitute When EB VR BEVRRLINK el Substitute E iter IEBVR GEVRRLINK is set Bitmap Logic Element Color Logic Element substitute When ls sel Substitute EE EMELINE Is set Bitmap Logic Element Colar Logic Element Substitute When is sel Substitute Get When Iz sel Figure 10 Example of the indication logic for the Train Stop RailCorp Page 20 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 NOTE The Train Stop normal symbol bitmap is substituted by a Train Stop reverse symbol when the VR and VRR LINK functions are true and the symbol colour is shown as magenta when the detection is made VNR LINK or VRR LINK Any loss of detection will result in this symbol displaying the default grey colour An example of the menu logic for the Train Stop is as shown in Figure 11 Add Menu Delete Menu Ok Cancel Gridmap Menu String Logic Bit BREAK NORMAL DETECTION will set EG NRLINK Emulates Pushbutton I Menu String Logic Bit MAKE NORMA
35. nd stored in this folder The Bitmap folder on the simulation computer shall be identical to this To ensure consistency in presentation Design Engineers shall only use bitmaps from the network folder Any new bitmaps to be created shall be consistent with current existing bitmaps and are to be saved in the monochrome format only RailCorp Page 18 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 5 3 2 5 3 1 Following the creation of the new bitmap it shall be the Design Engineers responsibility to ensure the new bitmap is copied into both the network and simulation computer Bitmap folder When the Track Panel or Control Panel is being created the bitmaps are placed on the screen by selecting the bitmap from the bitmap palette and dropping it in the required grid on the screen The bitmap palette is a scrollable region at the bottom of the screen design window seen when Trakplan exe is running Track Panels Where there is a requirement to simulate the field equipment during design testing a Track Panel may be designed using the Trakplan exe software This panel may show the layout of the track arrangements including Points Signals Train Stops Platforms and Track Circuits Additional indications can be provided such as interface functions warning lights individual signal aspec
36. on computer mounted in a 19 inch computer rack This computer may be connected to up to 5 monitors The computer rack also includes Microlok II cardfiles power supply units a Cyclades 16 port serial IO expansion unit and Traktronics electronic patch panels each with 16 port connections There are Traktronics electronic patch panels suitable for an RS232 hardware interface and an electronic patch panel suitable for an RS423 485 hardware interface The simulation computer is connected to the Microlok II CPU cards via the electronic patch panels Each of the 4 ports associated with the Microlok II CPU cards are wired to the electronic patch panels and the connectivity between each port is configured via the MISS software Drawings showing the serial port wiring from the simulation computer to the electronic patch panels and from the Microlok Il CPU cards to the electronic patch panels can be found in the appendix These drawings will need to be referred to when preparing the MISS signal interlocking configuration drawing Microlok Peer to Peer Configurations The MISS hardware for testing systems that use peer to peer protocols include RS400 switches This permits the RS400 data to also be tested although in a conglomerated file rather than the separated files that would be used in the field installation This document does not specifically address the peer to peer workstation However the testing functionalities described here in are to be ap
37. ount of links any link that is a direct serial connection between two Microlok II CPU card ports may be connected together directly bypassing the ePatch units RailCorp Page 12 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 3 2 7 Bit List csv Generally a separate Bit List file is created for each connection as defined in the PORT INFO csv file Each link is usually related to a Microlok serial link and the information in each bit list file is taken from the relevant Microlok data These bit list files include the listings of the inputs and outputs of the serial link and may include Auto Configuration or Turn Around logic for simulation purposes A bit list file is also generally created for each simulation panel the Track Panel and the Control Panel These files contain any intermediate bits that are required to be created to aid the auto configuration or simulation of the interlocking oection 2 3 3 describes the auto configuration logic in more detail An example of a Bit List file is shown in Figure 7 File Edit View Insert Format Tools Data Window Help A28 A B S D E F G H 1 Direction Bit Name Bit Offset Bit value AutoContigBit OnDelay OffDelay 2 OUT 27 4HP D 27 4HR D D 3 OUT 27 4HDP 2 0 27 4HDR D D 4 OUT 27 4DP 3 D 27 4DR D D 5 OUT 27 ANGPZ 4 1 27 4HR
38. plied to all applications In addition to the RS400 switches instead of the Cyclades expansion unit used on the Master Slave configuration the peer peer simulator has a MOXA serial port expander The cardfiles are wired for up to 18 CPU cards Test Configurations The testing configuration of every Signal Interlocking to be tested will be different Prior to the development of the MISS configuration files it is recommended that a MISS configuration drawing shall be produced to confirm all hardware requirements and the necessary serial port connections required for the simulation An example of a MISS configuration drawing can be found in Appendix B RailCorp Page 6 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 2 2 2 1 RailCorp Testing Facilities Signal Design has in 2010 two MISS testing facilities One MISS is a dedicated master slave system while the other can be configured to operate either as a peer to peer system or as a master slave system These testing facilities are available for Design Integrity testing of Microlok Il based signal interlockings The testing facilities includes a separate desktop PC running the Microlok II tools software which may be used to interrogate the diagnostics of the Microlok CPU cards and monitor the application data variables as required Whe
39. re there is a requirement to interrogate more than one CPU card during testing additional desktop PCs or laptop PCs may be used NOTE The simulation computer also includes the Microlok II tools software and a port connection is available for use to also interrogate the diagnostics of the Microlok II CPU cards Where the testing configuration includes connection to an ATRICS computer this computer may be connected to any spare port of the electronic patch panels The configuration of the files should not be changed after testing Therefore the settings used for the simulation should be set to the configuration used on site A photo of the testing facilities is shown in Figure 1 Figure 1 RailCorp MISS Test Facility 2 3 Software Configuration 2 3 1 General MISS exe is the executable program required to run the Microlok Interlocking Simulation System Generally this software would only be run from the simulation computer in the Microlok test room Trakplan exe is the executable program required for producing the Track Side Panel and the Mimic Control Panel These panels are used by MISS to simulate and control the interlocking via a mouse or keyboard interface This software is required to be installed on the Design Engineers PC for the development of the necessary panels RailCorp Page 7 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simu
40. rlocking Simulation System MISS Design Guidelines EGG 1232 1 Introduction 1 1 Purpose This specification is applicable to the Microlok Interlocking Simulation System MISS 1 2 Scope This specification provides guidance on the configuration testing and operation of the MISS 1 3 Referenced Documents The following documents provide supporting information or referenced information to that provided by this document US amp S Documents e Microlok Interlocking Simulation System Users Manual e Microlok Interlocking Simulation System Getting Started Guide e Microlok Interlocking Simulation System Trakplan User Manual e Microlok ll System Description SM 6800A e Microlok I Hardware Installation SM 6800B e Microlok Il System Start up Trouble Shooting and Maintenance SM 6800C e Microlok ll System Application Logic Programming Guide SM 6800D e Microlok Il Programmable Controller Platform Safety Application Issues RailCorp Documents e Design of Microlok Il Interlockings SPG 1230 e Microlok File Control Microlok Data Design and Factory Acceptance Test QSDP16 e Re Testing of Microlok Data QSDP31 e Checking of Microlok Circuit and Data Designs QSDP33 e Application of MISS Replay amp Emergency Control Software QSDP68 2 MICROLOK INTERLOCKING SIMULATION SYSTEM 2 1 General The MISS software and hardware has been developed to allow for the simulation and testing of the application data for Microlok based signal interlockings This syste
41. ry of change 14 September New document 2010 1 November 2 5 3 5 Control Panels reworded for NX as well as OCS 2010 panels 2 5 3 7 OCS added to title to read OCS Route control Function 2 5 3 8 new section titled NX Route control Function to describe behaviour of screen based buttons for commence and finish functionality 1 Reference documents QSDP68 added 2 1 new paragraph added re MISS data and QSDP 68 1 2 27 November Apply correct document template for Guideline type 2012 document Renumber TMG E1232 to EGG 1232 to comply with updated TMA 400 Engineering Publications Manual Summary of changes from previous version Summary of change Added Introduction as section 1 containing 1 1 Purpose 1 2 Scope and 1 3 Referenced Documents Sections 2 2 1 A renumbered to 2 2 1 1 and section 2 2 1 B renumbered to 2 2 1 2 Description added to figure captions RailCorp Page 2 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 Contents 1 MOGUC o ME 5 1 1 O m T 5 1 2 0 eae 5 1 3 Referenced Documents senes nnni nnn nes nnaa sanis s sna iaa n ensis nsa sans snas 5 2 MICROLOK INTERLOCKING SIMULATION SYSTEM c cecreeeeeeeeee 5 2 1 COR A
42. s Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 NOTE In the log section of the Microlok II data where it includes the logging of the enable bit associated with each local I O board in the cardfile these bits will be required to be commented out due to the modifications made for MISS This may be carried out as follows LOG BITS LOCAL JUN LOG OUT SLOT1 ENABLED COMMENTED OUT FOR MISS IN_SLOT2 ENABLED COMMENTED OUT FOR MISS INVIN32 SLOTA ENABLED COMMENTED OUT FOR MISS O RailCorp Page 35 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 6 2 Appendix B MISS Configuration Example 9600 9600 9600 9600 9600
43. s drawing shall show the configuration of the Microlok CPU cards and the port connections required for the simulation Reference would need to be made to the MISS circuits when producing the MISS configuration drawing An example of the ePatch file is shown in Figure 6 RailCorp Page 11 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 SI File Edit View Insert Format Tools Data Window Help ABB pal A E e 1 From Port To Port V 35 36 ds d 3b 3 4 50 E Ka De 3 6 54 12 E SE 15 FEA 50 16 L3 BU 13 10 be 22 11 ER 25 12 34 20 13 34255111410 21 24 27 Figure 6 ePatch file The port numbers shown in the table are the port numbers of the ePatch panels numbers 1 to 16 apply to ePatch panel 1 and ports 17 to 32 apply to ePatch panel 2 and port numbers 33 to 48 apply to ePatch panel 3 etc The From Port field is generally the master port of the link The To Port field is generally the slave port of the link These entries do not need to be in any particular numeric order Line 13 indicates an example of a multi drop link note the use of a comma for each of the slave ports of that multi drop link NOTE There is a limitation of 16 links that can be defined with the current hardware configuration Where the interlocking under test requires a greater am
44. sign Guidelines EGG 1232 2 5 3 8 ITS Tral paa Add Menu Delete Menu Ok Cancel Gridmap l Menu String Logic Bit SET EIMA ROUTE will set E1MA_URR Emulates Pashbatten v Menu String Logic Bit SET 61MB ROUTE wilset E1MB URR Emulates Pushbutton v Menu String Logic Bit ISET 6154 ROUTE willset 6154 LIRR B Emulates Pushbutton M Menu String Logic Bit ISET 6158 ROUTE wilset 515B pp EE Emulates Pushbutton v Menu String Logic Bit SCH CANCEL 61 SIGNAL will set Et UNR Emulates Pushbutton Iv Figure 14 Example of the logic associated with the Route command menu Depending on the menu item selected that particular control bit will be sent to the interlocking The control bits including the signal cancel bit are pulsed to momentarily set the control bit true NX Route Control Functions Push button controls for setting signal routes are sent to the panel processor via a drop down menu which provides an option to the push button to set a main or shunt route or to pull the button to cancel the route that has been set for that signal The symbol on the button indicates the available functions that may be selected When clicking a push button symbol the button selection drop down menu is displayed When a button has been selected as a commence action the outline of the button on the screen flashes white until a finish button for a valid route from the button is selected The outline of th
45. ssued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 bits and output bits defined within that Bit List file The bit value will be displayed as blue for true 1 and red for false 0 It is possible to manually alter transmit command the status of the bits in the output list or reset reset command these bits to the original logic state It is recommended that these windows are used for the through testing of non vital or miscellaneous bits that may not be indicated on the Track or Control panel For example the bit status in the slave location Bit List file can be transmitted change of state and the corresponding bit in the ATRICS Bit List file can be confirmed to that change of state Testing in this manner will reduce the need to provide numerous non vital or miscellaneous indications on the Track or Control Panel that would only be required to be tested the once An example of an I O Display screen is as shown in Figure 20 DER MN 521 1 0 Display m JP BITS FROM INT 420AT 12DT 1AT 1BT SP1 120vPOP SP1 A DLE HI MAIN SF1 A Div BEL B BLZ SF1 B MAIN SF1 B Div Figure 20 I O Display Screen 3 MICROLOK Il APPLICATION DATA 3 1 General The Microlok Il development system tools are to be used to develop and compile an application logic program debug the program and upload t
46. sting as explained in the following section 3 2 Application Data Modifications for MISS 3 2 1 Initial Design The interface section of the Microlok Il application data includes two sub sections LOCAL and COMM The LOCAL sub section specifies the interface I O boards installed in the Microlok cardfile and defines the individual data bits associated with each board The COMM sub section specifies the interface serial communication links to be defined including the individual data bits associated with the inputs and outputs of each serial link As the MISS does not include a facility to test the physical I O boards the LOCAL sub section is to be designed as per the final configuration and then modified to suit the MISS configuration by temporarily commenting out the relevant sections The UO defined in the LOCAL section is then to be duplicated in the COMM section including the same bit names A spare serial port is to be utilised for this purpose An example of the application data alterations designed for MISS can be found in the appendix 3 2 2 Pre commissioning Following the testing of the application data the data is to be modified for the commissioning In an effort to reduce the amount of modifications to the application data and in order to retain the simulation data for any possible future testing the simulation data is not to be deleted In the commisssioning version of application data the previously commented out data in the LOCAL
47. tection separately to confirm that each input bit is correctly in the data However once this is proven only one of the normal and one of the reverse need to be manipulated for control table testing Miscellaneous Auto Configuration Functions Miscellaneous functions such as Power Supply Units or Diversity Link Controllers where there are input bits that are brought back into the interlocking and are included in the Bit List file have the entry in the Bit Value field is set at 1 to ensure they are simulated as true at the start up of the interlocking 2 3 4 Hot Standby Configurations Hot Standby configurations generally include the duplication of Microlok master processors As the application data is duplicated in each processor it is considered not necessary to test the duplicated data in a dual hot standby configuration on a MISS Field testing needs to be carried out as described in SPG 1230 Should there be a requirement to specifically test Hot Standby application logic it is recommended that an ATRICS computer be included in the testing configuration This is to avoid the need to produce a complex MISS Control Panel Where a MISS Control Panel is to be provided there would be a requirement to include a separate Bit List file for each of the 2 master processors and the bits names in these files would need to be different to allow the separation of the controls and indications for each master processor in the MISS data base The MIS
48. tre An example of the logic associated with the Points key indications are as shown in Figure 12 Substitute Bitmap Substitute Color Delete NE OF Cancel d 2 GridMap Bitmap Color Displays In al az Default Bitmap Logic Element Color n Logic Element substitute When 225NR is sel Substitute Ki When 225NR is set Bitmap Logic Element Color Logic Elernent substitute When 225RR is set Substitute i When 225RR ig set Figure 12 Example of the logic associated with the Points key indications The arrow symbol is substituted for an alternate bitmap to indicate normal or reverse when the particular logic in the Logic Element field is true RailCorp Page 22 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 An example of the logic associated with the Points Key Control menu is as shown in Figure 13 icc D S ETT EES SA er nd Add Menu Delete Menu Ok Cancel Gridmap Menu String Logic Bit Normal will set 225NKEY Emulates Pushbutton Iv Menu String Logic Bit Centre will set 225CKEY Emulates Pushbutton v Menu String Logic Bit Reverse will set 225RKEY Emulates Pushbutton v Figure 13 Example of the logic associated with the Points Key Control menu When clicking on the Points Key arrow a menu will appear with 3 options to set the Points ke
49. tries will be missed For example a track item on the control panel is driven by the field bit as used on the track panel rather than using the control system indication bit Where multiple bitmaps have been stacked in a single grid square to build a complex object e g signal trainstop one cannot delete a single bitmap One needs to keep all or delete all Track panel may be spread out to fit all the objects e g 6 light signal with shunts and route indicator but the control panel does not need to be spread out as much The more compact the control panel can be drawn the easier it is to be able to view the whole picture Flashing indications may be provided in the screen design by creating a FLASH bit and utilising the On Delay and Off Delay fields in the Bit List files However this will cause the MISS log file to be almost unusable Hence this is not recommended The use of flashing indications can be very useful Should it be necessary to review the log it can be opened using MS Excel and the flash bits that tend to flood the file can be filtered out to leave the important bits visible The PC Port Number in the Port Info file should start with port 3 as this is actually port 1 of the 16 port expansion unit Ports 1 and 2 of the MISS computer are available for other uses such as for the Microlok Il Tools software MISS bit names are case sensitive The I O from the Microlok application data can be copied into the B
50. true RailCorp Page 19 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 An example of the logic associated with the Points detection control menu is as shown in Figure 9 L Zi fg r Zenn PR CL Ba va E z Ae aor ton Add Menu Delete Menu Ok Cancel Erndmap Menu String Logic Bit BREAK NORMAL DETECTION will set 225MLink Emulates Pushbutton Menu String Logic Bit IMAKE NORMAL DETECTION willset 225 Link Emulates Pushbutton I Menu String Logic Bit wll set Figure 9 Example of logic associated with the Points Detection For example when clicking on the Points normal detection indication a menu will appear with 2 options to make or break the normal detection Selecting the appropriate option will toggle the logic bit 225NLink true or false 2 5 3 2 Train Stops Train Stops are indicated on the Track Panel and the symbol is displayed in the raised or lowered position for simulation purposes The Train Stop symbol is shown as magenta when the detection is made The centre of the Train Stop symbol changes to magenta to indicate the VR function is true and the Train Stop symbol will be shown in the lowered position when the VRR function is true The manipulation of the Train Stop detection is carried out by clicking on the Train Stop symbol A drop down
51. ts lamp failures and EOL s This panel can allow the manipulation of functions through drop down menus including track circuits train stop detection point detection and other miscellaneous functions as required Points Point detection is indicated on the Track Panel for each set of Points An indication is displayed separately for both normal and reverse points detection and a yellow indication is displayed amp NORMAL when the detection is made Loss of detection will result in a grey indication Zei POINTS REVERSE EOL An indication is also provided for the Points EOL and a yellow indication is displayed when the EOL detection is made Loss of detection will result in a grey indication Clicking on the indication and selecting from the drop down menu may break Point and EOL detection where required An example of the logic associated with the Points indication is as shown in Figure 8 Substitute Bitmap Substitute Color Delete DE Cancel lt lt 22 GridM ap Bitmap Color Displays A in OH as Default Bitmap Logic Element Color Logic Element Substitute When SS Substitute when 2258NKP 2258NKA in Bitmap Logic Element Calor Logic Element Substitute When is sel Substitute 7 Wen is sel Figure 8 Example of the logic associated with the Points Indication The colour yellow is substituted for the standard bitmap colour when the result of the logic in the Logic Element field is
52. tton will result in a drop down menu being displayed giving the option to set or cancel the Auto Re clearing function When a signal route is set in the Auto Re clearing mode a white A will be displayed in the centre of the button Examples of the logic associated with the Auto Re clear indications and selection menu are as shown in Figure 16 and Figure 17 Substitute Bitmap Substitute Color Gridh ap Bitmap Color Displays ol in EI az Default Bitmap Logic Element Color Logic Element substitute When G MB ASR is sel Substitute es When ls sel Figure 16 Example of logic associated with the Auto Re clear Indications and selection menu O RailCorp Page 25 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 Add Menu Delete Menu Ok Cancel Gridmap 9 Menu String Logic Bit SET AUTO RECLEAR willset ETARR Emulates Pushbutton 4 Menu Sting Logic Bit CANCEL AUTO RECLEAR willset ETARXR Emulates Pushbutton v Figure 17 Example of logic associated with the Auto Re clear Indications and selection menu 2 5 3 11 Track Indications Track indications are provided for each track circuit on the Control Panel These indications include a red indication for track occupied a grey indication for track un occupied a green indication for main route set and a
53. ut associated with the signal as shown in Table 1 Bit Bit On Off OUT WeMAHP fo um ae o a our nao Jo namn jo 0 on na Jo nr o In on nesme o nesan o In our messe o mess o 0 112MAHR 112MBH OUT 112NGPZ R 112SAHR 112S5BHR Table 1 NOTE The RGKR function is usually created within the Microlok data If there is a requirement to display actual signal aspects on the Track Panel the logic associated with this is created within the Track Panel screen design This is covered later in the document 2 3 3 2 Trainstop Auto Configuration Functions To simulate the operation of the Train Stop the control bit that would normally drive the VR output relay is used in turn around logic and brought back into the interlocking Data is provided in the Auto Config Bit field for each input associated with the Train Stop detection as shown in Table 2 Bit Bit On Off OUT 112VNP O t12VR it2VNRLINK 0 O OUT H2VRP o 112VR 112VRRLINK o 0 Table 2 RailCorp Page 14 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS Design Guidelines EGG 1232 NOTE The logic in the Auto Config Bit field includes intermediate bits named VRRLINK and VNRLINK These bits are used to enable the breaking of the Train Stop detection for testing purposes These intermediate
54. y normal centre or reverse Selecting either option will send that control bit to the interlocking The bit value is pulsed true due to the Emulates Pushbutton field being selected The bit in the Logic Bit field is an intermediate bit which is defined in the Control Panel Bit List file Control Panel CSV The configuration logic associated with this bit is found in another Bit List file which is created for the control panel indications and controls serial link In this example the Bit List file is named ATRICS as it defines the I O bits between the Microlok interlocking and ATRICS An example of this configuration logic is as shown in Table 7 ee Bit Bit Bit m On Off 225NKEY 225RKEY 22 225RKEY 225NKEY 22 225CKEY 225NKEY 22 Table 7 Configuration Logic 2 5 3 7 OCS Route Control Functions Signal route controls are sent to the interlocking via a drop down menu which will provide an option to select the route to be set or an option to cancel the route set for that signal When clicking on the signal repeater symbol the route selection menu will be displayed When the route is set the associated route lights will be indicated on the Control Panel An example of the logic associated with the Route command menu is as in Figure 14 RailCorp Page 23 of 38 Issued November 2012 UNCONTROLLED WHEN PRINTED Version 1 2 RailCorp Engineering Guideline Signals Microlok Interlocking Simulation System MISS De
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