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NI cDAQ-9188XT User Manual

1. Counter S1 i i f S2 f Armed Ae i aa gt wA de a E OO Source TULU l i LI i i Ili sample a Clock i i i HL i i i i HL Buter f f i a5 i i i f a utter 2 2 3 3 313 A Note Ifa pulse does not occur between sample clocks an overrun error occurs For information about connecting counter signals refer to the Default Counter Timer Routing section 5 8 ni com NI cDAQ 9188XT User Manual Semi Period Measurement In semi period measurements the counter measures a semi period on its Gate input signal after the counter is armed A semi period is the time between any two consecutive edges on the Gate input You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate the semi period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Refer to the following sections for more information about semi period measurement options Single Semi Period Measurement Implicit Buffered Semi Period Measurement Refer to the Pulse versus Semi Period Measurements section for informatio
2. 5 24 ni com NI cDAQ 9188XT User Manual Pulse Train Generation Refer to the following sections for more information about the cDAQ chassis pulse train generation options e Finite Pulse Train Generation e Retriggerable Pulse or Pulse Train Generation e Continuous Pulse Train Generation Buffered Pulse Train Generation Finite Implicit Buffered Pulse Train Generation Continuous Buffered Implicit Pulse Train Generation Finite Buffered Sample Clocked Pulse Train Generation Continuous Buffered Sample Clocked Pulse Train Generation Finite Pulse Train Generation This function generates a train of pulses with programmable frequency and duty cycle for a predetermined number of pulses With cDAQ chassis counters the primary counter generates the specified pulse train and the embedded counter counts the pulses generated by the primary counter When the embedded counter reaches the specified tick count it generates a trigger that stops the primary counter generation Figure 5 28 Finite Pulse Train Generation Four Ticks Initial Delay Four Pulses Counter Armed soure UUU UUU UUU UULU Enablex Ctrx Retriggerable Pulse or Pulse Train Generation The counter can output a single pulse or multiple pulses in response to each pulse on a hardware Start Trigger signal The generated pulses appear on the Counter n Internal Output signal of the counter You can r
3. Controlling the Direction of Counting In edge counting applications the counter can count up or down You can configure the counter to do the following e Always count up e Always count down e Count up when the Counter 0 B input is high count down when it is low For information about connecting counter signals refer to the Default Counter Timer Routing section 5 4 ni com Pulse Width Measurement In pulse width measurements the counter measures the width of a pulse on its Gate input signal You can configure the counter to measure the width of high pulses or low pulses on the Gate signal NI cDAQ 9188XT User Manual You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges on the Source signal while the pulse on the Gate signal is active You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter A pulse width measurement will be accurate even if the counter is armed while a pulse train is in progress If a counter is armed while the pulse is in the active state it will wait for the next transition to the active state to begin the measurement Refer to the following sections for more information about cDAQ chassis pulse width measurement options e Single Pulse Width Measurement Implicit Buffered Pulse
4. Using a Digital Source To use AO Pause Trigger specify a source and a polarity The source can be a PFI signal or one of several other internal signals on the cDAQ chassis You also can specify whether the samples are paused when AO Pause Trigger is at a logic high or low level Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event depending on the trigger properties When you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high or low level depending on the trigger properties The analog trigger circuit must be configured by a simultaneously running analog input task 2 Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering National Instruments 3 5 Chapter 3 Analog Output Minimizing Glitches on the Output Signal When you use a DAC to generate a waveform you may observe glitches on the output signal These glitches are normal when a DAC switches from one voltage to another it produces glitches due to released charges The largest glitches occur when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequen
5. 3 Buffer 2 Sample Clocked Buffered Pulse Width Measurement A sample clocked buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses correlated to a sample clock The counter counts the number of edges on the Source input while the Gate input remains active On each sample clock edge the counter stores the count in the FIFO of the last pulse width to complete The STC3 transfers the sampled values to host memory using a high speed data stream Figure 5 7 shows an example of a sample clocked buffered pulse width measurement Figure 5 7 Sample Clocked Buffered Pulse Width Measurement Pulse Source LIL LIU UL IU UU l LALU aara 4 2 2 13 4 4 3 Note Ifa pulse does not occur between sample clocks an overrun error occurs Sample Clock i Buffer i For information about connecting counter signals refer to the Default Counter Timer Routing section 5 6 ni com NI cDAQ 9188XT User Manual Pulse Measurement In pulse measurements the counter measures the high and low time of a pulse on its Gate input signal after the counter is armed A pulse is defined in terms of its high and low time high and low ticks or frequency and duty cycle This is similar to the pulse width measurement except that the inactive pulse is meas
6. ccccecceecceseeeeeeeeeeeeeeeeeeees 5 28 Continuous Buffered Implicit Pulse Train Generation cceeeseseeeseeeceeeeees 5 28 Finite Buffered Sample Clocked Pulse Train Generation cceeeeseeeeees 5 28 Continuous Buffered Sample Clocked Pulse Train Generation 0 06 5 30 Frequency Generation enen Aes r E E A aa 5 30 Using the Frequency Generator ssessessesesseseseseteertsesststsrstestsetssestssesessseesese 5 30 Frequency Divisi Otene eiro ana a E E E EE EE oases 5 31 Watchdog TiMmetsnsnsisnysees eae a errre a Ee 5 31 Pu ls Gen rt tion for ETS 5 4 se vera islotlea ore e R E 5 32 Counter Timing Signals ccccccccsessessesseesesseescescescesceseeseeeeeeseceeceeceeceaesaeaaesaecaecaeeaeeneeas 5 32 Counter n Source Signal ccccccccsecseessescesceseeseeeeeseeseceeceeceeceseeseeseeaeeaecaecaecaeeaaeaaente 5 33 Routing a Signal to Counter n Source ccceceessesseseeeeeeeeeeeeeceeceeceseteeeeeeeeteees 5 34 Routing Counter n Source to an Output Terminal eee eeeeeeeeeeeeeeeeeeeees 5 34 Counter n Gate Signal cccccscesessecseeseesecseescescesceseeseeeeeeseceeceecscaeeaeeaeeaeeaecaeeaeenee 5 34 Routing a Signal to Counter n Gate cccceccecsesessesseeseesceeceeceeceeceeeesenseeeeeetaees 5 34 Routing Counter n Gate to an Output Terminal 0 0 cece cee ce ceeceeeeeeeeeeee 5 35 Countern Aux Sional steininn eE E cinch a aE 5 35 Routing a Signal to Counter n AUX ccccescessesseesesseeeesee
7. Ctr n Internal Output 4 DI Sample Clock PFI Sigma Delta Module Internal Output o Analog Comparison Event DI Sample Clock Timebase Programmable 20 MHz Timebase Clock H Divider er 80 MHz Timebase 100 kHz Timebase Routing DI Sample Clock to an Output Terminal You can route DI Sample Clock to any output PFI terminal DI Sample Clock Timebase Signal The DI Sample Clock Timebase di SampleClockTimebase signal is divided down to provide a source for DI Sample Clock DI Sample Clock Timebase can be generated from external or internal sources DI Sample Clock Timebase is not available as an output from the chassis Using an Internal Source To use DI Sample Clock with an internal source specify the signal source and the polarity of the signal Use the following signals as the source e AI Sample Clock e AO Sample Clock e Counter n Internal Output Frequency Output e DI Change Detection Output Several other internal signals can be routed to DI Sample Clock Refer to the Device Routing in MAX topic in the N DAQmx Help or the LabVIEW Help for more information National Instruments 4 3 Chapter 4 Digital Input Output and PFI Using an External Source You can route the following signals as DI Sample Clock e Any PFI terminal e Analog Comparison Event an analog trigger You can sample data on the rising or falling edge of DI Sample Clock Routing DI Sample Clock to an Out
8. Max Error 00125 6 67 02 00125 5 16 ni com NI cDAQ 9188XT User Manual Again the measurement time for the one counter measurement is lowest but the accuracy is lower Note that the accuracy and measurement time of the sample clocked and two counter large range are almost the same The advantage of the sample clocked method is that even when the frequency to measure changes the measurement time does not and error percentage varies little For example if you configured a large range two counter measurement to use a divide down of 50 for a 50 k signal then you would get the accuracy measurement time and accuracy listed in Table 5 3 But if your signal ramped up to 5 M then with a divide down of 50 your measurement time is 0 01 ms but your error is now 0 125 The error with a sample clocked frequency measurement is not as dependent on the measured frequency so at 50 k and 5 M witha measurement time of 1 ms the error percentage is still close to 0 00125 One of the disadvantages of a sample clocked frequency measurement is that the frequency to be measured must be at least twice the sample clock rate to ensure that a full period of the frequency to be measured occurs between sample clocks e Low frequency measurements with one counter is a good method for many applications However the accuracy of the measurement decreases as the frequency increases e High frequency measurements with two counters is accurate for high frequenc
9. The counter pauses pulse generation when the Pause Trigger is active Figure 5 31 shows a continuous pulse train generation using the rising edge of Source Figure 5 31 Continuous Pulse Train Generation SOURCE j j OUT Counter Armed Continuous pulse train generation is sometimes called frequency division If the high and low pulse widths of the output signal are M and N periods then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M N For information about connecting counter signals refer to the Default Counter Timer Routing section Buffered Pulse Train Generation The cDAQ chassis counters can use the FIFO to perform a buffered pulse train generation This pulse train can use implicit timing or sample clock timing When using implicit timing the pulse idle time and active time changes with each sample you write With sample clocked timing each sample you write updates the idle time and active time of your generation on each sample clock edge Idle time and active time can also be defined in terms of frequency and duty cycle or idle ticks and active ticks 4 Note On buffered implicit pulse trains the pulse specifications in the DAQmx Create Counter Output Channel are ignored so that you generate the number of pulses defined in the mu
10. com manuals and search for the document title A Caution Do not operate the NI cDAQ 9188XT in a manner not specified in these operating instructions Product misuse can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to National Instruments for repair A Note Because some C Series I O modules may have more stringent certification standards than the NI cDAQ 9188XT chassis the combined system may be limited by individual component restrictions Refer to the NJ cDAQ 9188XT Specifications for more details AN Hot Surface This icon denotes that the component may be hot Touching this component may result in bodily injury Safety Guidelines for Hazardous Locations The NI cDAQ 9188XT chassis is suitable for use in Class I Division 2 Groups A B C D T4 hazardous locations Class 1 Zone 2 AEx nA IIC T4 and Ex nA IIC T4 hazardous locations and nonhazardous locations only Follow these guidelines if you are installing the NI cDAQ 9188XT chassis in a potentially explosive environment Not following these guidelines may result in serious injury or death A Caution Do not disconnect the power supply wires and connectors from the chassis unless power has been switched off A Caution Substitution of components may impair suitability for Class I Division 2 A Caution For Zone 2 applications install the chassis in an enclosure rated
11. higher in frequency than the Nyquist frequency of the system Figure 5 36 shows an example of pulse generation for ETS the delay from the trigger to the pulse increases after each subsequent Gate active edge Figure 5 36 Pulse Generation for ETS GATE M or M o mn D1 D2 D1 AD D3 D1 2AD For information about connecting counter signals refer to the Default Counter Timer Routing section Counter Timing Signals The cDAQ chassis features the following counter timing signals e Counter n Source Signal Counter n Gate Signal 5 32 ni com NI cDAQ 9188XT User Manual e Counter n Aux Signal e Counter n A Signal Counter n B Signal e Counter n Z Signal e Counter n Up_Down Signal e Counter n HW Arm Signal Counter n Sample Clock Signal Counter n Internal Output Signal Counter n TC Signal Frequency Output Signal In this section n refers to the cDAQ chassis Counter 0 1 2 or 3 For example Counter n Source refers to four signals Counter 0 Source the source input to Counter 0 Counter 1 Source the source input to Counter 1 Counter 2 Source the source input to Counter 2 or Counter 3 Source the source input to Counter 3 Note All counter timing signals can be filtered Refer to the PFI Filters section of Chapter 4 Digital Input Output and PFT for more information Counter n Source Signal The selected edge of the Counter n Source signal increment
12. you can use the arm start trigger to have start trigger like behavior The arm start trigger can be used for synchronizing multiple counter input and output tasks When using an arm start trigger the arm start trigger source is routed to the Counter n HW Arm signal Start Trigger For counter output operations a start trigger can be configured to begin a finite or continuous pulse generation Once a continuous generation has triggered the pulses continue to generate until you stop the operation in software For finite generations the specified number of pulses is generated and the generation stops unless you use the retriggerable attribute When you use this attribute subsequent start triggers cause the generation to restart When using a start trigger the start trigger source is routed to the Counter n Gate signal input of the counter Counter input operations can use the arm start trigger to have start trigger like behavior e Pause Trigger You can use pause triggers in edge counting and continuous pulse generation applications For edge counting acquisitions the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa For continuous pulse generations the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or vice versa When using a pause trigger the pause trigger source is routed to the Counter Gate signa
13. 4 2 digital output 4 8 parallel versus serial DIO modules 4 1 static DIO 4 2 waveform acquisition 4 2 l 2 ni com digital input filters parallel DIO modules only 4 7 getting started with applications in software 4 7 timing signals 4 2 triggering 4 2 digital input signals DI Pause Trigger 4 6 DI Reference Trigger 4 5 DI Sample Clock 4 3 DI Sample Clock Timebase 4 3 DI Start Trigger 4 4 digital output data generation methods 4 9 getting started with applications in software 4 14 timing signals 4 10 triggering 4 10 watchdog timer 4 13 digital output signals DO Pause Trigger 4 12 DO Sample Clock 4 11 DO Sample Clock Timebase 4 11 DO Start Trigger 4 11 documentation NI resources B 1 drivers NI resources B 1 E edge counting 5 3 buffered 5 4 on demand 5 3 sample clock 5 4 single point 5 3 edge separation measurement buffered two signal 5 22 single two signal 5 22 electromagnetic compatibility guidelines 1 3 encoders quadrature 5 19 encoding X1 5 19 X2 5 19 X4 5 19 equivalent time sampling 5 32 Ethernet cabling 1 17 examples NI resources B 1 external source less than 40 MHz 5 40 F features counter 5 39 filters digital input parallel DIO modules only 4 7 PFI 4 15 FREQ OUT signal 5 37 frequency division 5 31 generation 5 30 generator 5 30 measurement 5 10 Frequency Output signal 5 37 G generations analog output data 3 1 buffered h
14. Appendix B Technical Support and Professional Services Index National Instruments ix Getting Started with the cDAQ Chassis This chapter provides a cDAQ chassis overview and lists information about mounting the chassis and installing C Series I O modules The National Instruments CompactDAQ Extended Temperature rugged eight slot Ethernet chassis CDAQ 9188XT is designed for use with C Series I O modules The cDAQ chassis is capable of measuring a broad range of analog and digital I O signals and sensors For module specifications refer to the documentation included with your C Series I O module s or go to ni com manuals Figure 1 1 shows the cDAQ chassis Figure 1 1 NI cDAQ 9188XT Chassis iol j QOOOQOQOOOQOOOOOQOOOSO BA epg Chassis Grounding Screw 5 Reset Button Installed C Series Modules 6 PFIO and PFI 1 BNC Connectors Module Slots 7 Ethernet Connector and 10 100 1000 and LINK ACT LEDs 9 to 30 VDC Power Connector 8 POWER STATUS and ACTIVE LEDs RON National Instruments 1 1 Chapter 1 Getting Started with the cDAQ Chassis Safety Guidelines A Caution Refer to the Read Me First Safety and Electromagnetic Compatibility document for important safety and electromagnetic compatibility information To obtain a copy of this document online visit ni
15. Channel Z Behavior cis co lt 251 sev siecayewiess staves ea ceo a E E EE EEE EES 5 19 Measurements Using Two Pulse Encoders ccscessesseeseeseeeceseeeeeeeeeeeeeceeeaes 5 20 Buffered Sample Clock Position Measurement ccccsessseseeseeseeseeeeeeeeeees 5 20 Two Signal Edge Separation Measurement cccsccscescessesseeeeeeeeeeseeseeaeeneeneeneenee 5 21 Single Two Signal Edge Separation Measurement c cceseeseeseereereereeeeees 5 22 Implicit Buffered Two Signal Edge Separation Measurement 000 5 22 Sample Clocked Buffered Two Signal Separation Measurement 045 5 22 Counter Output Applications cccceceeseeseeseescesceecesceseesceseeseeseceeceeceeceaeeaeeaeeaecsecaeeneeneeas 5 23 Simple Pulse Generation sinisi n eae EErEE EE Rar EE Ei 5 23 Single Pulse Generation 0 cccceeceescescescescesceseeseescceeceecesesaesaecaecsecsecaeeseeneeneens 5 24 Single Pulse Generation with Start Trigger ccc eeeseeseeeeeeteneeecesereteneeees 5 24 Pulse Train Generation 00 EERE E 5 25 Finite Pulse Train Generations sessing s ia E 5 25 Retriggerable Pulse or Pulse Train Generation ccceecescesceeeeseeeeeeeeeeceeeeaes 5 25 Continuous Pulse Train Generation cccesccsecsecsecsseeseeseseesecesceseeseeseeeceeenees 5 26 Buffered Pulse Train Generation cc ceeesecesseneeecesceeeceeceeeecseseceeceeeessesenseees 5 27 Finite Implicit Buffered Pulse Train Generation
16. Community Trademark of CAN in Automation e V DeviceNet and EtherNet IP are trademarks of ODVA Go SensorDAQ and Vernier are registered trademarks of Vernier Software amp Technology Vernier Software amp Technology and vernier com are trademarks or trade dress Xilinx is the registered trademark of Xilinx Inc Taptite and Trilobular are registered trademarks of Research Engineering amp Manufacturing Inc FireWire is the registered trademark of Apple Inc Linux is the registered trademark of Linus Torvalds in the U S and other countries Handle Graphics MATLAB Real Time Workshop Simulink Stateflow and xPC TargetBox are registered trademarks and TargetBox and Target Language Compiler are trademarks of The MathWorks Inc Tektronix Tek and Tektronix Enabling Technology are registered trademarks of Tektronix Inc The Bluetooth word mark is a registered trademark owned by the Bluetooth SIG Inc The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under license The mark LabWindows is used under a license from Microsoft Corporation Windows is a registered trademark of Microsoft Corporation in the United States and other countries Other product and company names mentioned herein are trademarks or trade names of their respective companies Members of the National Instruments Alliance Partner Program are business entities independent
17. Figure 5 19 X4 Encoding cha fo eH LE L E ChB Counter Value 5X 6X7X8X 9 X10X11X12X13 13X12 X11 KIO X9 XB X Serras Xi gt lt D gt lt a Channel Z Behavior Some quadrature encoders have a third channel channel Z which is also referred to as the index channel A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle You can program this reload to occur in any one of the four phases in a quadrature cycle National Instruments 5 19 Chapter 5 Counters Channel Z behavior when it goes high and how long it stays high differs with quadrature encoder designs You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B You must then ensure that channel Z is high during at least a portion of the phase you specify for reload For instance in Figure 5 20 channel Z is never high when channel A is high and channel B is low Thus the reload must occur in some other phase In Figure 5 20 the reload phase is when both channel A and channel B are low The reload occurs when this phase is true and channel Z is high Incrementing and decrementing takes priority over reloading Thus when the channel B goes low to enter the reload phase the increment occurs first The reload occurs within one maximum timebase period after the
18. For sample clocked operations an external signal must be provided to supply a clock source The source can be any of the following signals e AI Sample Clock e Al Start Trigger e AI Reference Trigger e AO Sample Clock e DI Sample Clock e DI Start Trigger e DO Sample Clock e CTR n Internal Output Freq Out PFI e Change Detection Event e Analog Comparison Event Not all timed counter operations require a sample clock For example a simple buffered pulse width measurement latches in data on each edge of a pulse For this measurement the measured signal determines when data is latched in These operations are referred to as implicit timed operations However many of the same measurements can be clocked at an interval with a sample clock These are referred to as sample clocked operations Table 5 1 shows the different options for the different measurements Table 5 1 Counter Timing Measurements Implicit Sample Clocked Measurement Timing Support Timing Support Buffered Edge Count No Yes Buffered Pulse Width Yes Yes Buffered Pulse Yes Yes Buffered Semi Period Yes No Buffered Frequency Yes Yes Buffered Period Yes Yes Buffered Position No Yes Buffered Two Signal Edge Separation Yes Yes 5 2 ni com NI cDAQ 9188XT User Manual Counter Input Applications The following sections list the various counter input applications available on the cDAQ chassis Counting Edges
19. Terminal You can route DI Reference Trigger to any output PFI terminal Reference Trigger is active high by default DI Pause Trigger Signal You can use the DI Pause Trigger di PauseTrigger signal to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low Using a Digital Source To use DI Pause Trigger specify a source and a polarity The source can be either from PFI or one of several other internal signals on your cDAQ chassis Refer to the Device Routing in MAX topic in the NJ DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa 4 Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering 2 Note Pause triggers are only sensitive to the level of the source not the edge 4 6 ni com NI cDAQ 9188XT User Manual Digital Input Filters When performing a hardware timed task you can enable a programmable debouncing filter on the digital input lines of a parallel DIO module
20. When performing a digital output operation you either can perform software timed or hardware timed generations Hardware timed generations must be buffered Software Timed Generations With a software timed generation software controls the rate at which data is generated Software sends a separate command to the hardware to initiate each digital generation In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing out a single value For software timed generations if any DO channel on a module is used in a hardware timed task no channels on that module can be used in a software timed task Hardware Timed Generations With a hardware timed generation a digital hardware signal controls the rate of the generation This signal can be generated internally on the chassis or provided externally Hardware timed generations have several advantages over software timed acquisitions e The time between samples can be much shorter e The timing between samples is deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed DO operations on the cDAQ chassis must be buffered Buffered Digital Output A buffer is a temporary storage in computer memory for generated samples In a buffered generation data is moved from a host buffer to the cDAQ chassis onboard FIFO before it is written
21. Width Measurement Sample Clocked Buffered Pulse Width Measurement Single Pulse Width Measurement With single pulse width measurement the counter counts the number of edges on the Source input while the Gate input remains active When the Gate input goes inactive the counter stores the count in the FIFO and ignores other edges on the Gate and Source inputs Software then reads the stored count Figure 5 5 shows an example of a single pulse width measurement Figure 5 5 Single Pulse Width Measurement GATE SOURCE rf Counter Value 0 Latched Value National Instruments 5 5 Chapter 5 Counters Implicit Buffered Pulse Width Measurement An implicit buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses The counter counts the number of edges on the Source input while the Gate input remains active On each trailing edge of the Gate signal the counter stores the count in the counter FIFO The STC3 transfers the sampled values to host memory using a high speed data stream Figure 5 6 shows an example of an implicit buffered pulse width measurement Figure 5 6 Implicit Buffered Pulse Width Measurement GATE source F711 ALA LALLA Counter Value 0 1 2 3 1 2 3 2
22. a counter or configure counters to be armed on a hardware signal Software calls this hardware signal the Arm Start Trigger Internally software routes the Arm Start Trigger to the Counter n HW Arm input of the counter Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input e Any PFI terminal e AI Reference Trigger e AI Start Trigger e Analog Comparison Event e Change Detection Event A counter s Internal Output can be routed to a different counter s HW Arm Some of these options may not be available in some driver software Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information about available routing options Counter n Sample Clock Signal Use the Counter n Sample Clock CtrnSampleClock signal to perform sample clocked acquisitions and generations You can specify an internal or external source for Counter n Sample Clock You also can specify whether the measurement sample begins on the rising edge or falling edge of Counter n Sample Clock If the cDAQ chassis receives a Counter n Sample Clock when the FIFO is full it reports an overflow error to the host software 5 36 ni com NI cDAQ 9188XT User Manual Using an Internal Source To use Counter n Sample Clock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals e DI Sample Clo
23. acquisition stops on the first rising or falling edge of the Analog Comparison Event signal depending on the trigger properties 4 Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Routing the Reference Trigger Signal to an Output Terminal You can route Reference Trigger to any output PFI terminal Reference Trigger is active high by default Al Pause Trigger Signal You can use the Pause Trigger to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low Using a Digital Source To use the Pause Trigger specify a source and a polarity The source can be either from PFI or one of several other internal signals on your cDAQ chassis Refer to the Device Routing in MAX topic in the NJ DAQmx Help or the LabVIEW Help for more information 2 6 ni com NI cDAQ 9188XT User Manual Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa Note Depending on the C Series I O module capabilities you may need two modules to utilize anal
24. and Professional Services You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events B 2 ni com Index Symbols lt 20 MHz source mode 5 40 Numerics 10 100 LED 1 16 10 100 1000 LED 1 16 80 MHz source mode 5 40 A acquisitions digital waveform 4 2 ACTIVE LED 1 16 analog input getting started with applications in software 2 7 timing signals 2 1 triggering 2 1 analog input signals AI Convert Clock behavior 2 2 AI Pause Trigger 2 6 AI Reference Trigger 2 5 AI Sample Clock 2 2 AI Sample Clock Timebase 2 2 Al Start Trigger 2 4 analog output data generation methods 3 1 getting started with applications in software 3 7 glitches on the output signal 3 6 timing signals 3 3 triggering 3 3 watchdog timer 3 6 analog output signals AO Pause Trigger 3 4 AO Sample Clock 3 3 AO Sample Clock Timebase 3 4 AO Start Trigger 3 4 antenna 1 19 applications counter input 5 3 counter output 5 23 edge counting 5 3 arm start trigger 5 38 B buffered edge counting 5 4 hardware timed generations analog output 3 2 digital output 4 9 position measurement 5 20 two signal edge separation measurement 5 22 C C Series I O module parallel versus serial DIO 1 21 calibration certificate NI resources B 1 cascading counters 5 39 cDAQ chassis featu
25. and television reception and prevent unacceptable performance degradation install and use this product in strict accordance with the instructions in the product documentation Furthermore any modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules A Caution To ensure the specified EMC performance operate this product only with shielded cables and accessories A Caution To ensure the specified EMC performance the length of any I O cable connected to a BNC PFI port must be no longer than 30 m 100 ft Special Guidelines for Marine Applications Some products are Lloyd s Register LR Type Approved for marine shipboard applications To verify Lloyd s Register certification for a product visit ni com certification and search for the LR certificate or look for the Lloyd s Register mark on the product label A Caution In order to meet the EMC requirements for marine applications install the product in a shielded enclosure with shielded and or filtered power and input output ports In addition take precautions when designing selecting and installing measurement probes and cables to ensure that the desired EMC performance is attained National Instruments 1 3 Chapter 1 Getting Started with the cDAQ Chassis Unpacking The cDAQ chassis ships in an antistatic package to prevent electrostatic discharge ESD ESD can damage sev
26. application or use examples to develop a new application or add example code to an existing application To locate NI software examples go to ni com info and enter the Info Code daqmxexp For additional examples refer to zone ni com To run examples without the device installed use an NI DAQmx simulated device For more information in Measurement amp Automation Explorer MAX select Help Help Topics NI DAQmx MAX Help for NI DAQmx and search for simulated devices Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices The following references to documents assume you have NI DAQm x 9 8 or later NI cDAQ Chassis Documentation The NI cDAQ 9188XT Quick Start packaged with your cDAQ chassis describes how to install your NI DAQmx for Windows software how to install the cDAQ chassis and C Series I O module and how to confirm that your device is operating properly The NI cDAQ 9188XT Specifications lists all specifications for your cDAQ chassis Go to ni com manuals and search for your cDAQ chassis The NI cDAQ Chassis Calibration Procedure contains information for calibrating all National Instruments CompactDAQ chassis Go to ni com manuals and search for your cDAQ chassis C Series I O Module Documentation and Specifications For module specifications refer to the documentation included with your C
27. computer the setup time may be longer Wait 30 to 60 seconds after the STATUS LED turns off then click Refresh List e Contact your system administrator to confirm that the network is working and that a firewall is not interfering with discovery For additional troubleshooting resources for the cDAQ chassis refer to the Troubleshooting Chassis Connectivity section of this manual and the Finding a Network DAQ Device in MAX topic in the Measurement amp Automation Explorer Help for NI DAQmx 12 Ifthe cDAQ chassis is not reserved automatically select the chassis and click the Reserve Chassis button Refer to the Reserving the Chassis in MAX section for more information 13 Self test your chassis in MAX by expanding Devices and Interfaces right clicking NI cDAQ 9188XT and selecting Self Test Self test performs a brief test to determine successful chassis installation When the self test finishes a message indicates successful verification or if an error occurred If an error occurs refer to ni com support daqmx 14 Runa Test Panel in MAX by expanding Devices and Interfaces NI cDAQ 9188XT right clicking your C Series module and selecting Test Panels to open a test panel for the selected module If the test panel displays an error message refer to ni com support Click Close to exit the test panel Note When in use the cDAQ chassis may become warm to the touch This is normal Wiring Power to the cDAQ Chassis A Cautio
28. excessive bus traffic or operating system latency Note Install parallel DO modules in slots 1 through 4 to maximize accessible FIFO size because using a module in slots 5 through 8 will reduce the accessible FIFO size With non regeneration old data is not repeated New data must continually be written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error Digital Output Triggering Signals Digital output supports two different triggering actions DO Start Trigger and DO Pause Trigger A digital or analog trigger can initiate these actions Any PFI terminal can supply a digital trigger and some C Series analog modules can supply an analog trigger For more information refer to the documentation included with your C Series I O module s Refer to the DO Start Trigger Signal and DO Pause Trigger Signal sections for more information about the digital output trigger signals Digital Output Timing Signals The cDAQ chassis features the following DO timing signals DO Sample Clock Signal DO Sample Clock Timebase Signal DO Start Trigger Signal DO Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section for more information 4 10 ni com NI cDAQ 9188XT User Manual DO Sample Clock Signal The DO Sample Clock do SampleClock signals when all the digital output channels in the t
29. from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents Export Compliance Information Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes ECCNs and other import export data WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAIL
30. pause trigger is asserted If the source of the sample clock is the onboard clock the generation resumes as soon as the pause trigger is deasserted as shown in Figure 4 5 Figure 4 5 DO Pause Trigger with the Onboard Clock Source Pause Trigger Sample Clock 4 12 ni com NI cDAQ 9188XT User Manual If you are using any signal other than the onboard clock as the source of the sample clock the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received as shown in Figure 4 6 Figure 4 6 DO Pause Trigger with Other Signal Source Pause Trigger en ne eed Sample Clock Using a Digital Source To use DO Pause Trigger specify a source and a polarity The source can be a PFI signal or one of several other internal signals on the cDAQ chassis You also can specify whether the samples are paused when DO Pause Trigger is at a logic high or low level Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event depending on the trigger properties When you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high or low level depending on the trigge
31. reload phase becomes true After the reload occurs the counter continues to count as before The figure illustrates channel Z reload with X4 decoding Figure 5 20 Channel Z Reload with X4 Decoding ChA mooo cha tf 2 E ee Max Timebase Counter Value 5Y e Y7 YA oy 1 VeXa Ya A 0 B 0 Z 1 Measurements Using Two Pulse Encoders The counter supports two pulse encoders that have two channels channels A and B The counter increments on each rising edge of channel A The counter decrements on each rising edge of channel B as shown in Figure 5 21 Figure 5 21 Measurements Using Two Pulse Encoders ChA ChB 1 Counter Value 2X 3 xX 4K 5 KX 4 X 3 X4 For information about connecting counter signals refer to the Default Counter Timer Routing section Buffered Sample Clock Position Measurement With buffered position measurement position measurement using a sample clock the counter increments based on the encoding used after the counter is armed The value of the counter is sampled on each active edge of a sample clock The STC3 transfers the sampled values to host memory using a high speed data stream The count values returned are the cumulative counts 5 20 ni com NI cDAQ 9188XT User Manual since the counter armed event that is the sample clock does not reset the co
32. sampled values to host memory using a high speed data stream Figure 5 25 shows an example of a sample clocked buffered two signal separation measurement Figure 5 25 Sample Clocked Buffered Two Signal Separation Measurement Sample Clock L L AUX GATE 4 p Ly source _ LPL UL LL Counter Value i 2 4 1 2 3 i 2 3 i L L gt l wj Buffer 4 Note Ifan active edge on the Gate and an active edge on the Aux does not occur between sample clocks an overrun error occurs For information about connecting counter signals refer to the Default Counter Timer Routing section Counter Output Applications The following sections list the various counter output applications available on the cDAQ chassis e Simple Pulse Generation e Pulse Train Generation e Frequency Generation e Frequency Division a Watchdog Timer Pulse Generation for ETS Simple Pulse Generation Refer to the following sections for more information about the cDAQ chassis simple pulse generation options e Single Pulse Generation e Single Pulse Generation with Start Trigger National Instruments 5 23 Chapter 5 Counters Single Pulse Generation The counter can output a single pulse The pulse appears on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is arme
33. times When the Filter Clock has sampled the signal high on N consecutive edges the low to high transition is propagated to the rest of the circuit The value of N depends on the filter setting as shown in Table 4 1 Table 4 1 Selectable PFI Filter Settings Max Pulse Min Pulse Width Filter Setting Filter Clock Jitter Width to Pass to Not Pass 112 5 ns 80 MHz 12 5 ns 112 5 ns 100 ns short 6 4 us 80 MHz 12 5 ns 6 4 us 6 3875 us medium 2 56 ms high 100 kHz 10 us 2 56 ms 2 55 ms Custom User 1 Filter Tees Taser 1 Filter configurable Clock Clock period period Pulse widths are nominal values the accuracy of the chassis timebase and I O distortion will affect these values National Instruments 4 15 Chapter 4 Digital Input Output and PFI On power up the filters are disabled Figure 4 7 shows an example of a low to high transition on an input that has a custom filter set to N 5 Figure 4 7 PFI Filter Example PFI Terminal Filtered input goes high when terminal 1 123 4 1 2 3 4 5 is sampled high on Filter Clock _ J J J J J J five consecutive filter clocks Filtered Input 4 16 ni com Counters The cDAQ chassis has four general purpose 32 bit counter timers and one frequency generator The general purpose counter timers can be used for many measurement and pulse generati
34. to the default False Figure 5 30 Retriggerable Single Pulse Generation False Counter Load Values 43210210 43210210 GATE Start Trigger OUT SOURCE _ IL Note The minimum time between the trigger and the first active edge is two ticks of the source For information about connecting counter signals refer to the Default Counter Timer Routing section Continuous Pulse Train Generation This function generates a train of pulses with programmable frequency and duty cycle The pulses appear on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is armed to the beginning of the pulse train The delay is measured in terms of a number of active edges of the Source input 5 26 ni com NI cDAQ 9188XT User Manual You specify the high and low pulse widths of the output signal The pulse widths are also measured in terms of a number of active edges of the Source input You also can specify the active edge of the Source input rising or falling The counter can begin the pulse train generation as soon as the counter is armed or in response to a hardware Start Trigger You can route the Start Trigger to the Gate input of the counter You also can use the Gate input of the counter as a Pause Trigger if it is not used as a Start Trigger
35. year membership in the Standard Service Program SSP with the purchase of most software products and bundles including NI Developer Suite NI also offers flexible extended contract options that guarantee your SSP benefits are available without interruption for as long as you need them Visit ni com ssp for more information For information about other technical support options in your area visit ni com services or contact your local office at ni com contact Training and Certification Visit ni com training for training and certification program information You can also register for instructor led hands on courses at locations around the world System Integration If you have time constraints limited in house technical resources or other project challenges National Instruments Alliance Partner members can help To learn more call your local NI office or visit ni com alliance Declaration of Conformity DoC A DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification e Calibration Certificate If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration National Instruments B 1 Appendix B Technical Support
36. 3 Optional Mount the cDAQ chassis to a panel wall or DIN rail or attach the desktop mounting kit as described in the Mounting the cDAQ Chassis section 4 Attacharing lug toa 1 31 mm 16 AWG or larger wire Connect the ring lug to the chassis ground terminal on the side of the cDAQ chassis using the chassis grounding screw as shown in Figure 1 2 Attach the other end of the wire to the grounding electrode system of your facility Refer to the Chassis Grounding Screw section for more information about making this connection 2 Note Ifyou use shielded cabling to connect to a C Series I O module with a plastic connector you must attach the cable shield to the chassis grounding terminal using 1 31 mm 16 AWG or larger wire Use shorter wire for better EMC performance 1 4 ni com NI cDAQ 9188XT User Manual Figure 1 2 Ring Lug Attached to Chassis Ground Terminal 5 Make sure that no signals are connected to the C Series I O module Align the C Series I O module with the cDAQ chassis slot Squeeze both C Series I O module latches insert the I O module into the module slot and press until both latches lock the module in place 8 Wire the C Series I O module as indicated in the C Series module documentation 1 Note Connect I O cable shields to the chassis ground terminal using the chassis grounding screw shown in Figure 1 2 unless otherwise specified in the C Series module documentation Refer to the Chassis Groun
37. 5 Counters You can route the pause trigger to the Gate input of the counter You can configure the counter to pause counting when the pause trigger is high or when it is low Figure 5 3 shows an example of on demand edge counting with a pause trigger Figure 5 3 Single Point On Demand Edge Counting with Pause Trigger Counter Armed Pause Trigger Pause When Low AAAA O 1 2 3 4 5 SOURCE Counter Value 0 Buffered Sample Clock Edge Counting With buffered edge counting edge counting using a sample clock the counter counts the number of edges on the Source input after the counter is armed The value of the counter is sampled on each active edge of a sample clock and stored in the FIFO The STC3 transfers the sampled values to host memory using a high speed data stream The count values returned are the cumulative counts since the counter armed event That is the sample clock does not reset the counter You can configure the counter to sample on the rising or falling edge of the sample clock Figure 5 4 shows an example of buffered edge counting Notice that counting begins when the counter is armed which occurs before the first active edge on Sample Clock Figure 5 4 Buffered Sample Clock Edge Counting Counter Armed Sample Clock Sample on Rising Edge f source LLA ALFALFA Counter Value 0 LTT el jvj N Buffer
38. 6 STC3 1 21 support technical B 1 synchronization modes 5 39 100 MHz source 5 40 external source less than 40 MHz 5 40 internal source less than 40 MHz 5 40 T technical support B 1 training and certification NI resources B 1 trigger arm start 5 38 pause 5 38 start 5 38 troubleshooting device connectivity 1 15 NI resources B 1 two signal edge separation measurement 5 21 buffered 5 22 single 5 22 NI cDAQ 9188XT User Manual U unpacking 1 4 using the cDAQ chassis 1 20 W watchdog timer 3 6 4 13 5 31 Web resources B 1 wireless networks 1 15 X X1 encoding 5 19 X2 encoding 5 19 X4 encoding 5 19 National Instruments l 5
39. AQ Assistant from MAX or from within Visual Studio You can use Measurement Studio to generate the configuration code based on your task or channel Refer to the DAQ Assistant Help for additional information about generating code The NI Measurement Studio Help is fully integrated with the Microsoft Visual Studio help To view this help file from within Visual Studio select Measurement Studio NI Measurement Studio Help For information related to developing with NI DAQm x refer to the following topics within the NI Measurement Studio Help e For step by step instructions on how to create an NI DAQmx application using the Measurement Studio Application Wizard and the DAQ Assistant refer to Walkthrough Creating a Measurement Studio NI DAQmx Application e For help with NI DAQmx methods and properties refer to the NationalInstruments DAQmx namespace and the NationalInstruments DAQmx ComponentModel namespace e For conceptual help with NI DAQmx refer to Using the Measurement Studio NI DAQmx NET Library and Creating Projects with Measurement Studio NI DAQmx e For general help with programming in Measurement Studio refer to Getting Started with the Measurement Studio Class Libraries To create an NI DAQm x application using Visual Basic NET or Visual C follow these general steps 1 In Visual Studio select File New Project to launch the New Project dialog box 2 Choose a programming language Visual C or Visual Basic NE
40. All lines on a module must share the same filter configuration When the filter is enabled the chassis samples the inputs with a user configured Filter Clock derived from the chassis timebase This is used to determine whether a pulse is propagated to the rest of the system However the filter also introduces jitter onto the input signal In NI DAQmx the filter is programmed by setting the minimum pulse width Tp that will pass the filter and is selectable in 25 ns increments The appropriate Filter Clock is selected by the driver Pulses of length less than 1 2 Tp will be rejected and the filtering behavior of lengths between 1 2 Tp and 1 Tp are not defined because they depend on the phase of the Filter Clock relative to the input signal Figure 4 3 shows an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on consecutive rising edges the low to high transition is propagated to the rest of the circuit Figure 4 3 Filter Example Digital Input PO x i 1 1 1 1 2 1 2 Filter Clock Filtered Input Getting Started with DI Applications in Software You can use the cDAQ chassis in the following dig
41. Analog Output Triggering Signals section of Chapter 3 Analog Output The Digital Input Triggering Signals section of Chapter 4 Digital Input Output and PFI The Digital Output Triggering Signals section of Chapter 4 Digital Input Output and PFI e Independent Data Streams The cDAQ chassis supports seven independent high speed data streams which allow for up to seven simultaneous hardware timed tasks such as analog input analog output buffered counter timers and hardware timed digital input output National Instruments 1 21 Chapter 1 Getting Started with the cDAQ Chassis 1 22 PFI Signals tThe PFI signals provide access to advanced features such as triggering synchronization and counter timers You can also enable a programmable debouncing filter on each PFI signal that when enabled samples the input on each rising edge ofa filter clock PFI signals are available through parallel digital input and output modules installed in up to two chassis slots and through the two PFI terminals provided on the cDAQ chassis Refer to the PFI section of Chapter 4 Digital Input Output and PFT for more information Flexible Counter Timers The cDAQ chassis includes four general purpose 32 bit counter timers that can be used to count edges measure pulse widths measure periods and frequencies and perform position measurements encoding In addition the counter timers can generate pulses pulse trains and square waves with adj
42. Chapter 4 Digital Input Output and PFI Static DIO Each of the DIO lines can be used as a static DI or DO line You can use static DIO lines to monitor or control digital signals on some C Series I O modules Each DIO line can be individually configured as a digital input DI or digital output DO if the C Series I O module being used allows such configuration All samples of static DI lines and updates of static DO lines are software timed Digital Input You can acquire digital waveforms using parallel digital modules The DI waveform acquisition FIFO stores the digital samples The cDAQ chassis samples the DIO lines on each rising or falling edge of the DI Sample Clock signal Digital Input Triggering Signals A trigger is a signal that causes an action such as starting or stopping the acquisition of data When you configure a trigger you must decide how you want to produce the trigger and the action you want the trigger to cause The cDAQ chassis supports three types of digital triggering internal software digital triggering external digital triggering and internal digital triggering Three triggers are available Start Trigger Reference Trigger and Pause Trigger An analog or digital trigger can initiate these three trigger actions Up to two C Series parallel digital input modules can be used in any chassis slot to supply a digital trigger To find your module triggering options refer to the documentation included with your C Se
43. I O modules provide built in signal conditioning and screw terminal spring terminal BNC D SUB or RJ 50 connectors A wide variety of I O types are available allowing you to customize the cDAQ system to meet your application needs C Series I O modules are hot swappable and automatically detected by the cDAQ chassis T O channels are accessible using the NI DAQmx driver software Because the modules contain built in signal conditioning for extended voltage ranges or industrial signal types you can usually make your wiring connections directly from the C Series I O modules to your sensors actuators In most cases the C Series I O modules provide isolation from channel to ground and channel to channel For more information about which C Series I O modules are compatible with the cDAQ chassis refer to the Developer Zone document C Series Support in NI DAQmx To access this Developer Zone document go to ni com info and enter the Info Code rdcdaq 1 20 ni com NI cDAQ 9188XT User Manual Parallel versus Serial DIO Modules Digital I O module capabilities are determined by the type of digital signals that the module is capable of measuring or generating e Serial digital I O modules are designed for signals that change slowly and are accessed by software timed reads and writes e Parallel digital I O modules are for signals that change rapidly and are updated by either software timed or hardware timed reads and writes For more
44. I PS 9 desktop power supply 780703 01 12 VDC 1 25 A 100 to 240 VAC input 0 to 70 C derated 0 27 W C above 40 C NI 9901 desktop mounting kit 779473 01 NI 9905 panel mount kit 779558 01 NI 9915 DIN rail mounting kit 779018 01 2 pos screw terminal kit for power supply connection qty 4 780702 01 CAT 5E Ethernet cable shielded 2 m 5 m and 10 m lengths 151733 02 05 10 Removing I O Modules from the cDAQ Chassis Complete the following steps to remove a C Series I O module from the cDAQ chassis 1 Make sure that no I O side power is connected to the I O module If the system is in a nonhazardous location the chassis power can be on when you remove I O modules 2 Squeeze the latches on both sides of the module and pull the module out of the chassis National Instruments 1 19 Chapter 1 Getting Started with the cDAQ Chassis Using the cDAQ Chassis The cDAQ system consists of three parts C Series I O module s the cDAQ module interface and the STC3 as shown in Figure 1 11 These components digitize signals perform D A conversions to generate analog output signals measure and control digital I O signals and provide signal conditioning Figure 1 11 Block Diagram C Series I O Module 4 gt A cDAQ Module Ethernet Interface STCS lt gt Network C Series V O Module Chassis PFI Terminals C Series I O Module National Instruments C Series
45. Includes overview information and a tutorial to learn how to take an NI DAQmx measurement in LabVIEW using the DAQ Assistant VI and Function Reference Measurement I O VIs and Functions DAQmx Data Acquisition VIs and Functions Describes the LabVIEW NI DAQmx VIs and functions Property and Method Reference NI DAQmx Properties Contains the property reference e Taking Measurements Contains the conceptual and how to information you need to acquire and analyze measurement data in LabVIEW including common measurements measurement fundamentals NI DAQmx key concepts and device considerations LabWindows CVI The Data Acquisition book of the LabWindows CVI Help contains Taking an NI DAQmx Measurement in LabWindows CVI which includes step by step instructions about creating a measurement task using the DAQ Assistant In LabWindows CVI select Help Contents then select Using LabWindows CVI Data Acquisition This book also contains information about accessing detailed information through the N DAQmx Help A 2 ni com NI cDAQ 9188XT User Manual The NI DAQm x Library book of the LabWindows CVI Help contains API overviews and function reference for NI DAQmx Select Library Reference NI DAQmx Library in the LabWindows CVI Help Measurement Studio If you program your NI DAQmx supported device in Measurement Studio using Visual C or Visual Basic NET you can interactively create channels and tasks by launching the D
46. LI UU 6 Buffer When CI Freq EnableAveraging is set to false the frequency measurement returns the frequency of the pulse just before the sample clock This single measurement is a single MUI frequency measurement and is not an average between clocks as shown in Figure 5 16 Figure 5 16 Sample Clocked Buffered Frequency Measurement Non Averaging iaae Ah Fp sowe FULTUULJULIZULIUUIULIUULIUU UUIUEL UU Us With sample clocked frequency measurements ensure that the frequency to measure is twice as fast as the sample clock to prevent a measurement overflow Choosing a Method for Measuring Frequency The best method to measure frequency depends on several factors including the expected frequency of the signal to measure the desired accuracy how many counters are available and how long the measurement can take For all frequency measurement methods assume the following f fk measurement time T 5 14 ni com is the frequency to be measured if no error is the known source or gate frequency is the time it takes to measure a single sample NI cDAQ 9188XT User Manual Divide down N is the integer to divide down measured frequency only used in fs large range two counters is the sampl
47. Manual Each Convert Clock signals the acquisition of a single channel from that module The Convert Clock rate depends on the module being used the number of channels used on that module and the system Sample Clock rate The driver chooses the fastest conversion rate possible based on the speed of the A D converter for each module and adds 10 ps of padding between each channel to allow for adequate settling time This scheme enables the channels to approximate simultaneous sampling Ifthe AI Sample Clock rate is too fast to allow for 10 us of padding NI DAQmx selects a conversion rate that spaces the AI Convert Clock pulses evenly throughout the sample NI DAQm x uses the same amount of padding for all the modules in the task To explicitly specify the conversion rate use the ActiveDevs and AI Convert Clock Rate properties using the DAQmx Timing property node or functions Simultaneous Sample and Hold Modules Simultaneous sample and hold SSH C Series analog input modules contain multiple A D converters or circuitry that allows all the input channels to be sampled at the same time These modules sample their inputs on every Sample Clock pulse Sigma Delta Modules Sigma delta C Series analog input modules function much like SSH modules but use A D converters that require a high frequency oversample clock to produce accurate synchronized data Some sigma delta modules in the cDAQ chassis automatically share a single oversample clock to sy
48. NI cDAQ 9188XT User Manual NI CompactDAQ Extended Temperature Rugged Eight Slot Ethernet Chassis Fran ais Deutsch AG BaH EPX ni com manuals August 2013 Qy NATIONAL 373929B 01 p INSTRUMENTS Worldwide Technical Support and Product Information ni com Worldwide Offices Visit ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information refer to the Technical Support and Professional Services appendix To comment on National Instruments documentation refer to the National Instruments Web site at ni com info and enter the Info Code feedback 2013 National Instruments All rights reserved Important Information Warranty NI devices are warranted against defects in materials and workmanship for a period of one year from the invoice date as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from
49. Series I O module or go toni com manuals National Instruments A 1 Appendix A Where to Go from Here NI DAQmx The NI DAQ Readme lists which devices ADEs and NI application software are supported by this version of NI DAQ Select Start All Programs National Instruments NI DAQ NI DAQ Readme The N DAQmx Help contains API overviews general information about measurement concepts key NI DAQmx concepts and common applications that are applicable to all programming environments Select Start All Programs National Instruments NI DAQ NI DAQmx Help LabVIEW If you are a new user use the Getting Started with LabVIEW manual to familiarize yourself with the LabVIEW graphical programming environment and the basic LabVIEW features you use to build data acquisition and instrument control applications Open the Getting Started with LabVIEW manual by selecting Start All Programs National Instruments LabVIEW LabVIEW Manuals or by navigating to the labview manuals directory and opening LV_Getting_Started pdf Use the LabVIEW Help available by selecting Help LabVIEW Help in LabVIEW to access information about LabVIEW programming concepts step by step instructions for using LabVIEW and reference information about LabVIEW VIs functions palettes menus and tools Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI DAQmx e Getting Started with LabVIEW Getting Started with DAQ
50. T and then select Measurement Studio to see a list of project templates 3 Select NI DAQ Windows Application You add DAQ tasks as part of this step Choose a project type You add DAQ tasks as a part of this step ANSI C without NI Application Software The NI DAQmx Help contains API overviews and general information about measurement concepts Select Start All Programs National Instruments NI DAQ NI DAQmx Help The NI DAQmx C Reference Help describes the NI DAQmx Library functions which you can use with National Instruments data acquisition devices to develop instrumentation acquisition and control applications Select Start All Programs National Instruments NI DAQ Text Based Code Support NI DAQm x C Reference Help National Instruments A 3 Appendix A Where to Go from Here NET Languages without NI Application Software With the Microsoft NET Framework you can use NI DAQmx to create applications using Visual C and Visual Basic NET without Measurement Studio Refer to the NI DAQmx Readme for specific versions supported Training Courses If you need more help getting started developing an application with NI products NI offers training courses To enroll in a course or obtain a detailed course outline refer to ni com training Technical Support on the Web For additional support refer to ni com support or zone ni com Note You can download these documents at ni com manuals Many DAQ specific
51. ULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of othe
52. URES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Contents Chapter 1 Getting Started with the cDAQ Chassis Safety Guidelines 3 cvccsccsccsccvccsccsccssed sacs deeds gusccbesscvncescousenced ces ii ii 1 2 Safety Guidelines for Haz
53. and NI 9474 modules Consult the module specifications for the expected I O behavior Note Restarting or re reserving the chassis may lead to undefined transient behavior on the outputs of any modules so these operations are not recommended as means of a watchdog expiration event recovery Note No other operations may be running on the cDAQ chassis while the watchdog timer task is being started this includes all DAQmx tasks calibration of modules and routing and configuration of signals on the chassis After the watchdog timer task starts DAQmx tasks can be started and stopped and other operations can be performed 3 6 ni com NI cDAQ 9188XT User Manual Getting Started with AO Applications in Software You can use the cDAQ chassis in the following analog output applications e Single point on demand generation e Finite generation e Continuous generation e Waveform generation For more information about programming analog output applications and triggers in software refer the LabVIEW Help or to the NI DAQmx Help National Instruments 3 7 Digital Input Output and PFI This chapter describes the digital input output DIO and Programmable Function Interface PFI functionality available on the cDAQ chassis Refer to the Digital Input Output and PFI sections Digital Input Output To use digital I O insert a digital I O C Series module into any slot on the cDAQ chassis The VO specifications such as number
54. ardous Locations c cceseeeeeeeeeeeeees 1 2 Special Conditions for Hazardous Locations Use in Europe 1 2 Electromagnetic Compatibility Guidelines ccceseseesecseeseereereeteeeeees 1 3 Special Guidelines for Marine Applications 00 0 0 ccceceeceecreeeceeceeeeeseserseeeeeeeaenees 1 3 Unpacking non enai E A T in tuna ia sanasndunses oes okeoas cleo eased ested auth eases 1 4 Installing the CDA Q Chassis ennnen riene e rin na aaie Ee 1 4 Wiring Power to the CDAQ Chassis s s eseeseseesseseseeeessreertrsesrsrstststsrerersereeressrreenrsenrereeees 1 7 Troubleshooting Chassis Connectivity 1 9 Reserving the Chassis in MAX 1 9 Mounting the CDAQ Chassis cceeeeeseees 1 10 Using the cDAQ Chassis on a Desktop cccccceessescescesceseeeeceeceeceaeaeeaeaecaecaeeneeneeas 1 10 NI 9901 Desktop Kit Zerin iedereens eai kan inann ea AEE a e 1 10 Mounting the cDAQ Chassis on a Panel ccececesceseeseeceecececesescecsecseceeeaeeeeeeeees 1 11 Panel Mounting with a Panel Mount Kit eceseeseeseeseeseeseeseeeeesceseeeeceeeeees 1 11 Panel Mounting without a Panel Mount Kit Mounting the cDAQ Chassis on a DIN Rail NI cDAQ Chassis Features ccccccccssseseesseeseeeees Chassis Grounding Screw ccccsesesecseeseeseeneeeeeeneees Ethernet Cabling esta chs niec aa odes eed AENEAS ReSet Button sorn soene aa dasans cesses AA as ua cuteaasenaduve AA A ATE ASEAS PoOWer CONMCCIO mscrireri
55. ardware timed analog output 3 2 digital output 4 9 continuous pulse train 5 26 digital output data 4 9 frequency 5 30 hardware timed analog output 3 2 digital output 4 9 pulse for ETS 5 32 pulse train 5 25 retriggerable single pulse 5 25 simple pulse 5 23 single pulse 5 24 single pulse with start trigger 5 24 software timed analog output 3 1 digital output 4 9 getting started AI applications in software 2 7 AO applications in software 3 7 DI applications in software 4 7 DO applications in software 4 14 NI cDAQ 9188XT User Manual H hardware timed generations analog output 3 2 digital output 4 9 help technical support B 1 implicit buffered pulse width measurement 5 6 semi period measurement 5 9 installation 1 4 instrument drivers NI resources B 1 internal source less than 40 MHz 5 40 K KnowledgeBase B 1 L LEDs 1 16 LINK ACT LED 1 16 M MAX chassis reservation 1 9 measurements buffered two signal edge separation 5 22 choosing frequency 5 14 frequency 5 10 implicit buffered pulse width 5 6 implicit buffered semi period 5 9 period 5 18 position 5 18 pulse width 5 5 semi period 5 9 single pulse width 5 5 single semi period 5 9 single two signal edge separation 5 22 two signal edge separation 5 21 using quadrature encoders 5 19 using two pulse encoders 5 20 National Instruments l 3 Index measuring high frequency with two counters 5 11 la
56. ask update DO Sample Clock can be generated from external or internal sources as shown in Figure 4 4 Figure 4 4 Digital Output Timing Options PFI Analog Comparison Event DO Sample Clock PFI Ctr n Internal Output Analog Comparison DO Sample Clock Event Timebase Programmable 20 MHz Timebase Clock Divider 80 MHz Timebase 4 100 kHz Timebase Routing DO Sample Clock to an Output Terminal You can route DO Sample Clock to any output PFI terminal DO Sample Clock is active high by default DO Sample Clock Timebase Signal The DO Sample Clock Timebase do SampleClockTimebase signal is divided down to provide a source for DO Sample Clock DO Sample Clock Timebase can be generated from external or internal sources and is not available as an output from the chassis DO Start Trigger Signal Use the DO Start Trigger do StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command If you are using an internal sample clock you can specify a delay from the start trigger to the first sample For more information refer to the NJ DAQmx Help Using a Digital Source To use DO Start Trigger specify a source and a rising or falling edge The source can be one of the following signals e A pulse initiated by host software e Any PFI terminal e Al Reference Trigger e Al Start Trigger The source al
57. ations and user guides manuals are available as PDFs You must have Adobe Reader 7 0 or later PDF 1 6 or later installed to view the PDFs Refer to the Adobe Systems Incorporated Web site at www adobe com to download Adobe Reader Refer to the National Instruments Product Manuals Library at ni com manuals for updated documentation resources A 4 ni com Technical Support and Professional Services Log in to your National Instruments ni com User Profile to get personalized access to your services Visit the following sections of ni com for technical support and professional services e Support Technical support at ni com support includes the following resources Self Help Technical Resources For answers and solutions visit ni com support for software drivers and updates a searchable KnowledgeBase product manuals step by step troubleshooting wizards thousands of example programs tutorials application notes instrument drivers and so on Registered users also receive access to the NI Discussion Forums at ni com forums NI Applications Engineers make sure every question submitted online receives an answer Standard Service Program Membership This program entitles members to direct access to NI Applications Engineers via phone and email for one to one technical support as well as exclusive access to self paced online training modules at ni com self paced training All customers automatically receive a one
58. ceseseesereeeeees 5 6 Pulse Measurement s nioa a eae eaa E E serge ued a a Single Pulse Measurement cccccecscescescesceseeeeeseescceeceeceeceaeeaesaesaecaecaeeaeeaeeas Implicit Buffered Pulse Measurement Sample Clocked Buffered Pulse Measurement Semi Period Measurement 0 0 00 cesses seceeereeeeeeees Single Semi Period Measurement Implicit Buffered Semi Period Measurement Pulse versus Semi Period Measurement scceeccseseeecseeeeseserseesesenseseeseens National Instruments vii Contents Frequency Measurement meoo Eee A a a a E AA EAEE Low Frequency with One Counter High Frequency with Two Counters cccccccsessessessesseeseescesceeceseeseeeeteceeceeeaes 5 11 Large Range of Frequencies with Two Counters ccceccessescesceseeseeeeceeceeeeaes 5 12 Sample Clocked Buffered Frequency Measurement c ccsccseesseseeseeeeeeeees 5 13 Choosing a Method for Measuring Frequency ccceccescesceseeeeeeeeeeceeceeceeceaes 5 14 Which Method Is Best ic f eccsc pence ceccic sepcetecacesdiaceysssdenenstenacasdededesetedeeestendees 5 16 Period Measurements sich csscosecscosschsssdoustasdepesenabass vanes heetdh cess EENEN SE SEA sania 5 18 Position Measurement cccceccecceseesessesseesecsecsecsecseeseeseeseeseeeeeeecececeeceaeeaeeaeeaeenes 5 18 Measurements Using Quadrature Encoders eseeeseseeesseeectesereceseeesseseeeeees 5 19
59. ck e DO Sample Clock e AI Sample Clock ai SampleClock te0 SampleClock tel SampleClock e Al Convert Clock e AO Sample Clock e DI Change Detection output Several other internal signals can be routed to Counter n Sample Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source You can route any of the following signals as Counter n Sample Clock e Any PFI terminal e Analog Comparison Event You can sample data on the rising or falling edge of Counter n Sample Clock Routing Counter n Sample Clock to an Output Terminal You can route Counter n Sample Clock out to any PFI terminal The PFI circuitry inverts the polarity of Counter n Sample Clock before driving the PFI terminal Counter n Internal Output and Counter n TC Signals The Counter n Internal Output signal changes in response to Counter n TC The two software selectable output options are pulse output on TC and toggle output on TC The output polarity is software selectable for both options With pulse or pulse train generation tasks the counter drives the pulse s on the Counter n Internal Output signal The Counter n Internal Output signal can be internally routed to be a counter timer input or an external source for AI AO DI or DO timing signals Routing Counter n Internal Output to an Output Terminal You can route Counter n Internal Output to any PFI terminal F
60. cy and nature of the output signal Go to ni com support for more information about minimizing glitches Watchdog Timer The watchdog timer is a software configurable feature used to set critical outputs to expiration states in the event of a software failure a system crash or any other loss of communication between the application and the cDAQ chassis When the watchdog timer is enabled if the cDAQ chassis does not receive a watchdog reset software command within the time specified for the watchdog timer the outputs go to a user defined expiration state and remain in that state until the watchdog timer is disarmed by a device reset After the watchdog timer expires the cDAQ chassis cannot perform any operation until the cDAQ chassis is reset You can set the watchdog timer timeout period to specify the amount of time that must elapse before the watchdog timer expires The counter on the watchdog timer is configurable up to 232 1 x 25 ns approximately 107 seconds before it expires When a watchdog timer expires analog output digital output and counter output changes may be configured to transition to an expiration state Resetting the chassis after a watchdog expiration event results in all module outputs defaulting to power up or startup states as defined in the module specifications Note Resetting the chassis after a watchdog expiration event may result in undefined transient behavior on the outputs of the NI 9269 NI 9401
61. d You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between the two active edges of the Gate signal You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Period measurements return the inverse results of frequency measurements Refer to the Frequency Measurement section for more information Position Measurement You can use the counters to perform position measurements with quadrature encoders or two pulse encoders You can measure angular position with X1 X2 and X4 angular encoders Linear position can be measured with two pulse encoders You can choose to do either a single point on demand position measurement or a buffered sample clock position measurement You must arm a counter to begin position measurements Refer to the following sections for more information about the cDAQ chassis position measurement options e Measurements Using Quadrature Encoders Measurements Using Two Pulse Encoders Buffered Sample Clock Position Measurement 5 18 ni com NI cDAQ 9188XT User Manual Measurements Using Quadrature Encoders The counters can perform measurements
62. d task can have channels from multiple modules in the same chassis Analog Output Data Generation Methods When performing an analog output operation you either can perform software timed or hardware timed generations Hardware timed generations must be buffered Software Timed Generations With a software timed generation software controls the rate at which data is generated Software sends a separate command to the hardware to initiate each DAC conversion In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing out a single value such as a constant DC voltage The following considerations apply to software timed generations e Ifany AO channel on a module is used in a hardware timed waveform task no channels on that module can be used in a software timed task e You can configure software timed generations to simultaneously update e Only one simultaneous update task can run at a time e Software timed generations are limited to 16 channels Refer to NJ cDAQ 9188XT Specifications for more information a Note Simultaneous update is not limited because it uses hardware timed generation with onboard regeneration e A hardware timed AO task and a simultaneous update AO task cannot run at the same time National Instruments 3 1 Chapter 3 Analog Output Hardware Timed Generations Wit
63. d to the beginning of the pulse The delay is measured in terms of a number of active edges of the Source input You can specify a pulse width The pulse width is also measured in terms of a number of active edges of the Source input You also can specify the active edge of the Source input rising or falling Figure 5 26 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source Figure 5 26 Single Pulse Generation Counter Armed i M SOURCE OUT Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal The pulse appears on the Counter n Internal Output signal of the counter You can specify a delay from the Start Trigger to the beginning of the pulse You also can specify the pulse width The delay is measured in terms of a number of active edges of the Source input You can specify a pulse width The pulse width is also measured in terms of a number of active edges of the Source input You can also specify the active edge of the Source input rising and falling Figure 5 27 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source Figure 5 27 Single Pulse Generation with Start Trigger GATE i Start Trigger SOURCE FLTT a OUT __
64. ding Screw section for more information about making this connection 9 Use a standard Category 5 Ethernet cable to connect the cDAQ chassis to an Ethernet network Connect one end to the RJ 45 Ethernet port on the chassis and the other end directly to your computer or any network connection on the same subnet as your computer Refer to the section for information about the Ethernet cable 10 Wire your external power source as outlined in the Wiring Power to the cDAQ Chassis section The cDAQ chassis requires an external power supply that meets the specifications listed in the NJ cDAQ 9188XT Specifications The POWER and STATUS LEDs light The POWER LED lights as long as power is being supplied to the cDAQ chassis The STATUS LED turns off after firmware boots Refer to the LEDs section for information about the LEDs on the cDAQ chassis You can either use a standard Category 5 Ethernet cable or an Ethernet crossover cable to connect the cDAQ chassis directly to your computer National Instruments 1 5 Chapter 1 Getting Started with the cDAQ Chassis 11 To add the chassis double click the Measurement amp Automation icon on the desktop to open MAX Expand Devices and Interfaces Network Devices e Ifthe connection is on your local subnet the chassis automatically appears in the list of available devices Right click the cDAQ chassis and select Add Device If the connection is not on your local subnet right click Netwo
65. e Pulse Width Measurement e Pulse Measurement Semi Period Measurement Frequency Measurement e Period Measurement Position Measurement Counting Edges In edge counting applications the counter counts edges on its Source after the counter is armed You can configure the counter to count rising or falling edges on its Source input You also can control the direction of counting up or down as described in the Controlling the Direction of Counting section The counter values can be read on demand or with a sample clock Refer to the following sections for more information about edge counting options Single Point On Demand Edge Counting Buffered Sample Clock Edge Counting Single Point On Demand Edge Counting With single point on demand edge counting the counter counts the number of edges on the Source input after the counter is armed On demand refers to the fact that software can read the counter contents at any time without disturbing the counting process Figure 5 2 shows an example of single point edge counting Figure 5 2 Single Point On Demand Edge Counting Counter Armed FL FLF 1 2 3 4 5 SOURCE Counter Value 0 You also can use a pause trigger to pause or gate the counter When the pause trigger is active the counter ignores edges on its Source input When the pause trigger is inactive the counter counts edges normally National Instruments 5 3 Chapter
66. e NI 9905 panel mount kit to mount the cDAQ chassis on a panel A Caution Remove the C Series I O module s from the cDAQ chassis before you mount the chassis to the panel After the cDAQ chassis is mounted you can reinsert the C Series module s Align the cDAQ chassis on the panel mount accessory and attach the chassis to the accessory with two M4 x 17 screws included in the kit as shown in Figure 1 7 You must use these screws because they are the correct depth and thread for the panel You can then attach the panel mount accessory to a wall or panel with the two holes or the four keyholes with M4 M5 No 8 or No 10 panhead screws National Instruments does not National Instruments 1 11 Chapter 1 Getting Started with the cDAQ Chassis provide these screws with the chassis Refer to the documentation included with the panel mount kit for more detailed dimensions Figure 1 7 NI cCDAQ Chassis Panel Mount Dimensions and Installation 330 2 mm gt a 13 00 in r SS e A A t 2 3 4 5 6 z 6 0 0 8 8 8 A A aA 1 rer T 28 1mm i 1 14 in Pr am 1 12 ni com NI cDAQ 9188XT User Manual Panel Mounting without a Panel Mount Kit You can mount the cDAQ chassis directly on a flat surface using the mounting holes Refer to the NI cDAQ 9188XT Specifications for mounting dimensions for the cDAQ chassis Drill appropriat
67. e a user defined pulse train Finite Buffered Sample Clocked Pulse Train Generation This function generates a predetermined number of pulse train updates Each point you write defines pulse specifications that are updated with each sample clock When a sample clock occurs the current pulse idle followed by active finishes generation and the next pulse updates with the next sample specifications A Note When the last sample is generated the pulse train continues to generate with these specifications until the task is stopped 5 28 ni com NI cDAQ 9188XT User Manual Table 5 7 and Figure 5 33 detail a finite sample clocked generation of three samples where the pulse specifications from the create channel are two ticks idle two ticks active and three ticks initial delay Table 5 7 Finite Buffered Sample Clocked Pulse Train Generation Sample Idle Ticks Active Ticks 1 3 3 2 2 2 3 3 3 Figure 5 33 Finite Buffered Sample Clocked Pulse Train Generation Counter Armed Sample Clock Counter Load Values 2101010371021 1 021021021 10 91010210210 U U Source Out There are several different methods of continuous generation that control what data is written The
68. e chassis on a standard 35 mm DIN rail To mount the chassis on a DIN rail fasten the DIN rail clip to the chassis using a number 2 Phillips screwdriver and two M4 x 17 screws included in the kit National Instruments 1 13 Chapter 1 Getting Started with the cDAQ Chassis Make sure the DIN rail kit is installed as shown in Figure 1 9 Figure 1 9 cDAQ chassis DIN Rail Installation Clip the chassis onto the DIN rail with the larger lip of the DIN rail clip positioned up as shown in Figure 1 10 Figure 1 10 DIN Rail Clip Parts Locator Diagram ye 1 DIN Rail Clip 2 DIN Rail Spring 3 DIN Rail When the DIN rail kit is properly installed the cDAQ chassis is centered on the DIN rail A Caution Remove the I O module s before removing the chassis from the DIN rail 1 14 ni com NI cDAQ 9188XT User Manual NI cDAQ Chassis Features The cDAQ chassis features a chassis grounding screw LEDs reset button Ethernet connector power connector and two PFI BNC connectors Refer to Figure 1 1 for locations of the cDAQ chassis features Chassis Grounding Screw A Caution To ensure the specified EMC performance the cDAQ chassis must be connected to the grounding electrode system of your facility using the chassis ground terminal To connect the cDAQ chassis to the grounding electrode system of your facility attach a ring lug to a 1 31 mm 16 AWG or larger stranded copper wire with a maximum length of 1 5 m 5 f
69. e clock rate only used in sample clocked frequency measurements Here is how these variables apply to each method summarized in Table 5 2 One counter With one counter measurements a known timebase is used for the source frequency fk The measurement time is the period of the frequency to be measured or 1 fx Two counter high frequency With the two counter high frequency method the second counter provides a known measurement time The gate frequency equals 1 measurement time Two counter large range The two counter larger range measurement is the same as a one counter measurement but now the user has an integer divide down of the signal An internal timebase is still used for the source frequency fk but the divide down means that the measurement time is the period of the divided down signal or N fx where N is the divide down Sample clocked For sample clocked frequency measurements a known timebase is counted for the source frequency fk The measurement time is the period of the sample clock fs Table 5 2 Frequency Measurement Methods Two Counter One High Variable Sample Clocked Counter Frequency Large Range Sk Known timebase Known l Known timebase timebase a ee gating period bie l l gating period N fs fx fx Max x D P i fXX f i JxX oon ae x 1 me fex E 1 PRR TAR Max error P EAN A f fk fx h ad ed 2 fix Bot f fr fe NX fk fe S Note Accuracy equatio
70. e holes in the mounting surface and align the chassis on the surface Then fasten the chassis to the surface using two M4 or No 8 panhead screws as shown in Figure 1 8 National Instruments does not provide these screws with the chassis Figure 1 8 Mounting the cDAQ Chassis Directly on a Flat Surface NATIONAL Oinstneenrs A Caution Make sure that no I O modules are in the chassis before removing it from the surface Mounting the cDAQ Chassis on a DIN Rail A Caution To maintain product performance and accuracy specifications when the ambient temperature is between 60 and 70 C you must mount the chassis horizontally to a metal panel or surface using the screw holes or the panel mount kit DIN mounting limits the device to 60 C maximum ambient operating temperature Measure the ambient temperature at each side of the CompactDAQ system 63 5 mm 2 5 in from the side and 25 4 mm 1 in from the rear cover of the system For further information about mounting configurations go to ni com info and enter the Info Code cdaqmounting You can use the NI 9915 DIN rail kit to mount the cDAQ chassis to a standard DIN rail For kit accessory ordering information refer to the pricing section of the cDAQ chassis product page at ni com The DIN rail mounting kit contains one clip for mounting th
71. e network Ifa connected chassis appears as disconnected in the configuration tree in MAX select Self Test or Reset Chassis If successful the chassis icon changes to blue Figure 1 5 MAX Icons and States Oo 1 Recognized but Disconnected from the Network 2 Recognized Present and Reserved on the Network For additional troubleshooting resources for the cDAQ chassis refer to the Finding a Network DAQ Device in MAX topic in the Measurement amp Automation Explorer Help for NI DAQmx Reserving the Chassis in MAX When the cDAQ chassis is connected to a network multiple users can access the chassis To perform any DAQ functionality on the C Series modules including reset chassis and self test you must reserve the cDAQ chassis in MAX Only one user at a time can reserve the cDAQ chassis If the cDAQ chassis was not reserved automatically after it was added Add Device you can reserve the cDAQ chassis in MAX by expanding Devices and Interfaces Network Devices selecting the chassis and clicking the Reserve Chassis button The Override Reservation dialog box appears when you attempt to explicitly reserve a chassis Agreeing to override the reservation forces the cDAQ chassis to be reserved by the current user National Instruments 1 9 Chapter 1 Getting Started with the cDAQ Chassis Mounting the cDAQ Chassis You can use the cDAQ chassis on a desktop or mount it to a panel wall or DIN rail For accessory orde
72. ecsecseeseesseseeeeeeeeeeeeeeeeceeceeeeeteeteeeeees 2 6 Using an Analog Source ccecececesessecsecsecsecseescesseseeeceeeeseeeeceeceseeseeeeaeeeeenees 2 6 Routing the Reference Trigger Signal to an Output Terminal 2 6 AI Pause Trigger Sigmal ccccssesssseesecsesseescescesceseesceseeseeseeeeseeseceeseeceeseaeeaeeaseaeease 2 6 Using a Digital Source 0 cee cececcecceseeseesecsecsecseescesseneeeeeeeeeeeeceeceeceseneseeeteees 2 6 Using an Analog Source aarne e e E E EEG E 2 7 Getting Started with AI Applications in Software s seseseeseseeseeessreessesesrerererrerrereeseree 2 7 Chapter 3 Analog Output Analog Output Data Generation Methods sssseesessssseseeesesssreerersssterstsesrsrersrserererseserees 3 1 Software Timed Generations Hardware Timed Generations Sar Buffered Analog Output 0 0 cccccecceccecceeceseeseesecsecsecaeeseeseeseeneeeeeeeeeeeeeceeeeeeeaees Analog Output Triggering Signals eeseeecsececeecseeeceeceesecsesenscsaesecsesesseeaeeenseseeeeees Analog Output Timing Signals 2 0 0 cccceceescescesceseeseesecseceecnecnceseesaeaeeeeeeeeeeeeeeeeeeeeeeeeees AO Sample Clock Signal cccccceccsescecesceseesesseeseceeceeceecesesaesaesaecaecaecaecaeeaeeneeneeas Routing AO Sample Clock to an Output Terminal cccceceeeeeeeeeceeeeteeees 3 3 AO Sample Clock Timebase Signal ccccccecssssescesceeceeceseseesesecaecaecaecaeeaeeneeneens 3 4 AO Start Trigger Signal cccccceesesesses
73. ed at 1000 Mbps Green On Connected at 100 Mbps E Off No Ethernet connection or 10 Mbps connection LINK ACT Green On Ethernet link Off No Ethernet connection Blinking Ethernet activity POWER Green On Power on Off Power off STATUS Yellow On Chassis firmware booting updating or resetting to factory default Off Normal operation 3 Blinks Firmware image corrupted update firmware through recovery utility To download the recovery utility go to ni com info and enter the Info Code cdaqrecoveryutility ACTIVE Green On A DAQ task is running on the chassis Off A DAQ task is not running on the chassis 1 16 ni com NI cDAQ 9188XT User Manual Ethernet Cabling Table 1 2 shows the standard Ethernet cable wiring connections for both normal and crossover cables Table 1 2 Ethernet Cable Wiring Connections Connector 2 Pin Connector 1 Normal Crossover 1 white orange white orange white green 2 orange orange green 3 white green white green white orange 4 blue blue blue 5 white blue white blue white blue 6 green green orange 7 white brown white brown white brown 8 brown brown brown Connector 1 Connector 2 Pin 1 gt Pin 8 Pin 1 ER Pin 8 National Instruments 1 17 Chapter 1 Getting Started with the cDAQ Chassis Reset Button The cDAQ chassis is equipped with a reset button Pressing the reset button results in the followi
74. ed in any chassis slot to supply a digital trigger An analog trigger can be supplied by some C Series analog modules Refer to the AO Start Trigger Signal and AO Pause Trigger Signal sections for more information about the analog output trigger signals Analog Output Timing Signals The cDAQ chassis features the following AO waveform generation timing signals e AO Sample Clock Signal e AO Sample Clock Timebase Signal AO Start Trigger Signal e AO Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section of Chapter 4 Digital Input Output and PFI for more information AO Sample Clock Signal The AO sample clock ao SampleClock signals when all the analog output channels in the task update AO Sample Clock can be generated from external or internal sources as shown in Figure 3 1 Figure 3 1 Analog Output Timing Options PFI PS Analog Comparison Event AO Sample Clock PFI Ctr n Internal Output Analog Comparison AO Sample Clock E P vent Timebase Programmable 20 MHz Timebase Clock Divider 80 MHz Timebase 100 kHz Timebase 4 Routing AO Sample Clock to an Output Terminal You can route AO Sample Clock to any output PFI terminal AO Sample Clock is active high by default National Instruments 3 3 Chapter 3 Analog Output AO Sample Clock Timebase Signal The AO Sample Clock Timebase ao SampleClockTimebase
75. eeeeeeeeeesceeeeseeeeeeeeteees 5 35 viii ni com NI cDAQ 9188XT User Manual Counter n A Counter n B and Counter n Z Signals c ccesesseeseeceeseeseceeeeseeneene 5 35 Routing Signals to A B and Z Counter Inputs ccc ceeceescecceseeseeeeeseeeeeeees 5 35 Routing Counter n Z Signal to an Output Terminal 0 eee eeeereeeeeeeeeee 5 35 Counter n Up_Down Signal Counter n HW Arm Signal Routing Signals to Counter n HW Aim Input Counter n Sample Clock Signal Using an Internal Source Using an External Sourceen iea ee E A a Routing Counter n Sample Clock to an Output Terminal Counter n Internal Output and Counter n TC Signals 0 0 eee Routing Counter n Internal Output to an Output Terminal Frequency Output Signal 0 0 cc ccecescesceseeeceseeeeceeceseeeesecneeseeneenee i Routing Frequency Output to a Terminal eee seeeeeeeeeeseeeeeeeenseeeeseees Default Counter Timer Routing Co nter Trig Serine sc sades ost n E N O EE E T R Other Counter Features nana te Hee a A e ee Cascading Counters PresCalin ge eseese Synchronization Modes 80 MHz Source Mode yii o i pe ene Ri A a dames External or Internal Source Less than 20 MHz Chapter 6 Digital Routing and Clock Generation Digital Routing Clock Routing ccccceccesseesessesscescescesceseeseeseesecseceeceeceeceaessesaesaesaesaesaecaecaecaecaeeaeeaeeseeeeeeeees 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase Appendix A Where to Go from Here
76. een edges on the Gate input but the counting does not start until the desired edge You can select whether to read the high pulse or low pulse first using the StartingEdge property in NI DAQmx National Instruments 5 7 Chapter 5 Counters Figure 5 9 shows an example of an implicit buffered pulse measurement Figure 5 9 Implicit Buffered Pulse Measurement Counter Armed Gate m O Source S LU UWL UL ULL LLL Ho t IHL H L 1 IHL HL Buffer 4 2 4 2 4 2 4 2 4 4 4j4 4 4 6 2 6 2 2 2 Sample Clocked Buffered Pulse Measurement A sample clocked buffered pulse measurement is similar to single pulse measurement but a buffered pulse measurement takes measurements over multiple pulses correlated to a sample clock The counter performs a pulse measurement on the Gate On each sample clock edge the counter stores the high and low ticks in the FIFO of the last pulse to complete The STC3 transfers the sampled values to host memory using a high speed data stream Figure 5 10 shows an example of a sample clocked buffered pulse measurement Figure 5 10 Sample Clocked Buffered Pulse Measurement
77. ent ec ci stsia astiessadenasceteeniaeiacovem erent RE n 4 8 Routing Change Detection Event to an Output Terminal eects 4 8 Change Detection Acquisition 0 ceceessescsseeceecseecseserscsaeeesscseescsaesenecsesetees Digital Output eu hi sais Digital Output Data Generation Methods Digital Output Triggering Signals e Digital Output Timing Signals 0 0 0 c cece ceceecesescenseeceeseeseeeeeseeseeseeeeteeteceeeees Watchdog Timer eeececcescessssssseesecsecsecsecasencesseseeeseeeeeseeseeseeseeseeeeeseeeeeeteeeeees Getting Started with DO Applications in Software ccccseseeeeeeeeeeeceteeees 4 14 Digital Input Output Configuration for NI 9401 oo ceceseeseeeesecseesecseceeeseeneeneees 4 14 PRI hs E E E E de cin T PFI Filters Chapter 5 Counters Counter Timing Engihessae siiri anart s ae r AA A EETA SANS 5 2 Counter Input Applications inenen naii aa en ES EKNE a 5 3 Counting Edge ooien E E EN EEA E A AS NEE a SEEE SE 5 3 Single Point On Demand Edge Counting s sesssessssessesesessesesssresesersssesess 5 3 Buffered Sample Clock Edge Counting eseesessesseessrsesseesssserssseressesesrrseses 5 4 Controlling the Direction of Counting 1 5 4 Pulse Width Measurement 00 3 5 Single Pulse Width Measurement 005 5 5 Implicit Buffered Pulse Width Measurement cccccsesseeseeseeseeseeeeeseeeeeeees 5 6 Sample Clocked Buffered Pulse Width Measurement c es
78. ent where the measurement is made on a continuous repetitive signal The prescaling counter cannot be read therefore you cannot determine how many edges have occurred since the previous rollover Prescaling can be used for event counting provided it is acceptable to have an error of up to seven or one ticks Prescaling can be used when the counter Source is an external signal Prescaling is not available if the counter Source is one of the internal timebases 30MHzTimebase 20MHzTimebase or 100kHzTimebase Synchronization Modes The 32 bit counter counts up or down synchronously with the Source signal The Gate signal and other counter inputs are asynchronous to the Source signal so the cDAQ chassis synchronizes these signals before presenting them to the internal counter Depending on how you configure your chassis the cDAQ chassis uses one of two synchronization methods 80 MHz Source Mode External or Internal Source Less than 20 MHz National Instruments 5 39 Chapter 5 Counters 80 MHz Source Mode In 80 MHz source mode the chassis synchronizes signals on the rising edge of the source and counts on the third rising edge of the source Edges are pipelined so no counts are lost as shown in Figure 5 38 Figure 5 38 80 MHz Source Mode 80 MHz Source A A Synchronize Count External or Internal Source Less than 20 MHz With an external or internal source less than 20 MHz the modu
79. er and saving the counter contents Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal Any of the following signals can be routed to the Counter n Gate input e Any PFI terminal e Al Reference Trigger AI Start Trigger e AO Sample Clock e DI Sample Clock e DI Reference Trigger e DO Sample Clock e Change Detection Event e Analog Comparison Event In addition a counter s Internal Output or Source can be routed to a different counter s gate 5 34 ni com NI cDAQ 9188XT User Manual Some of these options may not be available in some driver software Refer to the Device Routing in MAX topic in the NJ DAQmx Help or the LabVIEW Help for more information about available routing options Routing Counter n Gate to an Output Terminal You can route Counter n Gate out to any PFI terminal Counter n Aux Signal The Counter n Aux signal indicates the first edge in a two signal edge separation measurement Routing a Signal to Counter n Aux Each counter has independent input selectors for the Counter n Aux signal Any of the following signals can be routed to the Counter n Aux input e Any PFI terminal Al Reference Trigger e Al Start Trigger e Analog Comparison Event e Change Detection Event In addition a counter s Internal Output Gate or Source can be routed to a different counter s Aux A counter s own gate can also be routed to its Aux inp
80. eral components on the device A Caution Never touch the exposed pins of connectors To avoid ESD damage in handling the chassis take the following precautions e Ground yourself with a grounding strap or by touching a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the chassis from the package Remove the chassis from the package and inspect it for loose components or any other signs of damage Notify NI if the device appears damaged in any way Do not install a damaged chassis Store the chassis in the antistatic package when the chassis is not in use Installing the cDAQ Chassis The cDAQ chassis and C Series I O module s are packaged separately For an interactive demonstration of how to install the cDAQ chassis go to ni com info and enter cdaqinstall Refer to Figure 1 1 while completing the following assembly steps 1 Install the application software if applicable as described in the installation instructions that accompany your software 2 Install NI DAQmx 9 8 or later For more information download the Read Me First NI DAQmx and DAQ Device Installation Guide Note The NI DAQmx software is included on the disk shipped with your kit and is available for download at ni com support The documentation for NI DAQmx is available after installation from Start All Programs National Instruments NI DAQ Other NI documentation is available from ni com manuals
81. erminal screw to 0 2 to 0 25 N m 1 8 to 2 2 Ib in of torque 4 Connect the negative lead of the power source to the C terminal of the power screw terminal connector plug and tighten the terminal screw to 0 2 to 0 25 N m 1 8 to 2 2 lb in of torque 5 Install the power connector plug on the front panel of the cDAQ chassis and tighten the connector screws to 0 4 N m 3 5 1b in of torque 6 Turn on the external power source If the power source is connected to the power connector using long wiring with high DC resistance the voltage at the power connector may be significantly lower than the specified voltage of the power source The C terminal is not connected to chassis ground You can connect the C terminal to chassis ground externally Refer to the Power Requirements section of the NJ cDAQ 9188XT Specifications for information about the power supply input range Refer to the Safety Voltages section of the NJ cDAQ 9188XT Specifications for information about the maximum voltage from terminal to chassis ground 1 8 ni com NI cDAQ 9188XT User Manual Troubleshooting Chassis Connectivity If your cDAQ chassis becomes disconnected from the network try the following e After moving the chassis to a new network NI DAQmx may lose connection to the chassis In this case click Reconnect to provide NI DAQmx with the new hostname or IP address e The cDAQ chassis icon indicates whether it is recognized and present on th
82. falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO On the next active edge of the Gate signal the counter begins another measurement The STC3 transfers the sampled values to host memory using a high speed data stream Figure 5 24 shows an example of an implicit buffered two signal edge separation measurement Figure 5 24 Implicit Buffered Two Signal Edge Separation Measurement AUX GATE p a SOURCE Counter Value 1 2 3 i 1 2 3 1 2 3 3 3 3 3 3 Buffer 3 Sample Clocked Buffered Two Signal Separation Measurement A sample clocked buffered two signal separation measurement is similar to single two signal separation measurement but buffered two signal separation measurement takes measurements over multiple intervals correlated to a sample clock The counter counts the number of rising or 5 22 ni com NI cDAQ 9188XT User Manual falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO on a sample clock edge On the next active edge of the Gate signal the counter begins another measurement The STC3 transfers the
83. h a hardware timed generation a digital hardware signal controls the rate of the generation This signal can be generated internally on the chassis or provided externally Hardware timed generations have several advantages over software timed acquisitions e The time between samples can be much shorter e The timing between samples is deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed AO operations on the cDAQ chassis must be buffered Buffered Analog Output A buffer is a temporary storage in computer memory for generated samples In a buffered generation data is moved from a host buffer to the cDAQ chassis onboard FIFO before it is written to the C Series I O modules One property of buffered I O operations is sample mode The sample mode can be either finite or continuous Finite Finite sample mode generation refers to the generation of a specific predetermined number of data samples After the specified number of samples is written out the generation stops Continuous Continuous generation refers to the generation of an unspecified number of samples Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation There are three different continuous generation modes that control how the data is written These modes are regeneration onboard regeneration and non regeneration Inregeneration mode you define a buffe
84. he frequency generator when the divider is set to 5 Figure 5 35 Frequency Generator Output Waveform Frequency Output Timebase FREQ OUT Divisor 5 5 30 ni com NI cDAQ 9188XT User Manual Frequency Output can be routed out to any PFI terminal All PFI terminals are set to high impedance at startup The FREQ OUT signal also can be routed to many internal timing signals In software program the frequency generator as you would program one of the counters for pulse train generation For information about connecting counter signals refer to the Default Counter Timer Routing section Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal This function is equivalent to continuous pulse train generation Refer to the Continuous Pulse Train Generation section for detailed information For information about connecting counter signals refer to the Default Counter Timer Routing section Watchdog Timer The watchdog timer is a software configurable feature used to set critical outputs to expiration states in the event of a software failure a system crash or any other loss of communication between the application and the cDAQ chassis When the watchdog timer is enabled if the cDAQ chassis does not receive a watchdog reset software command within the time specified for the watchdog time
85. he task Sample Clock can be generated from external or internal sources as shown in Figure 2 1 Figure 2 1 Al Sample Clock Timing Options PFI Analog Comparison Event 4 Ctr n Internal Output PFI Al Sample Clock Analog Comparison Sigma Delta Module Internal Output Al Sample Clock Event Timebase Programmable 20 MHz Timebase Clock Divider 80 MHz Timebase 100 kHz Timebase Routing the Sample Clock to an Output Terminal You can route Sample Clock to any output PFI terminal Sample Clock is an active high pulse by default Al Sample Clock Timebase Signal The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock AI Sample Clock Timebase can be generated from external or internal sources AI Sample Clock Timebase is not available as an output from the chassis Al Convert Clock Signal Behavior For Analog Input Modules Refer to the Scanned Modules Simultaneous Sample and Hold Modules Sigma Delta Modules and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and C Series analog input modules Scanned Modules Scanned C Series analog input modules contain a single A D converter and a multiplexer to select between multiple input channels When the cDAQ Module Interface receives a Sample Clock pulse it begins generating a Convert Clock for each scanned module in the current task 2 2 ni com NI cDAQ 9188XT User
86. ignal to the Gate input of Counter 1 You can route a signal of known frequency fk to the Counter 1 Source input Configure Counter 1 to perform a single pulse width measurement Suppose the result is that the pulse width is J periods of the Jk clock From Counter 0 the length of the pulse is N fx From Counter 1 the length of the same pulse is J fk Therefore the frequency of fx is given by fx fk NIJ Sample Clocked Buffered Frequency Measurement Sample clocked buffered point frequency measurements can either be a single frequency measurement or an average between sample clocks Use CI Freq EnableAveraging to set the behavior For buffered frequency the default is True A sample clocked buffered frequency measurement with CI Freq EnableAveraging set to True uses the embedded counter and a sample clock to perform a frequency measurement For each sample clock period the embedded counter counts the signal to measure fx and the primary counter counts the internal time base of a known frequency fk Suppose T1 is the number of ticks of the unknown signal counted between sample clocks and T2 is the number of ticks counted of the known timebase as shown in Figure 5 15 The frequency measured is fe fk T1 T2 National Instruments 5 13 Chapter 5 Figure 5 15 Sample Clocked Buffered Frequency Measurement Averaging Counters Counter Armed Source fk Sample Clock i St e a TA 9 1 ULU
87. information about digital I O modules refer to Chapter 4 Digital Input Output and PFI cDAQ Module Interface The cDAQ module interface manages data transfers between the STC3 and the C Series T O modules The interface also handles autodetection signal routing and synchronization STC3 The STC3 features independent high speed data streams flexible AI AO and DIO sample timing triggering PFI signals for multi device synchronization flexible counter timers with hardware gating digital waveform acquisition and generation and static DIO AI AO and DIO Sample Timing The STC3 contains advanced AI AO and DIO timing engines A wide range of timing and synchronization signals are available through the PFI lines Refer to the following sections for more information about the configuration of these signals The Analog Input Timing Signals section of Chapter 2 Analog Input The Analog Output Timing Signals section of Chapter 3 Analog Output The Digital Input Timing Signals section of Chapter 4 Digital Input Output and PFI The Digital Output Timing Signals section of Chapter 4 Digital Input Output and PFI Triggering Modes The cDAQ chassis supports different trigger modes such as start trigger reference trigger and pause trigger with analog digital or software sources Refer to the following sections for more information The Analog Input Triggering Signals section of Chapter 2 Analog Input The
88. ital input applications e Single point acquisition e Finite acquisition e Continuous acquisition For more information about programming digital input applications and triggers in software refer to the NI DAQmx Help or the LabVIEW Help for more information Tp is a nominal value the accuracy of the chassis timebase and I O distortion will affect this value National Instruments 4 7 Chapter 4 Digital Input Output and PFI Change Detection Event The Change Detection Event is the signal generated when a change on the rising or falling edge lines is detected by the change detection task Routing Change Detection Event to an Output Terminal You can route ChangeDetectionEvent to any output PFI terminal Change Detection Acquisition You can configure lines on parallel digital modules to detect rising or falling edges When one or more of these lines sees the edge specified for that line the cDAQ chassis samples all the lines in the task The rising and falling edge lines do not necessarily have to be in the task Change detection acquisitions can be buffered or nonbuffered e Nonbuffered Change Detection Acquisition In a nonbuffered acquisition data is transferred from the cDAQ chassis directly to a PC buffer Buffered Change Detection Acquisition A buffer is a temporary storage in computer memory for acquired samples In a buffered acquisition data is stored in the cDAQ chassis onboard FIFO then transferred
89. l In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source for DI Start Trigger the acquisition begins on the first rising edge of the Analog Comparison Event signal A Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering 4 4 ni com NI cDAQ 9188XT User Manual Routing DI Start Trigger to an Output Terminal You can route DI Start Trigger to any output PFI terminal The output is an active high pulse DI Reference Trigger Signal Use a reference trigger di ReferenceTrigger signal to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples Once the acquisition begins the cDAQ chassis writes samples to the buffer After the cDAQ chassis captures the specified number of pretrigger samples the chassis begins to look for the reference trigger condition If the reference trigger condition occurs before the cDAQ chassis captures the specified number of pretrigger samples the chassis ignores the condition If the buffer becomes full the cDAQ chassis continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limita
90. l input of the counter 5 38 ni com NI cDAQ 9188XT User Manual Other Counter Features The following sections list the other counter features available on the cDAQ chassis Cascading Counters You can internally route the Counter n Internal Output and Counter n TC signals of each counter to the Gate inputs of the other counter By cascading two counters together you can effectively create a 64 bit counter By cascading counters you also can enable other applications For example to improve the accuracy of frequency measurements use reciprocal frequency measurement as described in the Large Range of Frequencies with Two Counters section Prescaling Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter The cDAQ chassis offers 8X and 2X prescaling on each counter prescaling can be disabled Each prescaler consists of a small simple counter that counts to eight or two and rolls over This counter can run faster than the larger counters which simply count the rollovers of this smaller counter Thus the prescaler acts as a frequency divider on the Source and puts out a frequency that is one eighth or one half of what it is accepting as shown in Figure 5 37 Figure 5 37 Prescaling External Signal JU LTLPLILI LILY LILY LPL LPL Prescaler Rollover Used as Source l by Counter Counter Value 0 X 1 Prescaling is intended to be used for frequency measurem
91. le generates a delayed Source signal by delaying the Source signal by several nanoseconds The chassis synchronizes signals on the rising edge of the delayed Source signal and counts on the following rising edge of the source as shown in Figure 5 39 Figure 5 39 External or Internal Source Less than 20 MHz Source fo E A Synchronize A Delayed Source Count 5 40 ni com Digital Routing and Clock Generation This chapter describes the digital routing and clock routing circuitry on the cDAQ chassis Refer to the Digital Routing and Clock Routing sections Digital Routing The digital routing circuitry has the following functions Manages the flow of data between the bus interface and the acquisition generation sub systems analog input analog output digital I O and the counters The digital routing circuitry uses FIFOs if present in each sub system to ensure efficient data movement Routes timing and control signals The acquisition generation sub systems use these signals to manage acquisitions and generations These signals can come from the following sources Your C Series I O modules User input through the PFI terminals using parallel digital C Series I O modules or the cDAQ chassis PFI terminals Routes and generates the main clock signals for the cDAQ chassis To determine the signal routing options for C Series I O module s installed in the cDAQ chassis refer to the Device Ro
92. ltipoint write On buffered sample clock pulse trains the pulse specifications in the DAQmx Create Counter Output Channel are generated after the counters starts and before the first sample clock so that you generate the number of updates defined in the multipoint write National Instruments 5 27 Chapter 5 Counters Finite Implicit Buffered Pulse Train Generation This function generates a predetermined number of pulses with variable idle and active times Each point you write generates a single pulse The number of pairs of idle and active times pulse specifications you write determines the number of pulses generated All points are generated back to back to create a user defined pulse train Table 5 6 and Figure 5 32 detail a finite implicit generation of three samples Table 5 6 Finite Implicit Buffered Pulse Train Generation Sample Idle Ticks Active Ticks 1 2 2 2 3 4 3 2 2 Figure 5 32 Finite Implicit Buffered Pulse Train Generation source UUUUUUUUUUUUUUUUUUUUL 1 2 2 3 4 2 2 Counter Armed OUT Continuous Buffered Implicit Pulse Train Generation This function generates a continuous train of pulses with variable idle and active times Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write generates a single pulse All points are generated back to back to creat
93. n To ensure the specified EMC performance do not connect the power input to a DC mains supply or to any supply requiring a connecting cable longer than 3 m 10 ft A DC mains supply is a local DC electricity supply network in the infrastructure of a site or building The cDAQ chassis requires an external power source as described in the Power Requirements section of the NJ cDAQ 9188XT Specifications Some suggested NI power supplies are listed in Table 1 4 The cDAQ chassis filters and regulates the supplied power and provides power to all of the I O modules The green POWER LED on the front panel identifies when the power input is in use National Instruments 1 7 Chapter 1 Getting Started with the cDAQ Chassis Complete the following steps to connect a power source to the cDAQ chassis 1 Make sure the power source is turned off 2 Ifconnected remove the power screw terminal connector plug from the cDAQ chassis Figure 1 4 shows the terminal screws which secure the wires in the screw terminals and the connector screws which secure the connector plug on the front panel Figure 1 4 Power Screw Terminal Connector Plug 1 V Positive Terminal Screw 3 Connector Screws 2 C Negative Terminal Screw Caution Do xof tighten or loosen the terminal screws on the power connector while the power is on 3 Connect the positive lead of the power source to the V terminal of the power connector plug and tighten the t
94. n a semi period measurement each high or low time is considered one point of data and returned in units of seconds or ticks In a pulse measurement each pair of high and low times is considered one point of data and returned as a paired sample in units of frequency and duty cycle high and low time or high and low ticks When reading data 10 points in a semi period measurement will get an array of five high times and five low times When you read 10 points in a pulse measurement you get an array of 10 pairs of high and low times Also pulse measurements support sample clock timing while semi period measurements do not Frequency Measurement You can use the counters to measure frequency in several different ways Refer to the following sections for information about cDAQ chassis frequency measurement options Low Frequency with One Counter e High Frequency with Two Counters e Large Range of Frequencies with Two Counters e Sample Clocked Buffered Frequency Measurement Low Frequency with One Counter For low frequency measurements with one counter you measure one period of your signal using a known timebase You can route the signal to measure fx to the Gate of a counter You can route a known timebase fk to the Source of the counter The known timebase can be an onboard timebase such as 80 MHz Timebase 20 MHz Timebase or 100 kHz Timebase or any other signal with a known rate 5 10 ni com NI cDAQ 9188XT User Manual Y
95. n about the differences between semi period measurement and pulse measurement Single Semi Period Measurement Single semi period measurement is equivalent to single pulse width measurement Implicit Buffered Semi Period Measurement In implicit buffered semi period measurements on each edge of the Gate signal the counter stores the count in the FIFO The STC3 transfers the sampled values to host memory using a high speed data stream The counter begins counting when it is armed The arm usually occurs between edges on the Gate input You can select whether to read the first active low or active high semi period using the CI SemiPeriod StartingEdge property in NI DAQmx Figure 5 11 shows an example of an implicit buffered semi period measurement Figure 5 11 Implicit Buffered Semi Period Measurement Counter Starting Armed Edge GATE source LF LALA LE LALF LE LALA Counter Value 0 i 1 2 3 144 2 1 38 iB 3B Buffer i 1 1 i 2 National Instruments 5 9 Chapter 5 Counters For information about connecting counter signals refer to the Default Counter Timer Routing section Pulse versus Semi Period Measurements In hardware pulse measurement and semi period are the same measurement Both measure the high and low times of a pulse The functional difference between the two measurements is how the data is returned I
96. nchronize data from all the modules that support an external oversample clock timebase when they all share the same task DSA modules are an example The cDAQ chassis supports a maximum of two synchronization pulse signals configured for your system This limits the system to two tasks with different oversample clock timebases The oversample clock is used as the AI Sample Clock Timebase While most modules supply a common oversample clock frequency 12 8 MHz some modules such as the NI 9234 supply a different frequency When sigma delta modules with different oversample clock frequencies are used in an analog input task the AI Sample Clock Timebase can use any of the available frequencies by default the fastest available is used The sampling rate of all modules in the system is an integer divisor of the frequency of the AI Sample Clock Timebase When one or more sigma delta modules are in an analog input task the sigma delta modules also provide the signal used as the AI Sample Clock This signal is used to cause A D conversion for other modules in the system just as the AI Sample Clock does when a sigma delta module is not being used When sigma delta modules are in an AI task the chassis automatically issues a synchronization pulse to each sigma delta modules that resets their ADCs at the same time Because of the filtering used in sigma delta A D converters these modules usually exhibit a fixed input delay relative to non sigma delta m
97. ncludes two metal feet you can install on the sides of the cDAQ chassis for desktop use With this kit you can tilt the cDAQ chassis for convenient access to the I O module connectors When you install the two metal feet the two existing screws on the back side and I O end of the chassis must be removed as shown in Figure 1 6 After removing the screws replace them with the screws included in the NI 9901 desktop mounting kit The cDAQ chassis uses two M3 x 14 screws 1 10 ni com NI cDAQ 9188XT User Manual Figure 1 6 NI 9901 Desktop Mounting Kit You must mount the chassis before installing the C Series I O modules Mounting the cDAQ Chassis on a Panel A Caution To maintain product performance and accuracy specifications when the ambient temperature is between 60 and 70 C you must mount the chassis horizontally to a metal panel or surface using the screw holes or the panel mount kit Measure the ambient temperature at each side of the CompactDAQ system 63 5 mm 2 5 in from the side and 25 4 mm 1 in from the rear cover of the system For further information about mounting configurations go to ni com info and enter the Info Code cdaqmounting You can use a panel mount kit to mount the cDAQ chassis on a panel or mount directly to the panel with your own screws For kit accessory ordering information refer to the pricing section of the NI cDAQ 9188XT product page at ni com Panel Mounting with a Panel Mount Kit Use th
98. ng chassis responses When pressed for less than five seconds the chassis reboots with the current configuration e When pressed for five seconds or longer the STATUS LED lights When released the chassis reboots into factory default mode which returns the chassis user configuration to the factory set defaults listed in Table 1 3 Table 1 3 NI cDAQ Chassis Default Settings Attribute Value Hostname cDAQ9188XT lt serial number gt IP DHCP or Link Local Comment Empty NI Auth User name admin Password no password required Power Connector The cDAQ chassis ships with a 2 position power screw terminal connector plug for use with an external power source Refer to the NJ cDAQ 9188XT Specifications for information about the power connector on the cDAQ chassis PFI BNC Connectors Refer to the PFI section of Chapter 4 Digital Input Output and PFI for information about the BNC connectors for PFI 0 and PFI 1 1 18 ni com Cables and Accessories NI cDAQ 9188XT User Manual Table 1 4 contains information about cables and accessories available for the cDAQ chassis For a complete list of cDAQ chassis accessories and ordering information refer to the pricing section of the NI cDAQ 9188XT product page at ni com Table 1 4 Cables and Accessories Accessory Part Number NI PS 15 power supply 24 VDC 5 A 781093 01 100 to 120 200 to 240 VAC input 25 to 70 C N
99. ng signals as the source e Any PFI terminal Counter n Internal Output The source also can be one of several other internal signals on your cDAQ chassis Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source for Start Trigger the acquisition begins on the first rising edge of the Analog Comparison Event signal Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Routing Al Start Trigger to an Output Terminal You can route the Start Trigger signal to any output PFI terminal The output is an active high pulse Al Reference Trigger Signal Use Reference Trigger to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples Once the acquisition begins the cDAQ chassis writes samples to the buffer After the cDAQ chassis captures the specified number of pretrigger samples the cDAQ chassis begins to look for the reference trigger condition If the reference trigger c
100. ns do not take clock stability into account Refer to the NJ cDAQ 9188XT Specifications for information about clock stability National Instruments 5 15 Chapter 5 Counters Which Method Is Best This depends on the frequency to be measured the rate at which you want to monitor the frequency and the accuracy you desire Take for example measuring a 50 kHz signal Assuming that the measurement times for the sample clocked with averaging and two counter frequency measurements are configured the same Table 5 3 summarizes the results Table 5 3 50 kHz Frequency Measurement Methods Two Counter Sample High Variable Clocked One Counter Frequency Large Range f 50 000 50 000 50 000 50 000 fk 80 M 80 M 1 000 80 M Measurement 1 02 1 1 time mS N 50 Max frequency 638 31 27 1 000 625 error Hz Max error 00128 0625 2 00125 From this you can see that while the measurement time for one counter is shorter the accuracy is best in the sample clocked and two counter large range measurements For another example Table 5 4 shows the results for 5 MHz Table 5 4 5 MHz Frequency Measurement Methods Two Counter High Variable Sample Clocked One Counter Frequency Large Range fx 5M 5M 5M 5M fk 80 M 80 M 1 000 80 M Measurement 1 0002 1 1 time mS N 5 000 Max 62 51 333 k 1 000 62 50 Frequency error Hz
101. ock When a sample clock occurs the current pulse finishes generation and the next pulse uses the next sample specifications Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit as described in the Using the Frequency Generator section Using the Frequency Generator The frequency generator can output a square wave at many different frequencies The frequency generator is independent of the four general purpose 32 bit counter timer modules on the cDAQ chassis Figure 5 34 shows a block diagram of the frequency generator Figure 5 34 Frequency Generator Block Diagram Frequency Output Timebase 20 MHz Timebase 2 100 kHz Timebase e _ Frequency Generator FREQ OUT Divisor 1 16 The frequency generator generates the Frequency Output signal The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16 The Frequency Output Timebase can be either the 20 MHz Timebase the 20 MHz Timebase divided by 2 or the 100 kHz Timebase The duty cycle of Frequency Output is 50 if the divider is either 1 or an even number For an odd divider suppose the divider is set to D In this case Frequency Output is low for D 1 2 cycles and high for D 1 2 cycles of the Frequency Output Timebase Figure 5 35 shows the output waveform of t
102. odules in the system This input delay is specified in the C Series T O module documentation National Instruments 2 3 Chapter 2 Analog Input Slow Sample Rate Modules Some C Series analog input modules are specifically designed for measuring signals that vary slowly such as temperature Because of their slow rate it is not appropriate for these modules to constrain the AI Sample Clock to operate at or slower than their maximum rate When using such a module in the cDAQ chassis the maximum Sample Clock rate can run faster than the maximum rate for the module When operating at a rate faster than these slow rate modules can support the slow rate module returns the same point repeatedly until a new conversion completes In a hardware timed task the first point is acquired when the task is committed The second point is acquired after the start trigger as shown in Figure 2 2 Figure 2 2 Sample Clock Timing Example StartTrigger j Jj 1st A D Conversion 2nd A D Conversion 8rd A D Conversion y gt i gt i Data fi ND Conversion nE A NWVVVVVVVVVVVVVVVV VV WAVVVVVVVVVVVVV AA Slow Module SampleClock i eee eee A A A A A A A Data Returned to Al Task A i A B B B G For example if running an AI task at 1 kHz using a module with a maximum rate of 10 Hz the slow module returns 100 samples of the first point followed by 100 samples of the second point etc O
103. of Pulse T gt Pulse _ Pulse Gate 1 2 ead N fx Source e PILILLA Pulse Width Width of T N Measurement Pulse fx N Frequency of fx TE Large Range of Frequencies with Two Counters By using two counters you can accurately measure a signal that might be high or low frequency This technique is called reciprocal frequency measurement When measuring a large range of frequencies with two counters you generate a long pulse using the signal to measure You then measure the long pulse with a known timebase The cDAQ chassis can measure this long pulse more accurately than the faster input signal Note Counter 0 is always paired with Counter 1 Counter 2 is always paired with Counter 3 5 12 ni com NI cDAQ 9188XT User Manual You can route the signal to measure to the Source input of Counter 0 as shown in Figure 5 14 Assume this signal to measure has frequency fx NI DAQmx automatically configures Counter 0 to generate a single pulse that is the width of N periods of the source input signal Figure 5 14 Large Range of Frequencies with Two Counters Signal to Measure fx gt Source Out Counter 0 Signal of Known Frequency fk Source Out Counter 1 Gate 0 s CTR_0_SOURCE pmnan aAnmnN Signal to Measure CTR_0_OUT CTR_1_GATE lt _ Interval p to Measure cTR_1_source JUUUUUUUUUUU UU Next route the Counter 0 Internal Output s
104. of lines logic levels update rate and line direction are determined by the type of C Series I O module used For more information refer to the documentation included with your C Series I O module s Serial DIO versus Parallel DIO Modules Serial digital I O modules have more than eight lines of digital input output They can be used in any chassis slot and can perform the following tasks e Software timed and hardware timed digital input output tasks Parallel digital I O modules can be used in any chassis slot and can perform the following tasks e Software timed and hardware timed digital input output tasks e Counter timer tasks can be used in up to two slots e Accessing PFI signal tasks can be used in up to two slots e Filter digital input signals Software timed and hardware timed digital input output tasks have the following restrictions e You cannot use parallel and serial modules together on the same hardware timed task e You cannot use serial modules for triggering e You cannot do both static and timed tasks at the same time on a single serial module e You can only do hardware timing in one direction at a time on a serial bidirectional module To determine the capability of digital I O modules supported by the cDAQ chassis refer to the Developer Zone document C Series Support in NI DAQmx To access this Developer Zone document go to ni com info and enter the Info Code rdcdaq National Instruments 4 1
105. of quadrature encoders that use X1 X2 or X4 encoding A quadrature encoder can have up to three channels channels A B and Z X1 Encoding When channel A leads channel B in a quadrature cycle the counter increments When channel B leads channel A in a quadrature cycle the counter decrements The amount of increments and decrements per cycle depends on the type of encoding X1 X2 or X4 Figure 5 17 shows a quadrature cycle and the resulting increments and decrements for X1 encoding When channel A leads channel B the increment occurs on the rising edge of channel A When channel B leads channel A the decrement occurs on the falling edge of channel A Figure 5 17 X1 Encoding Ch A l eee ChB Leeel h h Counter Vae 5X 6 X 7 7 X6 X5 X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A depending on which channel leads the other Each cycle results in two increments or decrements as shown in Figure 5 18 Figure 5 18 X2 Encoding cha l LT Counter Value 5X 6 X 7 X8X9 9X 8X7 X 6X5 X4 Encoding Similarly the counter increments or decrements on each edge of channels A and B for X4 encoding Whether the counter increments or decrements depends on which channel leads the other Each cycle results in four increments or decrements as shown in Figure 5 19
106. og triggering Note Pause triggers are only sensitive to the level of the source not the edge Getting Started with Al Applications in Software You can use the cDAQ chassis in the following analog input applications e Single point acquisition e Finite acquisition e Continuous acquisition For more information about programming analog input applications and triggers in software refer to the NI DAQmx Help or the LabVIEW Help for more information National Instruments 2 7 Analog Output To generate analog output insert an analog output C Series I O module in any slot on the cDAQ chassis The generation specifications such as the number of channels channel configuration update rate and output range are determined by the type of C Series I O module used For more information refer to the documentation included with your C Series I O module s On a single analog output C Series module you can assign any number of channels to either a hardware timed task or a software timed single point task However you cannot assign some channels to a hardware timed task and other channels on the same module to a software timed task Furthermore you cannot run multiple tasks of any type on a single analog output module With multiple analog output modules you can have as many software timed tasks as there are modules in the chassis but you can still have only one hardware timed task Any hardware timed task or software time
107. on applications Figure 5 1 shows the cDAQ chassis Counter 0 and the frequency generator All four counters on the cDAQ chassis are identical Figure 5 1 Chassis Counter 0 and Frequency Generator Input Selection Muxes Counter 0 Counter 0 Source Counter 0 Timebase Counter 0 Gate Counter 0 Internal Output Counter 0 Aux Embedded Ctro SF SF ST OS Counter 0 HW Arm Counter 0 A FIFO Counter 0 TC a y Counter 0 B Counter 0 Up_Down N y Counter 0 Z Counter 0 Sample Clock Input Selection Muxes Frequency Generator Frequency Output Timebase Freq Out Counters have eight input signals although in most applications only a few inputs are used For information about connecting counter signals refer to the Default Counter Timer Routing section Each counter has a FIFO that can be used for buffered acquisition and generation Each counter also contains an embedded counter Embedded Ctrn for use in what are traditionally two counter measurements and generations The embedded counters cannot be programmed independent of the main counter signals from the embedded counters are not routable National Instruments 5 1 Chapter 5 Counters Counter Timing Engine Unlike analog input analog output digital input and digital output the cDAQ chassis counters do not have the ability to divide down a timebase to produce an internal counter sample clock
108. ondition occurs before the cDAQ chassis captures the specified number of pretrigger samples the chassis ignores the condition If the buffer becomes full the cDAQ chassis continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limitations before the cDAQ chassis discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the Info Code rdcanq National Instruments 2 5 Chapter 2 Analog Input When the reference trigger occurs the cDAQ chassis continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 2 3 shows the final buffer Figure 2 3 Reference Trigger Final Buffer Reference Trigger Pretrigger Samples Posttrigger Samples ji ji T Complete Buffer Using a Digital Source To use Reference Trigger with a digital source specify a source and a rising or falling edge Either PFI or one of several internal signals on the cDAQ chassis can provide the source Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source the
109. ou can configure the counter to measure one period of the gate signal The frequency of fx is the inverse of the period Figure 5 12 illustrates this method Figure 5 12 Low Frequency with One Counter Interval Measured fx fx Gate 1 2 3 ee i N fk Source fk A A N Single Period Period of fx Measurement fk fk Frequency of fx Il High Frequency with Two Counters For high frequency measurements with two counters you measure one pulse of a known width using your signal and derive the frequency of your signal from the result Note Counter 0 is always paired with Counter 1 Counter 2 is always paired with Counter 3 In this method you route a pulse of known duration T to the Gate of a counter You can generate the pulse using a second counter You also can generate the pulse externally and connect it to a PFI terminal You only need to use one counter if you generate the pulse externally Route the signal to measure fx to the Source of the counter Configure the counter for a single pulse width measurement If you measure the width of pulse T to be N periods of fx the frequency of fx is N T National Instruments 5 11 Chapter 5 Counters Figure 5 13 illustrates this method Another option is to measure the width of a known period instead of a known pulse Figure 5 13 High Frequency with Two Counters ie Width
110. oute the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the beginning of each pulse You also can specify the pulse width The delay and pulse width are measured in terms of a number of active edges of the Source input The initial delay can be applied to only the first trigger or to all triggers using the CO EnableInitalDelayOnRetrigger property The default for a single pulse is True while the default for finite pulse trains is False National Instruments 5 25 Chapter 5 Counters The counter ignores the Gate input while a pulse generation is in progress After the pulse generation is finished the counter waits for another Start Trigger signal to begin another pulse generation For retriggered pulse generation pause triggers are not allowed since the pause trigger also uses the gate input Figure 5 29 shows a generation of two pulses with a pulse delay of five and a pulse width of three using the rising edge of Source with CO EnableInitalDelayOnRetrigger set to the default True Figure 5 29 Retriggerable Single Pulse Generation with Initial Delay on Retrigger Counter Load Values 43210210 43210210 GATE Start Trigger OUT SOURCE _ UU 5 3 5 3 Figure 5 30 shows the same pulse train with CO EnableInitalDelayOnRetrigger set
111. put Terminal You can route DI Sample Clock to any output PFI terminal The PFI circuitry inverts the polarity of DI Sample Clock before driving the PFI terminal DI Start Trigger Signal Use the DI Start Trigger di StartTrigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the acquisition to stop in one of the following ways e When a certain number of points has been sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition That is samples are measured only after the trigger When you are using an internal sample clock you can specify a delay from the start trigger to the first sample Using a Digital Source To use DI Start Trigger with a digital source specify a source and a rising or falling edge Use the following signals as the source e Any PFI terminal Counter n Internal Output The source also can be one of several other internal signals on the cDAQ chassis Refer to the Device Routing in MAX topic in the N DAQmx Help or the LabVIEW Help for more information Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signa
112. r the outputs go to a user defined expiration state and remain in that state until the watchdog timer is disarmed by a device reset After the watchdog timer expires the cDAQ chassis cannot perform any operation until the cDAQ chassis is reset You can set the watchdog timer timeout period to specify the amount of time that must elapse before the watchdog timer expires The counter on the watchdog timer is configurable up to 232 1 x 25 ns approximately 107 seconds before it expires When a watchdog timer expires analog output digital output and counter output changes may be configured to transition to an expiration state Resetting the chassis after a watchdog expiration event results in all module outputs defaulting to power up or startup states as defined in the module specifications A Note Resetting the chassis after a watchdog expiration event may result in undefined transient behavior on the outputs of the NI 9269 NI 9401 and NI 9474 modules Consult the module specifications for the expected I O behavior Note Restarting or re reserving the chassis may lead to undefined transient behavior on the outputs of any modules so these operations are not recommended as means of a watchdog expiration event recovery National Instruments 5 31 Chapter 5 Counters Note No other operations may be running on the cDAQ chassis while the watchdog a timer task is being started this includes all DAQmx tasks calibration of module
113. r in host memory The data from the buffer is continually downloaded to the FIFO to be written out New data can be written to the host buffer at any time without disrupting the output There is no limitation on the number of waveform channels supported by regeneration mode With onboard regeneration the entire buffer is downloaded to the FIFO and regenerated from there After the data is downloaded new data cannot be written to the FIFO To use onboard regeneration the entire buffer must fit within the FIFO size The advantage of using onboard regeneration is that it does not require communication with the main host memory once the operation is started which prevents problems that may occur due to excessive bus traffic or operating system latency There is a limit of 16 waveform channels for onboard regeneration With non regeneration old data is not repeated New data must continually be written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error There is no limitation on the number of waveform channels supported by non regeneration 3 2 ni com NI cDAQ 9188XT User Manual Analog Output Triggering Signals Analog output supports two different triggering actions AO Start Trigger and AO Pause Trigger An analog or digital trigger can initiate these actions Up to two C Series parallel digital input modules can be us
114. r properties The analog trigger circuit must be configured by a simultaneously running analog input task Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Watchdog Timer The watchdog timer is a software configurable feature used to set critical outputs to expiration states in the event of a software failure a system crash or any other loss of communication between the application and the cDAQ chassis When the watchdog timer is enabled if the cDAQ chassis does not receive a watchdog reset software command within the time specified for the watchdog timer the outputs go to a user defined expiration state and remain in that state until the watchdog timer is disarmed by a device reset After the watchdog timer expires the cDAQ chassis cannot perform any operation until the cDAQ chassis is reset National Instruments 4 13 Chapter 4 Digital Input Output and PFI You can set the watchdog timer timeout period to specify the amount of time that must elapse before the watchdog timer expires The counter on the watchdog timer is configurable up to 232 1 x 25 ns approximately 107 seconds before it expires When a watchdog timer expires analog output digital output and counter output changes may be configured to transition to an expiration state Resetting the chassis after a watchdog expiration event results in all module outputs defaulting to power up or startup states a
115. requency Output Signal The Frequency Output FREQ OUT signal is the output of the frequency output generator National Instruments 5 37 Chapter 5 Counters Routing Frequency Output to a Terminal You can route Frequency Output to any PFI terminal Default Counter Timer Routing Counter timer signals are available to correlated digital I O C Series modules To determine the signal routing options for modules installed in your system refer to the Device Routes tab in MAX You can use these defaults or select other sources and destinations for the counter timer signals in NI DAQmx Refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help for more information about how to connect your signals for common counter measurements and generations the cDAQ chassis default PFI lines for counter functions are listed in Physical Channels in the NI DAQmx Help or the LabVIEW Help Counter Triggering Counters support three different triggering actions Arm Start Trigger To begin any counter input or output function you must first enable or arm the counter Software can arm a counter or configure counters to be armed on a hardware signal Software calls this hardware signal the Arm Start Trigger Internally software routes the Arm Start Trigger to the Counter n HW Arm input of the counter For counter output operations you can use it in addition to the start and pause triggers For counter input operations
116. res 1 15 installation and configuration 1 4 mounting 1 10 NI cDAQ 9188XT 1 1 reserving in MAX 1 9 troubleshooting device connectivity 1 15 unpacking 1 4 using 1 20 cDAQ module interface 1 21 channel Z behavior 5 19 chassis grounding screw 1 15 choosing frequency measurement 5 14 configuration 1 4 connecting to wireless networks 1 15 connector PFI BNC 1 18 power 1 18 continuous pulse train generation 5 26 controlling counting direction 5 3 counter signals Counter n A 5 35 Counter n Aux 5 35 Counter n B 5 35 Counter n Gate 5 34 Counter n HW Arm 5 36 National Instruments l 1 Index Counter n Internal Output 5 37 Counter n Source 5 33 Counter n TC 5 37 Counter n Up_Down 5 36 FREQ OUT 5 37 Frequency Output 5 37 counters 5 1 cascading 5 39 edge counting 5 3 generation 5 23 input applications 5 3 other features 5 39 output applications 5 23 prescaling 5 39 pulse train generation 5 25 retriggerable single pulse generation 5 25 simple pulse generation 5 23 single pulse generation 5 24 with start trigger 5 24 synchronization modes 5 39 timing signals 5 32 triggering 5 38 watchdog timer 5 31 counting edges 5 3 D data AO generation methods 3 1 DO generation methods 4 9 Declaration of Conformity NI resources B 1 DI Sample Clock signal 4 3 diagnostic tools NI resources B 1 digital I O change detection event 4 8 configuration for NI 9401 4 14 digital input
117. rge range of frequencies using two counters 5 12 low frequency 5 10 minimizing glitches on the output signal 3 6 mounting 1 10 desktop use 1 10 DIN rail 1 13 panel wall 1 11 N National Instruments support and services B 1 O on demand edge counting 5 3 output signals minimizing glitches 3 6 P pause trigger 5 38 period measurement 5 18 PFI BNC connectors 1 18 PFI filters 4 15 position measurement 5 18 buffered 5 20 power connector 1 18 POWER LED 1 16 prescaling 5 39 programming examples NI resources B 1 pulse encoders 5 20 generation for ETS 5 32 train generation 5 25 continuous 5 26 pulse width measurement 5 5 implicit buffered 5 6 single 5 5 Q quadrature encoders 5 19 l 4 ni com R reciprocal frequency measurement 5 12 reserving the chassis in MAX 1 9 reset button 1 18 retriggerable single pulse generation 5 25 S safety guidelines hazardous locations use in Europe 1 2 sample clock edge counting 5 4 measurement 5 20 semi period measurement 5 9 implicit buffered 5 9 single 5 9 simple pulse generation 5 23 single point edge counting 5 3 pulse generation 5 24 retriggerable 5 25 with start trigger 5 24 pulse width measurement 5 5 semi period measurement 5 9 two signal edge separation measurement 5 22 software NI resources B 1 software timed generations analog output 3 1 digital output 4 9 start trigger 5 38 STATUS LED 1 1
118. ries I O modules For more information about using analog modules for triggering refer to the Analog Input Triggering Signals section of Chapter 2 Analog Input and the Analog Output Triggering Signals section of Chapter 3 Analog Output Refer to the DI Start Trigger Signal DI Reference Trigger Signal and DI Pause Trigger Signal sections for more information about the digital input trigger signals Digital Input Timing Signals The cDAQ chassis features the following digital input timing signals DI Sample Clock Signal e DI Sample Clock Timebase Signal DI Start Trigger Signal DI Reference Trigger Signal e DI Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section for more information 4 2 ni com NI cDAQ 9188XT User Manual DI Sample Clock Signal Use the DI Sample Clock di SampleClock signal to sample digital I O on any slot using parallel digital modules and store the result in the DI waveform acquisition FIFO If the cDAQ chassis receives a DI Sample Clock signal when the FIFO is full it reports an overflow error to the host software A sample consists of one reading from each channel in the DI task DI Sample Clock signals the start of a sample of all digital input channels in the task DI Sample Clock can be generated from external or internal sources as shown in Figure 4 1 Figure 4 1 DI Sample Clock Timing Options PFI Analog Comparison Event
119. ring information refer to the pricing section of the NI cDAQ 9188XT product page at ni com A Caution Your installation must meet the following requirements Allows 25 4 mm 1 in of clearance above and below the cDAQ chassis for air circulation e Allows at least 50 8 mm 2 in of clearance in front of the modules for common connector cabling such as the 10 terminal detachable screw terminal connector and as needed up to 88 9 mm 3 5 in of clearance in front of the modules for other types of cabling For more information about cabling clearances for C Series I O modules refer to ni com info and enter the Info Code cseriesconn A Caution To maintain product performance and accuracy specifications when the ambient temperature is between 60 and 70 C you must mount the chassis horizontally to a metal panel or surface using the screw holes or the panel mount kit DIN mounting limits the device to 60 C maximum ambient operating temperature Measure the ambient temperature at each side of the CompactDAQ system 63 5 mm 2 5 in from the side and 25 4 mm 1 in from the rear cover of the system For further information about mounting configurations go to ni com info and enter the Info Code cdaqmounting Using the cDAQ Chassis on a Desktop You can use the cDAQ chassis on a desktop with or without the optional desktop mounting kit A Caution Do not stack cDAQ chassis NI 9901 Desktop Kit The NI 9901 desktop mounting kit i
120. rk Devices and select Find Network NI DAQm x Devices If you know the chassis IP address such as 192 168 0 2 enter it into the Add Device Manually field and click the button QE Find Network NI DAQmx Devices ess Available Devices Hostname Wired IP Address Wireless IP Address Type a XT 16548C1 10 0 54 180 NI cDAQ 9188XT Select All Deselect All Refresh List Add Device Manually lt Aostname or IP Address gt Enter the hostname or IP address of a device on a different subnet gt Click here For troubleshooting tips if your device does not appear l Add Selected Devices l Cancel Otherwise enter the hostname of the chassis The default hostname is cDAQ9188XT lt serial number gt The cDAQ chassis icon changes from white to blue indicating that it is recognized and present on the network Figure 1 3 MAX Icons and States iDo m 1 Discovered But Not Added to the Network 2 Recognized Present and Reserved on the Network 1 6 ni com NI cDAQ 9188XT User Manual If your chassis does not appear in Available Devices click Refresh List If the chassis does not appear try the following e If you connected the cDAQ chassis directly to your computer ensure your network card is configured to obtain an IP address automatically then click Refresh List Note Ifyou connected the cDAQ chassis directly to your
121. rs and we ask our users to do the same NI software is protected by copyright and other intellectual property laws Where NI software may be used to reproduce software or other materials belonging to others you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction End User License Agreements and Third Party Legal Notices You can find end user license agreements EULAs and third party legal notices in the following locations e Notices are located in the lt National Instruments gt _Legal Information and lt National Instruments gt directories e EULAs are located in the lt National Instruments gt Shared MDF Legal license directory e Review lt National Instruments gt _Legal Information txt for more information on including legal information in installers built with NI products Trademarks Refer to the NMI Trademarks and Logo Guidelines at ni com trademarks for more information on National Instruments trademarks ARM Keil and Vision are trademarks or registered of ARM Ltd or its subsidiaries LEGO the LEGO logo WEDO and MINDSTORMS are trademarks of the LEGO Group 2013 The LEGO Group TETRIX by Pitsco is a trademark of Pitsco Inc 2013 FIELDBUS FOUNDATION and FOUNDATION are trademarks of the Fieldbus Foundation EtherCAT is a registered trademark of and licensed by Beckhoff Automation GmbH CANopen is a registered
122. s and routing and configuration of signals on the chassis After the watchdog timer task starts DAQmx tasks can be started and stopped and other operations can be performed Pulse Generation for ETS In the equivalent time sampling ETS application the counter produces a pulse on the output a specified delay after an active edge on Gate After each active edge on Gate the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount Thus the delay between the Gate and the pulse produced successively increases The increase in the delay value can be between 0 and 255 For instance if you specify the increment to be 10 the delay between the active Gate edge and the pulse on the output increases by 10 every time a new pulse is generated Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger Furthermore suppose you specify the delay increment to be 10 On the first trigger your pulse delay will be 100 on the second it will be 110 on the third it will be 120 the process will repeat in this manner until the counter is disarmed The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress The waveform thus produced at the counter s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are
123. s and decrements the counter value depending on the application the counter is performing Table 5 8 lists how this terminal is used in various applications Table 5 8 Counter Applications and Counter n Source Application Purpose of Source Terminal Pulse Generation Counter Timebase One Counter Time Measurements Counter Timebase Two Counter Time Measurements Input Terminal Non Buffered Edge Counting Input Terminal Buffered Edge Counting Input Terminal Two Edge Separation Counter Timebase National Instruments 5 33 Chapter 5 Counters Routing a Signal to Counter n Source Each counter has independent input selectors for the Counter n Source signal Any of the following signals can be routed to the Counter n Source input e 80 MHz Timebase e 20 MHz Timebase e 100 kHz Timebase e Any PFI terminal e Analog Comparison Event e Change Detection Event In addition TC or Gate from a counter can be routed to a different counter source Some of these options may not be available in some driver software Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information about available routing options Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI terminal Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the count
124. s defined in the module specifications A Note Resetting the chassis after a watchdog expiration event may result in undefined transient behavior on the outputs of the NI 9269 NI 9401 and NI 9474 modules Consult the module specifications for the expected I O behavior m Note Restarting or re reserving the chassis may lead to undefined transient behavior on the outputs of any modules so these operations are not recommended as means of a watchdog expiration event recovery Note No other operations may be running on the cDAQ chassis while the watchdog timer task is being started this includes all DAQmx tasks calibration of modules and routing and configuration of signals on the chassis After the watchdog timer task starts DAQmx tasks can be started and stopped and other operations can be performed Getting Started with DO Applications in Software You can use the cDAQ chassis in the following digital output applications e Single point on demand generation e Finite generation e Continuous generation For more information about programming digital output applications and triggers in software refer the LabVIEW Help or to the NI DAQmx Help Digital Input Output Configuration for NI 9401 When you change the configuration of lines on a NI 9401 digital I O module between input and output NI DAQmx temporarily reserves all of the lines on the module for communication to send the module a line configuration command For this reason
125. s referred to as start stop trigger measurement second gate measurement or A to B measurement Refer to the following sections for more information about the cDAQ chassis edge separation measurement options Single Two Signal Edge Separation Measurement Implicit Buffered Two Signal Edge Separation Measurement e Sample Clocked Buffered Two Signal Separation Measurement National Instruments 5 21 Chapter 5 Counters Single Two Signal Edge Separation Measurement With single two signal edge separation measurement the counter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO and ignores other edges on its inputs Software then reads the stored count Figure 5 23 shows an example of a single two signal edge separation measurement Figure 5 23 Single Two Signal Edge Separation Measurement Counter Armed Measured Interval 1 AUX J 4 GATE i f SOURCE Counter Value o0 001i 2 3 45 67 8 8 8 Latched Value 8 Implicit Buffered Two Signal Edge Separation Measurement Implicit buffered and single two signal edge separation measurements are similar but implicit buffered measurement measures multiple intervals The counter counts the number of rising or
126. sceeceecesceeceseeseeseeseceeceeceeceaesaesaeaaecaecneeaeeneeas 3 4 Using a Digital SOUrCE oe ceceeecessessessessesseeseeecescesceseeseeseeseceeceeceacaceaecneeneeneease 3 4 Using an Analog Source ccceccessessessessesscescesceseeceseescceeceeceeceaceaceaeeaecaeeneenseate 3 4 Routing AO Start Trigger Signal to an Output Terminal 0 0 eects 3 4 AQ Pause Irig ger Signal neiii sig hates ces E A tan a a Ena 3 4 Using a Digital SOUrCE iransi inah a E E A AEs 3 5 Using ati Analog Source nsession i re E EEE 3 5 Minimizing Glitches on the Output Signal eseeseseesseseseeeeeseseeeeeressrsrsreestsrersrsererresseserees 3 6 Watchdog Timers sokeena a EEE E Ar dele binslernanitieanana 3 6 Getting Started with AO Applications in Software ssssssesseessesesseseessesesersestsesesesseseses 3 7 vi ni com NI cDAQ 9188XT User Manual Chapter 4 Digital Input Output and PFI Digital Input Outpt esinen ho wad ales Sas ets ot bes died denies 4 1 Serial DIO versus Parallel DIO Modules 0 cececcesseeseeeceeceeceeceeceeceseeeeaeeneeneeneente 4 1 Statie DIO pacsecg ceeweseavea state ovate ae aE LEATA E NEEE Ea IERES AEAEE eae ovetpnia stv genatynacesiaseieek ate 4 2 Digital Input ericcson i ii i s 4 2 Digital Input Triggering Signals Digital Input Timing Signals Digital Input Filters oo eee cseeeceeeeeeeceeeeeeeeee 47 Getting Started with DI Applications in Software cece seeeesereeeeeeeeeeee 4 7 Change Detection Ev
127. se methods are regeneration FIFO regeneration and non regeneration modes Regeneration is the repetition of the data that is already in the buffer Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out New data can be written to the PC buffer at any time without disrupting the output With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started thereby preventing any problems that may occur due to excessive bus traffic With non regeneration old data is not repeated New data must be continually written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error National Instruments 5 29 Chapter 5 Counters Continuous Buffered Sample Clocked Pulse Train Generation This function generates a continuous train of pulses with variable idle and active times Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write specifies pulse specifications that are updated with each sample cl
128. signal is divided down to provide a source for AO Sample Clock AO Sample Clock Timebase can be generated from external or internal sources and is not available as an output from the chassis AO Start Trigger Signal Use the AO Start Trigger ao StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command If you are using an internal sample clock you can specify a delay from the start trigger to the first sample For more information refer to the NJ DAQmx Help Using a Digital Source To use AO Start Trigger specify a source and a rising or falling edge The source can be one of the following signals A pulse initiated by host software e Any PFI terminal Al Reference Trigger AI Start Trigger The source also can be one of several internal signals on the cDAQ chassis Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information You also can specify whether the waveform generation begins on the rising edge or falling edge of AO Start Trigger Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event depending on the trigger properties When you use an analog trigger source the waveform generation begins on the first rising or falling edge of the Analog Comparison Event signal depending on the trigger proper
129. so can be one of several internal signals on the cDAQ chassis Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information National Instruments 4 11 Chapter 4 Digital Input Output and PFI You also can specify whether the waveform generation begins on the rising edge or falling edge of DO Start Trigger Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event depending on the trigger properties When you use an analog trigger source the waveform generation begins on the first rising or falling edge of the Analog Comparison Event signal depending on the trigger properties The analog trigger circuit must be configured by a simultaneously running analog input task Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Routing DO Start Trigger Signal to an Output Terminal You can route DO Start Trigger to any output PFI terminal The output is an active high pulse DO Pause Trigger Signal Use the DO Pause Trigger signal do PauseTrigger to mask off samples in a DAQ sequence When DO Pause Trigger is active no samples occur but DO Pause Trigger does not stop a sample that is in progress The pause does not take effect until the beginning of the next sample When you generate digital output signals the generation pauses as soon as the
130. sosninsdien itira ia i iE PEU BNC Connectors a a a ae e aa aneen EA Cables and Accessories cccccscescessecsecesseeseeesees Removing I O Modules from the cDAQ Chassis Using the CDAQ Chassis ranan C Senes VO Module nonea te a KOE ENO ea LF Chapter 2 Analog Input Analog Input Triggering Signals sessesesssesssessesesesttseststsstsesseteststessseststesestsessesesseeest 2 1 Analog Input Timing Signals AI Sample Clock Signal Routing the Sample Clock to an Output Terminal 0 0 cee cceeseeseeeeeeeeeeeees 2 2 AI Sample Clock Timebase Signal cccccececsesceesceeceeceeceseeseaeaeeaecaecsecaecaeeaeeneens 2 2 National Instruments v Contents AI Convert Clock Signal Behavior For Analog Input Modules ccceseseeeees 2 2 Scanned Modulesjisissccsizets a decchvsesdhccseckeeavetbasnecSlboes ietdse deh snaneaeQecaurdecubeebeltvebstes 2 2 Simultaneous Sample and Hold Modules ccccccesscescesceseeseeeceeceeceensenaenee 2 3 Sigma Delta Modules ceeceeeceeereeeeeee Slow Sample Rate Modules AI Start Trigger Signal Using a Digital Source cronni aE E N R A Using ai Analog So rCE sinensis reerde EEEE en AE SEENE E Routing AI Start Trigger to an Output Terminal sesssssesesseseseseesesesesseseeseses 2 5 AI Reference Trigger Signal cccccsssesseescescesceseeseeeseseeeeceeceseeseeseeaecaecaecaeenseneeess 2 5 Using a Digital Source 0 ce cececesceseeseesecs
131. t Connect the ring lug to the chassis ground terminal on the side of the cDAQ chassis using the chassis grounding screw as shown in Figure 1 2 Attach the other end of the wire to the grounding electrode system of your facility For more information about earth ground connections refer to the KnowledgeBase document Grounding for Test and Measurement Devices by going to ni com info and entering the Info Code emcground A Caution To ensure the specified EMC performance the shield of any cable connected to a C Series I O module with a plastic connector must be connected to the chassis ground terminal using the chassis grounding screw To connect the cable shield of a C Series module I O cable to the chassis ground terminal of the cDAQ chassis attach a ring lug to a 1 31 mm 16 AWG or larger stranded copper wire of the minimum length needed to connect the shield to the chassis ground terminal Connect the ring lug to the chassis ground terminal using the chassis grounding screw Solder the other end of the wire to the cable shield Use shorter wires for better shield performance National Instruments 1 15 Chapter 1 Getting Started with the cDAQ Chassis LEDs The statuses for the 10 100 1000 LINK ACT POWER STATUS and ACTIVE LED indicators on the cDAQ chassis are listed in Table 1 1 Table 1 1 LED State Chassis Status LED Color LED State Chassis Status 10 100 1000 Yellow On Connect
132. the invoice date as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FA
133. ther modules in the task will return 1 000 new data points per second which is normal When performing a single point acquisition no points are repeated To avoid this behavior use multiple AI timing engines and assign slow sample rate modules to a task with a rate at or slower than their maximum rate Refer to the Developer Zone document C Series Support in NI DAQmx for more information To access this Developer Zone document go to ni com info and enter the Info Code rdcdaq Al Start Trigger Signal Use the Start Trigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the acquisition to stop in one of the following ways e When a certain number of points has been sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode 2 4 ni com NI cDAQ 9188XT User Manual An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition That is samples are measured only after the trigger When you are using an internal sample clock you can specify a default delay from the start trigger to the first sample Using a Digital Source To use the Start Trigger signal with a digital source specify a source and a rising or falling edge Use the followi
134. ties The analog trigger circuit must be configured by a simultaneously running analog input task Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Routing AO Start Trigger Signal to an Output Terminal You can route AO Start Trigger to any output PFI terminal The output is an active high pulse AO Pause Trigger Signal Use the AO Pause Trigger signal ao PauseTrigger to mask off samples in a DAQ sequence When AO Pause Trigger is active no samples occur but AO Pause Trigger does not stop a sample that is in progress The pause does not take effect until the beginning of the next sample 3 4 ni com NI cDAQ 9188XT User Manual When you generate analog output signals the generation pauses as soon as the pause trigger is asserted If the source of the sample clock is the onboard clock the generation resumes as soon as the pause trigger is deasserted as shown in Figure 3 2 Figure 3 2 AO Pause Trigger with the Onboard Clock Source Pause Trigger Sample Clock If you are using any signal other than the onboard clock as the source of the sample clock the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received as shown in Figure 3 3 Figure 3 3 AO Pause Trigger with Other Signal Source Pause Trigger J L Sample Clock i i
135. tions before the cDAQ chassis discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the Info Code rdcanq When the reference trigger occurs the cDAQ chassis continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 4 2 shows the final buffer Figure 4 2 Reference Trigger Final Buffer Reference Trigger Pretrigger Samples Posttrigger Samples j T Complete Buffer Using a Digital Source To use DI Reference Trigger with a digital source specify a source and a rising or falling edge Either PFI or one of several internal signals on the cDAQ chassis can provide the source Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information National Instruments 4 5 Chapter 4 Digital Input Output and PFI Using an Analog Source Some C Series I O modules can generate a trigger based on an analog signal In NI DAQm x this is called the Analog Comparison Event When you use an analog trigger source the acquisition stops on the first rising or falling edge of the Analog Comparison Event signal depending on the trigger properties Note Depending on the C Series I O module capabilities you may need two modules to utilize analog triggering Routing DI Reference Trigger Signal to an Output
136. to a PC buffer Buffered acquisitions typically allow for much faster transfer rates than nonbuffered acquisitions because data accumulates and is transferred in blocks rather than one sample at a time Digital Output To generate digital output insert a digital output C Series I O module in any slot on the cDAQ chassis The generation specifications such as the number of channels channel configuration update rate and output range are determined by the type of C Series I O module used For more information refer to the documentation included with your C Series I O module s On a single digital output C Series module you can assign any number of channels to either a hardware timed task or a software timed single point task However you cannot assign some channels to a hardware timed task and other channels on the same module to a software timed task Furthermore you cannot run multiple tasks of any type on a single digital output module With parallel digital output modules formerly known as hardware timed modules you can do multiple software timed tasks on a single module as well as mix hardware timed and software timed digital output tasks on a single module On serial digital output modules formerly known as static digital output modules you cannot mix hardware timed and software timed tasks but you can run multiple software timed tasks 4 8 ni com NI cDAQ 9188XT User Manual Digital Output Data Generation Methods
137. to at least IP 54 as defined by IEC EN 60529 Special Conditions for Hazardous Locations Use in Europe This equipment has been evaluated as Ex nA IIC T4 Ge equipment under DEMKO 12 ATEX 1202658X Each such chassis is marked II 3G and is suitable for use in Zone 2 hazardous locations in ambient temperatures of 40 C lt Ta lt 70 C A Caution You must make sure that transient disturbances do not exceed 140 of the rated voltage 1 2 ni com NI cDAQ 9188XT User Manual A Caution The chassis shall be mounted in an ATEX certified enclosure with a minimum ingress protection rating of at least IP 54 as defined in IEC EN 60529 and used in an environment of not more than Pollution Degree 2 A Caution The enclosure must have a door or cover accessible only by the use of a tool Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility EMC stated in the product specifications These requirements and limits provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment This product is intended for use in industrial locations However harmful interference may occur in some installations when the product is connected to a peripheral device or test object or if the product is used in residential or commercial areas To minimize interference with radio
138. to the C Series I O module s One property of buffered I O operations is sample mode The sample mode can be either finite or continuous Finite Finite sample mode generation refers to the generation of a specific predetermined number of data samples After the specified number of samples is written out the generation stops e Continuous Continuous generation refers to the generation of an unspecified number of samples Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation There are three different continuous generation modes that control how the data is written These modes are regeneration onboard regeneration and non regeneration Inregeneration mode you define a buffer in host memory The data from the buffer is continually downloaded to the FIFO to be written out New data can be written to the host buffer at any time without disrupting the output National Instruments 4 9 Chapter 4 Digital Input Output and PFI With onboard regeneration the entire buffer is downloaded to the FIFO and regenerated from there After the data is downloaded new data cannot be written to the FIFO To use onboard regeneration the entire buffer must fit within the FIFO size The advantage of using onboard regeneration is that it does not require communication with the main host memory once the operation is started which prevents problems that may occur due to
139. unter You can route the counter sample clock to the Gate input of the counter You can configure the counter to sample on the rising or falling edge of the sample clock Figure 5 22 shows an example of a buffered X1 position measurement Figure 5 22 Buffered Position Measurement Counter i i Sample se ae ames M M wea T AE LT Count 0 SK T 2 gt x lt 3 l 4 Buffer 1 1 Two Signal Edge Separation Measurement Two signal edge separation measurement is similar to pulse width measurement except that there are two measurement signals Aux and Gate An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting You must arm a counter to begin a two edge separation measurement After the counter has been armed and an active edge occurs on the Aux input the counter counts the number of rising or falling edges on the Source The counter ignores additional edges on the Aux input The counter stops counting upon receiving an active edge on the Gate input The counter stores the count in the FIFO You can configure the rising or falling edge of the Aux input to be the active edge You can configure the rising or falling edge of the Gate input to be the active edge Use this type of measurement to count events or measure the time that occurs between edges on two signals This type of measurement is sometime
140. ured as well You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate the high and low time of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Refer to the following sections for more information about cDAQ chassis pulse measurement options e Single Pulse Measurement Implicit Buffered Pulse Measurement e Sample Clocked Buffered Pulse Measurement Single Pulse Measurement Single on demand pulse measurement is equivalent to two single pulse width measurements on the high H and low L ticks of a pulse as shown in Figure 5 8 Figure 5 8 Single On Demand Pulse Measurement Counter Armed Gate i 1 i 1 i 1 i 1 Source i 1 i 1 Latched HL Value 1 2 3 4 6 6 7 12 8 4 6 6 F 8 9 10 70 Implicit Buffered Pulse Measurement In an implicit buffered pulse measurement on each edge of the Gate signal the counter stores the count in the FIFO The STC3 transfers the sampled values to host memory using a high speed data stream The counter begins counting when it is armed The arm usually occurs betw
141. ustable frequencies You can access the counter inputs and outputs using parallel digital I O modules installed in up to two slots or by using the two chassis PFI terminals provided on the cDAQ chassis Refer to Chapter 5 Counters for more information ni com Analog Input To perform analog input measurements insert a supported analog input C Series I O module into any slot on the cDAQ chassis The measurement specifications such as number of channels channel configuration sample rate and gain are determined by the type of C Series I O module used For more information and wiring diagrams refer to the documentation included with your C Series I O modules The cDAQ chassis has three AI timing engines which means that three analog input tasks can be running at a time on a chassis An analog input task can include channels from multiple analog input modules However channels from a single module cannot be used in multiple tasks Multiple timing engines allow the cDAQ chassis to run up to three analog input tasks simultaneously each using independent timing and triggering configurations The three AI timing engines are ai te0 and tel Analog Input Triggering Signals A trigger is a signal that causes an action such as starting or stopping the acquisition of data When you configure a trigger you must decide how you want to produce the trigger and the action you want the trigger to cause The cDAQ chassis supports internal soft
142. ut Some of these options may not be available in some driver software Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information about available routing options Counter n A Counter n B and Counter n Z Signals Counter n B can control the direction of counting in edge counting applications Use the A B and Z inputs to each counter when measuring quadrature encoders or measuring two pulse encoders Routing Signals to A B and Z Counter Inputs Each counter has independent input selectors for each of the A B and Z inputs Any of the following signals can be routed to each input e Any PFI terminal e Analog Comparison Event Routing Counter n Z Signal to an Output Terminal You can route Counter n Z out to any PFI terminal National Instruments 5 35 Chapter 5 Counters Counter n Up_Down Signal Counter n Up_Down is another name for the Counter n B signal Counter n HW Arm Signal The Counter n HW Arm signal enables a counter to begin an input or output function To begin any counter input or output function you must first enable or arm the counter In some applications such as a buffered edge count the counter begins counting when it is armed In other applications such as single pulse width measurement the counter begins waiting for the Gate signal when it is armed Counter output operations can use the arm signal in addition to a start trigger Software can arm
143. utes tab in MAX Clock Routing Figure 6 1 shows the clock routing circuitry of the cDAQ chassis Figure 6 1 Clock Routing Circuitry 80 MHz Timebase Onboard 80 MHz Oscillator 4 20 MHz Timebase 200 100 kHz Timebase National Instruments 6 1 Chapter 6 Digital Routing and Clock Generation 80 MHz Timebase You can use the 80 MHz Timebase as the Source input to the 32 bit general purpose counter timers The 80 MHz Timebase can be generated from the onboard oscillator 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals It can function as the Source input to the 32 bit general purpose counter timers The 20 MHz Timebase is generated by dividing down the 80 MHz Timebase as shown in Figure 6 1 100 kHz Timebase You can use the 100 kHz Timebase to generate many of the AI and AO timing signals It can also function as the Source input to the 32 bit general purpose counter timers The 100 kHz Timebase is generated by dividing down the 20 MHz Timebase by 200 as shown in Figure 6 1 6 2 ni com Where to Go from Here This section lists where you can find example programs for the cDAQ chassis and C Series modules and relevant documentation Example Programs NI DAQmx software includes example programs to help you get started programming with the cDAQ chassis and C Series modules Modify example code and save it in an
144. ware external digital triggering and analog triggering Three triggers are available Start Trigger Reference Trigger and Pause Trigger An analog or digital trigger can initiate these three trigger actions Up to two C Series parallel digital input modules can be used in any chassis slot to supply a digital trigger To find your module triggering options refer to the documentation included with your C Series I O modules For more information about using digital modules for triggering refer to Chapter 4 Digital Input Output and PFI Refer to the AI Start Trigger Signal AI Reference Trigger Signal and AI Pause Trigger Signal sections for more information about the analog input trigger signals Analog Input Timing Signals The cDAQ chassis features the following analog input timing signals e AI Sample Clock Signal e AI Sample Clock Timebase Signal Al Start Trigger Signal AI Reference Trigger Signal Al Pause Trigger Signal National Instruments 2 1 Chapter 2 Analog Input Signals with an support digital filtering Refer to the PFI Filters section of Chapter 4 Digital Input Output and PFT for more information Refer to the AJ Convert Clock Signal Behavior For Analog Input Modules section for AI Convert Clock signals and the cDAQ chassis Al Sample Clock Signal A sample consists of one reading from each channel in the AI task Sample Clock signals the start of a sample of all analog input channels in t
145. y signals However the accuracy decreases as the frequency of the signal to measure decreases At very low frequencies this method may be too inaccurate for your application Another disadvantage of this method is that it requires two counters if you cannot provide an external signal of known width An advantage of high frequency measurements with two counters is that the measurement completes in a known amount of time e Measuring a large range of frequencies with two counters measures high and low frequency signals accurately However it requires two counters and it has a variable sample time and variable error dependent on the input signal Table 5 5 summarizes some of the differences in methods of measuring frequency Table 5 5 Frequency Measurement Method Comparison Measures Number High Measures Low of Number of Frequency Frequency Counters Measurements Signals Signals Method Used Returned Accurately Accurately Low frequency 1 1 Poor Good with one counter High frequency lor2 1 Good Poor with two counters Large range of 2 1 Good Good frequencies with two counters Sample clocked 1 1 Good Good averaged National Instruments 5 17 Chapter 5 Counters For information about connecting counter signals refer to the Default Counter Timer Routing section Period Measurement In period measurements the counter measures a period on its Gate input signal after the counter is arme
146. you must reserve the task in advance through the DAQmx Control Task before any task has started If another task or route is actively using the module to avoid interfering with the other task NI DAQmx generates an error instead of sending the line configuration command During the line configuration command the output lines are maintained without glitching 4 14 ni com NI cDAQ 9188XT User Manual PFI You can configure channels of a parallel digital module as Programmable Function Interface PFI terminals The cDAQ chassis also provides two terminals for PFI Up to two digital modules can be used to access PFI terminals in a single chassis You can configure each PFI individually as the following Timing input signal for AI AO DI DO or counter timer functions Timing output signal from AI AO DI DO or counter timer functions PFI Filters You can enable a programmable debouncing filter on each PFI signal When the filter is enabled the chassis samples the inputs with a user configured Filter Clock derived from the chassis timebase This is used to determine whether a pulse is propagated to the rest of the circuit However the filter also introduces jitter onto the PFI signal The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several

NI cDAQ-9188XT User Manual

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