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8-Bit CMOS Microcontroller User`s Manual 06.99 http://www.siem

1. 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers Semiconductor Group SIEMENS Memory Organization C508 Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO after Reset E64 CT1OFL 004 7 6 5 4 3 2 1 0 E74 CT1OFH 00y 7 6 5 4 3 2 1 0 FO B 00 7 6 5 4 3 2 1 0 Fig CT2CON 0001 CT2P ECT2O STE2 CT2 CT2R CLK2 CLK1 CLKO 0000p RES F24 CCLO 00y 7 6 5 4 3 2 1 0 F34 CCHO 00j 7 6 5 4 i 2 1 0 F44 CCL1 00y 7 6 5 4 3 2 1 0 F54 CCH1 00j af 6 5 4 3 2 E 0 F64 CCL2 00H 7 6 5 4 3 2 A 0 F74 CCH2 00j 7 6 5 4 3 2 E 0 F842 P5 EE 6 5 4 3 2 E 0 F94 COTRAP 00y BCT PDTEN COUT2 CC2T COUT1 CC1T COUTO CCOT SEL T T T FB4 EINT XX00 IEX9 9FR IEX8 IBFR IEX7 I7FR 0000p FC 49 VRO C5H 1 1 0 0 0 1 0 1 FDy99 VR1 08H 0 0 0 0 1 0 0 0 FEH99 VR2 5 Y 6 5 4 3 2 1 0 FFL TRCON 00y TRPEN TRF A TREN5 TREN4 TREN3 TREN2 TREN1 TRENO 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set 4 These are read only registers 5 The content of this SFR varies with the
2. 1 0 Compare timer 1 is stopped and reset compare outputs are set to the logic state as defined in SFR COINI default after reset 0 0 1 Compare timer 1 starts Before CT1R is set the first time the CMSEL register should be programmed enable capture compare functions 1 0 1 Compare timer 1 starts running from count value 0000y compare outputs are set to the logic state as defined in SFR COINI 0 1 gt 0 Compare timer 1 is stopped and holds its value the compare outputs drive their actual logic state 1 1 gt 0 Compare timer 1 is stopped and reset to 0000jj compare outputs are set to the logic state as defined in SFR COINI Note for capture mode Setting CT1R 0 and CT1RES 1 after a capture event will destroy the value stored in the capture register CCx Therefore CT1RES should be set to 0 in capture mode Reason if CT1R20 and CT1RES 1 all shadow registers are transparent switched directly to the real registers Note When software power down mode is entered with CT1RES bit of SFR CT1CON set the compare timer 1 is reset after the execution of a wake up from power down mode procedure When CT1RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 1 is not reset Depending on the state of bit CT1R at power down mode entry the compare timer 1 either stops CT1R 0 or continues CT1R 1 counting after a wake u
3. PMSELO wo 99 Figure 10 2 OTP Programming Mode Pin Configuration for P MQFP 64 1 Package Top View Semiconductor Group 10 2 SIEMENS OTP Memory Operation C508 Figure 10 3 shows the detailed pin configuration of the C508 4E in programming mode for P SDIP 64 2 package 1 2 3 4 5 6 7 8 VDD Vss A0 A8 A1 A9 A2 A10 A3 A11 A4 A12 A5 A13 A6 A14 A7 PSEN PROG VDD Vss XTAL1 XTAL2 NC NC NC PALE PRD PSEL PMSEL1 PMSELO NC NC NC NC NC NC NC NC Figure 10 3 OTP Programming Mode Pin Configuration for P SDIP 64 Package Top View Semiconductor Group 10 3 SIEMENS OTP Memory Operation C508 10 3 Pin Definitions The following table 10 1 contains the functional description of all C508 4E pins which are required for OTP memory programming Table 10 1 Pin Definitions and Functions of the C508 4E in Programming Mode Symbol Pin Number l O Function P MQFP64 P SDIP64 RESET 1 9 Reset This input must be at static 1 active level during the whole programming mode PMSELO 33 41 Programming mode selection pins PMSEL1 34 42 These pins are used to select the different access modes in programming mode PMSEL1 0 must satisfy a setup time to the rising edge of PALE When the logic level of PMSEL1 0 is changed PALE must be at low level PMSEL1 PMSELO Access Mode 0 0 Reserved 0 1 Read si
4. ALE EA Vi Vine RESET Vi Data 1 Out Data 2 Out Figure 4 4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN ALE EA and RESET are put to the specified logic level Then the 15 bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines After a delay time port O outputs the content of the addressed ROM cell In ROM verification mode 1 the C508 must be provided with a system clock at the XTAL pins and pullup resistors on the port O lines Semiconductor Group 4 10 SIEMENS External Bus Interface C508 4 7 2 Protected ROM OTP Mode If the C508 4R ROM is protected by mask or C508 4E OTP in protection level 1 the ROM OTP verification mode 2 as shown in Figure 4 5 is used to verify the contents of the ROM Please refer the AC specifications in C508 data sheet for a detailed timing characteristics of the ROM verification mode RESET ET 1 ALE pulse after reset Latch a Latch h Latch Latch Latch Data for Data for Data for a Data for Ad j Addr 0 Adar 1 Adar 2 X 16 1 X6 1 Inputs ALE Vss Verify Result for previous DSEN En 16 bytes of data PSEN EA Vu Low Verify Error RESET X High Verify OK Note Please refer to C508 data sheet for the definition of TCL Figure 4 5 ROM Verification Mode 2 ROM OTP verification mode 2 is selected if the inputs PSEN EA and ALE are put to the specified logic levels With RESET going i
5. Count Value CT1 CT10FF A 9 CCP 7 Period Reg CTIOF 22 Offset Reg gt 0 0 Start of CT1 p Time Cycles CCx CC 5 o COINI Bit 0 4L en ee 0 e dr zi COUTx CC 5 5 COINI Bit 0 Ld xc e ic COUTx CC 5 COINI Bit 1 pie CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT1OF content of the CT1OFH CT1OFL offset registers MCT02603 Figure 6 28 Compare Timer 1 with Offset 0 Dead Time Mode 1 In the example above compare timer 1 counts from 0000 up to 00074 value stored in period register CCPH CCPL and then counts down again to 0000H The maximum and minimum 0000 values of the compare timer 1 occur always once in the count value sequence In the example shown in Figure 6 28 the offset registers have a value of 0002 With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level which is defined by the bits in SFR COINI In operating mode 0 two compare output signals CCx and COUTx are assigned to the related CAPCOM channel The compare outputs CCx change their state if a match of compare timer 1 content and the corresponding compare register occurs The compare outputs COUTx change their state when a match of compare timer 1 content plus the value stored in the offset registers and the corresponding compare register has occurred If the val
6. Note The prescaler ratios in Table 6 14 are minimum values Semiconductor Group 6 124 SIEMENS On Chip Peripheral Components C508 tADCC us 20 t ADCC min 6 US 10 5 fosc 5 6 7 8 9 10 MHz Figure 6 53 Minimum A D Conversion Time in Relation to Oscillator Clock Semiconductor Group 6 125 SIEMENS On Chip Peripheral Components C508 6 5 5 A D Converter Calibration The C508 A D converter includes hidden internal calibration mechanisms which assure a safe functionality of the A D converter according to the DC characteristics The A D converter calibration is implemented in a way that a user program which executes A D conversions is not affected by its operation Further the user program has no control over the calibration mechanism The calibration itself executes two basic functions Offset calibration correction of offset errors of comparator and the capacitor network Linearity calibration correction of the binary weighted capacitor network The A D converter calibration operates in two phases First phase is the calibration after a reset operation and the second is the calibration at each A D conversion The calibration phases are controlled by a state machine in the A D converter This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM After a reset operation the A D calibration is automatically started This reset calibra
7. PCON 7 Baud SMOD Rate Generator SRELH SRELL Only one mode can be selected Note The switch configuration shows the reset state Figure 6 41 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baud rate clock generation Figure 6 41 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register SCON 6 4 3 1 Baud Rate in Mode 0 The baud rate in mode 0 is fixed to oscillator frequency 3 Mode 0 baud rate 6 4 3 2 Baud Rate in Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON If SMOD 0 which is the value after reset the baud rate is 1 16 of the oscillator frequency If SMOD 1 the baud rate is 1 8 of the oscillator frequency SMOD Mode 2 baud rate x oscillator frequency Semiconductor Group 6 102 SIEMENS On Chip Peripheral Components C508 6 4 3 3 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1 6 4 3 3 1 Using the Internal Baud Rate Generator In modes 1 and 3 the C508 can use an internal baud rate generator for the serial port To enable this feature bit BD bit 7 of special function register ADCONO must be set Bit SMOD PCON 7 controls a divide by 2 cir
8. 1 1 0 0 0 1 0 inactive inactive inactive inactive inactive 2 1 0 6 1 active inactive inactive inactive active 5 2 0 6 2 active active inactive inactive inactive 1 3 0 6 3 inactive active active inactive inactive 2 4 0 6 4 inactive inactive active active inactive 3 5 0 6 5 inactive inactive inactive active active 4 1 0 6 6 inactive active inactive active active 2 1 0 6 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Semiconductor Group 6 94 SIEMENS On Chip Peripheral Components C508 Table 6 13 6 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUTO CC1 COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive inactive inactive 2 1 0 7 1 active active inactive inactive inactive inactive 5 2 0 7 2 inactive active active inactive inactive inactive 1 3 0 7 3 inactive inactive active active inactive inactive 2 4 0 7 4 inactive inactive inactive active active inactive 3 5 0 7 5 inactive inactive inactive inactive active active 4 6 0 7 6 active inactive inactive inactive inactive active 5 1 0 7 7 inac
9. COTRAP Compare output in trap state register F9y The following sections describe the CAPCOM registers in detail Semiconductor Group 6 57 SIEMENS On Chip Peripheral Components C508 Writing the CAPCOM Period Offset Compare Registers on the Fly If compare timer 1 is running period offset or compare registers can be written with modified values for generating new periods or duty cycles of the compare output signals For proper synchronization purposes a special mechanism for updating of the 16 bit offset period and compare registers is implemented in the C508 This mechanism is based on shadow latches When new values for offset period or compare registers have been written into the shadow latches the real register update operation must be initiated by setting bit STE1 shadow transfer enable in SFR CT1CON When this bit is set the content of the shadow latches is transferred to the real registers when compare timer 1 has reached its period value or zero value This applies to both operating modes 0 and 1 When the register transfer has been executed STE1 is reset by hardware So the software can recognize when the register transfer has occurred When compare timer 1 is started by setting the run bit CT1R the first time after reset a shadow register transfer into the real registers is automatically executed In this case STE1 must not be set Care must be taken when programming a new compare value If the new compa
10. FDH mapped addr FEL C508 4E AA Step C5H 08H 01y Note Future steppings of C508 would have a different version byte 2 content Semiconductor Group 10 12 SIEMENS OTP Memory Operation C508 Semiconductor Group 10 13 SIEMENS C508 11 Index Period registers 6 78 A SULVOy erre 6 75 3 channel CAPCOM unit 6 46 6 73 A D converter 6 115 6 126 Burstmode ios iu dis da chee ud 6 53 Block diagram 6 116 Capture mode 6 54 Calibration mechanisms 6 126 Clocking scheme 6 46 Clock selection ee EAP Dette 6 121 Operating mode 0 6 47 6 49 Conversion time calculation 6 124 Operating mode 1 6 50 Conversion timing Bed Svat RRE 6 122 Priod and resolution a 6 51 6 52 General operation 2k s 6 115 Registers 6 57 6 73 Registers IE 6 117 6 120 Capture compare registers 6 65 System clock relationship 6 123 CT1 control register 6 59 BU c suo NC 2 4 3 16 Interrupt enable register 6 68 ACC 5 st ae e ERE 2 3 3 12 3 17 Interrupt request register 6 66 ADCO ve dated il i o 3 17 Mode select registers 6 63 ADGIE sodas ino 3 17 Offset registers 6 62 ADCOND nia 9 18 9 75 9 T778 101 Output initialization register 6 70 ADOONT seis ci 3 12 3 17 Period registers 6 61 ADDATH pipea ne a i e 3 12 3 17 A eee 6 57 ADDATE het tid enan he
11. IEX5 and IEX6 in register IRCON In addition these flags will be set if a compare event occurs at the corresponding pins P5 1 T2CC1 INT4 P5 2 T2CC2 INT5 and P5 3 T2CC3 INT6 regardless of the compare mode established and the transition at the respective pin When an interrupt is generated the flag that generated it is cleared by hardware when the service routine is vectored to Semiconductor Group 7 13 SIEMENS Interrupt System C508 Special Function Register IRCON Address COg Reset Value X0000000p MSB LSB Bit No C7H C64 Cdy C4y C34 C24 C1y Coy COy TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCON Bit Function TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P5 3 T2CC3 INT6 Cleared when interrupt is processed IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P5 2 T2CC2 INT5 Cleared when interrupt is processed IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P5 1 T2CC1 INT4 Cleared when interrupt is processed IEX3 External interrupt 3 edge flag Set by hardware when external in
12. If EBCE is set the emergency interrupt for a block commutation mode error condition of the CCU is enabled In block commutation mode an emergency error condition occurs if a false signal state at INT2 INTO or a wrong follower state if selected by bit BCEM is detected see also Table 6 10 Semiconductor Group 6 82 SIEMENS On Chip Peripheral Components C508 Bit Function BCERR Block commutation mode error flag In block commutation mode BCERR is set in rotate right or rotate left mode if after a transition at INTx all INTx inputs are at high or low level Additionally in rotate right or rotate left mode a wrong follower condition according to Table 6 10 can cause the setting of BCERR see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 the setting of BCERR will generate a CCU emergency interrupt BCERR must be reset by software BCEN Block commutation enable If BCEN is set the multi channel PWM modes of the CAPCOM unit as selected by the bits PWM1 PWMO are enabled for operation Before BCEN bit is set all required PWM compare outputs should be programmed to operate as compare outputs by writing the registers CMSEL1 CMSELO BCM1 Multi channel PWM mode output pattern selection BCMO Additionally to bits PWM1 and PWMO these two control bits select the output signal pattern in all multi channel PWM modes The detailed signal pattern information is given in Table 6 10 to Table 6
13. Interrupt is latched are polled Vector Address Routine Figure 7 6 Interrupt Response Timing Diagram Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in Figure 7 6 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Semiconductor Group 7 24 SIEMENS Interrupt System C508 Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated LCALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored to as shown in the following Table 7 3 Table 7 3 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003H IEO Timer O Overflow 000BH TFO External Interrupt 1 0013y IE1 Timer 1 Overflow 001By TF1 Serial Channel 0023 RI TI Timer 2 Overflow 002By TF2 A D Converter 0043H IADC
14. Rotate right 1 o inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive inactive Rotate left inactive inactive active active inactive inactive 60 phase shift inactive active inactive active inactive inactive BCTSEL 0 MN ead Malla an are default inactive active inactive inactive inactive active active inactive inactive inactive inactive active active inactive inactive inactive active inactive inactive inactive active inactive active inactive Rotate left inactive inactive active inactive active inactive O phase shift inactive inactive active active inactive inactive BCTSEL 1 inactive active inactive active inactive inactive inactive active inactive inactive inactive active active inactive inactive inactive inactive active active inactive inactive inactive active inactive Rotate right active inactive inactive inactive active inactive active inactive inactive inactive inactive active inactive active inactive inactive inactive active inactive active inactive active inactive inactive inactive inactive active active inactive inactive inactive inactive active inactive active inactive Slow down inactive inactive inactive active active active Idle 2 lt x M
15. bit RMAP in special function register SYSCON must be set All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared 0 Special Function Register SYSCON Address B1y Reset Value XX10XX01 pg Bit No MSB LSB 7 6 5 4 3 2 1 0 Biy H EALE RMAP XMAP1XMAPO SYSCON 5 The functions of the shaded bits are not described here Bit Function RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area is enabled Reserved bits for future use Read by CPU returns undefined values As long as bit RMAP is set mapped special function register area can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set respectively by software All SFRs with addresses where address bits 0 2 are 0 e g 80H 88y 90H 98H F8y FFH are bitaddressable The 79 special function registers SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C508 are listed in Table 3 2 and Table 3 3 In Table 3 2 they are organized in groups which refer to the functional blocks of the C5
16. high byte C3y T2CCL2 Compare capture register 2 low byte C4y T2CCH2 Compare capture register 2 high byte C5H T2CCL3 Compare capture register 3 low byte C6y T2CCH3 Compare capture register 3 high byte C7H IENO Interrupt enable register O A8H IEN1 Interrupt enable register 1 B8y IRCON Interrupt control register COH Semiconductor Group 6 25 On Chip Peripheral Components C508 SIEMENS The T2CON timer 2 control register is a bit addressable register which controls the timer 2 function and the compare mode of registers CRC T2CC1 to T2CC3 Special Function Register T2CON Address C84 Reset Value 0000X0X0p Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy CE CD CCy CBy CA C9y C8y C84 T2PS ISFR I2FR T2R T2CM T2l T2CON The shaded bits are not used for controlling timer counter 2 Bit Function T2PS Prescaler select bit When set timer 2 is clocked with 1 6 of the oscillator frequency When cleared timer 2 is clocked with 1 3 of the oscillator frequency ISFR External interrupt 3 falling rising edge flag Used for capture function in combination with register CRC If set a capture to register CRC if enabled will occur on a positive transition at pin P5 0 T2CC0 INT3 T2R Timer 2 reload enable T2R Function 0 Reload disabled 1 Auto reload upon timer 2 overflow TF2 T2CM Compare mode bit for registers CRC T2CC1 through T2CC3 When set
17. register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 4 SIEMENS Fundamental Structure C508 2 2 CPU Timing The C508 has no clock prescaler Therefore a machine cycle of the C508 consists of 6 states 3 oscillator periods Each state is divided into a phase 1 half and a phase 2 half Thus a machine cycle consists of 3 oscillator periods numbererd S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts half an oscillator period Typically arithmetic and logic operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in Figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL1 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Execution of a one cycle instruction begins at S1P2 when
18. value stored in CCPH CCPL The offset registers CTTOFH CT1OFL have a value of 0000p If programmed in compare mode two output signals CCx and COUTx are assigned to the related CAPCOM channel x The mode select bits in the SFRs CMSELO and CMSEL1 define which of these two outputs will be Semiconductor Group 6 47 SIEMENS On Chip Peripheral Components C508 controlled by the CAPCOM channel In Figure 6 26 only the CCx signal is shown but the same or the inverted waveform can be generated at the COUTx outputs After reset all CCx COUTx pins are at high level driven by a weak pullup With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level which is defined by the bits in SFR COINI In Figure 6 26 the upper five waveforms are assigned to a CCx pin with the appropriate bit in COINI cleared while the lower five waveforms are assigned to a CCx pin with the appropriate bit in COINI set When the count value of the compare timer 1 is incremented and the new value matches with the value stored in the corresponding compare register the related compare output changes its logic state When the compare timer is reset to 0000p the related compare output changes its logic state again With the scheme shown in Figure 6 26 output waveforms with duty cycles between 096 and 100 can be generated For a compare register value of 0O00y the output will remain at high lev
19. 00001 After reset is internally accomplished the port latches of ports 0 1 2 3 and 5 default in FFy This leaves port 0 floating since it is an open drain port when not used as data address bus All other I O port lines ports 1 3 and 5 output a one 1 Port 2 lines output a zero or one after reset if the EA is held low or high Port 4 is a uni directional input port It has no internal latch and therefore the contents of the special function register P4 depend on the levels applied to port 4 The internal SFRs are set to their initial states as defined in table 3 2 The contents of the internal RAM and XRAM of the C508 are not affected by a reset After power up the contents are undefined while it remains unchanged during a reset if the power supply is not turned off Semiconductor Group 5 2 SIEMENS Reset System Clock C508 5 2 Fast Internal Reset after Power On The C508 uses the oscillator watchdog unit for a fast internal reset procedure after power on The clock source is provided by the RC oscillator during the internal reset procedure When the on chip oscillator is stabilised its clock output is multiplied by a fixed factor of 2 by the on chip PLL The clock from the PLL is then provided as the system clock Thus the system clock frequency is twice the external oscillator frequency Figure 5 1 shows the power on sequence under the control of the oscillator watchdog Normally the devices of the 8051 family do not enter the
20. 00H CY AC FO RS1 RSO OV F1 P 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers Semiconductor Group 3 16 SIEMENS Memory Organization C508 Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 X Bit3 Bit2 Bit1 Bit 0 after Reset D2y CP2L 00H Yi 6 5 4 3 2 A D3y CP2H XXXX A 0 XX00p D4y CMP2L 00y 7 6 5 4 3 2 A D5y CMP2H XXXX A 0 XX00p D6y CCIE 00H ECTP ECTC CC2 CC2 CC1 CC1 CCO CCO FEN REN FEN REN FEN REN D74 BCON 00H BCMP PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCEM D8y ADCONO 00X0 BD CLK BSY ADM MX2 MX1 MXO 0000p D94 ADDATH 00y 9 7 6 S 4 3 2 DAW ADDATL 00XX XXXXB DBy P4 7 6 5 4 3 2 A 0 DCH ADCON1 01XX ADCL1 ADCLO MX2 MX1 MXO X000p DEW CCPL 00H 6 D 4 3 2 1 0 DFy CCPH 00H 6 5 4 3 2 A 0 E0y ACC 00H 6 5 4 3 2 A 0 Ely CT1CON 0001 CTM ETRP STE1 CT CT1R CLK2 CLK1 CLKO 0000p RES E24 COINI FFy COUT COUTX COUT CC2 COUT CC1l COUT CCOI 3l 2l 11 ol ESy CMSELO 00y CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 E44 CMSEL1 00y ESMC NMCS 0 0 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 E5H CCIR 00H CT1FP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR
21. 13 BCM1 BCMO Function 0 0 Idle mode 0 1 Rotate right mode 1 0 Rotate left mode 1 1 Slow down mode Note When a multi channel PWM mode is initiated the first time after reset BCON must be written twice first write operation with bit BCEN cleared and all other bits set cleared as required BCM1 0 must be 0 0 for idle mode followed by a second write operation with the same BCON bit pattern of the first write operation but with BCEN set After this second BCON write operation compare timer 1 can be started setting CT1R in CT1CON and thereafter BCM1 0 can be put into another mode than idle mode Semiconductor Group 6 83 SIEMENS On Chip Peripheral Components C508 6 3 4 2 Signal Generation in Multi Channel PWM Modes The multi channel PWM modes of the C508 use the pins CCx and COUTx for compare output signal generation Before signal generation of a multi channel PWM mode can be started the COINI register should be programmed with the logic value of the multi channel PWM inactive phase After this the output pins which are required for the multi channel PWM signal generation must be programmed to operate as compare outputs by writing the mode select registers CMSELO and CMSEL1 Table 6 9 shows the CMSELO CMSEL1 register bits which are required for the full operation of the multi channel PWM modes Table 6 9 Programming of Multi Channel PWM Compare Outputs Multi Channel PWM Mode
22. A 3 2 1 0 AAW SRELL D9y oh 6 i5 4 3 2 A 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 3 15 SIEMENS Memory Organization C508 Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset BOW P3 FFH RD WR T1 TO INT1 INTO TxD RxD Bi SYSCON XX10 EALE RMAP XMAP1 XMAPO XX01p B8y IEN1 X000 SWDT EX6 EX5 EX4 EX3 EX2 EADC 0000p B94 IP1 XX00 5 4 3 2 A 0 0000p BAW SRELH XXXX A 0 XX1ip BEL IEN3 XXX0 EX9 EX8 EX7 00XXp COL IRCON X000 TF2 IEX6 IEX5 IEX4 EX3 IEX2 IADC 0000p Cip CCEN 00H COCA COCAL COCA COCAL COCA COCAL COCA COCAL H3 3 H2 2 H1 1 HO 0 C24 T2CCL1 00y af 6 5 4 3 2 A 0 C34 T2CCH1 00H d 6 3 4 3 2 A 0 C4y T2CCL2 00y 7 6 5 4 i3 2 A 0 C5y T2CCH2 00H a 6 D 4 3 2 A 0 C6y T2CCL3 00y zy 6 5 4 3 2 1 0 C74 T2CCHS3 00y 7 6 5 4 3 2 A 0 C8y T2CON 0000 T2PS ISFR I2FR T2R T2CM T2l X0X0p CAL CRCL 00H 4 6 5 4 i 2 1 0 CBy CRCH 00H 7 6 5 4 3 2 1 0 CCH TL2 00H of 6 5 4 3 2 A 0 CDy TH2 00H 7 6 5 4 3 2 1 0 DO PSW
23. Bus a PO Bus Ri lt P2 gt 31 0_ P2 gt 1 0_ P21 0_ P2 gt 1 0_ P2 gt 31 0_ P21 0_ XRAM b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active addr page c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is range used used used used used used XPAGE a PO Bus a PO Bus a PO Bus a PO P2 gt 1 O a PO gt Bus a PO Bus gt RD WR Data RD WR Data P2 gt 1 0 RD WR Data P2 gt 1 0 XRAM P2 4 O P2 UO na P2 O NES addr page b RD WR b RD WR active b RD WR active b RD WR b RD WR active b RD WR active range inactive inactive c XRAM is used c XRAM is used c ext memory is used c XRAM is used c XRAM is used c ext memory is used modes compatible to 8051 C501 family Table 3 1 Behaviour of PO P2 and RD WR During MOVX Accesses SN3IN3IS uoneziueBa4o Aowa 8059 SIEMENS Memory Organization C508 3 5 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The special function register area consists of two portions the standard special function register area and the mapped special function register area One special function register of the C508 PCON 1 is located in the mapped special function register area For accessing the mapped special function register area
24. CCLx CT1OFH CT1OFL is transferred to its real registers when compare timer 1 reaches the next time the period value or value 0000 After the shadow transfer event STE1 is reset by hardware CLK2 Compare timer 1 input clock selection CLK1 The input clock for the compare timer 1 is derived from the clock rate fosc of CLKO the C508 via a programmable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function Compare timer 1 input clock is 2fosc Compare timer 1 input clock is fosc Compare timer 1 input clock is fosc 2 Compare timer 1 input clockis fosc 4 Compare timer 1 input clock is fosc 8 Compare timer 1 input clockis fogc 16 Compare timer 1 input clock is fos 32 O O O AO OIOI gt Olo 0 1 0 1 0 1 0 1 Compare timer 1 input clock is fosc 64 Semiconductor Group 6 59 SIEMENS On Chip Peripheral Components C508 Bit Function CT1RES Compare timer 1 reset control CT1R Compare timer 1 run stop control These two bits control the start stop and reset function of compare timer 1 CT1RES is used to reset the compare timer and CT1R is used to start and stop the compare timer 1 The following table shows the functions of these two bits CT1RES CT1R Function 0 0 Compare timer 1 is stopped and holds its value the compare outputs stay in the logic state as they are
25. ERU Re REPE EDUmRI 6 82 6 3 4 2 Signal Generation in Multi Channel PWM Modes o ococcoocooccc eee 6 84 6 3 4 3 Block Commutation PWM Mode eee eee 6 87 6 3 4 4 Phase Delay Timer Sra eis od beds av os a ete x Wea ee ater ata dee e Mw 6 90 6 3 4 5 Compare Timer 1 Controlled Multi Channel PWM Modes 6 91 6 3 4 6 Software Controlled State Switching in Multi Channel PWM Modes 6 96 Semiconductor Group l 2 SIEMENS General Information C508 6 3 4 7 Trap Function in Multi Channel Block Commutation Mode 6 97 6 4 Serial Intel ACE io reves Bat AR xr Rc 6 98 6 4 1 Multiprocessor Communication eeeleeeee eee 6 99 6 4 2 Serial Port Registers 6tetchce cardos cara da sitae ahi edat aa 6 99 6 4 3 Baud Rate Generation tot et o ador AE dah E ede tid 6 101 6 4 3 1 Baud Rate in Mode Desgaste ia nig rhe nU ROO P prd as 6 102 6 4 3 2 Baud Rate in Mode 2 2 2 be EXAM PER AA DELS RESEIG A ees 6 102 6 4 3 3 Baud Rate in Mode 1 and 3 lt 5 were seb A E e SIN utt Qr wd 6 103 6 4 4 Details about Mode O 3 5 9 ia eos mene pd pa be 6 106 6 4 5 Details about MOSS ascia otc tO la Sot and de C reve de eet d 6 109 6 4 6 Details about Modes2and3 ocoocccccccco eren 6 112 6 5 A D Converter esop ao dd e Deo lee REFER Een ce e ete 6 115 6 5 1 AID Converter Operation sisse erem alla ERR n ERR A 6 115 6 5 2 A D Converter Registers osse kk RE XR AAA 6 117 6 5 3 A D Conve
26. External Interrupt 2 004By IEX2 External Interrupt 3 0053H IEX3 External Interrupt 4 005By IEX4 External Interrupt 5 0063H IEX5 External Interrupt 6 006By IEX6 CAPCOM Emergency Interrupt 0093H TRF BCERR Compare Timer 2 Interrupt 009BH CT2P Capture Compare Match Interrupt 00A3H CCxF CCxF x 0to 2 Compare Timer 1 Interrupt 00ABH CT1FP CT1FC External Interrupt 7 00D3y IEX7 External Interrupt 8 00DBy IEX8 External Interrupt 9 00E3y IEX9 Wake up from power down mode 007By Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have Semiconductor Group 7 25 SIEMEN Interrupt System S C508 left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged 7 5 External Interrupts The external interrupts O and 1 can be programmed to be level activated or negative transition activated by setting or clearin
27. Figure 6 24 b and d can be generated Further the initial logic output level of the CAPCOM channel outputs can be selected in compare mode This allows to generate waveforms with inverting signal polarities In capture mode of the CAPCOM unit the value of compare timer 1 is stored in the capture registers on a signal transition at pins CCx The compare unit COMP is a 10 bit compare unit which can be used to generate a pulse width modulated signal This PWM output signal drives the output pin COUTS In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs The block commutation control logic allows to generate versatile multi channel PWM output signals In one of these modes the block commutation mode signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic Depending on these signal transitions the six I O lines of the CAPCOM unit which are decoupled in block commutation mode from the three capture compare channels are driven as static or PWM modulated outputs CAPCOM channel 0 can be used in block commutation mode for a capture operation speed measurement which is triggered by each transition at the external interrupt inputs Further the multi channel PWM mode signal generation can be also triggered by the period of compare timer 1 These operating modes are referenced as multi channel PWM modes Using the CTRAP input signal of the C508 the
28. T BCON Prescalar z E e z z M Figure 6 23 Block Diagram of the Capture Compare Unit CCU Semiconductor Group 6 43 On Chip Peripheral Components SIEMENS C508 6 3 1 The compare timer 1 and 2 are free running processor clock coupled 16 bit 10 bit timers which have each a count rate with a maximum of 2fosc up to fos 64 The compare timer operations with its possible compare output signal waveforms are shown in Figure 6 24 General Capture Compare Unit Operation Compare Timer 1 Operating Mode 0 a Standard PWM Edge Aligned Period _ Value Compare alue 0000 Compare Timer 1 Operating Mode 1 c Symetrical PWM Center Aligned Compare alue 00004 CCx COINI 0 COUTx COINI 1 b Standard PWM Single Edge Aligned with programmable dead time torf Compare alue Offset 1 a d Symetrical PWM Center Aligned with programmable dead time tore Period Value Compare alue Offset4 CCx COINI 0 COUTx COINI 1 4 Interrupts can be generated Figure 6 24 Basic Operating Modes of the CAPCOM Unit Semiconductor Group 6 44 SIEMENS On Chip Peripheral Components C508 Both compare timers start counting upwards from 0000y up to a count value stored in the period registers If the value stored in the period register is reached they are reset operating mode 0 both compare timers or the count direction is changed from
29. The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS If software power down mode is activated the RC oscillator the on chip oscillator and the PLL are stopped Both oscillators and the PLL are again started in power down mode when a low level is detected at either P3 2 INTO or P5 7 INT7 and when bit EWPD in SFR PCONI is set wake up from power down mode enabled Bit WS in SFR PCON1 selects the wake up source In this case the oscillator watchdog does not execute an internal reset during startup of the on chip oscillator After the start up phase of the on chip oscillator the watchdog generates a power down mode wake up interrupt Detailed description of the wake up from software power down mode is given in section 9 4 2 Fast Internal Reset after Power On The C508 can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g SAB 80C52 do not enter their default reset state before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the C508 the oscillator
30. The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in Table 6 3 If the destination is a port or a port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO P2 and P3 for example MOV A P3 reads the value from port 3 pins while ANL P3 0AAH reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in Table 6 3 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Table 6 3 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANLP1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instr
31. actual step of the C508 eg 014 for C508 4E first step and 11 y for C508 4R first step Semiconductor Group 3 18 SIEMENS Memory Organization C508 Semiconductor Group 3 19 SIEMENS External Bus Interface C508 4 External Bus Interface The C508 allows for external memory expansion The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception It is the suppression of the ALE signal generation when C508 is used in systems with no external memory Resetting EALE bit in SFR SYSCON will be gated off the ALE signal This feature reduces RFI emissions of the system 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port O and port 2 with exceptions are used to provide data and address signals In this section only the port O and port 2 functions relevant to external memory accesses are described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri 4 1 1 Role o
32. after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD Nevertheless the slow down mode keeps enabled and if required has to be terminated by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow down mode power saving The other possibility of terminating the combined idle and slow down mode is a hardware reset Since the oscillator is still running the hardware reset has to be held active for only two machine cycles for a complete reset Semiconductor Group 9 5 SIEMENS Power Saving Modes C508 9 4 Software Power Down Mode In the software power down mode the RC oscillator the on chip oscillator which operates with the XTAL pins and the PLL are all stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE and PSEN are held at logic low level see Table 9 1 In the power down mode of operation Vpp can be reduced to minimize power consumption It must be ensured however that Vpn is not reduced before the power down mode is invoked and that V
33. an oscillator watchdog reset occured Can be set and cleared by software Semiconductor Group 8 6 SIEMENS Fail Save Mechanisms C508 8 2 1 Detailed Description of the Oscillator Watchdog Unit Figure 8 3 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for comparison with the frequency of the on chip oscillator It also shows the additional provisions for integration of the wake up from power down mode EWPD WS PCON1 o gen 4 Power down mode activated Power down mode P5 INE wake up interrupt Control P3 SING Logic pe g Internal Reset Start stop RC Oscillator PE Frequency Comparator XTAL2 Start O stop On Chip xTAL1 Oscillator _fosc IPO A9 e System Clock System Clock 2xf sc Generation Figure 8 3 Functional Block Diagram of the Oscillator Watchdog The frequency from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition In this case the RC oscillator provides the clock source for system clock generation This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the
34. assigned to the COUTx compare outputs TRENx 0 Compare channel output provides CAPCOM output signal in trap state TRENx 1 Compare channel output is enabled to set the logic level of the compare output CCx or COUTx in the trap state to a logic state as defined by the corresponding bits of the COTRAP register When writing TRENO 5 bit TRF should be reset to 0 Otherwise setting TRENO 5 will generate a software trap interrupt Semiconductor Group 6 72 SIEMENS On Chip Peripheral Components C508 Compare Output in Trap State Register The six lower bits of the COTRAP register define the values of port 1 pins 2 to 7 which are programmed to be used as compare outputs when a trap state is entered Bit 6 enables the phase delay timer for block commutation mode when set Bit 7 selects either one of the two block commutation tables for rotate left that is provided Special Function Register COTRAP Address F94 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 F94 BCTSEL PDTEN COUT2T CC2T COUT1T CC1T COUTOT CCOT COTRAP CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function BCTSEL Block Commutation Table Rotate Left Select BCTSEL 0 The table for 60 phase angle will be selected BCTSEL 1 The table for O phase angle will be selected PDTEN Phase Delay Timer Enable When set phase delay timer for block commutation mode will be enabled CC
35. at slower Vpp rise times the delay time will be less than the two values given above After the on chip oscillator has finally started Figure 5 2 III and the PLL locked the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to ensure a stable clock is available from the PLL Figure 5 2 IV Subsequently the system clock is supplied by the PLL and the oscillator watchdog s reset is released Figure 5 2 V However an externally applied reset still remains active and the device does not start program execution before the external reset is also released Figure 5 2 VI Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Fastreset of Compare Capture output pins during power on Semiconductor Group 5 3 dnog jojonpuoorues v S c S ainbig 9062 y JO J9S9Y uQ 19MOd Ports except P1 On chip Osc PLL RC Osc RESET undef Reset SEES m s ium Il Hl IV V VI Power On l On PLL Port remains undef Port Clock from RC Oscillator Chip y locks in ir eres lyp 18us Reset at Ports Osc Final Reset because of Start of m
36. baud rate is given by the formula 28M0D x oscillator frequency Mode 1 3 baud rate 32 x 3 x 256 TH1 Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001 p and using the timer 1 interrupt for a 16 bit software reload Semiconductor Group 6 105 SIEMENS On Chip Peripheral Components C508 6 4 4 Details about Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at fosc 3 Figure 6 43 shows a simplified functional diagram of the serial port in mode O The associated timing is illustrated in Figure 6 44 Transmission is initiated by any instruction that uses SBUF as a destination register The Write to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between Write to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S3 84 and S5 of every machine cycle and high during S6 S1 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift r
37. be used as high impendance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pullup transistors when issuing 1 s Port O also outputs the code bytes during program verification in the C508 4R External pullup resistors are required during program verification P5 0 P5 7 15 22 23 30 O Port5 is a an 8 bit quasi bidirectional I O port with internal pullup transistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current jj in the DC characteristics because of the internal pullup transistors As secondary functions port 5 contains the interrupt and Timer 2 capture compare pins They are assigned to the pins as follows P5 0 T2CCO INT3 T2 Compare Capture output 0 Interrupt 3 input P5 1 T2CC1 INT4 T2 Compare Capture output 1 Interrupt 4 input P5 2 T2CC2 INT5 T2 Compare Capture output 2 Interrupt 5 input P5 3 T2CC3 INT6 T2 Compare Capture output 3 Interrupt 6 input P5 4 INT2 Interrupt 2 input P5 5 INT9 Interrupt 9 input P5 6 INT8 Interrupt 8 input P5 7 INT7 Interrupt 7 input Input O Output Semiconductor Group 1 10 SIEMENS Introduction C508 Symbol Pin Numbers l O Function P MQF
38. bus interface 4 1 EXI ons toc rl a TP 3 18 ALE signal 4 4 BITS dad Cassie ecu s te ed 3 16 ALE switch off control 4 4 NST MR TERES 3 16 Overlapping of data program memory 4 3 Interrupt system 7 1 7 27 Program memory access 4 3 Interrupts Program data memory timing 4 2 Block diagram 7 2 7 6 PSENsignal sss 4 3 Enable registers 7 7 7 14 Role of PO and P2 4 1 External interrupts 7 26 F Handling procedure 7 24 FO arar 3 16 Priority registers 7 21 A ertet Eu 3 16 Priority within level structure 7 22 Fail save mechanisms 8 1 8 8 Request flags 7 12 7 19 Fast power on reset 5 3 8 8 Response time 7 27 Features auus Leid iu MAL Ste erf 1 2 Sources and vector addresses 7 25 Functional units 1 1 IPO d RE 3 12 3 14 3 15 8 3 8 6 Fundamental structure 2 1 IP rd vada 3 12 3 16 G IRCON cua ens 3 12 3 16 6 28 6 120 GATE Lee tate ac dede 3 15 a RA 3 15 Plean a PETERET APRI EUM 3 15 Semiconductor Group 11 3 Index SIEMENS 508 Be RR SA Haves Sat Cartas wate 10 4 10 5 Logic symbol o n nananana nnan 1 3 POMS AR ad 6 1 6 43 M Alternate functions 6 2 Minas adds EDEN da 3 15 Loading and interfacing ois Wein acts cp anche cinta RECON EN 3 15 Output drivers c
39. down mode also restarts the RC oscillator the on chip oscillator and the PLL The reset operation should not be activated before Vpn is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Figure 9 1 shows the procedure which must is executed when power down mode is left via the P3 2 INTO or the P5 7 INT7 wake up capability Execution of interrupt at 0 Power Down Mode P3 2 INTO 1 or P5 7 INT7 RETI Instruction Detailed Timing of Beginning of Phase 5 Invalid Address isti Invalid Address Data 7BH SRI Figure 9 1 Wake up from Power Down Mode Procedure When the power down mode wake up capability has been enabled bit EWPD in SFR PCON1 set prior to entering power down mode and bit WS in SFR PCON1 is cleared the power down mode can be exit via INTO while executing the following procedure 1 In power down mode pin P3 2 INTO must be held at high level 2 Power down mode is left when P3 2 INTO goes low for at least 10 us latch phase After this delay the internal RC oscillator the on chip oscillator and the PLL are started the state of pin Semiconductor Group 9 7 Power Saving Modes SIEMENS Mida P3 2 INTO is internally latched and P3 2 INTO can be set again to high level if required Thereafter the oscillator watchdog unit controls the wake up procedure in its start up phase 3 The oscillator
40. example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 8 or 1 16 of the oscillator frequency See section 6 4 6 for more detailed information Mode 3 9 Bit USART Variable Baud Rate 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 6 4 6 for more detailed information In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode O by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incomming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of a frames have been completed The corresponding interrupt request flags are TI or RI resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags Tl and RI can also be used for polling the serial interface if the serial interrupt is not to be used i e serial interrupt not enabled Semiconductor Group 6 98 SIEMENS On Chip Peripheral Components C508 6 4 1 Multiprocessor Communication Mode
41. overflow As long as compare mode 0 is enabled the appropriate output pin is controlled by the timer circuit only and not by the user Writing to the port will have no effect Figure 6 15 shows a functional diagram of a port latch in compare mode 0 The port latch is directly controlled by the two signals timer overflow and compare The input line from the internal bus and the write to latch line are disconnected when compare mode 0 is enabled Compare mode 0 is ideal for generating pulse width modulated output signals which in turn can be used for digital to analog conversion via a filter network or by the controlled device itself e g the inductance of a DC or AC motor Mode 0 may also be used for providing output clocks with initially defined period and duty cycle This is the mode which needs the least CPU time Once set up the output goes on oscillating without any CPU intervention Figure 6 16 and Figure 6 17 illustrate the function of compare mode 0 Semiconductor Group 6 32 SIEMENS On Chip Peripheral Components C508 Compare Register Port Circuit Read Latch Circuit Compare Reg Compare iepit Match Timer Rear m Timer Timer Circuit ue Overflow Read Pin Figure 6 15 Port Latch in Compare Mode 0 Compare Register CCx Shaded function for CRC only Compare Signal Reset Latch S Overflow P5 3 P5 2 P5 1 P5 0 T2CC3 T2CC2 T2CC1 T2CCO INT6 IN
42. part in its defined reset state The reset is performed Semiconductor Group 8 7 SIEMENS Fail Save Mechanisms C508 because clock is available from the RC oscillator This internal oscillator watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag WDTS is not reset the Watchdog Timer is however stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog unit even if meanwhile an oscillator failure occured If the frequency derived from the on chip oscillator is again higher than the reference the oscillator watchdog starts a final reset sequence which takes typically 1 ms Within that time the system clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator When this happens the PLL will be locked and its clock output is switched over as the system clock After that the oscillator watchdog releases its internal reset request If no other reset is applied at this time the part will start program execution If an external reset or a watchdog timer reset is active however the device will retain the reset state until the other reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog
43. possibly shortened by setting ADCL1 and ADCLO prescaler value to its final value immediately after reset After the reset calibration a second calibration mechanism is initiated This calibration is coupled to each A D conversion With this second calibration mechanism alternatively offset and linearity calibration values stored in the calibration RAM are always checked when an A D conversion is executed and corrected if required Semiconductor Group 6 126 SIEMENS On Chip Peripheral Components C508 Semiconductor Group 6 127 SIEMEN Interrupt System S C508 7 Interrupt System The C508 provides 19 interrupt vectors with four priority levels Nine interrupt requests are generated by the on chip peripherals timer 0 timer 1 timer 2 serial channel A D converter and the capture compare unit with 4 interrupts and ten interrupts may be triggered externally Four of the external interrupts INT3 INT4 INT5 and INT6 can also be generated by the timer 2 in capture compare mode The wake up from power down mode interrupt has a special functionality which allows the software power down mode to be terminated by a short negative pulse at pins P3 2 INTO or P5 7 INT7 The 19 interrupt sources are divided into six groups Each group can be programmed to one of the four interrupt priority levels 7 14 Structure of the Interrupt System Figure 7 1 to Figure 7 5 give a general overview of the interrupt sources and illustrate the reque
44. program e g by an internal jump instruction above the OTP memory boundary is still possible Note A 1 means that the lock bit is unprogrammed a 0 means that lock bit is programmed For a OTP verify operation at protection level 1 the C508 4E must be put into the OTP verification mode If a device is programmed with protection level 2 or 3 it is no longer possible to verify the OTP content of a customer rejected FAR OTP device When a protection level has been activated by programming of the lock bits the basic programming mode must be left for activation of the protection mechanisms This means after the activation of a protection level further OTP program verify operations are still possible if the basic programming mode is maintained The state of the lock bits can always be read if protection level 0 is selected If protection level 1 to 3 has been programmed and the programming mode has been left it is not possible to re enter the programming mode In this case the lock bits cannot be read anymore Figure 10 7 shows the waveform of a lock bit write read access For a simple drawing the PROG pulse is shortened In reality for lock bit programming a 100us PROG low pulse must be applied Semiconductor Group 10 10 SIEMENS OTP Memory Operation C508 PMSEL1 0 PALE Port 0 D1 DO PROG PRD MCT03365 The example shows the programming and reading of at protection level 1 Fig
45. s1 s2 s3 s4 s5 se s1 s2 s3 s4 s5 s6 ALE PSEN A RD without MOVX OUT OUT OUT OUT OUT Po IR Hon V8 J a s o 8 ei AR PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid b One Machine Cycle v One Machine Cycle s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ALE PSEN 8 1 A WI i MOVX po PCH DPH OUT OR PCH OUT OUT P2 OUT OUT DATA na ou A A A PCL OUT DPL or Ri PCL OUT valid valid valid MCD02575 Figure 4 1 External Program Memory Execution Semiconductor Group SIEMENS External Bus Interface C508 4 1 2 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustated in Figure 4 1 a and b Data memory in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port O before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe 4 1 3 External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active low or whenever the program counter PC content is greater than 7FFFy When the CPU is executing out of external pro
46. setting of CT1FC will generate a compare timer 1 interrupt Bit CT1FC must be cleared by software CCxR Capture compare match on up count flag x 0 2 Capture Mode CCxR is set at a low to high transition rising edge of the corresponding CCx capture input signal Compare Mode CCxR is set if the compare timer 1 value matches the compare register CCx value during the up count phase CCxF Capture compare match on down count flag x 0 2 Capture Mode CCxF is set at a high to low transition falling edge of the corresponding CCx capture input signal Compare Mode CCxF is set if the compare timer 1 value matches the compare register CCx value during the down count phase only in compare timer 1 operating mode 1 Semiconductor Group 7 17 SIEMENS Interrupt System C508 Special Function Registers CCIE Address D6y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D6H ECTP ECTC CC2FEN CC2REN CC1FEN CC1REN CCOFEN CCOREN CCIE Bit Function ECTP Enable compare timer 1 period interrupt If ECTP 0 the compare timer 1 period interrupt is disabled Compare timer 1 operating mode 0 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value Compare timer 1 operating mode 1 If ECTP 2 1 an interrupt is generated when compare timer 1 reaches the period value and changes the count direction from up to down counting E
47. software delay e g NOPs before reading the A D conversion result in the write result cycle This is the fastest method to get the result of an A D conversion Polling BSY bit The BSY bit is polled and the program waits until BSY 0 Attention a polling JB instruction which is two machine cycles long possibly may not recognize the BSY 0 condition during the write result cycle in the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C508 interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion Depending on the oscillator frequency of the C508 and the selected divider ratio of the conversion clock prescaler the total time of an A D conversion is calculated according to Figure 6 51 and Table 6 14 Figure 6 53 on the next page shows the minimum A D conversion time in relation to the oscillator frequency fosc The minimum conversion time is 6 us and can be achieved at fosc of 8 or whenever fApc 2 MHz Table 6 14 A D Conversion Time for Dedicated System Clock Rates fosc MHz Prescaler fApc MHz Sample Time Total Conversion Ratio PS ts us Time tApcc us 5 MHz 8 1 25 1 6 9 6 6 MHz 8 1 5 1 33 8 8 MHz 8 2 1 6 10MHz 16 1 25 1 6 9 6
48. switched to push pull drive capability when they are used as compare outputs of the CAPCOM unit As already mentioned port 1 3 and 5 are provided for multiple alternate functions These functions are listed in Table 6 2 Table 6 2 Alternate Functions of Port 1 3 and 5 Port Alternate Port Function Function Type P1 0 COUT3 D 10 bit compare channel output P1 1 CTRAP D CCU trap input P1 2 CCO D CAPCOM channel 0 input output P1 3 COUTO D CAPCOM channel 0 output P1 4 CC1 CAPCOM channel 1 input output P1 5 COUT1 D CAPCOM channel 1 output P1 6 CC2 D CAPCOM channel 2 input output P1 7 COUT2 D CAPCOM channel 2 output P3 0 RxD B Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD B Serial port s transmitter data output asynchronous or data clock output synchronous P3 2 INTO B External interrupt 0 input P3 3 INT1 B External interrupt 1 input P3 4 TO B Timer O external counter input P3 5 T1 B Timer 1 external counter input P3 6 WR B External data memory write strobe P3 7 RD B External data memory read strobe P5 0 T2CCO INT3 B T2 compare capture output O External interrupt 3 input P5 1 T2CC1 INT4 B T2 compare capture output 1 External interrupt 4 input P5 2 T2CC2 INT5 B T2 compare capture output 2 External interrupt 5 input P5 3 T2CC3 INT6 B T2 compare capture output 3 External interrupt 6 input P5 4 INT2 B External interrup
49. the interrupt inputs INTO to INT2 block commutation mode or by the operation of compare timer 1 or by software multi channel PWM mode In the active phase of a combined multi channel PWM mode compare timer 1 compare output signal or the compare timer 2 output signal or both can be switched selectively to the CCx or COUTx PWM output lines The combined multi channel PWM modes are controlled by the BCON block commutation control register Figure 6 33 shows the block diagram of the multi channel PWM mode logic which is integrated in the C508 CCU Emergency Interrupt CTRAP Trap Control INTO Multi Channel NTI PWM UR Control CCo INT2 BCON CC1 Port 1 CC2 Control Logic COUTO COUT1 COUT2 Capture Interrupt Channel 0 Capture Mode 16 Bit 10 Bit Period Compare Compare COUT3 Comp Match Timer 1 Timer 2 Interrupt Figure 6 33 Block Diagram of the Combined Multi Channel PWM Modes in the C508 Semiconductor Group 6 80 SIEMENS On Chip Peripheral Components C508 In block commutation mode a well defined incoming digital signal pattern of e g hall sensor signals which are applied to the INTO 2 inputs is sampled Each transition at the INTO 2 inputs results in a change of the state of the PWM outputs In block commutation mode all six PWM output signals CCx and COUTx x 0 2 are outputs According to a block commutation table Table 6 10 the outputs CCx are put either to a low or high state whil
50. up counting to down counting operating mode 1 only compare timer 1 Using operating mode 0 edge aligned PWM signals can be generated Using operating mode 1 center aligned PWM signals can be generated Compare timer 1 can be programmed for both operating modes while compare timer 2 always works in operating mode 0 with one output signal COUTS Figure 6 24 a and c shows the function of these basic operating modes Compare timer 1 has an additional 16 bit offset register which consists of the high byte stored in CT1OFH and the low byte stored in CT1OFL If the value stored in CT1OFF is 0 the compare timer operates as shown in Figure 6 24 a and c If the value stored in CT1OFF is not zero the compare timer operates as shown in Figure 6 24 b and d In operating mode 0 compare timer 1 is always reset after its value has been equal to the value stored in period register In operating mode 1 the count direction of the compare timer is changed from up to down counting when its value has reached the value stored in the period register The count direction is changed from down to up counting when the compare timer value has reached 0000 Generally the compare outputs CCx are always assigned to a match condition with the compare timer value directly where as the compare outputs COUTx are assigned to a match condition with the compare timer value plus the offset value Therefore signal waveforms with non overlapping signal transitions as shown in
51. upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed by XPAGE and Ri points outside the XRAM address range an external access is performed For the C508 the content of XPAGE must be FCy FFy in order to use the XRAM The software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to XRAM The upper address byte must be written to XPAGE or P2 both writes select the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be automatically loaded with the same address in order to deselect the XRAM 3 4 4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset After power up the contents are undefined while they remain unchanged during and after a reset as long as the power supply is not turned off If a reset occurs during a write operation to XRAM the content of a XRAM memory location depends on the cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycle The old value in XRAM is overwritten by the new value 3 4 5 Behaviour of Port 0 and Port 2 The behaviour of port 0 and port 2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The Table 3 1 lists the various operating conditions It sh
52. which is selected when bit CMSELx 3 is set the compare timer 2 output signal is switched to the COUTx or CCx outputs during the active phase of a multi channel PWM signal Bit BCMP BCON 7 defines whether only COUTx or COUTx and CCx are modulated by the compare timer 2 output signal Depending on the bits COUT3l and COUTXI of COINI the polarity of COUT3 and the switched CCx COUTx active phase signal can be identical or inverted Bit CMSELx 3 1 Compare timer 2 transitions in active phase at COUTx COINI Bit 1 COINI Bit 0 Compare imer 1 Compare ned 1 Mode 0 Mode 0 Compare Timer 2 Compare Timer 2 RRRRRRPTL Output signal TUUUWUUUL l output signal J UU UU oe ULL oe Rm cours COUTx p EQUI cour co UUU cours ee TINA cours COUTxI 0 ee COUTx active Phase Figure 6 35 Compare Timer 2 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 1 Semiconductor Group 6 86 SIEMENS On Chip Peripheral Components C508 6 3 4 3 Block Commutation PWM Mode In block commutation mode the INTO 2 inputs are sampled once each processor cycle If the input signal combination at INTO 2 changes its state the outputs CCx and COUTx are set to their new state according to Table 6 10 Table 6 10 Block Commutation Control Table Mode INTO INT2 CCO CC2 COUTO COUT2 BCM1 BCMO Inputs Outputs Outputs INTO INT1 INT2 CCO CC1 CC2 COUTO COUT1 COUT2 Rotate left 1 0
53. 00004 to FCOOL the XRAM may remain enabled Semiconductor Group 3 6 SIEMENS Memory Organization C508 Port 0 Address Data XRAM Write to XPAGE Address Port 2 1 O Data l l l l l l l l l l XPAGE l l l l l l l l l l l l MCB02113 Figure 3 3 Write Page Address to XPAGE MOV XPAGE pageaddress or MOV XPAGE PAL where PAL is internal RAM location containing the page address will write the page address only to the XPAGE register Port 2 is available for addresses or I O data Semiconductor Group 3 7 SIEMENS Memory Organization C508 Write 1 O Data to Port 2 MCB02114 Figure 3 4 Use of Port 2 as I O Port At a write to port 2 the XRAM address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register So whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch then it is absolutely necessary to rewrite XPAGE with the page address Example I O data at port 2 shall be AAy A byte shall be fetched from XRAM at address FF30y MOV RO 430H MOV P2 OAAH P2 shows AAH and XPAGE contains AAH MOV XPAGE 0FFH P2 still shows AAH but XRAM is addressed MOVX A ORO the contents of XRAM at FF30H is moved to accumulator Semiconductor Group 3 8 SIEMENS Memory Organization C508 The register XPAGE provides the
54. 08 Table 3 3 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 3 11 SIEMENS Memory Organization C508 Table 3 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator E0y 00H B B Register FOH 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H DPSEL Data Pointer Select Register 92H XXXXX000p PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 074 SYSCON System Control Register Bly XX10XX01 p VRO Version Register 0 FCH C5H VR19 Version Register 1 FDH 08H VR2 Version Register 2 FEH A D ADCONO A D Converter Control Register 0 D8y 00X00000p Converter ADCON1 A D Converter Control Register 1 DCH 01XXX000p ADDATH A D Converter Data Register High Byte D9y 00H ADDATL A D Converter Start Register Low Byte DAY O0XXXXXXp Interrupt IENO 2 Interrupt Enable Register 0 A8y 00H System IEN1 2 Interrupt Enable Register 1 B8y X0000000p IEN2 Interrupt Enable Register 2 9AH XX0000XXp IENS Interrupt Enable Register 3 BEH XXX000XXp IPO 2 Interrupt Priority Register O A9H 00H IP1 Interrupt Priority Register 1 B9y XX000000p TCON Timer Control Register 88y 00H T2CON Timer 2 Control Register C8y 0000X0X0p SCON Serial Channel Control Register 98g 00H IRCON Interrupt Request Control Register COW X0000000p EINT External Interru
55. 1 SIEMENS Power Saving Modes C508 Special Function Register PCON1 Mapped Address 88H Reset Value OXXOXXXXpg Bit No MSB LSB 7 6 5 4 3 2 1 0 884 EWPD WS PCON1 Symbol Function EWPD External wake up from power down enable bit Setting EWPD before entering power down mode enables the external wake up from power down mode capability more details see section 9 4 2 WS Wake up from power down source select WS 0 wake up via pin P3 2 INTO WS 1 wake up via pin P5 7 INT7 Pin P3 2 INTO is selected as the default wake up source after reset Reserved bits for future use Read by CPU returns undefined values Semiconductor Group 9 2 SIEMENS Power Saving Modes C508 9 2 Idle Mode In the idle mode the oscillator of the C508 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter the capture compare unit and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interfaces are not running the
56. 1 Offset Registers The CT1OFH and CT1OFL registers contain the value for the compare timer 1 CT1OFH holds the high byte of the 16 bit offset value and CT1OFL holds the low byte For the detection of a compare match event which results in changing polarity of a COUTx compare output signal the content of CT1OFH CT10OFL is always added to the actual value of the compare timer 1 The value stored in the offset registers has no effect on the signal generation at the CCx compare outputs If the compare timer 1 offset registers are written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value or count value 00004 When the compare timer 1 offset registers are read always shadow latches are accessed Special Function Register CT1OFL Address E6y Reset Value 00y Special Function Register CT1OFH Address E7g Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 E6y 7 6 5 4 3 2 1 LSB CT1OFL E74 MSB 6 5 4 3 2 1 0 CT1OFH Bit Function CT1OFL 7 0 8 bit compare timer 1 offset value low byte The 8 bit value in the CT1OFL register is the low part of the offset value for compare timer 1 shadow latch CT1OFH 7 0 8 bit compare timer 1 offset value high byte The 8 bit value in the CT1OFH register is the high part of the offset value for compare timer 1 shadow latch I
57. 1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 89H 00H Timer2 CCEN Compare Capture Enable Register C1y 00H T2CCH1 Compare Capture Register 1 High Byte C3H 00H T2CCH2 Compare Capture Register 2 High Byte C5H 00H T2CCH3 Compare Capture Register 3 High Byte C7y 00H T2CCL1 Compare Capture Register 1 Low Byte C2H 00H T2CCL2 Compare Capture Register 2 Low Byte C4y 00H T2CCL3 Compare Capture Register 3 Low Byte C6y 00H CRCH Comp Rel Capt Register High Byte CBH 00H CRCL Comp Rel Capt Register Low Byte CAH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H T2CON Timer 2 Control Register C8y 0000X0X0p 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 3 13 SIEMENS Memory Organization C508 Table 3 2 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Compare CTTCON Compare timer 1 control register Ely 00010000 Capture CCPL Compare timer 1 period register low byte DEH 00H Unit CCPH Compare timer 1 period register high byte DFy 00H CT1OFL Compare timer 1 offset register low byte E6y 00H CT1OFH
58. 1 s written to them are pulled high by the internal pull up transistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current jj in the DC characteristics because of the internal pullup transistors The output latch corresponding secondary function must be programmed to a one 1 for that function to operate except for TxD and WR The secondary functions are assigned to the pins of port 3 as follows 33 41 P3 0 RxD Receiver data input asynch or data input output synch of serial interface 34 42 P3 1 TxD Transmitter data output asynch or clock output synch of serial interface 35 43 P3 2 INTO External interrupt 0 input timer 0 gate control input 36 44 P3 3 INT1 External interrupt 1 input timer 1 gate control input 37 45 P3 4 TO Timer O counter input 38 46 P3 5 T1 Timer 1 counter input 39 47 P3 6 WR WR control output latches the data byte from port 0 into the external data memory 40 48 P3 7 RD RD control output enables the external data memory Input O Output Semiconductor Group 1 7 IE Introduction SIEMENS EOR Symbol Pin Numbers 1 0 Function P MQFP 64 P SDIP 64 P2 0 P2 7 47 54 55 62 O Port2 is an 8 bit quasi bidirectional I O port with internal pullup transistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as i
59. 16 bit timer counter 6 20 Multiprocessor communication 6 99 Mode 2 8 bit rel timer counter 6 21 Operating mode 0 6 106 6 108 Mode 3 two 8 bit timer counter 6 22 Operating mode 1 6 109 6 111 Registers 6 16 6 18 Operating mode 2 and 3 6 112 6 114 Timer counter 2 6 23 6 42 Registers 5 cba ut Hise Ri waar 6 99 Block diagram 6 24 E ee eee eee 3 15 Capture function 6 40 6 42 SIM eso O A vat der 3 15 Compare function 6 32 6 37 SMBL uoo tea on ace dido ns led 3 15 Compare mode 0 6 32 6 35 A ohne ddp date dots 3 15 Compare mode 1 6 36 6 37 Ss E 2 4 3 12 3 15 Compare mode interrupts 6 38 Special Function Registers 3 11 General operation 6 30 Access with RMAP 3 11 Port TURCOS eto Ee nates 6 23 Table address ordered 3 15 3 18 Registers 6 25 6 29 Table functional order 3 12 3 14 Reload configuration 6 31 SRELE cua sadi Le 02 1270629 Y 3 13 3 16 MED e cytes ane 3 13 3 15 A besser dees 3 13 3 15 TET coe eee eee eee een ee 3 13 3 15 O O 3 17 IRE 3 13 3 16 E oe ee 3 18 TMOD 60 0 e eee eee ee 3 13 3 15 UD RR ERE RE 3 16 8 3 TRO cs recientes C ehe RP mue en 3 15 SYSCON 3 3 3 11 3 12 3 16 4 4 A IO 3 15 TACON us anita 3 14 3 18 6 57 TRENO ou cana 3 18 A A o NO EE 3 18 T2CCH1 A dak Sot 3 13 3 16 TREN2 45 votes aa 3 18 T2
60. 2 Pin Symbol Function P5 0 T2CC0 INT3 Compare output capture input for CRC register P5 1 T2CC1 INT4 Compare output capture input for CC register 1 P5 2 T2CC2 INT5 Compare output capture input for CC register 2 P5 3 T2CC3 INT6 Compare output capture input for CC register 3 Semiconductor Group 6 23 SIEMENS On Chip Peripheral Components C508 Interrupt Timer 2 TF2 Hequest TL2 TH2 Compare P5 0 J lt gt T26C0 INT3 T2CCL3 T2CCL2 T2CCL1 T2CCH3 T2CCH2 T2CCH1 CRCL CRCH 16 Bit 16 Bit 16 Bit 16 Bit Comparator Comparator Comparator Comparator Control P5 2 v Ele r1 E gt pgo Capture INTS 3 pk Figure 6 13 Timer 2 Block Diagram Semiconductor Group 6 24 SIEMENS On Chip Peripheral Components C508 6 2 2 1 Timer 2 Registers This chapter describes all timer 2 related special function registers of timer 2 The interrupt related SFRs are also included in this section Table 6 5 summarizes all timer 2 SFRs Table 6 5 Special Function Registers of the Timer 2 Unit Symbol Description Address T2CON Timer 2 control register C8H TL2 Timer 2 low byte CCy TH2 Timer 2 high byte CDy CCEN Compare capture enable register C1H CRCL Compare reload capture register low byte CAy CRCH Compare reload capture register high byte CBy T2CCL1 Compare capture register 1 low byte C2H T2CCH1 Compare capture register 1
61. 2 Figure 5 4 CPU Timing after Reset Semiconductor Group 5 6 SIEMENS Reset System Clock C508 5 4 Clock Generation The top level view of the system clock generation of the C508 is shown in Figure 5 5 Fac or fosc Control system clock Logic Figure 5 5 Block Diagram of the Clock Generation The clock generation block consists of the RC oscillator the on chip oscillator and the PLL At power on reset the RC oscillator takes a shorter time to start compared to the on chip oscillator typ 2 us compared to 10 ms While the on chip oscillator is still unstable the PLL remains unlocked Thus the RC clock is provided as the system clock When the on chip oscillator has stabilised the PLL locks within 1ms providing a clock frequency twice that of the on chip oscillator s frequency The system clock source is now switched to the PLL clock External reset from the pin should only be released after this stage 5 5 PLL Operation Within 1ms after stable oscillations of the input clock within the specified frequency range the PLL will be synchronous with this clock at a frequency which is twice the input frequency In other words the PLL locks to its input clock Since the PLL is constantly adapting to the external clock so as to remain locked the CPU clock generated has a slight variation known as jitter This jitter is irrelevant for longer time periods For short periods 1 to 4 CPU clock cycles it remai
62. 2 SIEMENS On Chip Peripheral Components C508 6 3 Capture Compare Unit CCU The Capture Compare Unit CCU of the C508 has been designed for applications which have a demand for digital signal generation and or event capturing e g pulse width modulation pulse width measuring It consists of a 16 bit 3 channel capture compare unit CAPCOM and a 10 bit 1 channel compare unit COMP In compare mode the CAPCOM unit provides two output signals per channel which can have inverted signal polarity and non overlapping pulse transitions The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals For motor control applications both units CAPCOM and COMP may generate versatile multichannel PWM signals For brushless DC motors dedicated control modes are supported which are either controlled by software or by hardware hall sensors 16 Bit Capture Compare Unit CAPCOM f Mode Trap Initialization Period Register Select Register Registers CTRAP CCPH CCPL CMSELO CMSEL1 COINI COTRAP TREN Offset Register CC Channel 0 cco CT1OFH CT1OFL CCHO CCLO COUTO CC Channel 1 CC1 ompare Timer 1 SPEI SET COUTI 16 Bit CC Channel 2 CC2 CCH2 CCL2 COUT2 Cntrl Register 3 CT1CON Prescalar 10 Bit Compare Unit COMP Period Register CP2H CP2L Compare Timer 2 Compare Reg COUT3 10 Bit CMP2H CMP2L Block Commutation Cntrl Register CT2CON Gontro
63. 2 the instruction MOV ADDATL 0 starts the A D conversion machine cycle X 1 and X The total A D conversion sample conversion and calibration phase is finished with the end of the 8th 16th 32nd or 64th machine cycle after the A D conversion start In the next machine cycle the conversion result is written into the ADDAT registers and can be read in the same cycle by an instruction e g MOV A ADDATL If continuous conversion is selected bit ADM set the next conversion is started with the beginning of the machine cycle which follows the write result cycle Semiconductor Group 6 123 On Chip Peripheral Components SIEMENS COS The BSY bit is set at the beginning of the first A D conversion machine cycle and reset at the beginning of the write result cycle If continuous conversion is selected BSY is again set with the beginning of the machine cycle which follows the write result cycle The interrupt flag IADC is set at the end of the A D conversion If the A D converter interrupt is enabled and the A D converter interrupt is prioritized to be serviced immediately the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle IADC must be reset by software Depending on the application typically there are three methods to handle the A D conversion in the C508 Software delay The machine cycles of the A D conversion are counted and the program executes a
64. 3 Port 0 Circuitry Semiconductor Group 6 5 SIEMENS On Chip Peripheral Components C508 6 1 2 2 Port 1 Port 3 and Port 5 Circuitry The pins of ports 1 3 and 5 are multifunctional They are port pins and also serve to implement special features as listed in Table 6 2 Figure 6 4 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at O After reset all port latches contain ones 1 Alternate Output Function Internal Pull Up Arrangement Read Latch Int Bus Write to Latch Alternate Input Function Read Pin Figure 6 4 Ports 1 3 and 5 Semiconductor Group 6 6 SIEMENS On Chip Peripheral Components C508 6 1 2 3 Port 2 Circuitry As shown in Figure 6 3 and below in Figure 6 5 the output drivers of ports 0 and 2 can be switched to an internal address or address data bus for use in external memory accesses In this application these two ports cannot be used as general purpose l O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the progra
65. 3 12 3 17 Trap enable register 6 72 ADM ES 3 17 Write on the fly 6 58 ALE signal ao 4 4 Trap function o o 6 55 B Basic operating modes 6 44 Bees 2 4 3 12 3 18 Block diag cie desa 6 43 Basic CPU timing 2 5 General operation 6 44 BGEM Leia S 3 17 Multi channel PWM modes 6 80 6 97 BEN 2d rire b 3 17 4 5 6 phase PWM mode 6 91 6 97 BGOEREU Cesiones er aio MEE 3 17 4 phase PWM timing 6 91 BEMO ser d aiia dee cei 3 17 5 phase PWM timing 6 92 BOMI saint eee 3 17 6 phase PWM timing 6 93 BCOMP puntos 3 17 Block commutation mode 6 87 6 89 BOON 45 dedi criestichtie dd 3 14 3 17 Block diagram 6 80 BOTSEL mission ds 3 18 Control register BCON 6 82 BD ne eere es 3 17 Output waveforms 6 85 6 86 Block diagram 15 editt cete as 2 2 PWMstatetables 6 94 6 95 BOY thsi a tee Sd nodi ura 3 17 Signal generation 6 84 C State switching by software 6 96 Vi A aae I 3 15 Trap function iine 6 97 CAN controller COOP Lud qnae SORS RO efr tein E 3 17 Access control 2 cos a eS ae Sak 3 3 COOPEN S tis iso EE ERE ot 3 17 Capture compare unit CCU 6 43 6 97 ser ME di ES 3 17 1 channel COMP unit 6 74 6 79 ou A TT 3 17 Block diagram 6 74 COOREN ioi rg ERR REIS 3 17 Pulse generation 6 74 uel EP 3 18 Registers 22 e aad ee
66. 3 14 3 17 6 57 Program status word 2 3 CLK m E ar ei tek 3 17 Stack pointer ve dnce e sil 2 4 CEKO A A meer 3 17 3 18 o A e peor meris 2 6 GLK niae Cx ds AE 3 17 3 18 GACH niza apra hese head 3 13 3 16 GEKZ dd 3 17 3 18 GHOL tas 3 13 3 16 GOMP2 it cos tete dettes 3 14 3 17 6 75 CTIGON i eheu 3 14 3 17 6 57 CMP2L es Duct di es 3 14 3 17 6 75 CU LEG s odas ere IDA D a 3 17 CMSELO recta 3 14 3 17 6 57 Al A O M crt 3 17 GMSELOO vii obs dnte sou I dne ee 3 17 GTIOPH cit tern cease ndr 3 14 3 18 6 57 OMOSELDI uei dM th rp ae see 3 17 GUTOR 22 2 cheeses 3 14 3 18 6 57 GMSELU i rs xS da 3 17 CT TEL Bui idum Eod SURE ER SASS 3 17 GMSELOS 2s stake ie 3 17 CTTRES arar pot e oed 3 17 CMSELA et Ts cesta 3 14 3 17 6 57 CT2CON stan Ske age 3 14 3 18 6 75 OGMSEL TU su cis Diete i alata 3 17 OTAR added 3 18 GMSEIL TI not ula ens dudas dd ete 3 17 CTAR O UN 3 18 GMOSELIT2 ota tres dde 3 17 CT2RES is ds e 3 18 OMOSELIS 261v bie ha 3 17 CTM ais ea 3 17 GMSELZO cis ag Siesta ease 3 17 OY ne ie htxa mea Ad ENEAEEE 2 4 3 16 OMSEL2T 1000 x eS 3 17 D CMSEL22 sssssseeeesees 3 17 Datapointers co vos Lord lieto 4 6 4 9 OMSEL23 es sida ERE EROS 3 17 Application examples 4 7 4 9 COCAHO 6 eee eee eee 3 16 DPSEL register 22525 pt 4 6 COCAHT 1 cece eee eee 3 16 Functionality sa nesses Bes at e 4 6 COGAN 0 vti aro qot 1a RO of 3 16 PE averte da le A ad ose 3 12 3 15 GOCAHS 6 eee eee e
67. 508 Depending on the corresponding initial compare output level bit in COINI either a low or high level for the non modulated state at the COUTx pins can be selected Burst mode can be enabled in both operating modes of the compare timer 1 The burst mode as shown in Figure 6 30 is only valid if the block commutation mode of the CCU is disabled bit BCEN of SFR BCON cleared The modulation of the compare output signals at COUTx is switched on COUT3 signal is switched to COUTx when the compare timer 1 content plus the value stored in the compare timer 1 offset register is equal or greater than the value stored in the compare register of CAPCOM channel x 6 3 2 6 CAPCOM Unit in Capture Mode The three channels of the CAPCOM unit can be individually programmed to operate in capture mode In capture mode each CAPCOM channel offers one capture input at pin CCx Compare timer 1 runs either in operating mode 0 or 1 A rising or and falling edge at CCx will copy the actual value of the compare timer 1 into the compare capture registers Interrupts can be generated selectively at each transition of the capture input signal The capture mode is selected by writing the mode select registers CMSEL1 and CMSELO with the appropriate values The bit combinations in CMSELO and CMSEL1 also define the signal transition type falling rising edge which generates a capture event If a CAPCOM channel is enabled for capture mode its CCx input is sampled with 1 4TC
68. 6H SEL Reload Value WDTREL Bit Function WDTPSEL Watchdog timer prescaler select bit When set the watchdog timer is clocked through an additional divide by 16 prescaler WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT Table 8 1 Watchdog Timer Time Out Periods WDTREL Time Out Period Comments Jose 5 MHz fosc 8 MHz fosc 10 MHz 00H 39 322 ms 24 576 ms 19 668 ms This is the default value 80y 629 146 ms 393 2 ms 314 573 ms Maximum time period 7Fy 307 2 us 192 us 153 6 us Minimum time period Semiconductor Group 8 2 SIEMENS Fail Save Mechanisms C508 8 1 2 Watchdog Timer Control Status Flags The watchdog timer is controlled by two control flags located in SFR IENO and IEN1 and one status flag located in SFR IPO Special Function Register IENO Address A8jy Reset Value 00y Special Function Register IEN1 Address B8y Reset Value X0000000y Special Function Register IPO Address A9 4 Reset Value 00y MSB LSB AFy AEQ ADy ACy ABy AAW A94 A8y A8H EA WDT ET2 ES ETI EX1 ETO EXO IENO BF BE BDy BC BBy BA B94 B8y B8y SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O IPO
69. 7 6 1 Parallel I O The C508 has one 8 bit analog or digital input port and five 8 bit I O ports Port 4 is an uni directional input port Port O is an open drain bidirectional I O port while ports 1 to 3 and 5 are quasi bidirectional I O ports with internal pullup transistors That means when configured as inputs these ports will be pulled high and will source current when externally pulled low Port O will float when configured as input The output drivers of port 0 and 2 and the input buffers of port O are also used for accessing external memory In this application port O outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an open drain port but uses a strong internal pullup FET Port 4 provides the analog input channels to the A D converter 6 1 1 Port Structures The C508 generally allows digital I O on 32 lines grouped into 4 bidirectional 8 bit ports and analog digital input on one unidirectional 8 bit port Except for port 4 which is the unidirectional input port each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO P5 except P4 are performed via their corresponding special function registers When port 4 is used as analo
70. CCH2 3 13 3 16 TEENS said oe Minato ae Sues ores 3 18 TOCCH3 2 eee 3 13 TRENG heise i Y kde 3 18 TOGOD m Su ad om dob Ave 3 13 3 16 TRENS 6 ua ao A 3 18 T2CCL2 A 3 13 3 16 TRE ies 3 18 T2CCL3 A AE 3 13 3 16 TRPEN asas 3 18 T2CM LLL LLL LLL 3 16 TAD tds 3 16 T2CON a veces 3 12 3 13 3 16 7 13 C 3 16 Unprotected ROM verify timing 4 10 A De thee che oat Ree eles 3 16 MARA eh tere Sa as 3 16 Version registers 4 14 ie Ss cheba ERES 3 15 6 99 VRO uso Selly EPPweS tere 3 12 3 18 TON ascuas 3 12 3 13 3 15 7 12 Vlad ase 3 12 3 18 VEO ia haad pas 3 15 7 12 VB2 ia Ud ENN ERE ANE 3 12 3 18 TED tee 2 ole eee fo Bee a 3 15 7 12 quie gh duse sa tes esf esos ten S hates 3 16 7 14 Index SIEMENS C EOS W Watchdog timer 8 1 8 5 Block diagram a exi ve scada 8 1 Control status flags 8 3 Input clock selection 8 2 Refreshing of the WDT 8 4 Reset operation 8 5 Starting of the WDT 8 4 Time out periods 8 2 WIDE Segarra 3 15 8 3 WOTRSEL dba RR UR 3 15 WDTREL tics Sele soe 3 14 3 15 A eee Bare oa ake tee 3 15 MURS sig hint eo hint e Pen alt 3 16 WS sure oum ema E PEST eO ed 3 15 X AMARO cede babies 3 16 AMAR T ela o c eet es ad E 3 16 XPAGE 1 2 Tene pe 3 12 3 15 XRAM operation 3 3 Access control ius oxi ics 3 3 Accessing throu
71. CMSEL1 CMSELO Block commutation XXXX YO11p Y011 YO11p 6 phase multi channel PWM 5 phase multi channel PWM Y010 YO11p 4 phase multi channel PWM Y010 Y001p Note The abbreviation X means don t care The abrevation Y bit CMSELx 3 represents the burst mode bit If YO the signal generation at the COUTx pins is controlled by compare timer 1 If Y 1 the signal generation at the COUTx pins is also controlled by compare timer 1 but modulated by compare timer 2 Output signals during the active phase An active phase of a compare output signal in multi channel PWM mode can be controlled either by the CAPCOM unit compare timer 1 and or modulated by compare timer 2 The selection is done by bit CMSELx 3 see note below Table 6 9 Figure 6 34 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 1 Compare timer 1 may operate either in mode 0 or mode 1 In multu phase mode the block commutation logic switches from one state to the next state when compare timer 1 reaches the value 0000y As an active phase lasts always two states the duration of an active phase is determined by compare timer 1 reaching 0000y twice As shown in Figure 6 34a a compare output signal CCx or COUTx of a CAPCOM channel is either at low or high level during the whole active phase when the value stored in the compare timer 1 offset registers CT1OFH CT1OFL and the value stored in its compare regi
72. CTC Enable compare timer 1 count direction change interrupt status If ECTC 0 the compare timer 1 count change interrupt is disabled Compare timer 1 operating mode 0 Bit has no effect on the interrupt generation Compare timer 1 operating mode 1 If ECTC 1 an interrupt is generated when compare timer 1 reaches count value 0000 and changes its count direction from down to up counting CCxREN x 0 2 Capture compare rising edge interrupt enable Capture Mode If CCxREN is set an interrupt is generated at a low to high transition rising edge of the corresponding CCx input signal Compare Mode If CCXREN is set an interrupt is generated if the compare timer 1 value matches the compare register CCx value during the up counting phase of the compare timer 1 This function is available in both compare timer 1 operating modes CCxFEN x 0 2 Capture compare falling edge interrupt enable Capture Mode If CCxFEN is set an interrupt is generated at a high to low transition falling edge of the corresponding CCx input signal Compare Mode If CCxFEN is set an interrupt is generated only in compare timer mode 1 if the compare timer 1 value matches the compare register CCx value during the down counting phase of the compare timer 1 This function is available only in compare timer 1 operating mode 1 Semiconductor Group 7 18 SIEMENS Interrupt System C508 Special Function Register CT2CON Ad
73. Capture on rising edge at pin P5 2 T2CC2 INT5 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 COCAH 1 Compare capture mode for CC register 1 dcc COCAH1 COCAL1 Function 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P5 1 T2CC1 INT4 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 COCAHO Compare capture mode for CRC register MISSA COCAHO COCALO Function 0 0 Compare capture disabled 0 1 Capture on falling rising edge at pin P5 0 T2CCO INT3 1 0 Compare enabled 1 1 Capture on write operation into register CRCL Semiconductor Group 6 29 SIEMENS On Chip Peripheral Components C508 6 2 2 2 Timer 2 Operation The timer 2 which is a 16 bit wide register operates as a timer with its count rate derived from the oscillator frequency A prescaler offers the possibility of selecting a count rate of 1 3 or 1 6 of the oscillator frequency Thus the 16 bit timer register consisting of TH2 and TL2 is either incremented in every machine cycle or in every second machine cycle The prescaler is selected by bit T2PS in special function register T2CON If T2PS is cleared the input frequency is 1 3 of the oscillator frequency If T2PS is set the 2 1 prescaler gates 1 6 of the oscillator frequency to the timer The timer overflow flag TF2 in SFR IRCON is set when there is a roll over of the count from all 1 s to all O s This flag TF2 can generate an interrupt and it m
74. Compare timer 1 offset register high byte E7y 00H CMSELO Capture compare mode select register O E3y 00H CMSEL1 Capture compare mode select register 1 E4y 00H COINI Compare output initialization register E2H FFH CCLO Capture compare register 0 low byte F2u 00H CCHO Capture compare register 0 high byte F3H 00H CCL1 Capture compare register 1 low byte F4y 00H CCH1 Capture compare register 1 high byte F5H 00H CCL2 Capture compare register 2 low byte F6H 00H CCH2 Capture compare register 2 high byte F7H 00H TRCON Trap enable control register FFH 00H COTRAP Compare output in trap state register F9H 0X000000p CCIR Capture compare interrupt request flag reg E5y 00H CCIE Capture compare interrupt enable register D6y 00H CT2CON Compare timer 2 control register Fiy 00010000p CP2L Compare timer 2 period register low byte D24 00y CP2H Compare timer 2 period register high byte D3y XXXXXX00p CMP2L Compare timer 2 compare register low byte D4y 00H CMP2H Compare timer 2 compare register high byte D5y XXXXXX00p BCON Block commutation control register D7y 00H Watchdog WDTREL Watchdog Timer Reload Register 86H 00H IENO 2 Interrupt Enable Register 0 A8y 00H IEN1 2 Interrupt Enable Register 1 B84 00H IPO 2 Interrupt Priority Register O A9H 00H Power PCON Power Control Register 87H 00H Save PCON1 Power Control Register 1 88y OXXOXXXXp 9 Modes 1 Bit addressable special function
75. Counter Semiconductor Group 6 20 SIEMENS On Chip Peripheral Components C508 6 2 1 4 Mode2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in Figure 6 11 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged TFO Interrupt Figure 6 11 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 21 SIEMENS On Chip Peripheral Components C508 6 2 1 5 Mode 3 Mode 3 has different effects on timer O and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer O in mode 3 establishes TLO and THO as two seperate counters The logic for mode 3 on timer 0 is shown in Figure 6 12 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 and when TR1 is set timer 1 can be turned on by switching it to any mode other than 3 and off by switching it into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself Timer Clock Interrupt O
76. EX The shaded bits are not used for fail save control Bit Function WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer SWDT Watchdog timer start flag Set to activate the Watchdog Timer When directly set after setting WDT a watchdog timer refresh is performed WDTS Watchdog timer status flag Set by hardware when a watchdog Timer reset occured Can be cleared and set by software Immediately after start the Watchdog Timer is initialized to the reload value programmed in WDTREL 0 WDTREL 6 After an external HW reset an oscillator watchdog power on reset or a watchdog timer reset register WDTREL is cleared to 00 The lower seven bits of WDTREL can be loaded by software at any time Semiconductor Group 8 3 SIEMENS Fail Save Mechanisms C508 8 1 3 Starting the Watchdog Timer The Watchdog Timer can be started by software bit SWDT in SFR IEN1 but it cannot be stopped during active mode of the device If the software fails to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTS in IPO is set A refresh of the watchdog timer is done by setting bits WDT SFR IENO and SWDT consecutively This double instruction sequence has been implemented to increase system secur
77. Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each C500 production chip has built in logic for the support of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON ET RSYSCON Enhanced Hooks MCU Interface Circuit Optional m 1 0 Ports Port3 Port 1 RPort2 RPort TEA TALE TPSEN Target System Interface MCS02647 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to contr
78. Hz external crystal frequency the prescaler ratio 8 is selected Between 8 MHz and 10 MHz the prescaler ratio of at least 16 must be selected A prescaler ratio of 32 can used for any of the above frequency ranges A prescalar ratio of 4 should be used only when the C508 is operating in slowdown mode ADCLO Clock Prescaler Conversion Clock fADC A D Converter fin 2fose 4TCL fADC max 2 MHz Condition Oscillator Clock fin Prescaler fapc ADCL1 ADCLO Rate fosc MHz Ratio MHz 5 MHz 10 8 1 25 0 1 8 MHz 16 8 2 1 10 MHz 20 16 1 25 1 0 Figure 6 50 A D Converter Clock Selection The duration of an A D conversion is a multiple of the period of the fiy clock signal The calculation of the A D conversion time is shown in the next section Semiconductor Group 6 121 Note Please refer to C508 data sheet for the definition of TCL SIEMENS On Chip Peripheral Components C508 6 5 4 A D Conversion Timing An A D conversion is started by writing into the SFR ADDATL with dummy data A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the BSY flag in SFR ADCONO will be set The A D conversion procedure is divided into three parts Sample phase tg used for sampling the analog input voltage Conversion phase tco used for the real A D conversion inc
79. ISTSESTS d MOVX 1 Byte 2 Cycle ADDR DATA XTAL2 ALE Read Read Next Opcode Opcode Discard Reden Y Opcode Again ess sf Read Read 2nd Opcode Byt ue Read Next Bm Opcode ess sf Read Read Next Opcode Again Opcode Read Next Opcode Discard assess e s sTs e c 1 Byte 2 Cycle Instruction e g INC ia Read Next Opcode Again LE Fetch No No ALE V Fetch 5 Read Read NES Opcode Opcode MOVX Discard Access of External Memory Figure 2 2 Fetch Execute Sequence Semiconductor Group 2 6 SIEMENS Fundamental Structure C508 Semiconductor Group 2 7 SIEMENS Memory Organization C508 3 Memory Organization The C508 CPU manipulates operands in the following five address spaces upto 64 Kbytes of program memory 32K ROM for C508 4R 32K OTP for C508 4E up to 64 Kbytes of external data memory 256 bytes of internal data memory 1024 bytes of internal XRAM data memory a 128 byte special function register area Figure 3 1 illustrates the memory address spaces of the C508 Alternatively a FFFFH FFFFy Internal XRAM 1KByte Ext yte FC00H FBFFy indirect direct addr addr Internal RAM 7FH Internal RAM 0000H 00H Code Space Data Space Internal Data Space Figure 3 1 C508 Memory Map Semiconductor Group 3 1 SIEMENS Memory Organ
80. L i e 2fosc twice external oscillator clock rate Consecutive capture events generated through signal transitions at a CCx capture input overwrite the corresponding 16 bit compare capture register contents This must be regarded when successive signal transitions are processed Semiconductor Group 6 54 SIEMENS On Chip Peripheral Components C508 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode When a channel of the CAPCOM unit operates in compare mode its output lines can be decoupled in trap mode from the CAPCOM pulse generation The trap mode is controlled by the external signal CTRAP The CTRAP signal is sampled at each phase of the oscillator clock cycle If a low is detected the trap flag TRF of register TRCON is set and CCx or COUTx compare outputs are switched immediately to the logic state as defined by the bits in COTRAP if that particular channel has been enabled for trap function The compare outputs of the channels which are not enabled for trap function will have their last output levels maintained For safety reasons it is recommended that trap function is enabled If CT1RES 0 compare timer 1 continues its operation but no compare output signal will be generated If CT1RES 1 compare timer 1 is reset when CTRAP becomes active When CTRAP is sampled inactive high again the compare channel outputs are synchronously switched to the compare channel output signal generation when compare timer 1 has reached the
81. Lower 8 bits of the baud rate timer reload value Reserved bits for future use Read by CPU returns undefined values After reset SRELH and SRELL have a reload value of 3D9y With this reload value the baud rate generator has an overflow rate of input clock 39 With 10MHz oscillator frequency a reload value of 37Ey is required to achieve the commonly used baud rates of 4800 baud SMOD 0 and 9600 baud SMOD 1 at a deviation of 0 16 With the baud rate generator as clock source for the serial port in mode 1 and 3 the baud rate can be determined as follows 25M0D x oscillator frequency Mode 1 3 baud rate 16 x baud rate generator overflow rate Baud rate generator overflow rate 21 SREL with SREL SRELH 1 0 SRELL 7 0 Semiconductor Group 6 104 SIEMENS On Chip Peripheral Components C508 6 4 3 3 2 Using Timer 1 to Generate Baud Rates In modes 1 and 3 of the serial interface timer 1 can also be used for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows 2SMOD Mode 1 3 baud rate x timer 1 overflow rate The timer 1 interrupt is usually disabled in this application Timer 1 itself can be configured for either timer or counter operation and in any of its operating modes In most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010p In this case the
82. MOV LOW DES PTR 40A0H Initialize shadow variables with destination pointer MOV HIGH DES PTR 2FH Table Look up Routine under Real Time Conditions Number of cycles PUSH DPL Save old datapointer 2 PUSH DPH 2 MOV DPL LOW SRC PTR Load Source Pointer 2 MOV DPH HIGH SRC PTR 2 INC DPTR Increment and check for end of table execution time CJUNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV LOW SRC PTR DPL Save source pointer and 2 MOV HIGH SRC_PTR DPH load destination pointer 2 MOV DPL LOW DES PTR 2 MOV DPH HIGH DES_ PTR 2 INC DPTR Increment destination pointer ex time not relevant MOVX DPTR A Transfer byte to destination address 2 MOV LOW DES_PTR DPL Save destination pointer 2 MOV HIGH DES PTR DPH 2 POP DPH Restore old datapointer 2 POP DPL 2 Total execution time machine cycles 28 Semiconductor Group 4 8 SIEMENS External Bus Interface C508 Example 2 Using Two Datapointers Code for a C508 Initialization Routine MOV DPSEL 06H Initialize DPTR6 with source pointer MOV DPTR 1FFFH MOV DPSEL 07H Initialize DPTR7 with destination pointer MOV DPTR 2FA0OH Table Look up Routine under Real Time Conditions Number of cycles PUSH DPSEL Save old source pointer 2 MOV DPSEL 06H Load source pointer 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this considera
83. MOVX Ri A Write A special page register is implemented in the C508 to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Special Function Register XPAGE Address 915 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 91H 7 6 5 4 3 2 1 0 XPAGE Bit Function XPAGE 7 0 XRAM high address XPAGE 7 0 is the address part A15 A8 when 8 bit MOVX instructions are used to access internal XRAM Figure 3 2 to Figure 3 4 show the dependencies of XPAGE and Port 2 addressing in order to explain the differences in accessing XRAM external RAM or to show what to do when Port 2 is used as an l O port Semiconductor Group 3 5 SIEMENS Memory Organization C508 Port 0 lt gt Address Data XRAM XPAGE Write to Port 2 Page Address MCB02112 Figure 3 2 Write Page Address to Port 2 Moving the page address to Port 2 by either immediate addressing instruction MOV P2 pageaddress or direct addressing instruction MOV P2 PAL where PAL is internal RAM location containing the page address will write the page address to port 2 and also to XPAGE Register When external RAM is to be accessed in the XRAM address range the XRAM has to be disabled When the additional external RAM is to be addressed in an address range
84. MSELLO Z 14 H PALE 3FD 3FE 3FF 400 400 3FD por Zoe ro re rr o o o fol ro 7 Port 0 Data 1 Data 2 Data 3 Y Data 4 Y Data 4 Y Data 1 Y LL LL LL A w 0 NN MCT03364 Figure 10 6 Typical OTP Memory Programming Verify Access Waveform Semiconductor Group 10 9 SIEMENS OTP Memory Operation C508 10 6 Lock Bits Programming Read The C508 4E has two programmable lock bits which when programmed according to table 10 3 provide four levels of protection for the on chip OTP code memory Table 10 3 Lock Bit Protection Types Lock Bits at D1 DO Protection Protection Type D1 DO Level 1 1 Level 0 The OTP lock feature is disabled During normal operation of the C508 4E the state of the EA pin is not latched on reset 1 0 Level 1 During normal operation of the C508 4E MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset An OTP memory read operation is only possible according to OTP verification mode Further programming of the OTP memory is disabled reprogramming security 0 1 Level 2 Same as level 1 but also OTP memory read operation using OTP verification mode is disabled 0 0 Level 3 Same as level 2 but additionally external code execution by setting EA low during normal operation of the C508 4E is no more possible External code execution which is initiated by an internal
85. NET dta Ss are irt n Dit re etos 3 17 OWDS sei p C ebd d 315 R P A TESTE 3 15 6 99 Pole nnns 3 16 A s SONUS Si e Ie SRM DU 3 16 PO sss 3 12 3 15 A d sedi dent a et 3 15 Ple 3 12 8 15 SITAE EU 5 1 B2 usta tu duit LE 3 1 2 3 15 Fast power on reset 2 521 AX 5 3 P3 essen e n nnn 3 12 8 16 Hardware reset timing 5 5 PA sisse nnn 3 12 3 17 Reset circuitries 5 2 POS o A A 3 12 ANA en gerne 3 15 6 99 7 16 Parallel I O 6 1 6 43 RMAP CM 3 16 PCON 3 13 3 14 3 15 6 101 ROM protection 4 10 PGONT Nata teh debe Sat She 3 15 Protected ROM mode 4 11 PCONTA cardio Saee 3 14 Protected ROM verification example 4 13 PDE ovv o o dagas 3 15 Unprotected ROM mode 4 10 CO 3 15 ici M 3 16 PDTEN 0 eee eee eee 3 18 Oty Eois setius ls a SEL pei 3 16 Pin Configuration os cue etse ene 1 4 S D IN A 3 16 Pin Definitions and functions OTP Mode Semiconductor Group 11 4 Semiconductor Group SIEMENS C508 D 3 13 3 15 SBUF aaa 3 13 3 15 6 99 TEA pec A 3 13 3 15 SCON 3 12 3 13 3 15 6 99 7 16 n cp R aE 3 13 3 16 CARENT UMOR C OSRAM Bim Mess 3 15 6 99 7 16 Serial interface USART 6 98 6 114 TIME COUNMIE at 6 15 Baudrate generation 6 101 Timer counter 0 and 1 6 15 6 22 with internal baud rate generator 6 103 Mode 0 13 bit timer counter 6 19 with MET aa esi repo cos 6 105 Mode 1
86. P 64 P SDIP 64 Vss 24 43 55 32 51 63 Ground 0V Vbp 23 44 56 31 52 64 Power Supply 5V Vopa 3 11 Analog Power Supply 5V Vssa 4 12 Analog Ground 0V Vaner 13 21 Reference voltage for the A D converter VAGND 14 22 Reference ground for the A D converter Input O Output Semiconductor Group Introduction SIEMENS ap Semiconductor Group 1 12 SIEMENS Fundamental Structure C508 2 Fundamental Structure The C508 is fully compatible to the architecture of the standard 8051 C501 microcontroller family While maintaining all architectural and operational characteristics of the C501 the C508 incorporates a CPU with 8 datapointers a 10 bit A D converter a 16 bit capture compare unit a timer 2 with capture compare functions an improved interrupt structure with 4 priority levels built in PLL with a fixed factor of 2 an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C508 Semiconductor Group 2 1 SIEMENS Fundamental Structure C508 V ss Oscillator Watchdog XRAM RAM ROM OTP XTAL1 OSC amp Timing 1024 x8 256x8 32kx8 XTAL2 PLL factor of 2 RESET CPU 8 datapointers ALE EA Programmable Watchdog Timer Port 0 8 bit digital I O Porti Timer 2 with Port 2 4 PWM Channels 8 bit digital I O Port 3 8 bit digital I O Port 4 Capture Compare 8 bit analog Uni
87. P sey eT Oo oy oy sty oy oo cIoi oc 5 X X O O O O O O 2 A O O JO 0O 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 X X inactive inactive inactive inactive inactive inactive 1 If one of these two combinations of INTx signals is detected in rotate left or rotate right mode bit BCERR flag is set If enabled a CCU emergency interrupt can be generated When these states error states are reached immediately idle state is entered Semiconductor Group 6 87 SIEMENS On Chip Peripheral Components C508 2 Idle state is also entered when a wrong follower is detected if bit BCON 7 BCEM is set When idle state is entered the BCERR flag is always set Idle state can only be left when the BCERR flag is reset by software Two tables are available for rotate left direction The first table is identical to the one in C504 which has a 60 phase shift It will be selected if BCTSEL is cleared The second table has O phase shift and it will be selected if BCTSEL is set After reset the first table is selected by default This option is provided as a feature so that a wider range of motors can be operated at optimum performance In block commutation mode any signal transition at INTO 2 generates a capture pulse for CAPCOM channel 0 CCHO CCLO independently on the selected INTO 2 signal transition type rising or falling edge as defin
88. P2L gae Compare Timer 2 10 Bit Up Counter COUTSI COINI 7 Control Register CT2CON CT2 Value Reset of CT2 CP2H CP2Ll iul is a ai pp o e E el CMP2H CMP2L _ _ EE lenem Start of CT2 ET 0 0 0 Time COUTS3 COUT3I 0 COUT3 E AR aded gt COUTSI 1 Figure 6 32 COMP Unit Block Diagram and Pulse Generation Scheme Semiconductor Group 6 74 SIEMENS On Chip Peripheral Components C508 The COMP unit has a 10 bit up counter compare timer 2 CT2 which starts counting from 000p up to the value stored in the period register and then is again reset This compare timer 2 operation is equal to the operating mode 0 of compare timer 1 When the count value of CT2 matches the value stored in the compare registers CMP2H CMP2L COUTS toggles its logic state When compare timer 2 is reset to 0001 COUTS toggles again its logic state COUTS is only an output pin After a reset operation COUTS drives a high level as defined by the reset value 21 of bit COUT3 of SFR COINI When compare timer 2 is running bit CT2R in SFR CT2CON is set bit ECT2O in SFR CT2CON allows the disconnection of COUT3 from compare timer 2 signal generation In this case the logic value of COUTSI bit COINI 7 is put to the COUT3 output When ECT2O is set thereafter the compare timer 2 output signal is again switched to the COUTS output In the combined multi channel PWM modes and i
89. PTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 100 compatibility to 8051 architecture the C508 contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program may keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the C508 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 4 3 illustrates the addressing mechanism A 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx Special Function Register DPSEL Address 9214 Reset Value XXXXX000p Bit No MSB LSB 7 6 5 4 3 2 1 0 92H B A 0 DPSEL Bit Function DPSEL 2 0 Data pointer select bits DPSEL 2 0 defines the number of the actual active data pointer DPTRO 7 Semiconductor Group 4 6 SIEMENS External Bus Interface C508 ABE DPSEL 92 y DPT
90. R7 DPSEL Selected Data 2 1 0 pointer DPTRO DPTR 1 DPTR 2 DPH 83y DPL 8214 DPTR 3 DPTR 4 DPTR5 DPTR6 DPTR 7 DPTRO pe Ee nec eede External Data Memory MCD00779 A O O O O A O O 4 O O O O O O Figure 4 3 Accessing of External Data Memory via Multiple Datapointers 4 6 3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the contents of the datapointer must be altered between two or more 16 bit addresses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM 4 6 4 Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table 1FFFY Start address of table in external RAM 2FAOy Semiconductor Group 4 7 SIEMENS External Bus Interface C508 Example 1 Using only One Datapointer Code for a C501 Initialization Routine MOV LOW SRC PTR 40FFH Initialize shadow variables with source pointer MOV HIGH SRC PTR 1FH
91. RAM could be dangerous since indeterminate values could be read from the external bus To avoid this the XMAPO bit is forced to 1 only by a reset operation Additionally during reset an internal capacitor is charged So the reset status is a disabled XRAM Once a 0 is written to XMAPO bit i e discharging the capacitor it is not possible to set it back again to 1 due to the charge time of the capacitor On the other hand any distortion viz software hang up noise etc also can not charge this capacitor Thus the stable status is the enabled XRAM The clear instruction for the XMAPO bit should be integrated in the program initialization routine before XRAM is used In extremely noisy systems the user may have redundant clear instructions Semiconductor Group 3 4 SIEMENS Memory Organization C508 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode The XRAM can be accessed by two read write instructions which use the 16 bit DPTR for indirect addressing These instructions are MOVX A QDPTR Read MOVX DPTR A Write For accessing the XRAM the effective address stored in DPTR must be in the range of FCOOy to FFFFy 3 4 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX A Ri Read
92. RECEIVE is cleared and RI is set Semiconductor Group 6 106 SIEMENS On Chip Peripheral Components C508 Internal Bus 1 Write to SBUF RXD P3 0 Alt Output Function TXD P3 1 Alt Output Serial Function Port Interrupt REN E 2 RI Receive RX Control RXD P3 0AIt Input Function Load SBUF Read SBUF M Internal Bus 2 MCS02101 Figure 6 43 Serial Interface Mode 0 Functional Diagram Semiconductor Group 6 107 SIEMENS On Chip Peripheral Components C508 Transmit Co co Co Lo WM op co Na N Co co Co Lo Co Co co Na Co co Co Lo WM Mo an o Co co Co Lo Co na Na N Co co Co Lo WM na Na o Co co Co Lo Co Co co an eo Co co mw Co na Na N Co co Co Lo Co na an oN Co co Co Lo WM na an N Co co Mw Co Co co Na N Write to SBUF S6P2 Send Shift TXD Shift Clock m S3P1 Receive Write to SCON Clear RI Receive Shift S5P TXD Shift Clock MCT02102 Figure 6 44 Serial Interface Mode 0 Timing Diagram Semiconductor Group 6 108 SIEMENS On Chip Peripheral Components C508 6 4 5 Details about Mode 1 Ten bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit
93. Register IENO Address A814 Reset Value 00y Special Function Register IRCON Address C0 Reset Value X0000000p MSB LSB Bit No AFy AEQ ADu ACy AB AA A94 AH A8H EA WDT ET2 ES ETI EX1 ETO EXO IENO Bit No C74 C64 Cdy C44 C34 C24 Clu CO Coy EN TF2 IEX6 IEX5 IEX4 IEX3 IEX2 ADC IRCON Es The shaded bits are not used in timer counter 2 interrupt control Bit Function ET2 Timer 2 overflow external reload interrupt enable If ET2 0 the timer 2 interrupt is disabled If ET2 1 the timer 2 interrupt is enabled TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt Semiconductor Group 6 28 SIEMENS On Chip Peripheral Components C508 Special Function Register CCEN Address C11 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 C1y COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAHO COCALO CCEN Bit Function COCAH3 Compare capture mode for CC register 3 COCAL3 COCAH3 COCAL3 Function 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P5 3 T2CC3 INT6 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 COCAH2 Compare capture mode for CC register 2 SUD COCAH2 COCAL2 Function 0 0 Compare capture disabled 0 1
94. S ooooocccocncor ro 4 1 4 1 2 Bu xr e e o ia E ea 4 3 4 1 3 External Program Memory Access oocooccccco eere 4 3 4 2 PSEN Program Store Enable ocooocccococooonr 4 3 4 3 Overlapping External Data and Program Memory Spaces 4 3 4 4 ALE Address Latch Enable lee RII 4 4 4 5 Enhanced Hooks Emulation Concept ooococcccoccncor ees 4 5 4 6 Eight Datapointers for Faster External Bus Access ooooccccocc eee eee 4 6 4 6 1 The Importance of Additional Datapointers oooooococccno ee 4 6 4 6 2 How the eight Datapointers of the C508 are implemented sus 4 6 4 6 3 Advantages of Multiple Datapointers oooooccoocooooo ee 4 7 4 6 4 Application Example and Performance Analysis oo occcoooommmoooooo 4 7 4 7 ROM OTP Protection for the C508 4R C508 4E 00 2 0 ce eee 4 10 4 7 1 Unprotected ROM Mode sii REEL RR area 4 10 4 7 2 Protected ROM OTP Mode cisne dad is 4 11 4 8 Version Registers aa de da recia RR RR SUR aft 4 14 5 Reset and System Clock Operation oooooooccnn eee 5 1 5 1 Hardware Reset Operation rene 5 1 5 2 Fast Internal Reset after Power On ooooocccococcccocoo ellen 5 3 5 8 Hardware Reset Timing oz odo Shae Ameen RR TERRENT TERRE MS 5 5 5 4 Clock Generation sac Mei ee hae Drie aa EA AAA a aah 5 7 5 9 PLE Operation coe taras ra Es SO AR ee eS 5 7 5 6 Oscillator and Clock Circuit succionar ws det de wee ON o 5 8 6 On Chip Pe
95. S 01 SIUM 99x 6 114 Serial Interface Mode 2 and 3 Timing Diagram Semiconductor Group Figure 6 48 SIEMENS On Chip Peripheral Components C508 6 5 A D Converter The C508 includes a high performance high speed 10 bit A D Converter ADC with 8 analog input channels lt operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors The A D converter provides the following features 8multiplexed input channels port 4 which can also be used as digital inputs outputs 10 bit resolution Single or continuous conversion mode nternal start of conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Bullt in hidden calibration of offset and linearity errors The externally applied reference voltages have to be held at a fixed value within the specifications The main functional blocks of the A D converter are shown in Figure 6 49 6 5 1 A D Converter Operation An internal start of a single A D conversion is triggered by a write to ADDATL instruction The start procedure itself is independent of the value which is written to ADDATL When single conversion mode is selected bit ADM 0 only one A D conversion is performed In continuous mode bit ADM 1 after completion of an A D con
96. SC 3 P3 4 TO Pin C T 1 Control Gate P3 2 INTO TF1 Interrupt TR1 Figure 6 12 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Group 6 22 SIEMENS On Chip Peripheral Components C508 6 2 2 Timer Counter 2 with Additional Compare Capture Reload The timer 2 with additional compare capture reload features is one of the most powerful peripheral units of the C508 It can be used for all kinds of digital signal generation and event capturing like pulse generation pulse width modulation pulse width measuring etc Timer 2 is designed to support various automotive control applications as well as industrial applications frequency generation digital to analog conversion process control etc Please note that the functionality of this timer is not equivalent to timer 2 of the C501 The C508 timer 2 in combination with the compare capture reload registers allows the following operating modes Compare up to 4 PWM output signals with 65535 steps at maximum and 300 ns resolution Capture up to 4 high speed capture inputs with 300 ns resolution Reload modulation of timer 2 cycle time The block diagram in Figure 6 13 shows the general configuration of timer 2 with the additional compare capture reload registers The I O pins which can be used for timer 2 control are located as multifunctional port functions at port 1 see Table 6 4 Table 6 4 Alternate Port Functions of Timer
97. SIE Semicon ductor Siemens Semiconductor is Infineon Technologies SI EM EN S Since April 1 1999 ENS e The next revision of this document WWW in Eo will be updated accordingly C508 8 Bit CMOS Microcontroller User s Manual 06 99 Since April 1 1999 Semiconductor Siemens Semiconductor e is Infineon Infineon Technologies 109 ies The next revision DN of this document VWW in o will be updated accordingly Edition 06 99 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 97 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC m
98. T5 INT4 INT3 CCx stands for CRC T2CC1 to T2CC3 IEXx stands for IEX3 to IEX6 Interrupt Figure 6 16 Timer 2 with Registers CCx in Compare Mode 0 Semiconductor Group 6 33 SIEMENS On Chip Peripheral Components C508 Timer Count FFFFy Timer Count c RS Compare Value o Timer 2 Timer Count Reload Value 7 Interrupt can be generated on overflow Compare Output P5 x T2CCx N can be generated on compare match Figure 6 17 Function of Compare Mode 0 6 2 2 3 2 Modulation Range of a PWM Signal in Compare Mode 0 Generally it can be said that for every PWM generation in compare mode 0 with n bit wide compare registers there are 2 different settings for the duty cycle Starting with a constant low level 096 duty cycle as the first setting the maximum possible duty cycle would then be 1 1 2 x 100 This means that a variation of the duty cycle from 096 to real 10096 can never be reached if the compare register and timer register have the same length There is always a spike which is as long as the timer clock period This spike may either appear when the compare register is set to the reload value limiting the lower end of the modulation range or it may occur at the end of a timer period This spike in CCx register configuration of timer 2 in compare mode 0 is divided into two halves One at the beginning when the contents of the compare register is equal to the re
99. The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in Figure 7 6 01 h c2 cs ca gt e 65 Spe E A ee 4 SSS eae i Interrupts Long call to Interrupt Interrupt
100. addressable bit locations The stack can be located anywhere in the internal RAM area and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16 bit or an 8 bit address The internal XRAM is located in the external address memory area at addresses FC00 to FFFFy Using MOVX instruction with addresses pointing to this address area alternatively internal XRAM or external data RAM are accessed 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interrupt service routines The eight general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the stack pointer to location 074 and increments it once to start from location 08y which is also the first register RO of register bank 1 Thus if one is going to use more than one
101. alid at the rising edge of PALE With the falling edge of PALE the upper addresses A8 A14 of the 15 bit OTP memory address are latched After A8 A14 has been latched A0 A7 is put on the address bus port 2 A0 A7 must be stable when PROG is low or PRD is low If subsequent OTP address locations are accessed with constant address information at the high address lines A8 A14 A8 A14 must only be latched once page address mechanism Figure 10 5 shows a typical basic OTP memory programming cycle with a following OTP memory read operation In this example AO A14 of the read operation are identical to A8 A14 of the preceeding programming operation PMSEL1 0 Port 2 PALE D0 D7 D0 D7 min 100 uis gt min 100 ns Figure 10 5 Programming Verify OTP Memory Access Waveform If the address lines A8 A14 must be updated PALE must be activated for the latching of the new A8 A14 value Control address and data information must only be switched when the PROG and PRD signals are at high level The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode Semiconductor Group 10 8 SIEMENS OTP Memory Operation C508 Figure 10 6 shows a waveform example of the program read mode access for several OTP memory bytes In this example OTP memory locations 3FDy to 4004 are programmed Thereafter OTP memory locations 400y and 3FDy are read P
102. anufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs incurred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be en dangered C508 User s Manual Revision History Current Version 06 99 Previous Releases Original Version We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the qualit
103. ap State YU COUTx III Trap oe y 2 CTRAP MCT02606 Note The state of the CCx and COUTx signals in trap state is defined by the corresponding bits in COTRAP Figure 6 31 Trap Function of the CAPCOM Unit Semiconductor Group 6 56 On Chip Peripheral Components SIEMENS C508 6 3 2 8 CAPCOM Registers The CAPCOM unit of the C508 contains several special function registers Table 6 7 gives an overview of the CAPCOM related registers Table 6 7 Special Function Registers of the CAPCOM Unit Unit Symbol Description Address CAPCOM CT1CON Compare timer 1 control register Ely Capture CCPL Compare timer 1 period register low byte DEH Compare CCPH Compare timer 1 period register high byte DFH Unit CT1OFL Compare timer 1 offset register low byte E6H CT1OFH Compare timer 1 offset register high byte E7y CMSELO Capture compare mode select register 0 E3y CMSEL1 Capture compare mode select register 1 E4y CCLO Capture compare register 0 low byte F2H CCHO Capture compare register 0 high byte F3H CCL1 Capture compare register 1 low byte F4y CCH1 Capture compare register 1 high byte FSH CCL2 Capture compare register 2 low byte F6H CCH2 Capture compare register 2 high byte F7H CCIR Capture compare interrupt request flag register E5y CCIE Capture compare interrupt enable register D6y COINI Compare output initialization register E2H TRCON Trap enable register FFH
104. atch interrupt 6 Timer 2 overflow Compare timer 1 External interrupt 6 interrupt Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IPO and one in IP1 A low priority interrupt can be interrupted by a high priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure determined by the polling sequence This is illustrated in Table 7 2 Semiconductor Group 7 22 SIEMENS Interrupt System C508 Table 7 2 Interrupts Priority within Level Interrupt Priority Bits of Interrupt Source Priority Priority Group Interrupt Group High Priority E Low Priority 1 IP1 0 IP0 0 IEO ADC High 2 IP1 1 IPO 1 TFO IEX2 3 IP1 2 IPO 2 IE1 TRF IEX3 IEX7 BCERR 4 IP1 3 IPO 3 TF1 CT2P IEX4 IEX8 5 IP1 4 IPO 4 RI TI CCxR IEX5 IEX9 CCxF Low 6 IP1 5 1P0 5 TF2 CT1FP IEX6 CT1FC Within a group the leftmost interr
105. ated by the output signal of the COMP unit Using the burst mode the CAPCOM unit operates in compare mode and the COMP unit provides a PWM signal which is switched to the COUTx outputs This PWM signal typically has a higher frequency than the compare output signal of the CAPCOM unit Figure 6 30 shows the waveform generation using the burst mode Count Value A Period Register Compare Timer 1 CT10FF 0 Compare Register Start of CT1 Na a Time COUTx COINI 1 CMSELx3 0 Burst Mode COUTx gt Poo Disabled COINI 0 oe A V V UV uy ATA AAA V V v v LUV uiv ATA COUTS3 MU Sx COUTx COUTXI 0 COINI 1 COUTSI 0 COUTXI 1 A NN UL coors COUTx COUTXI 1 LLLA 111 o COUTXI 0 Note If the Bits COUT3I and COUTXI in the COINI register are identical COUTS and the burst signals at COUTx have the same polarity MCT02605 Figure 6 30 Burst Mode Operation The burst mode of a COUT x output is enabled by the bit CMSELx3 which is located in the mode select registers CMSELO and CMSEL1 Figure 6 30 shows four CAPCOM output signals with different initial logic states with burst mode disabled CMSELx3 0 and burst mode enabled CMSELx3 1 Generally the CCx outputs cannot operate in burst mode Optionally the signal at COUTx may have inverted polarity than the PWM signal which is available at pin COUTS Semiconductor Group 6 53 SIEMENS On Chip Peripheral Components C
106. ax 34us PLL starts with base frequency starts Sequence active ext program but still unlocked by Osc WD Reset Signal execution max 768 RC Clock Cycles SN3IN3IS 3420 2 USIS S 19S9Y 8059 SIEMENS Reset System Clock C508 Using a crystal or ceramic resonator for clock generation the external reset signal must be held active at least until the on chip oscillator has started and the internal watchdog reset phase is completed after phase IV in Figure 5 2 When an external clock generator is used phase ll is very short Therefore an external reset time of typically 1 ms is sufficent in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Figure 5 3 is a close up view of phase 1 in Figure 5 2 When RESET is high after Vpp is stable Port 1 will be defined with its default value ie high All other ports will still remain undefined for at most 34 us undefined typ 18 us max 34 us Note Except for P1 1 port 1 pins will be raised high when RESET is active Figure 5 3 Fast Reset of Compare Capture Output Pins Port 1 5 3 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active high level the internal
107. ay timer The current state of the outputs CCx and COUTx after each transition at the INTO 2 inputs will be maintained They will change states only after the desired delay has passed To enable this feature bit PDTEN of register COTRAP must be set The length of delay required is programmed by writing to capture compare registers CCL1 and CCH1 When a transition at the INTO 2 inputs is detected compare timer 1 is reset and started by hardware When the compare value is reached the states of the PWM outputs are changed The compare timer 1 can continue counting to its period value When the next transition at the INTO 2 inputs is detected compare timer 1 is again reset and the same process is repeated Since compare timer 1 is used as the counter for the phase delay the resolution of the phase delay timer is the same as that for compare timer 1 The interval between successive transitions at the INTO 2 inputs imposes a constraint on the value that can be programmed in registers CCL1 and CCH1 This value cannot result in a delay that is longer than the interval between successive transitions at the INTO 2 inputs Compare Compare Timer 1 Value PWM State PWM State with phase delay Phase Delay Figure 6 36b The figure above shows the change in PWM states ie CCx and COUTx outputs with respect to the change in input signal combination at INTO 2 for cases with and without phase delay timer With the phase delay tim
108. but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI SBUF is the receive and transmit buffer of serial interface Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register Semiconductor Group 6 99 SIEMENS On Chip Peripheral Components C508 Special Function Register SCON Address 98H Special Function Register SBUF Address 99 y Reset Value 00y Reset Value XXy Bit No MSB LSB 9Fy 9EH 9DH 9CH 9BH 9AH 99H 98H 98H SMO SM1 SM2 REN TB8 RB8 TI RI SCON 7 6 5 4 3 2 1 0 99H Serial Interface Buffer Register SBUF Bit Function SMO Serial port 0 operating mode selection bits SM1 SMO SM1 Selected operating mode 0 0 Serial mode 0 Shift register fixed baud rate fosc 3 0 1 Serial mode 1 8 bit USART variable baud rate 1 0 Serial mode 2 9 bit USART fixed baud rate fosc 8 or fosc 16 1 1 Serial mode 3 9 bit USART variable baud rate SM2 Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is O In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 REN Enable receiver of serial port Enables serial reception Set by s
109. cial Function Register IRCON Address CO Reset Value 00H MSB LSB BitNo BFu BE BD BCy BBy BA B B amp H B8y SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 C7H C6y C5H C4y C3H C2H Clg COH COH TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCON The shaded bits are not used for A D converter control Bit Function EADC Enable A D converter interrupt If EADC 0 the A D converter interrupt is disabled IADC A D converter interrupt request flag Set by hardware at the end of an A D conversion Must be cleared by software Semiconductor Group 6 120 On Chip Peripheral Components SIEMENS CENE 6 5 3 A D Converter Clock Selection The ADC uses two clock signals for operation the conversion clock f apc 1 tapc and the input clock fin 71 tiN fApc is derived from the C508 system clock 2 x fosc which is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as shown in Figure 6 50 The input clock fiy is equal to 2 x fosc The conversion clock fApc is limited to a maximum frequency of 2 MHz Therefore the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz The prescaler ratio is selected by the bits ADCL1 and ADCLO of SFR ADCON1 The table in Figure 6 50 shows the prescaler ratio which must be selected by ADCL1 and ADCLO for typical system clock rates Up to 8 M
110. cifications for high low input voltages and for the eight multiplexed analog inputs PSEN 46 54 O The Program Strobe Enable output is a control signal that enables the external program memory to the bus during external fetch operations lt is activated every one and a half oscillator periods except during external data memory accesses Remains high during internal program execution This pin should not be driven during reset operation ALE 45 53 O The Address Latch Enable output is used for latching the low byte of the address into external memory during normal operation It is activated every one and a half oscillator periods except during an external data memory access When instructions are executed from internal ROM EA 1 the ALE generation can be disabled by bit EALE in SFR SYSCON This pin should not be driven during reset operation EA 2 10 External Access Enable When held at high level instructions are fetched from the internal ROM when the PC is less than 8000 When held at low level the C508 fetches all instructions from external program memory This pin should not be driven during reset operation l Input O Output Semiconductor Group 1 9 IE Introduction SIEMENS EOR Symbol Pin Numbers 1 0 Function P MQFP 64 P SDIP 64 P0 0 P0 7 57 64 1 8 O PortO is an 8 bit open drain bidirectional I O port Port 0 pins that have 1 s written to them float and in that state can
111. compare mode 1 is selected T2CM 0 selects compare mode 0 T2l Timer 2 input selection T2I Function 0 No input selected timer 2 stops 1 Timer function input frequency fose 3 T2PS 0 or fosc 6 T2PS 1 Semiconductor Group 6 26 SIEMENS On Chip Peripheral Components C508 Special Function Register TL2 Address CC Reset Value 00y Special Function Register TH2 Address CD Reset Value 00y Special Function Register CRCL Address CA Reset Value 00H Special Function Register CRCH Address CB Reset Value 00y BitNo MSB LSB 7 4 3 2 1 0 CCH 7 4 3 2 1 LSB TL2 CDy MSB 4 3 e 1 0 TH2 CAH 7 4 3 2 LSB CRCL CBy MSB 4 3 2 1 0 CRCH Bit Function TL2 7 0 Timer 2 value low byte The TL2 register holds the 8 bit low part of the 16 bit timer 2 count value TH2 7 0 Timer 2 value high byte The TH2 register holds the 8 bit high part of the 16 bit timer 2 count value CRCL 7 0 Reload register low byte compare capture functions CRCL is the 8 bit low byte of the 16 bit reload register of timer 2 It is also used for CRCH 7 0 Reload register high byte compare capture functions CRCH is the 8 bit high byte of the 16 bit reload register of timer 2 It is also used for Semiconductor Group 6 27 SIEMENS On Chip Peripheral Components C508 Special Function
112. compare outputs can be put immediately into their state as defined in COTRAP register The CCU unit has four main interrupt sources with their specific interrupt vectors Interrupts can be generated at the compare timer 1 period match or count change events at the compare timer 2 period match event at a CAPCOM compare match or capture event and ata CAPCOM emergency event An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected All interrupt sources can be enabled disabled individually Semiconductor Group 6 45 SIEMENS On Chip Peripheral Components C508 6 3 2 CAPCOM Unit Operation 6 3 2 1 CAPCOM Unit Clocking Scheme The CAPCOM unit is basically controlled by the 16 bit compare timer 1 Compare timer 1 is the timing base for all compare and capture capabilities of the CAPCOM unit The input clock for compare timer 1 is directly coupled to the system clock of the C508 Its frequency can be selected via three bits of the CT1CON register in a range of 2fosc up to fosc 64 For the understanding of the following timing diagrams Figure 6 25 shows the internal clocking scheme of the CAPCOM unit The internal input clock of the CAPCOM unit is a symmetrical clock with 50 duty cycle The clock transitions edges of the CAPCOM internal input clock are used for different actions At clock edge 1 the compare timer 1 is clocked to the next count value and with clock edge 2
113. compare timer 1 must be 00004 CT1OFH CT1OFL 00p The 16 bit capture compare registers must be 0000y CCLO CCHO CCL1 CCH1 CCL2 CCH2 00 Bits CMSELx3 x 0 2 in the SFRs CMSELO CMSEL1 must be set Compare timer 2 must be enabled and initialized for compare output signal generation Both the CCx and the COUTx outputs can be controlled by compare timer 2 A combination of outputs modulated by compare timer 1 and or compare timer 2 is supported 6 3 4 7 Trap Function in Multi Channel Block Commutation Mode The trap function in the block commutation mode operates comparable to the trap function as described in chapter 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode on page 6 55 But there is one difference when CTRAP becomes inactive high the CCx and COUTx outputs are again switched back to the PWM pulse generation when compare timer 2 reaches the count value 0004 instead of compare timer 1 in all other modes All other trap functions of the multi channel PWM modes are identical as described in chapter 6 3 2 7 Semiconductor Group 6 97 SIEMENS On Chip Peripheral Components C508 6 4 Serial Interface The serial port of the C508 is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register however if the first byte still hasn
114. compare timer 2 value is equal to the value stored in the period register the COUTS signal changes from inactive to active state If CP2H CP2L is written only shadow latches are written The content of these latches is transferred to the real registers at compare timer count value 000y using bit STE2 of SFR CT2CON When the compare timer 2 period registers CP2L CP2H are read always the shadow registers are accessed Special Function Register CP2L Address D2 Reset Value 00y Special Function Register CP2H Address D3 Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D24 7 6 5 4 3 2 1 0 CP2L D3H B E Al 0 CP2H Bit Function CP2L 7 0 Compare timer 2 period low byte The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 shadow latch CP2H 1 0 Compare timer 2 period high bits The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 shadow latch Reserved bits Semiconductor Group 6 78 SIEMENS On Chip Peripheral Components C508 Compare Timer 2 Compare Registers The compare registers CMP2H CMP2L of compare timer 2 hold the 10 bit compare value which defines the duty cycle of the output signal at COUT3 When the compare timer 2 value is equal to the value stored in the CMP2H CMP2L register the COUT3 signal changes from passive to active state If CMP2H CMP2L is written
115. consecutive instructions The first instruction sets the flag bit IDLE PCON 0 and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS does not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect Note PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the
116. count value 0000 The trap function is controlled by bits in the TRCON register The general enable function of the external CTRAP signal is controlled by one bit TRPEN Further each CAPCOM compare channel output can be enabled disabled selectively for trap function Figure 6 31 shows the trap function for the two outputs CCx and COUTx of one compare channel x The timing diagram implies that the trap function is enabled at the CCx and COUTx outputs At reference point 1 in Figure 6 31 CTRAP becomes active and at reference point 2 the trap state is released again synchronously to the compare timer 1 count state 00004 If the trap function is enabled and CTRAP becomes active bit TRF trap flag in SFR TRCON is set and a CCU emergency interrupt will be generated if the related interrupt enable bits are set The flag TRF is level sensitive and must be cleared by software The trap function used in block commutation mode differs from the trap function described above Especially the synchronization scheme is different see section 6 3 4 7 Semiconductor Group 6 55 SIEMENS On Chip Peripheral Components C508 a Trap Function in CAPCOM Operating Mode 0 Period CT1 CT10FF Value Compare N Value CT Offset QUA CCx T Trap State COUTx Y Trap State y 2 CTRAP b Trap Function in CAPCOM Operating Mode 1 Period CT1 CT10FF Value Compare Value Offset CCx YY Tr
117. ctor Group 7 4 SIEMENS Interrupt System C508 Highest Priority Level Ae FA USART SCON 0 dits Wa IENO 4 SCON 1 Q5 0 Fv CC2 S e q u e n c e CCIR 5 CCIEO 5 Capture Compare Match Interrupt P5 2 TS IRCON 4 IEN1 4 P5 5 4 ENTS Exo 2 IEN3 4 EINT 4 EA Bit addressable d Request flag is cleared by hardware Figure 7 4 Interrupt Structure Overview Part 4 Semiconductor Group 7 5 SIEMENS Interrupt System C508 Overflow IRCON 6 IENO 5 cree Ho CCIR 7 ECTP CCIE 7 Compare 21 Timer 1 Pd Interrupt ECT1 IEN2 5 erro fo CCIR 6 ECTC CIE Q o P5 3 T2663 e id IRCON 5 IEN1 5 DN Bit addressable 4 Request flag is cleared by hardware Highest Priority Level Mo Priority Level GS 0 U 0O0O50CO000 Figure 7 5 Interrupt Structure Overview Part 5 Semiconductor Group IEMEN Interrupt System 2 gt C508 7 2 Interrupt Registers 7 2 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO IEN1 IEN2 and IEN3 Register IENO also contains the global disable bit EA which can be cleared to disable all interrupts at once Generally after reset all interrupt enable bits are set to 0 That means that the corresponding interrupts are disabled The SFR IENO contains the enable bi
118. cuit which affect the input and output clock signal of the baud rate generator After reset the divide by 2 circuit is active and the resulting overflow output clock will be divided by 2 The input clock of the baud rate generator is 2 x fosc output of PLL Baud Rate Generator SRELH alol SRELL L1 2fosc 10 Bit Timer PCON 7 SMOD Overflow Figure 6 42 Serial Port Input Clock when using the Baud Rate Generator The baud rate generator consists of a free running upward counting 10 bit timer On overflow of this timer next count step after counter value 3FFpj there is an automatic 10 bit reload from the registers SRELL and SRELH The lower 8 bits of the timer are reloaded from SRELL while the upper two bits are reloaded from bit O and 1 of register SRELH The baud rate timer is reloaded by writing to SRELL Semiconductor Group 6 103 SIEMENS On Chip Peripheral Components C508 Special Function Register SRELH Address BA Reset Value XXXXXX11p Special Function Register SRELL Address AA Reset Value D9y Bit No MSB LSB 7 6 5 4 3 2 1 0 MSB BAH E 9 8 SRELH Aay 7 6 5 A 3 2 e SREL E The shaded bits are not used for reload operation Bit Function SRELH 0 1 Baud rate generator reload high value Upper two bits of the baud rate timer reload value SRELL 0 7 Baud rate generator reload low value
119. cumulated verify result of the previous 16 bytes of data In ROM verification mode 2 the C508 must be provided with a system clock at the XTAL pins Figure 4 6 shows an application example of an external circuitry which allows to verify a protected ROM inside the C508 4R in ROM OTP verification mode 2 With RESET going inactive the C508 starts the ROM OTP verify sequence Its ALE is clocking a 15 bit address counter This counter generates the addresses for an external EPROM which is programmed with the contents of the internal protected ROM OTP The verify detect logic typically displays the state of the verify error output P3 5 P3 5 can be latched with the falling edge of ALE The CY signal of the address counter indicates to the verify detect logic the end of the internal ROM verification Semiconductor Group 4 12 SIEMENS External Bus Interface C508 Verify Detect Logic CY CLK 15 Bit Address Counter C508 4R C508 4E Compare Code ROM Figure 4 6 ROM OTP Verification Mode 2 External Circuitry Example Semiconductor Group 4 13 SIEMENS External Bus Interface C508 4 8 Version Registers Version registers are typically used for adapting the programming firmware to specific device characteristics such as ROM OTP size etc Three version registers are implemented in the C508 They can be read during normal program execution mode as mapped SFRs when the bit RMAP in SFR SYSCON is set The first step of t
120. de BCM1 0 0 1 with COINI XX000000 p Start Compare Timer 1 gt cco COUT1 High Active A rcu RN el COUT2 2 State No 2 1 4 3 2 1 4 3 MCT02612 Figure 6 37 Basic Compare Timer 1 Controlled 4 Phase PWM Timing Semiconductor Group 6 91 SIEMENS On Chip Peripheral Components C508 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111 p Start Compare Timer 1 gt cco COUT1 Lows Active CC2 Phase COUTO COUT2 State No 1 2 3 4 5 1 2 3 4 5 1 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000 p Start Compare Timer 1 gt cco COUT1 High Active CC2 Phase COUTO COUT2 State No 2 1 5 4 3 2 1 5 4 3 2 MCT02614 Figure 6 38 Basic Compare Timer 1 Controlled 5 Phase PWM Timing Semiconductor Group 6 92 SIEMENS On Chip Peripheral Components C508 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111 B Start Compare Timer 1 gt cco COUT1 CC2 Low Active Phase COUTO CC1 COUT2 State No 1 2 3 4 5 6 1 1 2 3 4 5 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000 p S
121. dependent from any service delay which in real time applications could be disastrous The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event This in turn is supposed to happen after a sufficient amount of time Please note the following special case where a program using compare interrupts could show a surprising behavior The configuration has already been mentioned in the description of compare mode 1 The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock In this case it should be carefully considered that the compare signal is active as long as the timer 2 count is equal to the contents of the corresponding compare register and that the compare signal has a rising and a falling edge Furthermore the shadow latches used in compare mode 1 are transparent while the compare signal is active Thus with a slow input clock for timer 2 the comparator signal is active for a long time i e high number of machine cycles and therefore a fast interrupt controlled reload of the compare register could not only change the shadow latch as probably intended but also the output buffer When using the CRC you can select whether an interrupt should be generated when the compare signal goes active or inactive depending on the status of bit IBFR in T2CON Initializing the interrupt to be negative transition triggered
122. des are provided for this function In mode 0 an external event latches the timer 2 contents to a dedicated capture register In mode 1 a capture will occur upon writing to the low order byte of the dedicated 16 bit capture register This mode is provided to allow the software to read the timer 2 contents on the fly In mode 0 the external event causing a capture is for T2CC registers 1 to 3 a positive transition at pins T2CC1 to T2CC3 of port 5 forthe CRC register a positive or negative transition at the corresponding pin depending on the status of the bit ISFR in SFR T2CON If the edge flag is cleared a capture occurs in response to a negative transition If the edge flag is set a capture occurs in response to a positive transition at pin P5 0 T2CCO INT3 In both cases the appropriate port 5 pin is used as input and the port latch must be programmed to contain a one 1 The external input is sampled in every machine cycle When the sampled input shows a low high level in one cycle and a high low in the next cycle a transition is recognized The timer 2 contents is latched to the appropriate capture register in the cycle following the one in which the transition was identified In mode 0 a transition at the external capture inputs of registers T2CC1 to T2CC3 will also set the corresponding external interrupt request flags IEX3 to IEX6 If the interrupts are enabled an external capture signal will cause the CPU to v
123. down mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode When the double instruction sequence shown above is used the power down mode can only be left by a reset operation If the external wake up from power down capability has also to be used its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above ORL SYSCON 00010000B set RMAP ORL PCON1 80H enable wake up from power down via P3 2 INTO ANL SYSCON 11101111B reset RMAP for future SFR accesses Setting EWPD automatically disables all interrupts still maintaining all actual values of the interrupt enable bits In the above sequence the value of register PCON1 should be modified for choosing a wake up via the P5 7 INT7 bit PCON1 4 should be set Note Before entering the power down mode an A D conversion in progress must be stopped Semiconductor Group 9 6 SIEMENS Power Saving Modes C508 9 4 2 Exit from Software Power Down Mode If power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power
124. dress F1y Reset Value 00010000p Bit No MSB LSB 7 6 5 4 3 2 1 0 Fly CT2P ECT2O STE2 CT2RES CT2R CLK2 CLK1 CLKO CT2CON The shaded bits are not used for interrupt control Bit Function CT2P Compare timer 2 period flag When the compare timer 2 value matches with the compare timer 2 period register value bit CT2P is set If the compare timer 2 interrupt is enabled the setting of CT2P will generate a compare timer 2 interrupt Bit CT2P must be cleared by software Special Function Register BCON Address D74 Reset Value 00H BitNo MSB LSB 7 6 5 4 3 2 1 0 D74 BOME PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCON 3 The shaded bits are not used for interrupt control Bit Function EBCE Enable interrupt of block commutation mode error If EBCE is set the emergency interrupt for a block commutation mode error condition of the CCU is enabled In block commutation mode an emergency error condition occurs if a false signal state at INT2 INTO or a wrong follower state if selected by bit BCEM is detected see also Table 6 10 BCERR Block commutation mode error flag In block commutation mode BCERR is set in rotate right or rotate left mode if after a transition at INTx all INTx inputs are at high or low level Additionally in rotate right or rotate left mode a wrong follower condition according Table 6 10 can cause the setting
125. ds 6 75 6 79 A IA ES 3 17 Compare registers 6 79 GOIFEN oi iii 3 17 CT2 control register 6 76 A SEES eai 3 17 Semiconductor Group 11 1 SIEMENS C508 OO TI os 24 corag 2 068 APRARRI SE IS 3 17 DOOALDD osi ex este cosi es 3 16 GOTREN eve REESE XE 3 17 COCA cotum sede im e e 3 16 AA Bede et ot ote ado 3 18 COIN 23 bte ts 3 14 3 17 6 57 A PMCID TEM So a et 3 17 COTRAP S La oia ALAS ok 3 14 3 18 GO2FEN 2 neto iori dete 3 17 COUTO ae eter e ina 3 17 OBI ui seme we eem epus 3 17 OWI T sea P RE etra 3 18 A uou xd end C ese CREE 3 17 COUT TI utt eh el artes 3 17 GU2BEN sterile b eset y ds 3 17 GOUT E 4 dre wants but Ems 3 18 oom e ui arated sie een deen meee oe 3 18 COUTZKSs nets sica E ERES SEES 3 17 ecc ANC PE 3 13 3 16 COUT2 sosta dos o SE ORE 3 18 CCHO use e ee thew teas 3 14 3 18 6 57 GOUT Ce as bas er see 3 17 GOL ao osa 3 14 3 18 6 57 GOUTXI dio tt e teet x 3 17 O siern s aaae 3 14 3 18 6 57 GPZH aus ctun sis sS Ete 3 14 3 17 6 75 GO od stc a RI RA NS 3 16 GPL e cies coe ease Bd 2 3 14 3 17 6 75 GOIE index Pratt 3 14 3 17 6 57 CPU CCI Ries tcd 3 14 3 17 6 57 Accumulator sss 2 3 CO esate tee tate cael ORE 3 14 3 18 6 57 B register esmas we dda we i 2 4 GOL iaa Gees 3 14 3 18 6 57 Basic timing e e 2 5 GGE2 antaras ee Rex 3 14 3 18 6 57 Fetch execute diagram 2 6 CCPH serios tech slo bor 3 14 3 17 6 57 Functionality p E EUER 2 3 CEP Lee ca m eR E t
126. e functions of these bits depend on the selected mode capture or compare of a capture compare channel In compare mode compare channel specific interrupts can be generated at a match event between compare register content and compare timer 1 count value during the up or down counting phase of compare timer 1 In capture mode capture channel specific interrupts can be generated selectively at rising or falling or both edges of the capture input signals at CCx Special Function Registers CCIE Address D6y Reset Value 00H BitNo MSB LSB 7 6 5 4 3 2 1 0 D6y ECTP ECTC CC2FEN CC2REN CC1FEN CCTREN CCOFEN CCOREN CCIE Bit Function ECTP Enable compare timer 1 period interrupt If ECTP 0 the compare timer 1 period interrupt is disabled Compare timer 1 operating mode 0 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value Compare timer 1 operating mode 1 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value and changes the count direction from up to down counting ECTC Enable compare timer 1 count direction change interrupt status If ECTC 0 the compare timer 1 count change interrupt is disabled Compare timer 1 operating mode 0 Bit has no effect on the interrupt generation Compare timer 1 operating mode 1 If ECTC 1 an interrupt is generated when compare timer 1 reaches count value 0000y and chang
127. e the outputs COUTx are switched to the PWM signal which is generated by the 10 bit compare timer 2 COMP unit The interval between a change of state of the PWM outputs and a transition at the INTO 2 inputs can be controlled by a phase delay timer If the phase delay timer is enabled the desired interval can be programmed If it is disabled then every transition will be followed by an immediate change in state of the PWM outputs This feature is described further in Section 6 3 4 4 For monitoring of sensor input signal timing in block commutation mode the signal transitions at INTO 2 can also generate an interrupt if enabled and a capture event at channel 0 of the CAPCOM unit compare timer 1 For emergency cases trap function of CTRAP input signal the six outputs CCx and COUTx can be put selectively to the levels as defined by the first six bits in COTRAP register At the multi channel PWM modes of the C508 a change of the PWM output states active or inactive is triggered by compare timer 1 which is running either in operating mode 0 or 1 If its count value reaches 0000y the PWM output signal changes its state according to a well defined state table The multi channel PWM modes are split up into three modes 4 phase multi channel PWM mode 4 PWM output signals 5 phase multi channel PWM mode 5 PWM output signals 6 phase multi channel PWM mode 6 PWM output signals Semiconductor Group 6 81 SIEMENS On C
128. ector to the appropriate interrupt service routine In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register The write to register signal e g write to CRCL is used to initiate a capture The value written to the dedicated capture register is irrelevant for this function The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction In this mode no interrupt request will be generated Figure 6 21 illustrates the operation of the CRC register while Figure 6 22 shows the operation of the compare capture registers 1 to 3 The two capture modes can be established individually for each capture register by bits in SFR CCEN compare capture enable register That means in contrast to the compare modes it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register Semiconductor Group 6 40 SIEMENS On Chip Peripheral Components C508 Timer 2 TF2 Interrupt Request External IEX3 Interrupt 3 P5 0 Request T2CC0 INT3 Figure 6 21 Timer 2 Capture with Register CRC Semiconductor Group 6 41 SIEMENS On Chip Peripheral Components C508 Input Timer 2 pui esc qe TL2 TH2 TF2 Interrupt Clock Request Write to CCL1 Mode 1 External IEX4 Interrupt 4 Request igure 6 22 Timer 2 Capture with Registers T2CC1 to T2CC3 Semiconductor Group 6 4
129. ed in the SFR ITCON SFR ITCON can be used to generate additional interrupts at an INTO 2 signal transition Semiconductor Group 6 88 SIEMENS On Chip Peripheral Components C508 Figure 6 36 gives an example of a block commutation mode timing only COUTx outputs are modulated with compare timer 2 output signal It shows the rotate left case BCM1 BCMO 1 0 BCTSEL 0 and rotate right case BCM1 BCMO 0 1 For the timing shown in Figure 6 36 the COINI register is set to XX111111p This means that a high level is defined as inactive phase The CMSELx 3 bits in the CMSELO CMSEL1 registers must also be set compare timer 2 switched to COUTx during active phase The timing shown below is directly derived from Table 6 10 a Block commutation mode timing in rotate left mode BCM1 0 1 0 INTO 0 0 0 a Input NTI 0 0 0 Signals INT2 i 0 0 0 cco CC1 ae w EE NEN NN he Output Signals b Block commutation mode timing in rotate right mode BCM1 0 0 1 m Input NTI i ED 0 Signals ee ly Output Signals l l MCTO2611 Figure 6 36 Block Commutation Mode Timing Semiconductor Group 6 89 SIEMENS On Chip Peripheral Components C508 6 3 4 4 Phase Delay Timer In block commutation mode the interval between the change in input signal combination at INTO 2 and the change in state of the outputs CCx and COUTx can be controlled by a phase del
130. egister are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control block to do one last shift and then deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after Write to SBUF Reception is initiated by the condition REN 1 and RI 0 At S6P2 of the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bit comes in from the right 1s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI
131. el COINI bit 2 0 or low level COINI bit 2 1 representing a duty cycle of 100 If the value stored in the compare register is greater than or equals to the value of the period register a low level COINI bit 0 or high level COINI bit 1 corresponds to a duty cycle of 0 Figure 6 27 shows the waveform generation in operating mode 0 when the offset register has a value which is not equal 0000y example CT1OFH CT1OFL 00025 Using compare timer 1 with an offset value not equal 0 is used to generate single edge aligned signals with a constant delay between one of the two signal transitions Compare timer 1 always counts from 00004 up to the value stored in CCP also if the value in the offset register is not equal 0 With reset count value 0000 of the compare timer 1 the CCx and COUTx will always change their logic state During the up counting phase CCx will change the logic state when the compare timer value is equal to the compare register value and COUTx will change the logic state when the compare timer value plus the offset value matches the value stored in the compare register In Figure 6 27 the waveforms a and b show an example for a waveform of two signals with a constant delay of their rising edge A compare register value of 3 is assumed Using inverted signal polarity SFR COINI signal c can be generated at COUTx If the value in the offset register plus the value of the period register is less than or equal to the value
132. el 2 Channel 1 Channel 0 Bit Function COUTSI COUTS initial logic level This bit defines the initial logic state of the output COUTS before compare timer 2 is started the first time Further COUTSI defines the logic state of output COUT3 when bit ECT2O CT2CON 6 is reset COUTS disabled COUTXI Compare timer 1 output signal inversion in burst and block commutation When COUTXI is set the output signal of compare timer 2 which is wired to the compare outputs COUTx x 0 2 in burst or block commutation mode is inverted Semiconductor Group 6 70 SIEMENS On Chip Peripheral Components C508 Bit Function CCxl COUTxI Compare output initial value x 0 2 Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are assigned to the COUTx compare outputs CCxl COUTxI 2 0 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts driving an initial value of O when this CCx COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSELO CMSEL1 registers CCxl COUTxI 2 1 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts driving an initial value of 1 when this CCx COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSELO CMSEL1 registers T
133. equest Flags Register The interrupt flags of the CAPCOM capture compare match and compare timer 1 interrupt are located in the register CCIR All CAPCOM capture compare match interrupt flags are set by hardware and must be cleared by software A capture compare match interrupt is generated with the setting of a CCxR bit x 0 2 if the corresponding enable bits are set The compare timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR CCIR Special Function Register CCIR Address E5 Reset Value 004 Bit No MSB LSB 7 6 5 4 3 2 1 0 E5y CTIFP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR CCIR CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function CT1FP Compare timer 1 period flag Compare timer 1 operating mode 0 CT1FP is set if compare timer 1 reaches the period value Compare timer 1 operating mode 1 CT1FP is set if compare timer 1 reaches the period value and changes the count direction from up to down counting Bit CT1FP must be cleared by software If compare timer 1 interrupt is enabled the setting of CT1FP will generate a compare timer 1 interrupt CT1FC Compare timer 1 count direction change flag This flag can only be set if compare timer 1 runs in operating mode 1 CTM 1 CT1FC is set when compare timer 1 reaches count value 0000y and changes the count direction from down to up counting If compare timer 1 interrupt is enabled the setting of CT1FC will
134. er enabled the PWM state changes after the compare timer 1 reaches the compare value that has been programmed This is the phase delay desired and this delay must be over before the next change in input signal combination occurs Semiconductor Group 6 90 SIEMENS On Chip Peripheral Components C508 6 3 4 5 Compare Timer 1 Controlled Multi Channel PWM Modes Using the multi channel PWM modes of the C508 several compare timer 1 controlled PWM waveforms can be generated 4 phase multi channel PWM waveforms 5 phase multi channel PWM waveforms 6 phase multi channel PWM waveforms The basic waveforms of these three compare timer 1 controlled PWM modes are shown the following three Figure 6 37 to Figure 6 39 The figures show waveforms for different COINI values with the resulting active inactive phases and rotate right rotate left condition All three figures assume that compare timer 1 operates with 100 duty cycle compare and offset registers 0000 4 and without compare timer 2 modulation Compare timer 1 duty cycles less than 100 or compare timer 2 modulation in the multi channel PWM modes are shown in Figure 6 34 and Figure 6 35 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111 p Start Compare Timer 1 gt cco COUT1 Low Active ER tee ees E a RO eap As COUT2 State No 1 2 3 4 1 2 3 4 1 2 b Timing in rotate right mo
135. eriodical refresh of the watchdog timer an internal reset will be initiated The software can be designed so that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the C508 is a 15 bit timer which is incremented by a count rate of fosc 6 upto fosc 96 The machine clock of the C508 is divided by two prescalers a divide by two and a divide by 16 prescaler For programming of the watchdog timer overflow rate the upper 7 bits of the watchdog timer can be written Figure 8 1 shows the block diagram of the watchdog timer unit 3 0 7 foso im UE Dm 14 8 WDT Reset Request IPO A9 WDTPSEL owoswors External HW reset 7 6 0 i WDTREL 86 Control Logic DA al es INO AR swot IENt B8 Figure 8 1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8 1 SIEMENS Fail Save Mechanisms C508 8 1 1 Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C508 There is a prescaler available which is software selectable and defines the input clock rate This prescaler is controlled by bit WDTPSEL in the SFR WDTREL Table 8 1 shows resulting timeout periods at fosc 5 8 and 10 MHz Special Function Register WDTREL Address 86 Reset Value 00y MSB LSB BitNo 7 6 5 4 3 2 1 0 8
136. es 3 16 DPE oot tested otha tata ee 3 12 3 15 COGALO 2 2 42s Regis 3 16 DPSEL Y aa o a ada as 3 12 3 15 CGOGALT a pO EUER cece 3 16 Semiconductor Group 11 2 SIEMENS C508 E co MMC MERE 3 15 AN Oe ee a 3 15 GET ss tate etree eh ea a ee 3 15 BADG 26 2052x346 Sad REP UR 3 16 7 9 H EALE vus iet deesse 1 9 3 16 Hardware reset o oo o o 5 1 EBGE LI minerit turae 3 17 ECOM sssssssees 3 15 VO polis SUE eee 6 1 6 43 ECEM eeeeeeeees 3 15 I2FR use ee penes EROR 3 16 7 13 ECT 2 ee eee eee 3 15 kt E 3 16 7 13 ECT2 6 ween eee 3 15 A O eat 3 18 zoro 3 18 BFR wedi a na We edet 3 18 zL 3 17 JER See Oe a a dota dde os E e 3 18 ECTP 0 seen 3 17 ADO PN NOR 3 16 6 120 7 14 EINT occ eee e eee eee eee 3 12 3 18 5 Bt MOORE CUP DEED EE 3 15 Emulation concept 4 5 Idle mode espresso e todos 9 3 9 4 ES eene 3 15 IDES 2 46 oO eese ico 3 15 ESMO 0000s 3 17 A POPE PORC ener 3 15 ETO 00 eee 3 15 ET a vil on A E 3 15 ETT lesse 3 15 IENO 3 12 3 14 3 15 6 28 8 3 p TE 3 15 7 7 IENT 3 12 3 14 3 16 6 120 8 3 ETRP coco 3 17 A uhr oho pcs 3 12 3 15 EWPD 4 3 15 js E RCNH 3 12 3 16 EXO oo eee eee eee eee 3 15 z CREE HF ARR Pete mod 3 16 EXA esses 3 15 Et Yes 3 16 ee 3 16 A PC EN 3 16 EXA cc 3 16 A TE 3 16 EXS coco 3 16 TS 3 16 EX6 coco 3 16 EXP sita ae IE 3 18 Execution of instructions 2 5 2 6 EX8 eee eee 3 18 External
137. es its count direction from down to up counting Semiconductor Group 6 68 SIEMENS On Chip Peripheral Components C508 Bit Function CCxREN x 0 2 Capture compare rising edge interrupt enable Capture Mode If CCxREN is set an interrupt is generated at a low to high transition rising edge of the corresponding CCx input signal Compare Mode If CCxREN is set an interrupt is generated if the compare timer 1 value matches the compare register CCx value during the up counting phase of the compare timer 1 This function is available in both compare timer 1 operating modes CCxFEN x 0 2 Capture compare falling edge interrupt enable Capture Mode If CCxFEN is set an interrupt is generated at a high to low transition falling edge of the corresponding CCx input signal Compare Mode If CCxFEN is set an interrupt is generated only in compare timer mode 1 if the compare timer 1 value matches the compare register CCx value during the down counting phase of the compare timer 1 This function is available only in compare timer 1 operating mode 1 Semiconductor Group 6 69 SIEMENS On Chip Peripheral Components C508 Compare Output Initialization Register COINI The six lower bits of the COINI register define the initial values passive levels of the port 1 lines which are programmed to be used as a compare output If an output of the CAPCOM unit is enabled for compare
138. esponse mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications If a ceramic resonator is used the two capacitors normally have different values depending on the oscillator frequency We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors Semiconductor Group 5 8 SIEMENS Reset System Clock C508 To internal timing circuitry Crystal or ceramic resonator Figure 5 7 On Chip Oscillator Circuiry To drive the C508 with an external clock source the external clock signal has to be applied to XTAL1 as shown in Figure 5 8 XTAL2 has to be left unconnected A pullup resistor is suggested to increase the noise margin but is optional if Voy of the driving gate corresponds to the Vinz specification of XTAL1 C508 XTAL2 External Clock XTAL1 Signal Figure 5 8 External Clock Source Semiconductor Group 5 9 SIEMENS On Chip Peripheral Components C508 6 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the C508 except for the integrated interrupt controller which is described separately in chapter
139. et If the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of typically 1ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator and the PLL have started This is described in Section 5 2 Control of external wake up from software power down mode When the software power down mode is terminated by a low level at pins P3 2 INTO or P5 7 INT7 the oscillator watchdog unit ensures that the microcontroller resumes operation execution of the power down wake up interrupt with the nominal clock rate In the power down mode the RC oscillator the on chip oscillator and the PLL are stopped They are started again when power down mode is terminated After the on chip oscillator is stable and the PLL has been locked the microcontroller starts program execution Note The oscillator watchdog unit is always enabled Special Function Register IPO Address A9jy Reset Value 00H MSB LSB BitNo 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O IPO The shaded bits are not used for fail save control Bit Function OWDS Oscillator Watchdog Status Flag Set by hardware when
140. every cycle until RESET goes low again During reset pins ALE and PSEN are configured as inputs and should not be stimulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the reset pin a pulldown resistor is internally connected to Vss to allow a power up reset with an external capacitor only An automatic power up reset can be obtained when Vpp is applied by connecting the reset pin to V5 via a capacitor After V55 has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset Semiconductor Group 5 1 SIEMENS Reset System Clock C508 The time required for a reset operation inlcudes the oscillator start up time the PLL lock time and the time for 2 machine cycles which under normal conditions must be at least 10 20 ms This requirement is typically met using a capacitor of 4 7 to 10 UF The same considerations apply if the reset signal is generated externally Figure 5 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive b C508 u RESET c Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location
141. f PO and P2 as Data Address Bus When used for accessing external memory port 0 provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port 0 pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FF to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX ORI the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 4 1 External Bus Interface SIEMENS C508 a I One Machine Cycle v One Machine Cycle
142. f Pins in Software Initiated Power Saving Modes In the idle mode and in the power down mode the port pins of the C508 have a well defined status which is listed in the following Table 9 1 This state of some pins also depends on the location of the code memory internal or external Table 9 1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORTO Data Data Float Float PORT 2 Data Data Address Data PORT 1 3 4 5 Data Data Data Data alternate outputs last output alternate outputs last output Semiconductor Group 9 8 SIEMENS Power Saving Modes C508 Semiconductor Group 9 9 SIEMENS OTP Memory Operation C508 10 OTP Memory Operation The C508 4E is the OTP version in the C508 microcontroller with a 32K byte one time programmable OTP program memory With the C508 4E fast programming cycles are achieved 1 byte in 100 usec Also several levels of OTP memory protection can be selected 10 1 Programming Configuration During normal program execution the C508 4E behaves like the C508 4R which has 32K byte of on chip ROM For programming the device the C508 4E must be put into the programming mode This typically is done not in system but in a special programming hardwa
143. g Inputs Port 5 8 bit Digital I O Figure 1 2 Logic Symbol Semiconductor Group 1 3 SIEMENS Introduction C508 1 1 Pin Configuration This section shows the pin configuration of the C508 i packages Y LO ob re lt ie S3RELCE rn up o g rdg tx QN NIN I A EFOODOO amp Qd x ox x amp LII LLIIDILILILIILILLLT AR 00 S N S zx S o dv o wo 00 wo N P2 5 A13 L 49 P2 4 A12 50 P2 3 A11 51 P2 2 A10 52 P2 1 A9 L 53 P2 0 A8 54 PO 0 ADO C 57 C508 PO 1 AD1 58 P0 2 AD2 C 59 P0 3 AD3 60 P0 4 AD4 L 61 PO 5 AD5 C 62 P0 6 AD6 C 63 P0 7 AD7 64 o ue En ois N Vppa e Vssa P4 0 ANO Ola P4 1 AN1 LJ P4 2 AN2 lu P4 3 AN3 LJ P4 4 AN4 lo P4 5 AN5 L P4 6 AN6 LJ P4 7 AN7 L Figure 1 3 Pin Configuration for P MQFP 64 1 Package Top View Semiconductor Group 1 4 P3 3 INT1 5 Co o both P MQFP 64 1 and P SDIP 64 2 doe Zea o a P ATRO CO CO CO aaa OLIT wo al wo R do wo 32171 P1 0 COUTS 81E1 P1 1 CTRAP 30 _ P1 2 CCO 2911 P1 3 COUTO 2817 P1 4 CC1 27 P1 5 COUT1 26 1 P1 6 CC2 25L P1 7 COUT2 2417 Vss 2307 Vpp 2217 P5 0 T2CCO INT3 2111 P5 1 T2CC1 INT4 2017 P5 2 T2CC2 INT5 19 1 P5 3 T2CC3 INT6 18 L1 P5 4 INT2 17 L1 P5 5 INT9 al 2r o P5 7 INT7L P5 6 INT8 C SIEMENS Introduction C508 The figure below shows the p
144. g bit ITx x 0 or 1 respectively in register TCON If ITx 0 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is negative edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt O or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external interrupts 2 3 7 8 and 9 can be programmed to be negative or positive transition activated by setting or clearing bits I2FR or I3FR in register T2CON or bits I7FR IBFR or I9FR in register EINT If IXFR 0 x 2 3 7 8 or 9 then the external interrupt x is negative transition activated If IXFR 1 external interrupt is triggered by a positive transition The external interrupts 4 5 and 6 are activated only by a positive transition Since the external interrupt pins are sampled once in each machine cycle an input high or low should be held for at least 3 oscillator periods to ensure sampling If the external interrupt is positive negative transition activated the external source has to hold the request pin low high for at least one cycle and then
145. g has a corresponding enable bit which are located in the register CCIE The compare timer 2 interrupt request flag CT2P is however located in register CT2CON The CCU emergency interrupt can be triggered by either bit TRF located in register TRCON or bit BCERR located in register BCON Each flag has an enable bit For bit TRF it is located in register CT1CON whereas for bit BCERR it is found in register BCON Semiconductor Group 7 16 SIEMENS Interrupt System C508 Special Function Register CCIR Address E5p Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 E54 CTIFP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR CCIR CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function CT1FP Compare timer 1 period flag Compare timer 1 operating mode 0 CT1FP is set if compare timer 1 reaches the period value Compare timer 1 operating mode 1 CT1FP is set if compare timer 1 reaches the period value and changes the count direction from up to down counting Bit CT1FP must be cleared by software If compare timer 1 interrupt is enabled the setting of CT1FP will generate a compare timer 1 interrupt CT1FC Compare timer 1 count direction change flag This flag can only be set if compare timer 1 runs in operating mode 1 CTM 1 CT1FC is set when compare timer 1 reaches count value 00004 and changes the count direction from down to up counting If compare timer 1 interrupt is enabled the
146. g input an analog channel is switched to the A D converter through a 3 bit multiplexer which is controlled by three bits in SFR ADCON see chapter 6 5 Port 4 lines may also be used as digital inputs In this case they are addressed as an input port via SFR P4 Since port 4 has no internal latch the contents of SFR P4 only depends on the levels applied to the input lines It makes no sense to output a value to these input only port by writing to the SFR P4 This will have no effect The parallel I O ports of the C508 can be grouped into four different types which are listed in Table 6 1 Table 6 1 C508 Port Structure Types Type Description A Standard digital I O ports which can also be used for external address data bus B Standard multifunctional digital I O port lines C Digital analog unidirectional input port D Standard digital I O with push pull drive capability Type A and B port pins are standard C501 compatible I O port lines which can be used for digital I O Type A port port 0 is also designed for accessing external data or program memory Type B port lines are located at port 2 port 3 and port 5 to provide alternate functions for the serial interface Semiconductor Group 6 1 SIEMENS On Chip Peripheral Components C508 LED drive interface PWM signals or are used as control outputs during external data memory accesses Type C port port 4 provides the analog input port Type D port lines can be
147. generate a compare timer 1 interrupt Bit CT1FC must be cleared by software CCxR Capture compare match on up count flag x 0 2 Capture Mode CCxR is set at a low to high transition rising edge of the corresponding CCx capture input signal Compare Mode CCxR is set if the compare timer 1 value matches the compare register CCx value during the up count phase Semiconductor Group 6 66 SIEMENS On Chip Peripheral Components C508 Bit Function CCxF Capture compare match on down count flag x 0 2 Capture Mode CCxF is set at a high to low transition falling edge of the corresponding CCx capture input signal Compare Mode CCxF is set if the compare timer 1 value matches the compare register CCx value during the down count phase only in compare timer 1 operating mode 1 Semiconductor Group 6 67 SIEMENS On Chip Peripheral Components C508 Capture Compare Interrupt Enable Register The bits of the interrupt enable register CCIE control the specific interrupt enable disable functions of the CAPCOM part of the capture compare unit The bits ECTP and ECTC control the compare timer 1 period count change interrupt Depending on the mode in which compare timer 1 is running interrupts can be generated at a period match or a count direction change event The lower 6 bits of CCIE are the CAPCOM channel specific interrupt enable disable control bits for the capture or compare match interrupt Th
148. gh DPTR 3 5 Accessing through RO R1 3 5 Behaviour of P2 PO 3 9 Reset operation 3 9 Table PO P2 during MOVX instr 3 10 XPAGE register 3 5 Use of P2 as I O port 3 8 Write page address to P2 3 6 Write page address to XPAGE 3 7 Semiconductor Group 11 6
149. gnature bytes 1 0 Program read lock bits 1 1 Program read OTP memory byte PSEL 35 43 Basic programming mode select This input is used for the basic programming mode selection and must be switched according to figure 10 4 PRD 36 44 Programming mode read strobe This input is used for read access control for OTP memory read version byte read and lock bit read operations PALE 37 45 Programming address latch enable PALE is used to latch the high address lines The high address lines must satisfy a setup and hold time to from the falling edge of PALE PALE must be at low level when the logic level of PMSEL1 0 is changed XTAL2 47 49 O XTAL2 Output of the inverting oscillator amplifier XTAL1 48 50 XTAL1 Input to the oscillator amplifier Input O Output Semiconductor Group 10 4 SIEMENS OTP Memory Operation C508 Table 10 1 Pin Definitions and Functions of the C508 4E in Programming Mode cont d Symbol Pin Number l O Function P MQFP64 P SDIP64 Vas 24 43 32 51 Circuit ground potential 55 63 must be applied in programming mode Vop 23 44 31 52 Power supply terminal 56 64 must be applied in programming mode P2 7 0 47 54 55 62 Address lines P2 0 7 are used as multiplexed address input lines AO A7 and A8 A14 A8 A14 must be latched with PALE PSEN 46 54 Program store enable This input must be at static O level during the whole p
150. goes into RB8 in SCON The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator Figure 6 45 shows a simplified functional diagram of the serial port in mode 1 The associated timings for transmit receive are illustrated in Figure 6 46 Transmission is initiated by an instruction that uses SBUF as a destination register The Write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to 0 transition a
151. gram memory all 8 bits of port 2 are dedicated to an output function and must not be used for general purpose I O The content of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is a MOVX ODPTR or a MOVX Ri 4 2 PSEN Program Store Enable The read strobe for external program memory fetches is PSEN It is not activated for internal program memory fetches When the CPU is accessing external program memory PSEN is activated twice every instruction cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 3 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 1 5 oscillator periods The execution sequence for these two types of read cycles is shown in Figure 4 1 a and b 4 3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C508 the external program and data memory spaces can be combined by the logical AND of PSEN and RD A positive resul
152. h conditions are met the stop bit goes into RB8 the 8 data bit goes into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RxD Semiconductor Group 6 109 SIEMENS On Chip Peripheral Components C508 6 Internal Bus 2 Write to SBUF Shift TX Control 21 Port Interrupt RX Load SBUF Start RX Control 1FF y Shift Baud Rate Clock 1 to 0 r Transition Detector e Input shift Register 9Bits RXD i Shift Load Een SBUF Read SBUF Internal Bus MCS02103 Figure 6 45 Serial Interface Mode 1 Functional Diagram Semiconductor Group 6 110 On Chip Peripheral Components SIEMENS his Transmit E S E e D o oc co a o T 9 ga SE SE Lo 20 xo x 0 lI PEN LL mo co mun e co y is o ten O 2 o c qa EO c E e x to Receive FO zg9 B ea 5 js E Figure 6 46 Serial Interface Mode 1 Timing Diagram Semiconductor Group 6 111 SIEMENS On Chip Peripheral Components C508 6 4 6 Details about Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB8 can be assigned the value of 0 or 1 On reception the 9th data bit goe
153. hardware reset must be held active only for two machine cycles for a complete reset Semiconductor Group 9 4 SIEMENS Power Saving Modes C508 9 3 Slow Down Mode Operation In some applications where power consumption and dissipation are critical the controller might run for a certain time at reduced speed e g if the controller is waiting for an input signal Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current a reduction of the operating frequency results in reduced power consumption The slow down mode is activated by setting the bit SD in SFR PCON If the slow down mode is enabled the clock signals for the CPU and the peripheral units are reduced to 1 32 of the nominal system clock rate The controller actually enters the slow down mode after a short synchronization period max two machine cycles The slow down mode is terminated by clearing bit SD The slow down mode can be combined with the idle mode by performing the following double instruction sequence ORL PCON 00000001B preparing idle mode set bit IDLE IDLS not set ORL PCON 00110000B entering idle mode combined with the slow down mode IDLS and SD set There are two ways to terminate the combined Idle and Slow Down Mode The idle mode can be terminated by activation of any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed
154. he C508 will contain the following information in the version registers Version register 2 will be incremented with each new step of the C508 Contents of Version registers Name Address C508 Version Register 0 FCH C5y Version Register 1 FDH 08H Version Register 2 FEH 01H Semiconductor Group 4 14 SIEMENS External Bus Interface C508 Semiconductor Group 4 15 SIEMENS Reset System Clock C508 5 Reset and System Clock Operation 5 1 Hardware Reset Operation The hardware reset function incorporated in the C508 allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode is to be terminated Additional to the hardware reset which is applied externally to the C508 there are three internal reset sources the watchdog timer the oscillator watchdog and the PLL This chapter deals only with the external hardware reset The reset input is an active high input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held high for at least two machine cycles 6 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle and is repeated
155. he COINI values are only valid for capture compare outputs which are enabled for compare mode operation Semiconductor Group 6 71 SIEMENS On Chip Peripheral Components C508 Trap Enable Register The trap enable register TREN is used to enable selectively the compare outputs of the three CAPCOM channels for switching it into high or low level in the trap state as defined by the bits of the COTRAP register Additionally for a general enable of the trap function bit TRPEN must be set The TRF flag indicates when a low level is detected at the CTRAP input signal Special Function Register TRCON Address F9 4 Reset Value 004 Bit No MSB LSB 7 6 5 4 3 2 1 0 F94 TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TRENO TRCON CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function TRPEN External CTRAP trap function enable bit This bit is a general enable bit for the trap function of the CTRAP input signal TRPEN 0 External trap input CTRAP is disabled default after reset TRPEN 1 External trap input CTRAP is enabled TRF Trap flag TRF is set by hardware if the trap function is enabled TRPEN 1 and the CTRAP level becomes active low If enabled an interrupt is generated when TRF is set TRF must be reset by software TREN5 0 Trap enable control bits Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are
156. he capture compare unit CCU which is useful in motor control applications extended power saving provisions 256x8 on chip RAM 32Kx8 on chip program memory and RFI related improvements The C508 has an internal PLL and with a maximum CPU clock rate of 20 MHz it achieves a 300 ns instruction cycle time The C508 basically operates with internal and or external program memory The C508 4R contains 32Kx8 on chip program memory ROM version while the C508 4E has 32Kx8 one time programmable program memory OTP version In this documentation the term C508 refers to both versions unless otherwise noted Figure 1 1 shows the different functional units of the C508 and Figure 1 2 shows the simplified logic symbol of the C508 XRAM RAM Pot oR gt lO 1k x8 256x8 Oscillator wo 10 ebtADO ADC Port 2 1 0 16 bit did ce Capture Compare 8 Datapointers USART i Port 3 ziz VO 8 Digital Analog Inputs 10 bit Compare Unit Watchdog Timer Figure 1 1 C508 Functional Units On Chip Emulation Module I O m 4 ROM OTP 32k x 8 Semiconductor Group 1 1 SIEMENS Introduction C508 Listed below is a summary of the main features of the C508 Fully compatible to standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers 10 to 20 MHz internal CPU clock using built in PLL with a factor of 2 external clock of 5 10 MHz at 50 duty cycle 300 ns instructio
157. he software adaptively determines the transition of the output signal It is commonly used when output signals are not related to a constant signal period as in a standard PWM Generation but must be controlled very precisely with high resolution and without jitter In compare mode 1 both transitions of a signal can be controlled Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity If compare mode 1 is enabled and the software writes to the appropriate output latch at the port the new value will not appear at the output pin until the next compare match occurs Thus one can choose whether the output signal is to make a new transition 1 to 0 or 0 to 1 depending on the actual pin level or should keep its old value at the time the timer 2 count matches the stored compare value Figure 6 19 and Figure 6 20 show functional diagrams of the timer compare register port latch configuration in compare mode 1 In this function the port latch consists of two separate latches The upper latch which acts as a shadow latch can be written under software control but its value will only be transferred to the output latch and thus to the port pin in response to a compare match Note that the double latch structure is transparent as long as the internal compare signal is active While the compare signal is active a write operation to the port will then change both latches This may become important whe
158. hip Peripheral Components C508 6 3 4 1 Control Register BCON The BCON register controls the selection of multi channel PWM modes It also contains the block commutation interrupt enable and status bit flag Special Function Register BCON Address D7 y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D74 B amp MF PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCON Bit Function BCMP In multi channel PWM mode Machine polarity If BCMP is set and multi channel PWM mode is selected PWM1 0 0 0 all enabled compare outputs COUTx and CCx are switched to the compare timer 2 output signal during their active phase If BCMP is cleared only the COUTx outputs are switched to the compare timer 2 output signal during the active phase in multi channel PWM mode CMSELx3 must be set for that functionality BCEM In block commutation mode Error mode select bit If BCEM is set in block commutation mode in rotate right or rotate left mode additionally a wrong follower condition causes the setting of BCERR if EBCE is set PWM1 Multi channel PWM mode selection PWMO These bits select the operating mode of the multi channel PWM modes PWM1 PWMO Function 0 0 Block commutation mode for hall sensor inputs 0 1 4 phase multi channel PWM mode 1 0 5 phase multi channel PWM mode 1 1 6 phase multi channel PWM mode EBCE Enable interrupt of block commutation mode error
159. hold it high low for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set see Figure 7 7 The external interrupt request flags will automatically be cleared by the CPU when the service routine is called Semiconductor Group 7 26 SIEMENS Interrupt System C508 a Level Activated Interrupt Low Level Threshold P3 x INTX gt 1 Machine Cycle b Transition Activated Interrupt High Level Threshold e g P3 x INTx Low Level Threshold 1 Machine Cycle 1 Machine Cycle MCTO1921 Transition to be detected Figure 7 7 External Interrupt Detection 7 6 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is al
160. imer 1 Resolution Period Resolution Period Input Clock 2fosc 50 ns 100ns 3 28 ms 50 ns 200 ns 6 55 ms fosc 100 ns 200 ns 6 55 ms 100 ns 400 ns 13 11 ms fosc 2 200 ns 400 ns 13 11 ms 200 ns 800 ns 26 21 ms fosc 4 400 ns 800 ns 26 21 ms 400 ns 1 6 us 52 43 ms fosc 8 800 ns 1 6 us 52 43 ms 800 ns 3 2 us 104 86 ms fosc 16 1 6 us 3 2 us 104 86 ms 1 6 us 6 4 us 209 71 ms fosc 32 3 2 us 6 4 us 209 72 ms 3 2 us 12 8 us 419 42 ms fosc 64 6 4 us 12 8 us 419 43 ms 6 4 us 25 6 us 838 85 ms Compare timer 1 period and duty cycle values can be calculated using the formulas given below Following abbreviations are used pv period value stored in the period registers CCPH CCPL ov Offset value stored in the offset registers CTTOFH CT1OFL cv compare value stored in the capture compare registers CCHx CCLx Operating Mode 0 Period value pv 1 Duty cycle of CC puts 1 a 100 uty cycle o x outputs TUNE x o Duty cycle of COUTx outputs cur za x 100 96 pv 1 Operating Mode 1 Period value 2xpv cv Duty cycle of CCx outputs x 100 Duty cycle of COUTx outputs cu z x 100 Semiconductor Group 6 52 SIEMENS On Chip Peripheral Components C508 6 3 2 5 Burst Mode of CAPCOM COMP Unit In the burst mode both units of the CCU are combined in a way that the CAPCOM outputs COUTx or CCx and COUTx controlled by bit BCMP in SFR BCON are modul
161. imer Counter 2 with Additional Compare Capture Reload 6 23 p 2 2 1 Timer 2 BegdlslelS centrico enc eO ie OPE Ra rp o oc a 6 25 622 2 Timer2 Operation 2260448 sereni SAXA iC REA ERE RRA E DE RAN AMOR 6 30 6 2 2 3 Compare Function of Registers CRC T2CC1to T2CC3 uus 6 32 6 2 2 4 Using Interrupts in Combination with the Compare Function 6 38 G2 i229 Capture FUNCION ita tia rie la id ede petet ubi Det Gang Nt qm eos deu 6 40 6 3 Capture Compare Unit CCU ee ees 6 43 6 3 1 General Capture Compare Unit Operation cece ees 6 44 6 3 2 CAPCOM Unit Operation 2n eere PIU aries 6 46 6 3 2 1 CAPCOM Unit Clocking Scheme ooooccccccocoo ees 6 46 6 3 2 2 CAPCOM Unit Operating Mode O ocoooccccccor ee 6 47 6 3 2 3 CAPCOM Unit Operating Mode 1 ocoooccccnconro ee 6 50 6 3 2 4 CAPCOM Unit Timing Relationships 0 2 cee eee 6 51 6 3 2 5 Burst Mode of CAPCOM COMP Unit 000 6 53 6 3 2 6 CAPCOM Unit in Capture Mode 1 ee 6 54 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode 6 55 6 3 2 8 CAPCOM Registers 5 aue et cst Do om ertt wa ia b aet Ee s 6 57 6 3 3 Compare COMP Unit Operation oooooccoccoococn ee 6 74 6 33 11 COMFP HRGOISIBIS rara ira e 6 75 6 3 4 Combined Multi Channel PWM Modes ococooccccccco een 6 80 6 3 4 1 Control Register BOON esses oeeem erm ee E DPPRRGE
162. in configuration of the C508 in the P SDIP 64 2 package P0 0 ADO O 1 Vob P0 1 AD1 0 2 Vss P0 2 AD2 C 3 P2 0 A8 P0 3 AD3 C 4 P2 1 A9 P0 4 AD4 5 P2 2 A10 P0 5 AD5 O 6 P2 3 A11 P0 6 AD6 O 7 P2 4 A12 P0 7 AD7 O 8 P2 5 A13 RESET L P2 6 A14 EAU P2 7 A15 Vopa O PSEN Vssa Lj ALE P4 0 ANO H Vpp P4 1 AN1LJ Vss P4 2 AN2 C XTAL1 P4 3 AN3 C XTAL2 P4 4 AN4 C P3 7 RD P4 5 AN5 C P3 6 WR P4 6 AN6 P3 5 T1 P4 7 AN7 E P3 4 TO VAREF C P3 3 INT1 VAGND C P3 2 INTO P5 7 INT7 L P3 1 TxD P5 6 INT8L P3 0 RxD P5 5 INT9 C P1 0 COUT3 P5 4 INT2 C P1 1 CTRAP P5 3 12CC3 INT6 C P1 2 CCO P5 2 T2CC2 INT5L P1 3 COUTO P5 1 T2CC1 INT4L P1 4 CC1 P5 0 T2CCO INT3 C P1 5 COUT1 VppL P1 6 CC2 Vss Ol P1 7 COUT2 Figure 1 4 Pin Configuration for P SDIP 64 2 Package Top View Semiconductor Group 1 5 SIEMENS Introduction C508 1 2 Pin Definitions and Functions This section describes all external signals of the C508 with its function Table 1 1 Pin Definitions and Functions Symbol Pin Numbers P MQFP 64 P SDIP 64 1 0 Function P1 0 P1 7 25 32 33 40 32 40 31 39 30 38 29 37 28 36 27 35 26 34 25 33 I O Port 1 is an 8 bit quasi bidirectional port with internal pull up transistors Port 1 pins can be used for digital input output Port 1 pins that have 1 s written to them are pulled high by the internal pull up transistors and in
163. ing offset and linearity calibration cycles are executed see also section 6 5 5 At the end of the calibration time the BSY bit is reset and the IADC bit in SFR IRCON is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is written into the ADDAT registers Figure 6 52 shows how an A D conversion is embedded into the microcontroller cycle scheme using the relation 6 x t y 1 instruction cycle It also shows the behaviour of the busy flag BSY and the interrupt flag IADC during an A D conversion Prescaler Selection Write result cycle MOV ADDATL 0 1 instruction cycle MOV A ADDATL co 2 3 4 5 7 ai se o e Ts e pax T2 Ts Taro Les er es se 67 08 i i i 1 1 1 Start of next conversion i i i I i i l in continuous mode T A l l l Start of A D A D Conversion Cycle Write i conversion cycle i ADDAT BSY Bit a a re eg a Cont conv l l I l I 1 l T Single conv IADC Bit l CON IS A E EE i i First instr of an interrupt routine Figure 6 52 A D Conversion Timing in Relation to Processor Cycles Depending on the selected prescaler ratio see Figure 6 50 three different relationships between machine cycles and A D conversion are possible The A D conversion is started when SFR ADDATL is written with dummy data This write operation may take one or two machine cycles In Figure 6 5
164. input the port bit stored in the bit latch must contain a one 1 that means for Figure 6 2 Q 0 which turns off the output driver FET n1 Then for ports 1 to 5 except port 4 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current J or J For this reason these ports are called quasi bidirectional Read Latch Internal Pull Up Arrangement Int Bus Write to Latch Read Pin Figure 6 2 Basic Output Driver Circuit of Ports 1 2 3 and 5 Semiconductor Group 6 4 SIEMENS On Chip Peripheral Components C508 6 1 2 1 Port 0 Circuitry Port 0 in contrast to ports 1 to 4 is considered as true bidirectional because the port 0 pins float when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see Figure 6 3 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port O is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data Voo Read Latch Int Bus Write to Latch Read Pin Figure 6
165. ir default reset states before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C508 the oscillator watchdog unit avoids this situation because its RC oscillator starts working within a very short start up time typ less than 2 microseconds after power on The on chip oscillator which feeds the PLL has not started yet and thus the PLL remains unlocked As long as the PLL is not locked the watchdog uses the RC oscillator output as the clock source for the chip This allows correct resetting of the part and brings also all ports to the defined state see Figure 5 2 Il The exception is port 1 except P1 1 which is used as compare capture outputs These pins will be set to their default levels as soon as the external reset is active This is illustrated further in Figure 5 3 Under worst case conditions fast Vpp rise time e g 1us measured from V pp 4 25 V up to stable port condition the delay between power on and the correct port reset state is Typ 18us Max 34us The RC oscillator will already run at a Vpp below 4 25V lower specification limit Therefore
166. ircuitry 6 9 Memory organization 3 1 Mixed digital analog vO pins eS ETI Data memory o o oioi 3 2 Multifunctional digital VO pins 6 9 General purpose registers 3 2 Output input sample WING aceon a pela Memory map ooo 3 1 Read modify write operation 6 14 Program Memory ooo 3 2 Types and structures T VP 6 1 NEC estes nunc mate tan clad xe 3 17 eee aa o MI E E A 3 17 O ee a onte uat edt 2o TA coii eu 3 17 AI pas 2 Standard I O port circuitry 6 3 6 4 Power down mode O P ear ed 3 17 by software o on 9 6 9 8 Power saving modes 9 1 9 8 Oscillator operation 5 7 5 9 Control registers 9 1 9 2 External clock source 5 9 Idle mode 2 9 3 9 4 On chip oscillator circuitry 5 9 Slow down mode 9 5 Recommended oscillator circuit 5 8 Software power down mode 9 6 9 8 Oscillator watchdog 8 6 8 8 Entry procedure 9 6 Block diagram E EG 8 7 Exit wake up procedure OEA 9 7 OTP memory esses 10 1 10 12 State of piNS x 5 cos oer nunnana 9 8 Access of Version Bytes 10 12 Protected ROM verify timing 4 11 Basic Mode Selection 10 6 PSEN signal 2000005 4 3 Pin Configuration 10 1 PSW e oct tata Gane eae 2 3 3 12 3 16 Program read operation 10 8 PWMO o 3 17 OV E E nnn 3 16 PW
167. is advisable in the above case Then the compare signal is already inactive and any write access to the port latch just changes the contents of the shadow latch Please note that for T2CC1 to T2CC3 registers an interrupt is always requested when the compare signal goes active Semiconductor Group 6 38 SIEMENS On Chip Peripheral Components C508 The second configuration which should be noted is when compare function is combined with negative transition activated interrupts If the port latch of port P5 0 contains a 1 the interrupt request flags IEXS will immediately be set after enabling the compare mode for the CRC register The reason is that first the external interrupt input is controlled by the pin s level When the compare option is enabled the interrupt logic input is switched to the internal compare signal which carries a low level when no true comparison is detected So the interrupt logic sees a 1 to 0 edge and sets the interrupt request flag An unintentional generation of an interrupt during compare initialization can be prevented If the request flag is cleared by software after the compare is activated and before the external interrupt is enabled Semiconductor Group 6 39 SIEMENS On Chip Peripheral Components C508 6 2 2 5 Capture Function Each of the compare capture registers T2CC1 to T2CC3 and the CRC register can be used to latch the current 16 bit value of the timer 2 registers TL2 and TH2 Two different mo
168. is disabled If EX8 1 external interrupt 8 is enabled EX7 External interrupt 7 enable If EX7 0 external interrupt 7 is disabled If EX7 1 external interrupt 7 is enabled Semiconductor Group 7 11 SIEMENS Interrupt System C508 7 2 2 Interrupt Request Flags The request flags for the different interrupt sources are located in several special function registers This section describes the locations and meanings of these interrupt request flags in detail Special Function Register TCON Address 88 Reset Value 00y MSB LSB Bit No 8Fy 8Ey 8Dy 8Cy 8By 8Ay 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON i The shaded bits are not used for interrupt control Bit Function TF1 Timer 1 overflow flag Set by hardware on timer counter 1 overflow Cleared by hardware when processor vectors to interrupt routine TFO Timer 0 overflow flag Set by hardware on timer counter 0 overflow Cleared by hardware when processor vectors to interrupt routine IE1 External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when processor vectors to interrupt routine IT1 External interrupt 1 level edge trigger control flag If IT1 0 low level triggered external interrupt 1 is selected If IT1 2 1 falling edge triggered external interrupt 1 is selected IEO External interrupt O request flag Set by hardware when externa
169. ity It must be noted however that the watchdog timer is halted during the idle mode and power down mode of the processor see section Power Saving Modes It is not possible to use the idle mode in combination with the watchdog timer function Therefore even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally 8 1 4 Refreshing the Watchdog Timer At the same time the watchdog timer is started the 7 bit register WDTH is preset by the contents of WDTREL 0 to WDTREL 6 Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT IENO 6 and by the next instruction setting SWDT IEN1 6 Bit WDT will automatically be cleared during the second machine cycle after having been set For this reason setting SWDT bit has to be a one cycle instruction e g SETB SWDT This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog The reload register WDTREL can be written to at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software Semiconductor Group 8 4 SIEMENS Fail Save Mechanisms C508 8 1 5 Watchdog Reset and Watchdog Status F
170. ization C508 3 4 Program Memory Code Space The C508 4R has 32 Kbytes of read only program memory ROM while the C508 4E provides 32Kbytes of OTP program memory The program memory can be externally expanded up to 64 Kbytes If the EA pin is held high the C508 4R executes program code out of the internal ROM unless the program counter address exceeds 7FFF 1 Address locations 8000y through FFFFy are then fetched from the external program memory If the EA pin is held low the C508 fetches all instructions from the external program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit general purpose registers occupy locations 0 through 1Fy in the lower RAM area The next 16 bytes locations 20y through 2Fy contain 128 directly
171. l registers bit STE2 is reset by hardware When the compare timer 2 period and compare registers are initialized after reset bit STE2 must also be set to enable the shadow latch transfer when compare timer 2 is started the first time Note Read operations with the compare timer 2 period and compare registers always access the shadow registers and not the real registers Semiconductor Group 6 75 SIEMENS On Chip Peripheral Components C508 Compare Timer 2 Control Register The 10 bit compare timer 2 is controlled by the bits of the CT2CON register With this register the count mode the timer input clock rate and the compare timer reset function is controlled Special Function Register CT2CON Address C1 y Reset Value 00010000g Bit No MSB LSB 6 5 4 3 2 1 0 Ciy CT2P ECT2O STE2 CT2RES CT2R CLK2 CLK1 CLKO CT2CON Bit Function CT2P Compare timer 2 period flag When the compare timer 2 value matches with the compare timer 2 period register value bit CT2P is set If the compare timer 2 interrupt is enabled the setting of CT2P will generate a compare timer 2 interrupt Bit CT2P must be cleared by software ECT2O Enable compare timer 2 output When ECT20 is cleared and compare timer 2 is running output COUTS is put into the logic state as defined by bit COUTSI which is located in SFR COINI 6 When ECT20 is set and compare timer 2 is running the compare timer 2 output COUTS is e
172. l interrupt O edge is detected Cleared by hardware when processor vectors to interrupt routine ITO External interrupt O level edge trigger control flag If ITO 2 O low level triggered external interrupt O is selected If ITO 1 falling edge triggered external interrupt O is selected The external interrupts 0 and 1 P3 2 INTO and P3 3 INT1 can each be either level activated or negative transition activated depending on bits ITO and IT1 in register TCON The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware Semiconductor Group 7 12 SIEMEN Interrupt System S C508 The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to Special Function Register T2CON Address C8y Reset Value 0000X0X0p MSB LSB Bit No CFy CEy CDy CCH CBy CAy C94 C84 C84 T2PS IBFR I2FR T2R T2CM T2l T2CON E The
173. lag If the software fails to refresh the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCy The duration of the reset signal then depends on the prescaler selection either 8 cycles or 128 cycles This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS watchdog timer status bit 6 in SFR IPO is set Figure 8 2 shows a block diagram of all reset requests in the C508 and the function of the watchdog status flags The WDTS flag is a flip flop which is set by a watchdog timer reset and cleared by an external HW reset Bit WDTS allows the software to examine from which source the reset was activated The watchdog timer status flag can also be cleared by software OWD Reset Request WDT Reset Request Sel IPO A9 Synchro ws wor NN NN NN O NN nization Clear Internal Reset RESET External HW Reset Request Internal Bus Figure 8 2 Watchdog Timer Status Flags and Reset Requests Semiconductor Group 8 5 SIEMENS Fail Save Mechanisms C508 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into res
174. le control XMAPO 0 The access to XRAM is enabled XMAPO 1 The access to XRAM is disabled default after reset All MOVX accesses are performed via the externl bus Further this bit is hardware protected Reserved bits for future use Read by CPU returns undefined values When bit XMAP1 in SFR SYSCON is set during all accesses to XRAM RD and WR become active and port 0 and 2 drive the actual address data information which is read written from to XRAM This feature allows to check the internal data transfers to XRAM When port O and 2 are used for I O purposes the XMAP1 bit should not be set Otherwise the I O function of the port 0 and port 2 lines is interrupted Semiconductor Group 3 3 SIEMENS Memory Organization C508 After a reset operation bit XMAPO is set This means that the accesses to XRAM are generally disabled In this case all accesses using MOVX instructions within the address range of FCOOy to FFFFy generate external data memory bus cycles When XMAPO is cleared the access to XRAM is enabled and all accesses using MOVX instructions with an address in the range of FCOO to FFFF will access the internal XRAM Bit XMAPO is hardware protected If it is cleared once i e if internal XRAM access enabled it cannot be set by software Only a reset operation will set the XMAPO bit again This hardware protection mechanism is done by an asymmetric latch at XMAPO bit An unintentional disabling of X
175. load value of the timer and the other half when the compare register is equal to the maximum value of the timer register i e FFFFyy Please refer to Figure 6 18 where the maximum and minimum duty cycle of a compare output signal are illustrated Timer 2 is incremented with every machine clock fosc 6 thus both these spikes are approximately 150 ns long at 20 MHz operational frequency Semiconductor Group 6 34 SIEMENS On Chip Peripheral Components C508 a CCHx CCLx 0000 or CRCH CRCL maximum duty cycle Appr 1 2 Machine Cycle b CCHx CCLx FFFF y minimum duty cycle Appr 1 2 Machine Cycle Figure 6 18 Modulation Range of a PWM Signal generated with a Timer 2 CCx Register Combination in Compare Mode 0 The following example shows how to calculate the modulation range for a PWM signal To calculate with reasonable numbers a reduction of the resolution to 8 bit is used Otherwise for the maximum resolution of 16 bit the modulation range would be so severely limited that it would be negligible Example Case Timer 2 in auto reload mode Contents of reload register CRC FFO0y Restriction of modulation range 1 256 x 2 x 100 0 195 This leads to a variation of the duty cycle from 0 195 to 99 805 for a timer 2 CCx register configuration when 8 of 16 bits are used Semiconductor Group 6 35 SIEMENS On Chip Peripheral Components C508 6 2 2 3 3 Compare Mode 1 In compare mode 1 t
176. ludes calibration Write result phase twp used for writing the conversion result into the ADDAT registers The total A D conversion time is defined by tapcc which is the sum of the two phase times tg and tco The duration of the three phases of an A D conversion is specified by their corresponding timing parameter as shown in Figure 6 51 Start of an Result is written AD conversion into ADDAT BSY Bit Conversion Phase Write tco r Result twR Phase tapcc A D Conversion Time Cycle Time twr tin tapcc ts tco PS Prescaler value Prescaler Ratio ts tco tapcc PS 32 64 x tin 320 x tin 384 x tin 16 32 X tin 160 x tin 192 x tin 8 16 x tin 80 x tin 96 X tin 4 8 X tin 40 x tin 48 X tin Figure 6 51 A D Conversion Timing Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With beginning of the sample phase the BSY bit in SFR ADCONO is set Semiconductor Group 6 122 SIEMENS On Chip Peripheral Components C508 Conversion Time tco During the conversion time the analog voltage is converted into a 10 bit digital value using the successive approximation technique with a binary weighted capacitor network During an A D conversion also a calibration takes place During this calibration alternat
177. lue 01XXX000p Bit No MSB LSB 7 6 5 4 3 2 1 0 D8H BD CLK BSY ADM MX2 MX1 MXO ADCONO DCH ADCL1 ADCLO MX2 MX1 MXO ADCON1 The shaded bits are not used for A D converter control Bit Function Reserved bits for future use BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D conversion mode When set a continuous A D conversion is selected If cleared during a running A D conversion the conversion is stopped at its end MX2 MXO A D converter input channel select bits Bits MX2 0 can be written or read either in ADCONO or ADCON1 The channel selection done by writing to ADCON 1 0 overwrites the selection in ADCON 0 1 when ADCON 1 0 is written after ADCON 0 1 The analog inputs are selected according the following table MX2 MX1 MXO Selected Analog Input 0 0 0 P4 0 ANO 0 0 1 P4 1 AN1 0 1 0 P4 2 AN2 0 1 1 P4 3 AN3 1 0 0 P4 4 ANA 1 0 1 P4 5 AN5 1 1 0 P4 6 ANG 1 1 1 P4 7 AN7 Semiconductor Group 6 118 SIEMENS On Chip Peripheral Components C508 Bit Function ADCL1 A D converter clock prescaler selection ADCLO ADCL1 and ADCLO select the prescaler ratio for the A D conversion clock fapc Depending on the clock rate fosc of the C508 fapc must be adjusted in a way that the resulting conve
178. lue TL1 is not used THx 7 0 Timer counter 0 1 high register x 0 1 Operating Mode Description 0 THx holds the 8 bit timer counter value THx holds the higher 8 bit part of the 16 bit timer counter value THx holds the 8 bit reload value 1 2 3 THO holds the 8 bit timer value TH1 is not used Semiconductor Group 6 16 SIEMENS On Chip Peripheral Components C508 Special Function Register TCON Address 88 Reset Value 00y Special Function Register IENO Address A8jy Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8Dy 8Cy 8By 8A4y 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON AFy AEn ADH ACH ABH AAH A9H A8H A8H EA WDT ET2 ESO ET1 EX1 ETO EXO IENO The shaded bits are not used for controlling timer counter 0 and 1 Bit Function TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TRO Timer 0 run control bit Set cleared by software to turn timer counter 0 ON OFF ET1 Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled ETO Timer O overflow interru
179. m S C508 Special Function Register SCON Address 984 Reset Value 00y MSB LSB Bit No 9Fy 9Ey 9Dy 9Cy 9By 9AHy 99H 98H 984 SMO SM1 SM2 REN TB8 RB8 TI RI SCON E The shaded bits are not used for interrupt control Bit Function TI Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission Must be cleared by software RI Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received Must be cleared by software The serial interface interrupt is generated by a logical OR of flag RI and TI in SFR SCON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the corresonding bit will have to be cleared by software The interrupt request flags of the CAPCOM capture compare match interrupt is located in the register CCIR All CAPCOM capture compare match interrupt flags are set by hardware and must be cleared by software A capture compare match interrupt is generated with the setting of a CCXR bit x 0 2 if the corresponding enable bits are set These enable bits are contained in register CCIE The compare timer 1 interrupt request flags CT1FP or CT1FC are also located in the register CCIR Each fla
180. m counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the PO P2 SFR remains unchanged Being an address data bus port O uses a pullup FET as shown in Figure 6 3 When a 16 bit address is used port 2 uses the additional strong pullups p1 Figure 6 5a to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Read Latch Control Adar DD Internal Pull Up Arrangement Int Bus Write to Latch Read Pin Figure 6 5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses port O can be used for I O functions Semiconductor Group 6 7 SIEMENS On Chip Peripheral Components C508 Control Input Data Read Pin Figure 6 5a Port 2 pull up arrangement Port 2 in I O function works similar to the Type B port driver circuitry section 6 1 3 1 whereas in address output function it works similar to Port O circuitry Semiconductor Group 6 8 SIEMENS On Chip Peripheral Components C508 6 1 3 Detailed Output Driver Circuitry In fact the pullups mentioned before and included in Figure 6 2 Figure 6 4 and Figure 6 5 are pullup arrangements The differences of the port types available in the C508 are described in the next sections 6 1 3 1 Type B Port Driver Circuitry Figure 6 6 shows the output drive
181. mal I O pin Compare outputs on pins CCx and COUTx enabled Capture mode enabled signal transitions at CCx do not generate a capture event COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input and a rising edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input and a falling edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input Rising and falling edge at CCx transfer the compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Note only CCO COUTO can be analog inputs if not selected as compare output In compare mode the two output signals of a CAPCOM channel can be enabled selectively In capture mode the type of signal transition which will generate a capture event can be chosen Semiconductor Group 6 64 SIEMENS On Chip Peripheral Components C508 Capture Compare Registers of CAPCOM Unit The capture compare registers are 16 bit registers organized as two 8 bit byte wide registers Each of the three CAPCOM channels has one capture compare register In compare mode they hold a compare value which typically defines the duty cycle of the output sig
182. maximum power reduction can be achieved This state is also the test condition for the idle mode pp Thus the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time when the idle mode was activated If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on This especially applies to the serial interface in case it cannot finish reception or transmission during normal operation The control signals ALE and PSEN are held at logic high levels As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode Semiconductor Group 9 3 SIEMENS Power Saving Modes C508 The idle mode is entered by two
183. mer counter with a divide by 32 prescaler Figure 6 9 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all 0 s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in Figure 6 9 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 Interrupt Gate P3 2 INTO Figure 6 9 Timer Counter 0 Mode 0 13 Bit Timer Counter Semiconductor Group 6 19 SIEMENS On Chip Peripheral Components C508 6 2 1 3 Mode 1 Mode 1 is the same as mode O0 except that the timer register is running with all 16 bits Mode 1 is shown in Figure 6 10 TFO Interrupt P3 4 TO Pin Gate P3 2 INTO Figure 6 10 Timer Counter 0 Mode 1 16 Bit Timer
184. mode operation by writing the corresponding bit combination into the CMSELO CMSEL1 registers the compare output is switched into push pull mode and starts driving an initial logic level as defined by the bits of the COINI register Bit COUTXI controls an inverter for the COMP unit output signal when it is wired to the CCx and COUTx outputs in burst or multi channel PWM mode COUTSI defines the initial logic level at COUTS before compare timer 2 is started as well as the logic state when COUTS is disabled by setting bit ECT2O in SFR CT2CON see Figure 6 32 The COINI register should be written prior to the starting of the compare timers Any write operation to the COINI register when the compare timer is running will affect the compare output signals immediately and drive the logic value as defined by the bits of COINI A PWM output signal of the C508 basically consists of two phases an inactive phase and an active phase The inactive phase of a PWM output signal is defined by the bit in the register COINI A 1 in a bit location 0 to 5 of COINI defines the high level of the corresponding PWM compare output signal as its inactive phase With a 0 in a bit location of COINI a low level is selected as inactive phase Special Function Register COINI Address E25 Reset Value FFy Bit No MSB LSB 7 6 5 4 3 2 1 0 E2H COUT3I COUTXI COUT2I CC2l COUT1I CC1l COUTOI CCOI COINI CAPCOM CAPCOM CAPCOM Chann
185. ms the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if set jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag the ALU can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Additionally to the CPU functionality of the C501 8051 standard microcontroller the C508 contains 8 datapointers For complex applications with peripherals located in the external data memory space or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages Accumulato
186. n cycle time for P MQFP 64 1 20 MHz CPU clock 375 ns instruction cycle time for P SDIP 64 2 16 MHz CPU clock 32 Kbyte on chip ROM OTP with optional ROM protection 256 byte on chip RAM 1024 byte on chip XRAM Five 8 bit ports Port 4 with pure analog digital input channels Port 1 and 2 with enhanced current sinking capabilities of 10 mA total max of 100mA Three 16 bit timers counters Timer 0 1 C501 compatible Timer 2 with 4 channels for 16 bit capture compare operation Capture compare unit for PWM signal generation 3 channel 16 bit capture compare unit j channel 10 bit compare unit Full duplex serial interface with programmable baudrate generator USART 8 channel 10 bit A D Converter 19 interrupt vectors with four priority levels On chip emulation support logic Enhanced Hooks Technology Programmable 15 bit Watchdog Timer Oscillator Watchdog Fast Power On Reset Power Saving Modes Slow down mode Idle mode can be combined with slow down mode Software power down mode with wake up capability through INTO or INT7 P MQFP 64 1 P SDIP 64 2 packages Temperature ranges SAB C508 Ta 0to 70 C SAF C508 Ta 40 to 85 C Semiconductor Group 1 2 SIEMENS Introduction C508 Voo Vss Vopa V Port 0 SSA 8 bit Digital I O VAREF VAGND Port 1 8 bit Digital I O XTAL1 Bono XTAL2 8 bit Digital I O RESET Port3 8 bit Digital I O EA ALE Port 4 PSEN 8 bit Digital Analo
187. n driving timer 2 with a slow external clock In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch A read modify write instruction will read the user controlled shadow latch and write the modified value back to this shadow latch A standard read instruction will as usual read the pin of the corresponding compare output Semiconductor Group 6 36 SIEMENS On Chip Peripheral Components C508 Circuit Compare Reg Shadow Latch Write to CLK Timer Register Timer Circuit Read Pin Compare Register Read Latch Port Circuit Figure 6 19 Port Latch in Compare Mode 1 Compare Register CCx Shaded function for CRC only i Compare Signal Latch il Circuit Overflow TH2 TL2 Interrupt Timer 2 P5 7 P5 3 P5 0 T26C3 T2CCO INT6 INT3 CCx stands for CRC T2CC1 to T2CC3 IEXx stands for IEX3 to IEX6 Figure 6 20 Timer 2 with Registers CCx in Compare Mode 1 Semiconductor Group 6 37 SIEMENS On Chip Peripheral Components C508 6 2 2 4 Using Interrupts in Combination with the Compare Function The compare service of registers CRC T2CC1 T2CC2 and T2CC3 are assigned to alternate output functions at port pins P5 0 to P5 3 Another option of these pins is that they can be used as external interrupt inputs However when using the port lines as compare outp
188. n order to generate correct dead times for PWM signals the offset value stored in CT1OFH CT1OFL must be lower than the values stored in the compare registers Semiconductor Group 6 62 SIEMENS On Chip Peripheral Components C508 Capture Compare Channel Mode Select Registers The capture compare channels of the CAPCOM unit can operate individually either in compare mode or in capture mode The CMSELO and CMSEL1 registers contain the mode select bits for the CAPCOM unit Special Function Register CMSELO Address E31 Reset Value 00y Special Function Register CMSEL1 Address E4p Reset Value 00y Bit No E3y E4y MSB LSB 7 6 5 4 3 2 1 0 CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL cMsg 9 13 12 11 10 03 02 01 00 A N N S CAPCOM CAPCOM Channel 1 Channel 0 7 6 5 4 3 2 1 0 CMSEL CMSEL CMSEL CMSEL Y A A CAPCOM Chamnel 2 Bit Function ESMC Enable software controlled multi channel PWM modes If ESMC 0 switching of the follower state in 4 5 6 phase multi channel PWM mode is controlled by compare timer 1 reaching its period value If ESMC 1 switching of the follower state in 4 5 6 phase multi channel PWM mode is controlled by bit NMCS NMCS Next multi channel PWM state Setting bit NMCS with ESMC set will select the follower state in the 4 5 6 phase multi channel PWM mode which is taken into acco
189. n the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Further the abrevation fosc refers to the external clock frequency oscillator or external input clock operation The baud rate of the serial port is controlled by two bits which are located in the special function registers as shown below Special Function Register ADCONO Address D8p Reset Value 00X00000p Special Function Register PCON Address 87g Reset Value 00y Bit No MSB LSB DFH DEH DDH DCH DBH DAH D9H D8H D8H CLK BSY ADM MX2 MX1 MXO ADCONO 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON The shaded bits are not used for controlling the baud rate Bit Function BD Baud rate generator enable When set the baud rate of serial interface is derived from the dedicated baud rate generator When cleared default after reset baud rate is derived from the timer 1 overflow rate SMOD Double baud rate When set the baud rate of serial interface in modes 1 2 3 is doubled After reset this bit is cleared Reserved bits for future use Read by CPU returns undefined values Figure 6 41 shows the configuration for the baud rate generation of the serial port Semiconductor Group 6 101 SIEMENS On Chip Peripheral Components C508 Timer 1 Overflow ADCONO 7 BD
190. n the burst mode the compare timer 2 output signal can be also switched to the CAPCOM output pins COUTO COUT1 and COUTS In these modes the polarity of the modulated output signal at COUT2 0 can be inverted by setting bit COUTXI COINI 6 6 3 3 1 COMP Registers The COMP unit has five SFRs which are listed in Table 6 8 Table 6 8 Special Function Registers of the COMP Unit Unit Symbol Description Address COMP CT2CON Compare timer 2 control register Py Compare CP2L Compare timer 2 period register low byte D2y Unit CP2H Compare timer 2 period register high byte D3y CMP2L Compare timer 2 compare register low byte D4y CMP2H Compare timer 2 compare register high byte D5H The compare timer 2 period and compare registers store a 10 bit value organized in two bytes For proper synchronization purposes these registers are not written directly Each value of a write operation to these registers is stored in shadow latches The transfer of these shadow latches into the real registers is synchronized with the compare timer 2 value 0004 and controlled by bit STE2 When the period or compare value is changed by writing the corresponding SFR the setting of bit STE2 CT2CON 5 enables the write transfer of the shadow registers into the real registers This shadow latch transfer happens when the compare timer 2 reaches the count value 000H the next time after STE2 has been set With the automatic transfer of the shadow latches to the rea
191. nabled and outputs the PWM signal of the COMP unit STE2 COMP unit shadow latch transfer enable When STE2 is set the content of the compare timer 2 period and compare latches CP2H CP2L CMP2H CMP2L is transferred to its real registers when compare timer 2 reaches the next time the period value After the shadow transfer event STE2 is reset by hardware Semiconductor Group 6 76 SIEMENS On Chip Peripheral Components C508 Bit Function CT2RES Compare timer 2 reset control CT2R Compare timer 2 run stop control These two bits controls the start stop and reset function of the compare timer 2 CT2RES is used to reset the compare timer and CT2R is used to start and stop the compare timer 2 The following table shows the functions of these two bits CT2RES CT2R Function 0 0 Compare timer 2 is stopped compare output COUT3 stays in the logic state as it is 0 1 Compare timer 2 is running If CT2R is set the first time after reset COUTS is set to the logic state as defined by bit COUTSI of SFR COINI 1 0 Compare timer 2 is stopped and reset The output COUTS is set to the logic state as defined by bit COUTSI of SFR COINI default after reset 1 1 Compare timer 2 is further running Note ECT2O must be set for COUTS signal output enable CLK2 Compare timer 2 input clock selection CLK1 The input clock for the compare timer 2 is derived from the clock rate fosc of CLKO the C508 via a p
192. nactive the ROM OTP verification mode 2 sequence is started The C508 outputs an ALE signal with a period of 12TCL and expects data bytes at port 0 The data bytes at port 0 are assigned to the ROM addresses in the following way 1 Data Byte content of internal ROM OTP address 0000H 2 Data Byte content of internal ROM OTP address 0001 y 3 Data Byte content of internal ROM OTP address 00024 16 Data Byte content of internal ROM OTP address 000FH Semiconductor Group 4 11 SIEMENS External Bus Interface C508 The C508 does not output any address information during the ROM OTP verification mode 2 The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000y and must be put onto the data bus with the falling edge of RESET With each following ALE pulse the ROM OTP address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally Between two ALE pulses the data at port 0 is latched at 6TCL after ALE rising edge and compared internally with the ROM OTP content of the actual address If a verify error is detected the error condition is stored internally After each 16th data byte the cumulated verify result pass or fail of the last 16 verify operations is output at P3 5 This means that P3 5 stays at a static level low for fail and high for pass while the next 16 bytes are checked The output of P3 5 will be updated according to the
193. nals In capture mode the actual compare timer 1 value is transferred into the capture compare registers at a capture event If CCLx CCHx is written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 00004 operating mode 1 When the capture compare registers are read always the real registers are accessed because of capture mode Special Function Registers CCLO CCHO Addresses F2 4 F3 4 Reset Value 00H Special Function Registers CCL1 CCH1 Addresses F4y F5 Reset Value 00y Special Function Registers CCL2 CCH2 Addresses F6 4 F7 4 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 F2H 7 6 5 4 PO 2 A LSB CCLO F3H MSB 6 5 4 a 2 1 0 CCHO F4y 7 6 25 4 3 2 E LSB CCL1 FSH MSB 6 25 4 m 2 1 0 CCH1 F6H a 6 5 4 3 2 1 LSB CCL2 F7y MSB 6 5 4 3 2 1 0 CCH2 Bit Function CCLx 7 0 Capture compare value low byte x 0 2 The 8 bit value in the CCLx register is the low part of the 16 bit capture compare value of channel x CCHx 7 0 Capture compare value high byte x 0 2 The 8 bit value in the CCHx register is the low part of the 16 bit capture compare value of channel x Semiconductor Group 6 65 SIEMENS On Chip Peripheral Components C508 Capture Compare Interrupt R
194. ng edge control flag If IBFR 0 the external interrupt 9 is activated by a negative edge transition at P5 5 INT9 If IBFR 1 the external interrupt 9 is activated by a positive edge transition at P5 5 INT9 IEX8 External interrupt 8 edge flag Set by hardware when external interrupt edge was detected Cleared by hardware when processor vectors to the interrupt routine I8FR External interrupt 8 rising falling edge control flag If IBFR 0 the external interrupt 8 is activated by a negative edge transition at P5 6 INT8 If IBFR 2 1 the external interrupt 8 is activated by a positive edge transition at P5 6 INT8 IEX7 External interrupt 7 edge flag Set by hardware when external interrupt edge was detected Cleared by hardware when processor vectors to the interrupt routine I7FR External interrupt 7 rising falling edge control flag If I7FR 0 the external interrupt 7 is activated by a negative edge transition at P5 7 INT7 If I7FR 2 1 the external interrupt 7 is activated by a positive edge transition at P5 7 INT7 The external interrupt 7 INT7 8 INT8 and 9 INT9 can be either positive or negative transition activated depending on bits I7FR I8FR and I9FR in register EINT The flag that actually generates these interrupts are bits IEX7 IEX8 and IEX9 in the same register EINT They are cleared by hardware when the respective service routine is vectored to Semiconductor Group 7 15 SIEMEN Interrupt Syste
195. nputs As inputs port 2 pins being externally pulled low will source current ji in the DC characteristics because of the internal pullup transistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX QDPTR In this application it uses strong internal pullup transistors when issuing 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register and uses only the internal pullup transistors As O functions port 2 pins also have LED drive capability of up to 10mA sinking current per pin XTAL1 42 50 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed XTAL2 41 49 O XTAL2 Output of the inverting oscillator amplifier Input O Output Semiconductor Group 1 8 SIEMENS Introduction C508 Symbol Pin Numbers l O Function P MQFP 64 P SDIP 64 P4 0 P4 7 5 12 18 20 Port 4 is an 8 bit uni directional input port to the A D converter Port pins can be used for digital input if voltage levels simultaneously meet the spe
196. ns below 4 When the PLL detects a missing input clock signal it releases the lock signal As a result an internal reset will be active until the PLL is locked again This may occur if the input clock is unstable or fails completely for example due to a broken crystal In this case an oscillator watchdog reset will also occur When software power down mode is entered the PLL is powered down together with the RC oscillator and the on chip oscillator In this mode the PLL is marked unlocked However no internal resets will be generated Semiconductor Group 5 7 SIEMENS Reset System Clock C508 5 6 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip These signals define the internal phases states and machine cycles Figure 5 6 shows the recommended oscillator circuit Crystal Oscillator Mode Driving from External Source External Oscillator Signal XTAL1 hist XTAL2 C 20pF 10pF for crystal operation incl StrayCapacitance Figure 5 6 Recommended Oscillator Circuit In this application the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in Figure 5 7 It is operated in its fundamental r
197. o state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If it is used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 Z the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 10 SIEMENS On Chip Peripheral Components C508 6 1 3 2 Type D Port Driver Circuitry The driver and control structure of the port pins used for compare output functions have a port structure which allows a true push pull output driving capability Type D This output driver characteristics is only enabled used when the corresponding port lines are used as compare outputs The push pull port str
198. odes is selected 5 Phase Multi Channel PWM Mode Rotate Left Mode BCM1 0 1 0 with COINI XX111111p Setting bit NMCS by Bit 1 software NMCS 0 CCO 1 1 COUT1 az E Go o L mr active i i phase COUTO l ex courte a State No E l l oa Static level during active phase Compare timer 2 modulation at CCx and COUTx outputs during active phase at CCx and COUTx output Figure 6 40 Software Controlled State Switching in 5 Phase Multi Channel PWM Mode Semiconductor Group 6 96 SIEMENS On Chip Peripheral Components C508 Static level during active phase When bit ESMC in SFR CMSEL1 is set static active or passive output levels during the active phase of a multi phase PWM timing are generated when the following conditions are met The 16 bit offset register of compare timer 1 must be 0000y CT1OFH CT1OFL 0014 static active compare values 0000 Static passive compare values gt period value The bits CMSELx3 x 0 2 in the SFRs CMSELO CMSEL1 must be 0 The logic state of the inactive active phases at the CCx and COUTx outputs is defined by the bits in SFR COINI Compare timer 2 controlled active phase at COUTx When bit ESMC in SFR CMSEL1 is set compare timer 2 controlled output levels at COUTx during the active phase of a multi pole PWM timing are generated when the following conditions are met The 16 bit offset register of
199. of BCERR see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 the setting of BCERR will generate a CCU emergency interrupt BCERR must be reset by software Semiconductor Group 7 19 SIEMENS Interrupt System C508 Special Function Register TRCON Address FF Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 FFy TRPEN TRF TRENS TRENA4 TRENS TREN2 TREN1 TRENO TRCON llc aD LL 068 S20 SSS CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 EN The shaded bits are not used for interrupt control Bit Function TRF Trap flag TRF is set by hardware if the trap function is enabled TRPEN 1 and the CTRAP level becomes active low If enabled an interrupt is generated when TRF is set TRF must be reset by software Special Function Register CT1CON Address El y Reset Value 00010000g Bit No MSB LSB 7 6 5 4 3 2 1 0 Ely CIM ETRP STE1 CT1RES CT1R CLK2 CLK1 CLKO CT1CON Bit Function ETRP CCU emergency trap interrupt enable If ETRP 1 the emergency interrupt for the CCU trap signal is enabled Semiconductor Group 7 20 SIEMENS Interrupt System C508 7 2 3 Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in Table 7 1 in the next section Special Func
200. oftware to enable serial reception Cleared by software to disable serial reception TB8 Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB8 Serial port receiver bit 9 In modes 2 and 3 RB8 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI Serial port transmitter interrupt flag Tl is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission TI must be cleared by software RI Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes in any serial reception exception see SM2 RI must be cleared by software Semiconductor Group 6 100 SIEMENS On Chip Peripheral Components C508 6 4 3 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating For clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results i
201. ol the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C500 MCU 1 Enhanced Hooks Technology is a trademark and patent of MetaLink Corporation licenced to Siemens Semiconductor Group 4 5 SIEMENS External Bus Interface C508 4 6 Eight Datapointers for Faster External Bus Access 4 6 1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment instruction any other pointer handling is to be handled bytewise For complex applications with peripherals located in the external data memory space or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages 4 6 2 How the eight Datapointers of the C508 are implemented Simply adding more datapointers is not suitable because of the need to keep up 10096 compatibility to the 8051 instruction set This instruction set however allows the handling of only one single 16 bit datapointer D
202. om the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to O transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bit come from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in modes 2 and 3 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and to set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time
203. only shadow latches are written The content of these latches is transferred to the real registers when compare timer count value 000 y is reached and bit STE2 of SFR CT2CON has been set When the compare CMP2H CMP2L registers are read always the shadow registers are accessed Special Function Registers CMP2L Address D4y Reset Value 00y Special Function Registers CMP2H Address D5y Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D4y 7 6 5 4 E 2 1 0 CMP2L D5y A 0 CMP2H Bit Function CMP2L 7 0 Compare value low byte for compare timer 2 The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 CMP2H 1 0 Compare value high bits for compare timer 2 The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 Reserved bits Semiconductor Group 6 79 SIEMENS On Chip Peripheral Components C508 6 3 4 Combined Multi Channel PWM Modes The CCU of the C508 has been designed to support also motor control or inverter applications which have a demand for specific multi channel PWM signal generation In these combined multi channel PWM modes the CAPCOM unit compare timer 1 and the COMP unit compare timer 2 of the C508 CCU are working together In the combined multi channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by
204. ooooooccoonooo nnn 9 1 9 1 Power Saving Mode Control Registers ww ee 9 1 9 2 dls MOS sue obe eda Coad les Le quitas dica ati disais c due A 9 3 9 3 Slow Down Mode Operation 00 cee tee 9 5 9 4 Software Power Down Mode 2 00 cee eens 9 6 9 4 1 Invoking Software Power Down Mode 1 eee eee 9 6 9 4 2 Exit from Software Power Down Mode 0 ee ee 9 7 9 5 State of Pins in Software Initiated Power Saving Modes 9 8 10 OTP Memory Operation ssclee ue el AER nh ean 10 1 Semiconductor Group 1 3 SIEMENS General Information C508 10 1 Programming Configuration sexu metesvexosteRPCIROPRITITRRERGEPSTQEEERAS 10 1 10 2 Pin COMNGUPATON sse o COE exe CR e RC SOROR eb M RO e beer d 10 2 10 3 Pin DETHAMIO T LEE 10 4 10 4 Programming Mode Selection 000 eee ro 10 6 10 4 4 Basic Programming Mode Selection 0 000 eee eee 10 6 10 42 OTP Memory Access Mode Selection llle 10 7 10 5 Program Read OTP Memory Bytes sso e eae ede geen ee aw E RS 10 8 10 6 Lock Bits Programming Head isa AA AAA 10 10 10 7 ACCESS of Version Bytes 6 4 CR ek eR EQ ee DURAS RICE RR EE REA ems 10 12 11 Index coz rose O ewe su ier d Rus 11 1 Semiconductor Group 1 4 SIEMENS Introduction C508 1 Introduction The C508 is a member of the Siemens C500 family of 8 bit microcontrollers It is fully compatible to the standard 8051 microcontroller Its features include t
205. ows the following characteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode I 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access c Use of internal XRAM or external XDATA memory The shaded areas describe the standard operation as each C5xx device without on chip XRAM behaves Semiconductor Group 3 9 3 EA 0 EA 1 Q 5 XMAP1 XMAPO XMAP1 XMAPO S 00 10 X1 00 10 X1 a MOVX DPTR a P0 P2 gt Bus a P0 P2 gt Bus a PO P2 Bus a P0 P2 gt Bus a P0 P2 gt Bus a PO P2 Bus 3 DPTR lt b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active 5 XRAM c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is address used used used used used used range DPTR a P0 P2 gt Bus a P0 P2 gt Bus a P0 P2 gt Bus a P0 P2 gt 1 0 a P0 P2 gt Bus a P0 P2 gt Bus gt RD WR Data RD WR Data SES HOPES RD WR Data Sate XRAM b RD WR b RD WR active b RD WR active b RD WR b RD WR active b RD WR active address inactive inactive range c XRAM is used c XRAM is used c ext memory c XRAM is used c XRAM is used c ext memory is used is used MOVX XPAGE a PO Bus a PO Bus a PO Bus a PO Bus a PO
206. p from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 60 SIEMENS On Chip Peripheral Components C508 Compare Timer 1 Period Registers The compare timer 1 period registers CCPH and CCPL store the 16 bit value for the compare timer 1 count period CCPH holds the high byte of the 16 bit period value and CCPL holds the low byte If CCPH CCPL is written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 00004 operating mode 1 When the compare timer 1 period registers are read always shadow latches are accessed Special Function Register CCPL Address DE Reset Value 00H Special Function Register CCPH Address DF Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 DEH 7 6 5 4 3 ie 1 LSB CCPL DFy MSB 6 5 4 3 2 1 0 CCPH Bit Function CCPL 7 0 Compare timer 1 period value low byte The 8 bit value in the CCPL register is the low byte of the 16 bit period value of compare timer 1 shadow latch CCPH 7 0 Compare timer 1 period value high byte The 8 bit value in the CCPH register is the high byte of the 16 bit period value of compare timer 1 Shadow latch Semiconductor Group 6 61 SIEMENS On Chip Peripheral Components C508 Compare Timer
207. pled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 6 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 6 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter 0 and 1 Timer counter 0 and 1 of the C508 are fully compatible with timer counter O and 1 of the C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter O is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL 1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of
208. pp is restored to its normal operating level before the power down mode is terminated The software power down mode can be left either by an active reset signal or by a low signal at one of the wake up source pins Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using either the P3 2 INTO pin or the P5 7 INT7 pin for power down mode exit starts the RC oscillator the on chip oscillator and the PLL and maintains the state of the SFRs which have been frozen when power down mode is entered Leaving power down mode should not be done before Vpp is restored to its nominal operating level 9 4 1 Invoking Software Power Down Mode The software power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the power down mode Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly freeze the chip s activity in an undesired status PCON is not a bit addressable register so the above mentioned sequence for entering the power
209. pt Control Register FBy XX000000p XRAM XPAGE Page Address Register for Extended on chip 91 4 00H XRAM and CAN Controller SYSCON System Control Register Bly XX10XX01 pg Ports PO Port 0 80y FFH P1 Port 1 90H FFy P2 Port 2 A0y FFH P3 Port 3 Boy FFH P4 Port 4 Analog Digital Input DBH P5 Port 5 F8H FFH Bit addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks This SFR is a mapped SFR For accessing this SFR bit RMAP in SFR SYSCON must be set 1 2 3 X means that the value is undefined and the location is reserved 4 5 The content of this SFR varies with the actual step of the C508 eg 01 y for the first step Semiconductor Group 3 12 SIEMENS Memory Organization C508 Table 3 2 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Serial ADCONO A D Converter Control Register 0 D8y 00X00000p Channel PCON Power Control Register 87H 00H SBUF Serial Channel Buffer Register 99H XXH SCON Serial Channel Control Register 98H 00H SRELL Serial Channel Reload Register low byte AAH D9u SRELH Serial Channel Reload Register high byte BAH XXXXXX1 1p Timer 0 TCON Timer 0 1 Control Register 88y 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8Dy 00H TLO Timer 0 Low Byte 8AH 00H TL
210. pt enable If ETO 0 the timer 0 interrupt is disabled Semiconductor Group 6 17 SIEMENS On Chip Peripheral Components C508 Special Function Register TMOD Address 89y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 894 Gate C T Mt MO Gate C T Mi MO TMOD MA JF Timer 1 Control Timer 0 Control Bit Function GATE Gating control When set timer counter x is enabled only while INT x pin is high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set GT Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Mode select bits MO M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an 8 bit timer counter controlled by the standard timer O control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 6 18 SIEMENS On Chip Peripheral Components C508 6 2 1 2 Mode 0 Putting either timer counter 0 1 into mode 0 configures it as an 8 bit ti
211. r ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 3 SIEMENS Fundamental Structure C508 Special Function Register PSW Address DO Reset Value 00y Bit No MSB LSB D7y D6y D5y D4y D3y D2y Diy DOy DOy CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instructions AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 005 07 0 1 Bank 1 selected data address 08y 0Fy 1 0 Bank 2 selected data address 10y 17y 1 1 Bank 3 selected data address 18y 1Fy OV Overflow Flag Used by arithmetic instructions F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP
212. r circuit of the type B multifunctional digital I O port lines The basic circuitry of these ports is shown in Figure 6 4 The pullup arrangement of type B port lines has one n channel pulldown FET and three pullup FETs Delay 1 state O Input Data Read Pin Figure 6 6 Driver Circuit of Type B Port Pins The pulldown FET n1 is of n channel type It is a very strong driver transistor which is capable of sinking high currents 7o it is only activated if a 0 is programmed to the port pin A short circuit to Vpp must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as input The pullup FET p1 is of p channel type It is activated for two oscillator periods S1P1 and S1P2 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a 0 The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level Semiconductor Group 6 9 SIEMENS On Chip Peripheral Components C508 The p
213. re In the programming mode the C508 4E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address data information control lines and an external 11 5 V programming voltage In the programming mode port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs The upper address information at port 2 is latched with the signal PALE For basic programming mode selection the inputs RESET PSEN EA Vpp ALE and PMSEL1 0 and PSEL are used Further the inputs PMSEL1 0 are required to select the access types e g program verify data write lock bits in the programming mode In programming mode Vpp Vss and a clock signal at the XTAL pins must be applied to the C508 4E The 11 5V external programming voltage is input through the EA Vpp pin Figure 10 1 shows the pins of the C508 4E which are required for controlling of the OTP programming mode Voo Vss P2 0 7 Port 2 Port 0 PALE gt PMSELO PMSEL1 gt XTAL1 XTAL2 Figure 10 1 Programming Mode Configuration Semiconductor Group 10 1 SIEMENS OTP Memory Operation C508 10 2 Pin Configuration Figure 10 2 shows the detailed pin configuration MQFP 64 1 package of the C508 4E in programming mode for P 1 A6 A14 oo A5 A13 L449 A4 A12 150 A3 A11 451 A2 A10 L 52 A1 A9 53 A0 A8 L 54 PMSEL1
214. re value is greater than or equal to the period value the reload should be delayed till the next zero match compare timer 1 reaches 0000p instead of the approaching period match compare timer 1 reaches period value This can be achieved by setting bit STE1 only in the period match interrupt service routine If the desired compare value is less than the offset value then the COUT bits in COINI register have to be inverted first before the reload is allowed Semiconductor Group 6 58 SIEMENS On Chip Peripheral Components C508 Compare Timer 1 Control Register The 16 bit compare timer 1 is controlled by the bits of the CT1CON register With this register the count mode the trap interrupt enable the compare timer start stop and reset and the timer input clock rate is controlled Special Function Register CT1CON Address El y Reset Value 00010000g Bit No MSB LSB 7 6 5 4 3 2 1 0 Ely CTM ETRP STE1 CTIRES CT1R CLK2 CLK1 CLKO CT CON Bit Function CTM Compare timer 1 operating mode selection CTM 0 selects operating mode 0 up count and CTM 1 selects operating mode 1 up down count for compare timer 1 ETRP CCU emergency trap interrupt enable If ETRP 1 the emergency interrupt for the CCU trap signal is enabled STE1 CAPCOM unit shadow latch transfer enable When STE1 is set the content of the compare timer 1 period compare and offset registers CCPH CCPL CCHx
215. ready in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IENO IEN1 or IPO IP1 the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 27 SIEMENS Fail Save Mechanisms C508 8 Fail Save Mechanisms The C508 offers enhanced fail save mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 153 6 us to 314 573 ms at fosc 10 MHz an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer To protect the system against software failure the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this p
216. register bank the SP should be initialized to a different location of the RAM which is not used for data storage Semiconductor Group 3 2 SIEMENS Memory Organization C508 3 4 XRAM Operation The XRAM in the C508 is a memory area that is logically located at the upper end of the external data memory space but is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types MOVX must be used for accessing the XRAM 3 4 1 XRAM Controller Access Control Two bits in SFR SYSCON XMAPO and XMAP 1 control the accesses to XRAM XMAPO is a general access enable disable control bit and XMAP1 controls the external signal generation during XRAM accesses Special Function Register SYSCON Address B1y Reset Value XX10XX01 pg Bit No MSB LSB 7 6 5 4 3 2 1 0 Biy e EALE RMAP XMAP1XMAPO SYSCON Ej The functions of the shaded bits are not described here Bit Function XMAP1 XRAM visible access control Control bit for RD WR signals during XRAM accesses If addresses are outside the XRAM address range or if XRAM is disabled this bit has no effect XMAP1 0 The signals RD and WR are not activated during accesses to the XRAM XMAP1 1 Ports 0 2 and the signals RD and WR are activated during accesses to XRAM In this mode address and data information during XRAM accesses are visible externally XMAPO Global XRAM access enable disab
217. registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 3 14 SIEMENS Memory Organization C508 Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset 804 PO FFy NA 6 i5 4 3 2 1 0 814 SP 07H 7 6 i5 4 id 2 A 0 824 DPL 00H 7 6 5 4 3 2 1 0 834 DPH 00H vi 6 5 4 3 2 1 0 864 WDTREL 004 WDT 6 5 4 3 2 1 0 PSEL 874 PCON 00H SMOD PDS IDLS SD GF1 GFO PDE IDLE 884 TCON 00H TF1 TR1 EO TRO IE1 IT1 IEO ITO 884 PCON1 0XXO EWPD WS XXXXB 894 TMOD 00y GATE C T M1 MO GATE C T M1 MO 8Ay TLO 00H af 6 5 4 iJ 2 A 0 8By TL1 00H 7 6 5 4 id 2 A 0 8Cy ITHO 00H NW 6 i5 4 3 ie A 0 8Dy TH1 00H oh 6 5 4 i3 2 1 0 9092 P1 FFH V 6 5 4 iJ 2 A 0 914 XPAGE 00y i 6 5 4 3 2 1 0 924 DPSEL XXXX 2 A 0 X000p 984 ISCON 00H SMO SM1 SM2 REN TB8 RB8 TI RI 994 SBUF XXH f 6 5 4 id 2 A 0 9A IEN2 XX00 ECT1 ECCM ECT2 ECEM 00XXp A0y P2 FFH ut 6 5 4 3 2 A 0 A8y IENO 00H EA WDT ET2 ES ET1 EX1 ETO EXO A94 IPO 00H OWDS WDTS 5
218. reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least two machine cycles after this time the C508 remains in its Semiconductor Group 5 5 SIEMENS Reset System Clock C508 reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 4 shows this timing for a configuration with EA 0 external program memory Thus between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles One Machine Cycle St S2 S3 S4 S5 S6 PIPA qiti v prb d 1 S2 S4 3 1 S2 S5 S6 S4 s5 S6 PACU M HE E ALE MCT0209
219. ripheral Components 200 e eee eee eee eee nnn 6 1 Semiconductor Group l 1 SIEMENS General Information C508 Contents Page 6 1 Parallell ose c eed ho S PLACE der ete SP ee a le e a a oii 6 1 6 1 1 POLL SIUGIUUAS sit eoi ea e ur poe esr E edd quee kon a F 6 1 6 1 2 standard WO Port Girc tiy Sar xe Rp tie ied xx onec fa vieta det 6 3 61 2 1 Port O GIFGUl s sota a ea o Bara Mes epo roce d ow e i herpes 6 5 6 1 2 2 Port 1 Port 3 and Port 5 Circuitry estaa us beats as dac ie dn Rd E 6 6 6T 23 sPORZ CICUIIYS deta rau S ee tetra e e tate ede pde ES ES Mertens Ae ks 6 7 6 1 3 Detailed Output Driver Circuitry llle 6 9 6 1 3 1 Type B Pott Driver Circuitry ua Ex eX RASSE oe RATERS 6 9 6 1 3 2 Type D Port Driver Circuitry utente A 6 11 6 1 4 Fort TIMING See toc A X E EE CE ec qs 6 12 6 1 5 Port Loading and Interfacing vo emt ede sorte ente Mee bd o dd ee Beds 6 13 6 1 6 Read Modify Write Feature of Ports 0 to 5 Except Port 4 6 14 6 2 TIrets COUMMBES uci sec bone de rice Sese ci rite Ce urs 6 15 6 2 1 Timer outnter Gand T ossa rare PHP hue rre 6 15 6 2 1 1 Timer Counter O and 1 Registers 0 eee ee 6 16 o2 12 MOJO rines eoi eom Re AR ESREE TERR T NOE e ated 6 19 p ra Modet we cert owes TERR set cate SCIENS mde deme Roatan mast Gd 6 20 B2 L4 MOdB 2 varitstwuv en te teats es DA T tue ak DS OK NUS RN tert 6 21 p2 1 5 MOOBUS tn SA err M ote ad cst cessa ses ER ca 6 22 6 2 2 T
220. rogrammable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function Compare timer 2 input clock is 2 fosc Compare timer 2 input clock is fosc Compare timer 2 input clock is fogc 2 Compare timer 2 input clockis fosc 4 Compare timer 2 input clock is fosc 8 Compare timer 2 input clockis fogc 16 Compare timer 2 input clock is fos 32 0 o0 o o o0o oc0oi o 0 1 0 1 0 1 0 1 Compare timer 2 input clock is fosc 64 Note With a reset operation external or internal compare timer 2 is reset 0001 and stopped When software power down mode is entered with CT2RES bit of SFR CT2CON set the compare timer 2 is reset after the execution of a wake up from power down mode procedure When CT2RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 2 is not reset Depending on the state of bit CT2R at power down mode entry the compare timer 2 either stops CT2R 0 or continues CT2R 1 counting after a wake up from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 77 SIEMENS On Chip Peripheral Components C508 Compare Timer 2 Period Registers The compare timer 2 period registers CP2L CP2H hold the 10 bit value for the compare timer 2 period When the
221. rogramming mode PROG 45 53 Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG EAVpp 2 10 Programming voltage This pin must be at 11 5 V Vpp voltage level during programming of an OTP memory byte or lock bit During an OTP memory read operation this pin must be at V high level This pin is also used for basic programming mode selection At basic programming mode selection a low level must be applied to EA Vpp P0 7 0 57 64 1 8 O Data lines 0 7 During programming mode data bytes are transferred via the bidirectional D7 0 lines which are located at port 0 N C 3 12 11 30 Not Connected 15 22 33 40 These pins should not be connected in programming mode 25 32 46 48 38 40 Input O Output Semiconductor Group 10 5 SIEMENS OTP Memory Operation C508 10 4 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts Basic programming mode selection Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic Further after selection of the basic programming mode OTP memory accesses are executed by using one of
222. rsion clock f Apc is less than or equal to 2 MHz see section 6 5 3 The prescaler ratio is selected according to the following table ADCL1 ADCLO Prescaler Ratio 0 0 divide by 4 0 1 divide by 8 default after reset 1 0 divide by 16 1 1 divide by 32 Note Generally before entering the power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the BSY bit or waiting for the A D conversion interrupt In continuous conversion mode bit ADM must be cleared and the last A D conversion must be terminated before entering the power down mode A single A D conversion is started by writing to SFR ADDATL with dummy data A continuous conversion is started under the following conditions Bysetting bit ADM during a running single A D conversion By setting bit ADM when at least one A D conversion has occurred after the last reset operation By writing ADDATL with dummy data after bit ADM has been set before if no A D conversion has occurred after the last reset operation When bit ADM is reset by software in continuous conversion mode the just running A D conversion is stopped after its end Semiconductor Group 6 119 SIEMENS On Chip Peripheral Components C508 The A D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON Special Function Register IEN1 Address B8jy Reset Value 00y Spe
223. rter Clock Selection 0 00 ee 6 121 6 5 4 A D Conversion Timing 2222392 ame i Raat eI Ue XE E ER Raid ad 6 122 6 5 5 A D Converter Calibration gt ati tii dede Saves See e ete De estet os 6 126 7 Int rrupt Systemi coerceri eise etus dadas wed e Mns 7 1 7 1 Structure of the Interrupt System 2 20 space dee er rer Rm eth eee te 7 1 7 2 Interrupt Registers iss costado ee eR hh ES as 7 7 7 2 1 Interrupt Enable Registers coss se E eR VECES UC SUCRE E n SUPR at cn 7 7 7 2 2 Interrupt Request Flags sai traia ia 7 12 7 2 3 Interrupt Priority Registers ati a A A SUCRE e ee 7 21 7 3 Interrupt Priority Level Structure iu us cc RR Rte eres 7 22 7 4 How Interrupts are Handled 0 cc eee eee 7 24 7 5 External Interr pts uev e ne yee A A a 7 26 7 6 Interrupt Response Time roscas ae Dre 7 27 8 Fail Save Mechanisms esee nnn 8 1 8 1 Programmable Watchdog Timer duiaeice o vr ayaa teen DELE XE as 8 1 8 1 1 Input Glock Selection y cai cR CE eg Ee SOR ROR ee ae E 8 2 8 1 2 Watchdog Timer Control Status Flags ooococcooooocccn ee 8 3 8 1 3 Starting the Watchdog Timer we ee 8 4 8 1 4 Refreshing the Watchdog Timer o o oocococcooco eee 8 4 8 1 5 Watchdog Reset and Watchdog Status Flag oocoococccocoo ee 8 5 8 2 Oscillator Watchdog nit sos 62 sess we bet ans e S 8 6 8 2 1 Detailed Description of the Oscillator Watchdog Unit 00 000 8 7 9 Power Saving Modes
224. s Note If protection level 1 to 3 has been programmed see section 10 6 and the programming mode has been left it is no more possible to enter the programming mode 10 4 2 OTP Memory Access Mode Selection When the C508 4E has been put into the programming mode using the basic programming mode selection several access modes of the OTP memory programming interface are available The conditions for the different control signals of these access modes are listed in table 10 2 Table 10 2 Access Modes Selection EA PMSEL Address Data Access Mode v PROG PRD gt 0 Port 2 Port 0 Program OTP memory byte Vpp LT H H H AO 7 DO 7 Read OTP memory byte Vin H LI A8 14 Program OTP lock bits Vep LT H H L D1 D0 see Read OTP lock bits Val H LT Maple 1973 Read OTP version byte Vin H LI IL H Byte addr DO 7 of version byte The access modes from the table above are basically selected by setting the two PMSEL1 0 lines to the required logic level The PROG and PRD signal are the write and read strobe signal Data is transferred via port O and addresses are applied to port 2 The following sections describe the details of the different access modes Semiconductor Group 10 7 SIEMENS OTP Memory Operation C508 10 5 Program Read OTP Memory Bytes The program read OTP memory byte access mode is defined by PMSEL1 0 1 1 It is initiated when the PMSEL1 0 1 1 is v
225. s 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the incoming data bytes SM2 has no effect in mode 0 SM2 can be used in mode 1 to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 6 4 2 Serial Port Registers The serial port control and status register is the special function register SCON This register contains not only the mode selection bits
226. s into RB8 in SCON The baud rate is programmable to either 1 16 or 1 32 the oscillator frequency in mode 2 When bit SMOD in SFR PCON 871 is set the baud rate is fosc 16 In mode 3 the baud rate clock is generated by timer 1 which is incremented by a rate of fos 6 or by the internal baud rate generator Figure 6 47 shows a functional diagram of the serial port in modes 2 and 3 The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register The associated timings for transmit receive are illustrated in Figure 6 48 Transmission is initiated by any instruction that uses SBUF as a destination register The Write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in fr
227. shaded bits are not used for interrupt control Bit Function I2FR External interrupt 2 rising falling edge control flag If I2FR 0 the external interrupt 2 is activated by a falling edge at P5 4 INT2 If 12FR 1 the external interrupt 2 is activated by a rising edge at P5 4 INT2 ISFR External interrupt 3 rising falling edge control flag If IBFR 0 the external interrupt 3 is activated by a falling edge at P5 0 T2CC0 INT3 If IBFR 1 the external interrupt 3 is activated by a rising edge at P5 0 T2CC0 INT3 The external interrupt 2 INT2 can be either positive or negative transition activated depending on bit I2FR in register T2CON The flag that actually generates this interrupt is bit IEX2 in register IRCON The flag IEX2 is cleared by hardware when the service routine is vectored to Like the external interrupt 2 the external interrupt 3 INT3 can be either positive or negative transition activated depending on bit I3FR in register T2CON The flag that actually generates this interrupt is bit IEX3 in register IRCON In addition this flag will be set if a compare event occurs at pin P5 0 T2CCO INTS3 regardless of the compare mode established and the transition at the respective pin The flag IEX3 is cleared by hardware when the service routine is vectored to The external interrupts 4 INT4 5 INT5 and 6 INT6 are positive transition activated The flags that actually generate these interrupts are bits IEX4
228. st and control flags which are described in the next sections Semiconductor Group 7 1 SIEMENS Interrupt System C508 ighest riority Level IENO O Priority Level A D Converter ADC ra IEN1 0 E O i n g S e q u e Timer 0 ea Overflow TFO e TCON 5 ETO d IENO 1 J Request flag is cleared by hardware Figure 7 1 Interrupt Structure Overview Part 1 Semiconductor Group 7 2 SIEMENS Interrupt System C508 T IENO 2 Q ON 2 Tar Heo AA E TCON 3 TRCON 6 TS CCU CT1CON 6 c o Emergency Interrupt IEN2 2 a BCON 3 BCON 4 P5 0 T2CC0 po IEX3 PE INT3 EX3 SER IRCON 2 EX3 IEN1 2 T2CON 6 P5 7 INT7 IEX7 d EINT 1 I7FR au IEN3 2 EINT O 4 Request flag is cleared by hardware Priority Level Highest Lowest Priority Level Q5 0c 00O050C0O000 Figure 7 2 Interrupt Structure Overview Part 2 Semiconductor Group 7 3 SIEMENS Interrupt System C508 I8FR EINT 2 ES EINT3 Timer 1 TF1 PA Overflow TCON 7 IENO 3 Compare m Timer 2 GTa Interrupt CT2CON 7 ECT2 IEN2 3 P5 1 T2CC1 IEX4 Ed INTA IRCON 3 EX4 IEN1 3 EX8 IEN3 3 3 Bit addressable 4 Request flag is cleared by hardware Highest Priority Level Lowest Priority Level e e 0 U i S e E u e n C e Figure 7 3 Interrupt Structure Overview Part 3 Semicondu
229. stem C508 The SFR IEN2 contains the enable bits for the four interrupts from the CCU unit Special Function Register IEN2 Address 9A py Reset Value XX0000XXp MSB LSB Bit No 7 6 5 4 3 2 1 0 9AH ECT1 ECCM ECT2 ECEM IEN2 Bit Function ECT1 Compare Timer 1 interrupt enable If ECT1 2 0 the compare timer 1 interrupt is disabled If ECT1 2 1 the compare timer 1 interrupt is enabled ECCM Compare capture match interrupt enable If ECCM 0 the compare capture match interrupt is disabled If ECCM 1 the compare capture match interrupt is enabled ECT2 Compare Timer 2 interrupt enable If ECT2 0 the compare timer 2 interrupt is disabled If ECT2 1 the compare timer 2 interrupt is enabled ECEM CCU emergency interrupt enable If ECEM 0 the emergency interrupt of the CCU is disabled If ECEM 1 the emergency interrupt of the CCU is enabled Semiconductor Group 7 10 SIEMENS Interrupt System C508 The SFR IENS contains the enable bits for the external interrupts 7 to 9 Special Function Register IEN3 Address BE Reset Value XXX000XXp MSB LSB Bit No 7 6 5 4 3 2 1 0 BEH EX9 EX8 EX7 IEN3 Bit Function EX9 External interrupt 9 enable If EX9 0 external interrupt 9 is disabled If EX9 1 external interrupt 9 is enabled EX8 External interrupt 8 enable If EX8 0 external interrupt 8
230. sters CCHx CCLx is equal 0000H When the compare value is not equal 0000y and less or equal the period value the active phase of the related compare output signal CCx or COUTx is controlled by the CAPCOM unit as shown in Figure 6 34b Semiconductor Group 6 84 SIEMENS On Chip Peripheral Components C508 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COINI Bit 1 AAT LE AV AV AVA 8B HN a No transitions in active phase offset and compare value z 0 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COINI Bit 0 AAT L 7L b CAPCOM transitions in active phase 0 lt compare value lt period value offset value 0 AADA COINI Bit 1 COINI Bit 0 Compare Timer 1 NAAA Compare Timer1 Aur Mode 0 Mode 0 ss CCx INM CCx Yy MN COUTx COUTx Compare Timer 1 ANUPNU NUZN Compare Timer 1 AUN Mode 1 LN II Mode 1 LIV x CCx MU CCx MA COUTx Ad COUTx q7 Active Phase MCTO2609 Figure 6 34 Compare Timer 1 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 0 Semiconductor Group 6 85 SIEMENS On Chip Peripheral Components C508 Figure 6 35 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 2 In this operating mode
231. stored in the compare register a static 1 or a static O depending on COINI content will be generated at COUTx see Figure 6 27 d and e Therefore CCx will also stay at a static level if the compare register value is greater than the value stored in the period register Semiconductor Group 6 48 SIEMENS On Chip Peripheral Components C508 Count Value CT1 CT10FF A CCP 7 Period Reg CT10F 22 Offset Reg 0 0 0 i Start of CT1 a Time CC COINI Pin 3 0 CCx 8 3 0 COUTx b 3 1 COUTx C CT10F cece 0 COUTX o 0 d CTIOF 0 COUTx 100 e CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT10F content of the CT1OFH CT10OFL offset registers MCTO2602 Figure 6 27 Compare Timer 1 with Offset not equal 0 Mode 0 Semiconductor Group 6 49 SIEMENS On Chip Peripheral Components C508 6 3 2 3 CAPCOM Unit Operating Mode 1 Using compare timer 1 in operating mode 1 two symmetric output signals with constant dead time forr at each signal transition can be generated per channel Figure 6 28 shows the operating mode 1 timing in detail
232. t Therefore unprotected as well as protected ROMs must provide a procedure to verify the ROM contents In ROM verification mode 1 which is used to verify unprotected ROMs a ROM address is applied externally to the C508 4R and the ROM data byte is output at port 0 ROM verification mode 2 which is used to verify ROM protected devices operates differently In this mode ROM addresses are generated internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte verify operations the state of the P3 5 pin shows whether the last 16 bytes have been verified correctly This mechanism provides a very high security of ROM protection Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort The behaviour of the move code instruction when the code is executed from the external ROM is in such a way that accessing a code byte from a protected on chip ROM address is not possible In this case the byte accessed will be invalid 4 7 1 Unprotected ROM Mode If the ROM is unprotected the ROM verification mode 1 as shown in Figure 4 4 is used to read out the contents of the ROM Please refer to the AC specifications in C508 data sheet for the AC timing characteristics of the ROM verification mode P2 0 P2 6 Address 1 Address 2 Inputs PSEN P2 7 Vas
233. t 2 input P5 5 INT9 B External interrupt 9 input P5 6 INT8 B External interrupt 8 input P5 7 INT7 B External interrupt 7 input Prior to the description of the port type specific port configurations the general port structure is described in the next section Semiconductor Group 6 2 SIEMENS On Chip Peripheral Components C508 6 1 2 Standard I O Port Circuitry Figure 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the five l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO to P4 activate the read latch signal while others activate the read pin signal Read Latch Int Bus Port Driver Write Circuit to Latch Read Pin Figure 6 1 Basic Structure of a Port Circuitry Semiconductor Group 6 3 SIEMENS On Chip Peripheral Components The output drivers of port 1 to 5 except port 4 have internal pullup FET s see Figure 6 2 Each O line can be used independently as an input or output To be used as an
234. t RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for the noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection or false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 Rl 20 and 2 either SM2 0 or the received stop bit 1 If one of these two condtions is not met the received frame is irretrievably lost If bot
235. t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes one synchronous mode three asynchronous modes The baud rate clock for the serial port is derived from the oscillator frequency mode 0 2 or generated either by timer 1 or by a dedicated baud rate generator mode 1 3 Mode 0 Shift Register Synchronous Mode Serial data enters and exits through RxD TxD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 3 of the oscillator frequency See section 6 4 4 for more detailed information Mode 1 8 Bit USART Variable Baud Rate In mode 1 ten bits are transmitted through TxD or received through RxD They are a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in special function register SCON The baud rate is variable See section 6 4 5 for more detailed information Mode 2 9 Bit USART Fixed Baud Rate 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for
236. t digital Input Port 5 Interrupt Unit 8 bit digital 1 O VAREF A D Converter VAGND 10 Bit Emulation Support Figure 2 1 Block Diagram of the C508 Semiconductor Group 2 2 SIEMENS Fundamental Structure C508 2 1 CPU The C508 is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 4196 two byte and 15 three byte instructions With a 10 MHz external crystal giving a 20MHz CPU clock 5896 of the instructions execute in 300 ns For an 8 MHz crystal the corresponding time is 375 ns The CPU Central Processing Unit of the C508 consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU These internal signals have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU perfor
237. t from this AND operation produces a low active read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 3 SIEMENS External Bus Interface C508 4 4 ALE Address Latch Enable The C508 allows to switch off the ALE output signal If the internal ROM is used EA 1 and PC 7FFFy and ALE is switched off by EALE 0 then ALE will only go active during external data memory accesses MOVX instructions If EA 0 the ALE generation is always enabled and the bit EALE has no effect After a hardware reset the ALE generation is enabled Special Function Register SYSCON Address B1y Reset Value XX10XX01p Bit No MSB LSB 7 6 5 4 3 2 1 0 Biy EALE RMAP XMAP1XMAPO SYSCON jJ The shaded bits are not described in this section Bit Function EALE Enable ALE output EALE 2 0 ALE generation is disabled disables ALE signal generation during internal code memory accesses EA 1 With EA 1 ALE is automatically generated at MOVX instructions EALE 1 ALE generation is enabled If EA 0 the ALE generation is always enabled and the bit EALE has no effect on the ALE generation Reserved bits for future use Read by CPU returns undefined values Semiconductor Group 4 4 SIEMENS External Bus Interface C508 4 5 Enhanced
238. t this logic level is noticed by the port at least once S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 S4 P1 P2 P1 P2 NAE CE cp a o 2 Input sampled e g MOV A P1 p1 active or i driver transistor Port Old Data X New Data Figure 6 8 Port Timing Semiconductor Group 6 12 SIEMENS On Chip Peripheral Components C508 6 1 5 Port Loading and Interfacing The output buffers of ports 1 to 5 except port 4 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the Data Sheet of the C508 The corresponding parameters are Vo and Voy The same applies to port O output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that the ports 1 to 5 except 4 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters and in the DC characteristics specify these currents Port O however has floating inputs when used for digital input Semiconductor Group 6 13 SIEMENS On Chip Peripheral Components C508 6 1 6 Read Modify Write Feature of Ports 0 to 5 Except Port 4 Some port reading instructions read the latch and others read the pin
239. tart Compare Timer 1 gt cco court CC2 HL uw PAT High Active Phase COUTO CC1 MCT02615 Figure 6 39 Basic Compare Timer 1 Controlled 6 Phase PWM Timing Semiconductor Group 6 93 SIEMENS On Chip Peripheral Components Table 6 11 to Table 6 13 show as state tables the basic signal pattern definitions of the three multi channel PWM modes They also include the information of the slow down mode and the idle mode bits BMC1 0 0 0 and 1 1 Table 6 11 4 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive 2 1 0 5 1 active inactive inactive active 4 2 0 5 2 active active inactive inactive 1 3 0 5 3 inactive active active inactive 2 4 0 5 4 inactive inactive active active 3 1 0 5 5 inactive active inactive active 2 1 0 5 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Table 6 12 5 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUTO COUT2 0
240. ted in SFR SYSCON B1 p The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down mode takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle mode For this an instruction that activates idle mode can also set one or both flag bits When idle mode is terminated by an interrupt the interrupt service routine can examine the flag bits Special Function Register PCON Address 87H Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode SD Slow down mode bit When set the slow down mode is enabled GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of the power down is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled Semiconductor Group 9
241. terrupt O is enabled Semiconductor Group 7 8 IE Interrupt System SIEMENS COE The SFR IEN1 contains the enable bits for the external interrupts 2 to 6 and the A D converter interrupt Special Function Register IEN1 Address B8y Reset Value X0000000g MSB LSB Bit No BF y BEy BDy BC BBy BAH B94 B84 B8H SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 The shaded bits are not used for interrupt control Bit Function EX6 External interrupt 6 Timer 2 capture compare interrupt 3 enable If EX6 0 external interrupt 6 is disabled If EX6 1 external interrupt 6 is enabled EX5 External interrupt 5 Timer 2 capture compare interrupt 2 enable If EX5 0 external interrupt 5 is disabled If EX5 1 external interrupt 5 is enabled EX4 External interrupt 4 Timer 2 capture compare interrupt 1 enable If EX4 0 external interrupt 4 is disabled If EX4 1 external interrupt 4 is enabled EX3 External interrupt 3 Timer 2 capture compare interrupt O enable If EX3 0 external interrupt 3 is disabled If EX3 1 external interrupt 3 is enabled EX2 External interrupt 2 enable If EX2 0 external interrupt 2 is disabled If EX2 1 external interrupt 2 is enabled EADC A D converter interrupt enable If EADC 0 the A D converter interrupt is disabled If EADC 1 the A D converter interrupt is enabled Semiconductor Group 7 9 SIEMENS Interrupt Sy
242. terrupt edge was detected or when a compare event occured at P5 0 T2CCO INT3 Cleared when interrupt is processed IEX2 External interrupt 2 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P5 4 INT2 Cleared when interrupt is processed IADC A D converter interrupt request flag Set by hardware at the end of an A D conversion Must be cleared by software The timer 2 interrupt is generated by bit TF2 in register IRCON This flag is not cleared by hardware when the service routine is vectored to It should be cleared by software The A D converter interrupt is generated by IADC bit in register IRCON If an interrupt is generated in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine If continuous conversion is established IADC is set once during each conversion If an A D converter interrupt is generated flag IADC will have to be cleared by software Semiconductor Group 7 14 SIEMENS Interrupt System C508 Special Function Register EINT Address FBy Reset Value XX000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 FBu IEX9 I9FR IEX8 I8FR IEX7 I7FR EINT Bit Function IEX9 External interrupt 9 edge flag Set by hardware when external interrupt edge was detected Cleared by hardware when processor vectors to the interrupt routine I9FR External interrupt 9 rising falli
243. that state can be used as inputs As inputs port 3 pins being externally pulled low will source current J in the DC characteristics because of the internal pullup transistors The output latch corresponding secondary function must be programmed to a one 1 for that function to operate As secondary functions port 1 contains the capture compare inputs outputs as well as the CCU trap input Port 1 pins except P1 1 have LED drive capability of up to 10mA sinking current per pin The secondary functions from the CCU unit are assigned to the pins of port 1 as follows P1 0 COUT3 10 bit compare channel output P1 1 CTRAP CCU trap input P1 2 CCO Input Output of capture compare channel 0 P1 3 COUTO Output of capture compare channel 0 P1 4 CC1 Input Output of capture compare channel 1 P1 5 COUT1 Output of capture compare channel 1 P1 6 CC2 Input Output of capture compare channel 2 P1 7 COUT2 Output of capture compare channel 2 Input O Output Semiconductor Group 1 6 SIEMENS Introduction C508 Symbol Pin Numbers l O Function P MQFP 64 P SDIP 64 RESET 1 9 RESET A high level on this pin for one machine cycle while the oscillator is running resets the device An internal diffused resistor to Vas permits power on reset using only an external capacitor to Vpp P3 0 P3 7 33 40 41 48 O Port3 is an 8 bit quasi bidirectional port with internal pull up transistors Port 3 pins that have
244. the access modes These access modes are OTP memory byte program read version byte read and program read lock byte operations 10 4 1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 10 4 Clock XTAL1 XTAL2 RESET PSEN PMSEL1 0 PROG PRD OV Ready for access During this period signals mode selection are not actively driven Figure 10 4 Basic Programming Mode Selection Semiconductor Group 10 6 SIEMENS OTP Memory Operation C508 The basic programming mode is selected by executing the following steps With a stable Vpp a clock signal is applied to the XTAL pins the RESET pin is set to 1 level and the PSEN pin is set to 0 level PROG PALE PMSEL1 and EA Vpp are set to 0 level PRD PSEL and PMSELO are set to 1 level PSELis switched from 1 to 0 level and thereafter PROG is switched to 1 level PMSEL1 0 can now be changed after EA Vpp has been set to Vj high level or to Vpp the OTP memory is ready for access The pins RESET and PSEN must stay at static signal levels 1 and 0 respectively during the whole programming mode With a falling edge of PSEL the logic state of PROG and EA Vpp is internally latched These two signals are now used as programming write pulse signal PROG and as programming voltage input pin Vpp After the falling edge of PSEL PSEL must stay at 0 state during all programming operation
245. the compare outputs CCx and COUTx are toggled set to the new logic level if required min 50ns O 10MHz oscillator clock Input clock of CT1 O i a UUUUUUUUUUUUUUUUL dE e UA me EA Wr ee EIE sa LT LJ L O increment decrement of compare timer 1 change modify logic level at CCx COUTx Figure 6 25 CAPCOM Unit Clocking Scheme Generally the CAPCOM clocking scheme shown above is also valid for the COMP compare timer 2 unit Semiconductor Group 6 46 SIEMENS On Chip Peripheral Components C508 6 3 2 2 CAPCOM Unit Operating Mode 0 Figure 6 26 shows the CAPCOM unit timing in operating mode 0 in detail CT1 Value CCP 7 Period Reg j Offset Reg i CT1OFF 0 Time o 0 10 Start of CT1 E EE 2 Duty E ta y Er Cycles CC 0 j uu P dog 10096 pos A 3 n gt CC 1 1 1 1 87 5 OSs e NT iit Cs a D 1 1 1 S ZE CC 4 id 50 OO E i m OOs o I 1 1 i i 1 i 3 CC gt 7 0 CC 0 M qm 10095 ps ro 1 1 1 l D a CC 1 87 596 Q Z5 1 l 1 1 1 1 1 1 OUS bzo e o 7 Lif L 303 D d Xx amp CC gt 7 gg o e a E 0 CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT1O content of the CT1OFH CT10OFL offset register Figure 6 26 Compare Timer 1 Mode 0 In the example above compare timer 1 counts from 0000y up to 0007
246. the final shift pulse is generated 1 RI 2 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bit goes into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RxD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI Semiconductor Group 6 112 SIEMENS On Chip Peripheral Components C508 M Internal Bus EA y TB8 Q E SBUF 5 51 TxD D CLK Zero Detector Write to SBUF Stop Bit Shift gt Stat Generation Data TX Control gt 16 TX Clock TI Send Baud Serial 21 Rate 4 Port Clock Interrupt Sample 1 to 0 RX Clock RI i gt Transition Start Detector RX Control 1FF y Shift 4 cn Input Shift Register 9Bits RXD Shift ST v gt SBUF SBUF Read A v Internal Bus MCS02105 Figure 6 47 Serial Interface Mode 2 and 3 Functional Diagram Semiconductor Group 6 113 C508 On Chip Peripheral Components SIEMENS L8SZOLON ld saw ajdwes 4010919 18 Receive 19019 XY t 9es8u 9 usd jig dois Transmit IdiS 9DON y pues Ld9S Z PON ANA
247. the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If itis a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figure 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C508 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 2 2 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction Semiconductor Group 2 5 SIEMENS Fundamental Structure C508 s1 s2 s3 S4 S5 se S1 S2 S3 S4 S5 se P1 P2 P1P2 P1 P2 P1 P2 P1P2 P1 P2 P1 P2 P1P2 P1 P2 PI P2 P1P2 P1 P2 a 1 Byte 1 Cycle Instruction e g INC A b 2 Byte 1 Cycle Instruction e g ADD A Data ESTSTSTSTSTSISTS
248. the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer 0 TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer O If not explicity noted this applies also to timer 1 Semiconductor Group 6 15 SIEMENS On Chip Peripheral Components C508 6 2 1 1 Timer Counter 0 and 1 Registers Totally seven special function registers control the timer counter 0 and 1 operation TLO THO and TL1 TH1 counter registers low and high part TCON and IENO control and interrupt enable TMOD mode select Special Function Register TLO Address 8Ay Reset Value 00y Special Function Register THO Address 8CH Reset Value 00H Special Function Register TL1 Address 8By Reset Value 00y Special Function Register TH1 Address 8D Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 8AH 7 6 5 4 3 2 A 0 TLO 8CH a 6 5 4 3 2 1 0 THO 8By 7 6 D 4 3 2 1 0 TL1 8DH 7 6 5 4 EC 2 1 0 TH1 Bit Function TLx 7 0 Timer counter 0 1 low register xp Operating Mode Description 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter va
249. tion MOVC A DPTR Fetch source data byte from ROM table 2 MOV DPSEL 07H Save source pointer and load destination pointer 2 MOVX DPTR A Transfer byte to destination address 2 POP DPSEL Save destination pointer and restore old datapointer 2 Total execution time machine cycles 12 The above example shows that utilization of the C508 s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here four data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that a C508 program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use Semiconductor Group 4 9 SIEMENS External Bus Interface C508 4 7 ROM OTP Protection for the C508 4R C508 4E The C508 4R allows to protect the contents of the internal ROM against unauthorized read out The type of ROM protection protected or unprotected is fixed with the ROM mask Therefore the customer of a C508 4R version has to define whether ROM protection has to be selected or not The C508 4E OTP version allows also program memory protection in several levels see chapter 10 6 The program memory proctection for the C508 4E can be activated after programming of the device The C508 4R devices which operate from internal ROM are always checked for correct ROM contents during production tes
250. tion Register IPO Address A9 Reset Value 00y Special Function Register IP1 Address B9y Reset Value XX000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O IPO Bit No 7 6 5 4 3 2 1 0 B9y IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 IP1 El The shaded bits are not used for interrupt control Bit Function IP1 x Interrupt group priority level bits x 0 5 see Table 7 1 IPO x IP1 x IPO x Function 0 0 Interrupt group x is set to priority level O lowest 0 1 Interrupt group x is set to priority level 1 1 0 Interrupt group x is set to priority level 2 1 1 Interrupt group x is set to priority level 3 highest Semiconductor Group 7 21 SIEMEN Interrupt System S C508 7 3 Interrupt Priority Level Structure The 19 interrupt sources of the C508 are grouped according to the listing in Table 7 1 Table 7 1 Interrupt Source Structure Interrupt Associated Interrupts Group 1 External interrupt O A D converter interrupt Timer 0 overflow External interrupt 2 External interrupt 1 CCU emergency External interrupt 3 External interrupt 7 interrupt 4 Timer 1 overflow Compare timer 2 External interrupt 4 External interrupt 8 interrupt 5 Serial channel Capture Compare External interrupt 5 External interrupt 9 interrupt m
251. tion phase which takes 3328 fapc clocks alternating offset and linearity calibration is executed Therefore at 8 MHz oscillator frequency and with the default after reset prescaler value of 8 a reset calibration time of approx 1 664 ms is reached For achieving a proper reset calibration the fapc prescaler value must satisfy the condition fapc max 2 MHz If this condition is not met at a specific oscillator frequency with the default prescaler value after reset the fapc prescaler must be adjusted immediately after reset by setting bits ADCL1 and ADCLO in SFR ADCON 1 to a suitable value It is also recommended to have the proper voltages as specified in the DC specifications applied at the Varer and Vaawp pins before the reset calibration has started After the reset calibration phase the A D converter is calibrated according to its DC characteristics Nevertheless during the reset calibration phase single or continuous A D can be executed In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A D conversion Therefore interrupting the reset calibration phase by A D conversions extends the total reset calibration time If the specified total unadjusted error TUE has to be valid for an A D conversion it is recommended to start the first A D conversions after reset when the reset calibration phase is finished Depending on the oscillator frequency used the reset calibration phase can be
252. tive active inactive active inactive active 2 1 0 7 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Semiconductor Group 6 95 SIEMENS On Chip Peripheral Components C508 6 3 4 6 Software Controlled State Switching in Multi Channel PWM Modes In the 4 5 6 phase multi channel PWM modes the compare timer 1 overflow controlled switching of the follower state can be switched off Instead of the compare timer 1 overflow a setting of bit NMCS in SFR CMSEL1 selects the follower state which is defined in the Table 6 11 to Table 6 13 Bit ESMC in SFR CMSEL1 enables the software controlled state switching If this software controlled 4 5 6 phase multi channel PWM mode generation is selected the compare timer 1 can be used for PWM signal generation compare mode in order to modulate the outputs It can be further used for example for timer based interrupt generation The waveforms of a PWM output signal in the multi channel PWM modes can be selected as shown in Figure 6 34 static low or high during active phase or as shown in Figure 6 35 compare timer 2 controlled modulation during active phase Figure 6 40 shows for the 5 pole PWM timing the possible waveforms of the active phase when the software controlled state switching in the multi channel PWM m
253. ts for the external interrupts 0 and 1 the timer interrupts and the USART interrupt Special Function Register IENO Address A8 Reset Value 00H MSB LSB BitNo AFy AE ADy ACy ABY AAY A94 A8y A8y EA WDT ET2 ES ET1 EX1 ETO EXO IENO The shaded bits are not used for interrupt control Bit Function EA Enable disable all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit ET2 Timer 2 overflow external reload interrupt enable If ET2 0 the timer 2 interrupt is disabled If ET2 1 the timer 2 interrupt is enabled ES Serial channel USART interrupt enable If ES 0 the serial channel interrupt 0 is disabled If ES 1 the serial channel interrupt O is enabled ET1 Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled If ET1 1 the timer 1 interrupt is enabled EX1 External interrupt 1 enable If EX1 0 the external interrupt 1 is disabled If EX1 1 the external interrupt 1 is enabled Semiconductor Group 7 7 SIEMENS Interrupt System C508 Bit Function ETO Timer 0 overflow interrupt enable If ETO 0 the timer 0 interrupt is disabled If ETO 1 the timer 0 interrupt is enabled EXO External interrupt O enable If EXO 0 the external interrupt 0 is disabled If EXO 1 the external in
254. uctions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch However reading the latch rater than the pin will return the correct value of 1 Semiconductor Group 6 14 SIEMENS On Chip Peripheral Components C508 6 2 Timers Counters The C508 contains three 16 bit timers counters timer 0 timer 1 and timer 2 which are useful in many applications for timing and counting In timer function the timer register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 3 oscillator periods the counter rate is 1 3 of the oscillator frequency In counter function the timer register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 or P3 5 respectively In this function the external input is sam
255. ucture is illustrated in Figure 6 7 Enable Push Pull Delay 1 State i o y Input Data Read Pin Figure 6 7 Driver Circuit of Type D Port Pins Semiconductor Group 6 11 SIEMENS On Chip Peripheral Components C508 6 1 4 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 8 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain reqirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees tha
256. ue in the offset register plus the value of the period register is less than or equal to the value stored in the compare register a static 1 or a static 0 depending on COINI content will be generated at COUTx In the same way CCx will also stay at a static level is the compare register value is greater than the value stored in the period register Semiconductor Group 6 50 SIEMENS On Chip Peripheral Components C508 6 3 2 4 CAPCOM Unit Timing Relationships Depending on the operating mode of the compare timer 1 compare output signals can be generated with a maximum period and resolution as shown in Figure 6 29 This example also demonstrates the reloading of the compare and period registers which occurs when compare timer 1 reaches the count value 0000y Operating Mode 0 Load Reg with Load Reg with Count COXReg o 2 GCxReg 2 Value CCP lt min 150ns 10MHz clock rate Operating Mode 1 Load Reg with CCxReg 1 coon CCP J alue min 200ns O 10MHz clock rate Figure 6 29 Maximum Period and Resolution of the Compare Timer 1 Unit Semiconductor Group 6 51 SIEMENS On Chip Peripheral Components C508 Figure 6 29 shows the resolution and the period value range which depends on the selected compare timer 1 input clock prescaler ratio Table 6 6 Resolution and Period of the Compare Timer 1 at fosc 10 MHz Compare Operating Mode 0 Operating Mode 1 T
257. ullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current Ji If in addition the pullup FET p3 is activated a higher current can be sourced M Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a logic high level is output The described activating and deactivating of the four different transistors translates into four states the pins can be input low state IL p2 active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with O the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 n
258. unt at the output pins when compare timer 1 is 0 Bit NMCS is reset by hardware in the next clock cycle after it has been set CMSELx3 x 0 2 Switching compare timer 2 output signal to COUTx If CMSELx3 is set and compare mode is selected for the outputs COUTx the output signal of the 10 bit compare unit typically a higher frequency signal is switched modulated to the COUTx pin The state of the corresponding COIN bit at the start of compare timer 1 defines the logic level of the CAPCOM channel output signal at which the COMP output signal is output to COUTx COIN is set The COMP output is switched to COUTx during the low phase of the CAPCOM channel X signal COIN is cleared The COMP output is switched to COUTx during the high phase of the CAPCOM channel X signal Semiconductor Group 6 63 SIEMENS On Chip Peripheral Components C508 Bit Function CMSELx2 0 CAPCOM capture compare mode enable bits x 0 2 The CMSEL registers are used to select enable the operating mode and the output input pin configuration of the capture compare channels Each CAPCOM channel can be programmed individually either for compare or capture operation CMSEL x2 CMSEL x1 CMSEL x0 Mode Compare outputs disabled No compare output signal is generated CCx and COUTx are normal I O pins Compare output on pin CCx enabled COUTx is normal I O pin Compare output on pin COUTx enabled CCx is nor
259. upt is serviced first then the second and the third and the fourth when available The interrupt groups are serviced from top to bottom of the table A low priority interrupt can itself be interrupted by a higher priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure which is illustrated in Table 7 2 The priority within level structure is only used to resolve simultaneous requests of the same priority level Semiconductor Group 7 23 SIEMEN Interrupt System S C508 7 4 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2
260. ure 10 7 Write Read Lock Bit Waveform Semiconductor Group 10 11 SIEMENS OTP Memory Operation C508 10 7 Access of Version Bytes The C508 4E and C508 4R provide three version bytes at address locations FC y FDH and FEy The information stored in the version bytes is defined by the mask of each microcontroller step Therefore the version bytes can be read but not written The three Version Registers hold information as manufacturer code device type and stepping code For reading of the version bytes the control lines must be used according to table 10 2 and figure 10 8 The address of the version byte must be applied at the port 2 address lines PALE must not be activated PMSEL1 0 PALE Port 2 Figure 10 8 Read Version Register s Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specific device characteristics such as OTP size etc Note The 3 version bytes are implemented in a way that they can be also be read during normal program execution mode as a mapped register with bit RMAP in SFR SYSCON set The addresses of the version bytes in normal mode and programming mode are identical and therefore they are located in the SFR address range The steppings of the C508 versions will contain the following version register byte information Stepping Version Byte 0 VRO Version Byte 1 VR1 Version Byte 2 VR2 mapped addr FCH mapped addr
261. ust be cleared by the interrupt service routine Semiconductor Group 6 30 SIEMENS On Chip Peripheral Components C508 Reload of Timer 2 The reload mode for timer 2 is selected by bit T2R in SFR T2CON Figure 6 14 shows the configuration of timer 2 in reload mode When timer 2 rolls over from all l s to all 0 s it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16 bit value in the CRC registers which are preset by software The reload will happen in the same machine cycle in which TF2 is set thus overwriting the count value 00004 Timer 2 Interrupt Request Ea Figure 6 14 Timer 2 in Reload Mode Semiconductor Group 6 31 SIEMENS On Chip Peripheral Components C508 6 2 2 3 Compare Function of Registers CRC T2CC1 to T2CC3 The compare function of a timer register combination can be described as follows The 16 bit value stored in a compare capture register is compared with the contents of the timer register If the count value in the timer register matches the stored value an appropriate output signal is generated at a corresponding port pin and an interrupt is requested The contents of a compare register can be regarded as time stamp at which a dedicated output reacts in a predefined way either with a positive or negative transition Variation of this time stamp somehow changes the wave of a rectangular output signal at a port pin This may as a variation of the dut
262. uts then the input line from the port pin to the interrupt system is disconnected but the pin s level can still be read under software control Thus a change of the pin s level will not cause a setting of the corresponding interrupt flag In this case the interrupt input is directly connected to the internal compare signal thus providing a compare interrupt The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next compare match The principle is that the internal compare signal generated at a match between timer count and register contents not only manipulates the compare output but also sets the corresponding interrupt request flag Thus the current task of the CPU is interrupted of course provided the priority of the compare interrupt is higher than the present task priority and the corresponding interrupt service routine is called This service routine then sets up all the necessary parameters for the next compare event Advantages when using compare interrupts First one is that there is no danger of unintentional overwriting a compare register before a match has been reached This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count Second and the most interesting advantage of the compare feature is that the output pin is exclusively controlled by hardware therefore completely in
263. version Bus Write to ADDATL m Shaded bit locations are not used in ADC functions Figure 6 49 Block Diagram of the A D Converter Semiconductor Group 6 116 SIEMENS On Chip Peripheral Components C508 6 5 2 A D Converter Registers This section describes the bits functions of all registers which are used by the A D converter Special Function Register ADDATH Address D9y Special Function Register ADDATL Address DA Reset Value 00y Reset Value OOXXXXXXp Bit No MSB LSB 7 6 1 0 D9H or 8 3 2 DAH a ERR E a ADDATH ADDATL The registers ADDATH and ADDATL hold the 10 bit conversion result in left justified data format The most significant bit of the 10 bit conversion result is bit 7 of ADDATH The least significant bit of the 10 bit conversion result is bit 6 of ADDATL To get a 10 bit conversion result both ADDAT registers must be read If an 8 bit conversion result is required only the reading of ADDATH is necessary The data remains in ADDAT until it is overwritten by the next converted data ADDAT can be read or written under software control If the A D converter of the C508 is not used register ADDATH can be used as an additional general purpose register Semiconductor Group 6 117 SIEMENS On Chip Peripheral Components C508 Special Function Register ADCONO Address D8j Reset Value 00X00000p Special Function Register ADCON1 Address DC Reset Va
264. version a new A D conversion is triggered automatically until bit ADM is reset The busy flag BSY ADCONO 4 is automatically set when an A D conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect The interrupt request flag IADC IRCON 0 is set when an A D conversion is completed The bits MXO to MX2 in special function register ADCONO and ADCON1 are used for selection of the analog input channel The bits MXO to MX2 are represented in both registers ADCONO and ADCON 1 however these bits are present only once Therefore there are two methods of selecting an analog input channel If a new channel is selected in ADCON 1 the change is automatically done in the corresponding bits MXO to MX2 in ADCONO and vice versa Port 4 is an input port These pins can be used either for digital input functions or as the analog inputs of the A D converter If less than 8 analog inputs are required the unused inputs are free for digital input functions Any inputs which are not used at all should be connected to Vas Semiconductor Group 6 115 SIEMENS On Chip Peripheral Components C508 Internal IEN1 B8y Bus peres se es e Jak IRCON CO BAHEA P4 DBH ADCON1 DCH poc spoci T wee wxi wok ADCONO D8 Port 4 A D Clock Converter 2 z fosc Prescaler Conversion Clock fane 32 16 8 4 Varer Vacno Start of Internal con
265. watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds Then the watchdog circuitry detects a failure condition for the on chip oscillator because they have not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the gated PLL clock output as described in the previous section As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state The exception is Port 1 which will be at its default state when external reset is active see also chapter 5 of this manual Semiconductor Group 8 8 SIEMENS Power Saving Modes C508 9 Power Saving Modes The C508 provides two basic power saving modes the idle mode and the power down mode Additionally a slow down mode is available This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode 9 1 Power Saving Mode Control Registers The functions of the power saving modes are controlled by bits which are located in the special function registers PCON and PCON1 The SFR PCON is located at SFR address 87 4 PCON1 is located in the mapped SFR area RMAP 1 at SFR address 88y Bit RMAP which controls the access to the mapped SFR area is loca
266. watchdog unit starts operation The on chip oscillator takes about typ 5ms to stabilize 4 The PLL will be locked within 1ms after the on chip oscillator clock is detected for stable nominal frequency Subsequently the microcontroller starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be executed after wake up is 0O7By ALE and PSEN are in their power down state up to this time At the end of phase 4 the CPU processes the interrupt call and during these two machine cycles ALE and PSEN behave as shown in Figure 9 1 i e at the begining of phase 5 Instruction fetches during the interrupt call are however discarded 5 After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode double instruction sequence will be executed The functionality of the peripheral units timer 0 1 2 capture compare unit and WDT are frozen until end of phase 5 All interrupts of the C508 are disabled from phase 2 until the end of phase 5 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine The procedure to exit the software power down mode via the P5 7 INT7 pin is identical to the above procedure except that in this case pin P5 7 INT7 replaces pin P3 2 INTO and bit WS in SFR PCON1 should be set prior to entering software power down mode 9 5 State o
267. xT COUTxT x 0 2 Compare output level in trap condition Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd positions 1 3 5 are assigned to the COUTx compare outputs CCxT COUTxT 0 If the compare timer is running the compare channel output CCx COUTx x 0 2 will be switched to 0 level in trap state if the channel is enabled for trap function CCxT COUTxT 1 If the compare timer is running the compare channel output CCx COUTx x 0 2 will be switched to 1 level in trap state if the channel is enabled for trap function Semiconductor Group 6 73 SIEMENS On Chip Peripheral Components C508 6 3 3 Compare COMP Unit Operation The Capture Compare Unit CCU of the C508 also provides an 10 bit Compare Unit COMP which operates as a single channel pulse generator with a pulse width modulated output signal This output signal is available at the output pin COUTS of the C508 In the combined multi channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx or CCx Figure 6 32 shows the block diagram and the pulse generation scheme of the COMP unit e g initial value of COUTS is set to 0 To CAPCOM Output Control Compare Registers CMP2H CMP2L COUTXI COINI 6 Pulse 2f OSC Generation Programmable Prescalar Period Registers CP2H C
268. y cycle of a periodic signal be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms Two compare modes are implemented to cover a wide range of possible applications The compare modes 0 and 1 are selected by bit T2CM in special function register T2CON In both compare modes the new value arrives at the port pin 1 within the same machine cycle in which the internal compare signal is activated The four registers CRC T2CC1 to T2CC3 are multifunctional as they additonally provide a capture compare or reload capability reload capability for CRC register only A general selection of the function is done in register CCEN Please note that the compare interrupt CCO can be programmed to be negative or positive transition activated The internal compare signal not the output signal at the port pin is active as long as the timer 2 contents is equal to the one of the appropriate compare registers and it has a rising and a falling edge Thus when using the CRC register it can be selected whether an interrupt should be caused when the compare signal goes active or inactive depending on bit I3FR in T2CON For the CC registers 1 to 3 an interrupt is always requested when the compare signal goes active see Figure 6 16 6 2 2 3 1 Compare Mode 0 In mode 0 upon matching the timer and compare register contents the output signal changes from low to high It goes back to a low level on timer
269. y of this document Please send your proposal including a reference to this document to I mcdocu comments siemens scg de SIEMENS General Information C508 Semiconductor Group l 4 SIEMENS General Information C508 Contents Page 1 Introduction lt A SS NS ei PD RAE PUN IS 1 1 1 1 Fri CONMGUFALION sies rne DP RR QU DE oe Sa Rot Bod gd 1 4 1 2 Pin Definitions and Functions iio da CEREREM 1 6 2 Fundamental Structure 23 22 a ia 2 1 2 1 CRU ias re e ver cedes La qe taa ds 2 3 2 2 CPU du sites pecu E tata seer ES ca qe bu 2 5 3 Memory Organization lleeeeeeere IIIA 3 1 3 1 Program Memory Code Space roses ep ERE RENE E UE REQUE P eo 3 2 3 2 Data Memory Data Space ener aaa ane ase ades us aia 3 2 3 3 General Purpose Registers 0 000 eee eee 3 2 3 4 XRAM Operation parara P ERE Rod ER dia Pesto tei uae race eve Egon 3 3 3 4 1 XRAM Controller Access Control ooocoocccocc 3 3 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode 3 5 3 4 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode 3 5 3 4 4 Reset Operation of the XRAM o ooocooocccco ree 3 9 3 4 5 Behaviour of Port 0 and POTE us mts Roe Sant Rma dte pet abt tuu Cee ee 3 9 3 5 Special Function Registers xu dia Ged fle ee ig eed Ere ones 3 11 4 External Bus Interface ais oasis od 4 1 4 1 Accessing External Memory societaria Nd 4 1 4 1 1 Role of PO and P2 as Data Address BU

8-Bit CMOS Microcontroller User`s Manual 06.99 http://www.siem

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