Home

56F803 - NXP Semiconductors

Contents

1. TISIHNI 03d i Wi WOO WEIS v ONISSONO OHSZ 41 15 55082 0937 944 Odd HQE WMd 934 Tor ana ove aNg oy 6 ava v aswa M8 8 LE 9 X 2 86 196 0537 a ee SSO OWT 24d IISIHNI 039 WOO 74836 E ASNES SHDIVNHdWRL HAIN SNV 9 5 SLOH HSNES INMRNO 8 SSVHd NOLOW g gHd EN ve ez SI WHd INV gd S I a aa S A ONY Sr IND e vu Sr E IND VAE E O 3 S EINN A0 s s 0 6 T WMd 8 L ENMd 9 5 ZWMd INMd ev wu 2 i OWMd zx waa ANWAS SAING NOLON ASNES O ZSNES INSNSDO V HOLOHNNOO INN 56F803EVM Schematics Rev 5 Appendix A 11 Freescale Semiconductor SsJ0j29Jeg Indu Bojeuy su s ju911n9 pue 4 3 L 2 v vi JO 19945 sjooj 61590 8661 zz eunp Kepuow 9180 Joqwn 9948 SH019313S LNdNI 3SN3S INIHHNO 3SVHd AWS MOVE vi 3O dN 959 568 215 4 0626 568 216 8698 98284 XL unsny 15 UOUUBD 1099 UOISIAIG 19q119SqnS sse 841M 5 9 lt SI Nv
2. 2 25 Zw 2 25 Appendix 56F803EVM Schematics Appendix B 56F803EVM Bill of Material DSP56F803EVM User Manual Rev 5 ii Freescale Semiconductor 1 1 1 2 1 3 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 1 2 3 4 5 6 7 8 9 10 LIST OF FIGURES Block Diagram of the 56F803EVM 1 2 S6F8035VNI OMR passa dowd adcer 1 3 the SOP SUSE 1 4 Schematic Diagram of the External Memory Interface 2 4 Schematic Diagram of the RS 232 Interface 2 5 Schematic Diagram of the Clock oie pex ode ac EROR AER CR 2 6 Schematic Diagram of the Debug LED Interface 2 7 Block Diagram of the Parallel JTAG Interface 2 9 Schematic Diagram of the User Interrupt Interface 2 10 Schematic Diagram of the RESET Interface 2 11 Schematic Diagram of the Power 2 11 POR 0660561865 525465455435 _ 2 13 PWM Group Interface and LED 2 14 DC Bus Over Voltage and Over Current Detection Schematic Diagram 2 15 Primary Back EMF or Motor Phase Current Sense Signals 2 16 Zero Crossing Encoder
3. Figure 2 7 Schematic Diagram the RESET Interface 2 10 Power Supply The main power input 12V DC at 4 0A to the 56F803EVM is through 2 1mm coax power jack A 4 0A power supply is provided with the 56F803EVM however less than 500mA is required by the EVM The remaining current is available for user motor control applications The 56F803EVM provides 3 3V DC voltage regulation for the device memory RS 232 CAN parallel JTAG interface and supporting logic refer to Figure 2 8 Power applied to the 56F803EVM is indicated with a Power On LED referenced as LEDI 12V DC 5 0V 3 3V Regulator Regulator 56F803EVM Figure 2 8 Schematic Diagram of the Power Supply Technical Summary Rev 5 Freescale Semiconductor 2 11 2 11 UNI 3 Interface Motor control signals from a family of motor driver boards can be connected to the EVM board via the UNI 3 connector interface The UNI 3 connector interface contains all of the signals needed to drive and control the motor drive boards These signals are connected to differing groups of the device s input and output ports A D TIMER and PWM Refer to Table 2 7 for the pin out of the UNI 3 connector Table 2 7 UNI 3 Connector Description Pin Signal Pin Signal 1 PWM AT 2 Shield 3 PWM AB 4 Shield 5 PWM BT 6 Shi
4. 2 17 CAR TV KE u Lu RTI RI T T T TT TIT 2 18 o c r A 2 Reset Mode Clock ROSE 223 H4 casa A 3 Program amp Data SRAM Memory A 4 RS 232 ang OO OMR etre RT ESSA dE Pp 5 5 803 PWM LEDs and Uger LED dg arde aae A 6 UNI 3 Over Voltage and Current Sense A 7 Zero Crossing Encoder or Hall Effect Selection A 8 High Sp d CAN eee oe s s s os RE A 9 Port Timer D Address Data A D and Control Line Connectors A 10 UNI 3 Interface and General Purpose Switches A 11 List of Figures Rev 5 Freescale Semiconductor iil A 11 Back EMF and Phase Current Sense Analog Input Selectors A 12 A 12 Parallel JTAG Host Target Interface and JTAG Connector A 13 A 13 Power Supplies and 5 0V A 14 A 14 Bypass Capacitors and Spare A 15 DSP56F803EVM User Manual Rev 5 iv Freescale Semiconductor 1 1 2 1 2 2 23 2 4 25 2 6 2 7 2 8 2 9 2 10 sd av 2 43 2 14 2 15 2 16 2 17 2 18 LIST OF TABLES S6F803EVM Default Jumper Options 1 3 RS 232 Serial Connector Dese fipti n Celadon eens 2 5 Liner d ded be EA EI a
5. Appendix 14 s eo oJedg pue ssojidede ssed g 21n614 Appendix A 15 T z Y 5 vi JO 19945 sjooy ueuBiseq 8661 22 eunp Aepuow 19180 z J qun 0 0898450 azs LE S31V9 34VdS 5 110 4 0 SSVdAS ars L 12 ars 999 968 219 Xv3 02 968 215 TE SALLE wh i 00VrL 8658 56 8 658 sen ocn uouue 1099 T UOISIAIG 1991054 5 SS9 81 M mm 00VbL ely ars esd 1 5 azin azin man snl x i xu NR i We Om nh P EN moo amo E amo moo anro anor EU anyo ANWIL 70297 snd UOLSHNNO sna SSWHIGQV anyo anyo 819 9TTZLSD VA INA LIOA 0 5 INn 820 i 29 VAG Et AG et ATTEENAY HOLOSNNOO UHCVHH L go L L ao 010 60 i D 0849S5dSQ 56F803bEVM Schematics Rev 5 F
6. BUISSO19 0197Z 77 JO 4 1994 1001 juewdojsneg 8661 zz Aepuon ejeq EL V ge 5 EUN MAC Jequun 5 NSQ WA3E089SdSQ 925 9 NId 8 S NId NOILO313S 193443 HICOONI 55 0832 HSVHd i 3O dW 996 568 215 4 0626 568 216 V 5 Nid 8698 96 8 XL unsny _ Nid ISOM uouue 1059 AO S t Nid UOISIAIG 49411254 6 ssoJ 8JIM J I CIOLLOHNNOO NORS his LSH ve 954 n a lt lt 8 A0 G olor K 299 P 5 L 39027 T m 059 OSH er 24 08 Jnz z 39027 0 80 i 670 874 178 9 0 08444 A0 S TIVH Z Asa NOLLWWYOANT ONISSOHO 6 em 8 x ouaz LOANNOO v x 0437 ONISSOMO Freescale Semiconductor DSP56F803EVM User Manual Rev 5 Appendix A 8 NYD 8 vi 10 g 1994 1001 juawdojaneg 19 61590 0002 So 91 gt Joaquin NSQ WA3e089sdsd ance 9219 3OVdH3lNI NYO 93395
7. sou 294 g gr ano E 2 215 r9 92 QN9 Por I ars 99 I 257 1997 99N Fog v 1881 19097 5 Agero a r ie a LE 1 eve T0L 1HOd 3 Lvai L ZAZ ave oval ZAZ 2 2 21 we LE MBI Teed SWI 1904 t VAL VAL evi Fg or 5 13838 1809 z 2 r e AL Y ST tas t ivi RENI INGO 1804 56F803EVM Schematics Rev 5 Appendix 13 Freescale Semiconductor Freescale Semiconductor g T g A ee i VE ester GND AE EF VAE ET I UOLVINDHU pdl 40 5 ANY ENA p AVAN SE 8 Bn gt ano NIA E 2 en 1 ER avag 5 VAS 5 ONS e 5 a o D gt LL 9 n o a E e 05 10692660201 mo L We ACT INdNI y 100 c x 2 LNOA NIA t NR 4 ke 2 an NI 10004 M
8. vi 3O QN 959 568 215 XV4 0626 568 216 8698 96 8 XL ulysny ISOM 1099 UOISIAIG 19q119SqnS 55 1052228 24 34015 INYO er d3HA axy 99A QXL HOLOSNNOO SNA NYD NIVHO ASIXG HOLOZNNOO 5 NYD A0 S XH lt NVOSW 56F803bEVM Schematics Rev 5 Appendix A 9 Freescale Semiconductor sio 5 uuoo pue q y ssaippy Jeu HOd 6 T 2 D T 5 40 6 19945 001 jueudoje eq ueuBiseq 9661 zz Aepuow 199920 8 3 5 J qun 07 380899450 SHOLOANNOO S3NI11OH1NOO NV Q V VLVYG SSIHGGV 1809 998 668 219 0606 568 215 8698 96 8 XL unsny neger 9 5 T 198A UOUUeD 1099 on ore UOISIAIG 1 SS9 91IM L Od Ids S IVNOIS MWA 105 n I rat L Or IHNNVHO ANIL Age I 9r Sr tig nos did mecum a 90 Nett a zd 0 6 0 6 O70 2 L LNY 8 4 9NV 8 L sq
9. Hig gt ono gg VSSA e 25 gt aq 91 H dois rawis NV NV 10081X3 10081X3 9Nv 13638 57 13834 SNY Fa NY LNHUUND O 8 SSVHi INXSSDO ze ENV 808 LE sour HSVHd INXNSDO V ZNV TS NV Hie sna INY INY SOWLIOANSAO SME ONV er ONY UM re M anya INSHHDONSAO 508 DA HINYA SU oz 5 Sal LINE SNE 0110 4 eyed vsi 91 sia ASNAS INHAAND ASVHd ovSi vid SVWMd WAN NOILWIOGOW HLGIM 570 ZYNMd LYNMd Xu NYOSW NVOSNW NYO e axy 13d 00XH TET SA 03d 0QXL NISSOND ONEZ 244 zal Dad LK tL nin gg SVU03WOH Swirly zv L OX3QNI SV ELV 1V1 083SVHd EAU vaSvHd yg OVLIOVASVHd woo SS 34 88 26 LIGIHNI 24d MIOS il 739158 8 TOULNOD miwa OSINY 93d OSIN SAd ISON 234 9 sv 158 1591 a ae lon D DULL s SNL M XOL pg ov DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Appendix A 2 15084 9
10. The PWM port is attached to this connector Refer to Table 2 18 for connection information Table 2 18 PWM Port Connector Description J4 Pin Signal Pin Signal 1 ISAO 2 ISA1 3 ISA2 4 FAULTO 5 FAULT1 6 FAULT2 7 PWMO 8 1 9 PWM2 10 PWM3 11 12 5 13 GND 14 3 3V 2 20 Test Points The 56F803EVM board has nine test points Five near the breadboard 3 3V GND 3 3VA AGND and 5 0V and four near the UNI 3 connector 15VA GND 15VA and GND Technical Summary Rev 5 Freescale Semiconductor 2 25 DSP56F803EVM User Manual Rev 5 2 26 Freescale Semiconductor Appendix 56F803EVM Schematics 56F803EVM Schematics Rev 5 Freescale Semiconductor Appendix A 1 JosseooJd 08499 V T 2 l JO 19945 9001 19001891 8661 zz Aepuow 19180 NSQ WA3 089sdSQ jueunooq 8 ISQUNN z 105592014 60895450 11 30 0N 955 568 215 4 0626 568 215 8698 5628 XL urisny 2A11Q UOUUeD 1059 UOISIAIG 19411254 lt sso aJIM INANI 0908508499459 L oanos LE LL ane aan SSA 20 19 19 gan ssa LE tc 82 SSA VD Hy WAX OdvOA WIX 7
11. 56F803 Evaluation Module User Manual 56F800 16 bit Digital Signal Controllers DSP56F803EVMUM Rev 5 07 2005 freescale com NA freescale semiconductor NA 1 1 1 2 L3 2 1 2 2 2 3 2 4 2 5 2 6 T 27 1 2 7 2 2 8 29 2 10 2 11 2 14 2 13 2 14 2 14 1 215 TABLE OF CONTENTS Preface vii vil dci reU 2225454 53 lie uuu u Definitions Acronyms and Abbreviations 1X CT P X Chapter 1 Introduction AUC Ray ae nasale Eds gt 1 2 56F803EVM Configuration Jumpers 1 3 lt 654 1 4 Chapter 2 Technical Summary nn ne nt be ab DRE RE ES 2 2 Program ceres 8h ide Oll 2 4 RS 232 Serial Communications 2 5 ono vr 2 6 MORE PR EE Vac ded Ro 2 6 ah PAS ose 2 7 Debug Support 2 7 de gt 2 7 Parallel JTAG Interface Connector 2 8 aE 2 10 BON PR ERE d
12. Ag e ATavSIQ Wvas RE 318VN3 WVYS DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Appendix A 4 S10 98UU09 195 pue ZEZ SH 21614 vi 10 p 19945 1001 juawdojaneg 19 61590 8661 zz Aepuon 91 V Joaquin NSQ WA3e089sdsd 2215 SYOLOANNOO 195 0262 5548 vi 3O QN 959 568 215 XV4 0626 568 216 8698 96 8 XL ulysny 1 9M UOUUEO 1069 UOISIAIG 4 4 1254 6 SS9J9IIM 894 Suvdlieewav NISE SL 91 NICE ZL NIZE 8t 61 axa 0841 gt gt 02 2 6 41 ke 22 NIEL NIZI lt axi i ve AO LOANNOD IZ cec sa into 775 E 92 m IOS 675 270 82 5 FH 075 L 2 v S 56F803bEVM Schematics Rev 5 Appendix A 5 Freescale Semiconductor L 431 4 pue sq31 608 496 9 4 Jo S 19945 81001 8661 zz unf Aepuon 1 V NSQ WA3 089SdSQ juauinooq 9215 5 5831 WMd 20899858 71530 9997 968 219 4 0622 968 219 8668 6684 XL unsny ISOM UOUUBD 1099 UOISIAIG 18q112SqQNS SS9J81IM 00
13. 1 N3349 AS e b 2 lt lt Ison vain AASA 4450 gt S lt 00 Jorn vWMd 131 MOTISA Diss a 30140 N33H9 00 qoin gt e 5 Q31M0113A 7 940 ieu Jorn 00 7 z lt N33H5 Diss oz osy v00VvZ gorn 041 MOTI3A 042 ALLS voin Ag et DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Appendix A 6 su s pue S INN 9 V 4 10 9 1994 5001 18UBIS8q 8661 zz eunr Aepuow 910 el 8 9 J qun NSC WA38089SdS Q jaana oN eus 3 3 133409 ANY 39V110A H3AO INN 1630 0W 9597 568 219 XV3 0626 968 21 8698 96 8 AAG UOUUBD 1059 UOISIAIG 1 ql19sqnS 55 lt Ars ldnva4 LINYA INN onya lt lt HSNHS LINYA i s I lt SNAS LNHNHOO AE NOILDHLHC HOVL IOA 4HAO INN SNAS HOVI IOA 56F803EVM Schematics Rev 5 Appendix A 7 Freescale Semiconductor 6 1994 7 2H 10
14. gt gt lt 60 INV 2 L ONY 2 L qu or T ST 0 AOLOHNNOOD 51 SANIT ST 8 V SNId 5 SSHHGGV HAVHS 0 O 8 LL 9 s IV i FIV api el 8 L SWMd e re y 9 5 01 6 tV v ZV 8 1 aie w FIVE H zi HOLOSNNOD 2 Xu NVOSN 191 2 051 TVNOIS jp lt T MYA ST 0 SNd 55 DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Appendix A 10 sayaJims sodind 9 pue INN 0L V 4 JO 1994 5001 1ueudojeneg 21906189 8661 9 e a 8 NSd NA3E089S4S q jueunooq SAHOLIMS 3SOdHNd 1VH3N3d9 39V3H3INI IND 630 04 9597 568 219 XVA 0626 968 21 8658 55 8 XL UNSNY IS8M UOUURD 1059 UOISIAIQ 49411285416 SS9 811M 1846 MS NV lt lt 6 s E HOLIMS dOLS NAN aw WAST T ano wast SLINIOd LISAL 17s LIAIHNI Odd WOO 5
15. lt S oes A v lt 8 999 lt SI vHd lt v 4Wwa 88 q L 2 v DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Appendix A 12 10 98UU09 pue 1 Sv f IelleJed ZL V z vi JO 19946 sjooy uawdojaneg 8661 zz 22180 el NSa WAae089sdsa megen azs 32 48 13931 LSOH 9 1 1311VHVd 956 568 219 4 0626 568 219 8698 96 8 XL ISOM uouueg 1059 UOISIAIG 19ql19sqnS SSAIM FE gt IJ63H d FETIS 2 KAD AVS H 383 8 n 13938 _ Hm E 5 xor Ag E lt 2 L gt lab su M LHSHU OVILC 5 Ae et ST Lasau es FR sal 15 2 TOSNNOT IBOd r anro 19804 0 xm Q ASCH DON THOd 5 pzeog uo Tos e LL
16. 14 group signals 14 LEDs 14 outputs 14 signals 14 PWM compatible peripheral 1 Q Quad Encoder 17 Quadrature Encoder Hall Effect 17 DSP56F803EVM User Manual Rev 5 Index 2 Freescale Semiconductor R Z RAM ix Zero Crossing Random Access Memory RAM ix Read Only Memory ROM ix real time debugging 7 ROM ix RS 232 cable connection 4 interface 5 Schematic Diagram 5 RS 232 interface 1 S SCI ix Serial Communications Port 23 SCI compatible peripheral 1 Serial Communications Interface SCI ix Serial Peripheral Interface Port SPI ix SPI ix Serial Peripheral Interface 24 SPI compatible peripheral 1 SRAM ix external data 1 external program 1 Static Random Access Memory SRAM ix T test points 25 Timer Channel 21 Timer compatible peripheral 1 U UART ix UNI 3 interface connector 14 16 Motor interface 2 UNI 3 connector interface 12 Universal Asynchronous Receiver Transmitter UART ix Index Rev 5 Freescale Semiconductor Index 3 DSP56F803EVM User Manual Rev 5 Index 4 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Informati
17. 42019 PO Joso4 Z Y 2 I n 2 19945 soo 198 61590 0002 01 Aepuon 94eq E L E K Jequun 184 NSQ WA3 0895dsd zIS 0010 S3qON ISIH eni 71530 9 999 68 1 4 0626 568 216 8698 98 15 9 UOISIAIG 49414155915 84 XL unsny 1059 SSaJe1IM lt lt I INI i roog NOLLNGHSNd LASHA 13S3u X 75 55 NOLINGHSNd L ZHNW00 8 418 WOL uld T SSWdAH DSO 959 voul lt lt 25 NOLINIHSAd 919 56F803EVM Schematics Rev 5 Appendix A 3 Freescale Semiconductor NVYS 9 vy anbi4 L JO 1994 1001 194615 8661 zz Aepuow 9124 V NSQ WA3e089SdSQ Jequiny 9215 AYOWAW WVHS VIVA PUE WYHOOUd 71530 955 568 215 4 0626 568 216 8698 98 8 XL ullsny ISOM UOUUBO 1099 UOISIAIG 19911259 5 5591941 a lt lt lt lt lt 8170103 arq 9rxNv9 pue 3 9
18. Connector s JTAG OnCE Power Supply 3 3 V amp GND 3 3V 5 4 3 3VA Figure 1 1 Block Diagram of the 56F803EVM DSP56F803EVM User Manual Rev 5 DSub 9 Pin Zero Crossing Detect Freescale Semiconductor 56F803EVM Configuration Jumpers 1 2 56F803EVM Configuration Jumpers Ten jumper groups JG1 JG10 shown in Figure 1 2 are used to configure various features on the 56F803EVM board Table 1 1 describes the default jumper group settings Figure 1 2 56F803EVM Jumper Reference Table 1 1 56F803EVM Default Jumper Options Connections JG1 UNI 3 serial selected 1 2 3 4 5 6 amp 7 8 JG2 Enable on board Parallel JTAG Command Converter Interface NC JG3 Use on board crystal for oscillator input 1 2 JG4 Selects device s Mode 0 BOOT From FLASH operation upon exit from 1 2 reset JG5 Enable external SRAM 1 2 JG6 UNI 3 3 Phase Current Source Selected 2 3 5 6 amp 8 9 JG7 Encoder Input Selected 2 3 5 6 amp 8 9 JG8 On board Parallel JTAG Command Converter powered by Host System 1 2 JG9 Use on board crystal for oscillator input 1 2 9610 Leave bus un terminated NC Introduction Rev 5 Freescale Semiconductor 1 3 1 3 56F803
19. Manual Rev 5 viii Freescale Semiconductor Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference A D Analog to Digital CAN Controller Area Network serial communications peripheral and method CiA CAN in Automation an international CAN user s group that coordinates standards for CAN communications protocols EVM Evaluation Module GPIO General Purpose Input and Output Port IC Integrated Circuit JTAG Joint Test Action Group a bus protocol interface used for test and debug LQFP Low profile Quad Flat Pack MPIO Multi Purpose Input and Output Port shares package pins with other peripherals on the chip and can function as a GPIO OnCE On Chip Emulation a debug bus and port created by Freescale to enable designers to create a low cost hardware interface for a professional quality debug environment PCB Printed Circuit Board PLL Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory ROM Read Only Memory SCI Serial Communications Interface SPI Serial Peripheral Interface Port SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter Preface Rev 5 Freescale Semiconductor ix References The following sources were referenced to produce this manual 1 DSP56800 Family Manual Freescale Semiconductor DSP56800FM 2 DSP56F801 803 805 807 User s Manual Freescale Semicond
20. RESET P2 Pin Signal Pin Signal 1 NC 14 NC 2 PORT RESET 15 PORT IDENT 3 PORT TMS 16 NC 4 PORT TCK 17 NC 5 PORT TDI 18 GND 6 PORT TRST 19 GND 7 NC 20 GND 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT Technical Summary Rev 5 Debug Support Freescale Semiconductor Table 2 6 On Board Host Target Interface Power Source Jumper Selection JG8 Comment 1 2 Host supplied power 2 3 Target supplied power 2 8 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Figure 2 9 S2 allows the user to generate a hardware interrupt for signal line IRQA S3 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 56F803 IRQA Figure 2 6 Schematic Diagram of the User Interrupt Interface DSP56F803EVM User Manual Rev 5 2 10 Freescale Semiconductor Power Supply 2 9 Reset Logic is provided in the 56F803 to generate a clean power on RESET signal Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button see Figure 2 7 RESET PUSHBUTTON MANUAL RESET
21. TET 2 11 se A E E 2 11 2 pho R 2 12 Eu Eee ER DRE 2 13 Motor Control PWM Signals and LEDSs 2 14 Motor Protection Logic o 2134 eq been ERIT IAS ES 2 14 UNE Motor Protechon uh Laisser or ded ao dos d ao eR ass a d 2 15 Back EMF and Motor Phase Current Sensing 2 16 Table of Contents Rev 5 Freescale Semiconductor i 2 16 Quadrature Encoder Hall Effect Interface 2 17 217 CR 2 17 CAN MEG u gt EE do d 2 18 219 Penpheral 2 19 2 191 External Memory Control Signal Expansion Connector 2 20 2 19 2 Encoder Timer Channel Expansion Connector 2 20 2 19 3 Timer Channel Expansion 2 21 2194 Address Bus Expansion Conmector 2204 2 21 L S De Bus Epson RA haard 2 22 2196 A D Port Expansion Gb EA 2 23 2 19 7 Serial Communications Port Expansion Connector 2 23 2 19 8 Serial Peripheral Interface Expansion Connector 2 24 299 CLAN Expansion COMO daa ad vac doe E CI o ER Ea ERE 2 24 2 19 10 PWM Port Expansion Connector
22. User Manual Rev 5 2 22 Freescale Semiconductor 2 19 6 A D Port Expansion Connector Peripheral Connectors The 8 channel Analog to Digital conversion port is attached to this connector See Table 2 14 for connection information Table 2 14 A D Connector Description J9 Pin Signal 1 ANO 2 AN1 3 AN2 4 AN3 5 AN4 6 AN5 7 AN6 8 AN7 9 GNDA 10 3 3VA 2 19 7 Serial Communications Port Expansion Connector The Serial Communications Port SCI is attached to this connector Refer to Table 2 15 for connection information Table 2 15 SCI Connector Description J12 Pin Signal 1 TXD 2 RXD 3 GND Technical Summary Rev 5 Freescale Semiconductor 2 23 2 19 8 Serial Peripheral Interface Expansion Connector The Serial Peripheral Interface SPI is attached to this connector See Table 2 16 for connection information Table 2 16 SPI Connector Description J6 Pin Signal Pin Signal 1 SCLK 2 MOSI 3 MISO 4 55 5 GND 6 3 3V 2 19 9 CAN Expansion Connector The CAN port is attached to this connector Refer to Table 2 17 for connection information Table 2 17 CAN Connector Description J5 Pin Signal 1 MSCAN TX 2 MSCAN RX 3 GND DSP56F803EVM User Manual Rev 5 2 24 Freescale Semiconductor 2 19 10 PWM Port Expansion Connector Test Points
23. ability to examine and modify all user accessible registers memory and peripherals through the OnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The OnCE port s unobtrusive design means that all of the memory on the board and on the chip are available to the user Introduction Rev 5 Freescale Semiconductor 1 1 1 1 56F803EVM Architecture The 56F803EVM facilitates the evaluation of various features present in the 56F803 part The 56F803EVM can be used to develop real time software and hardware products based on the 56F803 The 56F803EVM provides the features necessary for a user to write and debug software demonstrate the functionality of that software and interface with the customer s application specific device s The 56F803EVM is flexible enough to allow a user to fully exploit the 56F803 s features to optimize the performance of their product as shown in Figure 1 1 MODE IRQ LOGIC Program Memory 64Kx16 bit Data Memory 64Kx16 bit Memory Expansion Connector s JTAG Connector DSub Parallel 25 Pin JTAG Interface 56F803 Low Freq XTAL EXTAL Crystal RS 232 Interface MODE IRQ Address Data amp Peripheral Control Expansion
24. 0456 6 1 6 x 2 Bergstick J8 SAMTEC TSW 106 07 S D Test Points 9 1 x 1 Bergstick 1 TP2 5 TP6 Samtec TSW 101 07 S S TP7 8 9 Crystals 1 8 00 2 Crystal Y1 ECS 80 18 5P Connectors 1 20 x 2 Shrouded P1 3M 2540 6002UB 1 DB25M Connector P2 AMPHENOL 617 C025P AJ121 1 2 1mm coax P3 Switch Craft RAPC 722 Power Connector 1 DE9F Connector P4 AMPHENOL 617 C009S AJ120 Switches 1 SPDT Toggle S1 C amp K GT11MSCKE 3 SPST Pushbutton S2 S3 S4 Panasonic EVQ QS205K Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 11 Shunt SH1 SH11 Samtec SNT 100 BL T 6 Rubber Feet RF1 RF6 3M SJ5018BLKC 56F803EVM Bill of Material Rev 5 Freescale Semiconductor Appendix B 3 DSP56F803EVM User Manual Rev 5 Appendix B 4 Freescale Semiconductor INDEX Symbols 12VDC power supply 4 Numerics 4 0Amp power supply 11 56F803 Technical Data x 64Kx16 bit of data memory 1 64Kx16 bit of program memory 1 8 00MHZ crystal oscillator 1 A A D ix A D Port 2 Analog to Digital A D ix Back EMF signals 16 voltages 16 C CAN ix bus termination 1 bypass 1 interface 1 CAN in Automation CiA ix CAN interface 1 CAN physical layer peripheral 1 CAN Specification 2 0B x CiA ix CiA Draft Recommendation DR 303 1 Cabling and Connector Pin Assignment x Connector A D 23 Address bus 21 CAN 24 Data bus 22 Encoder Timer Channel 20 External Memory Control 20 PWM 25 SCI 23 SPI 24 Timer C
25. 2 6 JTAG Connector 5434 ne EXEAT XN E 2 8 Parallel JTAG Interface Disable Jumper Selection 2 8 Parallel JTAG Interface Connector Description 2 9 On Board Host Target Interface Power Source Jumper Selection 2 10 UNES Connector Description ss kieke sakini 2 12 CAN Header DOSCOPDEBSOIL ss css 2 19 External Memory Control Signal Connector Description 2 20 Timer Congector D C DUR cd can PAR GERE EM RR 2 20 Tuner D Connector Descriptio io 4465046455 S rh RI RU ERR eR ESI 2 21 External Memory Address Bus Connector Description 2 21 External Memory Address Bus Connector Description 2 22 A D Connector Description s AREE RR RACE CERO 2 23 SCI Connector Description 2 23 Connector Description 2 24 CAN Connector Sk 0 0064s da xii ded 2 24 PWM Port 2 25 List of Tables Rev 5 Freescale Semiconductor V DSP56F803EVM User Manual Rev 5 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56F803 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freesca
26. 803EVM User Manual Rev 5 2 20 Freescale Semiconductor Peripheral Connectors 2 19 3 Timer Channel Expansion Connector The Timer Channel port is a GPIO timer port attached to the Timer D expansion connector See Table 2 11 for the signals attached to the connector Table 2 11 Timer D Connector Description J10 Pin Signal 1 TD1 2 TD2 3 GND 4 3 3V 2 19 4 Address Bus Expansion Connector The 16 bit Address bus connector contains the controller s external memory address signal lines The upper 8 bits A8 A15 can also be used as Port A GPIO lines See Table 2 12 for the Address bus connector information Table 2 12 External Memory Address Bus Connector Description J7 Pin Signal Pin Signal 1 0 2 1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 A9 11 A10 12 A11 13 A12 14 A13 15 A14 16 A15 17 GND 18 3 3V Technical Summary Rev 5 Freescale Semiconductor 2 21 2 19 5 Data Bus Expansion Connector The 16 bit Data bus connector contains the controller s external memory data signal lines Refer to Table 2 13 for the Data bus connector information Table 2 13 External Memory Address Bus Connector Description J11 Pin Signal Pin Signal 1 DO 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 09 11 010 12 011 13 012 14 013 15 D14 16 D15 17 GND 18 3 3V DSP56F803EVM
27. CK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 NC 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG2 Reference Table 2 4 for this jumper s selection options Table 2 4 Parallel JTAG Interface Disable Jumper Selection JG2 Comment No jumper On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface 2 7 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P2 allows the 56F803 to communicate with a Parallel Printer Port on a Windows PC see Figure 2 5 By using this connector the user can download programs and work with the 56F803 s registers Table 2 5 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG2 should be removed refer to Table 2 4 A jumper JG8 is provided to allow the on board Host Target Interface to be powered by the Target board instead of the Host system as shown in Table 2 6 DSP56F803EVM User Manual Rev 5 2 8 Freescale Semiconductor DB 25 PORT TDI PORT TDO PORT TRST PORT TMS PORT TCK PORT RESET PARALLEL JTAG INTERFACE LOGIC 56F803 Figure 2 5 Block Diagram of the Parallel JTAG Interface Table 2 5 Parallel JTAG Interface Connector Description TDI TDO TRST TMS TCK
28. EC RC73L2A24OHMJT R56 R57 1 120 1 4W R61 YAGEO CFR 120QBK Potentioneters 2 10K O R40 R45 BC MEPCOPAL ST4B103CT Inductors 4 1 0mH L1 L4 Fair Rite 2743015112 LEDs 5 Green LED LED1 LED3 LED5 LEDT Hewlett Packard HSMG C650 LED8 3 Yellow LED LED2 LED4 LED6 Hewlett Packard HSMY C650 Diode 3 FM4001 D1 D2 D3 Vishay DL4001DICT Capacitors 3 2 2uF 50V DC C1 C2 48 UWX1H2R2MCR2GB 32 O 1uF C3 C5 C7 C9 C24 C26 SMEC MCCE104K2NR T1 C30 C31 C35 C36 C39 C47 3 0 01uF C27 C32 C33 SMEC MCCE103K2NR T1 1 470uF 16V DC C4 PANASONIC ECE V1CA471P 2 47uF 10V DC C6 C8 PANASONIC ECE V1AA470P 1 1 50V DC C25 TTI UWT1HO10MCR1GB 4 470pF C49 C52 SMEC MCCE471J2NO T1 Jumpers 4 3 x 1 Bergstick JG3 JG8 J5 J12 SAMTEC TSW 103 07 S S 1 4 x 2 Bergstick JG1 SAMTEC TSW 104 07 S D 5 1 x 2 Bergstick 902 964 JG5 469 JG10 SAMTEC TSW 102 07 S S DSP56F803EVM User Manual Rev 5 Appendix B 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Jumpers Continued 2 3 x 3 Bergstick JG6 JG7 SAMTEC TSW 103 07 S T 3 5 x 2 Bergstick J3 J9 J13 SAMTEC TSW 105 07 S D 1 4 x 1 Bergstick J10 SAMTEC TSW 104 07 S S 1 3 x 2 Bergstick J6 SAMTEC TSW 103 07 S D 2 9 x 2 Bergstick J7 J11 SAMTEC TSW 109 07 S D 2 7 x 2 Bergstick J1 J4 SAMTEC TSW 107 07 S D 1 6 x 1 MTA J2 AMP MTA 64
29. EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12V DC power supply to the 56F803EVM board Parallel Extension Cable 56F803EVM PC compatible Computer ig Connect cable to Parallel Printer port External with 2 1mm 12V receptacle Power connector Figure 1 3 Connecting the 56F803EVM Cables Perform the following steps to connect the 56F803EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P2 shown in Figure 1 3 on the 56F803EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12V DC 4 0A power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external power supply into P3 shown in Figure 1 3 on the 56F803EVM board 5 Apply power to the external power supply The green Power On LED will illuminate when power is correctly applied DSP56F803EVM User Manual Rev 5 1 4 Freescale Semiconductor Chapter 2 Technical Summary The 56F803EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging servo and motor control digital answering machines feat
30. J13 Pin Signal Pin Signal 1 NC 2 NC 3 CANL 4 CANH 5 GND 6 NC 7 NC 8 NC 9 NC 10 NC 2 19 Peripheral Connectors The EVM board contains a group of Peripheral Expansion Connectors used to gain access to the resources of the 56F803 The following signal groups have Expansion Connectors External Memory Control Encoder Timer Channel Timer Channel Address Bus Data Bus A D Input Port Serial Communications Port Serial Peripheral Interface Port CAN Port PWM Port Technical Summary Rev 5 Peripheral Connectors Freescale Semiconductor 2 19 2 19 1 External Memory Control Signal Expansion Connector The External Memory Control Signal connector contains the device s external memory control signal lines See Table 2 9 for the names of these signals Table 2 9 External Memory Control Signal Connector Description J8 Pin Signal Pin Signal 1 RD 2 IRQA 3 WR 4 IRQB 5 PS 6 RESET 7 DS 8 NC 9 CLKO 10 DE 11 GND 12 3 3V 2 19 2 Encoder Timer Channel Expansion Connector The Encoder Timer Channel port is an MPIO port attached to the Timer expansion connector The port can act as a Quadrature Decoder interface port or as a general purpose Timer port Refer to Table 2 10 for the signals attached to the connector Table 2 10 Timer Connector Description J2 Pin Signal 1 5 0V 2 GND 3 PhaseA 4 PhaseB 5 INDEX 6 HOME DSP56F
31. acture of the part 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56F803EVMUM Rev 5 07 2005
32. at allow the end user to select which signal group the device s A D will monitor Refer to Figure 2 12 for the design of a single channel BACK EMF AN SENSE gt Figure 2 12 Primary Back EMF Motor Phase Current Sense Signals DSP56F803EVM User Manual Rev 5 2 16 Freescale Semiconductor Zero Crossing Detection 2 16 Quadrature Encoder Hall Effect Interface The 56F803EVM board contains a Quadrature Encoder Hall Effect interface connected to the device s Quad Encoder input port The circuit is designed to accept 3 0V to 5 0V encoder or Hall Effect sensor inputs Input noise filtering is supplied on the input path for the Quadrature Encoder Hall Effect interface along with additional noise rejection circuitry inside the controller Figure 2 13 shows the encoder interface 2 17 Zero Crossing Detection An attached UNI 3 motor drive board contains logic that can send out pulses when the phase voltage of an attached 3 phase motor drops to zero The motor drive board circuits generate a 0 to 3 3V DC pulse via voltage comparators The resulting pulse signals are sent to a set of jumper blocks shared with the Encoder Hall Effect interface The jumper blocks allow the selection of Zero Crossing signals or Quadrature Encoder Hall Effect signals When in operation the controller will only monitor one set of signals either the Encoder Hall Effect or the Zero Crossing Figure 2 13 shows the Zer
33. eld 7 PWM BB 8 Shield 9 PWM CT 10 Shield 11 PWM CB 12 GND 13 GND 14 5 0V DC 15 5 0V DC 16 Analog 3 3V DC 17 Analog GND 18 Analog GND 19 Analog 15V DC 20 Analog 15V DC 21 Motor DC Bus Voltage 22 Motor DC Bus Current Sense Sense 23 Motor Phase A Current 24 Motor Phase B Current Sense Sense 25 Motor Phase C Current 26 Motor Drive Temperature Sense Sense 27 NC 28 Shield 29 Motor Drive Brake Control 30 Serial COM 31 PFC PWM 32 PFC Inhibit 33 PFC Zero Cross 34 Zero Cross A DSP56F803EVM User Manual Rev 5 Freescale Semiconductor Table 2 7 UNI 3 Connector Description Continued P1 Pin Signal Pin Signal 35 Zero Cross B 36 Zero Cross C 37 Shield 38 Back EMF Phase A Sense 39 Back EMF Phase B Sense 40 Back EMF Phase C Sense 2 12 Run Stop Switch Run Stop toggle switch is connected to GPIO signal AN7 as shown in Figure 2 9 An optional series resistor is provided which when removed allows the user to utilize the AN7 signal for other purposes RUN STOP SWITCH 567803 Figure 2 9 Run Stop Switch Technical Summary Rev 5 Run Stop Switch Freescale Semiconductor 2 13 2 13 Motor Control PWM Signals and LEDs The 56F803 has a dedicated PWM unit The unit contains six PWM three Phase Current sense and four Fault input lines The PWM lines are connected to the UNI 3 interface connector and to a set of six PWM LEDs via invertin
34. g buffers The buffers are used to isolate and drive the controller s PWM outputs to the PWM LEDs The PWM LEDs indicate the status of PWM group signals refer to Figure 2 12 The PWM group signals are routed out to headers and are available for use by the end user 56F803 UNI 3 PWMAO sy PWMAO PWMA1 gt PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 gt gt PWMAS5 3 3V YELLOW LED 9 LED2 GREEN LED 4 4 PWM_AB 1 YELLOW KR PWM BT 2 GREEN LED gt 4 PWM BB 3 BUFFER YELLOW LED 4 4 CT 4 GREEN LED SSI PWM CB 5 Figure 2 10 PWM Group Interface and LEDs 2 14 Motor Protection Logic The 56F803EVM contains a UNI 3 connector that interfaces with various motor drive boards The controller can sense error conditions generated by the motor power stage boards via signals on the UNI 3 connector The motor driver board s Motor Supply DC Bus Voltage Current and Motor Phase Currents are sensed on the power stage board The conditioned signals are transferred to the device board via the UNI 3 connector These analog input signals are compared to limits set by trimpots If the input analog signals are greater than the limit set by the trimpot a digital compatible 3 3V DC fault signal is generated DSP56F803EVM User Manual Rev 5 2 14 Freescale Semiconductor Motor Protection Log
35. hannel 21 Connectors Peripheral Expansion 19 Controller Area Network CAN ix D Data memory 4 Development Card 1 DSP56800 Family Manual x DSP56F801 803 805 807 User s Manual x Encoder Hall Effect circuits 17 Encoder Timer Channel 20 Evaluation Module EVM ix EVM ix External Memory Control Signal 20 external memory expansion connectors 2 External Memory Interface Schematic Diagram 4 external oscillator frequency input 1 Index Rev 5 Freescale Semiconductor Index 1 F FSRAM 1 4 G General Purpose Input and Output Port GPIO ix GPIO ix 1 13 21 GPIO compatible peripheral 1 H Hall Effect Quadrature Encoder interface 1 Host Parallel Interface Connector 7 Host Target Interface 1 7 external 7 IC ix Integrated Circuit IC ix J Joint Test Action Group JTAG ix JTAG ix 1 connector 7 JTAG port interface 1 Jumper Group 3 7613 76103 7623 7633 17643 7653 7663 7673 7683 139 3 L Logic motor bus over current 1 motor bus over voltage 1 motor zero crossing 1 Low Profile Quad Flat Pack LQFP ix LQFP ix MOSI 7 motor bus over current 1 over voltage 1 MPIO ix MPIO compatible peripheral 1 Multi Purpose Input and Output Port MPIO ix On board power regulation 2 OnCE ix OnCE TM 1 On Chip Emulation OnCE ix PCB ix Phase Locked Loop PLL ix PLL ix Printed Circuit Board PCB ix Program memory 4 Pulse Width Modulation PWM ix PWM ix Group Interface and LEDs
36. ic 2 14 1 UNI 3 Motor Protection Logic The UNI 3 DC Bus Over Voltage signal is connected to the controller s PWM group s fault input FAULTO The UNI 3 DC Bus Over Current signal is connected to the device s PWM group s fault input FAULTI Additionally the UNI 3 DC Bus Over Voltage and Over Current analog signals are connected to two A D inputs ANO and ANI respectively Figure 2 11 contains the diagram of the DC Bus Over Voltage and DC Bus Over Current circuit for the UNI 3 interface DC BUS VOLTAGE SENSE V sense DCB gt gt gt gt FAULTO DC BUS CURRENT SENSE l_sense_DCB 55 A AA e 3 FAULT1 Figure 2 11 DC Bus Over Voltage and Over Current Detection Schematic Diagram Technical Summary Rev 5 Freescale Semiconductor 2 15 2 15 Back EMF and Motor Phase Current Sensing The UNI 3 connector supplies Back EMF and Motor Phase Current signals from the three phases of a motor attached to a motor drive unit The Back EMF signals on the UNI 3 connectors are derived from a resistor divider network contained in the motor drive unit These resistors divide down the attached motor s voltages to a 0 to 3 3V level In certain instances the Back EMF signals can exceed this maximum range The Motor Phase Current signals are derived from current sense resistors Both of these signal groups are then routed to a group of header pins th
37. le 56F803 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the 56F803EVM and its features Chapter 2 Technical Summary describes in detail the 56F803EVM hardware Appendix 56F803EVM Schematics contains the schematics of the 56F803EVM Appendix 56F803EVM Bill of Material provides a list of the materials used on the 56F803EVM board Suggested Reading More documentation on the 56F803 and the 56F803EVM kit may be found at the URL http www freescale com Preface Rev 5 Freescale Semiconductor vii Notation Conventions This document uses the following conventions paths emphasis Term or Value Symbol Examples Exceptions Active High Signals No special symbol 0 Logic One attached to the sig CLKO nal name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbarintextandin OE Active Low Signals may most figures be noted by a backslash Hexadecimal Values Begin with OFFO symbol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter b1010 attached to the b0011 number Numbers Considered positive 5 Voltage is often shown unless specifically 10 as positive 3 3V noted as a negative value Bold Reference sources See www freescale com DSP56F801EVM User
38. miconductor Debug Support 2 6 Debug LED An on board Light Emitting Diode LED is provided to allow real time debugging for user programs This LED allows the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 4 LED8 is controlled by the MOSI signal line Setting MOSI to a Logic One value will turn on the LED 56F803 LED 8 MOSI BUFFER AN GREEN LED Figure 2 4 Schematic Diagram of the Debug LED Interface 2 7 Debug Support The 56F803EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Host Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector 2 7 1 JTAG Connector The JTAG connector on the 56F803EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F803 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 3 shows the pin out for this connector Technical Summary Rev 5 Freescale Semiconductor 2 7 Table 2 3 JTAG Connector Description J1 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 T
39. n of the 56F803 including functionality and user information is provided in the following documents 56F803 Technical Data DSP56F803 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging DSP56F803EVM User Manual Rev 5 2 2 Freescale Semiconductor 56F803 DSP56F801 803 805 807 User s Manual DSP56F801 7UM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem DSP56800 Family Manual DSP56800FM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set These manuals contain detailed information about chip functionality and operation and can be found at this URL http www freescale com Technical Summary Rev 5 Freescale Semiconductor 2 3 2 2 Program and Data Memory The 56F803EVM uses one bank of 128Kx16 bit Fast Static RAM GSI GS72116 labeled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 This physical memory bank is split into two logical memory banks of 64Kx16 bits one for Program memory and the other for Data memory By using the device s program strobe PS signal line along with the memory chip s AO
40. o Crossing and Encoder Hall circuits ZERO X ZERO X ZERO X 56F803 PHASEA FILTER PHASEB FILTER FILTER 5 0V FILTER GROUND PHASE A PHASE B INDEX HOME Figure 2 13 Zero Crossing Encoder Interface Technical Summary Rev 5 Freescale Semiconductor 2 17 2 18 CAN Interface The 56F803EVM board contains a CAN physical layer interface chip that is attached to the MSCAN RX and MSCAN TX pins on the 56F803 The EVM board uses a Philips 82 250 high speed 1Mbps physical layer interface chip Due to the 5 0V operating voltage of the CAN chip a pull up to 5 0V is required to level shift the Transmit Data output line from the 56F803 primary J3 and daisy chain J13 CAN connector are provided to allow easy daisy chaining of CAN devices Refer to Figure 2 14 for a connection diagram and to Table 2 8 for the CAN signals CAN CONNECTOR 56F803 U15 MSCAN_TX TXD VCC VREF MSCAN_RX RXD CANH CANL SLOPE GND PCA82C250T DAISY CHAIN CAN CONNECTOR Figure 2 14 CAN Interface DSP56F803EVM User Manual Rev 5 2 18 Freescale Semiconductor Table 2 8 CAN Header Description J3 and
41. o allow the user to connect his own SPI MPIO compatible peripheral J6 Connector to allow the user to connect his own PWM GPIO compatible peripheral J4 Connector to allow the user to connect his own CAN physical layer peripheral J5 Connector to allow the user to connect his own Timer MPIO compatible peripheral J10 Technical Summary Rev 5 Freescale Semiconductor 2 1 2 1 Connector to allow the user to connect to the device s A D Port 19 56F803 s external memory expansion connectors J7 J8 and J11 On board power regulation from an external 12V DC supplied power input P3 Light Emitting Diode LED power indicator LED1 Six on board PWM monitoring LEDs LED2 LED7 On board real time user debugging LED LED8 UNI 3 Motor interface P1 Encoder Hall Effect interface Over Voltage sensing U14 Over Current sensing U14 DC Bus Voltage sensing U13 DC Bus Current sensing U13 Back EMF sensing Temperature sensing Zero Crossing detection Pulse Width Modulation Power Factor Correction PFC sensing Manual RESET push button S4 Manual interrupt push button for IRQA S2 Manual interrupt push button for IRQB S3 General purpose toggle switch for RUN STOP control AN7 S1 56F 803 The 56F803EVM uses a Freescale DSP56F803BUS80 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 80MHz full descriptio
42. on Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any produc
43. reescale Semiconductor DSP56F803EVM User Manual Rev 5 Appendix A 16 Freescale Semiconductor Appendix B 56F803EVM Bill of Material Qty Description Ref Designators Vendor Part s Integrated Circuits 1 DSP56F803BU80 01 Freescale DSP56F803BU80 1 GS72116TP 12 U2 GSI GS72116TP 12 1 ADM3311EARS U3 Analog Devices ADM3311EARS 2 MC74HC244DW U6 U7 ON Semiconductor MC74HC244DW 1 MC33269DT 5 0 U8 ON Semiconductor MC33269DT 5 0 1 MC33269DT 3 3 U9 ON Semiconductor MC33269DT 3 3 2 74AC04SC U10 U12 Fairchild 74 045 1 LM393 U14 National Semiconductor LM393 1 82 250 015 Philips Semiconductor PCA82C250T Resistors 4 16K R36 R37 R41 R42 SMEC RC73L2A16KOHMJT 2 1M O R43 R38 SMEC RC73L2A1MOHMJT 16 5 1KQ R2 R5 R7 R11 R14 R39 SMEC RC73L2A5 1KOHMJT R44 R59 R60 R62 R65 8 10K O R1 R8 R16 R18 R20 R21 SMEC RC73L2A10KOHMJT R66 R67 2 510 R3 R4 SMEC RC73L2A51O0HMJT 1 4700 R10 SMEC RC73L2A4700HMJT 1 10M Q R17 SMEC RC73L2A10MOHMJT 14 1KQ R9 R22 R28 R46 R49 R52 SMEC RC73L2A1KOHMJT R55 R58 R68 56F803EVM Bill of Material Rev 5 Freescale Semiconductor Appendix B 1 Qty Description Ref Designators Vendor Part s Resistors Continued 7 2700 R29 R35 SMEC RC73L2A2700HMJT 8 240 R47 R48 50 R51 R53 R54 SM
44. signal line half of the memory chip is selected when Program memory accesses are requested and the other half of the memory chip is selected when Data memory accesses are requested This memory bank will operate with zero wait state accesses while the 56F803 is running at 70MHz However when running at 80MHz the memory bank operates with four wait state accesses This memory bank can be disabled by removing the jumper at JGS 56F803 GS72116 0 1 5 16 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External Memory Interface DSP56F803EVM User Manual Rev 5 2 4 Freescale Semiconductor RS 232 Serial Communications 2 3 RS 232 Serial Communications The 56F803EVM provides an RS 232 interface by the use of an RS 232 level converter Analog Devices ADM3311EARS designated as U3 refer to the RS 232 schematic diagram in Figure 2 2 RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P4 Flow control is not provided but could be implemented using uncommitted GPIO signals The pin out of connector P4 is listed in Table 2 1 56F803 RS 232 Level Interface RS 232 089 Tiout 1 Figure 2 2 Schematic Diagram of
45. t or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized foruse as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manuf
46. the RS 232 Interface Table 2 1 RS 232 Serial Connector Description P4 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND Technical Summary Rev 5 Freescale Semiconductor 2 5 2 4 Clock Source The 56F803EVM uses an 8 00MHZ crystal Y1 connected to its External Crystal Inputs EXTAL and XTAL The 56F803 uses its internal PLL to multiply the input frequency by 10 to achieve its 80MHZ maximum operating frequency An external oscillator source can be connected to the controller by using the oscillator bypass connectors JG3 and JG9 see Figure 2 3 EXTERNAL OSCILLATOR HEADERS 56F803 EXTAL Figure 2 3 Schematic Diagram of the Clock Interface 2 5 Operating Mode The 56F803EVM provides a boot up MODE selection jumper JG4 This jumper is used to select the operating mode of the controller as it exits RESET Refer to the DSP56F801 7 User s Manual for a complete description of the chip s operating modes Table 2 2 shows the two operation modes available on the 56F803 Table 2 2 Operating Mode Selection Operating Mode JG4 Comment 0 1 2 Bootstrap from internal memory GND 3 No Jumper Bootstrap from external memory 3 3V DSP56F803EVM User Manual Rev 5 2 6 Freescale Se
47. uctor DSP56F801 7UM 3 56 803 Technical Data Freescale Semiconductor DSP56F803 4 CiA Draft DR 303 1 Cabling and Connector Pin Assignment Version 1 0 CAN in Automation 5 CAN Specification 2 0B BOSCH in Automation DSP56F801EVM User Manual Rev 5 x Freescale Semiconductor Chapter 1 Introduction The 56F803EVM is used to demonstrate the abilities of the 56F803 and to provide a hardware tool allowing the development of applications that use the 56F803 The 56F803EVM is an evaluation module board that includes a 56F803 part peripheral expansion connectors external memory RS 232 interface and a CAN interface The expansion connectors are for signal monitoring and user feature expandability The 56F803EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800 architecture The tools and examples provided with the 56F803EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG OnCE port The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The
48. ure phones modems and digital cameras The power of the 16 bit 56F803 controller combined with the on board 64K x 16 bit external program Static RAM SRAM 64K x 16 bit external data SRAM CAN interface Hall Effect Quadrature Encoder interface motor zero crossing logic motor bus over current logic motor bus over voltage logic and parallel JTAG interface makes the 56F803EVM ideal for developing and implementing many motor controlling algorithms as well as for learning the architecture and instruction set of the 56F803 processor The main features of the 56F803EVM include 56F803 16 bit 3 3V controller operating at 830MHz U1 External fast Static RAM FSRAM memory U2 configured as 64Kx16 bit of Program memory with 0 wait states at 70MHZ 64Kx16 bit of Data memory with 0 wait states at 70MHZ 8 00MHz crystal oscillator for device frequency generation Y1 Optional external oscillator frequency input connector JG3 and JG9 Joint Test Action Group JTAG port interface connector for an external debug Host Target Interface J1 On board Parallel JTAG Host Target Interface with a connector for a PC printer port cable P2 RS 232 interface for easy connection to a host processor U3 and P4 CAN interface for high speed 1 0Mbps communications U15 and J3 CAN bypass and bus termination J13 and JG10 Connector to allow the user to connect his own SCI GPIO compatible peripheral J12 Connector t

Download Pdf Manuals

Related Search

Related Contents

Model PCL-722 144 Bit DIO Card  Technical specification - Xtender serial protocol    

Copyright © All rights reserved. Failed to retrieve file