The IEEE Verilog 1364
Contents
1. The EEE Verilog 1364 2000 Standard What s New and Why You Need It by Stuart Sutherland Sutherland HDL Inc Verilog Training and Consulting Experts Presented at the HDLCON 2000 Conference March 10 2000 San Jose California Sutherland Verilog 2000 Update nD P The specification of the Verilog 2000 standard is complete a Final draft completed March 1st 2000 m The final IEEE balloting process has started m Expect Verilog 2000 to be ratified in Q3 2000 The official standard will be IEEE Std 1364 2000 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com Sutherland Why a New Standard nD db Add enhancements to Verilog Design methodologies are evolving System level design intellectual property models design re use very deep submicron etc a Cliff Cumming s Top Five Enhancement Requests from HDLCON 1996 Clarify ambiguities in Verilog 1364 1995 m The 1364 1995 reference manual came the Gateway Design Automation Verilog XL User s Manual a Verilog 2000 more clearly defines Verilog syntax and semantics 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 3 Sutherland Goals for Verilog 2000 MDL Cb Enhance Verilog for Higher level abstract system level modeling a Intellectual Property IP modeling Greater timing accuracy for very deep submicron Make Verilog even easier to use Correct errata and ambiguitie2. If a pre process utility program modifies the Verilog source code the original file and line information could be lost 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 32 Sutherland 23 H D E Attributes Verilog 2000 adds attribute properties m A standard means to specify non Verilog tool specific information to Verilog models m Adds new tokens and Eliminates need to hide commands in comments The standard does not define any specific attributes Software vendors can define proprietary attributes Other standards might define standard attributes Verilog 1995 case 1 b1 synopsys parallel Verilog 2000 parallel case case 1 b1l 1 hot FSM 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 33 Sutherland 24 Hp L Standard Random Number Generator p Verilog 2000 defines the C source code for the generator used by random a All simulators can generate the same random number sequence when given the same seed value Simulation results from different simulators can be compared New products do not need to re invent the wheel a Uses the random number generator from Verilog XL 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 34 Sutherland 25 Hp Enhanced Invocation Option Tests Verilog 1995 contains a true false test to see if simulation was invoked with a specific option a test
3. Verilog 2000 reg clock 0 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 29 Sutherland 20 Hp L _ Register Changed To Variable The Verilog 2000 standard changes the term register to variable a register is not a reserved word it is just a term a Since its inception in 1984 Verilog manuals have used the term register to describe a class of data types reg unsigned variable integer signed variable real double precision variable etc The term register often confuses new Verilog users register is a hardware term for storage elements Verilog registers do not imply a hardware register 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 30 Sutherland 21 Hp L Enhanced Conditional Compilation Verilog 1995 supports limited conditional compilation m The ifdef else and endif compiler directives Verilog 2000 adds more extensive conditional compilation control New directives ifndef elsif and undef 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 31 Sutherland 22 Hp L File and Line Compiler Directives Verilog 2000 adds file and line compiler directives New directives file and line Document the original location of Verilog source code Verilog tools often include file name and line number information in error and warning messages
4. erilog 2000 adds powerful capabilities Greater deep submicron accuracy More abstract system level modeling Scalable re usable modeling Final approval is expected in the summer of 2000 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 47 Sutherland About The Author MDL ae Stuart Sutherland a President of Sutherland HDL Inc Portland Oregon a Provides expert Verilog design consulting and training More than 15 years design experience and over 12 years working with Verilog m Author of The Verilog HDL Quick Reference Guide The Verilog PLI Quick Reference Guide and The Verilog PLI Handbook a 750 page reference book Member of the I EEE 1364 Verilog standards committee since 1993 Co chair of the PLI task force within the committee 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 48
5. in the list can be separated with a comma The old or separated list will still work Verilog 1995 Verilog 2000 always sel a b c d case sel 2 b00 2 b01 a b CF d 2 b10 2 bit endcase 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 20 Sutherland Li Hp iD Combinational Logic Sensitivity Verilog 2000 adds a wildcard token to indicate a combinational logic sensitivity list a The token indicates that an always procedure is automatically sensitive to any change on any input to that procedure Verilog 1995 Verilog 2000 always case sel 2 b00 y 2 b01 y 2 b10 y 2 b1l y endcase 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 21 Sutherland 12 Hp Enhanced File I O db L Verilog 1995 has limited built in file O tasks Up to 31 files can be opened for writing Only ASCII characters can be written to files More complex file O is done using the Verilog Programming Language Interface PLI Verilog 2000 adds The ability to open up to 27 files New built in file I O tasks ferror fgetc fgets fflush fread fscanf fseek fsscanf ftel rewind sformat swrite swriteb Sswriteh swriteo ungetc 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 22 Sutherland 13 Hp E Automatic Width Extension Past 32 bits p
6. In Verilog 1995 m Verilog assignments zero fill when the left hand side is wider than the right hand side a Unsized integers default to 32 bits wide therefore the widths of integers must be hard coded Verilog 1995 _ Verilog 2000 will automatically extend a logic Z or X to the full width of the left hand side parameter WIDTH 64 Verilog 2000 reg WIDTH 1 0 data data bz fills with hzzzzzzzzzzzzzzzz 10 Mar 2000 23 Sutherland 14 Hp Verilog 2000 will default to a net data type on the left hand side of any continuous assignment The vector width is the size of the right hand side expression if not connected to a port of the module m n Verilog 1995 the left hand side must be explicitly declared if not connected to a port of the module Verilog 1995 Verilog 2000 assign n a b defaults to wire width of a b 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 24 Sutherland 15 Hp Disable Default Net Declarations L p In Verilog 1995 undeclared signals can default to a wire data type The default data type can be changed to another net data type using default_nettype lt data_type gt Verilog 2000 provides a means to disable default net declarations m default _nettype none a Any undeclared signals will be a syntax error Prevents hard to debug wiring errors due to a mistyped name none is not a new
7. a path output without the path delay a New reserved words added pulsestyle_onevent pulsestyle_ondetect 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 38 Sutherland 29 Hp L Negative Pulse Detection Verilog 2000 adds negative pulse detections Due to different rising transition and falling transition delays it is possible for the trailing edge of a glitch to propagate before the leading edge has propagated In Verilog 1995 a negative pulse is cancelled Negative pulse detection will propagate a logic X for the duration of the negative pulse New reserved words added showcancelled noshowcancelled 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 39 Sutherland 30 Hp L New Timing Constraint Checks Verilog 2000 adds new timing constraint checks More accurately model very deep submicron input constraints m New timing constraint tasks added removal recrem timeskew fullskew Refer to the proposed IEEE 1364 2000 Verilog standard for details on these tasks 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 40 Sutherland 31 Hp L Negative Timing Constraints Verilog 2000 adds the ability to specify negative values for setuphold setup and hold times Adds new optional arguments to the Verilog 1995 setuphold task recrem recovery and removal times A new timing chec
8. ign of a value New signed and unsigned system functions can cast a value to signed or unsigned 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 17 Sutherland 8 Hp Power Operator L Verilog 2000 add an exponential power operator Represented by the token m Works like the C pow function a f either operand is real a real value is returned a f both operands are integers an integer value is returned module ram parameter RAM SIZE 1024 input 2 RAM SIZE 1 0 address_bus 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 18 Sutherland 9 Re entrant Tasks Hp i L and Recursive Functions Cb Verilog 2000 adds automatic tasks and functions Each call to the task function allocates unique storage In Verilog 1995 tasks and functions are static each call shares the same storage space Concurrent task calls will not interfere with each other Recursive calls to a function are stacked New reserved word added automatic function automatic 63 0 factorial input 31 0 n if n 1 factorial 1 else factorial n factorial n 1 endfunction 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 19 Sutherland 10 Hp L Comma separated Sensitivity List Verilog 2000 adds a second syntax style for listing signals in a sensitivity list a Signals
9. k task in Verilog 2000 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 41 Sutherland 32 Hp Enhanced SDF support i The Verilog 2000 standard defines How timing objects in SDF map to objects in Verilog Based on the latest SDF standard EEE 1497 1999 VVerilog 2000 changes the syntax of the specparamM constant Can now be declared at the module level as well as within a specify block to support SDF labels Verilog 2000 adds a standard sdf_annotate system task a Already a de facto standard in all simulators 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 42 Sutherland 33 Hp L Extended VCD Files Verilog 2000 adds new Value Change Dump VCD capabilities Dump port change values Dump strength level changes Dump the time at which simulation finishes New system tasks added dumpports dumpportsall dumpportsoff dumpportson dumpportslimit and dumpportsflush 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 43 Sutherland PLI Enhancements HDI p Several enhancements added to the VPI library m Simulation control Stop finish save restart etc Support for new Verilog 2000 HDL constructs Array of instances attributes signed arithmetic recursive functions enhanced file I O etc Maintenance updates to TF and ACC libraries Corrected errata a Clarified ambig
10. oduct endgenerate endmodule 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 11 Sutherland G Hp L Constant Functions Verilog 2000 adds constant functions Same syntax as standard Verilog functions Limited to statements that can be evaluated at compile time Can be called anywhere a constant expression is required Vector width declarations Array declarations Replicate operations Provides for more scalable re usable models 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 12 Sutherland Constant Functions Example AD p module ram parameter RAM SIZE 1024 parameter ADDRESS 12 input ADDRESS 1 0 address_bus module ram parameter RAM SIZE 1024 input clogb2 RAM_SIZE 1 0 address_bus function integer clogb2 input depth integer i begin clogb2 1 for i 0 2 i lt depth i i 1 clogb2 i 1 end endfunction 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 13 Sutherland 4 Hp L Indexed Vector Part Selects Verilog 2000 adds the capability to use variables to select a group of bits from a vector The starting point of the part select can vary m The width of the part select remains constant reg 63 0 word reg 3 0 byte_num a value from 0 to 7 wire 7 0 byteN word byte_num 8 8 10 Mar 2000 2000 Su
11. plusargs VVerilog 2000 adds the ability to read arguments of invocation options New system function value plusargs 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 35 Sutherland 26 Hp Enhanced PLA Modeling i Verilog 2000 extends the capability of the PLA system tasks async or array async and array etc m n Verilog 1995 arguments had to be scalar a n Verilog 2000 arguments can be vectors 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 36 Sutherland 2 Hp Accurate BNF with Subsections L The Verilog 1995 BNF Backus Naur Form had errors and inconsistencies Verilog 2000 contains a much stronger BNF definition of the Verilog language Consistent terminology More definitive terms a Divided into sub sections to make it easier to find specific definitions Checked for accuracy 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 37 Sutherland 29 Hp On detect Pulse Error Propagation Verilog 1995 has on event pulse error propagation A pulse is a glitch on the inputs of a module path that is less than the delay of the path a An input pulse propagates to a path output as an X with the same delay as if a valid input change had propagated to the output Verilog 2000 adds on event pulse error propagation As soon as an input pulse is detected a logic X is propagated to
12. re to find top level modules design rtlLib top set the default search order for finding instantiated modules default liblist rtlLib gateLib explicitly specify which library to use for the following module instance instance test dut a2 liblist gateLib endconfig location of RTL models current directory library rellLib iv Library Map File Location of synthesized models library gateLib synth_out v 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 9 Sutherland 2 Hp L Verilog Generate Verilog 2000 adds true generate capability Use for loops to generate any number of instances of Modules primitives procedures continuous assignments tasks functions variables nets Use if else and Case decisions to control what instances are generated Provides greater control than the VHDL generate New reserved words added generate endgenerate genvar localparam 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 10 Verilog Generate Example Sutherland H DL p module multiplier a b product parameter a_width 8 b width 8 localparam product_width a_width b width input a_width 1 0 a output product_width 1 0 product generate if a_width lt 8 b_width lt 8 CLA_multiplier a_width b_width ul a b product else WALLACE multiplier a_width b_width ul a b pr
13. reserved word 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 25 Sutherland 16 Hp L Explicit In line Parameter Passing Verilog 2000 adds the ability to explicitly name parameters when passing parameter values Provides better self documenting code Parameter values can be passed in any order Verilog 1995 Verilog 2000 module my chip RAM SIZE 1023 ram2 endmodule 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 26 Sutherland 17 Hp L Combined Port Data Type Declarations p Verilog 2000 permits combining port declarations and data type declarations into one statement Verilog 1995 Verilog 2000 module mux8 y a b en output reg 7 0 y input wire 7 0 a b input wire en 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 27 Sutherland 18 Hp L ANSI Style Port Lists VVerilog 2000 adds ANSI C style input and output declarations For modules tasks and functions Verilog 1995 Verilog 2000 module mux8 output reg 7 0 input wire 7 0 input wire 7 0 input wire 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 28 Sutherland 19 H D Reg Declaration With Initialization Verilog 2000 permits initializing variables at the time they are declared a The initialization is executed in time step zero just like initial procedures Verilog 1995
14. s Maintain backward compatibility existing models will work with the new standard Ensure that EDA vendors will implement all enhancements 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 4 Sutherland The IEEE 1364 Hp L Verilog Standards Committee A main working group a Final approval of all changes to 1364 1995 m About 20 active participants Three task forces s Behavioral Task Force Cliff Cummings chair RTL and behavioral modeling enhancements a ASIC Task Force Steve Wadsworth chair ASIC and FPGA library modeling enhancements a PLI Task Force Drew Lynch Stu Sutherland co chairs PLI enhancements 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 5 Sutherland Overview of HDL Enhancements MD p 33 major enhancements were added to the Verilog HDL Brief description and examples New reserved words Errata and clarifications Dozens of corrections were made to 1364 1995 Do not affect Verilog users a Very important to Verilog tool implementors Not listed in this paper refer to the 1364 2000 Verilog Language Reference Manual LRM 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com Sutherland 1 Hp E Verilog Configurations Verilog 1995 leaves design management up to the software tools Every tool has different ways to manage large designs Verilog 2000 adds configuration blocks a All
15. software tools will have a consistent method m The version for each module instance can be specified Virtual libraries specified within Verilog source code Physical file locations specified in a map file New reserved words added config endconfig design instance cell use liblist 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 7 Sutherland Verilog Configuration Notes MDL p Verilog design hierarchy is modeled the same as always Configurations can be used to specify which module source code should be used for each instance of a module a With Verilog 1995 it is up to the simulator on how to specify which model version should be used for each instance if the simulator can do it at all The configuration block is specified outside of all modules m Can be in the same file as the Verilog source code a Can be in a separate file a Verilog model source code does not need to be modified in order to change the design configuration A separate file maps logical library names to physical file locations a Verilog source code does not need to be modified when a design is moved to a different physical source location 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 8 Sutherland Verilog Configuration Example AD Verilog Design Configuration Block part of Verilog source code define a name for this configuration config cfg4 specify whe
16. therland HDL Inc www sutherland hdl com 14 2 Hp Sutherland L Multi dimensional Arrays p 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com Verilog 1995 allows 1 dimensional arrays of reg integer and time variables m Typically used to model RAM and ROM memories Verilog 2000 adds a Multidimensional arrays of any variable data type a Multidimensional arrays of any net data type declare a 3 dimensional array of 8 bit wire nets wire 7 0 array3 0 255 0 255 0 15 select one word out of a 3 dimensional array wire 7 0 out3 array3 addr1 addr2 addr3 15 Sutherland 6 Hp Array Bit and Part Selects Verilog 2000 adds a Bit selects out of an array Part selects out of an array select the high order byte of one word in a 2 dimensional array of 32 bit reg variables reg 31 0 array2 0 255 0 15 wire 7 0 out2 array2 100 7 31 24 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 16 Sutherland T Hp Signed Arithmetic Extensions L Verilog 2000 adds reg and net data types can be declared as signed reg signed 63 0 data wire signed 11 0 address Function returns can be declared as signed function signed 128 0 alu a Literal integer numbers can be declared as signed 16 shc501 a signed 16 bit hex value New arithmetic shift operators lt lt lt and gt gt gt maintain the s
17. uities 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 44 Sutherland The VPI Library Is The Future AD Sr L All enhancements to the Verilog language will only be supported in the VPI library of the PLI The TF and ACC libraries PLI 1 0 are only being maintained A uE pO LOS VWarirg To Simlar Vedos Lat PL 1 0 isOUW s 1990 Verilag PU sache It ig it 1990 awe Yor asonres obrct veat peridcoic smilaos 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 45 Sutherland When Will These Hp Enhancements Be Available The official word from several EDA vendors is a They will not comment on future product plans a They will not begin to implement Verilog 2000 until it Is ratified expected to be mid 2000 The unofficial word from EDA vendors is Some have already started implementing Verilog 2000 One essentially says they do not see any need to Implement the new features in Verilog 2000 Tal yvousmilao sythsss ad dre Venilag toads poidas tet youwert a these Veilag2000 etercnnts NGM 10 Mar 2000 2000 Sutherland HDL Inc www sutherland hdl com 46 Sutherland Summary Hp Sri Verilog 2000 is complete The proposed IEEE 1364 2000 Verilog standard is now In the final balloting phase V erilog 2000 contains m Over 30 major enhancements a Many clarifications and errata corrections V
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