µPD780053,780054,780055,780056,780058
Contents
1. 60 10 z E gt Operation 5 Operation Range m Guaranteed a Range o 2 2 0 1 0 0 0 0 1 2 3 4 5 6 1 2 3 4 5 6 Supply Voltage V Supply Voltage V Preliminary Data Sheet 43 2 Read write operation a When MCS 1 PCC2 to PCC0 000B Ta 40 to 85 4 5 to 5 5 V Parameter Test Conditions ASTB high level width tasTH 0 85tcy 50 Address setup time taps 0 85tcy 50 Address hold time 50 Data time from address 1 2 85 2n tcv 80 tapp2 4 2n tcv 100 Data input time from RD trop 2 2n tcy 100 8002 2 85 2n tcv 100 Read data hold time 0 D low level width 2 2n tcy 60 2 85 2n tcv 60 WAIT input time from RD tnpwri 0 85tcv 50 tRDwr2 2tcv 60 WAIT input time from WRI twrwT 2tcv 60 WAIT low level width 1 15 2n tcv 2 2n tcv Write data setup time twos 2 85 2n tcv 100 Write data hold time twoH 20 WR low level width twn 2 85 2n tcv 60 RD delay time from ASTBJ lASTRD 25 WR delay time from ASTBL lASTWR 0 85tcy 20 delay time tRDAST 0 85tcy 10 1 15tcy 20 in external fetch A2. Note Cis the load capacitance of SOO output line ii 3 wire serial I O mode SCKO External clock input Parameter Test Conditions SCKO cycle time 4 5 V lt Vpp lt 5 5 V 2 7 V lt lt 4 5 V 2 0 V lt Vpp lt 2 7 V SCK0 high low level 2 4 5 V lt Vpp lt 5 5 V width 2 7 V lt Voo 4 5 V 2 0 V lt Vpp lt 2 7 V 10 setup time to 2 0 V lt lt 5 5 V SCKOT 10 hold time from SCKOT 500 output delay time C 100 pF Note Vpp 2 0 to 5 5V from SCKOL SCKO rise fall time tre When using external device expansion function When not using external device expansion function Note Cis the load capacitance of 500 output line Preliminary Data Sheet 47 780053 780054 780055 780056 780058 iii SBI mode SCKO Internal clock output Parameter Test Conditions SCK0 cycle time 4 5 V lt lt 5 5 V 800 2 0 V lt Voo lt 4 5 V 3200 4800 SCK0 high low level width taa 4 5 V lt lt 5 5 V 2 50 2 0 V lt Voo lt 4 5 V 2 150 SB0 SB1 setup time 4 5 V lt Voo lt 5 5 V 100 to SCK0T 2 0 V lt Voo lt 4 5 V 300 400 SB0 SB1 hold time tkcy3 2 from SCKOT SBO SB1 output delay R 1kQ Vpp 4 5 to 5 5 V time from C 100 pF Note 580 SB11 from SCKOT SCK
3. Output leakage Vout current high Output leakage Vour 0 V current low Mask option pull up ViN 0 V P60 P63 resistor Software pull up Vin 0 V P01 P05 10 17 P20 P27 P30 P37 resistor P40 P47 P50 P57 P64 P67 P70 P72 P120 P127 P130 P131 Note For P60 P63 without on chip pull up resistor specifiable by mask option low level input leakage current 04 200 MAX flows only during the 1 5 clocks no wait after an instruction has been executed to read out port 6 P6 or port mode register 6 PM6 Outside the period of 1 5 clocks following executing a read out instruction the current is 3 uA MAX Remark The characteristics of a dual function pin and a port pin are the same unless specified otherwise 40 Preliminary Data Sheet DC Characteristics 40 to 85 C Vpp 1 8 to 5 5 V Parameter Test Conditions Power supply 5 0 MHz Crystal oscillation Von 5 0 V 10 96 Note current Note 5 operating mode 3 0 V 10 Note 2 fxx 2 5 MHz Note 3 2 0 V 10 Note 2 5 0 MHz Crystal oscillation Voo 5 0 V 10 Note 1 operating mode 5 0 MHz Note 4 3 0 V 10 Note 2 5 0 MHz Crystal oscillation 5 0 V 10 HALT mode Voo 3 0 V 10 96 fxx 2 5 MHz Note 3 2 0 V 10 96 5 0 MHz Crystal oscillation 5 0 V 10 95 HALT mode fxx 5 0 MHz Note 4
4. 780053 780054 780055 780056 780058 iii 3 wire serial mode with automatic transmit receive function SCK1 Internal clock output Parameter SCK1 cycle time Test Conditions 4 5 V lt Voo lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1600 2 0 V lt Voo lt 2 7 V 3200 4800 SCK1 high low level width tkuo tkLo Vpp 4 5 to 5 5 V tkcy9 2 50 tkcvo 2 100 setup time to SCK17 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 hold time from SCK1T 400 501 output delay time from SCK14 C 100 pF Note 300 STBT from SCK1T tkcvo 2 100 tkcvo 2 100 Strobe signal high level width 2 7 V lt Voo lt 5 5 V tkcvo 30 30 2 0 V lt Voo lt 2 7 V 60 60 90 90 Busy signal setup time to busy signal detection timing 100 Busy signal hold time from busy signal detection timing 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 200 300 SCK11 from busy inactive Note Cisthe load capacitance of the SO1 output line Preliminary Data Sheet 2 51 780053 780054 780055 780056 780058 3 wire serial I O mode with automatic transmit receive funct
5. 00 05 7 10 17 20 27 P30 P37 40 47 0 3 to 0 3 50 57 64 67 70 72 120 127 P130 P131 X1 X2 XT2 RESET P60 P63 N ch Open drain 0 3 to 16 Output voltage 0 3 to 0 3 Analog input voltage P10 P17 Analog input pin AVss 0 3 to AVrero 0 3 Output 1 pin 10 P01 P05 P30 P37 P56 P57 P60 P67 P120 P127 total 15 P10 P17 P20 P27 40 47 P50 P55 P70 P72 15 130 P131 total Output 1 pin Peak value 30 current low rms value 15 P50 P55 total Peak value rms value P56 P57 P60 P63 total Peak value rms value 70 P10 P17 P20 P27 P40 P47 Peak value 50 P70 P72 P130 P131 total rms value 20 P01 P05 P30 P37 P64 P67 Peak value 50 P120 P127 total rms value 20 Operating ambient 40 to 85 temperature Storage 65 to 150 temperature Note rms value should be calculated as follows rms value Peak value x Vduty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily That is the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded 36 Preliminary Data Sheet 780053 780054 780055 7
6. 3 0 V 10 32 768 kHz Crystal oscillation 5 0 V 10 operating mode Note 6 3 0 V 10 Vpp 2 0 V 10 32 768 kHz Crystal oscillation Voo 5 0 V 10 HALT modassa 3 0 V 10 96 Voo 2 0 V 10 1 5 0 V 10 96 STOP mode When feedback resistor is used Vp 3 0 V 10 2 0 V 10 96 XT1 5 0 V 10 STOP mode When feedback resistor is unused 2 0 V 10 96 Notes 1 Operating in high speed mode when set the processor clock control register PCC to 00H 2 Operating in low speed mode when set the PCC to 04H Operation with fxx fx 2 when oscillation mode selection register OSMS is set to 00H Operation with fxx fx when OSMS is set to 01H This current flows in the Voo and AVpp pins However a current flowing in the A D converter D A converter and on chip pull up resistor are not included 6 When the main system clock is halted Preliminary Data Sheet 41 780053 780054 780055 780056 780058 Characteristics 1 Basic operation 40 to 85 Vpp 1 8 to 5 5 V Parameter Test Conditions Cycle time Operating on main system clock Voo 2 7 to 5 5 V 0 8 Min instruction fxx 2 5 MHz Note 1 20 execution ime Operating on main system clock Voo 3 5 to 5 5 V 0 4 fxx 5 0 MHz Note
7. 50 Write data output time from RDT Voo 2 7 to 5 5 V 0 4tcy 20 0 37tcy 40 Write data output time from WRU Vpp 2 7 to 5 5 V 0 60 0 120 Address hold time from WRT twWRADH Vpp 2 7 to 5 5 V tcy tcy 60 tcy 120 RDT delay time from WAITT Vpp 2 7 to 5 5 V 0 180 2 180 0 63tcv 350 2 63 350 WRT delay time from WAITT Vpp 2 7 to 5 5 V 0 120 2 6tcy 120 0 63tcv 240 Remarks 1 MCS Oscillation mode selection register OSMS bit 0 2 PCC2 to PCCO Processor clock control register PCC bit 2 to bit 0 3 tcy 4 4 number of waits 46 Preliminary Data Sheet 2 63tcy 240 780053 780054 780055 780056 780058 3 Serial interface 40 to 85 Vpp 1 8 to 5 5 V a Serial interface channel 0 i 3 wire serial I O mode SCKO Internal clock output Parameter Test Conditions SCKO cycle time 4 5 V lt Vpp lt 5 5 V 800 2 7 V lt Vpp lt 4 5 V 1600 2 0 V lt Vop 2 7 V 3200 4800 SCKO high low level tkm Von 4 5 to 5 5 V t cv 2 50 width 2 100 SIO setup time to 4 5 V lt Vop 5 5 V 100 SCKOT 2 7 V lt Vpp lt 4 5 V 150 2 0 V lt Vpp lt 2 7 V 300 400 SIO hold time from 400 SCK01 500 output delay time C 100 pF Note from SCKOL
8. 10 enable DE e duni E ee data p ch data e IN OUT output N ch open drain disable i output disable IN OUT Vsso phe input enable Type 5 N 11 D pullup b De 7 6 enable Vooo data 1 P ch data IN OUT output F N ch INOUT disable P ch Vsso output Comparator N ch ale disable N ch e E Vss Vrer Threshold Voltage pt enable 16 Preliminary Data Sheet 780053 780054 780055 780056 780058 Figure 3 1 Pin Input Output Circuits 2 2 Type 12 C 16 pullup feed back enable De cut off Pach data e W 7 gt 5 IN OUT gt output N ch disable V SSO pe input enable Analog Output XT1 XT2 Voltage E Non Vsso Type 13 J ae Mask Leal S IN OUT data output disable Vsso lt Middle High Voltage Input Buffer Preliminary Data Sheet 17 4 MEMORY SPACE 780053 780054 780055 780056 780058 Figure 4 1 shows the uPD780053 780054 780055 780056 780058 memory map Figure 4 1 Memory Map Special Function Registers SFR 256 x 8 bits
9. MIN Subseries Name Capacity Interface Value uPD78075B 32 K 40K Sch UART 1ch uPD78078 48 K 60K uPD78070A D780058 24 K 60 K 3ch time division UART 1ch D78058F 48K 60K Sch UART 1ch D78054 16K 60K 0780034 8 32 3ch UART 1 time D780024 division 3 wire 1ch D78014H 2ch D78018F D78014 D780001 D78002 D78083 ich UART 1ch Inverter D780988 32K 60K Sch UART 2ch D780208 32K D780228 48K D78044H 32 D78044F 16K 2ch D780308 48K Sch time division UART 1ch uPD78064B 32K 2ch UART 1 ch uPD78064 16K 32K uPD78098B 40 60 8ch UART 1 ch uPD78098 32K 60K uPD78P0914 32K Note 16 bit timer 2 channels 10 bit timer 1 channel 4 Preliminary Data Sheet OVERVIEW FUNCTION Product Name Internal ROM 780053 780054 780055 780056 780058 780054 1 780055 uPD780056 uPD780058 32K bytes 40K bytes 48K bytes 60K bytes uPD780053 24K bytes memory High speed RAM 1024 bytes Buffer RAM 32 bytes Expanded RAM None 1024 bytes Memory space 64 K bytes General registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks Minimum instruction execution On chip minimum instruction execution time c
10. 1 TH External count clock input to the 8 bit timer TM1 P33 TI2 External count clock input to the 8 bit timer TM2 P34 TO0 Output 16 bit timer TM0 output dual function as 14 bit PWM output P30 1 8 bit timer 1 output P31 TO2 8 bit timer TM2 output P32 PCL Output Clock output for main system clock subsystem clock trimming P35 BUZ Output Buzzer output P36 RTPO RTP7 Output Real time output port by which data is output in synchronization with a trigger P120 P127 ADO AD7 Input Low order address data bus at external memory expansion P40 P47 output Output High order address bus at external memory expansion P50 P57 Output External memory read operation strobe signal output P64 External memory write operation strobe signal output P65 12 Preliminary Data Sheet 3 2 OTHER PINS 2 2 WAIT Input Function Wait insertion at external memory access 780053 780054 780055 780056 780058 Dual Function Pin P66 ASTB Output Strobe output which latches the address information output at port 4 to access external memory P67 ANI ANI7 Input A D converter analog input P10 P17 ANOO ANO1 Output D A converter analog output P130 P131 AVREFo Input A D converter reference voltage input dual function as analog power supply AVREzEF1 Input D A converter
11. 78 0 5 Integrated Debugger PC Based Reference U12900J Planned ID78KO Integrated Debugger EWS Based Reference 1111514 ID78K0 Integrated Debugger Based Reference U11539J U11539E ID78KO Integrated Debugger Windows Based Guide U11649J U11649E Caution The documenis listed above are subject to change without notice Be sure to use the latest documents for designing your system 68 Preliminary Data Sheet 780053 780054 780055 780056 780058 Documents Related to Embedded Software User s Manual Document No Document Name Japanese English 78K 0 Series Real Time OS Fundamentals U11537J U11537E Installation U11536J U11536E 78K 0 Series OS 78 0 Fundamental U12257J U12257E Other Related Documents Document No Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J 11892 Semiconductor Device Quality Reliability Handbook C12769J Microcomputer Product Series Guide U11416J Caution The documents listed above are subject to change without notice Be sure to use the latest documents
12. Circuit fxx 2 Preliminary Data Sheet 23 5 6 A D CONVERTER An A D converter of 8 bit resolution x 8 channels is incorporated The following two types of the A D conversion operation start up methods are available Hardware start Software start 780053 780054 780055 780056 780058 Figure 5 8 A D Converter Block Diagram Series Resistor String ANIO P10 O Sample amp Hold Circuit ANI1 P11 5 Voltage Comparator dual funciton as analog ANI2 P12 C 0 t I power supply ANI3 P13 O T s AV elector ANM P14 9 Selector SS 5 15 ANI6 P16 0 gt Succesive Approxmation 2 i ss ANI7 P17 Register SAR Edge INTP3 P03 6 Detection 2 INTAD Circuit eui gt A D Conversion Result Register ADCR Internal Bus 24 Preliminary Data Sheet 780053 780054 780055 780056 780058 5 7 D A D A converter of 8 bit resolution x 2 channels is available Conversion method is R 2R resistor ladder method Figure 5 9 D A Converter Block Diagram Selector m DACSn Write INTTMx D A Converter Mode Register Internal Bus Conversion Value Set Register n DACSn 5 8 SERIAL INTERFACES Three channels of the clocked serial interface are incorporated
13. Internal Bus Preliminary Data Sheet O TO2 P32 2 Output p TO1 P31 Circuit 21 780053 780054 780055 780056 780058 Figure 5 4 Watch Block Diagram Selector fxx 27 Selector iW Prescaler fxr Selector INTTM3 16 Bit Event Counter Figure 5 5 Watchdog Timer Block Diagram INTWDT Maskable Interrupt Request Selector RESET 8 Bit Counter INTWDT Non Maskable Interrupt Request 22 Preliminary Data Sheet 780053 780054 780055 780056 780058 5 4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequency can be output as a clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz main system clock at 5 0 MHz operation 32 768 kHz subsystem clock at 32 768 kHz operation Figure 5 6 Clock Output Control Circuit Configuration fxx fxx 2 fxx 2 bo 2 Selector Synchronization Output Control PCL P35 fxx 24 Circuit Circuit fxx 26 fxx 29 fxx 27 fxr 5 5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequency can be output as a buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz main system clock at 5 0 MHz operation Figure 5 7 Buzzer Output Control Circuit Block Diagram 1 29 fxx 2 e Selector Output Control G BUZ P36
14. Serifal interface channel 0 Serifal interface channel 1 Serifal interface channel 2 Table 5 3 Types and Functions of Serial Interface Function 3 wire serial mode Serial Interface Channel 0 O MSB LSB first switchable Serial Interface Channel 1 O MSB LSB first switchable Serial Interface Channel 2 O MSB LSB first switchable 3 wire serial mode with automatic transmit receive function O MSB LSB first switchable SBI serial bus interface mode O MSB first 2 wire serial mode O MSB first Asynchronous serial interface UART mode on chip time division transfer function Preliminary Data Sheet O Dedicated baud rate generator incorporated 25 780053 780054 780055 780056 780058 Figure 5 10 Serial Interface Channel 0 Block Diagram Internal Bus SI0 SB0 P25 SO0 SB1 P26 D Serial I O Shift Register 0 SIO0 Selector Busy Acknowledge Output Circuit Selector Bus Release Command Acknowledge Detection Circuit Interrupt Aje Mean INTCSIO Serial Clock Counter Signal Generator fo 2 fxx 2 Serial Clock Control Circuit TO2 4 SCK0 P27 gt lt Figure 5 11 Serial Interface Channel 1 Block Diagram Internal Bus Y Buffer RAM Serial Shift Register 1 5101 Automatic Data Transmit Rece
15. Vpp 2 7 to 5 5 V P60 P63 4 5 Vs Voo lt 5 5 V 2 7 V lt Vop 4 5 V X1 X2 Vpp 2 7 to 5 5 V XT1 P07 XT2 4 5 Vs Voo lt 5 5 V 2 7 Vs Vop 4 5 V Note Output voltage high Voo 4 5 to 5 5 V 1 mA lou 100 uA Output voltage low P50 P57 P60 P63 Vpp 4 5 to 5 5 V lo 15 mA lt lt lt lt lt lt lt lt lt l lt lt lt P01 P05 P10 P17 P20 P27 P30 P37 P40 P47 P64 P67 P70 P72 P120 P127 P130 P131 4 5 to 5 5 V lo 1 6 mA 5 0 SB1 SCKO Vpp 4 5 to 5 5 V open drain pulled up R 1 kQ lo 400 uA Note For use as 7 use an inverter to input the reverse phase of P07 to the XT2 pin Remark The characteristics of a dual function pin and a port pin are the same unless specified otherwise Preliminary Data Sheet 39 780053 780054 780055 780056 780058 DC Characteristics 40 to 85 C Vpp 1 8 to 5 5 V Parameter Test Conditions Input leakage Vin P00 P05 10 17 20 27 current high P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 RESET X1 X2 XT1 P07 XT2 P60 P63 Input leakage P00 P05 P10 P17 P20 P27 current low P30 P37 P40 P47 P50 P57 P64 P67 P70 P72 P120 P127 P130 P131 RESET X1 X2 XT1 P07 XT2 P60 P63
16. 6 interrupt Non maskable sources Internal interrupt 1 Software 1 Test input Internal 1 external 1 Supply voltage Vpp 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Package 80 pin plastic 14 x 14 mm 80 pin plastic TQFP fine pitch 12 x 12 Preliminary Data Sheet 5 780053 780054 780055 780056 780058 CONTENTS 1 PIN CONFIGURATION TOP VIEW U U Uu u u uu uuu u uuu 7 2 BLOCK 2 2 2 aku 9 3s ORIN NIU eel me 10 3 1 PORT PINS uuu 10 3 2 OTHER PINS p M M 12 3 3 PIN I O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS 14 4 idoli o 18 5 PERIPHERAL HARDWARE FUNCTION FEATURES u u u 19 51 e e m 19 5 2 CLOCK GENERATOR O 20 5 3 COUNTER 20 5 4 CLOCK OUTPUT CONTROL CIRCUIT l 23 5 5 BUZZER OUTPUT CON
17. I 1 lt 00 gt lt 4 Operating Mode Data Retension Mode P gt gt STOP Instruction Execution RESET N lt lt Data Retention Timing Standby Release Signal STOP Mode Release by Interrupt Signal HALT Mode STOP Mode lt Operating Mode lt Data Retension Mode Vpp 4 lsREL gt STOP Instruction Execution Standby Release Signal Interrupt Request lt Preliminary Data Sheet 61 780053 780054 780055 780056 780058 Interrupt Input Timing TINTL gt lt TINTH gt INTP0 INTP5 RESET Input Timing 4 RESET 62 Preliminary Data Sheet 780053 780054 780055 780056 780058 12 PACKAGE DRAWINGS 80 PIN PLASTIC QFP 14 14 detail lead end k S t i Q N ITEM MILLIMETERS INCHES Each lead centerline is located within 0 13 mm 0 005 inch of A 17 20 0 20 0 677 0 008 its true position at maximum material condition B 14 00 0 20 0 551 0 009 0 009 C 14 00 0 20 0 55176 008 D 17 20 0 20 0 677 0 008 0 825 0 032 0 825 0 032 0 002 H 0 32 0 06 0 01376 003 0 13 0 005 J 0 65 T P 0 026 T P K 1 60 0
18. P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO P47 AD7 P50 A8 P57 A15 60 6 P64 RD P65 WR P66 WAIT P67 ASTB 14 Input output Independently connect to or Vsso through resistor Independently connect to through resistor Independently connect to Vooo or Vsso through resistor Independently connect to through resistor Independently connect to or Vsso through resistor Preliminary Data Sheet 780053 780054 780055 780056 780058 Table 3 1 Input Output Circuit of Each Pin 2 2 Input Output Pin Name P E Recommended Connection when Not Used Circuit Type P70 SI2 RxDO Independently connect to or Vsso through resistor P71 SO2 TxDO P72 SCK2 ASCK P120 RTPO P127 RTP7 P130 ANOO Independently connect to Vsso through resistor P131 ANO1 RESET XT2 Leave open AVntFO Connect to Vsso AVntF Connect to Vppo AVss Connect to Vsso IC Connect to Vsso or Vssi directly Preliminary Data Sheet 15 780053 780054 780055 780056 780058 Figure 3 1 Pin Input Output Circuits 1 2 Type 8 C Vppo enable DE output Schmitt Triggered Input with Hysteresis Characteristic disable V 550 p gt lt
19. Address taps tAsTH tADH lAsTRD High Order 8 Bit Address External data access wait insertion A8 A15 ADO AD7 ASTB WAIT tasrwR Low Order 8 Bit Address taps lt tASTH tasTRD High Order 8 Bit Address E 1 12 lt iRDWD gt 4 twos lt gt lt 4 lWRADH RC 2 lt P gt lt twrap twr Preliminary Data Sheet 4 gt 4 twr 57 780053 780054 780055 780056 780058 Serial Transfer Timing 3 wire serial mode SCK0 SCK2 tsikm tksim tksom m 1 2 7 8 11 12 n 2 8 12 SBI mode bus release signal transfer tkcys 4 TKL3 4 SCKO 4 tC C C SB0 SB1 SBI mode command signal transfer tkcy3 4 SCKO tsik3 4 SBO SB1 58 Preliminary Data Sheet PD780053 780054 780055 780056 780058 2 wire serial mode SCK0 05 6 SBO SB1 3 wire serial 1 mode with automatic transmit receive function SO1 tsiko 10 9 519 10 10 1 509 10 SCK1 tkL9 10 10 STB 3 wire serial mode with automatic transmit receive function busy process
20. Vpp 2 7 t0 5 5 V 1 4 2n tcy 20 1 37 2n tcy 20 Voo 2 7 to 5 5 V 2 4 2n tcv 20 2 37 2n tcv 20 WAIT input time from trowT1 Vpp 2 7 to 5 5 V tcy 100 tcy 200 trowT2 Vpp 2 7 to 5 5 V 2tcy 100 2tcy 200 WAIT input time from WR Vpp 2 7 to 5 5 V 2tcy 100 2tcy 200 WAIT low level width 1 2n tcy 2 2n tcy Write data setup time Voo 2 7 to 5 5 V 2 4 2n tcy 60 2 37 2n tcy 100 Write data hold time 20 WR low level width Voo 2 7 to 5 5 V 2 4 2n tcv 20 2 37 2n tcv 20 RD delay time from ASTBL tasTRD Vpp 2 7 to 5 5 V 0 4tcy 30 0 37tcy 50 WR delay time from ASTBL tasrwR Vpp 2 7 to 5 5 V 1 4tcv 30 1 37tcv 50 Remarks 1 MCS Oscillation mode selection register OSMS bit 0 2 2 to PCCO Processor clock control register PCC bit 2 to bit 0 3 tcv Tcv 4 4 nindicates number of waits Preliminary Data Sheet 45 780053 780054 780055 780056 780058 b When except MCS 1 PCC2 to PCCO 000B Ta 40 to 85 C 2 0 to 5 5 V Parameter delay time from RDT in external fetch tRDAST Test Conditions tcv 10 tcv 4 20 Address hold time from in external fetch tRDADH tcy 50
21. anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M4 96 5
22. to E correspond to A to E in Figure 6 1 respectively Preliminary Data Sheet 29 780053 780054 780055 780056 780058 Figure 6 1 Interrupt Function Basic Configuration 1 2 A Internal non maskable interrupt Internal Bus Interrupt Priority Control 4 Table Request Circuit ress Generator Standby Release Signal B Internal maskable interrupt Internal J gt Priority Control Circuit Vector Table Address Generator Interrupt Request Standby Release Signal C External maskable interrupt INTPO Internal Bus External Interrupt Mode Register INTM0 Sampling Clock Select Register SCS y Ed Vector Table Interrupt Sampling D S Address Request Clock ci Generator Standby Release Signal Preliminary Data Sheet 30 780053 780054 780055 780056 780058 Figure 6 1 Interrupt Function Basic Configuration 2 2 D External maskable interrupt except INTP0 Internal Bus External Interrupt Mode Register INTM0 Edge Detection Circuit Vector Table Address Generator Interrupt Request Standby Release Signal E Software interrupt Internal Bus Vector Table Address Generator Interrupt Priority Control Request Circuit IF Interrupt request flag IE
23. 16 Bit Timer Event Counter 1 channel 8 Bit Timer Event Counter 2 channels Watch Timer 1 channel Watchdog Timer 1 channel External event counter channel 2 channels Function 20 Timer output output 2 outputs PWM output output Pulse width measurement input Square wave output output 2 outputs Ono shot pulse output output Interrupt request 2 2 Preliminary Data Sheet 780053 780054 780055 780056 780058 INTP1 Output Control Circuit Figure 5 2 16 Bit Timer Event Counter Block Diagram Internal Bus TIO1 PO1 INTP1 16 Bit Capture Selector Compare Register CR00 Watch Timer Output 2 2 fxx 2 TIOO POO INTPO fxx 2 fxx 2 fx 2 TH P33 fxx 2 fxx 29 fx 2 TI2 P34 Edge Detector Match lt 4 gt 00 Too P30 gt INTTM01 16 Bit Capture Compare Register CR01 Internal Bus Figure 5 3 8 Bit Timer Event Counter Block Diagram Internal Bus Selector 8 Bit Compare Register CR10 Match gt INTPO 1 8 Bit Compare Register CR20 Match 8 Bit Timer Register 2 TM2 Clear Output Control Circuit
24. 20 0 063 0 008 0 009 L 0 80 0 20 0 03116 008 0 03 0 001 M 0 472002 0 00710 003 N 0 10 0 004 P 1 40 0 10 0 055 0 004 Q 0 125 0 075 0 005 0 003 7 7 R 39 3 4 s 1 70 MAX 0 067 MAX Preliminary Data Sheet P80GC 65 8BT 63 80 PLASTIC FINE PITCH 0212 64 Each lead centerline located within 0 10 0 004 inch of its true position T P at maximum material condition Preliminary Data Sheet 780053 780054 780055 780056 780058 detail of lead end ITEM MILLIMETERS INCHES 0 009 A 14 0 0 2 0 551 0 009 0 009 B 12 0 0 2 0 472 008 0 009 12 0 0 2 0 472 0 008 0 009 D 14 0 0 2 0 551 0 009 1 25 0 049 G 1 25 0 049 0 05 H 0 22 5 02 0 009 0 002 0 10 0 004 J 0 5 T P 0 020 T P 0 009 K 1 0 0 2 0 0397 0 508 0 008 L 0 5 0 2 0 020 0 008 0 055 M 0 14510 045 0 006 0 002 0 10 0 004 1 05 0 041 Q 0 05 0 05 0 002 0 002 R 5 5 5 5 S 1 27 MAX 0 050 MAX P80GK 50 BE9 4 780053 780054 780055 780056 780058 APPENDIX DEVELOPMENT TOOLS The following development tools are available for developing systems using the 780058 subseries Refer to 5 Cautions when the development tools are used 1 Language processing software RA78K 0 7
25. 214 07210 902 Guarulhos SP Brasil Tel 55 11 6465 6810 Fax 55 11 6465 6829 J98 11 71 780053 780054 780055 780056 780058 FIP and IEbus trademarks of NEC Corporation MS DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT and PC DOS are trademarks of IBM Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsystems Inc NEWS and NEWS OS are trademarks of Sony Corporation The documents referred to in this publication may include preliminary versions However preliminary versions are not marked as such The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectua
26. 5 V 2 0 V lt Voo lt 2 7 V ASCK rise fall time 54 tris tF13 4 5 to 5 5 V when not using external device expansion function Preliminary Data Sheet 780053 780054 780055 780056 780058 AC Timing Test Point Excluding X1 XT1 Input 0 8 0 8 Test Poi 0 2 Voo 12 Points 0 2 Voo Clock Timing Vina MIN X1 Input Vius MAX XT1 Input Vins MIN s Vis MAX TI Timing 86 troo trito troo TIOO TIO1 m 1 1 2 Preliminary Data Sheet 55 780053 780054 780055 780056 780058 Read Write Operation External fetch no wait A8 A15 High Order 8 Bit Address ADO AD7 tRDADH tAsTH lRDAST ASTB RD lASTRD 9 4 4 gt External fetch wait insertion A8 A15 High Order 8 Bit Address lt Low Order AD0 AD7 8 Bit Address taps trop1 t tRDADH TASTH t lRDAST p ASTB RD tASTRD 4 tRDL1 gt 4 gt WAIT twrRD trowT1 twit gt a gt 56 Preliminary Data Sheet External data access no A8 A15 ADO AD7 ASTB 780053 780054 780055 780056 780058 Low Order 8 Bit
27. A14 O 57 15 O P60 O P61 O P62 O P63 O P64 RD O Cautions 1 Directly connect the Internally Connected pins to Vsso Vss 2 Connect the AVss pin to Vsso Remarks 1 xxx indicates ROM code suffix 2 Ifthe microcontroller is used in an application where the noise generated from the microcontroller must be suppressed it is recommended that power be supplied to Vppo and from separate sources and that Vsso and Vss be connected to separate group lines to improve noise immunity Preliminary Data Sheet 7 A8 A15 ADO AD7 ANIO ANI7 ANOO ANO1 ASCK ASTB 1 AVss BUSY BUZ IC INTPO INTP5 P00 P05 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 780053 780054 780055 780056 780058 Address Bus Address Data Bus Analog Input Analog Output Asychronous Serial Clock Address Strobe Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals PortO Porti Port2 Port3 Port4 Port5 Port6 Port7 Porti2 P130 P131 PCL RD RESET RTPO RTP7 RxD0 RxD1 SBO SB1 SCKO SCK2 510 512 500 502 STB 00 TIO1 TH TI2 TOO TO2 TxDO TxD1 Vsso Vsst WAIT WR X1 X2 XT1 XT2 Preliminary Data Sheet Port13 Programmable Clock Read Strobe Reset Real Time Output Port Receive Data Serial Bus
28. General Registers 32 x 8 bits Internal High Speed RAM Note 3 FBOOH FAFFH Use Prohibited FAEOH Data Memory FADFH Space Internal Buffer RAM 32 x 8 bits FACOH FABFH Use Prohibited FA80H FA7FH External Memory Program Memory Space nnnnH 1 nnnnH Internal ROM Nete3 Y Y 0000H Notes 1 780058 only Use Prohibited Internal Expanded RAM 1024 x 8 bits Note 1 Use Prohibited Note 2 nnnnH Program Area 1000H CALLF Entry Area 0800H 07FFH Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area 0000H 2 When the external device expansion function is used with the 780058 the internal ROM capacity to 56K bytes or less using the memory size switching register IMS 3 The internal ROM capacity depends on the products see the next table Relevant Product Name 780053 Internal ROM Last Address nnnnH uPD780054 780055 uPD780056 uPD780058 18 Preliminary Data Sheet 780053 780054 780055 780056 780058 5 PERIPHERAL HARDWARE FUNCTION FEATURES 5 1 PORTS The following three types of I O ports are available e CMOS input P00 P07 2 CMOS input output 1 05 port 1 port 5 P64 P67 port 7 port 12 port 13 62 N channel open drain input output P60 P63 4 Total 68 Pin Name P00 P07 Table 5 1 Port Functions Functi
29. Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag Preliminary Data Sheet 31 6 2 TEST FUNCTIONS 780053 780054 780055 780056 780058 There are two sources of test functions as shown in Table 6 2 Table 6 2 Test Input Source List Test Input Source INTWT Watch timer o Trigger verflow Internal External Internal INTPT4 Port 4 falling edge detection Figure 6 2 Test Function Basic Configuration I Internal Bus Test Input flag IF Test input flag MK Test mask flag 32 Preliminary Data Sheet External Standby Release Signal 780053 780054 780055 780056 780058 7 EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion functions connect external devices to areas other than the internal ROM RAM and SFR Ports 4 to 6 are used for external device connection 8 STANDBY FUNCTION There are the following two standby functions to reduce the system power consumption HALT mode The CPU operating clock is stopped The average current consumption can be reduced by intermittent operation in combination with the normal operating mode STOP mode The main system clock oscillation is stopped The whole operation by the main system clock is stopped so that the system operates with ultra low power consumption using only the subsystem clock Figure 8 1 Standby Functi
30. and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Preliminary Data Sheet NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Rodovia Presidente Dutra Km
31. for designing your system Preliminary Data Sheet 69 780053 780054 780055 780056 780058 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Ea
32. load capacitance of the SO2 output line ii 3 wire serial I O mode SCK2 External clock input Parameter Test Conditions SCK2 cycle time 2 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK2 high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 12 setup time to SCK27 tsik12 2 0 to 5 5 V 12 hold time from 5 27 tksi12 SO output delay time from SCK24 100 Voo 2 0 to 5 5 V SCK2 rise fall time Other than below Vpp 4 5 to 5 5 V When not using external device expansion function Note Cis the load capacitance of the 502 output line Preliminary Data Sheet 53 780053 780054 780055 780056 780058 iii UART mode Dedicated baud rate generator output Parameter Transfer rate Test Conditions 4 5 V lt lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V iv UART mode External clock input Parameter ASCK cycle time Test Conditions 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V ASCK high low level width tkL13 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V Transfer rate 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4
33. to ultra low speed 122 us ports 68 pins N ch open drain 4 pins 8 bit resolution A D converter 8 channels Vpp 2 7 to 5 5 V 8 bit resolution D A converter 2 channels Vpp 2 7 to 5 5 V Serial interface 3 channels Timer 5 channels Operating voltage range 1 8 to 5 5 V APPLICATION FIELDS Car audio systems cellular phones pagers printers AV systems cameras PPCs and vending machines The information in this document is subject to change without notice Document No U12182EJ1V1DS00 1st edition The mark shows major revised points Date Published January 1999 N CP K Printed in Japan Corporation 1997 780053 780054 780055 780056 780058 ORDERING INFORMATION Part Number Package 780053 8 80 pin plastic 14 x 14 uPD780053GK ooc BE9 80 pin plastic TQFP fine pitch 12 x 12 mm 780054 8 80 pin plastic QFP 14 x 14 780054 9 80 plastic fine pitch 12 x 12 780055 8 80 pin plastic 14 x 14 uPD780055GK ooc BE9 80 pin plastic TQFP fine pitch 12 x 12 mm 780056 8 80 plastic QFP 14 x 14 780056 80 pin plastic fine pitch 12 x 12 780058 8 80 plastic 14 x 14 uPD780058GK ooc BE9 80 pin plastic TQFP fine pitch 12
34. x 12 mm Remark xxx indicates ROM code suffix 2 Preliminary Data Sheet 780053 780054 780055 780056 780058 78 0 SERIES PRODUCT DEVELOPMENT The following shows the 78K 0 Series products development Subseries name are shown inside frames Control 100 100 uPD78078Y 100 Du A 7 1 80 pin uPD780058 780058 80 uPD78058F uPD78058FY 80 64 pin 780034 uPD780034Y 1 64 pin uPD780024 64 pin uPD78014H 64 pin 64 pin 78014 uPD78014Y 64 pin 64pin L 42 44 pin Inverter control 64 pin uPD780988 FIP drive 78K 0 100 pin uPD780208 Series 100 pin 780228 80 pin 7 uPD78044H L 80 pin uPD78044F LCD drive m 100 pin uPD780308 uPD780308Y 100 pin uPD78064B 100 pin uPD78064 uPD78064Y IEBus supported 80 pin uPD78098B 80 pin 1 78098 Meter control d v uPD780973 Note Under planning Products in L mass production EEEE Oe development Y subseries products are compatible with bus EMI noise reduced version of the 78078 A timer was added to the 78054 and external interface was enhanced ROM less version of the uPD78078 Serial I O of the uPD78078Y was enhanched the function is limited Serial
35. 0 P131 RTP0 P120 RTP7 P127 AD0 P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 2 1 7 XT2 3 FUNCTIONS 3 1 PORT PINS 1 2 Pin Name P00 P01 P02 P03 P04 P05 po7Note 1 780053 780054 780055 780056 780058 Function Port 0 Input only Dual Function Pin INTPO TIOO 7 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software INTP1 TIO1 INTP2 4 5 Input only XT1 P10 P17 Port 1 8 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by softwareNote 2 ANIO ANI7 P20 P21 P22 P23 P24 P25 P26 P27 Port 2 8 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software SH 501 SCK1 STB TxD1 BUSY RxD1 SI0 SB0 SO0 SB1 SCK0 P30 P31 P32 P33 P34 P35 P36 P37 Port 3 8 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software TO0 TO1 TO2 TH 2 PCL BUZ P40 P47 Notes 1 10 Port 4 8 bit input output port Input output can be specified in 8 bit unit When used as an input port on chip pull up resistor
36. 0 pF Note 2 7 V lt Voo lt 5 5 V 1600 3200 4800 2 7 to 5 5 V tkcvs 2 160 5 2 190 4 5 to 5 5 V 5 2 50 5 2 100 4 5 V lt Voo lt 5 5 V 300 2 7 V lt Voo lt 4 5 V 350 2 0 V lt Voo lt 2 7 V 400 500 SB0 SB1 hold time 600 from SCKOT SBO SB1 output delay time from SCKOL Note R and are the load resistors and load capacitance of the SBO and SB1 output line 2 wire serial I O mode SCKO Internal clock input Test Conditions 2 7 V lt Voo lt 5 5 V 1600 Parameter SCK0 cycle time 2 0 V lt Voo lt 2 7 V 3200 4800 SCKO high level width 2 7 V lt Voo lt 5 5 V 650 2 0 V lt Voo lt 2 7 V 1300 2100 SCKO low level width 2 7 V lt Voo lt 5 5 V 800 2 0 V lt Voo lt 2 7 V 1600 2400 SB0 SB1 setup time Voo 2 0 to 5 5 V 100 to 150 5 0 SB1 hold time tkcve 2 from SCKOT 5 0 SB1 output delay time from SCKOL 1 4 5 V lt Voo lt 5 5 V 100 pF 20 V lt Voo lt 4 5 V rise fall time tre tre When using external device expansion function When not using external device expansion function Note C are the load resistors and load capacitance of the SBO and SB1 output line Prelimi
37. 00GC 80 Socket to be mounted on the board of the target system for 80 pin plastic QFP GC 8BT type ID78KO NSNote Integrated debugger for IE 78K0 NS SM78KO 78K 0 series common system simulator DF780058 Note Under development Device file for the 780058 subseries Preliminary Data Sheet 65 780053 780054 780055 780056 780058 When using the IE 78001 R A in circuit emulator IE 78001 R ANote 78K 0 series common in circuit emulator 70000 98 IE 70000 98 IF CNete Interface adapter necessary when a PC 9800 series computer except notebook type personal computer is used as host machine IE 70000 PC IF B IE 70000 PC IF CNete Interface adapter necessary when an IBM PC AT or a compatible machine is used as host machine IE 78000 R SV3 Interface adapter and cable necessary when an EWS is used as host machine IE 780308 NS EM 1 Note IE 780308 R EM Emulation board common to the uPD780308 subseries IE 78KO R EX1 Note Emulation probe conversion board necessary when the IE 780308 NS EM 1 is used in the IE 78001 R A EP 78230GC R Emulation probe for 80 pin plastic QFP GC 8BT type EP 78054GK R Emulaiton probe for 80 pin plastic GK BE9 type TGK 080SDW Conversion adapter to connect the board of the target system to be mounted on 80 pin plastic GK BE9 type and EP 78054GK R EV 9200GC 80 Socket to be
38. 2 Voo 2 7 to 3 5 V 0 8 Operating on subsystem clock 40Note 3 7100 input high 3 5 V lt lt 5 5 V 2lfsam 0 1 Note 4 low level width 2 7 V lt Voo lt 3 5 V 2Jsa 0 2Note 4 2 sam 0 5Note 4 01 input high triHo1 2 7 to 5 5 V 10 low level width triLot 20 1 2 TI5 6 fmi Voo 4 5 to 5 5 V 0 input frequency 0 1 2 TI5 6 Vpp 4 5 to 5 5 V 100 input high 1 8 low level width Interrupt request 3 5 V lt Voo lt 5 5 V 2 fsa 0 1Note 4 input high 2 7 V lt lt 3 5 V fsam 0 2Note 4 low level width 2 fsam 0 5NOte 4 INTP1 INTP5 P40 P47 Vpp 2 7 to 5 5 V 10 20 RESET low Vpp 2 7 to 5 5 V 10 level width 20 Notes 1 Operation with fxx fx 2 when oscillation mode selection register OSMS is set to 00H 2 Operation with fxx fx when OSMS is set to 01H 3 Value when external clock is used When a crystal resonator is used it is 114 us MIN 4 In combination with bits 0 SCS0 and 1 SCS1 of sampling clock select register SCS selection of fsam is possible between fxx 2 fxx 32 fxx 64 and fxx 128 when N 0 to 4 42 Preliminary Data Sheet 780053 780054 780055 780056 780058 Tcv vs At fxx fx 2 main system clock operation Tcv vs At fxx fx main system clock operation
39. 6 laddr16 PSW DE HL HL Byte HL B HL C X C Note Except r A 34 Preliminary Data Sheet 780053 780054 780055 780056 780058 2 16 bit instruction XCHW ADDW SUBW CMPW PUSH INCW DECW Second Operand First Operand laddr16 rp MOVW Nete INCW DECW PUSH POP sfrp MOVW saddrp MOVW laddr16 MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instruction MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand sfr bit saddr bit PSW bit HL bit addr16 First Operand saddr bit PSW bit HL bit 4 Call instruction branch instruction CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand laddr16 laddr11 addr16 First Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP Preliminary Data Sheet 35 780053 780054 780055 780056 780058 11 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 25 C Parameter Test Conditions Supply voltage 0 3 to 7 0 0 3 to Voo 0 3 0 3 to Voo 0 3 AVRzEr1 0 3 to Voo 0 3 AVss 0 3 to 0 3 Input voltage
40. 780058 1 CONFIGURATION 80 pin plastic QFP 14 x 14 780053 8 7800540 8 780055GC xxx 8BT 780056GC xxx 8BT 7800580 8 80 pin plastic fine pitch 12 x 12 mm 780053 9 780054GK xxx BE9 780055GK xxx BE9 780056GK xxx BE9 780058GK xxx BE9 4 3 2 1 0 NTP1 TIO1 NTPO TIOO O Q N n EEEE z z z z 22222 5 lt lt lt lt lt R Z lt SS lt lt lt u 6 3 ON re A gt o O O lt gt ox gt gt QUU CA 0097 CD SO i 15 5 O 1 O 16 6 O 2 127 7 17 7 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANO0 O 5 O P124 RTP4 131 1 O 6 O P123 RTP3 AVrer1 7 O P122 RTP2 P70 SI2 RxDO O 8 O P121 RTP1 P71 SO2 TxDO O 9 O P120 RTP0 P72 SCK2 ASCK O 10 O P37 20 5 O 11 O P36 BUZ P21 SO1 O 12 O P35 PCL P22 SCK1 O 13 P34 TI2 P23 STB TxD1 O 14 O P33 TI1 P24 BUSY RxD1 O 15 O P32 TO2 P25 SIO SBO 16 O P31 TO1 P26 SO0 SB1 O 17 P30 TOO P27 SCKO 18 P67 ASTB P40 ADO O 19 P66 WAIT P41 AD1 O 20 P65 WR N k P42 AD2 O P43 AD3 O P44 AD4 O P45 AD5 O P46 AD6 O P47 AD7 O P50 A8 O P51 A9 O P52 A10 O P53 A11 O P54 A12 O P55 A13 O Vssi O P56
41. 80056 780058 Main System Clock Oscillation Circuit Characteristics 40 to 85 Vpp 1 8 to 5 5 V Recommended hn Parameter Test Conditions Circuit Resonator Ceramic Oscillator Vpp Oscillator resonator frequency fx Nete 1 voltage range Oscillation After Voo reaches oscil stabilization time Nete2 lator voltage range MIN Crystal Oscillator resonator frequency Note 1 Oscillation Vpp 4 5 to 5 5 V stabilization time Note 2 External X1 input clock frequency fx Note 1 X1 input LPD74HCUO4 high low level width tx Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillator wirinin the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillator capacitor ground should be the same as Vss1 Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillator 2 When main system clock is stopped and the system is operated by the subsystem clock the s
42. 8K 0 series common assembler package CC78K 0 78K 0 series common C compiler package DF780058 Device file for the 780058 subseries CC78K 0 L 78K 0 series common C compiler library source file 2 Flash memory writing tools Flashpro 11 Part number FL PR2 Dedicated flash programmer for microcomputers incorporating flash memory FA 80GCNete FA 80GKNete Note Under development 3 Debugging tools Adapter for flash memory writing When using the IE 78KO NS in circuit emulator IE 78K0 NSNete 78K 0 series common in circuit emulator IE 70000 MC PS B Power supply unit for IE 78K0 NS IE 70000 98 IF CNete Interface adapter necessary when a PC 9800 series computer except notebook type personal computer is used as host machine IE 70000 CD IFNote PC card and interface cable necessary when a PC 9800 series notebook type personal computer is used as host machine IE 70000 PC IF CNete Interface adapter necessary when an IBM or a compatible machine is used as host machine IE 780308 NS EM 1Nete Emulation board common to the uPD780308 subseries NP 80GCNete Emulation probe for 80 pin plastic QFP GC 8BT type NP 80GKNete Emulation probe for 80 pin plastic GK BE9 type TGK 080SDW Conversion adapter to connect the board of the target system to be mounted on 80 pin plastic GK BE9 type NP 80GK EV 92
43. I O of the uPD78054 was enhanced and EMI noise was reduced EMI noise reduced version of the 78054 UART and D A converter were added to the 78014 and I O was enchanced A D converter of the 780024 was enchanced Serial of the uPD78018F was added EMI noise reduced version of PD78018F Low voltage 1 8 V operation version of the uPD78014 with larger selection of ROM and RAM capacities An A D converter and 16 bit timer were added to the 78002 An A D converter was added to the 78002 Basic subseries for control On chip UART capable of operating at low voltage 1 8 V On chip inverter control circuit and UART EMI noise was reduced and FIP C D of the uPD78044F were enhanced Display output total 53 I O and FIP C D of the uPD78044H were enhanced Display output total 48 N ch open drain was added to the 78044 Display output total 34 Basic subseries for driving FIP Display output total 34 The SIO of the 78064 was enhanced and ROM RAM capacity increased EMI noise reduced version of the 78064 Basic subseries for driving LCDs On chip UART EMI noise reduced version of the 78098 An IEBus controller was added to the uPD78054 On chip controller driver for automotive meter drive Preliminary Data Sheet 3 780053 780054 780055 780056 780058 following lists the main functional differences between subseries products Function ROM Serial
44. KO RX78K 0 78 0 Note DOS based software Preliminary Data Sheet 67 780053 780054 780055 780056 780058 APPENDIX RELATED DOCUMENTS Documents Related Devices Document No Document Name Japanese English 780058 780058Y Subseries User s Manual U12013J U12013E 780053 780054 780055 780056 780058 Data Sheet U12182J This document 78 0058 Preliminary Product Information U12092J U12092E 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78 0 Series Instruction Set U10904J Development Tool Documents User s Manual Document No Document Name Japanese English RA78K0 Assembler Package Operation U11802J U11802E Assembly Language U11801J U11801E Structured Assembly U11789J U11789E Language RA78K Series Structured Assembler Preprocessor U12323J EEU 1402 CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K 0 C Compiler Application Note Programming Know How U13034J U13034E CC78K Series Library Source File U12322J IE 78K0 NS Planned Planned IE 78001 R EM Planned Planned IE 780308 NS EM1 Planned Planned IE 780308 R EM U11362J U11362E EP 78230 EEU 985 EEU 1515 EP 78054GK R EEU 932 EEU 1468 5 78 0 System Simulator Windows Based Reference U10181J U10181E SM78K Series System Simulator External Part User Open U10092J U10092E Interface Specifications
45. O from SBO 581 SB0 SB1 high level width SB0 SB1 low level width Note are the load resistors and load capacitance of the SCKO SBO and SB1 output line iv SBI mode SCKO External clock input Parameter Test Conditions SCKO cycle time 4 5 V lt Voo lt 5 5 V 800 2 0 V lt Voo lt 4 5 V 3200 4800 high low level width 4 5 V lt lt 5 5 V 400 2 0 V lt lt 4 5 V 1600 2400 SBO SB1 setup time 4 5 V lt Voo lt 5 5 V 100 to SCK0T 2 0 V lt Voo lt 4 5 V 300 400 SB0 SB1 hold time tksi4 tkcv4 2 from SCKOT SBO SB1 output delay tkso R 1kQ Vpp 4 5 to 5 5 V time from C 100 pF Note 580 5 1 from SCK01 from SBO 5 1 tsek 580 SB1 high level width SBO SB1 low level width tse 5 rise fall time tra tra When using external device expansion function When not using external device expansion function Note R and are the load resistors and load capacitance of the SBO and SB1 output line 48 Preliminary Data Sheet 780053 780054 780055 780056 780058 2 wire serial mode SCK0 Internal clock output Parameter 5 cycle time SCKO high level width SCKO low level width 580 SB1 setup time to SCK0T Test Conditions 1 C 10
46. PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT uPD780053 780054 780055 780056 780058 8 SINGLE CHIP MICROCONTROLLER DESCRIPTION The uPD780053 780054 780055 780056 and 780058 are members of the uPD780058 subseries in the 78 0 series These microcontrollers suppress the EMI Electro Magnetic Interference noise internally generated to the lower level than the existing uPD78054 subseries In addition they have many peripheral hardware units such as an 8 bit resolution A D converter 8 bit resolution D A converter timers serial interface real time output ports and interrupt functions A flash memory model that can operate on the same voltage as the mask ROM models uPD78F0058 and various development tools are now under development The funcitons are explaned in detail in the following User s Manuals Be sure to read these manuals when designing your system uPD780058 780058Y Subseries User s Manual U12013E 78K 0 Series User s Manual Instruction U12326E FEATURES Internal high capacity ROM amp RAM Program Memory Data Memory Part Number ROM Internal high speed RAM Internal buffer RAM Internal expanded RAM 780053 24 bytes 1024 bytes 32 bytes 780054 32K bytes uPD780055 40K bytes uPD780056 48K bytes 780058 60K bytes 1024 bytes External memory expansion space 64K bytes Minimum instruction execution time changeable from high speed 0 4 us
47. Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clock 2 BLOCK DIAGRAM 16 bit TIMER TI00 INTP0 P00 TIO1 INTP1 P01 TO1 P31 8 bit TIMER EVENT COUNTER 1 TO2 P32 8 bit TIMER TI2 P34 EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SIO SBO P25 SERIAL i INTERFACE 0 o 78K 0 ROM CPU CORE SH P20 SO1 P21 SERIAL SCK1 P22 STB TxD1 P23 BUSY RxD1 P24 BUSY RxD1 P24 STB TxD1 P23 SI2 RxD0 P70 SERIAL 02 TxD0 P71 INTERFACE 2 SCK2 ASCK P72 RAM ANIO P10 ANI7 P17 A D CONVERTER AVss 130 ANOT PISI D A CONVERTER AVss AVREF1 INTP0 P00 INTERRUPT INTP5 P05 CONTROL BUZ P36 BUZZER OUTPUT CLOCK OUTPUT Vsso IC PCL P35 CONTROL Vss1 PORTO PORT1 PORT2 PORTS 4 PORT5 PORT6 PORT7 PORT12 PORT13 REAL TIME OUTPUT PORT Ec EXTERNAL ACCESS SYSTEM CONTROL Remark The internal ROM and RAM capacities differ depending on the product Preliminary Data Sheet 780053 780054 780055 780056 780058 00 01 05 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P13
48. TROL Ullu UU UU 23 5 6 A D UU uuu 24 5 7 D A GONVERTER uu IU IIIa Sasa sasa suassauusussasasassaasasnasssassasassaasasassasaswasusasassaasasassussaasus 25 5 8 SERIAL INTERFACES 2 25 5 9 REAL TIME OUTPUT PORT 8 1 tenens nessuna 27 6 INTERRUPT FUNCTIONS 22 2 4 u u u uu u 28 6 1 INTERRUPT FUNCTIONS I UU i ninos ERI Tasa UAR UAE M RA ER KRSEL AE KERN KR MER RO R RSEN EUN 28 6 2 TEST FUNCTIONS l uu u RARUS 32 EXTERNAL DEVICE EXPANSION FUNCTIONS 1 u 33 8 STANDBY FUNCTION 33 9 pem mm 33 10 INSTRUCTION ism 34 11 ELECTRICAL SPECIFICATIONS U U 36 12 PACKAGE DRAWINGS a sna snnt 63 APPENDIX A DEVELOPMENT TOOLS eres 65 APPENDIX B RELATED DOCUMENTS U nennen u u u uuu uuu u 68 6 Preliminary Data Sheet 780053 780054 780055 780056
49. TSR End of serial interface channel 2 UART reception INTCSI2 End of serial interface channel 2 3 wire transfer INTS End of serial interface channel 2 UART transmission Notes 1 The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously 0 is the highest order and 17 the lowest 2 Basic configuration types A to E correspond to A to E in Figure 6 1 respectively 28 Preliminary Data Sheet 780053 780054 780055 780056 780058 Table 6 1 Interrupt Source List 2 2 Note 1 Basic Interrupt Default Interrupt Source Internal Vector Table Configuration Type Priority Trigger External Address TypeNete 2 Referencetime interval signalfromwatch Internal timer INTTMOO Generation of match signal of 16 bit timer register and capture compare register 00 INTTMO1 Generation of match signal of 16 bit timer register and capture compare register CRO1 INTTM1 Generation of match signal of 8 bit timer event counter 1 INTTM2 Generation of match signal of 8 bit timer event counter 2 End of conversion by A D converter Software BRK instruction execution Notes 1 The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously 0 is the highest order and 17 the lowest 2 Basic configuration types A
50. amplification level more prone to misoperation due to noise than the main system clock Therefore when using the subsystem clock take care with the wiring Capacitance 25 C Vpp Vss 0 V Parameter Test Conditions Input f21MHz capacitance Measured pins returned to 0 V Input output f21MHz P01 P05 P10 P17 capacitance Measured pins returned to 0 V P20 P27 P30 P37 40 47 P50 P57 P64 P67 P70 P72 P120 P127 P130 P131 P60 P63 Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 38 Preliminary Data Sheet 780053 780054 780055 780056 780058 DC Characteristics 40 to 85 C 1 8 to 5 5 V Parameter Input voltage high Test Conditions P10 P17 P21 P23 P30 P32 P35 P37 P40 P47 P50 P57 P64 P67 P71 P120 P127 P130 P131 Vpp 2 7 to 5 5 V P00 P05 P20 P22 P24 P27 P33 P34 P70 P72 RESET Vpp 2 7 to 5 5 V P60 P63 N ch open drain Vpp 2 7 to 5 5 V X1 X2 Vpp 2 7 to 5 5 V XT1 P07 XT2 4 5 Vs Voo lt 5 5 V 2 7 V lt Vop 4 5 V Note Input voltage low P10 P17 P21 P23 P30 P32 P35 P37 P40 P47 P50 P57 P64 P67 P71 P120 P127 P130 P131 2 7 to 5 5 V lt lt lt lt lt lt lt lt lt lt P00 P05 20 P22 24 27 P33 P34 P70 P72 RESET
51. can be used by software Test input flag KRIF is set to 1 by falling edge detection mode Use of the on chip pull up resistor is cancelled automatically Preliminary Data Sheet ADO AD7 When using the PO7 XT1 pins as an input port set 1 in the bit 6 FRC of the processor clock control register PCC On chip feedback resistor of the subsystem clock oscillator should not be used When using the P10 ANIO to P17 ANI7 pins as the A D converter analog input pins set port 1 to input 780053 780054 780055 780056 780058 3 1 PORT PINS 2 2 Dual Pin Name Function Function Pin P50 P57 Port 5 8 bit input output port LED can be driven directly Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software Port 6 N ch open drain input 8 bit input outport port Input output can be output port On chip pull specified bit wise up resistor can be used by mask option LED can be driven directly When used as an input port on chip pull up resistor can be used by software ASTB Port 7 SI2 RxDO 3 bit input output port SO2 TxD0 Input output can be specified bit wise P72 When used an input port on chip pull up resistor can be used by software SCK2 ASCK P120 P127 Port 12 RTP0 RTP7 8 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by
52. ch unused pin should be connected to Vpp or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Produc 70 tion process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed imme diately after power on for devices having reset function Preliminary Data Sheet 780053 780054 780055 780056 780058 Regional Information Some information contained in this document may vary from country to country Before using any NEG product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages
53. ddress hold time from tRDADH 0 85tcy 50 1 15tcy 50 RDT in external fetch Write data output time from trowo 40 Write data output time from WR twawo 0 50 Address hold time from WRT twraDH 0 85tcy 1 15tcy 40 RDT delay time from WAITT twrRD 1 15tcv 40 3 15tcv 40 WRT delay time from WAITT twrwR 1 15tcv 30 3 15tcv 30 Remarks 1 MCS Oscillation mode selection register OSMS bit 0 2 PCC2 to PCC0 Processor clock control register PCC bit 2 to bit 0 3 4 4 nindicates number of waits 44 Preliminary Data Sheet 780053 780054 780055 780056 780058 b When except MCS 1 PCC2 to PCCO 000B Ta 40 to 85 C Vm 2 0 to 5 5 V Parameter ASTB high level width Test Conditions Vpp 2 7 to 5 5 V 80 tcv 150 Address setup time Vpp 2 7 to 5 5 V tcv 80 tcv 150 Address hold time 2 7 to 5 5 V 0 4tcy 10 0 37tcy 40 Data input time from address Vpp 2 7 to 5 5 V 3 2n tcv 160 3 2n tcv 320 Vpp 2 7 to 5 5 V 4 2n tcy 200 4 2n tcy 300 Data input time from Vpp 2 7 to 5 5 V 1 4 2n tcv 70 1 37 2n tcv 120 Vpp 2 7 to 5 5 V 2 4 2n tcv 70 2 37 2n tcv 120 Read data hold time 0 RD low level width
54. ing 7 7 SCK1 7 Q Note x 10 Note Note teys 5 5 gt BUSY Active high Note The signal is not actually driven low here it is shown as such to indicate the timing Preliminary Data Sheet 59 780053 780054 780055 780056 780058 UART mode external clock input tkcy13 gt ASCK A D Converter Characteristics TA 40 to 85 Vpp 2 7 to 5 5 V AVss Vss 0 V Parameter Test Conditions Resolution 8 Overall errorNote 1 0 Conversion time tconv 16 100 Sampling time 12 fxx Analog input voltage VIAN AVss AV REFO Reference voltage AVntro 2 7 AVnero current Inero When A D converter is operatingNete 2 1500 When A D converter is not operatingNote 3 3 Resistance between AVrero and AVss When A D conversion is not performed Notes 1 Overroll error excluding quantization error 1 2 LSB It is indicated as a ratio to the full scale value 2 The current flowing to pin when bit 7 CS of the A D converter mode register ADM is 1 3 The current flowing to pin when bit 7 CS of the A D converter mode regidter ADM is 0 Remark Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency D A Converter Characteristics TA 40 to 85 Vpp 2 7 to 5 5 V AVss V
55. ion SCK1 External clock input Parameter Test Conditions SCK1 cycle time tkcvio 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK1 high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V setup time to SCK1T tskio 2 0 to 5 5 V SI1 hold time from SCK1T 501 output delay time from SCK11 tksoro C 100 pF Voo 2 0 to 5 5 V SCK1 rise fall time trio 1 When using external device expansion function When not using external device expansion function Note Cis the load capacitance of the 501 output line 52 Preliminary Data Sheet 780053 780054 780055 780056 780058 Serial interface channel 2 i 3 wire serial I O mode SCK2 Internal clock output Parameter Test Conditions SCK2 cycle time 4 5 V lt lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1600 2 0 V lt Voo lt 2 7 V 3200 4800 SCK2 high low level width tkH11 Voo 4 5 to 5 5 V 11 2 50 11 2 100 12 setup time to SCK2T 4 5 V lt Von lt 5 5 V 100 2 7 V lt Vo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 12 hold time from 5 27 400 502 output delay time from SCK24 100 pF Note Note is
56. ive Address Pointer Automatic Data Transmit Receive Interval Specification Register ADTI Match 1 20 01 21 STB TxD1 P23 Handshake Control BUSY RxD1 P24 Circuit 1 22 Serial Clock Counter Interrupt Request Signal Generator 2 28 2 Serial Clock Control Circuit 26 Preliminary Data Sheet 780053 780054 780055 780056 780058 Figure 5 12 Serial Interface Channel 2 Block Diagram RxDO SI2 P70 RxD1 BUSY P24 O TxD0 SO2 P71 O TxD1 STB P23 O Selector Internal Bus Receive Buffer Register RXB SIO2 Direction Control Circuit Receive Shift Register RXS Receive Control Circuit INTSER INTSR INTCSI2 Direction Control Circuit Transmit Shift Register TXS SIO2 A 1 Transmit Control Circuit 4 SCK Output ASCK SCK2 P72 O Control Circuit VAJA 5 9 REAL TIME OUTPUT PORT FUNCTIONS Data set previously in the real time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output to off chip This is real time output function And pins to output to off chip are called real time output ports By using a real time output port a signal which has no jitter can be outpu
57. l property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems
58. mounted on the board of the target system made for the 80 pin plastic QFP GC 8BT type ID78KO Integrated debugger for IE 78001 R A SM78KO 78K 0 series common system simulator DF780058 Note Under development 4 Real time OS RX78K 0 Device file for the 780058 subseries Real time OS for 78K 0 series MX78KO OS for 78K 0 series 66 Preliminary Data Sheet 780053 780054 780055 780056 780058 5 Cautions when the development tools are used The ID78K0 NS ID78K0 and 5 78 0 are used in combination with the DF780058 The CC78K 0 and RX78K 0 are used in combination with the RA78K 0 and DF780058 Flashpro 1 FA 80GC FA 80GK NP 80GC and NP 80GK are products of Densei Machida Mfg Co Ltd TEL 044 822 3813 Contact an NEC distributor when purchasing these products TGK 080SDW is a product of Tokyo Eletech Corp Inquiry Daimaru Kogyo Ltd Electronics Dept TEL Tokyo 03 3820 7112 Electronics 2nd Dept TEL Osaka 06 244 6672 e Refer to the 78K 0 Series Selection Guide U11126E for information on third party development tools Host machines and OSs compatible with the software are as follows Host Machine OS PC EWS PC 9800 Series Windows HP9000 series 700 HP UX IBM PC AT and compatible machines SPARCstation SunOS Software Japanese English Windows NEWS RISC NEWS OS M RA78K 0 CC78K 0 ID78K0 NS ID78K0 SM78
59. nary Data Sheet 49 780053 780054 780055 780056 780058 b Serial interface channel 1 i 3 wire serial mode SCK1 Internal clock output Parameter Test Conditions SCK1 cycle time 4 5 V lt Voo lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1600 2 0 V lt Voo lt 2 7 V 3200 4800 SCK1 high low level width tkuz 4 5 to 5 5 V 7 2 50 2 100 SI1 setup time to SCK11 4 5 V lt Voo 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 SI1 hold time from SCK11 400 501 output delay time from SCK11 C 100 pF Note Note Cis the load capacitance of the SO1 output line ii 3 wire serial I O mode SCK1 External clock input Parameter Test Conditions SCK1 cycle time 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK1 high low level width 4 5 V lt lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V setup time to 5 17 2 0 to 5 5 V 511 hold time from SCK1 501 output delay time from 1 4 100 pF Von 2 0 to 5 5 V SCK1 rise fall time trs tre When using external device expansion function When not using external device expansion function Note Cisthe load capacitance of the SO1 output line 50 Preliminary Data Sheet
60. on Main System So Subsystem Clock i i ote Clock Operation CSS 0 Operation Interrupt STOP HALT Request Instruction nstruction ini Instruction Interrupt Request Request STOP Mode Main system clock oscillation stopped HALT Mode Note Clock supply to CPU is stopped oscillation HALT Mode Clock supply to CPU is stopped oscillation Note The power consumption can be reduced by stopping the main system clock When the CPU is operating on the subsystem clock setthe MCC bit 7 ofthe processor clock control register PCC to stopthe main system clock The STOP instruction cannot be used Caution When the main system clock is stopped and the system is operated by the subsystem clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program Remark CSS Bit 4 of processor clock control regisrer PCC 9 RESET FUNCTION There are the following two reset methods External reset input by RESET pin Internal reset by watchdog time runaway time detection Preliminary Data Sheet 33 780053 780054 780055 780056 780058 10 INSTRUCTION SET 1 8 bit instruction MOV ADD ADDC SUB SUBC AND MULU DIVUW INC DEC ROL RORC ROLC ROR4 ROL4 PUSH DBNZ HL Byte HL B HL C laddr16 addr1
61. on Dedicated input port pins P01 P05 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software P10 P17 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software P20 P27 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software P30 P37 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software P40 P47 Input output port pins Input output specifiable in 8 bit units When used as input port pins on chip pull up resistor can be used by software Test flag KRIF is set to 1 by falling edge detection P50 P57 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software LED direct drive capability P60 P63 N channel open drain input output port pins Input output specifiable bit wise On chip pull up resistor can be used by mask option LED direct drive capability P64 P67 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software Port 7 P70 P72 Input output port pins Input output specifiable bit
62. reference voltage input AVss A D converter D A converter ground potential Use at the same potential as Vsso RESET System reset input Main system clock oscillation crystal connection Subsystem clock oscillation crystal connection Port block positive power supply Port block ground potential Positive power supply except for port and analog blocks Ground potiential except for port and analog blocks Internally connected Connect to Vsso or Vss directly Preliminary Data Sheet 13 780053 780054 780055 780056 780058 3 3 PIN CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input output circuit type of each pin and recommended connection of unused pins are shown in Table 3 1 For the input output circuit configuration of each type see Figure 3 1 Pin Name 100 Table 3 1 Input Output Circuit of Each Pin 1 2 Input Output Circuit Type Input Recommended Connection when Not Used Connect to Vsso 1 1 101 PO2 INTP2 PO4 INTP4 POS INTP5 Input output Independently connect to Vsso through resistor 7 1 Input Connect to Vppo P10 ANI0 P17 ANI7 P20 SI1 P21 SO1 P22 SCK1 P23 STB TxD1 P24 BUSY RxD1 P25 SI0 SBO P26 SO0 SB1 P27 SCKO P30 TOO P31 TO1
63. software P130 P131 Port 13 ANO0 ANO1 2 bit input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software Preliminary Data Sheet 11 780053 780054 780055 780056 780058 3 2 OTHER PINS 1 2 Dual Pin Name Function Function Pin INTP0 External interrupt request input for which the effective edge rising edge 00 100 INTP1 falling edge or both rising edge and falling edge can be specified PO1 TIO1 INTP2 P02 INTP3 INTP4 P04 INTP5 P05 10 Serial interface serial data input P25 SB0 20 12 P70 RxD SO0 Serial interface serial data output P26 SB1 01 P21 SO2 P71 TxD SBO Serial interface serial data input output P25 SIO SB1 P26 SO0 SCK0 Serial interface serial clock input output P27 SCK1 P22 SCK2 P72 ASCK STB Output Serial interface automatic transmit receive strobe output P23 TxD1 BUSY Input Serial interface automatic transmit receive busy input P24 RxD1 RxD0 Input Asynchronous serial interface serial data input P70 SI2 RxD1 P24 BUSY TxDO Output Asynchronous serial interface serial data output P71 SO2 TxD1 P23 STB ASCK Input Asynchronous serial interface serial clock input P72 SCK2 TIOO Input External count clock input to the 16 bit timer TMO 01 Capture trigger signal input to the capture register 00
64. ss 0 V Parameter Test Conditions Resolution Overall error R 2 MQNote 1 R 4 MQNote 1 10 MQNote 1 Settling time C gopr ete 1 AVrert 4 5 to 5 5 V Output resistance Ro Note 2 Analog reference voltage AVREF1 AVerer1 current 1 Note 2 Resistance between AVrer1 and Rairer1 DACSO DACS1 55 2 Notes 1 R and C denote D A converter output load resistance and load capacitance respectively 2 Value for 1 D A converter channel Remark DACSO and DACS1 D A conversion value setting register 0 and 1 60 Preliminary Data Sheet uPD780053 780054 780055 780056 780058 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics TA 40 to 85 Parameter Test Conditions Data retention power supply voltage Data retention power 1 8 V supply current Subsystem clock stop and feed back resistor disconnected Release signal set time Oscillation stabiliation Release by RESET 27 wait time Release by interrupt Note Note Incombination with bits 0 to 2 OSTSO to OSTS2 of oscillation stabilization time select register OSTS selection of 2 fxx and 2 fxx to 2 7 fxx is possible Remark Main system clock frequency fx or fx 2 fx Main system clock oscillatior frequency Data Retention Timing STOP Mode Release by RESET Internal Reset Operation HALT Mode
65. t This is most applicable to control of stepping motor etc Control Circuit Baud Rate Generator fxx fxx 2 Figure 5 13 Real Time Output Port Block Diagram INTST Internal Bus Real Time Output Real Time Output Output Trigger Buffer Register Buffer Register High order 4 Bits Low order 4 Bits RTBH RTBL Output Latch 27 120 Preliminary Data Sheet Real Time Output Port Mode Register 27 780053 780054 780055 780056 780058 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6 1 INTERRUPT FUNCTIONS There are interrupt functions 21 sources of three different kinds as shown below Non maskable 1 Maskable 19 Software i 4 Table 6 1 Interrupt Source List 1 2 Note 1 Basic Default Internal Vector Table Configuration Interrupt Type Priority Trigger External Address TypeNote 2 Non maskable INTWDT Watchdog timer overflow Internal watchdog timer mode 1 selected Maskable INTWDT Watchdog timer overflow interval timer mode selected INTPO Pin input edge detection External INTP1 INTP2 4 5 INTCSIO End of serial interface channel 0 Internal transfer INTCSI1 End of serial interface channel 1 transfer INTSER Generation of serial interface channel 2 UART receive error IN
66. ubsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured in software Preliminary Data Sheet 37 780053 780054 780055 780056 780058 Subsystem Clock Oscillation Circuit Characteristics TA 40 to 85 Vpp 1 8 to 5 5 V Resonator Recommended Circuit Parameter Test Conditions Crystal JC 2 XTI Oscillator resonator frequency fxr Note 1 Oscillation Vpp 4 5 to 5 5 V stabilization time Note 2 External XT1 input clock frequency fxr Note 1 XT1 input uPD74HCUO4 high low level width txtH Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after Vpp reaches oscillator voltage MIN Cautions 1 When using the subsystem clock oscillator wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillator capacitor ground should be the same as Vss1 Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillator 2 The subsystem clock oscillation circuit is a circuit with a low
67. wise When used as input port pins on chip pull up resistor can be used by software Port 12 P120 P127 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software Port 13 P130 P131 Input output port pins Input output specifiable bit wise When used as input port pins on chip pull up resistor can be used by software Preliminary Data Sheet 19 780053 780054 780055 780056 780058 5 2 CLOCK GENERATOR Two types of generators a main system clock generator and a subsystem clock generator are avaibable The minimum instruction execution time can also be changed 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us main system clock at 5 0 MHz operation 122 us subsystem clock at 32 768 kHz operation Figure 5 1 Clock Generator Block Diagram XT1 P07 O Subsystem Clock Watch Timer Clock Output Function Oscillator Prescaler Clock to Peripheral Hardware Standby Control Circuit Wait Control Circuit CPU Clock fceu To INTPO Sampling Clock 5 3 TIMER EVENT COUNTER The following five channels of the timer event counter are available 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Table 5 2 Operations of Timer Event Counter Operation mode Interval timer
68. ycle modification function time When main system clock selected 0 4 5 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us at 5 0 MHz operation When subsystem clock selected 122 us at 32 768 kHz operation Instruction set 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test boolean operation BCD correction etc ports Total 68 CMOS input i 2 CMOS I O 62 N ch open drain I O 4 A D converter 8 bit resolution x 8 channels 2 7 to 5 5 V D A converter 8 bit resolution x 2 channels 2 7 to 5 5 V Serial interface 3 wire serial l O SBI 2 wire serial mode selectable 1 channel 3 wire serial mode on chip max 32 bytes automatic data transmit receive function 1 channel 3 wire serial l O UART mode on chip time division transfer function selectable 1 channel 1 channel 2 channels 1 channel 1 channel 16 bit timer event counter 8 bit timer event counter Watch timer Watchdog timer Timer output 3 14 bit PWM output x 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz at main system clock 5 0 MHz operation 32 768 kHz at subsystem clock 32 768 kHz operation Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz at main system clock 5 0 MHz operation Vectored Maskable Internal interrupt 13 external interrupt
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