2 structure of the pxi-c1553 module
Contents
1. zan CH GH B HAA Ef EES AIT CBL VHDCI 1553 4 Delivered with the PXI C 1553 4 If the customer application requires IRIG or other signals for a single or dual channel card normally shipped standard only with a quad channel card customers may order the quad channel cable from AIT s Price List For assistance contact your AIT Sales Engineer or call AIT at 1 402 763 9644 AIT will make any custom cable configurations and or length required PXI C1553 Hardware Manual 15 gestae TODAY S SOLUTIONS o Technologies for tomorrow s demands Table 3 2 2 Breakout Cable Pinout Pin _SignalName MIL bus twinax BNC connections CHA 1A XC CHA 1A XC CHA 1B XC CHA 1B XC CHA 2A XC CHA 2A XC CHA 2B XC CHA 2B XC CHA 3A XC CHA 3A XC CHA 3B XC CHA 3B XC CHA 4A XC CHA AA XC BNCs JB CHA 4B XC BI J93 J94 Jos J936 J97 Jos J939 9 10 _ J9 11 J912 J913 J9 14 J915 CHA_4B_XC 15 pin Standard VIO IN GND IRIG OUT IRIG IN GND DIO8 DIO7 DIO5 DIO4 DIO3 DIO2 DIO1 3 2 3 PXI C1553 Front Panel Connector J3 For applications not using the break out cables provided the PXI C1553 non EF front panel connector J3 is a 68 pin VHDCI connector that provides access to the transformer coupled and direct coupled MIL STD 1553 databus signals four redundant channels IRIG B2. Technologies Table 3 2 3 II Signal Descriptions Signal Desctpton Cid EE Output Sigra mn IRIG B Output iong Signal 3 2 4 PXI C1553 EF Front Panel Connector J3 For applications not using the break out cables provided the PXI C1553 EF Extended Functionality the pinout for the PXI C1553 EF front panel connector are different than those for the PXI C1553 due to the fact that the PXI C1553 EF supports multiple software programmable bus coupling modes on the same front panel pins Pinouts for the PXI C1553 EF are given below 18 PXI C1553 Hardware Manual TODAY S SOLUTIONS gta for tomorrow s demands Da NR Technologies Table 3 2 4 PXI C1553 EF Front Panel Connector J3 Pin Assignment ES E eno pics bios ea Gi OC OJO el el Gi OJO O el el el DIO2 DIO 7 1 1 1 1 1 3 3 3 4 4 4 4 4 4 4 4 4 4 ala o o dO cn Bar M 1 o Ooo o one fo G G el D D E G D C o CHA_3B M M M el N N N N zl s z 9 s z z g s z s z O 15 O 50 Sa 35 36 7 8 9 0 1 2 3 4 5 6 7 8 9 50 51 52 53 54 55 56 57 58 59 61 62 63 64 65 67 oer no N N N N N 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 0 1 2 3 4 7 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 3 PXI C1553 Hardware Manual 19 asma TODAY S SOLUTIONS a Technologies for tomorrow s dem
3. 3 3 v 1500 1600 1800 1600 1600 1600 ma ma jma jma jma ma 5v 400 400 400 550 700 1000 ma ma jma jma jma ma 100 100 100 ma KH Cem 24 PXI C1553 Hardware Manual TODAY S SOLUTIONS Qto for tomorrow s demands p AN Technologies NOTES Acronyms and Abbreviations ADC Analog to Digital Converter AFDX Avionics Full Duplex Databus ALBI Local Bus Interface ANSI American National Standards Institute ARINC Aeronautical Radio Incorporated ARM Advanced RISC Machine BC Bus Controller BIP Bus Interface Processor BIU Bus Interface Unit CM Chronological Bus Monitor cPCI Compact PCI CPLD Coupled CPU Central Processing Unit DAC Digital to Analog Converter DC DC Direct Current to Direct Current power conversion DIP Data Interface Processor DMA Direct Memory Access DRAM Dynamic Random Access Memory DSUB D Subminiature EDO Enhanced Data Output EEPROM Electrically Erasable and Programmable Read Only Memory EPROM Erasable Programmable Read Only Memory FIFO First in First out FLASH Page oriented electrical erasable and programmable memory FPGA Field Programmable Gate Array GND Ground TEEE Institute of Electric and Electronic Engineers IRIG Inter Range Instrumentations Group IRIG B Inter Range Instrumentations Group Time code Format Type B VO Input Output LCA Logic Cell Array XILINX Programmable Gate Array LED Light emitting Diode MIL STD Military Standard OWL Object Wrapper Librar
4. PXI C1553 EF Up to 4 Dual Redundant MIL STD 1553 channels with programmable coupling and output voltage are supported e PXI C1553 Up to 4 Dual Redundant MIL STD 1553 channels with both transformer and direct coupling modes are supported e Each channel independently capable of simultaneous Bus Controller Bus Monitor and Remote Terminal up to 31 simulation e Major Framing Minor Framing and Acyclic message transfer scheduling e Inter message Gap Scheduling e Full error injection capabilities in support of AS4112 RT Validation Testing e Automatic Bus Retries e Full Mode Code generation support e Simultaneously supports 31 RTs e Programmable Response Times 250 ns increments e Full Error Injection e Intelligent Mode Code responses e Passive receive only monitor mode operations e Chronologically time tags and stores all bus traffic e Error detection and notifications including detection of Gap and e Response time violations low bit word counts parity errors sync errors and status work exceptions e Complex Triggering and Filtering e Programmable Pre Post Trigger storage e Replay of stored bus monitor data e Replay can be synchronized across channels modules 46 bit IRIG time tag IRIG time microseconds since start of second Resolution 1 us Width 14 BCD digits 400 days Signal Type Single ended analog Signal Waveform Amplitude modulated sine wave or 22 PXI C1553 Hardware Manual TODAY S SOLUT
5. channel single function interfaces for PXI BC or 31 RTs or BM and 31 RT monitor only operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel simulate only interfaces for PXI BC or 31 RTs and 31 RT monitor only operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization PXI C1553 Hardware Manual 3 aen TODAY S SOLUTIONS DN Technologies for tomorrow s demands 1 2 How This Manual is Organized This manual is comprised of the following sections Section 1 INTRODUCTION contains an overview of this manual Section 2 STRUCTURE OF THE PXI C1553 describes the physical hardware interfaces on the PXI C1553 using a block diagram and a description of each main component Section 3 INSTALLATION describes the steps required to install the PXI C1553 device and to connect the device to other external interfaces including the MIL STD 1553 databus IRIG B and discretes Section 4 TECHNICAL DATA describes the technical specification of the PXI C1553 Section 5 NOTES contains a list of acronyms and abbreviations used in this manual 4 PXI C1553 Hardware Manual TODAY S SOLUTIONS apres for tomorrow s demands p SN Technologies 1 3 Applicable Documents The following documents shall be considered to be a part o
6. I C1553 128 MByte Local DDR2 RAM Data Buffers 128 MByte Local DDR2 RAM PXI C1553 Hardware Manual TODAY S SOLUTIONS apres for tomorrow s demands p SN Technologies The primary components of the PXI C1553 are e PCIto PCI Bridge This bridge allows multiple devices namely the PMC 1553 and PXI Trigger IO controller on the on card PCI bus This bus runs at 33 333 MHz whereas the CompactPCI backplane may run at 66 MHz or 33 MHz e MIL STD 1553 Core PowerPC FPGA The MIL STD 1553 Core and PowerPC is implemented in a Xilinx Virtex 4 The PowerPC operates at 250MHz and is capable of hosting time critical user application functions The MIL STD 1553 Core supports simultaneous Bus Controller Bus Monitor and Remote Terminal up to 31 functions on each of the available four bus interfaces Full error injection and error detection capabilities are provided e SDRAM Two 128MB banks of SDRAM provide storage for bus transmit amp receive buffers and for PowerPC program and data stores e MIL STD 1553 Transceivers and Coupling circuits The Transceivers and Coupling circuits provide both transformer and direct coupling access to all four dual redundant bus interfaces e IRIG B Encoder Decoder The IRIG B Decoder allows the PXI C1553 module to synchronize its time tagging clock source to an external IRIG B time source The IRIG B Encoder allows the PXI C1553 module to output an IRIG B time signal derived from the modules onboard t
7. IONS for tomorrow s demands IRIG Output Discretes Connectors Dimensions Weight Supply Voltages Modulation Ratio Input Amplitude Input Impedance Coupling Time Jitter Lock time Signal Type Signal Waveform Modulation Ratio Output Amplitude Output Impedance Technologies square wave 3 1 to 6 1 0 2Vpp to 3Vpp gt 3k Ohm AC Coupled 5nS typical module to module depending on input signal quality 1 to 5 seconds depending on input signal quality Single ended analog Amplitude modulated sine wave 3 1 1 5 volts 1 3 Ohmss typ designed for 50 Ohm load 10 Fully programmable as input or output discrete signals Inputs Outputs J1 XJ4 J4 Min Logic 1 2 5V Max Logic 0 0 8V Tolerant of up to 30V input Software configurable as open collector or emitter followers Maximum load 100mA Emitter Follower configuration capable of providing up to 5V signal without external VIO_IN supply or up to 30V signal with external VIO_IN supply 3U CompactPCI 100mm x 160mm lt 0 6 bbs 3 3V 5 5V 5 12V 5 12V 5 PXI C1553 Hardware Manual 23 gestae TODAY S SOLUTIONS ai for tomorrow s demands Technologies Temperature Operating 0 C to 70 C Storage 40 C to 85 C Humidity O to 95 non condensing 4 1 Power Consumption PXI C1553 1 2 4 EF Extended Function Channels 1 2 4 1 2 4
8. Input Output signals and the Discrete I O signals Pinouts for the PXI C1553 are given below 16 PXI C1553 Hardware Manual TODAY S SOLUTIONS gta for tomorrow s demands Da NR Technologies Table 3 2 3 I PXI C1553 Front Panel Connector J3 Pin Assignment VIO IN o al EC DO Be 39 DO ma 42 DO w O N DIO5 DIO4 a 7 1 EX DIO3 DO _ sch N oa O EN q DO pg 47 ala oa alje sle Een en ERR Co GND GND GND GND GND GND GND GND GND GND GND GND GND EN 20 ao Es CHA_4B_DC HA_4B_DC CHA 48 XC HA 48 XC CH CHA 4A D I HA_4A_DC CHA 4A XO HA 4A XC 54 ND q E CHA 3B DC HA_3B_DC CHA_3B_XC HA_3B_XC CHA_3A_DC HA_3A_DC CHA_3A_XC HA_3A XC q co Len Lal op LI CHA 28 DO oa 60 CHA ao HA 2B XC HA_2A_DC CHA 2A Xc IN 63 CHA_2A xc ao leal op TI HA_1B_DC IN ND GND GND ND O E 0 1 1 CHA 1B xC na 66 CHA_1B_XC CHA_1A_DC HA_1A_DC 4 CHAJAXC oa 68 CHA_1A_XC 6 7 8 9 0 2 3 4 5 6 7 8 9 0 2 3 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 PXI C1553 Hardware Manual 17 gestae TODAY S SOLUTIONS As for tomorrow s demands
9. PXI C1553 modules are capable of operations in both 3 3V PCI and PCI X systems The modules can be used to simulate monitor and inject protocol errors in MIL STD 1553A B systems and can provide up to 4 MIL STD 1553 Dual Redundant interfaces The Full Function variant of the module is capable of simultaneously supporting the operations of a Bus Controller BC Bus Monitor BM and up to 31 Remote Terminals RT The Single Function variant of the module is capable of supporting either BC operations or BM and Monitor only RT operations or up to 31 RT simulation operations The Simulator Only variant of the module is capable of simultaneously supporting BC operations up to 31 RT simulations and up to 31 RT monitor only operations Both Transformer and Direct MIL STD 1553 bus coupling modes are supported Additionally an extended function variant of the module PXI C1553 EF provides additional functions that support software programmable MIL STD 1553 bus coupling Transformer Direct Network or Isolated and software programmable output voltages The modules provide an onboard IRIG B Time Decoder Encoder in support of time synchronization with external equipment Each module may be configured to synchronize its PXI C1553 Hardware Manual 1 E TODAY S SOLUTIONS Technologies for tomorrow s demands internal clock to an input IRIG B time signal Additionally the module may also be configured as an IRIG B time source capable of provid
10. ands 3 2 5 PXIXJ4 Connector Table 3 2 5 XJ4 Connector 6 anp pxtrice op PxSTAR PXCLKIO GND 7 Loplrwme PATRico ND PxTRIGT ou 8 ano rsv cnD sv PxLBL6 PXLBRO GND 3 2 6 IRIG Connections The IRIG IN and IRIG OUT signals of the PCI C1553 and PCI C1553 EF are provided at both the front panel connector J4 The TRIG IN and IRIG OUT signals shall be connected depending on the time tagging method used as described below Single module with no external IRIG source No connections required Multiple modules with no common synchronization requirement No connections required e Single or multiple modules with external IRIG source Connect IRIG source to IRIG IN and GND of all modules e Multiple AIT modules with no external IRIG source Connect the IRIG_OUT signal and the GND of the module you have chosen as the time master to all IRIG IN and GND signals of all boards including the master s 3 2 7 Discrete Connections Ten Discrete I O signals are provided at the front panel connector J4 Each discrete can be operated as an output or an input The discrete outputs can be configured in software as open collector current sink emitter follower current source or a TTL like output In the case of the emitter follower configuration VIO_IN may be provided from an external source and used to externally set the high output voltage level If VIO_IN is not provided externally then the onboard 5V supply is
11. dundant 1553 channels For each channel both transformer coupled and direct coupled connections are provided The transformer coupled signals can be connected directly to a stub of a MIL STD 1553 coupler The direct coupled connections can be connected directly to the MIL STD 1553 bus Both the direct and transformer coupled signals are provided at the front panel connector J3 Additionally the transformer coupled signals are provided at the rear I O connector J4 The MIL STD 1553 bus interface of the PXI C1553 EF also supports up to four dual redundant 1553 channels For each channel one of four bus coupling modes can be independently programmed as described in the table below The MIL STD 1553 bus signals of the PXI C1553 EF modules are only provided at the front panel connector J3 Table 3 2 1 Bus Coupling Modes Direct Bus signal provided at front panel is direct coupled and can be connected directly to the 1553 bus Transformer Bus signal provided at the front panel is transformer coupled and can be connected directly to a stub of a bus coupler Network A properly terminated bus network is simulated on the PXI C1553 EF card and a bus stub is provided at the front panel connector the bus signal at the front panel can be connected directly to a transformer coupled MIL STD 1553 device Isolated No bus signal is provided at the front panel the front panel bus signal pins are disconnected from the internal circuitry of the PXI C1553 EF modu
12. e modified by the user Note We recommend that you use a wrist strap for any installations If there is no wrist wrap available then touch a metal plate on your system to ground yourself and discharge any static electricity during the installation work The following instructions describe how to install the PXI C1553 Follow the instructions carefully to avoid any damage on the device 3 1 1 Installation Instructions e To Install the PXI C1553 Module 1 Shut down your system and all peripheral devices Unplug the power cord from the wall outlet Inserting or removing modules with power applied may result in damage to the module devices 2 Remove any chassis panel covers necessary to gain access to a PXI CompactPCI peripheral slot 3 Place the PXI C1553 module into an open slot in your chassis 4 Screw the PXI C1553 board into the top rail with the captive screw at the top of the faceplate 5 Connect system with power source and turn on the power to your system 3 1 2 Board Connectors The PXI C1553 provides user access to the MIL STD 1553 Bus signals Discrete I O signals and IRIG B Input Output Signals at the front panel 68 pin VHDCI J4 connector 8 PXI C1553 Hardware Manual TODAY S SOLUTIONS apres for tomorrow s demands EN Technologies 3 2 Connections to the I O Signals 3 2 1 Connection to the MIL STD 1553 Interface The MIL STD 1553 bus interface of the PXI C1553 non EF supports up to four dual re
13. f this document to the extent that they are referenced herein In the event of conflict between the documents referenced and the contents of this document the contents of this document shall have precedence 1 3 1 Industry Documents e MIL STD 1553B Department of Defense Interface Standard for Digital Time Division Command Response Multiplex Data Bus Notice 1 4 January 1996 e MIL STD 1760 1 August 2003 Department of Defense Interface Standard for Aircraft Store Electrical Interconnection System PICMG 2 0 R3 0 CompactPCI Specification PXI Hardware Specification Revision 2 2 PXI Systems Alliance PXI Hardware Specification Revision 2 2 ECN 1 PXI Systems Alliance PCI Local Bus Specification R2 3 amp 3 0 PCI to PCI Bridge Architecture Specification Revision 1 1 1 3 2 Product Specific Documents e AIT MIL STD 1553 Getting Started Manual provides detailed instructions to assist first time users of AIT MIL S TD 1553 interface modules with software installation hardware setup and starting a sample project e AIT MIL STD 1553 Object Wrapper Library Reference Manual provides a detailed description of the high level object oriented programming interface between host application programs and the PXI C1553 PXI C1553 Hardware Manual 5 gens TODAY S SOLUTIONS emer for tomorrow s demands 6 2 STRUCTURE OF THE PXI C1553 MODULE The structure of the PXI C1553 module is shown in Figure 2 below Figure 2 Structure of the PX
14. ime tagging clock so that external equipment may be synchronized to the module This IRIG time may be reset by the PXI_STAR signal if configured through software to do so e Discrete Drivers and Buffers Ten discrete signals are provided each independently programmabke as an input or output In support of MIL STD 1760 applications outputs can be used to driver up to 30V signals with the help of an external power supply and inputs can tolerate up to 30V signals The variable output voltage MIL STD 1553 transceivers provide for the generation of variable voltage bus signals The output voltage is controlled by an software programmable control voltage via the digital potentiometers When direct bus coupling is used the output voltage can be varied between 140 mVp p and 7Vp p measured with 36 Ohm load When transformer bus coupling is used the output voltage can be varied between 410 mVp p and 19Vp p measured with 73 Ohm load The onboard coupling circuits allow software to control the bus coupling mode of each of the four channels independently and set them in either direct transformer network or isolated mode For definitions of these modes see Table 3 2 4 I PXI C1553 Hardware Manual 7 aen TODAY S SOLUTIONS o Technologies for tomorrow s demands 3 INSTALLATION 3 1 Installing the PXI C1553 Module The PXI C1553 features full PCI plug and play capability There are no jumpers or switches on the board which have to b
15. ing a reference time signal The PXI C1553 module provide 10 programmable as input or output discretes Each discrete is capable of up to 30 V operations with an external power supply 2 PXI C1553 Hardware Manual TODAY S SOLUTIONS for tomorrow s demands Table 1 1 PXI C1553 Variants Technologies PXI C1553 1 PXI C1553 2 PXI C1553 4 PXI C1553M 1 PXI C1553M 2 PXI C1553M 4 PXI C1553S 1 PXI C1553S 2 PXI C1553S 3 PXI C1553 EF 1 PXI C1553 EF 2 PXI C1553 EF A PXI C1553M EF 1 PXI C1553M EF 2 PXI C1553M EF 4 PXI C1553S E F 1 PX C1553S EF 2 FA PXI C1553S E e 1 2 and 4 channel full function interfaces for PXI Simultaneous BC 31 RTs and BM operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel single function interfaces for PXI BC or 31 RTs or BM and 31 RT monitor only operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel simulate only interfaces for PXI BC or 31 RTs and 31 RT monitor only operations IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4 channel extended full function interfaces for PXI Simultaneous BC 31 RTs and BM operations Programmable bus coupling output voltage IRIG B Input Output 10 programmable discretes PXI backplane triggers and timing synchronization 1 2 and 4
16. le The MIL STD 1553 specification clearly defines the process of coupling subsystems to the bus This connection called a stub has two coupling options direct coupled and transformer coupled In addition to these two methods of connecting to the bus a direct to device network coupling configuration is also an option All three methods are described in this section The Flight Director bus analyzer software allows the user to select isolated transformer direct or network coupling through the system setup controls Use of an AIT module without the Flight Director software is accomplished with library setup calls PXI C1553 Hardware Manual 9 E TODAY S SOLUTIONS Technologies for tomorrow s demands 3 2 1 1 Direct Coupling Direct coupling connects the subsystem terminal device directly to the bus and can only be used in connections under one foot in length Since a direct coupled stub provides only limited isolation in the event of a device subsystem or terminal short transformer coupling is normally the recommended method of connecting to the bus Figure 3 2 1 1 Direct Coupling Bus A Stub Length One Foot Max 10 PXI C1553 Hardware Manual TODAY S SOLUTIONS sim for tomorrow s demands A Technologies 3 2 1 2 Transformer Coupling Transformer coupling utilizes a bus coupler that contains an isolation transformer and isolation resistors Transformer coupling extends the stub length to 20 feet a
17. nd provides electrical isolation better impedance matching and higher noise rejection characteristics than direct coupling The electrical isolation prevents a terminal fault or stub impedance mismatch from affecting bus performance Figure 3 2 1 2 I Bus Coupler 2 Stub Bus Coupler Connecting to the bus using transformer coupling requires a coupler for each subsystem terminal device and proper termination on the bus Figure 3 2 1 2 II Terminal Device Connection Cables Aircraft orLab Cable Deng d 2 7 e a ada PXI C1553 Hardware Manual 11 genti TODAY S SOLUTIONS for tomorrow s demands Technologies Figure 3 2 1 2 III Transformer Coupling 78 Q Terminators Me S 12 PXI C1553 Hardware Manual TODAY S SOLUTIONS apres for tomorrow s demands AA Technologies 3 2 1 3 Direct to Device Network Coupling Direct to Device Network coupling is an option with AIT modules The AIT design includes onboard bus network circuitry that is software selectable This allows the user to connect directly to a single terminal device without the need for any bus coupling The network coupling mode selected by the user via software controls provides a terminated MI bus network simulation on the AIT module for direct connection between the AIT module software and the terminal under test Figure 3 2 1 3 Direct to Device Network Coupling PXI C1553 Hardware Manual 13 aen TODAY S SOLUTIONS As for tom
18. nformation Products Table 1 lists toxic or hazardous substances or elements contained in Avionics Interface Technologies AIT electronic information products EIPs including subassemblies that exceed limits specified in SJ T1 1363 2006 Table 1 Toxic or Hazardous Substances or Elements in Product Toxic or hazardous Substances or Elements Hexavale Lea nt Polybrominate Polybrominat Component d Mercur Cadmiu Chronium d Biphenyls ed Diphenyl Pb y Hg m Cd Ethers PBDE PXI 1553 4 Channel Carrier for PMC 1553 Hardware Standoff HEX 5mm x 10mm M2 5 Aluminum Clear lridite finish Hardware Screw Metric M2 5 x 5mm Hardware Faceplate Overlay Hardware Face Plate PXI 1553 PMC 1553 Channel Conduction Cooled Parts List Product Marking Explanations In accordance with the requirements specified in SJ T11364 2006 all AIT EIPs sold in the People s Republic of China are marked with a pollution control marking The following marking applies to AIT products PXI C1553 Hardware Manual 27 aen TODAY S SOLUTIONS DN Technologies for tomorrow s demands This marking indicates that some homogeneous substance within the EIP contains toxic or hazardous substances or elements above the requirements listed in SJ T1 1363 2006 These substances are identified in Table 1 The size or function of some products may prevent them from being directly marked These products still meet SJ T11364 2006
19. orrow s demands Technologies 3 2 2 PXI C1553 Breakout Cables The PXI C1553 and PXI C1553 EF modules are delivered with one of three cable assemblies which provide only transformer coupled outputs for the non EF and software selectable coupling for the EF e A single channel card is delivered with one break out cable Part Number CBL VHDCI 1553 1 It includes two Twinax BNC connectors for each of the MIL STD 1553 bus connections e A dual channel card is delivered with one break out cable Part Number CBL VHDCI 1553 2 It includes four Twinax BNC connectors for each of the MIL STD 1553 bus connections e A quad channel card is delivered with one break out cable Part Number CBL VHDCI 1553 4 It includes eight Twinax BNC connectors for each of the MIL STD 1553 bus connections and one 15 pin standard DSUB breakout connector to provide access to the IRIG Digital I O DIO and the Voltage I O VIO control signal Figure 3 2 2 PXI C1553 Cable Assemblies 15 00 AIT CBL VHDCI 1553 1 Delivered with the PXI C 1553 1 14 PXI C1553 Hardware Manual TODAY S SOLUTIONS ents for tomorrow s demands Technologies AIT CBL VHDCI 1553 2 Delivered with the PXI C 1553 2 E 15 00 12 00 j P1 J D CHATA H q
20. requirements and their marking information is covered by this document Environmentally Friendly Use Period The number in the marking shown as 40 in the illustration above refers to the EIP s environmentally friendly use period EFUP The EFUP is the number of years from the date of manufacture that toxic or hazardous substances or elements contained in EIPs will not leak or mutate under the normal operating conditions described in the EIP user documentation resulting in any environmental pollution bodily injury or damage to assets Note Except as expressly stated herein and as required under mandatory provisions of regulations of the People s Republic of China Avionics Interface Technologies makes no representation or warranty of any kind expressed or implied with respect to the EFUP and expressly disclaims any representations or warranties expressed or implied with respect to the EFUP Original Equipment Manufactured OEM EIPs SJ T11364 2006 specifies that OEM EIPs shipped by AIT should include hazardous substance information and EFUP markings Table 1 applies to products that do not supply OEM product information Manufacture Date Contact your local sales representative to obtain the manufacture date of your product Waste Electrical and Electronic Equipment WEEE EU Customers At the end of the product life cycle all products must be sent to a WEEE recycling center For more information about WEEE recycling cen
21. ssassatassisssisosesasiasssitoedasadi sis itaiadaira saia 1 To General rasgo ss eee nee ee 1 1 2 How This Manual is Organized sons agrado adsl pasa idasa ii sas 4 1 3 Applicable DOC UNISTS cs ches sentence eebe 5 1 3 1 Industry Documents sccssseciccosscnsdousaavsieasacdedassedesseebaanjncdsoatsaussaabaddereduartesanaaveradaees 5 1 3 2 Product Specific Documents s seseesseseneeeseestrerrtrtrstrsttrtnntttetnttnrtnnetnnnnn ensenen 5 Section 2 STRUCTURE OF THE PXI C1553 MODULE en 6 Section 3 INSTALLATION eneen 8 3 1 Installing the PX C1553 EEN 8 3 1 1 Installation Instructions soacssecnsinsccesvaesnsssnesduvnsusssdiessansduesenuas Udeadusiddasanentla atdusduecnuaarees 8 3 12 e Keen ere 8 3 2 Connections to the VO Signals ssa ss Sad DS sisal add 9 3 2 1 Connection to the MIL STD 1553 Interface An 9 321 Direct OU PIO DEE 10 3 2 1 2 Transformer Die le Pon REAR PR RR ne 11 3 2 1 3 Direct to Device Network Couplmg 13 3 22 PREG OSS Ee e uge 14 3 2 0 PX C 1553 Front Panel Connector J3 sa sas ciissoiasiaesmsasanirssaasstnsataisstnisa pra a 16 3 2 4 PXI C1553 EF Front Panel Connector J3 18 e IP IA CONNOR EE 20 3 2 6 IRIG CONNGCIONS reene 20 3 2 7 Discrete Connections ere egene eege Eege EE de r 20 Section 4 TECHNICAL DATA rear 22 4 1 PONErConSumplion EE 24 PXI C1553 Hardware Manual Il age TODAY S SOLUTIONS o for tomorrow s demands Section 5 NOTES aisisiiaassaasssismasisassssise
22. ssia dass soa fadicica aaa da sda pitadas ain 25 5 1 Acronyms and ALOT E 25 Section 6 APPENDIX Ae e erererreerrreerurersrueneusunsununnnunnnonunnnonuunnonnuneonnunenunnennnnnnnnnnnnnnn nn 27 Ill PXI C1553 Hardware Manual 1 1 TODAY S SOLUTIONS apres for tomorrow s demands p SN Technologies INTRODUCTION General DOCUMENT HISTORY Verson Date Author Description V01 00 Rev A October 2010 Andy Kragick Melissa Created document Amarawardana V01 00 Rev B December Melissa Format revisions 2010 Amarawardana V01 00 Rev C March 2011 Melissa Updated connector cable specifications Amarawardana Connecting the AIT Module to the Bus V01 00 Rev D September Drew Dingman Bill Updated connector cable specifications 2011 Fleissner V01 00 Rev E March 2012 Troy Troshynski Updated J9 connector pinout V01 00 Rev F January 2013 Drake Dingeman Updated power consumption and Melissa structural specifications Amarawardana This document comprises the Hardware User s Manual for the PXI C1553 hardware module which is a member of AIT s family of advanced MIL STD 1553 test and simulation modules This document covers the hardware installation the board comnections a general description of the hardware architecture and specific electrical and physical technical data of the module For programming information refer to the appropriate reference documents listed in the Applicable Documents section of this manual The
23. ters National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste Electrical and Electronic Equipment visit ni com environment weee htm 28 PXI C1553 Hardware Manual
24. used External pull up or pull down resistors must be selected to ensure that the output load does not exceed 100mA An output voltage decrease will be seen as loads increase as described below 20 PXI C1553 Hardware Manual TODAY S SOLUTIONS gta for tomorrow s demands B T Technologies Table 3 2 8 Output Voltage Load toma 7OMA 100mA Do D output powered by onboard 5V VIO Load Il Logic 1 output powered by externally provided 30V at VIO IN Load 10mA Logic 100mA Logic 0 output powered by externally provided 30V at VIO IN oad ToutputVoltage any load up to 100mA The discrete input Logic 1 minimum voltage is 2 5V The input Logic 0 maximum voltage is 0 8V All discrete inputs are protected up to 30V Note An optional onboard pull up resistor to onboard 5V supply or the externally provided VIO_IN may be provided Please consult factory for details PXI C1553 Hardware Manual 21 aen TODAY S SOLUTIONS o Technologies for tomorrow s demands 4 TECHNICAL DATA PCI Interface Form Factor Memory MIL STD 1553 Channels MIL STD 1553 Bus Controller MIL STD 1553 Remote Terminals MIL STD 1553 Bus Monitor MIL STD 1553 Replay Time Tagging IRIG Input 32 bit 33 MHz PCI plus PXI Trigger Bus PXI System Clock and PXI Star Trigger 3U Hybrid Slot Compatible PXI Module 256 Mbyte DDR2 SDRAM 128MB for channel data 128MB for onboard processor e
25. www aviftech com ZS mcs In Bes ter a co GR Technologies PRI G1903 Hardware Manual Single Double or Quad Stream MIL STD 1553 Test and Simulation Module for cPCI PXI February 2013 V01 00 Rev F He Avionics Interface Technologies TODAY S SOLUTIONS 3703 N 200th Street FOR TOMORROW S DEMANDS Omaha NEj68042 1 402 763 9644 Technologies PHI C1553 Hardware Manual Single Double or Quad Stream MIL STD 1553 Test and Simulation Module for cPCI PXI V01 00 Rev F February 2013 AIT HEADQUARTERS DESIGN amp PRODUCTION CENTER 3703 N 200th Street 2689 Commons Blvd Omaha NE 68022 Suite 201 Tel 1 402 763 9644 Beavercreek OH 45431 Fax 1 402 763 9645 Tel 1 937 427 1280 Fax 1 937 427 1281 ext 202 WESTERN TERRITORY OFFICE 9221 E Baseline Road EASTERN TERRITORY OFFICE Suite A 109 432 34 Country Road Mesa AZ 85209 East Hampstead NH 03826 Tel 1 480 354 0142 Tel 1 603 378 0957 Find your local Sales Representative at www aviftech com sales sales aviftech com Notice The information that is provided in this document is believed to be accurate No responsibility is assumed by AIT for its use No license or rights are granted by implication in connection therewith Specifications are subject to change without notice AIT 2012 TODAY S SOLUTIONS apres for tomorrow s demands EN Technologies Table of Contents Section 1 INT RODUG TIO MN ssssasessssssssssss
26. y PC Personal Computer PCI Peripheral Component Interconnect PCIe Peripheral Component Interconnect Express PMC PCI Mezzanine Card PROM Programmable Read Only Memory PXI C1553 Hardware Manual 25 Technologies PSC PXI PXle RISC RS 232 RT RTPTP SDK SIMM SRAM SSRAM TCP UART USB VME VME64 XMC TODAY S SOLUTIONS for tomorrow s demands PCI and System Controller PCI Extensions for Instrumentation PCI Extensions for Instrumentation Express Random Access Memory Reduced Instruction Set Computer Read Modify Write Recommended Standard No 232 US Norm Remote Terminal Remote Terminal Production Test Plan Received Data ATT s Software Development Kit Single Inline Memory Module Static Random Access Memory Synchronous Static Random Access Memory To be determined Time Code Processor Transistor Transistor Logic Transmitted Data Universal Asynchronous Receiver and Transmitter Universal Serial Bus VERS Amodule Eurocard VME 64bit extension VME Extensions for Instrumentation PCI Express Mezzanine Card 26 PXI C1553 Hardware Manual TODAY S SOLUTIONS apres for tomorrow s demands p SN Technologies APPENDIX A Avionics Interface Technologies Product Information for People s Republic of China This document provides product information as required by the People s Republic of China Electronic Industry Standard SJ T1 1364 2006 Marking for Control of Pollution Caused by Electronic I
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