SMT370 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. DATA D 0 31 FIFO D 0 7 bom 16x32x2 STRB RDY REQ Control Logic and Status N Figure 3 ComPort interface data path Sundance High speed Bus SHB Both SHB buses are identical and 60 bit wide SHBs are parallel communication links for synchronous transmissions Each SHB can be divided into two independent 8 bit buses Each 8 bit bus includes a clock and Port x Version 2 0 Page 15 of 46 SMT370v2 v3 User Manual three control signals write enable request and acknowledge An SHB bus can also be divided into two 16 bit buses and one 8 bit bus Here is the architecture of the SHB interface implemented into the FPGA DATA 00 31 00 15 coo m _ SHB Control Logic and Status kl Figure 4 SHB interface structure Communication links implemented on the SMT370 The SMT370 provides 2 ComPort links They are given the numbers 0 and 3 The default firmware provided with the board implements ComPort3 as a control register communication port which means that every control register word has to be sent to ComPort3 on the SMT 370 to be received The board also connects two full SHB connectors 60 bits to the FPGA The FPGA implements two 16 bit or one 32 bit unidirectional interfaces per SHB connector output only for SHBA used to send out samples coming from both AD2. Bit 22 LSB MSB first O MSB or 1 ZLSB be set to 0 when using default firmware Bit 11 Enable zero stuffing 0 zero stuffing on interpolation filter or 1 Enables zero stuffing Bit 10 Mix Mode 0 Complex and 1 Real Bit 9 Q 2e Bit 8 DATACLK PLL select 0 PLLLOGCK or 1 DATACLK O 2zSigned Input Data Two s complement or 1 Unsigned Binary Bit 7 Bit 6 0 Two Port Mode or 1 One Port Mode Bit 0 Q first 0 first or 1 Q first Version 2 0 Page 31 of 46 SMT370v2 v3 User Manual Register 0x1 DAC register report to AD9777 datasheet for more details mm n mm 0 gt mu Bit 17 PLL Divide Prescaler Ratio Bit 16 PLL Divide Prescaler Ratio Bit 15 O ZPLL Off or 1 PLL Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Charge Pump Control or 1 Programmable Not Used PLL Charge Pump Control PLL Charge Pump Control PLL Charge Pump Control IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment Note the Bit15 should be set to 0 when there is no interpolation and to 1 otherwise Version 2 0 Page 32 of 46 SMT370v2 v3 User Manual Register 0x2 DAC register report
3. LOC 9 V9 3 TREE E E NET ADCB DATA lt 5 gt LOC AB10 CONFIG PART XC2V1000 FG456 6 NET ADCB DATA lt 6 gt LOC AA10 NET ADCB DATA lt 7 gt LOC Ull Start of Constraints extracted by E ai Floorplanner from the Design NET FREQ MASTER RESET LOC C16 NE AR DA LENE wf NET FREQ CLK SEL ADCs lt 0 gt LOC D21 s DUE a a NET FREQ CLK SEL ADCs lt 1 gt LOC F18 Peer ae NET FREQ CLK SEL DAC 0 LOC E16 NET FREQ CLK SEL DAC lt 1 gt LOC E17 FREQ CLK SEL lt 0 gt LOC D21 NET FREQ LOAD ADCs LOC B18 ke aa ii M NET FREQ LOAD DAC LOC DIT NET FREQ 5 CLOCK ADCs LOC A19 NET ADCB RDY GCLK LOC yi2 NET FREQ S CLOCK DAC LOC A17 Version 2 0 Page 23 of 46 SMT370v2 v3 User Manual NET ADC TRIG LOC T21 NET DQa lt 1 gt LOC NET DU LOG t3 NET ZBT DQa lt 0 gt Bar NET ADGA RDY GOLK NLI NET ZBT CS2 LOC B13 NET ZBT nOE LOC DIS NET ZBT CLK LOC B11 NET ZBT nLBO LOC B12 ZBT ADV LOC CIS NET ABT 16352 LOC 5 NET ZBT ADDR lt 19 gt LOC C4 NET IOG C12 NET ADDR lt 18 gt LOC C5 ABT nCKE NET UABT ADDR lt 17 gt LOC E6 NET ZBT nBWd LOC A13 NET
4. Figure 7 ADC input stage DC coupled Version 2 0 Page 18 of 46 SMT370v2 v3 User Manual The following graphs gives the average FFT of sixteen 16K FFTs processed after capturing data from Channel B The on board sampling frequency set to 100 MHz A 20MHz sine signal is fed to the board The test has been performed without any input filter which explains the second peak due to harmonics at all and with a 35dBc harmonic performance signal generator 10 x EET PLOT CHANNEL B AMPLITUDE dB LU 1 2 3 4 5 ANALOGUE INPUT FREQUENCY MHz T 107 Figure 8 FFT ADC Channel On board clock Similar results are obtained when using an external clock It is recommended to use a low jitter clock and a filter on the ADC inputs They indeed have a large input bandwidth and therefore allow a high level of harmonics in Version 2 0 Page 19 of 46 SMT370v2 v3 User Manual DAC Performance Sege 0 DC coupled input Requires an External clock signal centered around OV Minimum voltage 0 2 Volt peak to peak minimum Maximum voltage 3 3 Volts Minimum voltage 3 3 Volts Frequency range 20 160 MHz low jitter External Trigger Frequency Range 30 160 MHz LVTTL 3 3 Volts format connected to 3 3V FPGA mr Figure 9 DAC Performance Signal format Version 2 0 Page 20 of 46 SMT370v2 v3 User Manual Ul D 1 5 LI a J 4 i 90 d r m LI
5. LOC E7 de NET PXI TRIG2 LOC C22 3 NET 2 _ lt 0 gt LOC VEE 3 NET PXI TRIG3 LOC ZEN xy NET DQb lt 7 gt LOC 5 NET PXI TRIG4 LOC D18 NET ZBT DOb 6 LOC B4 NET SHBA CLKO LOC E12 3 NET ZBT DQb lt 5 gt LOC A5 2 NET SHBA CLK1 LOC D12 gy NET DQb lt 4 gt LOC B 7 NET SHBB CLKO LOC F12 2 NET ABT DQb lt 3 gt LOC AG 2 NET SHBB CLK1 LOC F13 o NET ZBT DQb lt 2 gt LOC B6 3 NET TTLs lt 3 gt LOC A15 NET D b lt 1 gt C6 NET TTLs lt 2 gt LOC D15 NET ZBT DQb lt 0 gt LOC D6 7 NET TTLs lt 1 gt LOC C15 3 NET ZBT DQa lt 7 gt LOC AG 4 NET TTLs lt 0 gt LOC E15 5 NET ZBT DQ lt 6 gt LOC NET nRESET LOC V12 NET ABT DQa lt 5 gt LOC F9 2 NET LEDs lt 3 gt LOC F14 NET ZBT DQa lt 4 gt LOC E9 3 NET LEDs lt 2 gt LOC BIG NET ABT DQa lt 3 gt LOC NET LEDs lt 1 gt LOC A16 NET ABT DQa lt 2 gt LOC D9 NET LEDs lt 0 gt LOC D16 Version 2 0 Page 24 of 46 SMT370v2 v3 User Manual NET CONF INIT LOC AA19 2 NET DAC 1 lt 14 gt LOC Y21 4 NET CONF DIN LOC V18 4 NET DAC P1B lt 15 gt LOC Y22 NET CLOCK LOC D11 NET DAC 2 lt 0 gt LOC W13 NET CP3 LOC V21 NET DAC 2 lt 1 gt LOC Y13 NET CP3 DATA lt 0 gt LOC U18 5 NET DA
6. Clock multiplexers which take there default state external clocks routed to FPGA DAC and ADCs The interface implemented in the FPGA including ComPort interface It is note recommended to proceed to an FPGA global reset while communications are happening It might stick the other end into an unknown state Version 2 0 Page 43 of 46 SMT370v2 v3 User Manual Register OXE DAC Register Read back Bit Bit 27 0 Not Used SMT370v2 By sending this control word the FPGA reads back the AD9777 DAC internal registers and send them of the 370 There are 14 ComPort words in total They all have the following format OXAD9777xx The last byte 8 Less Significant Bits gives the value of a DAC internal register The 370 starts by sending out register at address 0x0 and carries on up to register Example Let s consider that the following registers have been loaded into the DAC RegisterO 0x00010203 Register1 0x01111213 Register2 0x02212223 Register3 0x03313233 Register4 0x044142xx By sending the word 0 0000000 to an SMT370v2 the host gets back in return the following values OXAD977701 977702 OxXAD977703 0OxAD977711 977712 OxAD977713 0xAD977721 OXAD977722 OxAD977723 OXAD9777317 0xAD9771 32 OXAD977733 0xAD977741 OxAD977742 This function gives the user a way of verifying that the DAC has been loaded with the correct registers SMT370v3 By sending this contr
7. TONMANCE EE 19 Figure 10 DAC output s age e orte kwen don ea a out ann seanser a kika 20 Figure 11 FFT GO 20 PIOUS mis Pi Ne 21 Version 2 0 Page 5 of 46 SMT 370v2 v3 User Manual Figure 13 0 E 217 FE TA COCK ROUMO EE 36 Figure 155 SHBB 0148 e EE 41 Contacting Sundance You can contact Sundance for additional information by sending email to supportQsundance com Notes SMT370 denotes in this document SMT370v2 or SMT370v3 The board in available in two options AC or DC coupled inputs ADC It is to be specified when placing an ordering SHB stands for Sundance High speed Bus ComPort denotes an 8 bit communication port following the Tl C4x standards Precautions In order to guarantee that the SMT370 functions correctly and to protect the module from damage the following precautions should be taken The SMT370 is a static sensitive product and should be handled accordingly Always place the module in a static protective bag during storage and transition When operated in a closed or warm environment make sure that the heat generated by the system is extracted e g by the use of a fan extractor or an air blower Version 2 0 Page 6 of 46 SMT 370v2 v3 User Manual Outline description The SMT7370 is a dual high speed ADC DAC module offering the following features Two 14 bit ADCs AD6645 105 sampling at up to 105MHZ Dual 16 bit TX
8. 1Meg It is connected to the FPGA which controls read and write operations The default FPGA bit stream implements a pattern generator which consists in storing a pattern into the memory reading it back continuously and sending data out to the DAG This generator is controlled via bits in the control registers It can be loaded started and stopped by setting bits For more details see further in the documentation the part dealing with control registers This pattern generator feature is also called Arbitrary Waveform Generator AWG Please note that to change of waveform the memory has to be reloaded and the pattern generator to be re started This is due to the default firmware starting reading data from address 0 i e the start address is not a parameter unlike the size is Version 2 0 Page 11 of 46 SMT370v2 v3 User Manual ADCS and DAC The SMT370 is populated with two AD6645s 2 channels and one AD9777 dual channel For more details about these converters inner characteristics please refer to the manufacturer Analog Devices datasheets Data and control lines of the converters are all connected to the FPGA Clock management The SMT370 has two identical on board low jitter clock synthesizers ICS8430 one for the ADCs and one for the DAC Both have a Serial Port Interface The FPGA is responsible for setting them to the correct values loaded into a control register A wide range of frequencies can be set this way The
9. NET SHBA lt 57 gt LOC U4 NET SHBA lt 13 gt LOC KS NET SHBA lt 56 gt LOC ET NET SHBA lt 12 gt LOC 25 Version 2 0 Page 26 of 46 SMT370v2 v3 User Manual NET SHBA lt 11 gt LOC JI NET SHBA lt 5 gt LOC H3 NET 5 lt 10 gt LOC J2 NET SHBA lt 4 gt LOC H4 NET SHBA lt 9 gt LOC J3 NET SHBA lt 3 gt LOC 06 NET SHBA lt 8 gt LOC J4 NET SHBA lt 2 gt H5 NET SHBA 7 LOC H1 NET SHBA lt 1 gt LOC GL NET SHBA lt 6 gt LOC H2 NET SHBA lt O gt LOC G2 At power up and on reset At power up the FPGA is not configured and is waiting for a bit stream to be loaded By fitting Jumper J8 Figure 13 Connector Location it will allow the bit stream stored into the PROM to be loaded into the FPGA at power up and after every TIM reset If J8 is not fitted nothing happens This condition is useful when needing to configure the FPGA JTAG Version 2 0 Page 27 of 46 SMT370v2 v3 User Manual Connector position JE EIER 3 3Vl TTLH i8 not TTLZ configured J14 DAC Clk J4 SHBG J13 ja Ch A en 2 2 mE son Zo vo oe eege ee ee e e e li e A L5 2442482290995 9 A A EE SS PIB e 8 HH J2 JTAG Tdi Tek Tdo Tms n d 3 3 QV Fan Connector J8
10. can be done automatically when jumper J8 Figure 13 Connector Location is fitted If it is not fitted no configuration is loaded into the FPGA and allows therefore the user to program the FPGA via JTAG with no possible conflict Ten control registers are implemented into this FPGA to set up converters their data format clock synthesizers ComPort SHB and memory transfers Some more details are given in the next parts of this document Registers can be individually programmed They can also be read back but all at the same time The FPGA is serially programmed using the dedicated pins The PROM is originally programmed with a default bit stream which implements all features mentioned in this document Version 2 0 Page 10 of 46 SMT370v2 v3 User Manual Ressource occupied The default firmware as it comes with the board uses FPGA resources such as Ram Blocks Flip flop Slices l O pads The following table gathers all of them Number Out of Percentage used of utilisation External IOBs Number of 40 2290 RAMB16s SLICEs Number of 16 37 BUFGMUXs Number of 25 DCMs Number of 1 External DIFFMs Number of 1 External DIFFSs Figure 2 FPGA utilisation Most of the resources are not used by the default firmware which allows the user to implement some extra processing such as for example digital filters to add some processing gain to the chain Memory The SMT370 is populated with 32Mbits of ZBTRAM 32 bits x
11. l o Figure 10 DAC output stage The following capture shows a 5MHz signal generated by the DAC under an on board sampling clock of 160MHz Note that no output filter was used during the capture Herr M2 00Uus Chi l 196mv 20 Feb 2003 0 000 18 51 55 Figure 11 FFT DAG Channel Version 2 0 Page 21 of 46 SMT370v2 v3 User Manual SHB pinout Pin Signal Signa Signal CON oe ab oe al o e www el o v af mue a om ag ab me SH 2 wwe DU pa sp c 4 Sam er ws 4 penam w D al Gees or af o maen ai Da wem ab o al oe a2 nm eil om o om _ ab ow a pe on sf bows a om af owe a ov ws sl wae e pe fae s maen me al oo pe oe Figure 12 SHB Pinout This standard is implemented using SAMTEC QSTRIP 0 50mm Hi speed connectors To improve electrical performances a ground plane is embedded in each QSTRIP connector For long distances micro coax ribbon cable is used to connect 2 QSTRIP connectors An SHB interface can be 8 16 or 32 bit wide Version 2 0 Page 22 of 46 SMT370v2 v3 User Manual The default FPGA firmware implements 2 16 bit interfaces FPGA Pinout de ak ak tH E ak ak NET FREQ S DATA ADCs LOC B19 f
12. possible to output a 16 bit counter on each SHB half for system testing purpose It then becomes easier to detect any missing data ADCA is mapped onto the lowest part of SHBA and ADCB onto the highest As the 5 370 is populated with two ADCs two data stream are theoretically available on SHBA Each of them can be synchronised to either an external sampling clock or an on board clock In the FPGA each data stream goes through a Decimator which value 0 to 31 can be set via control register Both decimators are independent If both decimators are set with the same values and if the sampling clocks for Channel A and Channel B are the same i e both ADCs are using either the external or the on board clock both data streams are synchronised with each Version 2 0 Page 12 of 46 SMT370v2 v3 User Manual other and therefore the two 16 bit data streams can be considered as a single 32 bit data stream It is possible to control start stop the data flow by the way of an external trigger for which the active level high or low can be set in a control register It is recommended to have external trigger signal synchronised to the sampling clock This external trigger also goes thought 7 latch stages SHBB DAC Data received on SHBB are samples routed to the DAC Data from both SHBB channels go through a first row of latched then stored into a FIFO read out and finally go through two rows of latches It takes at least 4 DAC sampling cloc
13. synthesizer M Bit1 ADCs Bit 12 Clock synthesizer M BitO ADCs Bit 11 Clock synthesizer N divider Bit2 DAC Bit 10 Clock synthesizer N divider Bit1 DAC Bit 9 Clock synthesizer N divider BitO DAC Bit 8 Clock synthesizer M Bit8 DAC Bit 7 Clock synthesizer M Bit7 DAC Bit 6 Clock synthesizer M Bit6 DAC Bit 5 Clock synthesizer M Bit5 DAC Bit 4 Clock synthesizer M Bit4 DAC Bit 3 Clock synthesizer M Bit3 DAC Bit 2 Clock synthesizer M Bit2 DAC Bit 1 Clock synthesizer M Bit1 DAC Bit 0 Clock synthesizer M DAC Version 2 0 Page 36 of 46 SMT370v2 v3 User Manual Fsynthesized M N MHz With 500 lt lt 250 binary encoding can take one of the following values 1 000 1 5 001 2 010 011 4 100 6 101 8 110 or 12 41117 See ICS8430 01 datasheet for more information performance jitter etc The following diagram shows how clock signals can be routed on the PCB AC or DC AC or DC coupling coupling 2xAD6645 ADCs 14 bit 105MSPS 52 LQFP pins 28 bit data ctl amp amp Clock feedbacks 1 FPGA C Clock aye sizer ADCs Virtex ll FG456 NES o uidi XC2V1 000 6 Bit24 rae a 324 I O Pins MEE Q 1 PV Core amp Clock feedback 1H I 3 44 UO pins 16 bit data ctl
14. to 3 3 and Ground to avoid damaging the FPGA l Os This is achieved by using single diodes BAV99 These diodes can support as maximum 200mA of forward current and 70 Volts of reverse voltage It is to the customer to consider this when building a system using an SMT 370 LEDs oeven LEDs Figure 13 Connector Location are available on the board Four denoted 1 2 3 and 4 on the PCB top left of them green are driven by the FPGA In the default bitstream they indicate what follows Version 2 0 Page 13 of 46 SMT370v2 v3 User Manual 1 Flashing under the ADC sampling clock it can be useful to check that the LED is flashing when using an external sampling clock signal 2 Flashing under the DAC sampling clock 3 gt Direct To DAC mode selected when ON 4 gt ON when a data is being read out of the DAC FIFO Two green LEDS located at the bottom left and right of the board indicate the status of the power supplies Both should be on when the board is under power A red LED located on the top right of the board indicated when the FPGA is not programme In normal operation i e J8 fitted Figure 13 Connector Location it flashes once at power up and after resetting the module Just after a reset TIM or FPGA Global Reset the LEDs display the Firmware version This is available from the Version 4 of the Firmware For earlier version the LEDs are connected to un driven signals LED1 ON LED2 OFF LED3 ON and LED
15. to AD9777 datasheet for more details ma mm n mum Bit 7 IDAG Direction O lofrset ON loura or 1 lorrset ON loute Version 2 0 Page 33 of 46 SMT370v2 v3 User Manual Register 0x3 DAC register report to AD9777 datasheet for more details omm 7 p n mm 00075 Version 2 0 Page 34 of 46 SMT370v2 v3 User Manual Register 0x4 DAC register report to AD9777 datasheet for more details QDAC lorrset Direction O lorrsert ON loura or 1 lorrset ON loute Not Used Version 2 0 Page 35 of 46 SMT370v2 v3 User Manual Register 0x5 Clock management mm 70 T mus n Bit 27 Clock Selection ADCA 0 Internal 1 External Bit 26 Clock Selection ADCB ADCB 0 Internal 1 External Bit 25 Clock Selection DAC 0 Internal 1 External Bit 24 Clock Selection DAC FPGA must match with Bit 25 0 Internal 1 External Bit 23 Clock synthesizer N divider Bit2 ADCs Bit 22 Clock synthesizer N divider Bit ADCs Bit 21 Clock synthesizer divider ADCs Bit 20 Clock synthesizer M Bit8 ADCs Bit 19 Clock synthesizer M Bit7 ADCs Bit 18 Clock synthesizer M Bit6 ADCs Bit 17 Clock synthesizer M Bit5 ADCs Bit 16 Clock synthesizer M Bit4 ADCs Bit 15 Clock synthesizer M Bit3 ADCs Bit 14 Clock synthesizer M Bit2 ADCs Bit 13 Clock
16. 04 20 O pini e 14 bit 105MSPS 6 Clock feedback 52 pin LQFP gu gen TTT TT TTT Xilinx FRGA eader Clock 2xClock Virtex ll FG456 XC2V1000 6 parameters synthesizers Clock 4 1 Filter 2 Sundance High speed 120 pins 324 I O Pins Clock selection P Multiplexer Filter Bus connector 2 x 60 bits 1 5V Core 3 3V C 1 AD9777 DA 44 16 bit data ctl One bank of 1Mx32 bits of 68 I O pins 32 bit data 16 bit Q 400MSPS NISRAM 166 MHz ge Clock feedback 80 pin TQFP RF RF a 0 transformer transformer a EE a Q e 55 Option to the board Main parts of the board are described in the next part of this document Version 2 0 Page 8 of 46 SMT 370v2 v3 User Manual Architecture Description The module consists of a Xilinx Virtex ll FPGA two Analog Devices 14 bit monolithic sampling Analog to Digital converters AD6645 and one Analog Devices AD9777 Dual TXDAC Digital to Analog converter The AD6645 is a 14 bit monolithic sampling analog to digital converter The chip provides CMOS compatible digital outputs It is the Analog Devices fourth generation of wideband ADCs The AD6645 maintains outstanding AC performance up to input frequencies of 200 MHz which makes it suitable for multi carrier 3G applications The AD6645 is able to sample from 30 up to 105 MHz Nevertheless it is possible to reduce that rate by performing decimation on the data flow T
17. 22 NET CPO DATA lt 0 gt W5 x NET SHBB lt 58 gt LOC P17 NET CPO ACK LOC YI NET SHBB lt 57 gt LOC R18 NET DAC CLAN LOC AA12 NET SHBB lt 56 gt LOC R19 NET DAC LOC AB12 3 NET SHBB lt 55 gt LOC R20 NET DAC PLL LOCK LOC W21 NET SHBB lt 54 gt LOC R21 NET DAC P1B lt 0 gt V16 NET SHBB lt 53 gt LOC R22 NET DAC P1B lt 1 gt V15 NET SHBB lt 52 gt LOC P19 NET DAC 1 lt 2 gt LOC AA17 NET SHBB lt 51 gt LOC P20 NET DAC P1B lt 3 gt LOC ABIT NET SHBB lt 50 gt LOC P21 NET DAC 1 lt 4 gt LOC AAIS NET SHBB 495 LOC P22 NET DAC 1 lt 5 gt LOC AB18 gt NET SHBB lt 48 gt LOC P18 NET DAC 1 lt 6 gt LOC W17 NET SHBB lt 47 gt LOC N18 NET DAC P1B lt 7 gt LOC Y17 a NET SHBB lt 46 gt LOC N19 DAC lt 8 gt LOC WIS NET SHBB lt 45 gt LOC N20 NET DAC P1B lt 9 gt LOC Y18 NET SHBB lt 44 gt LOC N21 NET DAC P1B lt 10 gt LOC AB19 NET SHBB lt 43 gt LOC N22 NET DAC P1B lt 11 gt V17 2 NET SHBB lt 42 gt LOC N17 NET DAC P1B lt 12 gt LOC AA20 SHBB lt 41 gt LOC M17 NET DAC P1B lt 13 gt LOC AQ 7 NET SHBB lt 40 gt LOC MIS Version 2 0 Page 25 of 46 SMT370v2 v3 User Manual NET SHBB lt 39 gt LOC M19 NE
18. 4 OFF gt Version 2 5 of the firmware LED1 OFF LED2 ON LED3 ON and LED4 OFF gt Version 3 6 of the firmware TTL I Os Four TTL I Os J6 see Figure 13 Connector Location are connected directly to the FPGA They support LVTTL signals It is recommended to make sure the lines connected to these pins are LVTTL compatible in order not to damage the FPGA pads as lines are not clamped Sundance Standards Communication Ports ComPorts According to the Sundance module you can get up to six 8 bit data parallel inter processor links that folow Texas Instruments TMS320C4x Communication Port standard Additional information on the standard is available in the TMS320C4x Users Guide chapter 12 Communication ports and the Texas Instrument Module Specification The standard gives a TIM six links numbered from O to 5 Each link can be a transmitter or a receiver and will switch automatically between these states depending on the way you use it Writing to a receiver or reading from a transmitter will cause a hardware negotiation token exchange that will reverse the state of both ends of the link Following a processor reset the first three links 0 1 and 2 initialise as transmitters and the remainder 3 4 and 5 initialise as receivers When you wire TIMs together Version 2 0 Page 14 of 46 SMT370v2 v3 User Manual you must make sure that you only ever connect links initialising as transmitters to links initialising as rec
19. 41 OxAD977742 Please note that DAC internal registers are effectively read back and that clock synthesizer registers are not read back from the devices themselves but from the FPGA as they don t have that feature Version 2 0 Page 45 of 46 SMT370v2 v3 User Manual Register 0xF Serial Interfaces load Bit The and the clock synthesizers have Serial Port Interface By sending this control word the FPGA serialises Register 0 to 5 and send them to the DAC and both clock synthesizers The SPI in the DAC allows read back using control word OxE but not in the clock synthesizers Version 2 0 Page 46 of 46 SMT370v2 v3 User Manual SMT370 package The SMT370 comes with an install package SMT6600 that contain examples and C header file When ordered with either an SMT365 or SMT365E or SMT374 it comes with a Pegasus application and a 3L application SMT370 Dimensions SMT370 Metal Can In red extra height when mated on a 310Q In green height of the module itself
20. 7 datasheet for more details 31 Register 0x2 DAC register report to AD9777 datasheet for more details 32 Register Ox3 DAC register report to AD9777 datasheet for more details 33 Register Ox4 DAC register report to AD9777 datasheet for more details 34 Register 0x5 Clock management 35 Register 0 6 Channel selection Triggers Decimator for ADCs 37 Register 0 7 DAC control Pattern generator 39 Register OxD FPGA Global Reset 42 Register SE DAC Register Read back 43 Register OxF Serial Interfaces load 45 SY ETE oe a E 46 SE SOUS EE 46 FET BIOCK NN 7 Wlslfle CM 10 Figure ComPort interface data path 14 Figure 4 SHB interface structure 15 Figure S ADC PNAN 16 Figure 6 ADC input stage AC coupled 17 Figure 7 ADC input stage DC coupled 17 Figure 8 FFT ADC Channel On board clock 18 Figure 9 DAG FP
21. ADC A ADC B 1x AD9777 DAC 16 bit Q 400MSPS 80 pin TQFP RF transformer transformer Figure 14 Clock Routing The skew between ADC clock signals is negligible which means that samples coming from both converters can be considered as synchronised when Bit26 and Bit27 are the same It is to the user not to set too high frequencies i e higher than 105MHz for the ADCs and 160MHz for the DAC This could damage the converters Version 2 0 Page 37 of 46 SMT370v2 v3 User Manual Register 0x6 Channel selection Triggers Decimator for ADCS oma 4 7 mm 9 gt ma gt Ces 7 mms _ S Bit 12 Decimation Factor Channel A Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 External Trigger Level 0 Active low 1 Active high External Trigger Enable 0 External Trigger Disabled 1 Enabled Not Used Channel A Selection Enable Bit 2 Channel A Selection Enable Bit 1 Channel A Selection Enable Bit 0 Not Used Channel B Selection Enable Bit 2 Channel B Selection Enable Bit 1 Channel B Selection Enable Bit 0 Version 2 0 Page 38 of 46 SMT370v2 v3 User Manual A Decimation Factor of 0 default value does not have any effect on the data flow Whe
22. C P2B lt 2 gt LOC NET OPES DATA lt 1 gt LOC TISE NET DAC P2B lt 3 gt LOC AB14 NET CP3 DATA lt 2 gt LOC U19 NET DAC P2B lt 4 gt LOC W14 NET CP3 DATA lt 3 gt LOC U20 NET DAC 2 lt 5 gt LOC Y14 NET DATA lt 4 gt LOC U21 NET DAC 2 lt 6 gt LOC U14 NET CP3 DATA lt 5 gt U22 NET DAC 2 lt 7 gt LOC V14 NET DATA lt 6 gt LOC T19 NET DAC P2B lt 8 gt LOC AA15 NET COPS DATA lt 7 gt LOC T20 NET DAC P2B lt 9 gt LOC AB15 NET CP3 RDY LOC V20 NET DAC P2B lt 10 gt LOC W15 NET CP3 REQ LOC V22 NET DAC 2 lt 11 gt Y15 NET CUDPS STBT 106 VIS 7 NET DAC 2 lt 12 gt LOC AA16 NET CPO STB LOC V3 NET DAC P2B lt 13 gt LOC AB16 NET CPO REQ LOC Y2 NET DAC P2B lt 14 gt LOC W16 NET CPO RDY LOC V4 NET DAC P2B lt 15 gt LOC Y16 NET CPO DATA lt 7 gt LOC U5 NET DAC RESET LOC V13 CPO DATA lt 6 gt LOC V5 NET DAC SPI CLK LOC AA13 NET DATA lt 5 gt ABA NET DAC SPI CSB LOC U12 NET CPO DATA lt 4 gt LOC AA4 NET DAC SPI SDIO LOC AB13 NET CPO DATA lt 3 gt LOC Y4 NET DAC SPI SDO LOC U13 NET DATA lt 2 gt LOC AAS gt NET DAC TRIG LOC W22 NET CPO DATA lt 1 gt LOC Y5 d NET SHBB lt 59 gt LOC T
23. Cs and input only for SHBB used to suck samples in to the DAC For more details about ComPorts and SHB The following link will give YOU more information External Interface User manual pdf Version 2 0 Page 16 of 46 SMT370v2 v3 User Manual ADC Performance Analogue inputs 1 2 Vols peak to peak AC coupling SMT370v2 v3 Maximum voltage 2 2 Volts peak to peak DC coupling Gain 1 Specify ADC coupling when placing an order No anti aliasing filter on the board It is to the user to set one up if required Bandwidth Input transformers AC option 2 775 MHz Input opamps DC option 0 320 MHz A to D converters 0 250 MHz External Clock DC coupled input Requires a External clock signal centered around OV Minimum voltage 0 2 Volt peak to peak minimum Maximum voltage 3 3 Volts Minimum voltage 3 3 Volts LVTTL 3 3 Volts format connected to 3 3V FPGA Clamp diodes to 3 3V and Ground Maximum sampling frequency Figure 5 ADC Performance Signal format Version 2 0 Page 17 of 46 SMT370v2 v3 User Manual The schematics below give details on the ADC input coupling Both options AC or DC couplings are shown Standard coupling is AC Specify when ordering if DC coupling is required Figure 6 ADC input stage AC coupled L Gi 31 a FAR Ms 22R 5 GA RS RE 60 4m 22H 623A u H R7 Q 5 R
24. DAC AD9777 sampling at up to 400MHz interpolation 32Mbits 1Mx4bytes of NISRAM working at up to 160 MHz for pattern generator or AWG mode Single width module Two Sundance High speed Bus SHB connectors Two 20 MegaByte s communication ports Low jitter on board system clock Xilinx Virtex ll FPGA 50 Ohm terminated analogue inputs and outputs external triggers and clocks via MMBX Huber and Suhner connectors User defined pins for external connections Compatible with a wide range of Sundance SHB modules TIM standard compatible Default FPGA firmware implementing all the functions described in this documentation Version 2 0 Page 7 of 46 SMT370v2 v3 User Manual Block Diagram Architecture The following diagram shows the architecture of the SMT 370 Connections to the outside world are greyed out gt cN J1 Top Primary TIM Connector 2x CommPorts SDLs 0 amp 3 Figure 1 Block Diagram 3 Power J2 Bottom Primary TIM supply Connector LEDs FPGA configured D LED 9 i On board Oscillator 50 zx or DC AC or DC 4 LEDs or coupling coupling 4 LVTTL I O pins FPGA PROM I 2xAD6645 ADCs m a dw 20 ta cti TT XC18V
25. HBB lt 18 gt LOC H22 3 NET SHBA lt 34 gt LOC NS NET 5 lt 17 gt LOC H21 g NET SHBA lt 33 gt LOC N4 NET 5 lt 16 gt LOC H20 NET SHBA lt 32 gt LOC N3 NET SHBB lt 15 gt LOC H19 NET SHBA lt 31 gt LOC N2 S NET 5 lt 14 gt LOC G22 NET SHBA lt 30 gt LOC UNIV NET 5 lt 13 gt LOC GAL 4 NET SHBA lt 29 gt LOC M6 NET 5 lt 12 gt LOC G20 NET SHBA lt 28 gt LOC MS NET 5 lt 11 gt LOC G19 NET SHBA lt 27 gt LOC MA NET 5 lt 10 gt LOC HIS NET SHBA lt 26 gt LOC M3 NET SHBB lt 9 gt LOC G18 NET SHBA lt 25 gt LOC M2 s NET SHBB lt 8 gt LOC F22 NET SHBA lt 24 gt LOC MI NET 5 lt 7 gt LOC F21 5 NET SHBA lt 23 gt LOC L2 7 NET 5 lt 6 gt LOC F20 73 NET SHBA lt 22 gt LOC L3 4 NET 5 lt 5 gt LOC F19 NET SHBA lt 21 gt LOC L4 NET SHBB lt 4 gt LOC E22 NET SHBA lt 20 gt LOC L5 NET 5 lt 3 gt LOC E21 NET SHBA lt 19 gt LOC KI NET 5 lt 2 gt LOC E20 5 NET SHBA lt 18 gt LOC K2 NET 5 lt 1 gt LOC EIS NET SHBA lt 17 gt LOC K3 NET SHBB lt 0 gt LOC D22 3 NET SHBA lt 16 gt LOC K4 NET SHBA lt 59 gt LOC W2 NET SHBA lt 15 gt LOC L6 SHBA lt 58 gt LOC WL NET SHBA lt 14 gt LOC K6
26. SPIs are write only i e they can t be read back directly from the chip Clock multiplexers are also available on the board to route the appropriate clock signal from external or on board source to the converters It is usual to have both ADOs fed with the same sampling clock but it is possible to have an ADC receiving the external clock and the second one receiving the on board clock In this particular case two 16 bit interfaces are necessary to transfer samples to an external TIM The DAC is fed either with an on board DAC or external clock coming from connector J14 The clock selection is made via the control register Sundance High speed Bus SHB The SMT370 provides 2 full SHB Sundance High speed Bus connectors labelled SHBA J3 and SHBB J4 see Figure 13 Connector Location SHBA is set as transmitter only to transfer data coming from the Analogue to Digital Converters to an external SHB module for instance SMT365 SMT365E or SMT374 SHBB is set as a receiver only and is dedicated to receive data for the Digital to Analogue converter Transfers at up to 100 MHz are supported on these two SHB connectors SHBA ADCs The FPGA routes the data lines coming from the ADCs to SHBA Data lines go through 7 latch stages inside the FPGA which means that it takes 7 sampling clock cycles for a sample to go from the ADC to SHBA The board offers to possibility to output data in either two s complement or binary format It is also
27. SUNDANCE 5 SMT370v2 v3 User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Version 2 0 Page 2 of 46 SMT370v2 v3 User Manual Revision History Date Comments Engineer Version 08 03 03 Details added about registers and external signals figure references examples FPGA Firmware changed ADC DAC Triggers 31 03 03 and ADC decimators added SHBA and B 16 Or 32 bits 15 05 03 ComPorts description improved Two separate options to the board FPGA Global reset register added More comments on register settings FPGA utilisation added Example code removed 01 08 03 Corrects spelling mistakes adds temperature measurements mentions SMT6600 package 05 09 03 One link fig11 was missing PSR issi PSR 15 10 03 Updated for SMT370v3 PSR 17 12 03 Pattern generator description a bit confused PSR Modified it Module 18 12 03 Module Height added PSR 2 05 04 AWG term added PSR PSR SR 13 07 04 Input and output stages ADC DAC schematics added ADC input voltage corrected 02 06 05 Figure 13 corrected Version 2 0 Page 3 of 46 SMT 370v2 v3 User Manual Table of Contents REVISION ISIONY u is di 2 Table of Contents 3 UN AN gt EEE EE 5 NNN D ever 5 JUNE w kl
28. T SHBA lt 55 gt V2 3 NET SHBB lt 38 gt LOC M20 NET SHBA lt 54 gt LOC VI 7 NET 5 lt 37 gt LOC M21 NET SHBA lt 53 gt U2 NET SHBB lt 36 gt LOC L22 NET SHBA lt 52 gt LOC UI NET 5 lt 35 gt LOC L21 NET USHBACOIU LOG 15 lt NET SHBB lt 34 gt LOC L20 NET SHBA lt 50 gt LOC R5 NET SHBB lt 33 gt LOC L19 NET SHBA lt 49 gt LOC T4 NET 5 lt 32 gt LOC L18 NET SHBA lt 48 gt LOC T3 3 NET 5 lt 31 gt LOC 117 NET SHBA lt 47 gt LOC T2 NET 5 lt 30 gt LOC K22 3 NET SHBA lt 46 gt LOC TI NET 5 lt 29 gt LOC K21 4 NET SHBA lt 45 gt LOC 7 NET SHBB lt 28 gt LOC K20 gt NET SHBA lt 44 gt R3 NET 5 lt 27 gt LOC NET SHBA lt 43 gt LOC R2 NET 5 lt 26 gt LOC Klo NET SHBA lt 42 gt LOC RI NET 5 lt 25 gt LOC Kl 2 NET SHBA lt 41 gt LOC P6 NET SHBB lt 24 gt LOC J22 NET SHBA lt 40 gt LOC PS NET 5 lt 23 gt LOC J21 3 NET SHBA lt 39 gt LOC P4 NET 5 lt 22 gt LOC J20 3 NET SHBA lt 38 gt LOC NET SHBB lt 21 gt LOC J19 NET SHBA lt 37 gt LOC P2 3 NET 5 lt 20 gt LOC J18 NET SHBA lt 36 gt LOC PI NET 5 lt 19 gt LOC J17 4 NET SHBA lt 35 gt LOC NG NET S
29. When fitted PROM loaded into at reset SMT3I7BVZ Figure 13 Connector Location The diagram below gives the position and the meaning of the connectors that the customer is likely to use Version 2 0 Page 28 of 46 SMT370v2 v3 User Manual Operating conditions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to a TIM40 compliant carrier board The SMT370 module is in a range of modules that must be supplied with a 3 3v power source In addition to the 5v supply specified in the TIM specification these new generation modules require an additional 3 3v supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3v power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended The SMT370 is compatible with all Sundance TIM carrier boards It is a 5v tolerant module and as such it may be used in mixed systems wit
30. ZBT ADDR lt 16 gt LOC E5 NET ZBT nBWc E14 NET ZBT ADDR lt 15 gt LOC OZ NET ZBT nBWb E13 NET ZBT ADDR lt 14 gt LOC C1 NET ZBT nBWa LOC D13 NET ZBT ADDR lt 13 gt LOC D2 NET ABT ZZ B15 NET ADDR lt 12 gt LOC Di w nWE LOC BLA NET ZBT ADDR lt 11 gt LOC E4 X NET ZBT DQd lt 7 gt LOC 75 NET ZBT ADDR lt 10 gt LOC E3 NET DQd lt 6 gt LOC VELIT NET ZBT ADDR lt 9 gt E2 NET AST DQd lt 5 gt BIO NET ADDR lt 8 gt El NET ZBT DQd lt 4 gt LOC A10 NET ZBT ADDR lt 7 gt LOC F5 ug NET DQd lt 3 gt LOC VEND NET ZBT ADDR lt 6 gt LOC G5 y NET AST DQd lt 2 gt LOC F10 X NET ADDR lt 5 gt F4 NET ASI DQd lt 1 gt LOC DION 4 NET ABT ADDR lt 4 gt F3 NET DQd lt 0 gt LOC C10 NET ZBT ADDR lt 3 gt F2 NET AST DQc lt 7 gt LOC DE 3 NET ZBT ADDR lt 2 gt F1 x NET 2 _ lt 6 gt LOC C8 2 NET ABT ADDR lt 1 gt LOC G4 NET ZBT DQc lt 5 gt LOC B7 NET ZBT ADDR lt 0 gt LOC G3 NET ABT DQc lt 4 gt LOC NET ZBT CLK LOC VALLE NET ZBT DQc lt 3 gt LOC D7 4 NET PXI CLK LOC C18 NET DQc lt 2 gt LOC VETT 3 NET PXI TRIG1 LOC E18 v NET ZBT DQc lt 1 gt
31. d NET FREQ S DATA DAC LOC B17 NET FREQ S LOAD ADCs LOC A18 Constraint File Virtex II for SMT370 m NET FREQ S LOAD DAC LOC C17 ADCA DATA 0 LOC W9 t NET ADCA DATA lt 1 gt LOC AB9 Author Philippe ROBERT NET ADCA DATA lt 2 gt LOC AA7 NET DATA lt 3 gt LOC U9 SDate 23 O07 2002 NET ADCA DATA lt 4 gt LOC V8 SVersion 1 O Original draft NET DATA lt 5 gt LOC Y8 ADCA DATA lt 6 gt LOC AA6 SDate 09 09 2002 DATA lt 7 gt LOC Y7 SVersion 1 1 CP1 removed Clock synth NET ADCA DATA lt 8 gt LOC WI changedt NET ADCA DATA lt 9 gt LOC AB 22 ADCA DATA lt 10 gt LOC AA5 NET DATA lt 11 gt LOC Y6 SVersion 1 O generated with FloorPlanner 5 NET ADCA DATA lt 12 gt LOC W6 5 1 1 1 generated with FloorPlanner NET DATA lt 13 gt LOC AB6 NET ADCA OVR LOC W8 SVersion 1 2 IIOFs added on V11 W12 and H mw 11 Version 1 3 ADCA and ADCB data lines BET SAN Dese TRUM swapped NET ADCB DATA 0 LOC U10 been put back in the right order NET ADCB DATA lt 1 gt LOC 11 E NET ADCB DATA lt 2 gt LOC V6 Sundance Multiprocessor Technology s NET ADCB DATA lt 3 gt LOC ABS tt tH HE HE EH EE EH EH TE E E E EE EH E E EE EH HH NET ADCB DATA 4
32. e sure that a Start operation is not selected when loading data into memory for pattern use Data are written into the memory under the SHB clock and read out under the DAC sampling clock Version 2 0 Page 41 of 46 SMT370v2 v3 User Manual SHBB works either on 16 Or 32 bits see also SDB technical specification v 2 1 pdf 16 bits each half of SHBB is 16 bit wide and has its own set of control signals Clock Write enable and acknowledge When Channel A and Channel B are enabled Bit24 and Bit25 set to 1 both FIFOs wait for each other to read out data to make sure that samples on both DAC ports P1B and P2B carry synchronised samples 32 bits if both sets of control lines are driven by the same signals SHBB becomes 32 bit compatible and each 32 bit data carries two synchronised samples Channel Enable A AcknowledgeO FIFO DAC 16 bit data 2048 words J13 Port P2B Q DAC Sampling Clock Acknowledge 1 FIFO DAC 2048 words Port P1B N N E C T R Channel Enable B Figure 15 SHBB data path Version 2 0 Page 42 of 46 SMT370v2 v3 User Manual Register 0xD FPGA Global Reset Bit By sending this control word the gets reset Every single register in the FPGA is reset The FPGA transmit that command to the DAC which will need to be reconfigured Clock synthesizers which keep the internal register values but does not output any signal
33. efer to the SHB specifications for more details about ways connectors can be configured Both SHBs can work either as two 16 bit interfaces or a single 32 bit interface In the case of a 32 bit interface both ADCs must receive the same sampling clock signal The SMT370 is therefore fully compatible with Sundance 16 bit and 32 bit processor modules without setting any register Four LEDs are driven by the FPGA Four LVTTL I Os for general purpose are also available No clamping diodes to 3 3 Volts and ground are available on the board to avoid damaging pads on the FPGA It is therefore to the customer to make sure the signals connected to these I Os are LVTTL and don t show any overshoots External Clock trigger and analogue input signals are all single ended External connections to the board are all 50 Ohm terminated External triggers have clamping diodes to 3 3V and to Ground to avoid damaging the FPGA they are connected to A global reset signal is mapped to the FPGA from the top TIM connector to reset the FPGA and reload the FPGA Virtex FPGA What the FPGA does The SMI370 is populated with a Xilinx Virtex FPGA XC2V1000 6FG456 This device controls major functions on the module like ComPorts and SHB communications data flows to and from the converters memory and clock management This FPGA needs being configured after power up and after a module reset This operation is possible thanks to the on board Xilinx PROM This operation
34. eivers never connect two transmitters or two receivers For example connecting link 0 of one TIM to link 4 of another is safe connecting link 0 of one TIM to link 2 of another could damage the hardware Always connect ComPort 0 1 2 to ComPort 3 4 or 5 On most carrier board the physical connection between comm ports is made with FMS cables Ref SMT3xx FMS You must be careful when connecting the cables the make sure that one end is inserted in the opposite sense to the other One end must have the blue backing facing out and the other must have the silver backing facing out The SMT310Q SMT320 motherboard communicates with the host PC using ComPort 3 of the site 1 TIM You should not make any other connections to this ComPort ComPorts Communication ports links follow Texas Instrument C4x standard They are 8 bit parallel inter processor ports of the C4x processors The ComPorts drive at 3 3v signal levels The FPGA can implement up to two FIFO buffered ComPort interfaces fully compliant with the TIM standard They are guaranteed for a transfer rate of 20MB s The FIFOs are useful to maintain a maximum bandwidth and to enable parallel transfers Therefore as an example each ComPort can be associated with two 15x32 bit unidirectional FIFOs implemented into the FPGA one for input and one for output An additional one word buffer makes them appear as 16x32 bit FIFOs
35. h older TIM modules carrier boards and modules It is anyway recommended to use the SMT370 connected to an SHB TIM module such as SMT365 or SMT365E in order to get better transfer performance The external ambient temperature must remain between 0 and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I O activity The maximum power consumption is 10W Temperature This test has been performed in an ambient temperature of 28 degrees C in an open case standard PC The board was configured in Pattern generator mode and running full speed i e ADCs at 105 MHz with input signal full scale and the DAC at 400 MSPS 50 MHz and interpolation 8 FPGA 52 degrees Top metal case 51 degrees Bottom board 68 degrees Version 2 0 Page 29 of 46 SMT370v2 v3 User Manual When the board works in a close or warm environment Sundance recommends having a fan extractor or a fan blowing across the carrier board in order to keep the board away from the maximum temperature ratings of the components Version 2 0 Page 30 of 46 SMT370v2 v3 User Manual Register settings Register 0 0 DAC Register report to AD9777 datasheet for more details Bit m Bit 28 Bit 27 24 Not Used SDIO bidirectional O Input or 1 1 O To be set 0 when using default firmware Bit 23
36. he AD9777 dual interpolating 2x 4x 8x DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture This programmable converter has a resolution of 16 bits It features a Serial Port Interface SPI for programming The chip features a selectable 2x 4x 8x interpolation filter an Fs 2 Fs 4 or Fs 8 digital quadrature modulation with image rejection a direct F mode a programmable channel gain and offset control a programmable internal clock divider a straight binary to two s complement data interface and a single port or dual data interface Parallel busses connect both ADCs and the DAC to the FPGA which is responsible for transferring samples from to the converters An on board frequency synthesizer generates differential encode lines sampling clocks to feed the converters a connector for external clocks is also available Each input analogue signal to the ADCs goes through an extra stage which can be an opamp DC coupling or an RF transformer AC coupling The option must be defined when ordering the SM7370 When it comes to the DAC its outputs can only be set as AC coupled output RF transformer Both ADCs can be coupled together i e they have the same sampling clock or have two separate clocks one external and one coming from the on board clock synthesizer The Xilinx FPGA Virtex ll is configured via a 6 pin JTAG header or from the on board Xili
37. k cycles to go through the FPGA As both channels of the DAC are not necessarily synchronised the two FIFOs are read out at the same time as soon as there is a least one data in each FIFO it is the case when using two independent 16 bit interfaces To avoid synchronisation problems SHBB can be used as a single 32 bit interface Simply drive both sets of control register with the same signals DAC Channel A is mapped onto the lowest part of SHBB and DAC Channel B onto the highest Communication Ports ComPorts The SMT370 provides 2 physical ComPorts 0 and 3 The default bit stream provided implements ComPort 3 Input at reset to load control registers A physical connection to a ComPort 0 1 or 2 Output at reset is therefore necessary to an SMT365 for instance Please report to the part dealing with ComPorts Communication Ports ComPorts in this document for more details External triggering Two external trigger connectors J15 and J16 see Figure 13 Connector Location are available on the board to start or stop converters from an external source The selection is made via a control register where channel selection can also be set Triggering consists in enabling or disabling the converters ADCs and or DAC This is available and accurate as long as the triggering signals are synchronised on the sampling clock Trigger signals can be set as active high or low in via the control register Each trigger input is clamped
38. n is set to 1 one sample out of two is trimmed out When it is set to 2 one out of three is trimmed out and so on The maximum value is 31 The External Trigger signal is routed from connector J15 to the FPGA Two clamping diodes avoid too high amplitude signals to damage the FPGA Channel A selection 000 Channel disabled 001 16 bit counter on clock ADCA O10 Channel A two s complement encoding i e samples go straight through as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 O11 Channel A binary encoding Binary conversion consists in inverting the MSB of each sample This operation introduces a DC offset of half the full scale which can be removed by subtracting 8192 decimal of each sample Channel B selection 000 Channel Disabled 001 216 bit counter on clock ADCB 010 2Channel B two s complement encoding i e samples go straight through as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 011 Channel B binary encoding Binary conversion consists in inverting the MSB of each sample This operation introduces a DC offset of half the full scale which can be removed by subtracting 8192 decimal of each sample Version 2 0 Page 39 of 46 SMT370v2 v3 User Manual Register 0
39. nx PROM XC18V04 at startup The default configuration mode is from a PROM which contains the standard modes of operation as described in this document An on board red LED DONE LED indicates that the FPGA is configured Both devices FPGA and PROM are in the same JTAG chain The SMT370 is also populated with some NtSRAM memory It is 32 bit wide and to store two 16 bit samples at the same address at up 160 MHz size is 1 Megawords of 32 bits The FPGA is implemented with an NtSRAM interface to write read to from it Memory accesses are made via a control register A pattern generator function is available to store a pattern or periodic frame into the memory read back continuously and send samples out to the DAC This configuration allows to board to work as a periodic generator in stand alone mode In this mode the SMT370 works as a loadable AWG Arbitrary Waveform Generator Version 2 0 Page 9 of 46 SMT 370v2 v3 User Manual Two Communication links ComPorts following the Texas Instrument C4x standard are connected to the FPGA and will be used to receive control words or for other purpose They can achieve transfers at up to 20Mbytes s Two full SHB connectors 60 pin are accessible from the FPGA The first connector SHBA J3 is set as output only and is dedicated for sending out samples coming from the ADC The second connector SHBB J4 is set as input only to receive samples which are redirected to the DAC Please r
40. ol word the FPGA reads back the AD9777 DAC internal registers and send them on CP3 as well as the ADC coupling option Register Ox5 Register 0x6 and Register 0 7 in the following order Board Option 0x000000AC for an AC coupled board or 0x000000DC for a DC coupled board Clock Management Register Register 0x5 Clock management Trigger Decimator Register Register 0x6 Channel selection Triggers Decimator for ADCs the Pattern Generator Register Register 0 7 DAC control Pattern generator and then 14 words of the following format OXxAD9777xx The last byte 8 Less Significant Bits gives the value Version 2 0 Page 44 of 46 SMT370v2 v3 User Manual of a DAC internal register The 370 starts by sending out register at address 0 0 and carries on up to register Oxd Example Let s consider that the following registers have been loaded into the DAC RegisterO 0x00010203 Register1 0x01111213 Register2 0x02212223 Register3 0x03313233 Register4 0x044142xx After sending the word 0 0000000 to an SMT370v3 AC which internal clocks are set to 100MHz ADC clock and 50MHz DAC clock and which ADC and DAC channels are all enabled the host gets back in return the following values 0x000000AC 0x03990D90 0 00000033 0 00000000 OxAD977701 OXAD977702 OXAD977703 97 7711 0xAD977712 OXAD977713 97 7721 OxAD977722 0xAD977723 97 7731 0xAD977732 OXAD977733 97 77
41. sabled its corresponding FIFO is too Direct Transfer When Direct DAC mode selected Bit22 1 samples follow the following path SHBB gt FPGA FIFO gt DAG Data are first written into a FIFO at the SHB clock rate and read out and routed to the DAC at the DAC sampling clock rate There is one FIFO per 16 bit SHB path Each of them can contain up to 512 words Version 2 3 of the FPGA firmware or 2048 words of 16 bits Version 2 4 and above of the FPGA firmware When Bit20 0 the Pattern Generator mode is enabled The Pattern Generator is a feature of the SMT370 which allows the user generating a periodic signal without taking any external CPU resource It consists in using the on board ZBTRAM memory Here are the steps to follow o Load into register 0x7 a Pattern Size Bit22 0 Bit20 1 and set Bits 24 and 25 o Send Samples to be loaded into the memory on SHBB o Once sample transfer completed send a Start command Load Pattern Size when Bit20 is set high PatternSize is loaded into a register It also resets the Pattern Generator itself allowing then reloading a pattern of a different size at any time Pattern Size 20 bits are available to define the size of a pattern One unit bit defines a 32 bit value two 16 bit synchronised DAC samples A 20 bit size corresponds to the maximum size of the on board ZBTRAM Start Stop This to start or stop the pattern generator i e the read back operation Mak
42. wl kd a sa la a al a ca a 6 Block Diagram Architecture 7 Areniecture DESEN PO WON aS 8 ME FP 9 VE PN NN 9 FYESSOUFC OCCUDIGG eda a a ka kek k ea e koka ke a kab A 10 MENN EN 10 ADC O BB EN 11 Clock nn Ee e En EE 11 Sundance High speed BUS s SHB vvs 11 lt lt Sat t t t aa 11 FEED 12 Communication Ports COMPOMS EE 12 PE NN 12 EID vr 12 iunio HH 13 Sundance Standards a uuu sak u kako kan 13 GOMMUNICAtON POTTS COMP OMS EE 13 Sundance High speed Bus SHB 14 Communication links implemented the SMT370 15 For more details about ComPorts and SHB 15 DAC DOMO E te u u u EE uo ons eh 19 SEE 8 a 19 8 M m 21 OU get ata a ai ase tee srs m 22 AUDOWSISUD and NES EE 26 Connector P S kk ak a kk ak ak ka a ak a uai vi a 27 Version 2 0 Page 4 of 46 SMT370v2 v3 User Manual leede e Re eil tele EE 28 sS e EE ey s 28 EN 28 General 28 Bee ein Gr leit e 28 Fe EG 28 REST 30 Register 0 0 DAC Register report to AD9777 datasheet for more details 30 Register Ox1 DAC register report to AD977
43. x7 DAC control Pattern generator ms Bit 29 1 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Start Stop Pattern generator 1 Start 0 Stop Bit 20 Load Pattern Size Active high 1 Load into FPGA 0 No Load Bit 19 Pattern Size Bit 19 Bit 18 Pattern Size Bit 18 Bit 17 Pattern Size Bit 17 Bit 16 Pattern Size Bit 16 Bit 15 Pattern Size Bit 15 Bit 14 Pattern Size Bit 14 Bit 13 Pattern Size Bit 13 Bit 12 Pattern Size Bit 12 Bit 11 Pattern Size Bit 11 Bit 10 Pattern Size Bit 10 Bit 9 Pattern Size Bit 9 Bit 8 Pattern Size Bit 8 Bit 7 Pattern Size Bit 7 Bit 6 Pattern Size Bit 6 Bit 5 Pattern Size Bit 5 Bit 4 Pattern Size Bit 4 Bit 3 Pattern Size Bit 3 Bit 2 Pattern Size Bit 2 Bit 1 Pattern Size Bit 1 Bit 0 Pattern Size Bit 0 External Trigger Level 0 Active low 1 Active high External Trigger Enable 0 External Trigger Disabled 1 Enabled Channel B Enable 0 Disabled 1 Enabled Channel A Enable 0 Disabled 1 Enabled Direct Transfer 17 SHB Direct DAC mode 0 Pattern generator mode Version 2 0 Page 40 of 46 SMT370v2 v3 User Manual The External Trigger signal is routed from connector J16 to the FPGA Two clamping diodes avoid too high amplitude signals to damage the FPGA Channel Enable allows using only one DAC channel When one is di
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