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Thesis by Brian C. Keeney - SCIPP - University of California, Santa

1. 7 77 if this is the feedback loop for dcmi BUFG dcm 1 fb I dcmi cik out O fe_clk DCM demi CLKFB fe clk CLKIN cIk DSSEN gnd PSCLK gnd PSEN gnd PSINCDEC gnd RST res_dcmi CLKO dcmi_clk_out LOCKED dcmilocked synthesis attribute DLL FREQUENCY MODE of dcmi is LOW synthesis attribute CLKOUT PHASE SHIFT of dcmi is fixed synthesis attribute PHASE SHIFT of dcmi is 64 synthesis attribute DUTY CYCLE CORRECTION of dcmi is true synthesis attribute STARTUP WAIT of dcmi is false synopsys translate off defparam dcmi CLKOUT PHASE SHIFT FIXED defparam dcmi PHASE_SHIFT 64 defparam dcmi DLL FREQUENCY MODE LOW defparam dcmi DUTY CYCLE CORRECTION true defparam dcmi STARTUP WAIT false synopsys translate on 86 7777 777 7 7 7 7 7 7 7 7 7 7 7 7 7 77 7 7 7 This DCM controls the phase of clk data wrt fe cik and creates the 1 5 clk 7777 777 7 77 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 BUFG dcm 2 fb I dcm2 out O chop_clk DCM dcm2 CLKFB chop c1k CLKDV div5 RST res dcm2 CLKO dcm2 out CLKIN fe clk DSSEN gnd PSCLK gnd PSEN gnd PSINCDEC gnd LOCKED dcm21ocked synthesis attribute CLKDV_DIVIDE of dcm2 is 5 000000 synthesis attribute CLKOUT_PHASE_SHIFT of dcm2 is fixed synthes
2. 3K 3K 3K 3K 3K 3K 3K 3K K K K K K K 2K 2K 2K 2K 3K 3K 3K 3K 3K 3K 3K 2K 3K KK K KK HE void fit_gauss TNtuple ptsmout s_pulse_index s_pulse s_fit_gauss s_gauss float v_thresh_comp char ps name 128 char h label 128 char h_cut 128 char h name 128 int i pulse float event id channel tot v pulse v thresh TH1F x NUM PULSE BINS TCanvas c MAX NUM PULSE BINS TBranch bri ptsmout GetBranch event id bri gt SetAddress amp event id TBranch br2 ptsmout gt GetBranch channel br2 gt SetAddress amp channel TBranch br3 ptsmout GetBranch tot br3 gt SetAddress amp tot TBranch br4 ptsmout GetBranch v pulse br4 SetAddress amp v pulse TBranch br5 ptsmout GetBranch v thresh br5 gt SetAddress amp v thresh TF1 g new TF1 g gaus g gt SetLineColor 2 g gt SetLineWidth 2 for i pulse 0 i pulse s_pulse gt num_pulses i_pulse sprintf h name h d d s gauss ochannel i pulse sprintf h cut iv pulse 4f 001 amp amp v pulse Af 001 amp amp v thresh 4f 001 amp amp v_thresh lt f 001 amp amp channel d 138 S pulse pulse index i pulse S pulse pulse index i pulse v thresh comp v thresh comp s_gauss gt channel h i pulse new THIF h name h name MAX TOT 0 MAX TOT 1 hli_pulse gt SetStats kFALSE c i pulse new TCanvas if pt
3. 128 NOISE SECTION noise graph iChannel new TGraphErrors fit array iChannel n points fit array iChannel mu fit array iChannel sigma fit array iChannel mu err fit array iChannel sigma err noise canvas iChannel new TCanvas noise graph iChannel Draw A fnoise gt SetParameters 1 0 0 1 noise graph iChannel Fit fnoise Q set title array gr title fnoise iChannel 0 noise graph iChannel GetXaxis O 5SetTitle Charge Input fC noise graph iChannel GetYaxis O SetTitle Noise e noise graph iChannel SetTitle gr title sprintf pslabel noise curves noise ch d ps iChannel TPostScript ps2 pslabel type ps2 Range 24 16 set x y of printed page noise canvas iChannel gt Update ps2 CloseO store gain noise chan gain noise iChannel fgain oGetParameter 1 gain fgain GetParError 1 fgain oGetParameter 0 offset fgain oGetParError 0 fnoise oGetParameter 0 noise fnoise oGetParError 0 fnoise oGetParameter 1 noise slope fnoise oGetParError 1 1 if there are points else a dud channel store gain noise chan gain noise iChannel 0 gain 0 0 offset 0 129 0 noise 0 0 noise slope 0 printf n fit_gain_curves void make chip map channel stats chan gain noise int num_chan float chan numbers num chan int i float chip gain f O float chip gain err f O float chip noise f 0 float c
4. parameter 4 0 group 14 5 b11111 parameter 5 0 init 6 b000001 updateO 6 b000010 updatei 6 b000100 update2 6 b001000 update3 6 b010000 hold 6 b100000 106 wire 34 0 fifo out wire 1 0 data count wire fifo full fifo empty assign many data count 1 assign some fifo empty assign dout group_id fifo out synthesis attribute uselowskewlines of S is yes ch fifo ch fifo Clk clk sinit res fifo din chan updown tyme The event data is Wr en wr fifo concatenated here rd_en rd_fifo dout fifo_out full fifo_full empty fifo empty data count data count always posedge clk begin if res begin chan_stat chan updown wr_fifo lt 0 res fifo lt 1 bi S lt init end else begin case S init begin chan_stat chan updown wr_fifo res_fifo lt 0 S data ready updateO init end update0 begin chan statl01 lt din 0 wr fifo lt chan stat 0 din O0 chan lt 2 b00 updown lt din 0 S lt updatel end 107 updatei begin chan stat 1 din 1 wr fifo chan stat 1 din 1 chan lt 2 b01 updown lt din 1 S lt update2 end update2 begin chan stat 2 din 2 wr fifo chan stat 2 din 2 chan lt 2 b10 updown lt din 2 S lt update3 end update3 begin chan stat 3 din 3 wr fifo chan stat 3 din 3 chan lt 2 b11 updow
5. 4 16 6 66 8 3 9 65 10 75 12 05 13 2 14 65 16 15 18 float charge high NUM DATA POINTS charge low NUM DATA POINTS error bars NUM DATA POINTS g o NUM DATA POINTS err NUM DATA POINTS g NUM DATA POINTS g err NUM DATA POINTS char fit results 128 file name 128 int i j for i 0 i lt NUM_DATA_POINTS i charge high i 1 22 5 50 5 6 25 float i 1 vout vin ccap 5volt inc charge low i 316f 5 50 5 1 56 float i 1 vout vin ccap 5volt inc error_bars i 01 float charge picker NUM DATA SETS charge low charge low charge low charge low charge high charge high charge high charge high charge low charge low charge high charge high charge low charge low charge high charge high 161 float x data set NUM DATA SETS43 ch 1 pulse 100mv low ch 4 pulse 100mv low ch 10 pulse 100mv low ch 15 pulse 100mv low ch 1 pulse 100mv high ch 4 pulse 100mv high ch 10 pulse 100mv high ch 15 pulse 100mv high ch 1 pulse 125mv low ch 15 pulse 125mv low ch 1 pulse 125mv high ch 15 pulse 125mv high ch 1 det 125mv low ch 4 det 125mv low ch 1 det 125mv high ch 4 det 125mv high charge low charge high error bars char data names NUM DATA SETS 3 128 1 ch 1 pulse 100mv low ch 4 pulse 100mv low ch 10 pulse 100mv low ch 15 pulse 100mv low ch 1 pulse 100mv high ch
6. Figure 17 Typical gain curve for a range of thresholds m this example the gain is 97 6 mV fC 92 reasonable limitation it is highly unlikely that 16 particles will ever be incident on the detector during its operation The uncollimated beam used by LLUMC has lt 100 protons spaced evenly over several hundred ms with an active area of more than 100 cm This makes the odds of having two events overlap negligible 4 1 2 Statistical Analysis Using the threshold value and the 50 point of the s curve in fC the gain G for a single threshold is computed in the following way mV H Vinresh mV i FC i Coal Vpulsel fC 24 The output of the pulse generator is attenuated by four 6 dB and one 14 dB attenu ators in order to bring the pulse generators output into the appropriate range The calibration capacitors internal to the PMFE are nominally 50 fF Direct measure ment on chip with a precision LCR meter confirmed this value The final conversion equation becomes ae Vinresh 75 m Vinresh 25 50fF Voutse 1655 atten l Voutse 50 a 625 26 The error on the gain using the fit errors is dG Vihresh o g x 0M se 8 V ise 27 gain dV ise pulses gor ccr pulse50 The noise and the error on the noise are computed in a similar manner The noise OV uise 18 extracted from the width of the Gaussian i e the standard deviation in 53 units of electrons Qnoise _ O
7. 1 bi good read lt 17b0 S lt home end else if good read begin idle lt 0 rd fifo lt 17b0 shift reg lt din 39 30 1 b0 din 29 15 1 bO din 14 0 shift count lt 0 S lt shift data out end else begin S lt home idle lt 1 bi end end 114 shift data out begin if lack begin S lt home ack err lt 1 bi end else 18 req lt daq clk 7 ishift 1 1261 ishift data out 1 bO end shift 1 begin if lack begin S lt home ack err lt 1 bi end else S lt daq clk 7 shift 1 wait 4 latch end wait 4 latch begin if lack begin S lt home ack err lt 1 bi end 5 lt daq_clk 7 hold time wait 4 latch end hold time begin if lack begin S lt home ack err lt 1 bi end else begin 115 shift_reg lt shift_reg gt gt packet shift the reg by packet bits shift count lt shift count 1 7 2 b00 f shift count shift countl01 req lt shift count 1 S lt shift count 1 home shift 1 good read lt shift count 1 end else end default S lt init endcase end always endmodule 116 C Gain v2 Source Code DOERR AAA ak 3k 3K K aK K K aK ak aK aK ak aK 3K 3K 3K 3K 3K 3K 3K 3K K 2K 2K 2K 3K 3K 3K K I I I I K K 2k 2k 2k 2k 2k 2k v2 Program to fit s curves make gain and resolution curves and chip wide maps of these parameters Brian Keeney 6 2004 HE 3k
8. Diagram showing how data corruption occurs Event 4 was lost by the NI6534 causing a shift in the data For example what is really the time stamp of one event could be interpreted as the channel ID of the next events M t Er een a te EP SR E TD V UR d Diagram showing the first event to be read out Note that all digits are in hexadecimal format See the Glossary for an explanation of hex notation 2 x79 ce ques DEC e en C Reb aaa Re Saree Cy es Diagram showing error handling When an word is corrupted an error code is sent out and the whole event is sent again Note that all digits are in hexadecimal format Results of the comparator based method of TOT characterization The computed error on these figures is artificially low due to fitting a line to non linear data Summary of the characterization of the PTSM system The TOT gain results listed are for the 5 60 fC region at the 125 mV threshold The noise measurements were taken without a mounted detector viii Abstract The Design Implementation and Characterization of a Prototype Readout System for the Particle Tracking Silicon Microscope Brian C Keeney The purpose of this paper is to describe the development and effectiveness of a pro totype instrument with applications in radiobiology Radiobiologists at Loma Linda University Medical Center are studying the effects of ionizing radiation o
9. R R R R SK SK SK SK SK SR SR SR 3K I SR SR SR SR SR SR SR SR 21 R k k k ok k 3K 2K k kok ok COMP_GAIN CXX Program to fit and analyze gain curves obtained from a scope output 3K k ak ak 3k 3k k 3K aK aK K aK aK aK aK ak ak aK 3K 3K 3K 3K 3K 3K 3K 3K 3K 3K K K K K K 2K 2K K 2K 2K 3K 3K 3K 2K 3K 3K K KKK KK K K const int NUM_DATA_SETS 16 const int NUM_DATA_POINTS 10 const float MAX CHARGE 70 include TFile h include TROOT h include TTree h include TBranch h include TH1 h include TProfile h include TNtuple h include lt stdio h gt include lt stdlib h gt include TMath h include TF1 h include TCanvas h include TGraph h include TGraphErrors h include TPostScript h include math h int main int comp_gain 5 float paper datal26 34 55 76 9 1 1 1 26 1 46 1 6 1 74 1 88 2 07 2 39 2 66 2 93 3 25 3 49 3 79 4 12 4 28 4 56 5 88 7 09 8 18 9 3 10 45 12 85 float paper chargel261 159 11 25 1 875 2 5 3 125 3 75 4 375 5 5 625 6 25 6 875 7 5 8 75 10 11 25 12 5 13 75 15 16 25 17 5 18 75 25 31 25 37 5 43 75 50 62 5 77 77 7 7 100mvset 7 7 7 float ch 4 pulse 100mv low 10 45 1 20 1 89 2 6 3 2 3 8 4 3 4 8 5 26 5 64 float ch 4 pulse 100mv high 10 2 47 4 68 6
10. case amp wakeup timer 1 b1 S cal jumper 7 send pulse radiation test 1 bO S lt init endcase end 95 send_pulse begin trig_delay lt trig_delay 1 this sends a trigger pulse that is one slow clock period wide the LeCroy can take pulses down to 1 5nS trig lt amp trig delay S amp trig delay wait for idle send pulse end wait for idle begin trig delay 8 h00 idle settle fast or amp amp Isome flag amp amp ctrlr idle 7 idle settle 2 idle settle 1 0 idle settle 1 0 idle settle 0 0 S amp idle settle inc pulse counter wait for idle end inc pulse counter begin cnt lt pulse jumper 7 cnt 6 amp cnt 5 0 cnt 5 amp cnt 4 0 cnt 4 amp cnt 3 0 cnt 3 amp cnt 2 0 cnt 2 amp cnt 1 0 cnt 1 0 cnt 0 not or xor below is equivalent to cnt limit cnt S lt CCcnt limit cnt pulse jumper pulse finish send pulse end pulse finish begin cnt lt 0 done lt 1 bi 96 res fifos lt 1 bi S lt Istart init pulse finish end radiation test begin drop done if data appears in fifos or controller if some flag ctrlr idle done lt 1 b0 after data disappears or start is dropped wait for 1 6 uS before the next state rad settle start some flag amp ctrlr idle rad s
11. iStatus DIG Out Line iDACDevice iDACPort iLineReset 1 iRetVal NIDAQErrorHandler iStatus DIG Out Line ilgnoreWarning printf resetting FPGA n ProcessSystemEvents iStatus DIG_Out_Line iDACDevice iDACPort iLineReset 0 iRetVal NIDAQErrorHandler iStatus DIG_Out_Line ilgnoreWarning ProcessSystemEvents ProcessSystemEvents ProcessSystemEvents ProcessSystemEvents ProcessSystemEvents DRO S R S R SR R SR SR R R SR R SSR SR R SR SR k kk kk kk kk k k k k k kk kk poll done polls the line corresponding to the calibration done pin of the FPGA done state specifies if the line is low 0 or high 1 kok kk kokk SR k kk kk kok kokk kokk ok void poll done ii6 iStatus i16x iRetVal intx done state 1 short s 0 iStatus DIG In Line iDACDevice iDACPort iLineDone amp s iRetVal NIDAQErrorHandler iStatus DIG In Line ilgnoreWarning done state s T void set cal bus i16 6703 dev num 116 bus num i16x iRetVal 116 iStatus 4 WriteToDigitalLine 6703 dev num 0 8 0 O bus num WriteToDigitalLine 6703 dev num 1 8 1 bus num WriteToDigitalLine 6703 dev num 0 2 8 0 2 bus num 149 WriteToDigitalLine 6703 dev num 3 8 3 bus num void set cal bus R K R R K RK SK RKS SR RK k R R SR RK K R SR SR SR R SR R SR SR R R SR R R
12. 10 01 33 The value of 10 fC is similar to that of the measured charge 1 fC A Monte Carlo study of the radiation source is needed to more accurately predict the charge deposited in the detector This measurement shows that the P TSM is a functioning instrument and that the characterization of the analog gain and TOT gain are reasonable 74 4 4 Conclusion The purpose of this section was to characterize the analog gain noise and Time Over Threshold TOT gain and to verify these results by imaging a Sr radiation source The two measurements of the TOT gain agree very closely with previously published data in 3 The TOT resolution is very low fine and appears to be relatively constant in the region from 10 to 60 fC Additionally reasonable spatial and energy deposition data was obtained when imaging a Sr 3 source The data in the preceding sections shows that the prototype readout system for the P TSM is a functional instrument with the following characteristics Table 5 Parameter Method Experimental Value Specified Value Units Analog Gain DAQ 93 9 55 120 DA Noise DAQ 616 24 1000 e TOT Gain SCOPE 200 00 l fo TOT Gain Offset SCOPE 1 81 01 NA LS TOT Gain DAQ 21702 1 Gain Offset DAQ 1 26 30 NA LS TOT Resolution 4 50 fC DAQ 23 Df 08 8 Source Measurement DAQ 8 86 38 10 01 Table 5 Summary of the charact
13. Co x V 17 C V3 V 18 a 18 AV ic Cmutual 332 01 19 mutual 227 05 AV Ci Os ViC 20 ic T PC Substituting eq 18 into 20 the total crosstalk savings is C 50fF C2 2 2pF toy _ 90 fF 2 6 516 5 10 21 ic MS 23pF i 2 This means that the crosstalk for the equivalent charge is reduced by a factor of nearly 2000 when using the external calibration capacitors For large charge inputs the external capacitors are essential 28 Biasing The Test Board also routes and filters the detector bias voltage as well as several other bias currents and voltages for the PMFE FPGA Interface The Test Board See Fig 10 was designed to mount directly onto the stake headers of a Xilinx Virtex 2 FG256 Proto Board See Fig 11 for a photo of the Proto Board which is a prototyping workstation for Xilinx FPGAs The Proto Board provides a variable frequency clock the connection to a PC for design downloading and arrays of stake headers leading directly to the FPGA input output blocks The Test Board uses a system of female row headers on the back side of the PCB such that it sits directly on top of one stake header array 3 4 The Readout Controller There were very few requirements placed on the design of the Readout Controller ROC In fact the only two requirements on the structuring of the ROC are at the interfaces to the PMFE and the NI6534 The front end chip require
14. R R R k R R k R R k R R SSR k SR kk kk kk kk kk k Main Functions kok R R R SR R R kokk R RK k R R R R R S R OR R SR R R SR R R XR R SR R R R RK R SR R R R a k k k k a 2k kk kk kkk RK R K S R R K R S R SR R SR RK SSR SSR SR RK SR K R S R R RK k R kk kk kk kk kkk kinit daq sets up the DAC DIO card and Pulser SOOO OO a kk kk ak Kk void init daq float v pulse float v thresh i16 iRetVal i16x iStatus int dev pulser int dev thresh 1 Configure the Pulser timeout is 3 seconds dev pulser ibdev iPulserBrdIndex iPulserPrimAdd iPulserSecAdd T3s 1 0 config pulser v pulse dev pulser config threshold power supply dev thresh ibdev iPulserBrdIndex iThreshPrimAdd 0 T3s 1 0 config thresh ps v thresh dev thresh configure Done line iStatus DIG Line Config iDACDevice iDACPort iLineDone iDirIn iRetVal NIDAQErrorHandler iStatus DACDIG LineDone Config ilgnoreWarning configure Start line iStatus DIG Line Config iDACDevice iDACPort iLineStart iDirOut iRetVal NIDAQErrorHandler iStatus DACDIG LineStart Config ilgnoreWarning configure Reset line iStatus DIG Line Config iDACDevice iDACPort iLineReset iDirOut iRetVal NIDAQErrorHandler iStatus 150 DACDIG LineReset Config ilgnoreWarning Configure group of ports as input with handshaking
15. W lt lt Figure 4 Schematic array of silicon strips on a Detector 18 or not a particle hit a 20 um diameter nucleus to 50 Lmarimum 107 m kov 12 35 pm 6 As was stated previously this value of 35 um is a worst case estimate because it does not take into account that there is a measurement of the charge deposited on each strip Using the ratio of charge deposited between 2 strips actual position resolution can far exceed this value Since the project is interested in using protons or heavy ions with relatively low energies and correspondingly high Linear Energy Transfers LET dE pdX working with a double sided detector is advantageous for two reasons First if a particle stops in the first of two single sided detectors X Y pair there will be no position resolution in one dimension Secondly the particle emerges from the first detector with a slightly different trajectory than the one it entered with By using a double sided detector the particle has to go through half of the mass that it would have otherwise had to in order to register as a legitimate event Therefore the project decided to use a double sided detector The downside to using a double sided detector is that the pulses that come out of the N side are negative Therefore more sophisticated front end electronics must be developed to handle both the positive and negative pulse shapes The goal of PTSM is to be able to detect whether or not a proton or h
16. tempstamp piBuffer i amp Ox7fff lt lt 15 grab the next 15 bits iWords else if iWords 2 tempstamp tempstamp piBufferl i 1 amp 0x3 lt lt 30 grab the last two bits tempstate piBuffer i 1 amp 0x4 gt gt 2 amp 0x1 grab the updown bit ibin piBuffer i amp Ox3f8 gt gt 3 amp Ox7f grab the 7 bit channel if f NULL 1 fprintf f event at 4X channel d goes to d n tempstamp ibin 64 tempstate fflush f 154 ibin ibin 64 if ve ve got a falling edge we ve got an event if tempstate 0 gg state ibin 1 1 if tempstamp 5 timestampl ibin 1 j tempstamp timestampl ibin else j tempstamp timestamp ibin 1 do ve add a 1 to this ftot j bin ibin if ibin NUM CHANNELS bin MAP ibin ptsmout gt Fill event id bin ftot v pulse v thresh timestamp ibin tempstamp state ibin tempstate iWords if iWords gt WORDS_PER_FRAME iWords O0 for i O to num words read find channels that were left high for ibin 0 ibin NUM CHANNELS ibin if state ibin 1 1 ftot 0 bin ibin if ibin NUM CHANNELS bin MAP ibin printf channel Zi left high n MAP ibin 1 ptsmout PFill event id bin ftot v pulse v thresh d 155 return 0 int parse data void cleanup 1 d
17. ulCount ulRemaining i 1 if f NULL fprintf f 4X Nt piBuffer i amp Oxffff if 1 piBuffer i OxfffO fprintf f Nt 2 for b 15 b gt 0 b fprintf f Ac C C piBuffer i amp long pov 2 gt 0 7 212 70 fprintf f Am fprintf f piBuffer i amp Oxffff look for start or error codes fill bins 201 202 203 and set iWords to 0 event analysis will begin with the next word read in HEY DORK Remember this if else if else if chain prioritizes actions from the first case on down Break the else if chain when you need two things to happen at once if piBuffer i amp Oxffbf Oxaaaa no more stuck bits right 1 bin 201 ftot 0 ptsmout gt Fill event id bin ftot v pulse v thresh iWords 0 d else if piBuffer i amp Oxffbf Oxbbbb bin 202 ftot 0 153 ptsmout PFill event id bin ftot v pulse v thresh iWords 0 d else if piBufferl i amp Oxffbf Oxcc8c bin 203 ftot 0 ptsmout PFill event id bin ftot v pulse v thresh iWords 0 d else if i 0 1 there s no error code to sync off of printf No error code was found at the start of data n return 0 d else if iWords tempstamp piBuffer i amp Ox7fff grab the first 15 bits iWords else if iWords 1 tempstamp
18. 0 00 0 17 4 0 01 ch 15 pulse 125mv low 0 28 0 00 1 84 0 01 ch 1 pulse 125mv high 0 20 0 00 1 06 0 01 ch 15 pulse 125mv high 0 20 0 00 2 55 0 01 ch 1 det 125mv low 0 44 4 0 00 1 32 0 01 ch 4 det 125mv low 0 36 4 0 00 1 05 0 01 ch 1 det 125mm high 0 23 0 00 3 53 0 01 ch 4 det 125mv high 0 19 0 00 3 14 0 01 167 Bibliography 1 10 11 12 Apoptosis Wikipedia The Free Online Encyclopedia http en wikipedia org wiki Apoptosis pp 1 2 1 3 2 2 E J Hall The Bystander Effect Health Phys July 2003 pp 1 H F Sadrozinski et al The Particle Tracking Silicon Microscope PTSM IEEE Transactions on Nuclear Science scheduled for publication 2004 pp 1 M Verheij and H Bartelink Radiation induced Apoptosis Cell Tissue Research Springer Verlag 2000 331 133 Advisory Committee on Human Radiation Experiments Final Report Department of Energy http tis eh doe gov ohre roadmap achre intro 9 5 html R K Sachs et al Radiation Produced Chromosome A berrations Colourful Clues Trends in Genetics 2000 pp 16 143 M Barcinski Apoptotic cell and phagocyte interplay recognition and consequences in different cell systems An Acad Bras Cienc March 2004 pp 94 M Andreeff et al Cell Proliferation Differentiation and Apoptosis Robert C Bast Jr et al editors Cancer Med
19. 12 DAQ_CLK DAQ CLK REQ Translator ACK Board 16X1 ROC DOUT Figure 3 System level diagram of the PTSM prototype 14 board memory of the ROC until it can be transferred to the DAQ When the DAQ is finished taking data it lowers the start line The ROC then stops taking data and sends the last of its data to the DAQ When the on board FIFO s are empty it then raises a done line which signals to the DAQ that there are no more data to be sent The ROC holds all data handling state machines in reset until the start line is raised again There is currently no external triggering The ROC sends all transition events channel comparators going low to high and then high to low to the DAQ as they occur There is an additional function built into the controller where the controller when signaled by the start line triggers the pulse generator 1 or 100 times It then reads out the resulting data This is used to calibrate the PMFE s analog gain and TOT gain 3The only dead time occurs in the PMFE and currently lasts for 5 ns see Section 3 2 2 for a discussion of the dead time For reasons that are explained in Section 3 2 2 a particle would have to deposit 1 25 fC or less at exactly the right moment in order not to be detected during this dead time The probability of this occurring is negligible 15 3 1 Silicon Strip Detector The silicon strip detector is the sensor in the PTSM When a particle traver
20. 126 sigma err 0 mu store fit fit arravliChannell MU err sigma sigma err fv thresh current thresh v thresh 1000 sprintf hlabel ch 4d v thresh 41 0f mV Q_inj 4 3f 4 3f fC noise 1 0f4 1 0f e gain 3 2f 3 2f mV fC iChannel fv thresh current thresh v thresh 1000 float ferf gt GetParameter 0 V_2_FC float ferf gt GetParError 0 V_2_FC noise noise_err gain gain_err h index gt SetTitle hlabel Int_t type 112 landscape TPostScript ps pslabel type ps Range 24 16 set x y of printed page c index gt Update ps CloseO for current_thresh printf n vo SKSKSK SR HE ak 3k 3K 3K SR SR K K R R R R R RK SK 3K 3K 3K OR SR 3K R SR 3K SR SR SR SR SR SR R R R R R R Rk R SK SK SK SK SK OR K K R SK K 2k 2k 2k 2k 2k FIT GAIN CURVES This function takes the fitted parameters of the s curves makes a graph for the noise and a graph for the gain for each channel between and including channel start and channel stop SKSKSK SR SR SR SR SR SR SR SR SR SR R K R R R R R R SR SK SK SK SK 3K SR OR 3K SK 3K SR SR SR SR SR SR R R R R R R R R R SK 3K 3K SK SR Ok SR HE K ok 2k 2k 2k K id fit gain curves channel fit x fit array channel stats x chan gain noise int iChannel Int t type 112 this is the type of ps file TGraph gain graph NUM CHANNELS TGraph x noise graph NUM CHANNE
21. 2k 2k 2k This section just pipelines the lock so that all the synchronous elements get plenty of clocks vith reset high kok kok kok kok kok kok RER SR SR kok AAAI I II I I R R kok k ka 2k a synthesis attribute uselowskewlines of timer is yes always posedge clk begin if dcm2locked timer lt 0 else timer lt amp timer timer timer 3 amp timer 2 0 timer 2 amp timer 1 0 timer 1 0 timer 0 end endmodule 88 B 2 Serial to Parallel Conversion paaa oao o E k k kk kkk kkk kkk kkk kkk kkk kkk k kk k kk k kk k kk k kk k ser 2 par v4 V ser 2 par reads out the DDR data lines from the PMFE For the data format refer to Scipp ucsc edu bkeeney ptsm files pmfe files data format ps Brian Keeney 6 1 04 bkeeney scipp ucsc edu Copyright 2004 University of California Santa Cruz Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 RK SR SSR SOR SR SR SR oko oko ke ke OR SR S 2K SR OR SR SR SOR SR 2k R R SR SR SK k SR kk kk kk kk kk k k k k ok k k k k k k k k k kk k kk k 2k a 2k kk k k Theory of peration 3k ak ak 3k SR 3K K R R R R R R K SK SK SK SK SR SR OR OR SR K SR SR SR SR SR SR tubu R R R R R R 3K 3K SK SK 3K A SR K SR OR OR SR SR SR SR SR R R k k k k k ok ok K K X X X o X X XX XX X X KF KF X KF X X
22. 4 pulse 100mv high ch 10 pulse 100mv high ch 15 pulse 100mv high ch 1 pulse 125mv lov ch 15 pulse 125mv lov ch 1 pulse 125mv high ch 15 pulse 125mv high 162 ch 1 det 125mv low ch 4 det 125mv low ch 1 det 125mm high ch 4 det 125mv high charge low charge high error bars Hh printf Data Set or Parameter n for i 0 i lt NUM_DATA_SETS 3 i printf data names i for j 0 j NUM DATA POINTS j printf 43 2f data set i j printf n printf nFit Results n n TCanvas c new TCanvas TGraphErrors x gi TF1 x pol new TF1 pol poli 0 MAX CHARGE for i 0 i lt NUM_DATA_SETS i gi new TGraphErrors NUM DATA POINTS charge picker il data setlil NULL error bars g1 5Drav As pol gt SetLineColor 2 pol gt SetLineWidth 2 gi gt Fit pol RQ gi gt GetYaxis gt SetTitle TOT us gi gt GetXaxis gt SetTitle Q fC strcpy file_name data names i 163 strcat file name ps TPostScript gain ps file name 112 gain ps Range 24 16 set x y of printed page sprintf fit results G 43 2f 23 2f Offset 3 2f 4 7 3 2f pol gt GetParameter 1 pol gt GetParError 1 pol gt GetParameter 0 pol gt GetParError 0 printf data nameslil printf t 18 26 413 21 48 2f 3 2f n pol oGetParameter 1 pol GetParError 1 pol oGetParameter 0 pol GetParErro
23. If the SM ever glitches into an undefined state it syncs up again in the init state It might seem strange that the DDR FFs are in the top level This makes it easier possible to pack them into the IOBs which makes them much faster Note that the timing here is VERY critical because we shift from 2 time domains posedge and negedge to one posedge Therefore care must be taken to make the tools understand how the setup and hold times must be constrained see ucf I could not find a single place in the whole xilinx site where it was done correctly their way won t even pass the parser This way might not be perfect but it seems to understand what we mean This is near the top on the list of things to ask a xilinx engineer R S R SR SK S R S K SR SR Xk SR SR S R SR kk 3 2k 2 kk 2k k kokk kk kk kk kk kk kk kk module ser 2 par v4 dout data ready din slow clk clk res frame output 63 0 dout output data ready input 15 0 din input slow clk clk res input 2 0 frame reg 2 0 timer reg 63 0 SR dout reg 7 0 S reg data ready slow follower start bit is for syncing wr fifo duh zero buf inserts 64 zeroes after good event synthesis attribute uselowskewlines of data ready is yes synthesis attribute uselowskewlines of S is yes synthesis attribute uselowskewlines of timer is yes 90 parameter 7 0 init 87b0000 0001 initi 87b0000 0010 sync 8 b0000 0100 gr
24. N16534 timing diagram 3 5 2 Readout Software Getting the data latched into the NI6534 is only half of the process of data acquisition Events are 40 bits wide in the ROC but the data bus is only 16 bits wide 32 bits total 16 are reserved for another FPGA This means that 3 packets need to be made from the one 40 bit event Using these error codes and knowledge of the packet structure University of California Santa Cruz physics undergraduate Jason Heimann wrote a C program which interfaces to the card The program PTSM CALIB uses National Instruments C libraries to initialize the NI6534 to initiate read operations by the card and to read the card s RAM The program then parses the file looking for There are 32 bits for the time seven bits for the address and one bit for the transition 42 error codes and reassembling the packets When an error code is found the current event that is being parsed is thrown out and the first word after the error code starts a new event It then turns this data into separate events for each channel that is active Finally using ROOT libraries 21 the data is stored with very high compression 430 into an NTuple This NTuple is then easily transported and analyzed on other machines For the source code to PTSM CALIB see appendix E 3 6 The PTSM Translator Board One drawback to using the NI6534 is that it cannot interface with LVDS logic levels A translator card was designed to ma
25. O qpl91 OB qn 91 OBUFDS bufiO I dout 10 O qp 10 OB qn 101 OBUFDS bufii I dout 11 1 O qp 11 OB qn 111 OBUFDS buf12 1 dout1121 O qp 12 0B qn 121 OBUFDS bufi3 I dout 13 O qpl13 OB qn 131 OBUFDS bufi4 I dout 14 O qp 14 0B qn 141 OBUFDS buf15 1 dout1151 O qp 15 OB an 151 endmodule 83 B 1 Clock Tree k kkk kkk kkk kkk kkk kkk kkk k kk k kk kkk kkk k kk k x CLK TREE V Brian Keeney 6 1 04 bkeeney scipp ucsc edu Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 SRSRR SR SR SR SR SR SR R R R R R KR SK SK SK SK SR SR SR 3K SK K 3K SR SR SR SR SR tubu RK R R R R OS SK SK A 3K SR K SR OR OR SR SR SR K K 21 k k k k k Copyright 2004 University of California Santa Cruz DRO ok kok kk ok kokk kokk kk kk kk kk kk kkk clk_tree v This module creates all of the required clocks for the design Brian Keenev and Gavin Nesom 3 4 04 EAA AAA Kok Kok Kok KOK KOK KOK KOK Kok KOK KOK KOK KOK Kok KOK KKK kk kok AI a ok kok kok a 2k a 2k timescale ins 1ps module clk tree fe clk clk data slow clk slow clk bufg clk in clk res out res input clk in res output clk data fe clk slow clk slow clk bufg clk output res out reg up down reg 3 0 timer assign gnd 0 wire dcmOlocked dcmilocked dcm2locked div5 wire res 4 0
26. Read out Controller This section describes the process by which 64 channel statuses are mapped to specific time slices over 4 clock cycles and multiplexed onto 8 signal lines Figure 7 System level timing diagram for the PMFE The FDR s are D flip flops with resets and the M2 s are two input multiplexers see Glossary B CLK defines the bus cycle which is 5 clocks long The data is transferred over eight differential signal pairs1D7 D0 only the first DO is shown The channel numbers which are transferred over D are indicated The channels for D1 are 14 15 12 13 10 11 8 9 D2 D1 8 etc Front End Latches The output of the shaper is fed to a comparator with a thresh old voltage A rising edge from the comparator feeds to the input of an asynchronous set reset SR latch In one chip there are 64 front end amplifiers 64 comparators and 64 SR latches At a specific time in the bus cycle a bus cycle consists of five clock cycles and begins with a B CLK on the front end chip the statuses of all latches are checked and then reset The frequency of this operation determines the quantization and thus the precision on TOT The TOT is defined as the number of B CLK s for which a given channel is high 22 Parallel to Serial Data Conversion One approach to transferring the channel information to the outside world would be to have signal pair for each channel This would work but it would make the size of the ch
27. SR SR SR SR SR R K R R R OS S SK SK SK SK SR SR SR R SR 3K SR SR SR SR SR SR R R R R R R RK RK SK SK SK SK K K I I I SK SR SR SR SR 2k 2k 2k 2k CHAN SERVER V this module monitors a group of four channels chan stat holds the previous status of the channel If there is a difference between chan stat and din for that chanel a fifo write strobe will go high for that channel and the timestamp will be written to the fifo along with the status bit up or down and the channel It is critical that chan server be started at the right time so that it has valid data for all four processing states This is currently assured by data ready from ser 2 par Brian Keeney 6 7 04 XX x X Copyright 2004 Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 akk SK SR SR SR SR SR SR SR SR SR SR SR SR R R R R R R R S SK SK SK SR 3K SR OR R SR 3K SR SR SR SR SR SR R R R R R R 3K 3K 3K SK SK SK SK SR OR HE 2k 2k 2k K module chan server dout some many fifo full din data ready rd fifo ur fifo tyme clk res output 139 01 dout output some many fifo full vr fifo input 31 0 tyme time with an i is a token input 3 0 din input data ready clk res rd fifo reg 3 0 chan stat onehot channel encoding of status up or down reg 5 0 S reg 1 0 chan this is the channel to write to the fifo reg updown wr fifo res fifo
28. SetLineColor 2 polo gt SetLineWidth 2 s_gauss gt g_gain gt Fit pol RQ final gain pol gt GetParameter 1 sprintf ps label gain curves ch d gain ps s_gauss gt channel TPostScript gain ps ps label 112 sprintf ps label TOT Gain Curve for Channel d The average gain is 43 2f 23 2f s_gauss gt channel pol gt GetParameter 1 pol gt GetParError 1 s_gauss gt g_gain gt SetTitle ps_label gain_ps Range 24 16 set x y of printed page s_gauss gt c_gain gt Update gain ps CloseO 140 Do the same for the resolution measurement s_gauss gt c_res new TCanvas s_gauss gt g_res new TGraphErrors s_pulse gt num_pulses S pulse q inj S gauss gauss sig NULL s gauss 2gauss sig err s_gauss gt g_res gt GetYaxis gt SetTitle TOT STD DEV uS s_gauss gt g_res gt GetXaxis gt SetTitle Q Injected fC s gauss 2g res Draw Ax s_gauss gt g_res gt Fit polo RQ MIN CHARGE MAX CHARGE final res polo gt GetParameter 0 sprintf ps label T T Gain Resolution Curve for Channel d The average resolution is 3 2f 7 3 2f uS s_gauss gt channel polo oGetParameter 0 polo oGetParError 0 s gauss 2g res oSetTitle ps label sprintf ps label res curves ch d res ps s gauss channel TPostScript res ps ps 1abel 112 res ps Range 24 16 set x y of printed page s_gauss gt c_res gt Update res_ps Close
29. else if v_pulse fold_v_pulse fv_thresh iv_thresh_count 1 n_bins fold_v_pulse v_pulse for iEvents ptsmout GetEntry iEvent 1 fv thresh iv thresh count 1 q stop v pulse set delta fv thresh iv thresh count 1 return iv thresh count void print struct thresh bin bin 1 float v thresh bin gt v_thresh float q start bin 2q start float q stop bin gt q_stop int n bins bin 7n bins printf vthr 44 3f qstrt 4 3f qstp 4 3f nbins d n v thresh q start q stop n bins print struct memory cleanup G scratch all void store fit channel fit x fit arrav float mu float mu err float sigma float sigma err float thresh fit_array gt mulfit_array gt n_points mu fit array omu err fit array on points mu err fit array osigmalfit array on points sigma fit array osigma err fit array n points sigma err fit array othreshlfit arrav 2n points thresh 121 fit_array gt n_points store_fit void init fit array channel fit fit array int num thresh int num channels int i for i 0 i lt num_channels i fit_array i mu float calloc num_thresh sizeof float fit array i mu err float calloc num thresh sizeof float fit arraylil sigma float x calloc num thresh sizeof float fit arraylil sigma err float x calloc num thresh sizeof float fit array i thresh float calloc num thresh sizeof float
30. iStatus DIG Grp Config iHSDevice iHSGroup iHSGroupSize iHSPort iDirIn iRetVal NIDAQErrorHandler iStatus HSDIG Grp Config ilgnoreWarning Configure handshaking parameters for burst mode handshaking iStatus DIG Grp Mode iHSDevice iHSGroup iSignal iEdge iReqPol iAckPol iAckDelayTime iRetVal NIDAQErrorHandler iStatus HSDIG Grp Mode ilgnoreWarning Setup the device for External PClock iStatus Set DAQ Device Info iHSDevice ND CLOCK REVERSE MODE GR1 ND ON iRetVal NIDAQErrorHandler iStatus Set HSDAQ Device Info ilgnoreWarning void init daq kokk kok kok kokk kok ok kk kk kk kk kk kkk k x read data initiates an asvnchronous read operationx K R kok kk R R kokk kk kok kokk kok k kkk kk kkk void read data i16x iStatus i16 iRetVal i16 piBuffer u32x ulCount 1 iStatus DIG Block In iHSDevice iHSGroup piBuffer ulCount iRetVal NIDAQErrorHandler iStatus HSDIG Block In ilgnoreWarning void read data void halt read ii6 iStatus i16 iRetVal u32 ulRemaining find out how many words were read during the block read iStatus DIG Block Check iHSDevice iHSGroup ulRemaining iRetVal NIDAQErrorHandler iStatus HSDIG Block Check ilgnoreWarning 151 if we haven t read out a full block terminate the read operation if ulRemaining 0 1 iStatus DIG Block Clear iHSDevice iHSGroup iRetVal N
31. noise values for a range of thresholds 95 offset and their respective uncertainties In an ideal system the noise slope would be 0 since it should be independent of input charge The gain offset would also ideally be 0 but a nonzero value does not adversely affect performance Finally Gain v2 creates 2 T Graph objects one for the chip gain and one for the chip noise The error bars are the fitted uncertainties At each step Gain v2 saves copies of the histograms and graphs for later viewing in case one of the channels shows strange behavior 4 1 4 Interpretation of Results The first analysis of the data is in the fitting of the s curves A typical s curve is shown in Fig 19 Overall the fits were quite good with occasional fitting errors Occupancy E o e o B o S o i e o e a Figure 19 Example of an s curve from channel 42 These errors did not significantly affect the quality of the overall results Lines were fit to the sets of s curves to find the average gain for small signals An example of a typical gain curve can be found in Fig 20 The gain curves and associated errors are plotted in Fig 21 56 The noise was also computed for the channels A typical noise curve for one channel is shown below in Fig 22 for channel 43 The noise for the entire chip is shown in Fig 23 The noise is 616 24 electrons When repeating these tests for the Test Board w
32. s curves See Appendix C for the complete source code Incorrectly binning the data results in 54 non physical spikes giving a picket fence appearance to a physically smooth dataset e g 2 voltage steps could be in one bin and none in the following bin Gain v2 then initializes several structures to aid in passing the many s curves to different functions The s curves are then fit to error functions and the mean mean error standard deviation and standard deviation errors are stored in an array one for each channel of structures of arrays one for each fitted parameter Coding in this style prevents the passing of any actual values to various subroutines Instead addresses to the data structures are passed greatly reducing the total time of computation After the s curves have been fit Gain v2 makes two TGraph objects for each channel one for noise one for gain and plots the fitted parameters as a function of input charge using the fit uncertainties as error bars It then fits lines to each of these graphs and stores them in different arrays in a new structure These parameters again as a function of input charge are the noise the noise slope the gain the gain Ch 43 Noise 651 04 28 4 e Slope 4 2 17 9 740 o 2 8 720 700 680 660 a R o D o a e o e o o o eo A i A o Charge Input fC Figure 18 Typical
33. s trigger signal the comparator output was averaged 128 times The result of this averaging can be seen in Fig 24 The TOT was measured with the cursor function on the oscilloscope between the 50 96 points of the rising and falling edges Two ranges of charge were studied 1 56 15 63 fC hereafter referred to as low range and 6 25 62 5 fC hereafter referred to as high range An example TOT gain curve can be seen in Fig 25 Both ranges were swept in ten steps The error of the measurements is estimated to be 10 ns based 61 upon repeated measurements of a single waveform Both the detector mounted and unmounted configurations of the Test Board were characterized by this method After having characterized the analog output of the comparators the full PTSM DAQ was used to characterize the TOT gain The TOT gain was measured by the DAQ in one trial at 125 mV for the range of 6 25 62 5 fC and at 100 mV for the range of 5 2 75 fC using the Test Board with no detector mounted PTSM_CALIB was used to sweep the charge range in ten steps One thousand pulses were injected at each charge step 4 2 2 Statistical Analysis The characterization of the TOT using the averaging function on the oscilloscope yielded several measurements of the average TOT for two ranges of charge These Figure 24 A typical oscilloscope display of the averaged comparator response to an input charge 62 Board V Thresh Q 1 15
34. to convey information A bit is either TRUE 1 or FALSE 0 bus a group of signals that are logically associated It is common to call the first signal bus 0 the second signal bus 1 etc byte two nibbles or eight bits binary Notation The binary number system uses 2 as a base instead of 10 A binary number 1010 stands for 1 2 0 x 22 1 x 21 0 x 20 1010 differential A signal which travels on two wires One signal is the complement on the other They do not need to have a ground reference double data rate DDR Data is latched on both the rising and falling edge of the clock Twice the normal amount of data is transferred for a given clock rate thus the name event In the context of PTSM an event occurs when a comparator output transi tions either from low to high or high to low flip flop A flip flop is based on the most fundamental unit of memory the latch The simplest flip flop has two inputs clock and D and one output Q When the clock input rises from 0 to 1 the flip flop assigns the input to the output and keeps the output at that value until the next rising edge of the clock hexadecimal Notation Hexadecimal notation represents a nibble as a number from 0 15 as 0 9 and A F For example 10102 1010 A16 latch A latch is the most fundamental unit of memory The most important dif ference between a latch and a flip flop is that a latch is asynchronous while a flip flop is synchronous An SR lat
35. were undertaken The prototype SSD is an ATLAS single sided Test detector with 50 um pitch and is six cm long The PMFE was designed to interface on one side with the SSD and on the other to be bonded to traces on a printed circuit board called the Test Board The Test Board is designed to provide services e g biasing and calibration signals to the SSD and PMFE and to interface with the Readout Controller ROC The ROC is implemented on a Xilinx Virtex II XC2V1000 FG256 Field Programmable Gate Array FPGA The FPGA is mounted on a Xilinx Virtex 2 FG256 Proto Board The Test Board mounts directly on the prototyping board through arrays of stake headers The ROC interfaces though twisted pair ribbon cable to a translator board which converts the data signals from LVDS to CMOS The Translator Board then connects to a PCI based DAQ card the National Instruments 6534 in a PC This section discusses the methods used in implementing the detector front end readout controller and DAQ of the PTSM and will explain the motivation for choosing these methods Before discussing the details of how the prototype readout system is implemented it helps to understand the theory of operation of PTSM See Fig 3 for a system level diagram of the prototype readout system The proton beam at LLUMC has a very well defined spill structure with 100 protons spaced evenly over several hundred milliseconds in an area of 100 cm These spills occur ever
36. 1 1 5 2 25 3 3 5 4 Charge Figure 15 Average response of a comparator with Gaussian noise superimposed on the input charge 90 at 0 and approaching 1 at high charge inputs This process was performed for 15 thresholds between 60 and 210 millivolts or between 63 and 2 2 fC 4 1 1 Experimental Method In order to find the gain and noise of the PMFE an automated method of control ling threshold voltage and charge injection is needed to gain statistical results The threshold is set by an AMREL programmable power supply via GPIB It is updated by the data acquisition software PTSM_CALIB as it takes data See appendix E for the complete source code A pulse generator also controlled by the DAQ through GPIB but triggered by the ROC pulses input capacitors on the chip with a voltage step Since Q CV the charge injected into the amplifier is simply the product of the calibration capacitance and the pulse amplitude The pulse is long enough that the full C V amount of charge is fully measured The DAQ software steps through a set of pulse amplitudes for a given threshold and records the digital output from the ROC via the NI6534 PTSM_CALIB parses the output from the ROC looking for error codes and assembling the packets into full events The events are then written to a ROOT NTuple for later analysis Once the data are collected the s curves are fit to error functions and the related Gaussian means standard deviations and t
37. 1 A TO 4 3 Radiation Source Measurement The final test performed in the characterization of the prototype readout system of the PTSM was to place a Test Board with a detector mounted on it in the presence of a radiation source Strontium 90 has two f spectra one at 546 MeV and one at 2 283 MeV 26 In the first trial an uncollimated 100 uCi 9 Sr source was placed within 1 cm of the detector Data was taken for one minute The intensity map is shown in Fig 34 The combined TOT spectrum for all channels is plotted in Fig 35 For the second trial a 1 cm X 50 um collimator was used to collimate the source Data was then taken for 30 minutes The slit was aligned by trial and error along the major axis of the strips in the center of the active area Because the rotational angle of the slit is ill defined little quantitative information about the beam can be determined from the intensity map Fig 36 although it is likely that the dominant causes of the width are multiple scattering and beam divergence Nonetheless it is reassuring that a very well defined peak is present in the center of the chip The TOT spectrum Fig 37 matches the spectrum obtained in the previous trial No software has been developed to combine events where charge was shared between strips Because of this there are many TOT events in the spectrum which show half or less of the actual amount of charge deposited For example if a particle hit between two strips and shar
38. 2 1 it kon M2_1 FDR m e M o a 5 o b a LI va i EDR M2 1 FDR M2 1 a E ce Le R T 5 M LT on oc ims gax Figure 8 Schematic of the digital region of the PMFE An identical block handles the odd channels for the data line The two are multiplexed by the fast clock at the multiplexer furthest to the right 24 after the reset falls 5 ns at 50 MHz the latch will go high as it should and the event will be recorded If the comparator goes high and then low where the peak of the pulse just grazes the threshold voltage during this brief window the event will not be recorded At a gain of 120 T and a threshold of 120 mV this would correspond to a signal which is highly unlikely for a legitimate particle 26 Proper Acquisition of Data From the PMFE When transferring data it is important that the data is valid during a clock edge If the data is changing while the clock is changing the value latched by the readout controller will be either the data from before or after the transition but it will be impossible to know which See figure 9 The time during which the data must be stable before the rising edge of the clock is called the setup time and the time after the rising edge is called the hold time 17 Since data is being transferred at DDR it is especially important that the setup T Setup T Hold CLK D Qo Figure 9 Timing diagram of setup and hold requirements D is the input
39. 26 7 7 9 0 10 3 11 8 13 45 14 9 16 5 float ch 15 pulse 100mv low 10 11 96 2 58 3 12 3 62 4 06 4 5 4 84 5 28 5 58 5 92 float ch 15 pulse 100mv high 10 3 52 5 18 6 5 7 65 8 75 9 85 11 2 12 5 13 85 15 2 float ch 10 pulse 100mv low 10 2 62 3 22 3 7 4 22 4 74 5 2 5 52 5 94 6 34 6 64 float ch_10_pulse_100mv_high 10 4 35 5 95 7 35 8 55 9 80 11 15 12 65 14 1 15 6 17 05 float ch 1 pulse 100mv low 10 1 26 855 1 47 2 2 52 3 08 3 54 3 94 4 34 4 78 float ch 1 pulse 100mv high 10 2 04 3 96 5 25 6 55 7 65 8 8 10 11 2 12 5 13 9 12 6 float ch_1_pulse_125mv_low 10 115 77 1 47 1 92 2 44 2 96 3 43 3 88 4 32 4 68 float ch_1_pulse_125mv_high 10 1 82 3 76 5 3 6 5 7 15 8 8 9 95 11 15 12 45 13 85 float ch_15_pulse_125mv_low 10 2 04 2 64 3 2 3 66 4 12 4 56 4 88 5 38 5 58 5 96 float ch_15_pulse_125mv_high 10 3 54 5 14 6 4 7 58 8 7 9 8 10 95 12 25 13 55 14 96 7 d3et setv float ch 4 det 125mv low 10 11 46 2 08 2 74 3 36 4 02 4 64 5 16 5 64 6 02 6 5 160 float ch 4 det 125mv high 10 3 3 5 66 7 05 8 4 9 45 10 4 11 45 12 45 13 55 14 7 float ch 1 det 125mv low 10 1 32 2 5 3 6 4 38 5 2 5 84 6 42 6 8 7 3 7 65 float ch 1 det 125mv high 10
40. 30 40 50 60 Channel o2 Figure 36 Intensity map for data taken with the collimated Sr source Note that channels 0 and 63 were poorly behaved and so they were cut from the histogram There are two dead strips channels 6 and 15 TOT distribution for 90 SR Beta Spectrum Mu 0 59 0 01 us Sigma 0 17 0 00 us 2 32200 2000 1800 1600 1400 1200 1000 800 600 400 200 le ua v xu Du s sos Los 5 10 15 20 25 TOT 1 us o Figure 37 TOT spectrum for the collimated 9 Sr source measurement 73 substituted into the linear approximation for the TOT gain at low charge TOT AG A ro Bus 30 Where A is the TOT gain 7 45 and B 13us is the TOT offset TOT B g A 31 The mean charge deposited by the Sr B source is 1 fC It is reasonable to assume that the mean of the TOT distribution occurs at the energy where electrons are just stopped because of the nature of the Bethe Bloch relation 26 This energy can be found by consulting electron range tables in 28 The range is given in 4 The density of silicon is 2 3 7 29 Given that the detector is 300 um thick the range is range pl 2 3 x 03 0692 32 cm The energy corresponding to an electron just being stopped in the silicon is 225 keV 28 Using aforementioned constants the charge deposited is Exinetic 1 602 107 V 3 62 af e Q aeposited
41. 32 40 48 56 11 19 27 35 43 51 59 10 18 26 34 42 50 58 13 21 29 37 45 53 61 12 20 28 36 44 52 60 15 23 31 39 47 55 63 14 22 30 38 46 54 62 157 R K R K R K S R K R SR SR SR SR R S R SR R OR S R R R k R SR S R R k R SR SSR SR R SR k kok ok k k kk kk kkk k Constants for NI hardware R R kok kk R R k K R k R R R R k R R SR R R k R R R SR RR SR R R R SR R R SR R k ok ok kk kkk These are used for the NI cards iHS correspond to the NI 6534 High Speed Digital IO card iDAC correspond to the NI 6703 Analog Digial ID card const i16 iHSDevice 1 const i16 iDACDevice 2 const 116 iHSGroup const i16 iHSGroupSize const i16 iDACGroup const i16 iDACGroupSize const i16 iHSPort const i16 iDACPort const i16 iDirIn const i16 iDirOut const i16 iLineStart 7 const i16 iLineDone 6 const i16 iLineReset 4 const 116 iSignal const i16 iEdge const i16 iReqPol m const i16 iAckPol const i16 iAckDelayTime const 116 ilgnoreWarning const i16 iDacDevNum const i16 iDacThreshChan const i16 iPulserBrdIndex const i16 iPulserPrimAdd const i16 iPulserSecAdd const i16 iThreshPrimAdd 2 const i16 iThreshSecAdd 0 ve ve ve we ve ve me Hm we we nn O N o w we 158 F COMP GAIN Source Code JP SK SR SK SR SR SR SR SR SR SR SR K R
42. 5 04 jheimann scipp ucsc edu Copyright 2004 University of California Santa Cruz Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 kok kokk kokk SSR SR SR SR RK SOR S K SOR SR SR SOR SR OK SR k SR R SR SK SK S kk kk kk ok k k k k k kk kk k k k k k k k k module pulse handler done trig res fifos start some flag pulse jumper cal jumper ctrlr idle fast or res clk output done trig res fifos input start pulse jumper cal jumper fast or some flag ctrlr idle res clk reg done res fifos trig reg 6 0 S reg 6 0 cnt reg 1 0 wakeup timer reg 2 0 idle_settle reg 3 0 rad settle reg 11 0 trig delay 94 parameter 6 0 cnt limit 7 h63 this is 99 decimal parameter 6 0 init 7 b 0000001 send_pulse 7 b 0000010 wait_for_idle 7 b 0000100 inc pulse counter 7 b 0001000 pulse finish 7 b 0010000 radiation test 7 b 0100000 radiation finish 7 b 1000000 always posedge clk begin if res begin cnt wakeup timer done trig trig delay idle settle rad settle lt 0 res fifos lt 1 bi S lt init end else begin case S init begin was done lt 1 b0 now only drop done if start is high or we are doing calib if start cal jumper done lt 1 b0 if start res_fifos lt 1 b0 wakeup_timer lt start f wakeup timer wakeup_timer 0 2 b0
43. 534 Although the overall system design is trivial one chip does the entire conversion keeping the interference from the CMOS from adversely affecting the ROC and PMFE is slightly more difficult A4 The basic conversion between LVDS and CMOS was accomplished with three National Semiconductor ICs The DS90C031 is a quad CMOS to LVDS chip that uses a single 5V supply 23 It is used for sending the ACK signal to the ROC The DS90C032 is an LVDS to CMOS converter that is used to send the 16 data lines and REQ signal to the NI6534 24 The DS90C401 is a bidirectional LVDS driver which is used to supply the clock 25 At the time of the layout it was unclear whether it was better to use the NI6534 clock or one supplied by the ROC so flexibility was added in In order to reject common mode noise from the CMOS lines two strategies were used Pulse T8008 common mode chokes were used to isolate all LVDS signals A common mode choke is a coil with two different windings When a truly differential signal is passed the B fields null and there is no back EMF When there is a common mode signal the inductance of the choke presents a high impedance The second strategy was to split the ground plane between the input and output section of the chokes so that all CMOS was referenced to one ground and all LVDS to another The grounds were then tied at one point in the circuit Standard IC bypassing techniques were used on the five volt line supplied by
44. 6 26 7 70 9 00 10 30 11 80 13 45 14 90 16 50 ch 10 pulse 100mv high 4 35 5 95 7 35 8 55 9 80 11 15 12 65 14 10 15 60 17 05 ch 15 pulse 100mv high 3 52 5 18 6 50 7 65 8 75 9 85 11 20 12 50 13 85 15 20 ch 1 pulse 125mv low 0 12 0 77 1 47 1 92 2 44 2 96 3 43 3 88 4 32 4 68 ch 15 pulse 125mv low 2 04 2 64 3 20 3 66 4 12 4 56 4 88 5 38 5 58 5 96 ch 1 pulse 125mv high 1 82 3 76 5 30 6 50 7 15 8 80 9 95 11 15 12 45 13 85 ch 15 pulse 125mv high 3 54 5 14 6 40 7 58 8 70 9 80 10 95 12 25 13 55 14 96 ch 1 det 125mv low 1 32 2 50 3 60 4 38 5 20 5 84 6 42 6 80 7 30 7 65 ch_4_det_125mv_low 1 46 2 08 2 74 3 36 4 02 4 64 5 16 5 64 6 02 6 50 ch 1 det 125mm high 4 16 6 66 8 30 9 65 10 75 12 05 13 20 14 65 16 15 18 00 ch 4 det 125mv high 3 30 5 66 7 05 8 40 9 45 10 40 11 45 12 45 13 55 14 70 charge low 1 56 3 12 4 68 6 24 7 80 9 36 10 92 12 48 14 04 15 60 charge high 6 25 12 50 18 75 25 00 31 25 37 50 43 75 50 00 56 25 62 50 error bars 0 01 0 01 0 01 0 01 0 01 0 01 0 01 0 01 0 01 0 01 Fit Results ch_1_pulse_100mv_low 0 32 4 0 00 0 08 4 0 01 166 ch 4 pulse 100mv low 0 37 0 00 0 13 4 0 01 ch 10 pulse 100mv low 0 29 0 00 2 36 0 01 ch 15 pulse 100mv low 0 28 0 00 1 76 0 01 ch 1 pulse 100mv high 0 20 0 00 1 26 4 0 01 ch 4 pulse 100mv high 0 24 0 00 1 46 4 0 01 ch 10 pulse 100mv high 0 22 0 00 3 01 0 00 ch 15 pulse 100mv high 0 20 0 00 2 50 0 01 ch 1 pulse 125mv low 0 32
45. 9 0 dO di d2 d3 d4 d5 d6 d7 48 49 410 411 412 413 414 415 input num_fifo 1 0 many some input clk res bf rd wire many flag many wire bf rd bf full bf empty bf stands for big fifo reg 39 0 mux out reg empty bit wr main fifo reg 2 0 S reg num fifo bits 1 0 ch count reg num fifo 1 0 rd ch fifo 109 assign big_wr wr_main_fifo parameter 2 0 home 3 b001 read 3 b010 write_fifo 3 b100 synthesis attribute uselowskewlines of S is yes big_fifo big_fifo Clk clk sinit res din mux_out wr en wr main fifo rd en bf rd dout dout full bf full empty bf empty mux to switch between the little fifos and the main fifo always d0 or di or d2 or d3 or 44 or d5 or d6 or d7 or d8 or d9 or d10 or dii or d12 or 413 or 414 or 415 or ch count begin case ch count 4 h0 mux out d0 4 h1 mux out di 4 h2 mux out d2 4 h3 mux out d3 4 h4 mux out d4 4 h5 mux out d5 4 h6 mux out 46 4 h7 mux out d7 4 h8 mux out d8 4 h9 mux out d9 4 ha mux out d10 4 hb mux out dil 4 hc mux out d12 4 hd mux out d13 4 he mux out d14 4 hf mux out did endcase end 110 always posedge clk begin if res begin empty_bit rd_ch_fifo ch_count wr_main_fifo lt 0 S lt home end else begin case S home begin wr_main_fifo lt 1 b0 empty bitcemanylch cou
46. Data Handler Channel Server FIFO Server Output Controller B PTSM Readout Controller Verilog Source Code Gain v2 Source Code C 1 Gain v2 Include File TOT Gain Source Code D 1 TOT Gain Include File PTSM CALIB Source Code E l PTSM CALIB Include File E 2 PTSM CALIB Constants COMP GAIN Source Code 1 GAIN Output V 48 48 51 53 54 56 60 61 62 63 68 71 75 76 77 117 119 132 135 144 147 157 159 Bibliography 168 List of Figures 1 oe W bd 10 11 Schematic diagram of ghosting The two legitimate events are indis tinguishable from the two that are nonexistent When measuring the charge deposited by the tracks in a double sided detector it is usu ally possible to correlate the two X and Y measurements such that the ghosts can be removed Schematic diagram of the PTSM detector geometry System level diagram of the PTSM prototype Schematic array of silicon strips on a Detector Charge in a detector I is the current from the detector while the charge is being collected V is the voltage at the input of the amplifier The voltage rises with increasing charge and slowly decays Here the time scale is logarithmic The duration of I is typically 25 ns while the duration of V is much longer and depends on RampCamp det Schematic of charge sensitive amplifier System level timin
47. Gain Map Noise Z 4 23 2f chip noise f chip noise err f chip noise PSetTitle label chip_noise gt GetYaxis gt SetTitle Noise e chip_noise gt GetXaxis gt SetTitle Channel ID chip_noise gt Draw AB TPostScript chip_noise_ps chip_noise ps 112 chip_noise_ps Range 24 16 c_noise gt Update chip_noise_ps Close 131 D TOT Gain Source Code DOERR AAA 3k k 3K K aK K aK aK aK kk kk 3K 3K 3K K K I I I Ik K K 2k 2k 2k 2k 2k TOT_GAIN_V1 Program to analyze TOT Gain of PMFE Brian Keeney 6 2004 SRRSRSRSRSRSR SR R K R R R R R R SK SK SK SK SK SR OR SR OR DO R R R R R R R SK SK SK SK K SR K SR OR OR SR SR SR SR SR k k k k k k k k k const int MAX NUM THRESH 100 const float Y_SCALE 1 100 const float V_2_FC float 3 237 const float DELTA 0 001 fudge factor due to float imprecision const int NUM CHANNELS 100 const int REAL NUM CHANNELS 64 const int MAX NUM PULSE BINS 200 which threshold do you want to examine const float V THRESH COMPARE 10 const float TOT QUANTUM 1 TOT sampling period in microseconds const int MAX TOT 200 const float MIN CHARGE 1 fC const float MAX CHARGE 20 fC include TFile h include TROOT h include TTree h include TBranch h include TH1 h include TProfile h include TNtuple h include lt stdio h gt include lt stdlib h gt include TMat
48. IDAQErrorHandler iStatus HSDIG Block Clear ilgnoreWarning p void cleanup read kok kokk kk kokk kk kokk kokk kokk ok kk ok kok kk kokk kok kokk kok kokk kokk kok kokk Kokk x int Parse data takes a filled data buffer and parses it into events kok kokk kokk R R R kokk kok kokk kok kokk kk kk ok kokk kok kokk Kokk SR R R SR Kok kk kk kk int parse data ii6 piBuffer u32 ulRemaining u32 ulCount int iEvent float v thresh float v pulse TNtuple ptsmout FILE f 1 float ftot O f float event id iEvent float bin O f int ibin 0 int iWords int i j int b unsigned long tempstamp 0 short tempstate timestampll holds the last timestamp read in from a channel event each element in the timestamp array corresponds to one channel unsigned long timestamp NUM CHANNELS state 1 if no state information is available 0 if the channel is known low 1 if the channel is known high short state NUM CHANNELS for i 0 i NUM CHANNELS state i 1 timestamplil 0 i iWords is set at 1 to prevent the analysis of any 152 events without first reading in a start or error code iWords 1 bin 200 is filled if no words were read at all printf Aul words read n ulCount ulRemaining if ulRemaining ulCount 1 bin 200 ptsmout gt Fill event id bin ftot v pulse v thresh else for i 0 i
49. K 3K K K aK aK aK aK 2K II K 3K K K aK K aK 2K 2K K 2K 2K 3K ACA 3K 3K A K K I K K K 21 21 K 21 24 21 2 2 3K 3K 2K K 2K const int MAX_NUM_THRESH 100 const float Y_SCALE 1 500 Scale by number of PULSES const float NUM PULSES 500 g what does a 1 volt pulse correspond to in fC const float V 2 FC 50 01131148 const float DELTA 0 001 fudge factor due to float imprecision const int NUM CHANNELS 100 const float GAIN MAX 120 when a fit on charge or sig charge is gt it const float CHARGE CUT 20 include TFile h include TROOT h include TTree h include TBranch h include TH1 h include TProfile h include TNtuple h include lt stdio h gt include lt stdlib h gt include TMath h include TF1 h include TCanvas h include TGraph h include TGraphErrors h include TPostScript h include gain v2 include cxx include math h int main 1 Structures thresh bin fv thresh MAX NUM THRESH channel stats chan gain noise 117 Stuff long nEvents int iv thresh count 0 int cal bus channels iChannel char fname 128 channel fit fit array NUM CHANNELS init fit array fit array MAX NUM THRESH NUM CHANNELS init chan gain noise chan gain noise for cal bus 0 cal_bus lt 4 cal_bus cal0 is 8 15 40 47 call is 0 7 32 39 cal2 is 24 31 56 63 cal3 is 16 23 48 55 sprintf fname ptsm d
50. LS TCanvas gain canvas NUM CHANNELS TCanvas noise canvas NUM CHANNELS char pslabel 128 char gr title 128 printf fitting gain and noise curves to fflush 0 127 if iChannel gt 9 printf b printf b d iChannel fflush 0 TF1 fgain new TF1 fgain O 1 x 001 9 99 TF1 fnoise new TFi fnoise O 1 x 001 9 99 GAIN SECTION gain canvas iChannel new TCanvas print fit array amp fit arravliChannell if fit arravliChannell n points gain graph iChannel new TGraphErrors fit array iChannel n points fit array iChannel mu fit array iChannel thresh fit array iChannel mu err NULL gain_graph iChannel gt GetXaxis gt SetTitle Q_inj fC gain_graph iChannel gt GetYaxis gt SetTitle V_thresh mV gain_graphliChannel gt GetYaxis gt CenterTitle gain_graph iChannel gt GetXaxis gt CenterTitle gain_graph iChannel gt GetXaxis gt SetTitle 50 Point fC gain_graphliChannel gt GetYaxis gt SetTitle Threshold mV gain graphliChannell PDrawC Ax fgain gt SetParameters 20 100 gain_graph iChannel gt Fit fgain Q set_title_array gr_title fgain iChannel 1 gain_graphliChannel gt SetTitle gr_title sprintf pslabel gain curves gain ch 4 iChannel TPostScript gain ps pslabel type gain ps Range 24 16 set x y of printed page gain canvas LiChannell PUpdate gain ps Close
51. OV use 28 The error on the noise is Qnoise OOoy 29 pulse VVhere d the error on the standard deviation of the s curve These points are collected for each channel for a range of thresholds These points are then plotted for each channel In the case of gain the y axis is threshold and the x axis is charge The slope of the line intersecting the points is the average number of millivolts generated per femtoCoulomb of input charge which is defined as the gain The typical gain for charge amplifiers designed by SCIPP is about 100 mV fC The specified gain of the PMFE is 120 mV fC In the case of the noise it is convenient to plot noise on the y axis and threshold on the x axis See Fig 18 The line should have no slope because the noise should be independent of gain The y intercept is then the noise This process is repeated for the remaining calibration buses and a chip map of gain and noise can be produced 4 1 3 Computation This section describes how the analysis of the analog gain and noise was accomplished using C programs which called precompiled analysis routines in the ROOT library 21 The ROOT Object Oriented Analysis Framework was developed by physicists at CERN to analyze particle physics data sets Custom C code using ROOT libraries was compiled using GCC 3 2 2 under Redhat Linux 9 0 for the purpose of determining the gain and noise The program Gain v2 first determines the correct binning for all of the
52. Q is the output and CLK is the clock and hold times are obeyed Failure to latch the data correctly means that channel identities will be mis matched which is disastrous for this instrument 25 3 3 The PTSM Test Board The Test Board provides several services to the PMFE and detector if one is be ing used It provides a low noise threshold voltage It also has some rudimentary logic to control how calibration pulses are routed to the PMFE It has several filters which condition power signals being brought to the PMFE and provides a durable mechanical test platform for several different types of experimentation Comparator Threshold Voltage The comparator threshold in the PMFE is set by an American Reliance Programmable Power Supply via GPIB It has accuracy to 1 mV The signal is transported via RG 58 cable to an SMB connector on the Test Board where it is processed further by an AD620 instrumentation amp and low pass filter to reduce errors in the voltage Calibration Control The calibration pulse is transmitted via RG 58 cable from a LeCroy 4145 to an SMB connector on the Test Board There it is terminated and routed through four CMOS switches ADG 436 The output of each of these switches is passed to a calibration bus which feeds to 50 fF capacitors at the input of every fourth channel on the PMFE Additionally there are 16 2 2 pF capacitors mounted where a detector would otherwise be Wires can be bonded from these capacitor
53. SR SR SR R R R R R OK SK SK SK SK SR OK SR OR OR SK 3K SR SR SR SR SR SR R R R R R R R SK SK SK SK SK OK K SR OR SK SR SR SR SR 2k 2k 2k ak GPIB Pulser Functions k SR SR SR SR SR SR SR SR SR SR R R R R R R R R SK SK SK OO DORE EH 2k 2k 2k K config pulser sets up the pulser vith the correct pulse height and period void config pulser float v hi int dev pulser 1 char ConfigStr 1024 int done 0 sprintf ConfigStr A WID 40U DEL U PER 100U TRMD BURST BC d VHI VLO O LEAD 1E 9 TRAIL 1E 9 num pulses v hi sprintf ConfigStr A WID 400U DEL O U PER 402U TRMD SINGLE VHI f VLO O LEAD 1n TRAIL 1n DEL 80n v hi sprintf ConfigStr As A TRLV 1 20 TRSL POS TRIM HIGHZ TROV SET TTL DISA OFF INVERT OFF ConfigStr sprintf ConfigStr As A TRLV 1 20 TRSL POS TRIM HIGHZ TROV 1 40 DISA OFF INVERT OFF ConfigStr ibwrt dev pulser ConfigStr strlen ConfigStr config_pulser set_voltage sets only the high side voltage of the pulser void set_pulser_voltage float V int dev_pulser char V word 16 sprintf V word A VHI 4 3f V ibwrt dev pulser V word strlen V word set voltage void config thresh ps float v thresh int dev thresh 1 set over voltage protection and other shit as it becomes necessary obvious char V word 1024 147 if v_thresh gt THRESH OV SET v thresh THRESH OV SET sprintf V word vset 3f ise
54. T for the charge injected and the standard deviation gives the resolution of the TOT gain on charge Understanding the T OT resolution is very important because it places a limit on the precision with which the energy of the particle can be measured The TOT gain was studied both by observing the raw comparator output on the PMFE using a pico probe and by conducting traditional DAQ based TOT calibration where several pulses are injected at different charge values resulting in a Gaussian distribution due to noise for each charge step The TOT spectra for each pulse magnitude are fit to Gaussian functions The mean and standard deviations are derived from the fits and a gain curve can be fit to these values This function is then used to map experimental TOTs to injected charge which can further be mapped to the LET of the particle If the digital part of the PTSM is working properly the average comparator response measured using the oscilloscope should match the mean of the Gaussian distribution obtained by the DAQ It was discovered during pico probe measurements of the PMFE amplifiers that the external calibration capacitors were not providing electrically sound calibration pulses Research is being conducted to find the source of this problem Until the external calibration method is functional the gain curves will be limited in range to 7 60 fC 60 4 2 1 Experimental Method The experimental method involved in taking TOT data is very
55. The user sets jumpers on the board for frame The comparison betveen frame and timer makes it possible to change the framing between the front end chip and when the data from it gets latched For example an output register which should store the value of channel 6 might instead be storing the value of 4 or it might be storing the dead time null To remedy this change frame and all will come into alignment eventually If you are getting an odd channel instead of an even one then you need to change the phase between the fe clocks and the latching clock A change of 64 corresponds to 90 degrees which is the most that it should be changed at any one time Assuming that the above conditions are satisfied ser 2 par operates thusly wait ctr counts up on the slow clock to delay startup of the state machine until after the glitchy first few clocks clear the dcms After the wait ctr counts up the synchronization using frame occurs The next four states just grab data from the DDR registers in the top layer and shift them into a shift register On the fifth clock cycle of the bus cycle see web for format there is a dead frame so that time is used to store the contents of the shift register in a buffer which is obviously only updated every 5 clock cycles The data ready pulse is timed such that the subsequent SMs which 89 XX X XX X o X X X KF monitor this data have all the time that they need to process the channel statuses
56. UNIVERSITY OF CALIFORNIA SANTA CRUZ THE DESIGN IMPLEMENTATION AND CHARACTERIZATION OF A PROTOTYPE READOUT SYSTEM FOR THE PARTICLE TRACKING SILICON MICROSCOPE thesis submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in PHYSICS by Brian C Keeney September 2004 The Thesis of Brian C Keeney is approved Professor David Dorfan Chair Professor Hartmut Sadrozinski Professor Bruce Schumm Robert C Miller Vice Chancellor for Research and Dean of Graduate Studies Contents List of Figures vi List of Tables viii Abstract ix Acknowledgements x 1 Introduction 1 1 1 Biological Motivations for the Development of the PTSM 1 1 2 Manipulation of Radiation Effects in Tissue 3 1 3 The Integration of Particle Tracking Silicon Microscope PTSM Measurements into Radiotherapy 4 2 Design 5 2 1 Physical Requirements for Particle Tracking 5 2 2 Architecture Development 6 2 21 Detector Selection 6 2 3 Front End Chip Specification 9 2 3 1 Field Programmable Gate Array FPGA Selection for the Readout Controller ROC ds 11 2 4 Data Acquisition Hardware 11 2 5 CONCLUSION Le 2 e ertt Mere Len ER a der nee 11 3 Implementation 13 3 1 Silicon Strip Detector 16 3 1 1 Propertie
57. Without him the PTSM would not have a functioning DAQ Post doctoral Researcher Gavin Nesom Ph D has provided valuable instincts and insight into the physics of the instrument as well as expertise in analysis of data Last but certainly not least the author thanks Chantal Keeney who has supported the author through good times and bad Without her love and her absolute disdain for mediocrity this work would never have been finished This paper is dedicated to her xi 1 Introduction Oncologists and radiobiologists at Loma Linda University Medical Center LLUMC are studying the biological effects of radiation on living tissue for the purpose of improving the treatment and prevention of cancer When ionizing radiation traverses a cell there is the possibility of damaging the cell s DNA which can in turn adversely affect that cell and the cells which surround it When cells are damaged in this way it is possible for them to replicate uncontrollably This process is known as cancer 1 It is important to understand how radiation affects cells both to learn how cancer develops and to effectively stop it To date the standard practice in studying these effects has been stochastic Cell cultures have traditionally been irradiated by a micro collimated beam of ionizing radiation 2 By knowing the average fluence and Linear Energy Transfer LET an approximation of the radiation dose can be inferred With the development of the Pa
58. a to lower the reset on everything in data handler v This makes it so that there are no noise hits or weird events left over in the fifos from the time before data taking Started After wakeup timer has allowed enough time for these processes to be synced up it sends a trigger pulse trig to the pulser The pulser promptly returns a negative going pulse which in turn triggers a 230 us pulse made by a LM555 timer The state machine waits for the rising edge of this pulse then waits for either the fall of the pulse or for all of the fifos to empty whichever comes last It then raises the DONE line and waits for the START line to be lowered It should be noted that there might be 1 event left in the output controller when the DONE line gets strobed so the readout software should have at least 10 us of delay before issuing a dig block clear not that this should be a a difficult goal to achieve In fact it s not worth worrying about There are a couple of other functions that should also be noted If the pulse jumper is shorted to ground the SM will send a total of 100 pulses before raising the DONE line This will be useful when the kinks get worked out of the readout software because it will DRAMATICALLY raise the maximum acheivable event rate If the cal jumper is shorted the state machine will assume that source data is being taken and not send any pulses Instead the fifos will be inhibited until start is raised Done drops to low un
59. abO 8 b0000 1000 grabi 8 b0001 0000 grab2 8 b0010 0000 grab3 8 b0100 0000 buffer 87b1000 0000 always posedge slow clk begin if res slow follower lt 0 else slow follower lt slow follower end always posedge clk begin if res begin SR timer dout data_ready lt 0 S lt init end else case S init begin SR timer dout data_ready lt 0 S lt slow_follower sync init end initi S lt slow follower 7 sync initi Sync begin timer lt timer 1 S lt frame timer sync grab0 end 91 grab0 begin SR lt 1SR 47 01 din S lt grabi end grabl begin SR lt SR 47 0 din S grab2 end grab2 begin SR SR 47 0 din S lt grab3 end grab3 begin data_ready lt 1 b1 SR lt SR 47 0 din S lt buffer end buffer begin dout lt SR data_ready lt 1 b0 S grab0 end default S init endcase end always endmodule 92 B 3 Pulse Handler RK ak R SR R SR SR SR SR SR SR R K R R R R S S SK SK SK SK SK SK SR R SK 3K SR SR SR SR SR SR R R R R R R RK SR SK SK SK SK SK OR OR OR I SK SR SR SR SR OR 2k 2k 2k kPULSE HANDLER V This module establishes an asynchronous handshake between the readout software and the fpga The readout software raises the START line which causes the fpg
60. ansferring and storing data from the ROC A PCI based data input output DIO card was an obvious choice because it can be installed in any PC At the time of selection there were no affordable 5000 LVDS based DIO cards available National Instruments makes a single ended DIO card the NI6534 The PTSM project decided to use the NI6534 with a custom converter card to translate between CMOS and LVDS 2 5 Conclusion The PTSM project developed a non standard architecture to scale existing technology in particle physics and electronics to a new area of research A double sided silicon strip detector was chosen because of the improved energy resolution and detector mass savings over pixel detectors An ASIC front end chip the PMFE was specified to amplify condition and digitize the detector signals A Xilinx Virtex II FPGA was chosen to implement the readout controller ROC because of its ability to utilize the LVDS logic family A PCI data I 0 card the National Instruments 6534 was chosen 11 to transfer data from the FPGA to the PC based data acquisition system DAQ Having specified the architecture and functionality of the detector front end readout controller and DAQ engineers at SCIPP constructed the PTSM 12 3 Implementation The implementation of the PTSM was carried out in parallel by several groups Si multaneously the PMFE readout controller ROC DIO card software and printed circuit board PCB development
61. arrives evaluate this Q D assign the value of the input to the output 78 B PTSM Readout Controller Verilog Source Code Jk k ak ak ak ak ak aK K aK aK aK aK aK ak aK 3 3K kk 3K 3K kk 3K 3K 3K K I A I I I K K K 24 2k 2k 2k 2k PTSM_READOUT_V4_0 v top level readout for pmfe chip Conventions d is input q is output name_ is active low signal name_i denotes single ended version of a signal Brian Keeney 6 10 04 Copyright 2004 University of California Santa Cruz Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 BREA SR R R R R R R R R R SK SK SK SK SK SR SK SR tu SR OR OR SR SR SR SR SR tubu R R R R R R OS SK SK OK tuta tatu tu tuta tubu utu tubu k k k k k k k k module PTSM_RDOUT_V4_O qp qn clk_data fe_clk daq_clk dp dn clk_in res_ req cal_out cal_in pulse_jumper cal_jumper pulse_start pulse_done frame ack output 15 0 qp qn output 3 0 cal_out output 1 0 clk_ data fe clk daq clk req pulse done pulse trig out input clk in res pulse jumper cal jumper input 1 0 ack pulse start input 2 0 frame input 7 0 dp dn input 3 0 cal in assign cal out cal in reg 15 0 din DDR IOB registers wire 7 0 d lvds out from chip wire 63 0 q ser wire 39 0 fifo dout wire 15 01 dout wire clk fifos full ctrlr idle synthesis attribute
62. as circuitry is located at D Calibration pulses are routed through an SMB connector at E The two IC s above F are the CMOS switches which route the calibration pulses to the four buses The IC below G is the AD620 which conditions the comparator threshold voltage brought in on SMB connector H All LVDS communication is routed through the connectors on the back side of the board at T 30 positive edge is always latched correctly and data associated with a negative edge is always latched correctly on a negative edge A feature of the FPGA called a Digital Clock Manager DCM is used to implement this function A DCM is a physical device in the FPGA which can vary phase manipulate frequency change duty cycle and implement other functionalities There are eight DCMs in the XC2V1000 19 The other requirement placed on the Readout Controller is that it be able to inter face with a National Instruments PCI 6534 The 6534 is a Digital 1 0 input output card with 32 single ended bidirectional data lines In addition it has a bidirectional clock and two handshaking lines ACK acknowledge or ready for data and the REQ request or ROC ready to send data The 6534 has several modes of opera tion In the mode used Burst Mode Handshaking more commonly known as Fully Bc 2 ao 4 Figure 11 Photo of the Test Board mounted on the Proto Board The Proto Board is denoted by D The Test Board is
63. at C The output data lines from the ROC are shown at A The FPGA is in the socket at B 31 Synchronous Handshaking the ROC sends the clock to the 6534 and waits for ACK to be high signaling that the 6534 is ready to accept data When the ROC wants to send data it raises REQ and places data on the bus On the rising edge of the clock the data is latched by the 6534 If ACK falls it means that the data will not be latched These requirements placed on the interfaces of the ROC are the only constraints placed on the architecture The rest of the design is flexible and is a compromise between speed gate count and data compression 3 4 1 Timing Services As has been stated previously it is very important that data be latched from the front end chip at the correct times otherwise channel statuses will be mislabeled and some statuses will be lost altogether To remedy this there are two parameters which must be constant every time that the ROC is reset The phase between the front end clock FE CLK and the main clock CLK must be aligned such that the rising edge of CLK is framed squarely by the rising and falling edges of the even channel data This is referred to as correct phasing of the clock Secondly the front end state machine must start so that when it latches its first positive channel valid data is present from the corresponding channel on the front end chip This is referred to as correct framing of the cl
64. ata 7 28 out pulse cal d a root cal bus TFile f new TFile fname TNtuple ptsmout TNtuple x f Get ptsmout 1 nEvents long ptsmout gt GetEntries printf Analyzing Calibration Bus d which has 74 events n cal_bus nEvents iv thresh count set bins ptsmout fv thresh for channels O channels lt 16 channels iChannel cal bus channels 4 fit_s_curves ptsmout fv_thresh fit_array nEvents iv thresh count iChannel printf Successfully fit S Curves for Channel d n iChannel fit gain curves fit array amp chan gain noise iChannel printf Successfully fit Gain and Noise Curves for Channel d n iChannel for channels f gt Close for_cal_bus make_chip_map amp chan_gain_noise 64 printf Na end main 118 C 1 Gain v2 Include File typedef struct thresh bin 1 float v thresh float q start float q stop float q delta long n bins thresh bin typedef struct channel fit 1 int n points this is the number of fits accomplished float thresh mV float mu fC float mu err fC float sigma e float sigma err e channel fit typedef struct channel stats float gain mv fc float gain_err float gain offset mv float gain offset err float noise e float xnoise err float noise slope e mv float xnoise slope err 1 stats void set delta thresh bin bin 1 float delta b
65. aving many strips improves the resolution but it adds cost complexity and mass to the system More channels are needed which translates to more bonding pads on chips more power consumption and in some cases active cooling All of this is difficult and costly Conversely one large strip covering the active area will capture all the charges and will be inexpensive but will tell nothing of the position of particle tracks and have large capacitance One first needs to decide what resolution one can live with and then pick a detector pitch The resolution is not the pitch as one might assume There is a very good probability near 10096 that if a particle traverses a strip or any point before the half way point to the adjacent strip that a hit will be registered See Fig 4 This assumption gives rise to a box probability distribution 17 0 x W 2 4 1 VV 2 c x VV 2 0 2 V 2 where VV is the strip pitch and the origin is at the center of the pitch By symmetry 2 One can derive the standard deviation c which is the positional resolution of the detector Ww 2 a 2 z gt dx Pow P x dx 3 3 0 Therefore NE SE L o 289L v 12 This result means that for v 12 5 of all events the particle will have landed within of the center of the strip For the Silicon strip detector to be able to resolve whether V12
66. buffer type of clk is BUFG 79 synthesis attribute IOB of din is true always posedge clk begin din 15 8 lt d end always negedge clk begin din 7 0 lt d end clk_tree clk tree fe clk fe clk i Clk data clk data i slow clk slow clk Slow clk bufg slow clk bufg Clk in clk in Clk clk res out res res res ser 2 par v4 ser 2 par v4 din din dout q ser data ready data ready Slow clk slow clk bufg Clk clk res res frame frame 80 pulse handler pulse handler done pulse done i trig pulse trig out i res fifos res fifos Start pulse start i some flag some flag pulse jumper pulse jumper cal jumper cal jumper ctrlr idle ctrlr idle fast or fast or res res clk slow_clk_bufg data handler data handler dout fifo dout bf empty fifo empty fifo flag fifos full din q ser data ready data ready rd fifo rd fifo Clk clk res res fifos little wr little wr flag big wr big wr flag some flag some flag many flag many flag output ctrlr output ctrlr dout dout req req i idle ctrlr idle rd_fifo rd_fifo din fifo_dout ack ack_i fifos_full fifos_ full res res_fifos Clk clk fifo empty fifo empty daq clk slow clk 81 clock and control buffers OBUFDS fe buf I fe clk i O fe_clk 1 OB fe clk 0 OBUFDS clk data buf I c
67. ch br4 ptsmout GetBranch v pulse br4 SetAddress kv pulse TBranch br5 ptsmout gt GetBranch v thresh br5 gt SetAddress amp v thresh s_pulse gt num_pulses 0 for iEvent 0 iEvent lt nEvents iEvent ptsmout GetEntry iEvent if v_pulse fold_v_pulse amp amp v_thresh v_thresh_comp s_pulse gt pulse_index s_pulse gt num_pulses v pulse s_pulse gt q_inj s_pulse gt num_pulses V_2_FC v_pulse s_pulse gt num_pulses fold v pulse v pulse return s pulse 7num pulses int set bins void print bins s pulse index s pulse int i printf d is num pulsesMn s pulse onum pulses for i 0 i s pulse num pulses i printf 4d f n i s pulse Ppulse index il 136 void print bins DRO R R K S R R K SR R R SR RK SSR R SR SR RK SR RK S R R R k R SR SR R kokk kk kk R kk k k kk kk kkk VOID SET H label kok SR R SR SR kokk kk kk OR kokk k k kk kk kk kkk void set h label THiF xh char xh label TF1 x g int channel float v_pulse float mu mu err sig sig err mu g gt GetParameter 1 TOT_QUANTUM mu err g gt GetParError 1 TOT_QUANTUM sig g oGetParameter 2 TOT_QUANTUM sig err g gt GetParError 2 TOT_QUANTUM sprintf h_label TOT Distribution for CH 4d Q 3 2f fC MU 3 226 3 22 uS STDEV 3 2f4 3 2f 9 channel v pulse V 2 FC mu mu err sig sig err h gt GetXaxis
68. ch has two inputs SET and RESET and an output Q When SET goes high the output goes high until RESET goes high Then the output is low until SET rises again mixed signal design A single circuit board or ASIC which has both analog and digital signals on it multiplexer A combinatorial logic device with at minimum two inputs a select bit or more for more than 2 inputs and an output A two input multiplexer with 77 inputs and B might express the value of A if the select bit were high and B if the select bit were low nibble four bits register One or more flip flops in a logical array skew The difference in arrival time between two paths of one signal that originate in the same location but differ in destination single ended An electrical signal which travels on one wire with a potential refer enced to ground synchronous logic Logic units which have memory and only change state on a clock edge Verilog Verilog is a Hardware Descriptive Language HDL which in Syntax appears very close to C 30 For example an OR gate with inputs A and B and output C would be implied with assign C A B An AND gate with the same inputs and outputs would be implied with assign C A amp B a flip flop with input D and output Q is only slightly more complicated Reg flop one must declare a register there are no formal flip flops in Verilog Always posedge clk every time the positive edge of the clock
69. cial PCI digital input output card could be used plugged directly into a PC 2 2 1 Detector Selection The detector selection process involves balancing the relative strengths and weaknesses of different architectures pixels vs strips and single vs double sided and pitch to best detect particles with a minimum of difficulty The two main parameters which are influenced by these choices are position and energy resolution Pixel detectors are made up of rectangles of doped silicon on one side of an oppo sitely doped wafer There is a trace and thus a channel for each square A detector with N N pixels must have N connections to readout electronics Each connection is ultrasonically welded to the input pads of the readout electronics Silicon strip detectors are made up of strips of doped silicon on one or both sides of a doped wafer For an N x N array there are 2N strips This is the most striking difference between strips and pixels When using two sets of strips from either two single sided detectors or from one double sided detector there are also two signals one from the x side and one from the y side Although the signals are not the same they permit two measurements of the charge and thus the resolution is improved by 5 One liability in using silicon strips when the amount of charge is not precisely known is called ghosting Ghosting occurs when two particles traverse the detector at the same time Then there are four po
70. cupancy Number of Events Above Threshold Number of Identical Charges Injected Occupancy 48 on the y axis and charge on the x axis Since there is noise in the system a different behavior is observed Consider an event where the noiseless signal falls just short of firing the comparator and just at the peaking moment of this event a few extra electrons of noise are added to the signal putting it just above the comparator voltage This would cause an event to be recorded even though the signal was not sufficient in magnitude to cause the event alone This behavior occurs much less frequently very far from the rising edge of the step function than at the rising edge itself This causes an s curve type shape shown in Fig 15 Response Curve of System Without Noise 100 F 80 l 60 Occupancy 40 F 20r 1 1 1 1 1 1 1 0 0 5 1 1 5 2 2 5 3 3 5 4 Charge Figure 14 Idealized response curve to varying charge input The 50 point of the s curve corresponds to the transition point in the ideal system where the shaper output just touches the threshold voltage By finding this point one can measure the height of the pulse for a given charge input The width of the s curve gives a direct measurement of the noise assuming that the noise is Gaussian S curves have a related Gaussian distribution and the standard deviation of the corresponding Gaussian is a convenient measure of the noise The rate of transiti
71. d be done channel by channel when the system is used in the field but rather to characterize the large scale behavior of the instrument Because of this the offset in gain is normal and expected The DAQ based TOT calibration matches very closely the values obtained above with an average gain of 21 03 fo and an offset of 1 26 30 us These values both agree very closely with the data taken in 3 which show a gain of 20 Fel and an offset of 50 us The DAQ based TOT calibration further shows that the resolution on charge is constant measured at 22 08 23 06 and 23 05 us for charges of 4 20 and 50 fC respectively This width is very small especially considering that the bin width used for the data gathering is 1 us due to the effective sampling rate of 10 MHz It has been previously thought that the outliers of the resolution curve channels 5 10 etc were the result of errors in the fitting routines or statistical fluctuations But on comparison with the noise map of the previous section composed from completely unrelated data and source code it is clear that increased TOT resolution is highly correlated with noise Compare Fig 23 with Fig 30 Further investigation is being conducted into the causes of this effect The three characterizations of TOT to date the first being in 3 consistently show that the TOT gain is 2 Fo for the charge range of 10 60 fC which is close to the specified value of
72. dout controller ROC The major specification to be made in the Particle Microscope Front End PMFE was that of the shaping time Charge signals are emitted from the detector as short bursts of current lasting up to 30 ns 12 This charge is deposited on the input of the PMFE where the input capacitance and input resistance are very large This can be modeled as a current source charging a capacitance which forms a ramp in voltage Since this happens over 30 ns which is much smaller than the discharge time the effective waveform is a step function preamplifier amplifies the charge on the input capacitance into a voltage which is proportional to that charge A shaper circuit similar to a differentiator integrator then shapes the step into a longer in time pulse with a quasi gaussian shape A characteristic of the shaper called the shaping time is the time that the shaper takes to rise from to the maximum pulse height The time during which the pulse is above a certain threshold is a function of the input charge which in PTSM is used as a measurement of the particle energy Only a very approximate measurement of the energy is needed enough to verify that the incident beam energy is in the correct region Picking the rise time is a trade off between resolution on the pulses dead time and noise If the rise time is very short then many events can occur sequentially on one channel and the amplifier will be able to distinguish them as ind
73. e LET which can be used to compute the energy deposited in the cell dose IProtons deposit energy as d x ET where X has units of 11 1 3 The Integration of Particle Tracking Silicon Microscope PTSM Measurements into Radiotherapy Successful radiotherapy destroys the maximal volume of cancerous tissue while seeking to minimize damage in the patient Radiotherapy kills cancer cells by stimulating apoptosis and the bystander effect in the malignant tissue The favorable mechanisms of the bystander effect and apoptosis exhibit a saturation effect after a certain level increasing the dose does not provide the same increase in effectiveness Therefore it is extremely important to have accurate models of how radiation affects cells In order to develop accurate models large scale reliable and reproducible studies are needed The Particle Tracking Silicon Microscope developed by the Santa Cruz Institute for Particle Physics SCIPP in cooperation with Loma Linda University Medical Center can help make such large scale studies both accurate and economi cal This paper will show how the prototype readout system was designed describe the development process of the instrument and present the results of the prototype characterization 2 Design In the study of radiation effects in tissue it is essential that the location and mag nitude of the damage be well known The PTSM project correlates specific particle tracks with the cel
74. e inputs are low the FIFO s empty and the output controller is idle Then it polls a jumper on the Proto Board If the jumper is set i e the value is 0 then it repeats this process 99 times If the jumper is not set or if the counter that counts the number of pulses is at 99 100 pulses sent the controller forces the blocks under its control to reset It then raises the done line and waits for the DAQ to lower the start line Once the 1015 ms is an empirically derived and very approximate number It is however several orders of magnitude above that which is needed making a precise measurement unnecessary 40 start line is low the controller waits for the next start in the idle state There is another jumper which can be set to have the ROC run in a normal mode where the ROC begins taking data from the PMFE when the start line goes high and stops taking data when it is lowered This mode is used for taking noise data with no calibration pulses or calibration data with a radiation source There is no trigger for particle events zero suppressed data is simply read out to the DAQ as it comes in from the PMFE 3 5 The NI6534 Data Acquisition PCI Card The PTSM project decided that it was not cost effective to design and build a custom DAQ card and instead purchased a ready made card with existing driver software The NI6534 is capable of transferring up to 32 bits at up to 20 MHz for short
75. e noise and analog gain of the front end electronics T he analog gain is the ratio between the peak height of the output pulse and the input charge The noise is defined as the standard deviation of the input charge 15 The gain and noise are important figures of merit because they place lower bounds on signal resolution and measurement The second round of testing sought to verify the TOT gain The TOT gain differs from the analog gain in that it is a measure of the length of the output pulse whereas the analog gain measures the peak height The TOT is an important parameter to understand because it provides the charge measurement that is recorded by the DAQ The third test sought to verify the accuracy of both tests by imaging a 99Sr radiation source This is an important test because it provides feedback on both the instrument and the calibration and testing methods 4 1 Determination of the Analog Gain and Noise of the PMFE One way of measuring the gain is to set the comparator in the PMFE at a known threshold voltage and to slowly increase the charge If there were no noise in the system one would expect that for all charges which produce a shaped output less than the threshold there would be no signal since the comparator would never go high Conversely for all charges which produced a signal greater than the threshold the output would always go high See Fig 14 This behavior would be shown as a step function when plotted with oc
76. eaning that the amplifier is insensitive to input load ca pacitance This is important because different detectors have different capacitances The computed error of the fits to the comparator based T OT gain data are artificially low due to linear fits to non linear data Based on experience the collection of several different sets of data the author estimates the error on the gain to be 3 and the error on the offset to be 2 Table 4 also shows that the variation between 100 mV Average Chip Resolution at 50 0 fC 0 23 0 05 us 7 0 5 21 5 0 45 40 50 60 PMFE Channel Number Figure 31 Chip wide map of the TOT resolution for 50 fC 68 for Gain Curve for Channel 43 The average gain is 0 68 0 00 us fC with an offset of 0 14 0 00 us 2 TOT us 0 LR AA TA TT 0 8 0 6 0 4 0 2 jim L il 214 ic JL i Jo ill 1 1 5 2 2 5 3 Q Injected fC Figure 32 A typical TOT gain curve for the charge region of 5 to 2 75 fC Chip TOT Gain 0 70 0 00 us fC with an offset of 0 13 0 00 us TOT gain us fC 50 60 PMFE Channel Number Figure 33 The chip wide TOT gain for the region of 5 to 2 75 fC The errors are artificially low The actual error on the gain is close to 05 fo 69 and 125 mV in threshold is negligible at charges greater than 10 fC The linear fits are not meant to exactly map the behavior of the TOT as shoul
77. eavy ion traverses a single cell The diameter of a cell is 10 20 um which necessitates a pitch of 435 um The detector that best fits the needs of the PTSM for prototyping is a SINTEF double sided SSD with 50 80 um pitch P N and an active area of 2 4 cm X 1 2 cm 4 As the project matures a custom detector with a smaller active area and finer pitch will be developed PTSM uses only 64 cm X 1 2 cm 19 3 2 The Particle Microscope Front End PMFE Application Spe cific Integrated Circuit ASIC The heart of the electronics of the PTSM is in the Particle Microscope Front End PMFE In the PMFE are 64 charge sensitive amplifiers and shapers which detect the charge on the detector strips and turn it into an easily digitized signal Pulse width modulation circuitry converts the analog signal to a digital one A parallel to serial converter shifts the status of each channel out over 8 wires in 4 clock cycles using Double Data Rate DDR 3 2 1 Charge Amplification Charge amplification is the first and most critical of the electronic operations in the PTSM An RC network is formed with the detector s coupling capacitance and the input resistance of the amplifier This RC is typically much larger than the 25 ns collection time As the charge is collected the voltage at the front end rises linearly The discharge time is much larger than this charging time as much as several thousand times greater due to RingmpCinamptdet 12 Refer
78. ection of charge for calibration pulses via GPIB This proved to be a problem because the synchronization between the two buses is limited to 15 ms in either direction This low and unpredictable rate limited data gathering to a few hundred Hertz It was decided that it would be much better to have the FPGA trigger the pulses and to add two handshaking signals to the system Extra digital lines on a NI6703 Digital to Analog Converter DAC card were converted to LVDS on a lab built PCB One line is from the DAQ to the ROC and the other is from the ROC to the DAQ An asynchronous handshaking protocol is used to signal the FPGA to start accepting data The ROC raises its line when it is finished pulsing and reading out its data to the DAQ The two lines are named start and done respectively Pulse Handler v serves as a master controller and handles the reset states of the zero suppression FIFO and output controller blocks The master reset line still controls the clock tree which in turn controls the resets of the serial to parallel conversion and calibration controller blocks When Pulse Handler receives the start strobe it lowers the reset line of the zero suppression FIFO and output controller blocks It then waits for them to synchronize and become idle After this wait it sends a trigger to the pulser via an LVDS line It then waits 409 6 us for the analog electronics to fully integrate the charge It then waits until all of th
79. ectrons http physics nist gov PhysRefData Star Text ESTAR html 5102 29 Semiconductor Glossary Silicon Dioxide http semiconductorglossary com default asp searchterm silicon dioxide 2C SiO2 30 S Palnitkar Verilog HDL Prentice Hall PTR 1996 pp 1 170
80. ed charge equally between them the two resulting TOTs would not represent the total amount of charge due to one electron These multiple strip hits at lower TOT s occlude the other spectra which exist in addition to the Landau distribution When the charge from a particle is measured correctly the charge and thus the TOT spectrum should follow a Landau distribution 26 As a first approximation a Landau curve was fit to the data to provide the mean TOT for the spectrum The mean of the Landau distribution is 61 us To find the amount of charge deposited this value can be 71 Intensity Map for 90 SR Source Data with Collimator 2500 2000 4 1500 1000 500 10 20 30 40 50 60 Channel o2 Figure 34 Intensity map for data taken with uncollimated 9 Sr source Note that channels 0 and 63 were poorly behaved and so they were cut from the histogram There are two dead strips channels 6 and 15 TOT distribution for 90 SR Beta Spectrum Mu 0 59 0 01 us Sigma 0 17 0 00 us 2 32200 2000 1800 1600 1400 1200 1000 800 600 400 200 ol il sos sc db osa sca bos nu x JD xoa rm 5 10 15 20 25 TOT 1 us o Figure 35 TOT spectrum for the uncollimated 9 Sr source measurement 72 Intensity Map for 90 SR Source Data with Collimator 9 600 500 400 300 200 100 10 20
81. er It is difficult to study radiation effects in the tissue of large organisms because there are too many parameters to control The best organism for studying these effects is the one which has the fewest cells while still exhibiting tissue like behavior Biologist Sidney Brenner in the early 1960 s found a simple organism which had sufficient cells and was easy to study and replicate with regularity C elegans is a nematode that develops 1090 cells 131 of which always undergo apoptosis during development 10 Every cell is deterministic in that it always shows up in the same location and performs the same function C elegans was the first organism to have its genome completely sequenced making it possible to manipulate the genetic structure of the organism Another advantage of using the C elegans is that it is one mm long which makes it barely visible to the naked eye and easily manipulated in a laboratory setting Additionally C elegans is easy and inexpensive to produce in bulk with specific phenotypes 10 The PTSM project uses C elegans in its studies of radiation effects in tissue because of these favorable traits The most precise way to study these effects would be by relating single particle events to individual cells In the past there have been no instruments able to provide this type of measurement The P TSM is designed to be able to resolve particle tracks at the resolution of a cell nucleus and to provide a measurement of th
82. er SO dout CO some some 101 many manyl101 fifo full fifo full 0 din din 3 0 data ready data ready rd fifo ch rd 0 tyme tyme Wr fifo wr little bus 0 Clk clk res res defparam S1 group id 5 h11 chan server S1 dout C1 some some 1 100 many many 1 fifo full fifo full 1 din din 7 4 data ready data ready rd fifo ch rd 1 tyme tyme wr fifo wr little bus 1 Clk clk res res defparam S2 group_id 5 h12 chan_server S2 dout C2 some some 121 many many 2 fifo full fifo full 2 din dinl11 81 data ready data ready rd_fifo ch_rd 2 Wr fifo wr little bus 2 tyme tyme Clk clk res res Jis defparam S3 group_id 5 h13 chan_server S3 dout C3 some some 3 nany many 3 ifo fnll frfo full 31 din din 15 12 data ready data ready rd fifo ch rd 3 Wr fifo wr little bus 3 tyme tyme Clk clk res res defparam S4 group_id 5 h14 chan server S4 dout C4 some some 4 101 many many 41 fifo full fifo full 4 din din 19 16 data ready data ready rd fifo ch rd 4 Wr fifo wr little bus 4 tyme tyme Clk clk res res 33 defparam S5 group_id 5 h15 chan server S5 dout C5 some some 5 many many 51 fifo full fifo full 5 din din 23 20 data
83. erization of the PTSM system The gain results listed are for the 5 60 fC region at the 125 mV threshold The noise measurements were taken without a mounted detector 75 5 Conclusion This paper discussed the design implementation and characterization of a prototype readout system of the Particle Tracking Silicon Microscope PTSM Radiobiologists at Loma Linda University Medical Center are studying the effects of ionizing radiation on living tissue An instrument is needed which can correlate particle tracks with specific cells Using this information detailed and precise models of the effect of radiation on tissue can be developed and adapted to cancer therapy and prevention A prototype readout system was designed and implemented at the Santa Cruz Institute for Particle Physics This paper described and analyzed the characterization process of this prototype The preliminary results of both calibration and radiation source tests indicate that the PTSM will be able to detect fast protons and heavy ions with excellent charge resolution and spatial resolution on the order of a cell nucleus These measurements will aid radiobiologists in solving complex problems in cancer therapy 76 A Glossary ASIC Application Specific Integrated Circuit asynchronous logic Logic which does not wait for a clock edge to transition Asyn chronous logic may or may not have memory bit Bit stands for Binary Digit Most digital systems use bits
84. es 33 defparam S11 group id 5 hib chan_server S11 dout C11 some some 11 many many 11 fifo full fifo full 11 din din147 441 data ready data ready rd_fifo ch_rd 11 Wr fifo wr little bus 11 tyme tyme Clk clk res res Jis defparam S12 group id 5 hic chan server S12 dout C12 some some1121 many many 121 fifo_full fifo_full 12 din din 51 48 data ready data ready Wr fifo wr little bus 12 rd_fifo ch_rd 12 tyme tyme Clk clk res res defparam S13 group_id 5 hid chan_server S13 dout C13 some some 1131 104 many many 131 fifo_full fifo_full 13 din din 55 52 data ready data ready rd fifo ch rd 13 Wr fifo wr little bus 13 tyme tyme Clk clk res res 33 defparam S14 group id b h e chan server S14 dout C14 some some1141 many many 14 fifo full fifo full 14 din din 59 56 data ready data ready rd_fifo ch_rd 14 Wr fifo wr little bus 14 tyme tyme Clk clk res res Jis defparam S15 group id 5 hif chan server S15 dout C15 some some 1151 many many 151 fifo_full fifo_full 15 din din 63 60 data ready data ready rd fifo ch rd 15 Wr fifo wr little bus 15 tyme tyme Clk clk res res endmodule 105 B 5 Channel Server iet tata SK SK SK R SR
85. ettle 3 amp rad settle 2 0 rad settle 2 amp rad settle 1 0 rad settle 1 0 trad settle 0 0 S lt amp rad settle radiation finish radiation test end radiation finish begin ifno data in fifos or controller raise done if some flag amp ctrlr idle done 1 b1 otherwise lower it else done lt 1 b0 if we re not done in this state go back to rad test S lt start amp done init radiation test end 97 default S lt init endcase end end always endmodule 98 B 4 Data Handler SR R SR SR R SR SR SR R SR SR Ok R SR SR Ok k OR SR R Xk R R SR R R SR I aK R SR SR A R SR A 3K R SR SR K OR SR Ok k k k tatu k k k k k k k k DATA HANDLER V1 V Data Handler stitches together fifo server and channel server The overall functionality of the set of modules is that of data compression The module marks a start time when a channel goes high and stores the start time and the transition in one of 16 fifos When the channel goes low the stop time is marked and entered into the same fifo The 16 fifos are then selectively read out based generally on need into one main fifo At this point an additional tag is placed on the data to identify the non mapped channel id The main fifo is read out by the output controller Brian Keeney 6 1 04 bkeeney scipp ucsc edu Copyr
86. fC Q 6 63 fC Conf Gain 45 Offset wus Gain 45 Offset js Calibration 100 mV 315 1 08 215 2 06 Calibration 125 mV 300 635 200 1 81 Detector 125 mV A 1 19 21 3 34 Table 4 Results of the comparator based method of TOT characterization The computed error on these figures is artificially low due to fitting a line to non linear data TOT s were then fit to lines and the average behaviors computed The DAQ based method of TOT gain measurement yielded ten Gaussian distributions for each chan nel Gain and resolution curves were then fit to the resulting means and standard deviations These were then averaged to give a chip wide measurement of the gain and resolution 4 2 8 Computation The program used to analyze the comparator based TOT calibration COMP_GAIN can be found in Appendix F COMP GAIN stores the data in arrays and fits lines to each curve using ROOT fitting and graphics libraries 21 The curves and fits are saved to postscript files for later viewing The parameters from each fit are then printed to stdout The output from this program can be seen in Appendix F 1 A sample gain curve is shown in Fig 25 Table 4 shows the results of the fits 63 ch 1 pulse 100mv high G 0 20 0 00 Offset 1 26 0 01 TOT us e proprji rs rss qp uu L uu 08 PEA A 9 10 20 30 40 50 60 Q fC Figure 25 A typical gain curve from the c
87. fit array i n points 0 for i init_fit_array void init_chan_gain_noise channel_stats stats stats gt gain float x calloc NUM CHANNELS sizeof float stats gt gain_err float calloc NUM CHANNELS sizeof float stats gt gain_offset float calloc NUM CHANNELS sizeof float stats gt gain_offset_err float calloc NUM_CHANNELS sizeof float stats gt noise float calloc NUM_CHANNELS sizeof float stats gt noise_err float calloc NUM_CHANNELS sizeof float stats gt noise_slope float calloc NUM CHANNELS sizeof float stats gt noise_slope_err float calloc NUM_CHANNELS sizeof float init_chan_gain_noise void print_fit_array channel_fit fit_array int i for i 0 i lt fit_array gt n_points i printf Af 4f 4f Wf fNn fit array thresh i fit array mu i fit_array gt mu_err i fit array osigmalil fit_array gt sigma_errlil 122 fori print fit array void store gain noise channel stats stats int iChannel float gain float gain err float gain offset float gain offset err float noise float noise err float noise slope float noise slope err stats gain iChannel gain stats 2gain err iChannel gain err stats gain offset iChannel gain offset stats gain offset err iChannel gain offset err stats noise iChannel noise stats noise err iChannel noise err stats noise slope iChannel no
88. fit gauss int channel float kx gauss mu gauss mu err float gauss sig gauss sig err TGraph g gain g res TCanvas xc gain xc res TG1F x tot res H typedef struct s pulse index int num pulses float pulse index float q inj Hh void init pulse index s pulse index x s pulse 1 S pulse Pnum pulses 0 S pulse pulse index float x calloc MAX NUM PULSE BINS sizeof float s_pulse gt q_inj float x calloc MAX NUM PULSE BINS sizeof float 1 init pulse index void init s fit gauss s fit gauss s gauss int channels 1 int i for i 0 i lt channels i s gauss i channel i s gauss il gauss mu float x calloc MAX NUM PULSE BINS sizeof float s gauss il gauss mu err float calloc MAX NUM PULSE BINS sizeof float s gauss il gauss sig float x calloc MAX NUM PULSE BINS sizeof float s gauss il gauss sig err float calloc MAX NUM PULSE BINS sizeof float init s fit gauss int set bins TNtuple x ptsmout s pulse index s pulse 135 float v_thresh_comp float fold_v_pulse 1 long iEvent 0 float event_id channel tot v_pulse v_thresh long nEvents long ptsmout gt GetEntries TBranch bri ptsmout gt GetBranch event id bri gt SetAddress amp event id TBranch br2 ptsmout gt GetBranch channel br2 gt SetAddress amp channel TBranch br3 ptsmout GetBranch tot br3 gt SetAddress amp tot TBran
89. fit_gain_res void print s gauss s fit gauss x s gauss int num points 1 int i for i 0 i lt num_points it printf A4d 4d 2 f f 2fAn s gauss ochannel i s gauss gauss mu i s gauss gauss mu errlil 141 s_gauss gt gauss_siglil s_gauss gt gauss_sig_errlil void plot chip float chip gain float chip_res int i float res sum res sqd g sum g sqd float res avg res dev g avg g dev float chan num REAL NUM CHANNELS char label 128 for i 20 i REAL NUM CHANNELS i chan num i float i fori for i 0 i REAL NUM CHANNELS i res sum chip reslil res sqd chip res i chip reslil g sum chip gainlil g sqd chip gainlilxchip gain il g avg g sum float REAL NUM CHANNELS g dev sqrt g sqd g sum g sum float REAL NUM CHANNELS res avg res sum float REAL NUM CHANNELS res dev sqrt res sqd res sumxres sum float REAL NUM CHANNELS sprintf label Chip TOT Gain 3 2f 3 2f uS fC g avg res avg TCanvas c chip new TCanvas TGraph g chip new TGraphErrors REAL NUM CHANNELS chan num chip gain NULL chip res 142 g_chip gt SetTitle label g_chip gt GetYaxis gt SetTitle TOT gain uS fC Error Bars are Resolution g_chip gt GetXaxis gt SetTitle PMFE Channel Number g_chip gt Draw AB TPostScript gain ps chip tot gain ps 112 gain ps Range 24 16 set x y of printed page c_chip gt Update ga
90. g diagram for the PMFE The FDR s are D flip flops with resets and the M2 s are two input multiplexers see Glossary B CLK defines the bus cycle which is 5 clocks long The data is trans ferred over eight differential signal pairs D7 D0 only the first DO is shown The channel numbers which are transferred over D are indicated The channels for D1 are 14 15 12 13 10 11 8 9 D2 AU Sr elo ste e PAUSE ee Schematic of the digital region of the PMFE An identical block handles the odd channels for the data line The two are multiplexed by the fast clock at the multiplexer furthest to the right Timing diagram of setup and hold requirements D is the input Q is the output and CLK is the clock Photo of the Test Board A shows the PMFE The detector bias ring is marked by B If a detector is used a window is milled out removing region C Within C are the 16 external calibration capac itors The detector bias circuitry is located at D Calibration pulses are routed through an SMB connector at E The two IC s above F are the CMOS switches which route the calibration pulses to the four buses The IC below G is the AD620 which conditions the compara tor threshold voltage brought in on SMB connector H All LVDS communication is routed through the connectors on the back side of the board ato 0030000000 Photo of the Test Board mou
91. gt SetTitle TOT 1 uS h gt GetYaxis gt SetTitle Number of Events h gt GetXaxis gt CenterTitle h gt GetYaxis gt CenterTitle h gt SetTitle h_label set_h_label PERRO SR SR SR SR R R R R R OS S SK SK SK SK SR SR tu SR 3K 3K SR SR SR SR SR SR R R R R R R RK SK SK 3K SK K I A I I SK OR SR SR SR SR 2k k k VOID STORE GAUSS FIT SKK SK SR SR SR SR ak ak SR SR SR SR SR SR R R R R R R R R SK SK SK SK SR SR 3K 3K SR SR SR SR SR SR SR SR R R R R R R R RK SK 3K 3K SK SK OR SR OR OR SR SR K ok 2k 2k 2k K void store gauss fit TF1 x g s fit gauss s gauss int index if g gt GetParameter 1 gt 0 amp amp g gt GetParameter 1 lt 100 amp amp g gt GetParError 1 lt 20 s gauss gauss mulindexl g gt GetParameter 1 TOT_QUANTUM s_gauss gt gauss_mu_err index g gt GetParError 1 TOT_QUANTUM s_gauss gt gauss_sig index g gt GetParameter 2 TOT_QUANTUM s gauss gauss sig err index g oGetParError 2 TOT_QUANTUM else s_gauss gt gauss_mu index 0 s gauss gauss mu err index 0 137 s_gauss gt gauss_siglindex 0 s gauss gauss sig err index 0 void store_gauss_fit VA istat tatu tu SR SR SR SR SR SR SR SR K K R R R OS SK SK SK SK SR SK SR OR SR SK 3K SR SR SR SR SR SR SR R R R R R R RK SK SK SK SK SK OR K OR OR SK SR OR SR SR 2k 2k 2k 2k VOID FIT GAUSS akk SK SR SR SR SR SR SR SR SR SR SR SR 3K K aK K aK aK ak ak
92. h h include TF1 h include TCanvas h include TGraph h include TGraphErrors h include TPostScript h include math h include tot gain include cxx int main 132 long nEvents int cal bus channels iChannel char fname 128 float chip gain 64 chip res 64 s fit gauss s gauss REAL NUM CHANNELS S pulse index s pulse init s fit gauss s gauss REAL NUM CHANNELS init pulse index s pulse for iChannel 0 iChannel REAL NUM CHANNELS iChannel chip gain iChannel 1 chip res iChannel 1 for ichannel for cal bus 0 cal_bus lt 4 cal_bus sprintf fname ptsm data 7 24 out tot bus d no grn root cal bus TFile f new TFile fname TNtuple ptsmout TNtuple x f Get ptsmout 1 nEvents long ptsmout gt GetEntries printf Analyzing Calibration Bus d which has d events n cal_bus nEvents set_bins ptsmout amp s_pulse V_THRESH_COMPARE for channels O channels lt 16 channels iChannel cal bus channels 4 fit gauss ptsmout amp s_pulse amp s_gauss iChannel V THRESH COMPARE fit gain gauss iChannel pulse amp chip gain iChannel amp chip res iChannel printf Na Finished Analyzing Chip Channel d n iChannel 133 for channels f Close for cal bus plot chip chip gain chip res printf Na 4 end main 134 D 1 TOT Gain Include File typedef struct s
93. h lt f amp amp v_thresh gt f amp amp channel d fv thresh current thresh v thresh DELTA fv thresh current thresh v thresh DELTA iChannel sprintf pslabel s curves s curve c d v thr f ps iChannel fv thresh current thresh v thresh if fv thresh current thresh n bins 4 hl index 1 new THIF hname histo 125 fv thresh current thresh n bins fv thresh current thresh q start fv thresh current thresh q stop else hl index new THiF hname histo 1 0 1 h index gt SetStats kFALSE if ptsmout gt Project hname v pulse hcut 1 c index new TCanvas h index gt Scale Y SCALE sprintf axlabel Q fC 45 4f V_2_FC hlindex gt GetXaxis gt SetTitle axlabel hlindex gt GetYaxis gt SetTitle Dccupancy h index gt GetXaxis gt CenterTitle h index gt GetYaxis gt CenterTitle h index gt Fit ferf Q noise float V_2_FC ferf gt GetParameter 1 10000 1 602176 noise err float V 2 FC ferf GetParError 1 10000 1 602176 gain float 1000 V mV fv thresh current thresh v thresh V 2 FC x ferf oGetParameter 0 gain err float gain ferf gt GetParError 0 ferf oGetParameter 0 mu ferf oGetParameter 0 V 2 FC mu err ferf oGetParError 0 xV 2 FC sigma noise sigma err noise err if nu CHARGE CUT mu err CHARGE CUT mu 0 mu_err 0 sigma O
94. h stores the last known state of the channels During the first monitoring state it compares the zeroth bit of its input bus with the zeroth bit of the channel status register If the two are different it raises the write enable of a FIFO which stores a two bit channel ID the transition 1 for 0 to 1 0 for 1 to 0 At the moment that the FIFO writes the event the state machine is already in the next state comparing the status of the next channel As an example of typical operation consider a case where channel 15 goes high for 2 us at time 10 0X0000000A 9 The bus clock period is 100 ns so there will be 20 full checks of channel 15 s status before it goes low At the first presence of a 1 in the data bit for channel 15 the state machine will write 11 1 0000000A to the FIFO When the channel falls at time 30 0X0000001E the state machine will write 11 1 0000001E to its FIFO 6 The state machine itself sees channel 15 as channel 3 The first state machine truly has channels 0 through 3 the second state machine has 4 5 6 7 which it sees as 0 1 2 3 and so on 35 At this point in the design there are 16 channel monitors each having a FIFO to which it writes data These state machines collectively monitor all 64 channels Fifo server v monitors the status of each of the 16 FIFO s and reads each of their contents into a master FIFO which is in turn emptied by the output controller The different channels in the small FIFO s are dis
95. heir errors are obtained Given these values an estimate of the gain and the noise can be made for every curve in the set The gain is stated as the number of millivolts of amplifier output for 1 fC of input charge We obtain the gain by dividing the threshold by the 5096 occupancy input charge We expect the noise measurements to be flat with respect to input charge because the noise is a property of the amplifier and not of the charge 15 Since the amplifier will be nonlinear at some point it is prudent to take gain measurements for several thresholds in the area where the amplifier will operate One can then 51 derive the gain curve for the system which yields valuable information about how the amplifier will function under normal operating conditions See Fig 17 for an example of a gain curve It is important to raise only one calibration bus at a time because the stability of the chip might degrade if all channels were pulsed at once This is a ch 4 v thresh 110 mV Q ini 1 2724 0 114 fC noise 544 446 e gain 86 464 7 77 mV fC o pb DT fa o 96 Occupancy e A 0 2 025 0 3 035 04 045 a iC 3 237 Figure 16 Typical s Curve for determining the gain and noise at a particular thresh old Ch 56 Gain 97 64 0 2 mV fC Offset 2 8 0 3 mV ND e o E 2 2180 9 EN o o iux inc apt je uM p arcte 18 2 22 50 Point fC
96. hift reg extra 2 bits for the zeros reg count bits 1 0 shift count reg req good read ack err start bit fifo full bit reg 2 0 S 112 assign dout shift reg 15 0 parameter 15 0 start code 16 haaaa ack word 16 hbbbb fifo err 16 hcccc parameter 2 0 init 3 b000 home 3 b001 shift_data_out 3 b01 shift_1 3 b011 wait 4 latch 3 b100 hold time 3 b101 always posedge clk begin if res begin S req good_read rd_fifo start_bit ack_err fifo_full_bit idle lt 0 end else case S init begin shift_reg shift_count req ack_err idle lt 0 rd_fifo good_read fifo_full_bit lt 0 start bit lt 1 bi S lt home end home begin req lt 1 b0 if rd_fifo begin idle lt 0 rd_fifo lt 0 S lt home end else if start_bit amp ack begin 113 idle lt 0 shift_reg 15 0 lt start_code shift count max count start bit lt 0 S shift data out end else if fifos full amp ack amp fifo full bit begin idle lt 0 shift reg 15 0 lt fifo err fifo full bit lt 1 bi shift count lt max count S lt shift data out end else if ack err ack begin idle lt 0 shift reg 15 0 shift regl151 7 shift reg 15 0 ack word shift count lt max count ack err lt ack 7 1 bo 1 bi S lt ack shift data out home end else if fifo empty amp good read begin idle lt 0 rd fifo lt
97. hip noise err f O char label 128 for i 0 i lt num_chan i chan numbers i float i for i 0 i lt 16 i 4 chan gain noise gain i 4 0 chan gain noise gain err i 4 for i 0 i lt num_chan i chip gain f chan gain noise gain i chip gain err f chan gain noise gain errlil chip noise f chan gain noise onoiselil chip noise err f chan gain noise noise errlil chip gain f chip gain f float num chan chip gain err f chip gain err f float num chan chip noise f chip noise f float num chan chip noise err f chip noise err f float num chan TCanvas xc gain new TCanvas TGraph x chip gain new TGraphErrors num chan chan numbers chan gain noise gain NULL chan gain noise gain err 130 chip_gain gt SetMaximum GAIN_MAX chip_gain gt SetMinimum O sprintf label PMFE Gain Map Gain 4f 4 3 2f chip gain f chip gain err f chip gain oSetTitle label chip gain oGetXaxis 5SetTitle Channel ID chip_gain gt GetYaxis gt SetTitle Gain mV fC chip gain oDrav AB TPostScript chip gain ps chip gain ps 112 chip gain ps Range 24 16 c_gain gt Update chip_gain_ps Close TCanvas c noise new TCanvas TGraph x chip noise new TGraphErrors num chan chan numbers chan gain noise noise NULL chan gain noise onoise err chip noise 5SetMaximum 1500 chip noise oSetMinimum 0 sprintf label PMFE
98. hronizes off this pulse but does not use it at any other time because the signal is periodic 3 4 3 Buffering the Data Zero Suppression It is important to compress data as quickly as possible because every stage where the data is not compressed must have a higher throughput than would otherwise 34 be necessary Delaying data compression translates directly into cost and difficulty PTSM uses a blend of zero and data compression The output from the PMFE is the multiplexed status of all channels over one bus cycle even if a channel is inactive and has been for several seconds the PMFE will continue to send its status Therefore the first operation that is done on the data after de serialization is to store information about a channel only when it transitions from low to high or high to low Since there are 64 channels to perform this operation on and only four clock cycles in which to do it parallel processing techniques must be used It makes sense that the largest number of channels able to be monitored by a state machine over four clock cycles is four because it needs a clock for each comparison Channel server v is a state machine with one init synchronization state and four monitoring states During the init state Channel Server monitors the data ready line of the serial to parallel conversion and launches into the first comparison state just after the 64 bit channel status bus is updated It has a four bit register whic
99. icine 5th Edition B C Decker Inc 2000 pp 1 C E Mothersill Radiotherapy and the potential exploitation of bystander effects International Journal of Radiation Oncology Biology and Physics Volume 58 Issue 2 February 2004 575 Caenorhabditis elegans Wikipedia The Free Online Encyclopedia http en wikipedia org wiki Caenorhabditis elegans pp 1 B Keeney A Silicon Telescope for Applications in Nanodosimetry Bachelor s of Science Thesis in Physics University of California Santa Cruz CA June 2002 pp 6 H Spieler Semiconductor Detectors Part 2 Lectures on Detector Techniques http physics lbl gov spieler Stanford Linear Accelerator Center Stanford CA September 1998 February 1999 pp 2 3 C F Delaney Electronics for the Physicist with Applications Halsted Press New York 1980 pp 280 168 14 15 16 17 18 19 20 21 122 23 24 25 26 27 E Barberis et al Analysis of Capacitance Measurements on Silicon Strip Detectors Conference Record IEEE Nucl Sciences Symposium San Francisco CA Nov 1993 pp 5 T Pulliam Noise Studies on Silicon Microstrip Detectors Bachelor s of Science Thesis in Physics University of California Santa Cruz CA June 1995 pp 4 11 12 P Horowitz and W Hill The Art of Electronics 2nd Edition Cambridge University Press 1989 pp 432 J Wakerly Digital Design Princip
100. iggered flop Therefore a very elegant way of latching both the positive edge data and the negative edge data is to configure the IOB to grab both edges using its two flip flops one of which is configured in negative edge triggered mode At that point there is no need to keep the negative edge data in negative edge triggered flip flops so the change to one time domain can be made immediately to only positive edge triggered flip flops This reduces the complexity of the design which therefore reduces the possibility of mistakes Four 16 bit flip flops are linked in series and continually latch and shift the data from the DDR IOBs This configuration is known as a shift register or pipeline because data continually shifts through the flip flops See Appendix B 2 for the complete de serialization source code At any one time there are four registered time slices from the front end chip being shifted through the pipeline If one were to look during the correct clock cycle one would see the statuses of all 64 channels at the outputs of the flip flops The outputs of these flip flops are then wired to a single 64 bit flip flop with a clock enable At the appropriate time in the bus cycle the clock enable on this 64 bit register is raised and the status of all 64 channels is captured A strobe called data ready signals to the subsequent stage that the data is present and stable and will continue to be for four clock cycles The following stage sync
101. ight 2004 University of California Santa Cruz Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 R K S R kokk SR R k R R k R S R R SR R RK k R R R K R K R R SR R R R k R R k I SR Ra R SR a R k k 2k 2 k k k k k k k module data handler dout bf empty fifo flag din data ready some flag many flag rd fifo clk res little ur big_wr output 139 01 dout output bf empty output fifo_flag this goes high if one or more fifos are full output many flag some flag little vr big_wr input 163 01 din input data ready rd fifo clk res wire 139 01 CO C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 wire 15 0 many some ch rd fifo full wr little bus wire 31 0 tyme wire many flag some flag assign fifo flag lfifo full assign some flag some bf empty assign many flag many assign little wr wr little bus 99 fifo server v2 fifo_server dout dout rd ch fifo ch rd many many some some Clk clk res res bf rd rd fifo big wr big wr bf empty bf empty d0 C0 d1 C1 d2 C2 43 C3 d4 C4 d5 C5 d6 C6 d7 C7 d8 C8 d9 C9 d10 C10 d11 C11 d12 C12 d13 C13 d14 C14 d15 C15 2 timer timer Q tvme CE data_ready CLK cik SCLR res ki defparam SO group id 5 h10 chan serv
102. in gt q_ stop bin gt q_start 2 x float bin 7n bins bin gt q_start bin gt q_ start delta bin gt q_stop bin gt q_stop delta 119 set delta int set bins TNtuple ptsmout thresh bin fv thresh 1 float fold v pulse 1 float fold thresh 1 int iv thresh count 0 long iEvent 0 float event id channel tot v pulse v thresh long nEvents long ptsmout gt GetEntries TBranch bri ptsmout gt GetBranch event id bri gt SetAddress amp event id TBranch br2 ptsmout gt GetBranch channel br2 gt SetAddress amp channel TBranch br3 ptsmout GetBranch tot br3 gt SetAddress amp tot TBranch br4 ptsmout GetBranch v pulse br4 SetAddress pulse TBranch br5 ptsmout GetBranch v thresh br5 gt SetAddress amp v thresh for iEvent 0 iEvent lt nEvents iEvent if v_thresh gt 070 break ptsmout GetEntry iEvent if v thresh fold thresh set up the new thresh fold threshev thresh fv threshliv thresh count n bins 1 fv thresh iv thresh count v thresh v thresh fv thresh iv thresh count q start v pulse fold v pulse v pulse take care of q stop for the last bin if iv thresh count 0 1 ptsmout GetEntry iEvent 1 fv thresh iv thresh count 1 q stop v pulse set delta amp fv thresh iv thresh count 1 120 print struct fv threshliv thresh count 11 iv_thresh_count
103. in 3 separate chip wide maps See Figs 29 30 and 31 65 for Gain Curve for Channel 41 The average gain is 0 17 0 00 us fC with an offset of 0 82 0 00 us N lt TOT gt us Liao oar i org rg iii D 10 20 30 40 50 60 Q Injected fC Figure 27 A typical TOT gain curve from the DAQ based method of TOT calibration Chip TOT Gain 0 21 0 03 us fC with an offset of 1 26 0 30 us 7 0 3 TOT gain us fC o iy N a u oa 0 1 50 60 PMFE Channel Number Figure 28 Chip wide map of the TOT gain for the range of 6 63 fC 66 Average Chip Resolution at 4 0 fC 0 22 0 08 us 595 3 20 45 8 504 o 40 35 50 60 Channel Number Figure 29 Chip wide map of the TOT resolution for 4 fC Average Chip Resolution at 20 0 fC 0 23 0 06 us wos 50 60 PMFE Channel Number Figure 30 Chip wide map of the TOT resolution for 20 fC 67 Additionally one data set was taken for small charge values between 5 and 2 75 fC to determine the small signal TOT gain Fig 32 shows a typical gain curve from this set Fig 33 shows a chip wide tot gain map for the region of 5 to 2 75 fC As before all histograms and graphs were saved for later analysis 4 2 4 Interpretation of Results Table 4 shows that the matching between the mounted and unmounted detector con figurations is very good m
104. in ps Close 1 void plot chip 143 E PTSM CALIB Source Code Includes include ptsm_constants h include ptsm_include h MAIN int main int argc char argv 1 NI VARS i16 iStatus 0 i16 iRetVal 0 u32 ulCount NUM WORDS u32 ulRemaining NUM WORDS int dev pulser int dev thresh int done flag 0 FILE xf NULL ROOT VARS float bin O f int ibin 0 float ftot O f int iEvent 0 float v pulse V PULSE START int pulse step 0 float thresh var 0 f float v thresh V THRESH START int thresh step 0 unsigned long i j ARRAYS static i16 piBuffer NUM WORDS 144 f fopen out dat w this TTree call is actually required for the ROOT libraries to work the variable name and paramaters are not required these are the programmer s choice TTree root blows ROOT R00T 9 TFile froot new TFile out root RECREATE TNtuple ptsmout new TNtuple ptsmout Here we are now entertain us event id channel tot v pulse v thresh PEINE OMR gt n lt PTSM gt n lt Nn printf Now fortified with 12 vitamins and minerals Wn init daq v pulse v thresh amp iRetVal amp iStatus amp dev pulser amp dev_thresh for v thresh V THRESH START thresh step 0 thresh step NUM THRESH STEPS amp amp iStatus 0 thresh_step v thresh V THRESH STEP 1 se
105. in the data file Brian Keeney 6 1 04 bkeeney scipp ucsc edu Copyright 2004 University of California Santa Cruz Santa Cruz Institute for Particle Physics Natural Sciences 2 1156 High St Santa Cruz CA 95064 SRSRSRSRSRSRSR R SR R R R R R R RK SK SK SK SK SK 3K SR OR SR OR 3K SR SR SR SR SR tubu R R R R R R 3K 3K SK SK 3K A SR K SR SK OR SR OR SR SR SR SR R k k k k ok k ok ok K XX XX o SRRSR SR SR SR SR SR SR R R R R R R R SK SK SK SK SK SR 3K SR OR SR OR 3K SR SR SR SR SR tubu R R R R R R SK SK SK 3K K SR K SR OR OR SR OR SR SR SR SR 21 k k k k k k ok K K The timing diagram for this protocol can be found in the NI6534 manual at NI com or scipp bkeeney The page number is 67 section 3 10 EEE SR SR R R R R R R RK SK SK SK SK SR SR SR OR SR K OR SR SR SR SR SR tubu R R R R R R SK SK SK SK SK SR SR SK OR OR SR SR SR R R k 2K 3K 3K k k k k k module output ctrlr dout req idle rd fifo din ack fifos full res clk fifo empty daq clk parameter n chan 40 this is the width of the fifo coming in parameter packet 16 this is the width of the output bus parameter max count 2 b11 this is the bcd of n chan packet parameter count bits 2 index for def of counter output 15 0 dout output rd fifo req idle input n chan 1 0 din input res clk fifo empty daq clk ack fifos full reg rd fifo idle reg n_chan 1 2 0 s
106. ip very large given the pitch of the detector It also would require a lot of power to drive each wire which in turn would cause heating noise and power supply problems The opposite approach would be to serialize the data which is a technique where each channel gets its own slice of time on one wire 17 This technique called Time Division Multiplexing TDM is very inexpensive because there is only one data output pad on the chip which can make it very small When one does this the effective data rate is decreased by Ge when compared to the parallel technique The technique used by PTSM is a compromise between the two appropriately named serial parallel The PMFE serializes groups of 8 channels cutting the wire count by a factor of eight It also uses a technique known Double Data Rate DDR where data is read out on both the rising and falling edges of the clock For instance if the clock is running at 100 MHz it is possible to read out 200 megabits of data per second per wire This technique is accomplished by using a pair of positive and negative edge triggered flip flops together for each data line This means that the statuses of two channels can be read out in one clock cycle one on the rising edge and one on the falling edge For example channel 0 could be valid during the rising edge of the clock cycle and channel 1 then could be valid during the falling edge of the clock cycle This places higher demands on the system because data mu
107. is attribute PHASE_SHIFT of dcm2 is 64 synthesis attribute DLL_FREQUENCY_MODE of dcm2 is LOW synthesis attribute DUTY_CYCLE_CORRECTION of dcm2 is true synthesis attribute STARTUP_WAIT of dcm2 is false synopsys translate off defparam dcm2 CLKDV DIVIDE 5 000000 defparam dcm2 CLKOUT PHASE SHIFT FIXED defparam dcm2 PHASE SHIFT 64 defparam dcm2 DLL FREQUENCY MODE LOW defparam dcm2 DUTY CYCLE CORRECTION true defparam dcm2 STARTUP WAIT false synopsys translate on 87 R R R S SK SK SK SK SK SR SR SR R SR 3K SR SR SR SR SR SR R R R R kk I I R SK OR SR OR 24 2k 2k 2k 2k This section chops the 1 5 output of dcm 2 into a 1 2 incoming clk duty cycle This chopped clk is clkdata which can be phased wrt fe clk using dcm 2 s phase shift variable k SR SR SR SR SR SR SR SR SR SR SR R R R R R KR SK SK SK SK OR SR OR R SK 3K SR SR SR SR SR SR R R R R R kk 3K 3K 3K 3K 2K 3K 3K KK HE HE 2k 2k 2k 2k always posedge chop_clk begin if res_out up lt 0 else up lt slow_clk end always negedge chop_clk begin if res out down lt 0 else down lt up end assign clk data up amp down synthesis attribute uselowskewlines of clk data is true istatut SR R SR SR SR SR SR SR SR SR R K K R R OS SK SK SK SKS SR SR tu SR 3K 3K SR SR SR SR SR SR R R R R R k R 3K 3K SK SK 3K SK SK K A OR OR SK OR SR SR 2k
108. ise slope stats noise slope err iChannel noise slope err 1 store gain noise void set title array char label TF1 fit int channel int gain float par0 parOerr pari parlerr fit GetParameter 0 par0err fit oGetParError 0 pari fit oGetParameter 1 parierr fit gt GetParError 1 if gain sprintf label Ch 4d Gain 2 124 2 12 mV fC Offset 42 1f 2 1f mV channel pari parlerr parOerr j else sprintf label Ch 4d Noise 2 124 2 12 e Slope 2 1f 4 2 1f channel par0 parOerr pari parlerr 123 set_title_array void print_gain_noise channel_stats stats int iChannel printf Wd Af Af AE AE AE AE hE Af n iChannel stats gt gain stats gt gain_err stats gt gain_offset stats gt gain_offset_err stats gt noise stats gt noise_err stats gt noise_slope stats gt noise_slope_err print_gain_noise J ak SK R SR SR SR SR SR SR K aK R R R R O SK SK SK SK SK SR SR OR OR SK OR SR SR SR SR SR SR R RK R R R RK SK SK SK SK K K K SK I OR SR SR SR 2k 2k 2k 2k 2k 5 CURVES Takes the data bins accordingly and fits s curves to it Then stores the data in fv thresh as electrons fC and mV k SR SR SR SR SR SR SR SR SR SR SR K R R R R R R R SK SK SK SK OR SR SK R SK 3K SR SR SR SR HE ok 24 K 2k 2k void fit s curves TNtuple ptsmout thresh bin fv thresh channel fit fit array long nE
109. ith a detector mounted the PMFE Ch 42 Gain 99 14 0 3 mV fC Offset 6 7 0 4 mV Threshold mV EY CEN CUN o eo e o o o i 2 22 50 Point fC Figure 20 Gain curve for Channel 42 The error is artificially small due to a linear fit to non linear data PMFE Gain Map Gain 93 931007 0 55 72120 o E Eo G 60 Channel ID Figure 21 Analog gain map of each channel on the Test Board 57 oscillated to a point where the data output was non physical The oscillatory behavior becomes infrequent at 125 mV 1 34 fC but at that level it becomes very difficult to probe the small signal characteristics of the amplifiers It is clear from diagnostic tests that the digital ground of the Proto Board is coupling to the input of the PMFE This can be shown by running different designs on the FPGA when a simpler design with Ch 43 Noise 651 0 28 4 e Slope 4 2 17 9 740 o a 0720 z o o o eo x 56383 8 8 TTTTTTTTTTTTTTTTTTTTTTTTTTTTTT o a e e to m b E DA DEI Charge Input fC Figure 22 Noise curve for channel 43 PMFE Gain Map Noise 616 906311 23 91 4400 3 3200 1000 80 600 400 50 60 Channel ID Figure 23 Chip wide map of the noise S very few gates and thus fewer transitions is running the oscillations are significa
110. ividual pulses The downside is that there will be poor resolution on the magnitude of the input charge assuming that the TOT is used as a measurement of charge and not the height of the pulse By lengthening the rise time the precision on charge measurement increases but different charge inputs might overlap making two small charges look like one A related term is the rise time which is the convolution of the shaping with the collection time large one 13 These statements assume that the sampling rate of the signal is kept constant PTSM chose to use a shaping time of 200 ns and a maximum pulse length of 300 us which corresponds to a maximum particle rate of 3 kHz for very large charge 10 2 3 1 Field Programmable Gate Array FPGA Selection for the Readout Controller ROC All digital communication in the PTSM is required to be in a logic family called Low Voltage Differential Signaling LVDS It is a balanced pair of digital signals which minimize interference in the analog portion of the microscope See section 3 6 1 This requirement made selection of the FPGA type very easy because at the time of part selection only the Xilinx Virtex 2 series had the capability of LVDS communication From there it was relatively simple to pick a model in the Virtex 2 series which conformed to the speed and size requirements of the PTSM 2 4 Data Acquisition Hardware The PTSM project wanted a portable and economical way of tr
111. ke communication possible between the ROC and the NI6534 3 6 1 Differential signaling The Low Voltage Differential Signalling family LVDS is used extensively in PTSM At first it is not easy to comprehend why it would be used It is differential so it uses twice the wires it is expensive more than 10 times that of CMOS and one cannot directly interface it with most equipment or parts The reason that CMOS or any single ended logic family is inappropriate for use in mixed signal systems analog and digital on the same board is because ground has a finite non zero impedance When a CMOS signal switches from 0 to 3 3 or 5 V current rushes into or out of ground Depending upon the rise time of that signal very high frequencies are forced into ground The dominant parasitic effect is inductance with an impedance Z iwL causing a level shift of lt Vinterference lt I gt wL This causes the voltage level of ground to oscillate These oscillations can ripple from the ground plane into the analog ground plane they are always tied at at least one point causing it to oscillate 12A typical LVDS to CMOS translator is 3 while a typical 74HC part is 25 43 as well Since the signals of interest here are typically 10 000 electrons a small shift in voltage across the input capacitance can create a large spike in charge This makes it nearly impossible to take measurements of quality What makes differential signals imm
112. les and Practices 3rd Edition Prentice Hall August 2000 pp 540 712 H Johnson High Speed Digital Design A Handbook of Black Magic Prentice Hall PTR 1993 pp 6 27 233 Xilinx Virtez II Platform FPGAs Introduction and Overview Xilinx Inc www support xilinx com 2004 pp 37 DAQ 653X User Manual High Speed Digital I O Devices for PCI PXITM CompactPCI AT EISA and PCMCIA Bus Systems National Instruments Texas 2001 pp 3 8 R Brun et al The ROOT Users Guide v3 10 CERN http root cern ch root doc RootDoc html 2003 pp 1 LVDS Owners Manual A General Design Guide for National s Low Voltage Differential Signaling LVDS and Bus LVDS Products National Semiconductor 2000 pp 1 1 1 2 DS90C031 Data Sheet National Semiconductor http www national com pf DS DS36C031 html pp 1 DS90C032 Data Sheet National Semiconductor http www national com pf DS DS36C200 html pp 1 DS90C401 Data Sheet National Semiconductor http www national com pf DS DS90C401 html pp 1 S Eidelman et al The Review of Particle Physics Physics Letters B592 2004 pp 163 190 H Spieler Electronics 1 Devices and Noise Lectures on Detector Techniques http physics lbl gov spieler Stanford Linear Accelerator Center Stanford CA September 1998 February 1999 pp 2 169 28 National Institute of Standards and Technology E STAR Stopping Power and Range Tables for El
113. lk data i 0 clk datal11 0B clk data 0 OBUFDS daq clk buf I slow clk O daq clk 1 OB daq clk 0 OBUFDS flag bufO I flags 3101 O flagsp 0 OB flagsn 0 OBUFDS flag bufi I flags i 1 O flagsp 1 OB flagsn 1 Software handshaking Buffers OBUFDS done buf I pulse done i D pulse_donel 1 0B pulse_done 0 IBUFDS start buf O pulse start i I pulse start 1 IB pulse start 0 IBUFDS ack buf I ack 1 IB ack O O ack i OBUFDS req buf I req i 0 req 11 0B req 0 Data input buffers IBUFDS din bufO I dp O IB dn O 0 d101 IBUFDS din bufi I dp 1 IB dn 1 O d 1 IBUFDS din buf2 I dp 2 IB dn 2 0 4121 IBUFDS din buf3 I dp 3 IB dn 3 O d 3 IBUFDS din buf4 I dp 4 IB dn 4 0 d141 IBUFDS din buf5 I dp 5 IB dn 5 O d 5 1 IBUFDS din buf6 I dp 6 IB dn 6 0 d161 IBUFDS din buf7 1 dp171 1B dn 71 0 d171 82 data output buffers OBUFDS buf0 I dout 0 O qplO1 0B qn101 OBUFDS bufi I dout 1 O qpl1 0B qn111 OBUFDS buf2 I dout 2 O qpl21 OB qn 21 OBUFDS buf3 I dout 3 O qp 3 OB qn 31 OBUFDS buf4 I dout 4 0 qp141 0B qn141 OBUFDS buf5 I dout 51 O qpl51 OB qn 51 OBUFDS buf6 I dout 6 O qpl61 OB qn 61 OBUFDS buf7 I dout 7 O qp 7 OB gn 71 OBUFDS buf8 I dout 8 O qp 8 OB qn 81 OBUFDS buf9 I dout 9
114. ls of Radiobiology Engineer Ned Spencer B S and Dr David Dorfan Ph D provided a spectacular education in high speed low noise analog design Super Technicians Max Wilder B S and Bill Rowe B S were invaluable in teaching their craft of micro manipulation and electronics prototyping They have always been willing to give freely of their time and knowledge Cyrus Bazeghi M S C E is an extraordinary teacher of digital design and the Verilog Hardware Descriptive Language Without his support both in and out of the classroom the Readout Controller would never have reached an operational level Steve Petersen M S E E P E has been an invaluable teacher mentor and friend throughout the process of implementing P TSM His knowledge of digital systems and their analog characteristics has given the author a rich background and understanding of the field and of the infinite possibilities in engineering Prof Josh Deutsch has been an incredible teacher and mentor for the author s computer programming education The development of the analylitical software developed for this thesis would never have been possible without his enthusiastic and expert support The author also wishes to thank Super Technician Forest Martinez McKinney who in addition to being a wonderful friend to the author did a great deal of the detailed design of PTSM Undergraduate Research Assistant Jason Heimann A A has also done a phenomenal amount of work on the DAQ software
115. ls that they traverse This is accomplished by subjecting a large number of cells to a broadly collimated proton or heavy ion beam and tracking the energy and position of each particle with a silicon strip detector SSD based instru ment This section will discuss the considerations in choosing a design which would effectively measure position and energy of particle tracks in a hostile physical environ ment i e a saline solution in contact with electronics and repeated physical contact with the detector itself and the technologies i e the detector type front end elec tronics readout controller and data acquisition hardware that were utilized in the development of the system 2 1 Physical Requirements for Particle Tracking For effective large scale study of radiation effects in tissue there are four physical requirements that must be satisfied in order to obtain optimal results 1 The spatial resolution must be fine enough to distinguish between two cells 2 The energy resolving ability of the electronics must be fine enough to ensure approximate quality i e energy and variance of the proton or heavy ion beam 3 The detector must be able to withstand the presence and repeated application of biological samples directly to its surface This is important in ensuring the accuracy of the position measurement by the detector due to multiple scattering uncertainties 4 The system as a whole must be economically accessible
116. me in the bus cycle If it doesn t some of the channels will be missed and the rest will be incorrectly mapped due to misalignment of the bus cycle and the latching cycle This synchronization has to happen on startup The state machine uses a clock from which that B CLK is derived and triggers a counter after the rising edge of that clock The state machine begins latching data when the counter has delayed by a set number of fast clocks The exact number of clocks is found by trial and error using jumpers on the Proto Board As stated previously it is desirable to run the front end as fast as possible because the precision on TOT is proportional to the sampling rate Therefore this de serializing block of the ROC should be organized to run as fast as possible One way to ensure a high running speed is to arrange the logic blocks very tightly This way there will be very low skew See Glossary even though the regular routing layer is used Additionally it is possible to latch the data in the input output blocks IOBs IOBs are a slightly different type of CLB which 5The root clock is the fastest clock on the FPGA used to run most of the state machines and services in the ROC 33 additionally contain the physical pin connected to the outside world The signal from the front end chip first comes through the IOB before traveling to the rest of the ROC The IOBs have two flip flops one of which can be configured as a negative edge tr
117. n lt din 3 S lt hold end hold begin S lt updated wr_fifo lt 1 b0 end default begin S lt init res_fifo lt 1 b1 end endcase end end endmodule 108 B 6 FIFO Server J k k ak ak ak ak ak 3k k 3K K kk kk 3K 3K 3K kk I I I I K K 24 2k 2k 2k 2k 2k FIFO SERVER V2 V This module monitors the channel server fifos In normal operation when none of the fifos are more than half full the SM spins through each fifo reading out one event before moving to the next server When it reads an event it writes it to the main fifo which is in turn read out by the readout controller The state machine only performs a read and write when the main fifo is not full In emergency operation when the many flag is high the SM skips over fifos which have only some events and reads out fifos with many events completely This mode persists until the many flag goes down Brian Keeney 6 7 04 Copyright 2004 Santa Cruz Institute for Particle Physics Santa Cruz CA R K kok kk R R S XKS R R R R R R R RK S R R SR SR R k SR R OK k k k k kk kk kkk X X X X XX XX XX module fifo server v2 dout rd ch fifo many some clk res bf rd bf empty d0 di d2 d3 d4 d5 46 47 48 49 410 411 412 413 414 415 big wr parameter num_fifo 16 parameter num_fifo_bits 4 output 39 0 dout output num fifo 1 0 rd ch fifo output bf empty big wr input 3
118. n living tis sue An instrument is needed which can correlate particle tracks with specific cells Using this information detailed and precise models of the effect of radiation tissue can be developed and adapted to cancer therapy and prevention Engineers at the Santa Cruz Institute for Particle Physics designed and implemented a prototype read out system This paper describes and analyzes the characterization process of this prototype The preliminary results indicate that the PTSM will be able to detect fast protons and heavy ions with excellent energy resolution and spatial resolution on the order of a cell nucleus These measurements will aid Radiobiologists in solving complex problems in cancer therapy Acknowledgments P TSM is a collaboration of incredible people who have given selflessly of themselves and have worked many long days to see the prototype to fruition The author wishes to thank Dr Hartmut Sadrozinski Ph D for teaching him the art and science of instrumentation He has treated the author with parent like kindness and given him as many opportunities as possible He is never upset when occasionally these oppportunities turn into failures but rather pushes for lessons to be learned from them It is only in this caring environment that learning truly flourishes The author also wishes to thank Dr Reinhard Schulte M S Ph D for introducing the author to the concept of this microscope and educating him in the fundamenta
119. not connected to any other circuitry the peak voltage would be 2 7 mV assuming 1 5 pF When an amplifier is connected to the strip the effective capacitance becomes much higher decreasing the voltage Since SSDs are depleted in normal operation there is very little quiescent current 16 typically 1 A This is an extremely important parameter because of the signal size What in other applications would be considered to be negligible variations in bias current translate to potentially crippling shot noise at the output of the detector inoise V2QtbiasB where q is the charge of an electron and B is the bandwidth in Hz 16 The shaping time of the amplifier is a reasonable measure of the bandwidth The equation for the noise can be rewritten in terms of noise charge by substituting this value noise 2ibiasT shaping 1 Using the previous values and a shaping time of 300 ns that of the PMFE the noise is 60 electrons which is very small when compared to one MIP Another important parameter of a SSD is the capacitance The effective input capacitance of the ampli fier stage must be much larger than the detector capacitance because otherwise the amplifier will appear as a high impedance node which will cause a long shaping time before the shaping stage which is undesirable from the point of shot noise The spacing between adjacent detector strips or pitch is a trade off between resolution and the number of channels Obviously h
120. nt S lt some ch_count amp many_flag manylch count1l 7read home ch_count lt somelch_count amp many_flag manylch count ch count 1 ch count 3 gch count 2 0 1 ch count 1217 gch count 1 0 ch count 1 ch count 0 ch_count 0 rd ch fifolch count lt some ch_count amp many flag many ch count end read begin rd ch fifo lt 1 b0 wr main fifo lt bf full 17b0 1 b1 S lt bf full read write fifo end write fifo begin wr main fifo 1 b0 empty bit empty bit amp some ch count 1 b1 1 b0 S empty bit amp some Lch count read home rd ch fifo ch count lt empty bit amp some ch count 17b1 1 b0 ch count empty bit amp some ch count ch count 1 ch count 3 amp ch count 2 0 1 ch count 1217 amp ch count 1 0 ch count 1 ch count 101 7ch count 0 end endcase end end endmodule 111 B 7 Output Controller RK SK SK SK SK SK SR R SR SR SR SR SR SR R R R R R OS S SK SK SK SR OR SR OR R SR 3K SR SR SR SR SR SR R R R R R R R SK SK SK SK K OR K SK I SK SR SR SR SR SR 2k 2k 2k OUTPUT_CONTROLLER V The output controller reads out the main fifo data handler v and chops the data into 3 16 bit packets The 16th bit is reserved for error codes so a zero is inserted in the data such that the 16th bit is always empty The error codes are important for maintaining synchronization
121. nted on the Proto Board The Proto Board is denoted by D The Test Board is at C The output data lines from the ROC are shown at A The FPGA is in the socket at 27 Da eu dS A A Ves po abiding ERI A UR Hue vi 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 39 36 37 N16534 timing diagram Photo of the Translator Board Idealized response curve to varying charge input Average response of a comparator with Gaussian noise superimposed on the input charge Typical s Curve for determining the gain and noise at a particular thresholds ses eer CHAIR A ARA bp A ed e Typical gain curve for a range of thresholds In this example the gain 1 07 0 m V MC ea dele oo cac kS ROC SA Oo d RE Tokio de Typical noise values for a range of thresholds Example of an s curve from channel 42 Gain curve for Channel 42 The error is artificially small due to a linear lit to non lineat datas aes RUE RE IV TUR deg Analog gain map of each channel on the Test Board Noise curve for channel 43 Chip wide map of the noise A typical oscilloscope display of the averaged comparator response to an input charge A typical gain curve from the comparator ba
122. ntly reduced Further research is being conducted to mitigate the problem so that the PMFE can be run at a lower threshold with a detector The analog gain and noise give valuable information about the small signal perfor mance of the device The specified gain was 120 kie while the measured gain was 94 z Although the gain is not as high as planned it will still provide a fully functional charge measurement The noise is well below the specification of 1000 electrons with a value of 616 24 electrons This value is linearly dependent on the detector capaci tance due to the noise voltage at the input of the amplifier and will increase with the addition of a detector 27 It was noted during analysis of the gain data that there are several statistically significant outliers in the noise map These include channels 5 10 15 etc 59 4 2 TOT Gain The TOT Gain or TOT calibration is the ratio between the time that a comparator output is high and the input charge for a given threshold To determine the TOT gain the threshold is set to a single voltage well above the noise floor and groups of pulses of increasing charge are injected into the front end The pulse heights gradually increase causing progressively longer TOTs For one charge setting the distribution of TOTs should be Gaussian due to the same noise that causes the step functions to become s curves when measuring the analog gain The mean of the Gaussian gives the average TO
123. ock If everything starts deterministically after the falling edge of the reset pulse this is a trivial task However the DCMs are analog devices which take varying amounts of time to lock onto their clock signals Since two DCMs are cascaded in this design one must wait until both DCMS are locked onto their frequencies Secondly the DCM outputs glitch for the first 10 clock cycles after the LOCKED signal goes high so a delay must be inserted using a counter to remove the possibility of synchronizing incorrectly on the glitches Additionally there is a 32 variable phase between FE CLK CLK_DATA and CLK All of the state machines in the ROC are clocked with CLK but need to start with respect to CLK DATA In the case of a state machine glitching and needing to restart the signal must also be recurring i e a step function cannot be used Therefore a clock which is 1 5 the root clock frequency used to make the B CLK pulse is used to provide the synchronization pulse to SER 2 PAR The clock tree source code can be found in appendix B 1 3 4 2 De serialization of PMFE Data The first step in handling the data is to decode it from eight channels over eight wires to 64 registers each holding the status of a particular channel Since it takes five clock cycles 4 for readout and one reset cycle to read in all 64 channels the 64 bit register is updated every five clock cycles The buffering of the 64 bits has to begin at the correct ti
124. omparator based method of TOT calibra tion The low error 00 is artificial and is due to a linear fit to non linear data 64 The architecture of the DAQ based TOT analysis program Gain vi is very similar to that of Gain v2 although the source files are unrelated see Appendix D The ROOT libraries are extensively used for fitting histogram and graph methods and objects The first section of the program computes the correct binning as above in Gain v2 The second section fits Gaussian functions to the distributions and stores the fitted parameters and errors in an array of structures of arrays as before See Fig 26 for a sample TOT Gaussian TGraphs are made for each channel in which the TOT is plotted on the Y axis and the injected charge is plotted on the X axis The slope of this line is the TOT gain See Fig 27 for an example of a typical DAQ based TOT gain curve Again a chip wide map of TOT gain was produced TOT Distribution for CH 41 Q 43 75 fC MU 8 56 0 01 us STDEV 0 17 0 00 uS 220F 200 1801 m seo Mor 6 120 821007 EURE 2 80 60F 40 20E 0 20 40 60 80 100 120 140 160 180 TOT 1 us Figure 26 A typical TOT distribution from the DAQ based method of TOT cali bration The width of the distribution is directly related to the falling edge of the averaged comparator output in Fig 24 See Fig 28 The resolution at 4 20 and 50 fC is plotted
125. on t check for errors ve don t carel x Clear the block operation x DIG Block Clear iHSDevice iHSGroup Unconfigure group x DIG Grp Config iHSDevice iHSGroup O 0 0 not necessary to clear 6703 156 E 2 PTSM CALIB Constants Defines define _NI_mswin32_ include StdAfx h TRA k k k A k k k k k k k k k k k k k k k k k KK k k k k k ok k k k k k k k k 2K k k k k k k k k k k k k k 2k k 2K k k k k k Constants kok SR R R k R SR k R S R R R k R SR k R R ok SR R SR SR R R R R SR R R R R R kokk R a k k k k k k k kkk kkk const const const const const const const const const const const x const const const const const const const 15 ON O1 N o int WORDS_PER_FRAME 3 int NUM_WORDS 65536 int NUM_CHANNELS 64 unsigned long NUM_PULSES 100 2500 float THRESH_OV_SET 1 1f float V_THRESH_START 100f float V_THRESH_STEP 020f int NUM_THRESH_STEPS 21 float V_PULSE_START 0 50f float V PULSE STEP 0 10f int NUM PULSE STEPS 21 float V THRESH START 060f float V THRESH STEP 010f int NUM THRESH STEPS 15 float V PULSE START 3 2001 float V PULSE STEP 0 080f int NUM PULSE STEPS 20 int MAP 64 1 9 17 25 33 41 49 57 8 16 24
126. on in the s curve corresponds directly to the width of the corresponding Gaussian 49 To understand why error functions s curves give information about Gaussian behavior it is helpful to remember that the value of an error function can be generated by integrating a Gaussian from infinity to X The error function is zero at infinity reaches 5 at the mean of the Gaussian and approaches 1 at negative infinity By measuring pulse occupancy the percentage of input pulses which cause a response at the output for increasing amounts of charge one is effectively keeping X the threshold voltage fixed and varying the mean Increasing charge results in more pulses being above threshold thereby integrating more of the Gaussian If this integration is performed at infinitesimally small increments over all space an error function is formed To find one point in the gain curve 500 pulses were sent into the front end electron ics for each of 20 increasing charges picked to frame the 50 points of the s curves num hits 260 forming s curves starting The occupancy was computed at each point i e This is technically the complementary error function which is 1 the error function For the purpose of this discussion they can be treated identically Response Curve of System with Noise 100 T T T T T r 80 l 4 70 4 60r 4 50r 4 Occupancy 40 4 30r 4 20r 4 el L L L L 1 1 0 0 5
127. ontents into the tissue This causes inflammation and stress in the surrounding cells When it is possible a cell will self destruct by apoptosis Stress conditions such as starvation as well as damage to the cel s DNA resulting from toxicity or exposure to ionizing radiation such as ultraviolet or X rays can induce a cell to begin an apoptotic process 1 The cell gradually shuts down its internal mechanisms and breaks up cellular matter into pieces which are easily expelled from the tissue This causes little or no trauma to the surrounding tissue 7 Apoptosis is a normal function in organisms and is the complement to mitosis or cellular division Most diseases are caused by a malfunction in apoptosis or mitosis 1 It has been estimated that 50 to 70 billion cells perish each day in the average adult human because of apoptosis a process by which in a year each individual will produce and eradicate a mass of cells equal to its entire body weight 8 Bystander Effect The bystander effect occurs when one cell is critically damaged by radiation Instead of just that one cell undergoing apoptosis several cells surrounding the injured cell also undergo apoptosis 9 1 2 Manipulation of Radiation Effects in Tissue It is important to study radiation induced mutations chromosomal aberrations apop tosis and bystander effects because all are mechanisms which are involved in both the causes and treatments of canc
128. ord is corrupted an error code is sent out and the whole event is sent again Note that all digits are in hexadecimal format which take precedence over the ACK error code The first is the start code signaling that the state machine has just come out of reset and is sending its first event The second error code signals a problem in the data acquisition software It is the FIFO overrun word which means that so much data came into the ROC that the FIFO couldn t store it all and that it had to be erased If the DAQ is working properly this condition should never be encountered Handshaking in the Output Controller The NI6534 has specific setup and hold time requirements that must be obeyed for data transmission to be successful See Fig 12 for an example of fully synchronous handshaking and Ref 20 for the timing requirements of the NI6534 An example of a setup time is that data must be present and stable four ns before the rising edge of the clock 20 A hold time is the same concept except that it applies to the amount of time after the rising edge of the clock The output controller makes sure that these setup and hold times are obeyed and that it raises REQ and places data on the bus at appropriate times See Appendix B 7 for the complete source code for the output controller 39 3 4 5 Calibration Controller Originally it had been planned that the DAQ PC would control both the readout of data with the NI6534 and the inj
129. packets to the NI6534 and performs error handling if there is a problem with either the FIFO or the NI6534 It performs all of these tasks in one finite state machine called output ctrlr v Appendix 36 Correct 1213 415161718 Error 1 213 X15161718 Result 1 1213 5116171819 Table 1 Diagram showing how data corruption occurs Event 4 was lost by the N16534 causing a shift in the data For example what is really the time stamp of one event could be interpreted as the channel ID of the next event B 7 Packet Creation in the Output Controller The NI6534 s data bus is 16 bits wide while the event length in the ROC is 40 bits Therefore it is necessary to package the data into three packets of 10 15 and 15 the 16th bit of the bus is reserved for error codes These packets must then arrive in succession at the NI6534 in order for them to be reassembled into the correct event A missed packet corrupts all of the data in the file following the corruption See Table 1 Therefore it is important to send out codes that subsequent software can look for to synchronize with the start of an event It is too wasteful to send a code signaling the start of every event Rather an error code is sent out when the state machine starts OXAAAA any time that there is an error in the communications protocol between the ROC and the NI6534 OXBBBB and if the FIFO gets overrun 0xCCCC 5 Note that the 16th bit i
130. periods of time which is a higher throughput than Firewire or USB 2 0 yet with a much simpler protocol 3 5 1 Fully Synchronous Handshaking The National Instruments PCI 6534 is a 5V CMOS Digital input output PCI card with 32 bidirectional data lines and six control lines It is capable of acquiring data in a number of protocols the most reliable and robust of which is called fully synchronous handshaking FSH One can make an analogy to FSH with a water balloon toss Nobody wants to drop the balloon Every throw of the balloon counts If a thrower wants to initiate a toss s he makes sure that the sender is ready by calling out If the sender is not ready nothing happens otherwise the toss occurs The same is true of FSH The PC the receiver has control of a line called ACKnowledge Any time ACK is high the ROC is free to send data The ROC might not always be ready however so it has a control line called REQuest When ACK is high and REQ is high A1 the PC will latch whatever is on the data bus at the next rising edge of the clock sent by the ROC Figure 12 shows the timing diagram for this process Note that the card is limited to certain period setup and hold time constraints that must be obeyed in addition to the handshaking protocol 20 i fpc te tow PCLK mooo 6S M tha si ACK Y mm ja ts eund REQ ROOK OOOO tqis lain gt Data in Valid AOS X Figure 12
131. r 0 strcat data names i fit results gl PSetTitle data names i c gt Update gain ps Close c Clear gi gt Clear D0 THE PAPER DATA TGraph g2 new TGraph 26 paper charge paper data g2 gt Draw Ax pol gt SetLineColor 2 pol gt SetLineWidth 2 g2 gt Fit pol RQ 5 63 g2 gt GetYaxis gt SetTitle TOT us g2 gt GetXaxis gt SetTitle Q fC 164 TPostScript gain ps paper data ps 112 gain ps Range 24 16 set x y of printed page sprintf fit results Analog TOT Data G 23 2f 43 2f Offset 3 2f 3 2f pol gt GetParameter 1 pol gt GetParError 1 pol gt GetParameter 0 pol GetParError 0 printf Analog Data printf 3 2f 13 22 23 2f 3 2f n pol gt GetParameter 1 pol gt GetParError 1 pol gt GetParameter 0 pol GetParError 0 g2 gt SetTitle fit_results c gt Update gain_ps Close 1 g2 gt Clear end_main 165 F 1 COMP GAIN Output Data Set or Parameter ch_1_pulse_100mv_low 0 26 0 86 1 47 2 00 2 52 3 08 3 54 3 94 4 34 4 78 ch_4_pulse_100mv_low 0 45 1 20 1 89 2 60 3 20 3 80 4 30 4 80 5 26 5 64 ch 10 pulse 100mv low 2 62 3 22 3 70 4 22 4 74 5 20 5 52 5 94 6 34 6 64 ch 15 pulse 100mv low 1 96 2 58 3 12 3 62 4 06 4 50 4 84 5 28 5 58 5 92 ch 1 pulse 100mv high 2 04 3 96 5 25 6 55 7 65 8 80 10 00 11 20 12 50 13 90 ch 4 pulse 100mv high 2 47 4 68
132. ready data ready rd fifo ch rd 5 Wr fifo wr little bus 5 tyme tyme Clk clk res res Jis defparam S6 group_id 5 h16 chan_server S6 dout C6 some some 61 many many 61 fifo full fifo full 6 din din 27 24 data readv data readv rd fifo ch rd 6 tyme tyme Wr fifo wr little bus 6 Clk clk res res defparam S7 group_id 5 h17 chan_server S7 dout C7 some some 7 102 many many 71 fifo full fifo full 7 din din 31 28 data ready data ready rd_fifo ch_rd 7 wr_fifo wr_little_bus 7 tyme tyme clk clk res res defparam S8 group_id 5 h18 chan_server S8 dout C8 some some 8 many many 81 fifo full fifo full 8 din din 35 32 data ready data ready rd fifo ch rd 8 Wr fifo wr little bus 8 tyme tyme Clk clk res res Jis defparam S9 group_id 5 h19 chan_server S9 dout C9 some some 191 many many 91 fifo full fifo full 9 din din 39 36 data ready data ready rd fifo ch rd 9 Wr fifo wr little bus 91 tyme tyme Clk clk res res defparam S10 group_id 5 h1a chan_server S10 dout C10 some some 1101 103 many many 101 fifo_full fifo_full 10 din din 43 40 data ready data ready Wr fifo wr little busl101 rd fifo ch rd 10 tyme tyme Clk clk res r
133. roller attempts to send these bits After successfully sending them the output controller shifts the contents of the shift register down by 16 bits overwriting the word that was just sent out with bits 31 16 and leaving bits 41 32 empty This continues until all three packets have been successfully sent See Table 2 If there is an error during this process the event is not dropped After having serviced the error the output controller reloads the same event from the output of the FIFO this time not strobing the FIFO RD line and attempts to shift out the entire event again The only exception to this is when ACK is low for a long time in which case the FIFO will fill up in turn causing the readout controller to issue a FIFO error code See Fig 3 for a diagram of normal error handling Error Handling in the Output Controller When an error such as those in troduced above occurs the output controller loads the appropriate error code into the output register and waits until it is able to send it to the NI6534 In the case of ACK falling see section 3 5 1 an ACK error is registered when ack is low during the rising edge of the fast clock 50 MHz There are two other error codes both of 38 Data Bus Interpretation AAAA Start Error Code 0123 Data 4567 Data BBBB ACK ERROR send same event again 0123 Data 4567 Data 89AB Successful transfer of event Table 3 Diagram showing error handling When an w
134. rticle Tracking Silicon Microscope PTSM it is now possible to correlate specific particle tracks and measurements of the LET with individual cells Thus a very precise study of radiation effects in tissue is possible 3 This paper will explain the need for the PTSM define the requirements that result from these needs describe the development process of the instrument and present the results of a prototype characterization 1 1 Biological Motivations for the Development of the PTSM Radiation can cause damage in cells which can lead to the death of an organism 1 This damage manifests itself in many ways 4 The four effects which are of greatest interest to this project are as follows 1 Mutations Mutations occur when DNA is ionized in such a way as to remove or change a base pair in the DNA lattice This results in a different genetic code being interpreted by the cell This is often to the detriment of the cell and is a cause of cancer 5 Chromosomal Aberrations Aberrations are mutations which are physically manifested in the shape of the chromosomes It is useful to study aberrations because they are correlated to radiation dose and linked to larger physical prob lems in organisms 6 Apoptosis If a cell is critically damaged and is not able to repair itself the cell can either undergo necrosis or apoptosis Necrosis is harmful to the surrounding tissue because the cell walls simply burst releasing the c
135. s to the amplifier inputs These capacitors are switched using jumpers on four stake headers in groups of four four calibration capacitors for each of four buses In this way a very large charge can be injected with very low voltages minimizing channel to channel crosstalk at the inputs of the amplifiers For example injecting 20 fC with the external capacitors 2 2 pF requires only 91 mV while the internal capacitors 50 fF require 400 mV to inject the same charge The maximum rate of change of voltage between two conductors where one is being driven and the other is quiescent 26 is 18 dV AV Where AV is the difference in voltage between a logic 1 and and the rise time Tp is 18 T 2 2Z C 10 Zo is the characteristic impedance of the driving conductor and C is the load capac itance The maximum current crosstalk is derived below 11 dQ dV 13 dV Icrosstalk Cmutual r 14 Where Cinutual is the parasitic capacitance between channels and Ccalibration is the capacitor through which charge is injected The total current crosstalk in terms of capacitance is then dQ AV aaa OC C mutual dT 2 27 Calibration 15 which clearly shows that there are gains to be made by both increasing the capacitance and decreasing the voltage The total crosstalk savings can be seen by comparing the two crosstalk errors for an equivalent amount of charge input Q Q 16 27 C x Vj
136. s a very specific clocking structure Fig 7 and the data acquisition card follows a strict fully synchronous handshaking protocol Since there is no buffering or handshaking between the ROC and the front end chip it is essential that the ROC have the capability to send the front end clock and B CLK to know when data would be arriving back at the ROC to latch it correctly and to process it quickly enough so that there are no overruns There is a delay between the time when the front end clocks are sent and when data is received at the ROC due to the propagation delay in both the wires and chips See Eq 22 Tactey Ex BAT x VAS 22 c is the speed of light is the dielectric constant FRA PCB is 4 5 18 and 1 is the 29 distance of the PCB trace It is necessary to be able to adjust the phase between the clock which latches the data in the ROC and the clocks that are sent to the front end chip so that correct data can be acquired By looking at the front end DDR registers one can vary the phase until the correct data is latched i e data associated with a e p ISCIPP LLU PTSM Testboord 1 AI noon Em XU 4 T m as c La b t Fa H Figure 10 Photo of the Test Board A shows the PMFE The detector bias ring is marked by B If a detector is used a window is milled out removing region O Within C are the 16 external calibration capacitors The detector bi
137. s high for all of these words Since it is possible for the time stamp to have any of these values in both the high and low two byte packets the 16th bit is reserved only for error codes and the 40 bit data packet is split into 10 15 and 15 bit packets In this way it is impossible for a time stamp to appear to be an error code During normal operation the output controller reads the FIFO by strobing the FIFO RD port of the FIFO This causes a new event to appear at the FIFO output The output controller TThere are 7 bits for 128 channels or 2 PMFE s 1 transition bit and 32 time bits for roughly 7 minutes of operation without a repeat time stamp For a brief description of hexadecimal notation see Appendix A 9A word is a string of digital numbers 37 Data Bus Interpretation AAAA Start Error Code 0123 Bits 15 0 of first event 4567 Bits 31 16 of first event 89AB Bits 47 32 of first event CDEF Bits 63 48 of first event Table 2 Diagram showing the first event to be read out Note that all digits are in hexadecimal format See the Glossary for an explanation of hex notation then loads the 40 bit word into its shift register As it loads the 40 bit word it inserts two zeros between bits 14 and 15 and between 28 and 29 so that the high bit of every 16 bit packet is zero in compliance with the error code rule The lowest 16 bits of the shift register are also the output bits The output cont
138. s of Silicon Strip Detectors 16 3 2 The Particle Microscope Front End PMFE Application Specific Inte grated Circuit A SIG du edgy Put s qx dor ee Das 20 3 2 1 Charge Amplification 20 3 2 2 Digital Topology inthe PMFE 22 3 8 The PTSM Test Board 26 3 4 The Readout Controller 29 3 4 1 Timing Services 32 3 4 2 De serialization of PMFE Data 33 3 4 3 Buffering the Data Zero Suppression 34 3 4 4 Output controller 36 3 4 5 Calibration Controller 40 3 5 The N16534 Data Acquisition PCl Card 41 3 5 1 Fully Synchronous Handshaking 41 3 5 2 Readout Software SU 2222s s 42 3 6 The PTSM Translator Board 43 ili 3 6 1 Differential signaling 3 6 2 Design of Translator Board 3 7 External Lab Equipment Characterization 4 1 Determination of the Analog Gain and Noise of the PMFE Experimental Method 4 1 2 Statistical Analysis 4 1 3 Computation 4 1 4 Interpretation of Results 42 TOT Gain 4 2 1 Experimental Method 4 4 4 1 1 4 2 2 Statistical Analysis 4 2 3 Computation Interpretation of Results 4 8 Radiation Source Measurement 4 2 4 Conclusion Conclusion B 1 B 2 B 3 B 4 B 5 B 6 B 7 A Glossary Clock Tree Serial to Parallel Conversion Pulse Handler
139. sed method of TOT cal ibration The low error 00 is artificial and is due to a linear fit to Honslnearmdabtab RTE en a hee A typical TOT distribution from the DAQ based method of TOT cali bration The width of the distribution is directly related to the falling edge of the averaged comparator output in Fig 24 4 typical TOT gain curve from the DAQ based method of TOT cali brAti ni s x ia pan S la ak bens MU aa Hae a a ET Chip wide map of the TOT gain for the range of 6 63 fC Chip wide map of the TOT resolution for 4 fC Chip wide map of the TOT resolution for 20 fC Chip wide map of the TOT resolution for 50 fC A typical TOT gain curve for the charge region of 5 to 2 75 fC The chip wide TOT gain for the region of 5 to 2 75 fC The errors are artificially low The actual error on the gain is close to 05 To Intensity map for data taken with uncollimated 90Sr source Note that channels 0 and 63 were poorly behaved and so they were cut from the histogram There are two dead strips channels 6 and 15 TOT spectrum for the uncollimated 9 Sr source measurement Intensity map for data taken with the collimated Sr source Note that channels 0 and 63 were poorly behaved and so they were cut from the histogram There are two dead strips channels 6 and 15 TOT spectrum for the collimated 70Sr source measurement vii List of Tables 1
140. ses one of the depleted PN junctions in the detector a small bursts of charge is liberated which the front end amplifier collects and amplifies A single sided detector was used for the prototype because it is identical with respect to analog characteristics while being much easier to implement mechanically 3 1 1 Properties of Silicon Strip Detectors Silicon Strip Detectors SSD s are arrays of diode strips The fabrication of these strips is usually accomplished by implanting strips of P type silicon on N bulk The diodes are back biased depleted with 1 40 MQ resistors connected to ground The backside is biased at 100 V The strips are then capacitively coupled to the signal connections by placing an aluminum oxide layer over the strip with a silicon oxide layer sandwiched between the aluminum and the strip The capacitive load seen by the input of the amplifier varies depending on the geometry of the detector but typically it is 1 2 pF cm 14 When a particle traverses a depleted junction it deposits a certain amount of energy which in turn liberates e e pairs These charges flow up their potentials creating a very brief spike in current This current is very small and is most commonly referred to in terms of charge not current or voltage A typical signal of one Minimum Ionizing Particle MIP is about 25 000 electrons 15 Assuming a 1 cm detector and a 25 ns collection time the average current is 160 nA If a detector were
141. similar to that of ana log gain and noise Two different thresholds were used for the TOT calibration The threshold used for calibration should be the same one used in operation of the instru ment because the TOT gain can vary greatly between thresholds for small charges The Test Board with a detector is only stable at 125 mV 1 25 fC and above so the TOT was calibrated at that threshold The Test Board with no detector is stable at 100 mV 1 fC and so it was calibrated at that both 100 and 125 mV Each calibration bus was tested separately as in the characterization of the analog gain Again pulses of increasing amplitude were injected into the PMFE The TOT signals resulting from these pulses were measured using two methods First to ensure that the analog behavior of the amplifier and comparator were correct a pico probe was used to measure both the incoming calibration pulse and the comparator output be fore begin digitized for 4 unrelated channels The calibration pulse was measured at the bond pad where the calibration pulse enters the chip This ensured that any inaccuracies in the pulser or attenuators would be accounted for The comparator outputs were measured at special probe pads that were included for debugging on seven of the channels Channels 1 4 10 and 15 were tested None share a cali bration bus The output of the pico probe was fed to a Tektronix 4195A digitizing oscilloscope While triggering on the pulse generator
142. smout gt Project h_ name tot h cut h i_pulse gt Draw h i pulse Fit g Q set h label h i pulse h label g s_gauss gt channel s pulse pulse indexli pulsel store gauss fit g s gauss i pulse Int t type 112 landscape sprintf name gauss curves ch d q f ps s_gauss gt channel S pulse pulse indexli pulse TPostScript ps ps name type ps Range 24 16 set x y of printed page c i pulsel PUpdate ps CloseO void fit gauss J okokokokokokokokokolokookolokolokolokolokolokolokolokolokookolokolokookolokololokokookololokololokolokojolololelolololeloejololelok VOID FIT GAIN RES fit lines to the gain and resolution k SR SR SR SR SR SR SR SR SR R K R R R R R R R SK SK SK SK OR SR OK R SR 3K SR SR SR SR SR SR R kk SK SK OR OR OR HO void fit gain res s fit gauss s gauss s pulse index x s pulse float x final gain float x final 1 139 char ps label 128 TF1 x pol new TF1 pol poli 0 MAX CHARGE TF1 x polo new TF1 polo polO O MAX CHARGE s gauss c gain new TCanvas s gauss g gain new TGraphErrors s pulse num pulses S pulse q inj s gauss gauss mu NULL Ss gauss gauss mu err s_gauss gt g_gain gt GetYaxis gt SetTitle lt TOT gt uS s_gauss gt g_gain gt GetXaxis gt SetTitle Q Injected fC s gauss 2g gain oDrav As pol PSetLineColor 2 pol gt SetLineWidth 2 polo gt
143. ssible locations X1Y1 X1Y2 X2Y1 X2Y3 for only two valid hits See Fig 1 This can be overcome when using a double sided detector provided that the difference in the charge deposition of the two particles is larger than the resolution Then the two legitimate pairs each with matching energy can be distinguished from the ghosts The PTSM project elected to use silicon strips in the instrument because of the savings on detector mass and complexity Figure 2 shows a conceptual schematic of the detector geometry The proton beam enters the research room horizontally The detector is positioned with its normal axis aligned parallel with the beam Biological samples are deposited on the upstream face of the detector Particles pass through the biological samples and then through the detector Figure 1 Schematic diagram of ghosting The two legitimate events are indistinguish able from the two that are nonexistent When measuring the charge deposited by the tracks in a double sided detector it is usually possible to correlate the two X and Y measurements such that the ghosts can be removed kid Beam Biolo Samples Test Board PMFE Figure 2 Schematic diagram of the PTSM detector geometry 2 3 Front End Chip Specification In the PTSM architecture the front end chip amplifies and digitizes the signals coming from the silicon strip detector SSD It then sends the digital channel status information to the rea
144. st be latched twice as fast cutting all slack time in half Figure 7 is a timing diagram of how data is clocked out from the front end chip Note that on every signal line there are two channel statuses transferred for every clock cycle Below Fig 8 is a schematic of part of the digital section of the front end chip This block repeats 16 times in the chip 8 for the even channels 8 for the odd and is basically 4 SR latches and a four bit shift register Note the signal called B_CLK 23 This is a reset pulse which determines the bus cycle The time during which B_CLK is high before clock is high loads the shift register The time when the two signals are overlapping clears the SR latches When B CLK falls the shift register stops loading and begins to shift out the data on each edge The data is clocked out over four cycles followed by one cycle of dead time Dead Time When both the B CLK and CLK are high see Fig 7 the front end latches are in reset If comparator goes high during the reset and continues to be high M2 1 FDR FDR 1 22 o Lx em i M2 1 f R M2 1 FDR mem 3 o A a po T n Ae H 35 ox piat T A M
145. t 01 ovset 2 3f ocp on ovp on v thresh THRESH OV SET ibwrt xdev thresh V word strlen V word Fun Strings OCP ON turns overcurrent protection on OVP ON ISET 1 0 sets current to 1 amp VSET 1 0 sets voltage to 1 amp OVSET 1 0 sets overvoltage protection at 1 volt EA void config thresh ps paaa E kkk kkk kk kk kkk k kkk kk k kk kk k Kk k k kK kk k K Kk K K KK set thresh ps sets V THRESH using power supply NOT DAQ card kkk kk kkk kkk kk kkk void set_thresh_ps float v_thresh int dev_thresh char command 1024 if v thresh gt THRESH OV SET v thresh THRESH OV SET sprintf command vset 4 3f v thresh ibwrt xdev thresh command strlen command void set thresh ps R ok ok SR SR SR SR SK SR SK SR R ok R SR SR SR SR SK SR I AK R R R SR SR SR SR Ok k k k k k k send start sets the line corresponding to the k calibration start pin of the FPGA start state k specifies if the line is lov 0 or high 1 kokk kk kk R SR SR SR SR SR SR k kk R R SR SR SR SR SR SK SR R R R SR SR SR SK SR ok k k K R R SR SR SR k k k k k void send start ii6 iStatus i16 iRetVal int start state x if start state 0 start state 1 iStatus DIG Out Line iDACDevice iDACPort iLineStart start state iRetVal NIDAQErrorHandler iStatus DIG Out Line ilgnoreWarning 148 void send reset ii6 iStatus i16 iRetVal
146. t thresh ps v thresh amp dev thresh printf set thresh ps 3f n v thresh ProcessSystemEvents ProcessSystemEvents thresh var 0 8f417 8f v thresh for v_pulse V PULSE START pulse step 0 pulse step lt NUM PULSE STEPS amp amp iStatus 0 pulse step v pulse V PULSE STEP 1 set pulser voltage v pulse amp dev pulser printf set pulser voltage 3fw v pulse ProcessSystemEvents ProcessSystemEvents for i 0 i NUM PULSES i 1 _getche 145 read_data amp iStatus amp iRetVal piBuffer amp ulCount send_start amp iStatus amp iRetVal 1 done flag 0 j 0 while done_flag 1 ProcessSystemEvents poll done amp iStatus amp iRetVal amp done flag ttj printf poll done returns dw done flag printf poll done returns d after d polls n done flag j send start iStatus amp iRetVal 0 halt read iStatus amp iRetVal amp ulRemaining ProcessSystemEvents parse data piBuffer amp ulRemaining amp ulCount iEvent v thresh v pulse ptsmout f iEvent cleanup The device s is are taken offline ibonl dev_pulser 0 ibonl dev_thresh 0 froot Write if f NULL fclose f printf Press any key to continue n getchar return 0 int main 146 F 1 PTSM CALIB Include File include ptsm constants h RK k SK SK SR SR SR R
147. the NI6534 Fig 13 shows the completed Translator Board The single ended CMOS lines are fed via the blue and black cable directly to the PCI based NI6534 The 3M type ribbon cable connects the Translator board to the ROC via the Proto Board 3 7 External Lab Equipment Two AMREL power supplies power the instrument One supplies 7V to the Xilinx Proto Board which in turn regulates and supplies 3 3V 2 5V and 1 5V to the FPGA The other supply is 5V for the instrumentation amplifier and the CMOS switches for the calibration A Keithley 237 High Voltage Source sets the 100V bias voltage 45 on the detector The voltage is carried to the board on twisted pair wire The wire is choked with 20 turns on a large ferrite is current limited with a 1 MQ resistor and bypassed with a 47 uF XTR capacitor The filter s 3dB point is well below 1Hz and is implemented on the Test Board in close proximity to the detector A LeCroy Pulse Generator controlled via GPIB provides the calibration pulses The signal is first attenuated by 55 dB before entering the Test Board to allow for more precision in charge injection 46 D PTSM TRANSL L ZHANG 11 2 Figure 13 Photo of the Translator Board AT 4 Characterization The data and analysis reviewed in this section is an examination of the first attempt at characterization of a prototype PTSM Three separate rounds of testing were con ducted The first test sought to characterize th
148. til the first event arrives Once the fifos are empty and the controller is idle i e the event is read out done will go high If start remains raised done will go low again once the fifos are populated or the controller is busy When start is forced low done will remain low until the fifos are empty and the controller is idle after which it will go high and inhibit the fifos S SR SSR SR S K SR SR oko oko ke R RK SSR S K SR SR R SR S R S kk kk R SR SSR SR kk SR R kkk kkk k 2 k kkk k k k k k k 93 V LELILELELILELELLLELELELELELELELLELELELLLLELELLLELELLLLLLLLLELLLLLLLES IN A NUTSHELL pulse_ and cal_ jumpers are pulled up and can be forced to ground pulse_jumper should be put in grounded when you want 100 pulses trig is the trigger output to the pulser trig_in goes low when the pulse is done cal_jumper should be grounded when pulses are not wanted i e when doing source measurements with cal_jumper grounded the start line becomes an inverted inhibit line i e start high inhibit low the done line becomes an inverted busy line i e done low busy high k k k k k k k k k K k k k k FK k ok k k ok ook k ok k k k k k K K OH k k k ok k FK k k OH k k k k k k k k k ok k k k k k FK k K k k K K ok k kk Brian Keeney 6 9 04 bkeeney scipp ucsc edu Jason Heimann 6 1
149. tinguished with an additional five bit channel tag 5 bits 2 bits in the FIFO 128 channel IDs The FIFO s are each equipped with some many and full flags The some flag is true whenever the FIFO is not empty The many flag is true whenever the FIFO is half or more full and the full flag is true when the FIFO is full When none of the many flags are true the server loops over each FIFO reading out a single event if there are any to be read If one or more many flags are high the server skips over any FIFO s which only have a some flag and completely empties those which have a many flag If there is more than one many flag the server will empty the first one that it finds and skip over some FIFO s until it finds and empties the remaining many FIFO s The some FIFO s are still read out after all many FIFO s are empty and no data is lost unless a FIFO is overrun 3 4 4 Output controller Inserting a FIFO between the input and output stages effectively divides them into distinct blocks which are not synchronized If the input block has no data it writes nothing to the FIFO If the FIFO is empty the output controller waits in an idle state ready to send data to the DAQ The output controller performs four main tasks it reads data from the FIFO when the FIFO is not empty it divides the data up into packets that the NI6534 can handle it sends these
150. to Fig 5 for a logarithmic representation of the pulse shapes This discharge time must be greater than the shaping time Otherwise charge will be removed from the input of the amplifier before it has been fully integrated The discharge time must be short enough so that the charge is completely removed from the input before the next particle arrives Otherwise there will be overlap between the two charges which will cause inaccuracies in the measurements Fig 6 shows a schematic of a charge sensitive amplifier The gain of the amplifier is inversely proportional to the value of The gain of this amplifier can be derived 20 as follows The charge on will be the same on both sides Therefore Qi Qf Cy Vout 7 in T Figure 5 Charge in a detector I is the current from the detector while the charge is being collected V is the voltage at the input of the amplifier The voltage rises with increasing charge and slowly decays Here the time scale is logarithmic The duration of I is typically 25 ns while the duration of V is much longer and depends on RampCamp det Figure 6 Schematic of charge sensitive amplifier 21 The gain is the voltage output compared to the charge input Rearranging eq 7 V 1 Gain A E 8 3 2 2 Digital Topology in the PMFE Having amplified and digitized the charge impulses the next and final task of the PMFE is to register the digitized channel statuses and transmit them to the
151. to researchers in the general radiobiology community 2 2 Architecture Development The relatively small scale of the PTSM project allows for a simpler and more compact architecture than that of most particle physics experiments The mass of readout and support electronics required is minimal because only a small active area lt 1cm is needed to study hundreds of C elegans very few channels 1000 The small number of channels coupled with a low event rate 1000 Hz means that the data acquisition system DAQ can be managed by a PC instead of a larger CAMAC or server farm Building a front end from discrete commercial parts is nearly impossible due to the size of the detector and the parasitic electrical effects that scale with increasing size Therefore a custom front end chip was designed and laid out at SCIPP by Ned Spencer The analog blocks of the design are based on those in the Gamma Ray Large Area Space Telescope GLAST The digital blocks are new and reflect the size of the experiment It was decided that a Field Programmable Gate Array FPGA would be used to implement the Readout Controller ROC FPGA s are arrays of Configurable Logic Blocks CLBs which can emulate any design that fits on the chip The ROC is used to do all of the digital processing of the signals created in the detector and analog front end electronics Because of the relatively small data output of the detector electronics it was decided that a commer
152. une to these shortcomings is that as one wire is pulling current out of ground the other is pushing current in If the wires are correctly matched for impedance in a voltage source the currents will exactly cancel In 1994 National Semiconductor developed a new family called Low Voltage Dif ferential Signaling LVDS which improved all of these shortcomings 22 It runs on a single positive supply and uses very little power no bipolar technology 22 Additionally the outputs are currents not voltages so the net current into ground is always nullified Because its noise immunity is so good it can afford to switch on very narrowly defined noise margins running at 3 5 mA across 100 Q dissipating only 3 5 mW in contrast to 75 mA and 285 mW per channel in ECL a competing differential logic family 221 There are drawbacks to using LVDS over CMOS One is that it uses twice the wires and it uses considerably more quiescent power There is no qui escent power dissipation in CMOS and only Chats owf is burned in switching In PTSM LVDS is used for all data clock and control lines between the PMFE ROC and Translator Board 3 6 2 Design of Translator Board It was clearly necessary to use LVDS for all digital communication to and from the PMFE and ROC for acceptable analog performance Therefore it was necessary to make a converter card that would switch between LVDS going to and coming from the ROC and 5V CMOS going to and from the NI6
153. vents int iv thresh count int iChannel float event id channel tot v pulse v thresh float mu mu err sigma sigma err gain gain err noise noise err char hname 128 char hcut 128 char hlabel 128 char pslabel 128 axlabel 128 int current thresh int index TF1 x ferf new TFi ferf 2 1 24TMath Erf C x 012 112 22 0 01 9 99 TF1 x ferf new TF1 ferf 124 1 2 1 2 TMath Erf C x 012 1122 2 0 01 9 99 make a histogram and canvas for each s curve TH1F h NUM CHANNELS x MAX NUM THRESH TCanvas c NUM CHANNELS MAX NUM THRESH this array of structs holds the fitted parameters set up the pointers TBranch bri ptsmout GetBranch event id bri gt SetAddress amp event id TBranch br2 ptsmout gt GetBranch channel br2 gt SetAddress amp channel TBranch br3 ptsmout GetBranch tot br3 gt SetAddress amp tot TBranch br4 ptsmout gt GetBranch v pulse br4 SetAddress v pulse TBranch br5 ptsmout GetBranch v thresh br5 gt SetAddress amp v thresh printf fitting s curves to channel ferf gt SetParameters 1 0 0 1 500 for current thresh 0 current thresh iv thresh count current thresh 1 if iChannel gt 9 printf b printf b d iChannel fflush 0 index NUM CHANNELS current thresh iChannel sprintf hname h Ad index sprintf hcut v_thres
154. wire res_dcmi dcmOlocked wire res dcm2 dcmilocked assign res out dcm2locked amp amp timer assign slow clk div5 BUFG slow buf I div5b 0 slow clk bufg synthesis attribute uselowskewlines of slow clk is yes 84 7777 777 7 77 77 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 DCMO Deskews the input clock x 77 17 0 7 1777177 7777177 7771771117 EL Bg M ELI EP TA 77 this is the feedback loop for dcm0 BUFG dcm fb I dcmO clk 0 0 c1k BUFG dcm in buf 1 1 in O dcm 0 in DCM dcmO CLKFB clk CLKIN dcm in DSSEN gnd PSCLK gnd PSEN gnd PSINCDEC gnd RST res_dcm0 CLKO dcmO_clk_0 LOCKED dcmOlocked synthesis attribute DLL FREQUENCY MODE of dcmO is LOW synthesis attribute CLKOUT PHASE SHIFT of dcmO is fixed synthesis attribute PHASE SHIFT of dcmO is O synthesis attribute DUTY CYCLE CORRECTION of dcmO is true synthesis attribute STARTUP WAIT of dcmO is false synopsys translate off defparam dcmO CLKOUT PHASE SHIFT FIXED defparam dcmO PHASE SHIFT 0 defparam dcmO DLL FREQUENCY MODE LOW defparam dcmO DUTY CYCLE CORRECTION true defparam dcmO STARTUP WAIT false synopsys translate on 85 HIPH HTTP P BP P P P ARRETE P LP LET PEEL PEAT AT EA ATA DCM1 is just a phase shifter between the root clk and the FE system 777 7 7 7 7 7 7 7777
155. y 2 2 seconds Heavy ion sources are not as well defined but the proton beam provides a reasonable base line estimate of the particle rate When the DAQ is ready to start taking data it raises an asynchronous start line which is continuously polled by the ROC The ROC then begins allowing events from the PMFE to be interpreted and sent to the 13 DAQ The data from the PMFE are the time division multiplexed statuses of all 64 channels The statuses are transferred over 8 signal pairs in four clock cycles at Double Data Rate DDR The ROC looks for transitions in each channel and sends an event packet holding the channel the direction of the transition and the time to the DAQ An event in PTSM is defined as a transition from low to high or from high to low of a latched comparator output Data is transferred from the ROC to the DAQ card National Instruments 6534 via a fully synchronous handshaking protocol see Fig 12 Section 3 4 4 and Source 20 When data needs to be cleared from the RAM on the N16534 the NI6534 lowers an ACKnowledge line The ROC buffers data in a first in first out buffer FIFO until the NI6534 is able to receive it again This should not be confused with dead time it merely means that data is stored in the on TRIG OUT 55 Pulse 55 1x2 CaL DONE 1x2 Pulse TTA Readout SIARI 12 Pata Controller Xilim Proto Test Board Board 16X2 ROC DOUT 1x2 REQ 7

Thesis by Brian C. Keeney - SCIPP - University of California, Santa

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