MSM9552/9553 IC for FM Multiplex Broadcast Reception User`s
Contents
1. 4 MHz 0 0 u 1 fy TS Packet count 2 2 2 2 2 2 required for S S S S S S a 1 bit phase X displacement 2 2 Rx i a i 8000 14000 2000 1000 500 250 125 2 0 8 8000 ppm 4 MHz 0 1 Packetcount 2 2 2 2 required for S S S S S S a 1 bit phase zig r displacement 2 2 X N 16000 8000 14000 2000 1000 500 250 1101 4 1 6 16000 ppm ppm ppm ppm ppm ppm ppm ppm 4 MHz Packet count E E amp 8 required for Ss E d a 1 bit phase displacement 75 2 3 5 4 BLOCK SYNCHRONIZATION REGISTERS 5 4 1 Allowable Number of BIC Error Bits This register specifies how many erroneous bits can be allowed in the block identification code BIC Values can be changed depending on parameter values before and after block synchro nization This register is used for initial settings Address Read write Reset DB7 086 DBS DB4 DB3 DB2 DB1 DBO 010H Write value 0 1 1 0 1 Allowable number of erroneous BIC bi2. BIC3 Information BIC2 Information CRC Horizontal Parity BIC1 Information BIC4 f Vertical Parity 8102 Real Time Information Block CRC Parity BIC4 f Vertical Parity BIC2 Real Time Information Block CRC Parity 8104 f Vertical Parity BIC2 Real Time Information Block CRC Parity 8104 f Vertical Parity 3 Format Frame according to method with block interleave BIC1 Information 1 CRC Parity 13 Blocks f f f f ae BIC1 Information 13 CRC Parity BIC3 Information 14 CRC Parity BIC3 Information 15 CRC Parity BIC4 Parity 1 BIC3 Information 16 CRC Parity BIC3 Information 17 CRC Parity 123 Blocks BIC4 Parity 2 BIC3 Information 18 CRC Parity f f f f BIC4 Parity 40 BIC3 Information 95 CRC Parity BIC3 Information 96 CRC Parity EN BIC4 Parity 41 BIC2 Information 97 CRC Parity 13 Blocks f f f 5 3 BIC2 Information 109 CRC Parity BIC3 Information 110 CRC Parity BIC3 Information 111 CRC Parity BIC4 Parity 42 BIC3 Information 112 CRC Parity BIC3 Information 113 CRC Parity 123 Blocks BIC4 Parity 43 BIC3 Information 114 CRC Parity f f f f BIC4 Parity 81 BIC3 Information 189 CRC Parity BIC3 Information 190 CRC Parity m We 8104 Parity 82 4 Format C Frame according to method C block code only BIC3 Information CRC Parity
3. iwm od lHWR 1982 Data bus input y Figure 4 1 Write Timing Address input x x so tmo CS to Y Data bus output 4 Figure 4 2 Read Timing Address signal input X 000H X Data signal input XXXX01XX R input INTCLR signal lt TNT output DINTCLR Figure 4 3 Interrupt CLR Timing 10413 ty 2 2 x yoo q Add Jeyuozuoy 1 1883 A TOLNIC umm uid INI m 2 180 HZZO n uM Em A GERI Aa V Mee d NL Y AAA DADA AA A 1 428 7 X0 X sna eea ea eq ea eq 0 080 9 280 ufs ejs eq eg eq Bed 0 08 juoq un uIiznVueznVueznVunznYunnnVunnvV uzznV V V HEZO HLZOXHYZOXHEZOXHOZOXHO00XH000X HZZO HEZO _ Hiz0 XHOZOX snq sseippy pea peel eje peas pea 1299 pua 401291109 40419 yes aluN eq 18915 sselppe 8 5 1 11891 SSeJppe 14011991109 u01 991109 leualul eq 401991109 949 10 13 10113 10113 yeusayu peal INI CRC clear Data load CRC result read Address bus X 028H X 029H 02
4. 1 DBO DB3 Number of frame synchronization forward protection steps DB3 DB2 DB1 DBO Number of Frame Synchronization Forward Protection Steps 0 0 0 0 0 Inhibit 0 0 0 1 1 1 1 1 15 5 5 3 Frame Synchronization Monitor 1 2 Frame synchronization monitoring register DB1 Register for monitoring the number of frame synchronization forward protection steps DB4 DB7 Both 1 and 2 are for testing 2 le Address Read write DB7 DB6 DB5 DB4 DBS DB2 DBO Read value 0 0 0 0 0 1 DB1 Monitors frame synchronization status 0 frame out of synchronization 1 frame synchronized 2 DB4 DB7 Monitors the number of frame synchronization forward protection steps While a frame is synchronized when successive attempts to detect frame synchronization points fail that number of attempts is decremented from the set number of frame synchronization forward protection steps when all the values of DB4 to DB7 change from 1 to 0 the frame is judged to be out of synchronization Remaining Number of DB7 DB6 DB5 DB4 Frame Synchronization Forward Protection Steps 4 0 0 Out of synchronization 0 0 0 1 1 Synchronization detection __ When Synchronization point cannot be detected 1 1 1 1 15 gt Load when a synchronization point is det
5. 5 5 1 Number of Frame Synchronization Backward Protection Steps 5 5 2 Number of Frame Synchronization Forward Protection Steps 5 5 3 Frame Synchronization Monitor se 5 5 4 Frame Synchronization 6 5 5 5 Frame Synchronization Clear en 5 5 0 Block Number Monitor ceci ansia 5 5 7 Frame Format Specification 5 6 ERROR CORRECTION REGISTERS esee 5 6 1 Internal Memory Address Counter Clear 5 6 2 Data Transfer Port for Error Correction ppp 5 6 3 Error Correction Start Signal ae 5 6 4 CRC Result Indication rn een 5 6 5 Error Correction Result Indication pp 5 6 6 Majority Logic Threshold Value nn 5 6 7 Internal Address Monitor 5 f sierra 5 7 1 Layer4 Register Clear terr ae 5 7 2 Layer 4 CRC Data 5 7 3 Layer 4 CRC Result 5 1 4 Layer 4 CRGO Register ea 5 8 ANALOG SECTION CONTROL MONITOR REGISTER 5 9 POWER DOWN CONTROL REGISTER 5 10 TEST CONTROL REGISTERS een 9 1071 Test rU 5 10 2 Test Control T users 5 11 ADDRESS REGISTER 5 12 EXTENDED PORT nnne nnne nnne 6 EXTERN
6. Address Read write Reset 012H Write value 1 0 0 0 1 DBO DBS3 Number of block synchronization forward protection steps DB3 DB2 DB1 DBO Number of Block Synchronization Forward Protection Steps 0 0 0 0 0 Inhibit 0 0 0 1 1 15 5 4 4 Block Synchronization Monitor 1 Block synchronization monitoring register DBO 2 Registers to monitor the number of block synchronization forward protection steps DB4 DB7 Both 1 and 2 are used for testing 2 A Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 013H Read value 0 0 0 0 0 1 DBO Monitors block synchronization status 0 block out of synchronization 1 block synchronized 2 DB4 DB7 Monitors the number of block synchronization forward protection steps While a block is synchronized if a BIC is not detected a number of successive attempts the number of attempts is decremented from the set number of block synchronization forward protection steps when all the values of DB4 to DB7 change from 1 to 0 it is judged that the block is out of synchronization Remaining Number of DB6 DB5 DB4 Block Synchronization Forward Protection Steps 0 0 Out of synchronization 1 Synchronization detection When BIC cannot be detected 77777 Load during synchronization 5 4 5 Block Synchronization Set This regis
7. si 1 sseJppe eule U 2 30N IL Aq si 30N e 910 ssaJppe 0 5591 10 SU 009 Jabuo 10 su 022 A spiom x aq 190 q e9ruen 8212 REM sei Aq pg 190019 jejuozuou 91 pz D X ponad 40199409 EM vid LNI aa Suneisdo im Er AAA REN ewa eed Bed0 0800 080 49 caa 1 280 eubis 11215 8 0 0 0 O sum eje eg Bled ea 1uoq HIO HIZO JHOZOy sng ssesppy peal nn pee peal Jeep HTOLNI pue utis peal eje 59 ts Monee 1043 u01 991109 aam eed a ai 40991109 043 aed 10113 Ju jeusyuj pee INI 1014 5 7 LAYER 4 CRC REGISTERS 5 7 1 Layer 4 CRC Register Clear This command clears the CRC register and sets all of its contents to 0 before layer 4 CRC processing Execute this command once before reading the data group on which CRC processing is to be performed Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 028H Write value X X X X X X X X x don t care 5 7 2 Layer 4 CRC Data Buffer Write the data
8. 2 BPF internal waveform 1 3 BPF internal waveform 2 4 BPF internal waveform 3 5 BPF output 6 Internal Amp output Limiter bol Variable BPF O re LPF gain AMP SCF e Vref SG LO al Filter Section TIT 4 1T delay circuit t gt LPF O To digital signal processor Limiter Delay Detection Sectio D Delay detection output Figure 5 8 2 Analog Section Output Waveform Monitor 5 9 POWER DOWN CONTROL REGISTER This is a power down setting register Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 031H Write Value 0 0 0 0 0 0 1 DBO Analog section power down control 0 Power down operation stops 1 Power on after power is turned on several milliseconds are necessary until the circuit stabilizes 2 DB1 Digital section power down control 0 The digital section is power down and the internal clock stops Since the clock stops at H operation can be continued after power on 1 The digital section is power on Operation starts from clock H 3 DB2 External oscillation control When input pin XOUTC 1 operation of crystal oscillation circuits XTAL1 XTAL2 is controlled as described below The output pin XOUT is fixed to
9. CRC clear Data Data Data Data DBO 0 po 0 00 WR nz O 0 UWRWR NER EE iod H t ticLRWR4 IWRRD4 Figure 4 5 Layer 4 CRC Timing Diagram Chapter 5 CONTROL REGISTERS 5 CONTROL REGISTERS 5 1 INTERRUPT REGISTERS 5 1 1 Interrupt source These registers indicate the four types of interrupt factors 1 receive interrupt 2 1st horizontal error correction completion 3 out of sync and 4 vertical error correction 2nd horizontal error correction completion When an interrupt occurs 1 is written The registers must be externally cleared after reading however clear conditions are different for each interrupt factor For details see Table 5 1 1 Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Reset value 0 0 0 0 000H Read write Read Read Read Read Note write write write write Note Write is used to clear the interrupt Write 1 clear Write 0 none Table 5 1 1 Interrupt Sources Type Generation Condition Generation Cycle Clear Condition INTO At the time one block is Every time 34 bytes are 1 Write DBO 1 to INT Receive interrupt received in a frame block received 18 ms 000H 000H DBO synchronization state 2 Clear the CLR pin Data is received only ina Initial setting synchronized status not received in an out of sync state INTA At the time1st hor
10. od uonoejep uo e uea euin UONeZIUOIYIUAS 9u uonoajoJd piemuo aureJj 9315 Jo 919 3 gt lt 099 014 puemyoeq awed 4915 Jo ejdurex3 3 pue 9 Slulod abueyo 9 8 pue q sjulod 918 JOU sapoo awed e awed e A lt 5 0098 i lt 0 95 gt eubis BurziuoJuou S guey lt U0I103104d pyewyo2eq 190 q 4915 2 10 ajduex3 gt epoo eure 919 snonunuos e SU 9g ZX sw gr eubis Burziuouuou s 490 g paj29jap 100 919 Snonulju0I 8 lt 9 uonoejap apo 2018 218 3 su 94 Su 81 HES J a 9 8 V a 9 8 V q pue 2 g y 19 uonoeyep uoneziuo1uou s awed 2 gt 617 051 19014 6rl ZEL gt 19018 gt 9 L p1 30014 1 1 49018 awed awed 5 5 7 Frame Format Specification Address Read Write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 01FH Write value 1 0 1 Frame Format Symbol Note 0 0 Format A Including real
11. ELECTRICAL CHARACTERISTICS 4 ELECTRICAL CHARACTERISTICS 4 1 MSM9552 ELECTRICAL CHARACTERISTICS 4 1 1 Absolute Maximum Ratings No Parameter Symbol Condition Rating Unit AVpp 1 Power supply voltage ESO NE 0 3 to 47 0 DVpp AVpp DVpp V Input voltage Vi 25 C 0 3 to AVpp 0 3 Output voltage Vo 0 3 to DVpp 0 3 Maximum power Ta 25 C per package 400 3 Pp mW dissipation Ta 25 C per output 50 4 Storage temperature Tera 55 to 150 C 4 1 2 Recommended Operating Conditions No Parameter Symbol Condition Range Unit Applied Pin 1 Power supply voltage AVpp DVpp 4 5 to 5 5 Vo DVpp DVpp 2 Crystal oscillation 8192 MHz 100 XTAL1 frequency IAL XTAL2 FM multiplex signal Composite signal in 3 on VAIN j eee 0 5 to 2 Vp p AIN input voltage cluding multiplex signal 4 Operating temperature Ta 40 10 85 C The of the variable amplifier VGain x 1 x 1 5 x 2 or x 3 The VGain should be adjusted to satisfy the equation x VGain 1 5 V to 2 0 V 4 1 3 DC Characteristics DVpp AVpp 5 V 10 DGND AGND 0 V Ta 40 to 85 C No Parameter Symbol Condition Min Typ Max Unit Applied Pin T WR RD Vin XOUTC DVpp aeo 087 volta
12. 0J U00 uomeziuoJuou s uoneziuoJupu s _ 49019 dv NIV Jay wey lt 3 PIN INFORMATION 3 3 1 PIN INFORMATION PIN CONFIGURATION TOP VIEW MON ADETIN AGND 56 XOUTC MOUTO MOUT1 MOUT2 MOUT3 a sf BER Ss sag _ 2 e e e al 8 151 el lt SY 2 y 2 3 4 5 6 7 8 9 10 u M Jeary lt 0 r O O IN fel IN a m 5 5 5 o 33 32 31 30 29 28 27 26 25 24 23 44 Pin Plastic QFP Figure 3 1 Pin Layout Leave the NC pins 17 39 43 and 44 open A0 XOUT CS XTAL2 XTAL1 DVpp DGND DB7 DB6 DB5 084 3 2 DESCRIPTIONS Table 31 Pin Description Function Symbol Pin Type Description Microcontroller WR 16 Write signal to internal
13. 1 0 Stops the operation of the crystal oscillation circuits 1 Starts the operation of the crystal oscillation circuits When input pin XOUTC 0 the crystal oscillation circuits XTAL1 and XTAL2 are always in an oscillation state and the output pin XOUT always outputs oscillation clocks 4 Dividing of external clock XOUT The divided clocks to the XOUT pin are set up DB6 DB5 DB4 Clock XOUT XCK2 XCK1 XCKO 0 0 0 8 192 MHz 0 0 1 4 096 MHz 0 1 0 2 048 MHz 0 1 1 1 024 MHz 1 0 0 0 512 MHz 1 0 1 0 256 MHz 1 1 0 0 128 MHz 1 1 1 0 064 MHz XTAL2 XTAL1 DB2 WAST kek CLR Frequency Divider XOUT ann E sip Figure 5 9 1 Oscillator Circuit Control 5 10 TEST CONTROL REGISTERS 5 10 1 Test Control 0 This register controls switching of the test pins MOUTO MOUTA 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 032H Write value 0 0 0 1 DB5 DB7 See Table 5 10 1 for details 5 10 2 Test Control 1 This register controls the decoding mode of serial receive data and test switching 5 1 4 3 2 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 033H Write value 0 0 0 0 0 0 0 1 DBO DB4 Serial receive data output Outputs serial receive
14. 4 3991 4 i 15 12 ZHIN 2618 08 aNdV gt 0010 LE 43 ce ve 95 95 indu gmod A G 15 85 0p OLNOW LLNOW ELNOIN SLNOW 9LNOW ANI aad 08d 190 cad ead vad 990 180 CIVLX 59 110 mol 080 9LNOX 5 130 vy r ov 30N MIN rm 41 2 ZaloN 30N 30N lt Jd ped oun 01 cSSBINSIN 7 APPLICATION CIRCUIT APPLICATION CIRCUIT 7 fe dsip 027 saul Z x SJ9 0PJeyo ueejxis i JeAup 10 409 121 WOU 1004 Jayng NOY NOW Y 19 8 01 Jaun xald ynw N4 NJ cSS6INSIN APPENDIX APPENDIX INTERNATIONAL FRAME FORMAT ITU R Rec BS1194 1 Format AO Frame according to method A without insertion of real time blocks BIC4 j BIC3 Information BIC2 Information BIC1 Information Vertical Parity CRC Horizontal Parity 2 Format A1 Frame according to method A with Static insertion of real time blocks 4x 82 12 Blocks 4x
15. Error 2 DBO DB7 Vertical direction error correction result corresponding to bits 0 7 0 Normal 1 Error 5 6 6 Majority Logic Threshold Value This register sets the majority logic threshold value for error correction The setup range 15 1 to 17 This register is used for initial settings Address Read write Reset DB7 DB6 DBS 084 DB3 DB2 DBO 025H Write value 0 1 0 0 0 084 DB3 DB2 DB1 DBO Majority Logic Threshold Value 0 0 0 0 0 Inhibit 0 0 0 0 1 1 f f f f f f 0 1 0 0 0 8 f f f f f f 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 5 6 7 Internal Address Monitor This register indicates the addresses 0 271 of internal memory for error correction This is used for testing Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 026H Read value 0 0 0 0 0 0 0 0 b7 b6 65 b4 b3 b2 bi Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 027H Read value 0 b8 e Error correction involves external a microcontroller and MSM9552 9553 e Transfer data in error correction units horizontal direction equals 34 bytes vertical direction equals 272 bytes from external memory to the internal buffer of the MSM9552 9553 Error correction is then executed Transfer data after error correction from
16. correction data write tIWRWRE Error correction 250 ns WR and write Interval between error 8 correction data read tIRDRDE Error correction 250 ns RD and read Interval between error WR 9 correction data write tiwRRDE Error correction 100 ns BD and read 10 Interval between id T Layer 4 CRC 100 u _ WR 4 data clear and write man m Mawr ms mace as Read data output bum _ u u Bs RD delay 1 DBO to DB7 Read data output T BO RD delay 2 DBO to DB7 15 Interrupt CLR delay TDINTCLR Step Bul DE 250 ns w Error correction interrupt WR Error correction time INT 1 Horizontal direction TERAL u an zd 080 Error correction time INT 17 Vertical direction TERRY 7 878 u 18 CLR pulse width tWCLR 200 ns CLR See section 4 3 TIMING DIAGRAM 4 1 5 Filter Characteristics No Parameter Symbol Condition Min Typ Max Unit Applied Pin BPF pass band 1 GAIN1 Variable gain amplifier 3 0 dB MON attenuation gain 0 dB BPF block band 2 GAIN2 Variable gain amplifier 50 dB MON attenuation 1 0 block band 3 GAIN3 Variable gain amplifier 50 dB MON attenuation 2 gain 0 dB 4 2 MSM955
17. suld 1oyuow 1 010 1591 5 11 MO ADDRESS REGISTER This register sets up an internal register address irrespective of pins AO to A5 The address set up by this register becomes valid when IOEN DB7 is set to 1 When CS 1 and IORD 0 data in the internal register is output onto the data bus When CS 1 and IOWR 0 data on the data bus is written in the internal register ZUR 2 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 037H Write value 0 0 0 0 0 0 0 1 087 IOEN 0 Address set up this register is invalid 1 Address set up by this register is valid as an internal address in the IC 2 DBO DBS Corresponds to external addresses AO to A5 5 12 EXTENDED PORT REGISTER Data BO to B4 in this register is output to the monitor output pins MOUTO to MOUT4 by writing 000xxxxx 101xxxxx or 110xxxxx to the port mode register 032H Refer to the table 5 10 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00FH Write value 0 0 0 0 0 Usage example of the extended port When the clock of the microcomputer that controls the MSM9552 9553 is supplied from the XOUT of the 9552 9553 the following two problems will occur 1 When used with XOUTC 1 When this register is cleared the microcomputer does no
18. 4 2 5 Filter Characteristics 4 4 8 43 TIMING DIAGRAM ee aha 4 9 CONTROL REGIS TERS ne 5 1 5 1 INTERRUPT REGISTERS ici iiit mini en 5 1 5 1 1 Interrupt 0 5 1 5 1 2 INT Mask ie iei tib 5 3 5 2 RECEIVE DATA REGISTERS zu nn anne 5 4 5 21 Receive Block Status eite rex cea rra 5 4 5 2 2 Receive Data RAM 5 6 5 2 3 Receive RAM Data Accumulation Condition and Address Clear 5 6 5 2 4 BIC Monitor M 5 7 5 3 CLOCK REGENERATION nennen 5 10 5 3 1 Fixed Phase Adjustment cion nennen 5 10 AMICI 5 12 5 3 3 Integration Constant nee 5 13 534 Phase Correction Step ia 5 14 5 4 BLOCK SYNCHRONIZATION REGISTERS Ne 5 15 5 4 1 Allowable Number of BIC Error Bits 5 15 5 4 2 Number of Block Synchronization Backward Protection Steps 5 16 5 4 3 Number of Block Synchronization Forward Protection Steps 5 16 5 4 4 Block Synchronization Monitor eene 5 17 5 4 5 Block Synchronization 5 18 5 4 6 Block Synchronization 5 18 5 4 7 Bit Number Monitor i eerte dt se oer ace 5 18 5 5 FRAME SYNCHRONIZATION REGISTERS
19. data serial receive data converted by the control in 3 to 5 below to MOUTSG pin The output data changes at the rising edge of a 16 kHz regeneration data clock MOUT5 pin DB4 DBO MOUT 6 Pin Output 0 0 Fixed to L 0 1 Serial receive data after descrambling 1 0 1 1 Serial receive data before descrambling 2 DB1 16 kHz regeneration data clock A 16 kHz regeneration data clock is output to the MOUT5 pin 0 MOUTS Pin is fixed to L 1 16 kHz regeneration data clock is output to the MOUTS pin 3 DB2 Differential decoding control 0 Performs differential decoding to input data 1 Does not perform differential decoding FM multiplex broadcast differential decoding is not used so use DB2 1 4 DB3 Descrambler regeneration of dc component of data control 0 Descrambles input data other than BIC This is used for receiving FM multiplex broadcast 1 Does not descramble This is used for testing 5 DB5 DB6 Delay detector output control Delay Detector Control DB6 DB5 controls input data and Purpose of Use data before 1T 0 0 ENOR FM multiplex broadcast reception 0 1 Through data before 1T 1 EOR For testing 1 10 91215 918 lt 130919 2018 2019 bold ON 319 0 0 1918 0 0 098 Jaquinu 918
20. register interface RD 18 Read signal to internal register INT 15 0 Interrupt signal to microcontroller When set to L an interrupt is generated 05 31 Chip select signal When set to L the read write and data bus signals become effective CLR 40 When set to 17 the internal register is initialized and the IC enters power down mode A0 A5 33 38 Address signal to internal register DBO DB7 19 26 1 0 Data bus signal to internal register Tuner interface AIN 6 FM multiple signal input SG 5 0 Analog reference voltage pin Connect a capacitor between this pin and the analog ground pin to prevent noise Analog section MON 1 0 Analog section waveform monitoring pin The test mode setting for the blocks in the analog section is specified by the analog section control register ADETIN 2 Analog signal input pin for testing Digital section TORD 41 Digital section test signal input pins pulled up test TOWR 42 internally MOUTO 8 14 0 Digital section test signal and monitor output MOUT6 pins Clock XTAL1 29 8 192 MHz crystal connection XTAL2 30 0 8 192 MHz crystal connection XOUT 32 0 Pin to supply variable clock 64 kHz to 8 192 MHz to external devices XOUTC 7 XOUT control L sets XOUT output sets XOUT output inhibit This pin is pulled up internally Power supply 3 Analog power supply AGND 4 Analog ground DVpp 28 Digital power supply DGND 27 Digital ground Chapter 4
21. value 0 0 1 0 3 Integration constant after block synchronization outside the gate 0 63 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00CH Write value 0 1 1 0 0 0 4 Integration constant after block synchronization inside the gate 0 63 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00DH Write 0 1 1 0 0 0 5 3 4 Phase Correction Step This register sets the phase correction step width of DPLL used for data clock regeneration This register can be used to adjust data clock supply speeds or data clock jitter control Phase correction step widths can be changed depending on parameters set before or after block synchronization This register is used for initial settings Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00EH Write value 0 1 0 1 Time constants can set as shown in Table 5 3 1 by combining the integration constants shown in Sections 5 3 3 and 5 3 4 Table 5 3 1 Phase Correction Step Integration Constant After Block Synchronization b bl Phase Before Block Synchronization 1 0 Correction Step 1 2 4 8 16 32 64 4000 2000 11000 500 250 125 62 5 1 _ 0 4 4000 ppm
22. 0 0 5 9552 0 0 0 0000 20000 OO OKI MSM9552 9553 IC for FM Multiplex Broadcast Reception User s Manual 1 0 ISSUE DATE Mar 1998 QU O pdfdzsc com IMPORTANT NOTICE DARC DAta Radio Channel an FM multiplex broadcast technology has been developed by NHK Japan Broadcasting Corporation DARC is a registered trademark of NHK Engineering Service NHK ES Any manufacturer who intends to manufacture sell products that utilize DARC technology needs to be licensed by NHK ES For detailed information on licenses please contact NHK Engineering Service Phone 81 3 3417 4840 E2Y0001 28 30 NOTICE 1 9 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature Oki assumes no resp
23. 1 13 14 136 137 and 149 150 under format B are detected the same number of times as the specified number of successive steps number of frame synchronization backward protection steps frame synchronization is entered and the internal frame counter is synchronized with the detected block number Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 018H Write value 0 1 1 DBO DB1 Number of frame synchronization backward protection steps DB1 DBO Number of Frame Synchronization Backward Protection Steps 0 0 1 0 1 2 1 0 3 1 1 4 5 5 2 Number of Frame Synchronization Forward Protection Steps This register specifies the number of times that successive unsuccessful attempts to detect the synchronization points required for frame synchronization that will cause a judgment that a frame is out of synchronization After frame synchronization if the block number changing points frame synchronization points 272 1 13 14 186 3137 and 149 4150 under format B are not detected the same number of times as the specified number of successive steps number of frame synchronization forward protection steps the frame will be out of synchronization to terminate data reception This register is used for initial settings Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 019H Write value 0 1 0 0
24. 136 Receive data of block numbers 61 to 130 1 0 Receive data of block numbers 137 to 149 Receive data of block numbers 131 to 190 1 1 Receive data of block numbers 150 to 272 Receive data of block numbers 191 to 272 Method AO Receive data of block numbers 191 to 284 Method A1 3 083 Block Synchronization Status 0 Indicates receive data in a block out of sync state 1 Indicates receive data in a block sync state 4 084 Parity Block Indication This bit indication is available only in a frame synchronization state 0 Receive data is not the data of the parity block 1 Receive data is of the parity block 5 DB5 Frame Synchronization Status Indication 0 Receive data is in a frame out of sync state 1 Receive data is in a frame sync state 6 DB6 CRC Result Indication 0 Indicates that the CRC result for the receive data is normal 1 Indicates that the CRC result for the receive data is an error 7 DB7 REAL Block Indication This indication is used for receive block data in a frame sync state when frame A is set in the frame method register 01FH 0 Receive data is not of the REAL block 1 Receive data is of the REAL block 5 2 2 Receive Data RAM Port This port is used for one block receive data RAM of 34 bytes excluding BIC When an interrupt occurs the internal memory addresses are cleared to zero Since the next receive data is output at the rising edge of an RDO3 signal 34 bytes
25. 2 DB1 DBO 02CH Read write value 0 0 0 0 0 0 0 0 b15 b14 b13 bi2 b11 b10 b9 b8 Data bus DBO DB7 DBO RD2B RD2C RD2A WR29 L CRC register CRC register ue gt P S gt high order gt low order de t 8 bits 8 bits WR2B WR2C Shift clock generation 8 Shift CK CLR WR28 CRC clear _ Data load CRC result read Address bus 028H Y 09H 029H Y 024H Y CRC clear Data Data Data Data DBO 0 FE 0 ED E 3 RD cum Write data at time 4 5 us or longer intervals of 4 5 us or longer Figure 5 7 1 Layer 4 CRC Block Diagram and Timing Diagram 5 8 ANALOG SECTION CONTROL MONITOR REGISTER This register is used for level adjustment of the analog input signal composite signal and analog section test mode settings 3 2 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 030H Write value 0 0 0 0 0 1 080 DETC Controls the input of analog input ADETIN 0 Disables the input of analog input pin ADETIN so that the input buffer amplifier is powered down during FM multiplex broadcast reception 1 Enables the input of analog input pin ADETIN so that the input buffer amplifier is powered on The connections are switched as follows available f
26. 3 ELECTRICAL CHARACTERISTICS 4 2 1 Absolute Maximum Ratings No Parameter Symbol Condition Rating Unit 1 ly volt 21 0 310 7 0 ower supply voltage 0 3 to 7 DVpp AVpp DVpp V 9 Input voltage Vi 25 C 0 3 to AVpp 0 3 Output voltage Vo 0 3 to DVpp 0 3 Maximum power Ta 25 C per package 400 3 eae Pp mW dissipation Ta 25 C per output 50 4 Storage temperature Tera 55 to 150 C 4 2 2 Recommended Operating Conditions No Parameter Symbol Condition Range Unit Applied Pin 1 Power supply voltage AVpp DVpp 2 7 to 3 3 V DVpp DVpp Crystal oscillation XTAL1 2 frequency XTAL 8 192 MHz 100 ppm XTALO FM multiplex signal Composite signal in 3 V 0 2 to 0 9 VP AIN input voltage AIN cluding multiplex signal 4 Operating temperature Ta 20 10 75 C The of the variable amplifier VGain x 1 x 1 5 x 2 or x 3 The VGain should be adjusted to satisfy the equation x VGain 0 6 V to 0 9 V 4 2 3 DC Characteristics DVpp AVpp 3 V 10 DGND AGND 0 V 20 to 75 C No Parameter Symbol Condition Min Typ Max Unit Applied Pin WR RD 0 8 x A pH ViH XOUTC DVpp V to DB7 id 02 XTAL1 CS VIL A0 to A5 CLR de IORD TOWR DVpp MOUTO to Vou 1 mA 3 0 5 V MOUTE INT
27. 3A139941 2010 N 1dnJJalul 3A198931 490 q 1 0 98 ve 9c Ge 9 0 GE LEN N L N ON 49019 12914 gt 5 3 5 3 1 CLOCK REGENERATION REGISTERS Fixed Phase Adjustment This register adjusts the phase of a 16 KHz data sampling clock in 1 125 steps within the range of 1 5 to 24 125 This register is used for initial settings Address Read write 008H Write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO value 0 0 0 0 0 0 0 1 DB0 DB2 Phase delay settings in 1 125 steps DB2 DB1 DBO Phase Delay Setup Value 0 0 0 0 125 0 0 1 1 125 0 1 0 2 125 0 1 1 3 125 1 0 0 4 125 1 0 1 Inhibit 1 1 0 Inhibit 1 1 1 Inhibit 2 DB3 DB5 Phase delay settings in 1 25 steps DB5 DB4 DB3 Phase Delay Setup Value 0 0 0 0 25 0 0 1 1 25 0 1 0 2 25 0 1 1 3 25 1 0 0 4 25 1 0 1 Inhibit 1 1 0 Inhibit 1 1 1 Inhibit 3 086 Phase advance setting in 1 5 steps DB6 Phase Lead Setup Value 0 0 1 1 5 Receive data MON pin X x Data sampling clock ear MOUTS pin e i 4 LSB x0100100 x0000000 x1100100 x1000000 Figure 5 3 1 Phase Adjustment 5 3 2 Bit Gate This register sets the gate width centered around the rising edge of the data clock Gate width can be ch
28. AL CONNECTION EXAMPLE 7 APPLICATION CIRCUIT tacet tutu unn APPENDIX INTERNATIONAL FRAME FORMAT 1 1 GENERAL DESCRIPTION GENERAL DESCRIPTION The MSM9552 and MSM9553 are LSI devices which demodulate FM character multiplex signals in the DARC DAta Radio Channel format to acquire digital data These devices operate on 5 V and 3 V respectively In the DARC format baseband signals at ordinary FM broadcasting frequencies are multiplexed with 16 kbps digital data which are L MSK modulated at 76 kHz Each device has a bandpass filter consisting of SCF frame synchronization circuit and error correction circuit on a single chip They allow a system for acquisition of digital data to be easily constructed by externally mounting an FM receiver tuner microcontroller for control and memory for temporary storage of data The MSM9552 and MSM9553 have a simple configuration and are equipped with only necessary functions By making changes to software for the external microcontroller the MSM9552 and MSM9553 meet the various requirements of FM multiplex broadcasting services to be offered in future These devices are best suited for radio sets and information devices using FM character multiplex broadcasting which began in Japan in October 1994 The MSM9553 is especial
29. DB DB3 Receive interrupt 1st horizontal error correction completion interrupt Out of sync interrupt Vertical 2nd horizontal error correction completion interrupt INT3 P DB2 CK INT2 DB1 7 3 p gt CK INT1 DBO Da p gt CK INTO D h gt CK Figure 5 1 1 INT Mask Register 5 2 RECEIVE DATA REGISTERS 5 2 1 Receive Block Status This register indicates the status of the received block data which consists of the following 1 Frame Number Change 2 Frame Number 3 Block Synchronization Status 4 Parity Block Indication 5 Frame Synchronization Status 6 Layer 2 CRC Result and 7 Real Time Block Indication 7 6 5 4 3 2 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 002H Read value 0 0 0 0 0 0 0 0 1 DBO FNCHG Frame Number Change 0 No frame number changed 1 1 is indicated when receive data is the first data 2nd byte of block number 1 14 137 150 for Method A and block numbers 1 61 131 191 for Method B 2 DB1 DB2 Frame Number Indicates that the receive data is data of the following block number groups Receive Data DB2 DB1 Method B Method A 0 0 Receive data of block numbers 1 to 13 Receive data of block numbers 1 to 60 0 1 Receive data of block numbers 14 to
30. TR ES DBO to 087 XOUT Vin DV 2 WR RD ES an di a DBO to 087 nput curren m DGND 2 IL1 IL CLR lima Vin AVpp 2 4 Input current 2 ADETIN 112 AGND 2 5 Input current Vin DV 2 LL IH3 IH DD XOUTC 6 Pull t 3 13 50 TORD rren nn pi Vi DGND _ _ 9 Output off leakage a During nonmonitoring Hiz 7 uA current Vor AGND L During nonmonitoring Hiz During operation no load 13 22 mA f 8 192 MHz 8 Supply current loo DVpp During power down 10 no load 4 2 4 AC Characteristics No Parameter Symbol Condition Min Max Unit Applied Pin tswat 10 WR CS 1 Write setup time ns AO to 5 120 DBO to 087 WR CS 2 Write hold time THWR 10 ns AO to DBO to DB7 3 Write pulse width tWWR 130 ns WR RD CS 4 Read setup time tsRD 10 ns AO to A5 5 Read hold time tHRD a 10 ns ets to A5 6 Read pulse width twRD 160 ns RD Interval between error 7 correction data write twRWRE Error correction 250 ns WR and write Interval between error 8 correction data read tIRDRDE Error correction 250 ns RD a
31. anged depending on parameters set before and after block synchronization This function is for varying the constant of integration for the clock sampling timing detected inside and outside the gate This register is used for initial settings Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 009H Write value 0 0 0 0 1 DBO DB1 Before block synchronization 2 DB2 DB3 After block synchronization After Block Synchronization Before Block Synchronization Gate DB3 DB2 DB1 DBO 0 0 0 0 Gate 0 0 1 0 1 Gate 1 10 1 0 1 0 Gate 2 20 1 1 1 1 Gate 3 30 Receive data Data clock Gate 0 Gate 1 Gate 2 Gate 3 Clock sampling timing Figure 5 3 2 Clock Sampling Gate 5 3 3 Integration Constant This register sets the timing sampling count required for phase control The parameters are before and after block synchronization and inside and outside the gate This register is used for initial settings 1 Integration constant before block synchronization outside the gate 0 15 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00AH Write value 0 0 1 0 2 Integration constant before block synchronization inside the gate 0 15 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 00BH Write
32. can be read successively The status of receive data is shown in 5 2 1 1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 003H Read value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined b7 b6 b5 b4 b3 b2 b1 5 2 3 Receive Data Accumulation Condition and Address Clear 1 081 This register specifies the condition frame block synchronization for accumulating data into the receive RAM If any data is written to this register the receive RAM addresses are cleared to zero Write the following data before reading the receive RAM second time and thereafter 0 Receive data is accumulated in receive RAM when the frame is synchronized 1 Receive data is accumulated in receive RAM when the block is synchronized However when frame synchronization is entered receive data is accumulated even if the block is out of sync DA Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 004H Write value 0 5 2 4 BIC Monitor This register indicates the block indentification code BIC of the block receive data 1 2 Address Read Write Reset 007H Read value DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 082 When BIC is detected 1 is indicated 2 DBO DB1 The detected BIC is output as shown b
33. correction for receive block data DB1 Displays the operation status of the vertical error correction DB2 Displays the operation status of the 2nd horizontal error correction for each of these bits 0 Error correction circuit is idle 1 Error correction circuit is in operation 5 6 4 CRC Result Indication This register indicates a 14 bit CRC result When horizontal direction error correction is executed a 14 bit CRC is performed internally on corrected data and the result is indicated This register is cleared immediately after error correction starts Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 023H Read value 0 5 6 5 DBO 14 bit CRC result 0 Normal 1 Error Error Correction Result Indication This register indicates an error correction result If syndrome registers are all 0 after error correction this register indicates a normal status If not it indicates an error This register is cleared immediately after error correction starts In the case of a horizontal direction correction the result is indicated at DB7 In the case of a vertical direction correction the result is indicated at DBO DB7 corresponding to bits 0 7 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 024H Read value 0 0 0 0 0 0 0 0 1 DB7 Horizontal direction error correction result 0 Normal 1
34. ected 5 5 4 Frame Synchronization Set This register forcibly sets frame synchronization and is used for testing Address Read write 01BH Write Reset value DB7 DB6 DB5 084 DB3 DB2 DB1 DBO X X X X X X X X x don t care 5 5 5 Frame Synchronization Clear This register forcibly sets frame out of synchronization This function is effective when a channel is changed in clearing a previous synchronizing status to permit faster synchronization for the new channel Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 01CH Write value X X x x X X x x x don t care 5 5 6 Block Number Monitor These registers monitor block numbers and are used for testing DBO of 01EH register is MSB and DBO of 01DH register is LSB Numbers 0 to 271 are displayed Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 01DH Read value 0 0 0 0 0 0 0 0 b7 b6 65 b4 b3 b2 b1 b0 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 01EH Read value 0 b8 pue Moolg L G G uoy Jepun 1 ue s siy 30N uomneziuoJuou S j0 1no 104 SI aures SPUOIAS Y SABUU 01 Pappe SI spuooes zz 1898 ueewjeq euim JO u
35. elow DB1 DBO BIC number 0 0 BIC 1 0 1 BIC 2 1 0 BIC 3 1 1 BIC 4 Serial Serial to Data receive receive parallel o 34 Bytes RAM data conversion 055 4 Switching Data read RD03 dm C 4 First horizontal 34 Bytes RAM error correction Data bus O Error correction vertical horizontal uu Vertical error correction amp second horizontal error correction s 272 Bytes RAM gt Figure 5 2 1 Receive RAM Configuration 00 X ON IN 080 JOWUOW Ig X uoneopuroolg 1v3u I N 180 0 ON 4 X uoneopurinsei 989 xoold 1 980 Joug X 91215 SNOVOJYIU S 5014 L N X H200 X 2209 Aued 40010 1 pad alelS xolg idis X 9jejs SNOUOJYIV S xoo g 019 L N x X ON 2019 L N c 18d p d y oN 50 L N X X 080 X saikq pe erep an aoay 49019 I N X reg 18910 2 1dnJJeluI Y 10111940
36. ge XTAL1 CS Vit E AO to CLR gt TOWR DVpp MOUTO to V 1 mA mE er 05 y moure INT ER us DBO to DB7 XOUT WR RD CS Vin DV 2 m 108000087 n rren m DGND 2 IL1 IL GR lima Vin AVpp 2 4 Input current 2 uA ADETIN lio Vit AGND 2 5 Input current Vin DV 2 IH3 7 XOUTC DD 9 V aie 6 Pull 8 35 110 A IORD IOWR ull up curren pull Vi DGND u _ _ 9 Output off leakage During nonmonitoring Hiz 7 uA current Vor AGND 9 oL During nonmonitoring Hiz Duri tion no load uring operation no loa 16 32 mA f 8 192 MHz 8 Supply current loo AVpp DVpp During power down 20 load 4 1 4 AC Characteristics No Parameter Symbol Condition Min Max Unit Applied Pin tswr1 10 WR CS 1 Write setup time ns AO to A5 tswr2 60 DBO to 087 WR CS 2 Write hold time tHWR 10 mE ns AO to A5 DBO to DB7 3 Write pulse width twwR 65 ns WR 4 Read setup time 10 ns BD ES to A5 5 Read hold time tHRD 10 ns to A5 6 Read pulse width twRD 105 ns RD Interval between error 7
37. group on which CRC processing is to be performed in byte units with a cycle of 4 5 us or longer The data written inside the IC is loaded to the CRC operation register and a shift operation is executed eight times The system then waits for the next data input Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 029H Write value 0 0 0 0 0 0 0 0 5 7 3 Layer 4 CRC Result Indication This register indicates a layer 4 CRC result After the last data of a data block is written pause for at least 4 5 us before reading 010 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 02AH Read value 0 1 DBO layer 4 CRC result 0 Normal 1 Error 5 7 4 Layer 4 CRC Register This register is used for writing initial values directly to the CRC operation register and reading values which are still in progress With this function layer 4 CRC processing for multiple data groups can be performed in parallel For example CRC processing for a short data group can be inserted while CRC processing for a long data group is in progress 1 Layer 4 CRC register high order 8 bits Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 02BH Read write value 0 0 0 0 0 0 0 0 b7 b6 65 b4 b3 b2 b1 b0 2 Layer 4 CRC register low order 8 bits Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB
38. izontal error 0 274 ms after 1st error 1 Write DB1 1 to INT 1st horizontal error correction completion correction is completed correction start signal is written 000H 2 Clear the CLR pin 000H DB1 Initial setting INT2 When frame is out of ad ms 1 Write DB2 1 to INT Out of synchronization synchronization protection steps 13 000H 000H DB2 This comes out at 10to 12 2 Clear the CLR pin seconds when the number of Initial setting forward protection steps is 8 INT3 At the time error correction is When the time shown in the 1 Write 083 1 to INT Vertical horizontal completed table below has elapsed after 000 2nd error correction tion start sional 2 Clear the completion an error correction start signal 2 Clear the pin 000H DB3 is written see table below Initial setting Error Time Data did No 0 138 ms ai ps ornzonia Nas 0 274 ms nn 1 090 ms gt Yes 2 178 ms ae Error correction is skipped when there is no error 5 1 2 INT Mask This register controls interrupt generation Address Read write Reset DB7 086 DBS DB4 DB3 DB2 DB1 001H Write value 0 0 0 1 DBO DB3 0 interrupt disabled 1 INTO INTS interrupt enabled INTO INT1 INT2 INT3
39. lt 919 0919 BuiziuoJuou S BurziuoJuouus JO NO 0 9121 HulziuosyauAs 9019 lt INAST 2x HulziuosyouAs BurziuoJuouus 10 0 91215 HulziuoiyouAs awes4 lt 2NASJ aq ueo MoJaq 01 SUS 34 1nq y sn 0 JAVY 104 90 ay uonoadsu Jugwd ys aoIlAap S 104 pasn si euis jeusa ul 97 24 991 aloN 3J0J9d Buljquiesosap Jaye n idt SAA yid 1 01 vL 9LNOW 3A189391 2119 281 BLES 39149 1 0 SLNOW 0 vad 0 0 09 Laa 09 104409 152 3591 on ON Uld Uld HEEO 5 04 U09 1591 014109 1591 0 rad ndyn y 130918 130919 308 O pax she H40 21 pLNOW Indlno ead e 1918 87043 3199 pane Leia THO ELMO 0ISL indino 134 a nd n e 0918 INOW zy0dj 440 0 OL 2 LNOW 59 7984 105 nun rad 6 LLNOW Thera 19151091 H40 9NASJ 04044 151 an yndyng 8 OLNOW be i un 19151681 H40 000 Gr 001 110 010 100 LoL on owen 9151 19451 09151 ILISL 0151 or ana eloN eub s 157 uoIsuspg 80 HZEO 0409 1591
40. ly suitable for portable units Features Built in Bandpass Filter SCF Built in Block Synchronization Circuit and Frame Synchronization Circuit Setting of Synchronization Protecting Stage number Regeneration of Data Clocks by Digital PLL 1T Delay Detection Built in Error Correcting Circuit Built in Layer 4 and Layer 2 CRC Processing Circuit International Frame Formats A supporting a real time block B and C available Microcontroller Parallel Interface Clock Output for External Devices 64 kHz to 8 192 MHz selectable Power Source 5 V MSM9552 3 V MSM9553 Package 44 pin plastic QFP QFP44 P 910 0 80 2K Product MSM9552GS 2K MSM9553GS 2k 2 BLOCK DIAGRAM BLOCK DIAGRAM 2 19019 Sqv oqv 80 080 g E ANI 919 59 HM 04 sselppy snq epeq LIWLX cIVIX LAOX ILNOX O O O O O A AER 105 990 4 eubig 9289101 Japiaip lt Aguanbe4 dd snq sseJppy Js snq geq Aejap LL la Y y 910 lt 4 1 19019 D 989 2 1347 18151691 Y uopoeuoo ewm x pontum fon a eaa 2048 peau Inve sama pe ed 191114 D J8JA
41. nd read Interval between error 9 correction data write twRRDE Error correction 100 ns i and read Interval between layer 10 HICLRWRA Layer 4 CRC 100 ns WR 4 data clear and write 4 Interval between layer Layer 4 CRC 45 _ us WR 4 data write and write 12 Interval between layer m Layer 4 CRC 45 u u iis WR 4 data write and read RD Read data output RD 13 1 toro 180 ns 00 Read data output RD 14 delay 2 toro 180 ns 0 15 Interrupt CLR delay TDINTCLR Step out al 250 ns Mr Error correction interrupt WR Error correction time INT Horizontal direction TERRL u E DBO Error correction time INT 17 Vertical direction TERRY O a 18 CLR pulse width twcLR 200 ns CLR See section 4 3 TIMING DIAGRAM 4 2 5 Filter Characteristics No Parameter Symbol Condition Min Max Unit Applied Pin BPF pass band une 1 P GAIN1 Variable gain amplifier 3 0 dB MON attenuation gain 0 dB BPF block band en 2 GAIN2 Variable gain amplifier 50 dB MON attenuation 1 gain 0 dB 100t kH BPF block band i nd i 3 GAIN3 Variable gain amplifier 50 dB MON attenuation 2 gain 0 dB 4 3 TIMING DIAGRAM Address input X x CS tHwR
42. ndefined Undefined Undefined Undefined Undefined Undefined b7 b6 b5 b4 b3 b2 b1 60 5 6 3 Error Correction Start Signal When start action specification data is written into DBO to DB2 error correction starts in the specified mode When error correction is completed an interrupt is generated The operation status of the error correction circuit can be monitored by this register 2 Read gt 1 Write Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 022H Read write value 0 0 0 1 DB2 Write Error correction start mode specification DB2 DB1 DBO Start Action write 0 0 1 Horizontal error correction of receive block data at address 003H on the 34 byte RAM starts Corrected data is written toaddress 003H on the RAM 0 1 0 Vertical error correction of data written in address 021H on the 272 byte RAM starts Corrected data is written in address 021H on the RAM 1 0 0 Horizontal error correction of data written in address 021H on the 34 byte RAM starts Corrected data is written in address 021H on the RAM 2 DBO DB2 Read Monitor The data written in this register can be used to monitor the error correction circuit operation status because the data is cleared after error correction is complete DBO Displays the operation status of the horizontal error
43. onsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to trafficand automotive equipment safety devices aerospace equipment nuclear power control medical and life support systems Certain products in this document may need government app
44. or input of a 16 kbps digital test signal DBO Internal delay Ap detection circuit Y 0 Data discrimi nation circuit DET Figure 5 8 1 Switching Analog Input Pins ADETIN pn O gt Input buffer amplifier 2 DB1 DB2 SGAINO SGAIN1 This register is used for gain switching for the variable gain amplifier for analog input signal These signals are used for initial settings Set the values of DB1 and DB2 so that the following expression is satisfied Peak value of the analog input signal composite signal x gain 1 5 to 2 0 Vp_p MSM9552 0 5 to 0 9 Vp_p MSM9553 This is effective for improving the S N ratio SGAIN1 SGAINO Gain DB2 DB1 0 0 x 1 0 1 1 5 1 0 2 1 1 x3 DB3 DB5 MO M2 Monitors internal filter output waveforms and controls pin 1 output Refer to Figure 5 8 2 for the part that can be monitored After clear the internal MON amplifier is powered OFF and the output becomes high impedance 2 DB5 M1 DB4 DB3 MON Pin pin 1 Output 0 0 0 Internal monitor amplifier power off high impedance output 0 0 1 CD LPF output of input stage 0 1 0 2 BPF internal waveform 1 0 1 1 3 BPF internal waveform 2 1 0 0 4 BPF internal waveform 3 1 0 1 5 BPF output 1 1 0 6 Internal amplifier output 1 1 1 7 Delay detection output Input stage LPF output
45. roval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these No part of the contents cotained herein may be reprinted or reproduced without our prior permission MS DOS is a registered trademark of Microsoft Corporation Copyright 1998 Oki Electric Industry Co Ltd Printed in Japan TABLE OF CONTENTS GENERAL DESCRIPTION Een Maas x 1 1 DIAGRAM ite aida sale 2 1 JPIN INFORMATION gs 3 1 3 1 PIN CONFIGURATION TOP VIEW 3 1 3 2 PIN DESCRIPTIONS u nee a aaa 3 2 ELECTRICAL CHARACTERISTICS tnu en ea 4 1 41 MSM9552 ELECTRICAL CHARACTERISTICS 4 1 4 1 1 Absolute Maximum 5 4 1 4 1 2 Recommended Operating Conditions 4 1 4 1 3 DC Characteristics 4 2 43 4 AC Characteristics 4 3 4 15 EilterGliaracterlStl6S daos Eneas 4 4 4 2 MSM9553 ELECTRICAL CHARACTERISTICS 4 5 4 2 1 Absolute Maximum 4 5 4 2 2 Recommended Operating Conditions 4 5 4 23 A ernennen 4 6 424 NC e SEN EHRE 4 7
46. t operate because the XOUT pin is fixed at HDN 2 When used with XOUTC 0 When this register is cleared oscillation does not stop even in the power down mode because the XOUT pin always outputs clock The above troubles are cleared up using the extended port function By connecting the XOUTC pin and MOUTO pin externally as shown below XOUTC goes to 0 and XOUT pin outputs the clock after clear By writing DBO of OOFF to 1 XOUTC is set to 1 during power down mode As aresult oscillation does not stop during clear and can be stopped by the software only during power down mode E gt gt o x 7 8 Connect XOUTC and MOUTO externally Figure 5 12 1 Usage Example of Extended Port Chapter 6 EXTERNAL CONNECTION EXAMPLE EXTERNAL CONNECTION EXAMPLE 6 punoJ6 1aun sdl pue uid punos6 eui ALN y pue Jamod aui ayeredas Jojoedeo 2141013299 Wnleluel e asf sis eue 10 Jano e YIM Al sea pajoauuo9sIp eq uid siu gt anda y 0N Z 910N NI 2 T l l Lo 0 CC 4 9 30N i e10N 9 UL 10 3122 22 A 57 8c
47. ter forcibly sets block synchronization and is used for testing Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 014H Write value x X X X X X X X x don t care 5 4 6 Block Synchronization Clear This register forcibly sets block out of synchronization This setting is effective when a channel is changed in clearing a previous synchronizing status to permit faster synchronization for the new channel Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 015H Write value X X X X X X X X x don t care 5 4 7 Bit Number Monitor These registers monitor bit numbers They are used for testing DBO of the 017H register is MSB and DBO of the 016H register is LSB Numbers 0 to 287 displayed Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 016H Read value 0 0 0 0 0 0 0 0 b7 b6 65 b4 b3 b2 b1 Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 017H Read value 0 b8 5 5 5 5 1 FRAME SYNCHRONIZATION REGISTERS Number of Frame Synchronization Backward Protection Steps This register specifies the number of times that synchronization points required for frame synchronization have to be detected in succession in order for the frame to be judged as being synchronized When the block number changing points frame synchronization points 272
48. the internal buffer to external memory External memory Data bus MSM9560 9561 Internal data buffer S Microcontroller Error correction Figure 5 6 1 General Configuration of Error Correction CRC Error correction start result Address generation Address bus o 7 gt Data bus Bus IF Internal RAM P gt S Error correction WR O 272W x 8 bits PES 14 bit CRC RD Note CRC is executed on data after horizontal direction error correction Figure 5 6 2 Configuration of Error Correction Section Internal data memory address Internal data memory address Bit No Bit No See Error ee Error 00 correction 00 lt correction DA execution 1 execution 01 Sras sequence 0 sequence i Parity 33 Mace Error correction is executed for each bit of bit 0 to bit 7 from byte 0 to byte 271 189 190 7 block 271 Horizontal direction error correction gi Eight times Vertical direction error correction Figure 5 6 3 Error Correction Sequence UONDS1109 10413 9 euim 1xeu BU eq 01 euo si ssejppe ey pasoyuou aq sseJppe AJOWAW euJaju 8 30N 099 109 10 19 USym JUO
49. time 0 1 Al information block 1 0 Format B B Japan FMSS 1 1 Format C C 5 6 5 6 1 ERROR CORRECTION REGISTERS Internal Memory Address Counter Clear This command clears the address counter of internal memory set to 0 before writing and reading an error correction data block Since error correction is executed sequentially from address 0 of internal memory the internal memory address counter must be cleared before writing After error correction it is necessary to clear the internal memory address counter to read data sequentially from address 0 of internal memory Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 020H Write value X X X X X X X X 5 6 2 x don t care Data Transfer Port for Error Correction This port writes data before error correction and reads data after error correction When correcting an error in a horizontal vertical direction after clearing the internal memory address counter write 34 272 bytes of data to this port After correcting an error in a horizontal vertical direction clear the internal memory address counter then read 34 272 bytes of data from this port When reading or writing data for this port it is unnecessary to specify the horizontal vertical direction error correction mode Address Read write Reset DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 021H Read write value Undefined Undefined U
50. ts before block synchronization DB1 DBO Allowable Number of Erroneous Bits in BIC Before Block Synchronization 0 0 0 0 1 1 1 0 2 1 1 3 2 Allowable number of erroneous BIC bits after block synchronizaiton DB3 DB2 Allowable Number of Erroneous Bits in BIC After Block Synchronization 0 0 0 0 1 1 1 0 2 1 1 3 5 4 2 Number of Block Synchronization Backward Protection Steps This register specifies the number of block synchronization backward protection steps When block identification codes BICs are successively detected for a specified number of times the internal bit counter and the bit position of the block 0 287 are synchronized This register is used for initial settings DB7 DB6 DBS 084 DB3 DB2 DB1 DBO Address Read write Reset 011H Write value 0 1 1 DBO DB1 Number of block synchronization backward protection steps DB1 DBO Block proving in synchronization step count 0 0 Inhibit 0 1 2 1 0 3 1 1 4 5 4 3 Number of Block Synchronization Forward Protection Steps This register specifies the number of block synchronization forward protection steps If BICs cannot be detected successively for a specified number of times after block synchroniza tion the block is regarded as out of synchronization This register is used for initial settings 1 DB7 086 DBS 084 DB3 DB2 DBO
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