FM480 User Manual
Contents
1. follows Pin Signal Signal Pin 1 3 3V GND 2 3 3 3V GND 4 5 3 3V GND 6 7 3 3V GND 8 9 5V GND 10 11 5V GND 12 13 5V GND 14 15 5V GND 16 17 12V GND 18 19 12V GND 20 21 12V GND 22 23 12V GND 24 25 GND reserved 26 27 reserved reserved 28 29 reserved reserved 30 31 reserved reserved 32 33 GND Table 9 Daughter card power connector pin assignment on PMC side 2 FM480 User Manual March 2006 www 4dsp com 16 FM480 USER MANUAL Joe T 4 Power requirements The Power is supplied to the FM480 via the PMC connectors Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board Optionally the FM480 can be used as a stand alone module and is powered via the external power connector The FM480 power requirements are as follow Device Interface Voltage Maximum current DCI and memory reference voltage 0 85V 0 5A Virtex 4 device B core 1 2V 12A Virtex ll Pro device core 1 5V 6A QDR2 DDR2 SDRAM and I O banks 1 8V 10A Virtex 4 abd Virtex Il Pro devices I O banks Virtex 4 device B bank connected to the 1 8V 2 5 3 3V 1 5A front panel daughter card Virtex Il Pro device A I O bank connected to 3 3V 2A the PCI bus Flash CPLD front Panel I O daughter card Front Panel IO daughter card 5V 1A Front Panel IO daughter card 12V 0 5A Front Panel IO daughter card2. 13 3 4 2 DDR2 SDRAM ee eee eee 13 3 5 Front Panel IO daughter 14 3 5 1 Virtex 4 device to I O front Panel daughter card 14 only available with daughter card 14 3 5 2 Power connection to the front panel I O daughtercard 16 4 Power 17 4 1 External power connector eee ea ti AR 18 5 Environment pM 19 5 1 Temperature ai ed E E LR ER EE ELLOS ERA EE EAE LOGER ESL EE EE LG EL 19 5 2 us pEED P eee 19 5 3 Conduction Cooling ete EEL BREE ane 19 MERCI EE 19 T EMO nn 19 8 19 FM480 User Manual March 2006 www 4dsp com 3 FM480 USER MANUAL Joe TT 1 Acronyms and related documents 1 4 Acronyms ADC Analog to Digital Converter DAC Digital to Analog Converter DC Digitally Controlled Impedance DSP EPROM FBGA Fineline Ball Grid Array FPDP FPGA JTAG LVTTL LVDS LSB LVDS it s SDRAM Synchronous Dynamic Random Access memory Table 1 Glossary LED S MGT MSB PCB PC
3. User I O PCI X PCI 66 33MHz 64 32 bit Figure 1 FM480 block diagram FM480 User Manual March 2006 www 4dsp com 5 FM480 USER MANUAL Joe TT 2 Installation 2 4 Requirements and handling instructions e The FM480 must be installed on a motherboard compliant to the IEEE Std 1386 2001 standard for 3 3V PMC e Do not flex the board e Observe SSD precautions when handling the board to prevent electrostatic discharges Do not install the FM480 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The FM480 is delivered with an interface to the Xilinx PCI core in the Virtex Il Pro device and an example VHDL design the Virtex 4 device so users can start performing high bandwidth data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the FM480 Get Started Guide 3 Design 3 1 FPGA devices The Virtex Il Pro and Virtex 4 FPGA devices interface to the various resources on the FM480 as shown on Figure 1 They also interconnect to each other via 86 general purpose pins and 2 clock pins 3 1 1 Virtex Il Pro device 3 1 1 1 Virtex Il Pro device A family and package The Virtex Il Pro device is a XC2VP7 in a Fineline Ball Grid array with 672 balls FF672 3 1 1 2 Power PC embedded processor IBM Power
4. FM480 USER MANUAL Joe vid FM480 User Manual 4DSP Inc 1757 Fox Run road Reno NV 89509 0907 USA Email support 4dsp com This document is the property of 4DSP Inc and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP Inc 2006 FM480 USER MANUAL Joe Revision History 03 22 06 Initial release FM480 User Manual March 2006 www 4dsp com FM480 USER MANUAL Joe T Table of Contents 1 Acronyms and related 4 1 1 ree teet eu EH EE 4 1 2 Related 4 1 3 GeneraldescriptiOnozz eee eee 5 2 Jnstallation 4 6 2 1 Requirements handling instructions 6 2 2 Flim Ware 5 6 3 6 3 1 FPGA devices iiid iid dated da LLL 6 3 1 1 Vinex Pro device 6 3 1 2 Virtex 4 device 9 3 2 FPGA devices configuration 10 3 2 1 Flash storage ugue BEGUN eH HOHER 10 3 2 2 10 3 2 3 biu etus btt bt obtuso etc 12 3 3 CIOCKS ii ee eee eee 12 3 4 Memory Tesources 2 p hoes Woh ieee eben Bane 13 3 4 1 QDR2 SRAM
5. a host computer via the JTAG connector The FPGA devices configuration can also be performed using the JTAG FM480 User Manual March 2006 www 4dsp com 10 FM480 USER MANUAL Joe T 3 2 2 1 Jumper A Jumper J1 is connected to the CPLD and is used to choose the FPGA configuration scheme The jumper is located next to the Pn3 connector The Jumper positions are defined as follows ON JTAG chain enabled for FPGAs configuration FPGAs are not configured from the flash OFF Configuration from the flash enabled if valid FPGA bitstreams are stored in the flash OFF to The Virtex Il Pro safety configuration is loaded from the Flash into the ON Virtex Il Pro This scheme is to be used only to allow a user to reprogram the flash with valid FPGA bitstreams Table 3 Jumper 3 2 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status LED 1 Blinking FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured LED 2 Blinking FPGA A or B bitstream or user ROM register is currently being written to the flash ON FPGA B not configured OFF FPGA devices configured LED 3 Blinking The Pro FPGA has been configured with the safety configuration bitstream programmed in the flash at factory Please write a valid Virtex ll Pro bitstream in the flash ON Flash is bu
6. 12V 0 5A Table 10 Power supply PMC connectors 12V Front Panel I O 12V daughter card 5V 33 1 gt Power switch 18V DC DC 3 3V or 2 5V converter to Front Panel DC DC converter DC DC 2 5 converter DC DC 1 8V converter DC DC 1 5V 4 converter 1 2V converter DC DC 0 85V converter 5V 3 3V External Power connector Figure 4 Power supply FM480 User Manual March 2006 www 4dsp com 17 FM480 USER MANUAL Joe vidi An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex Il Pro device Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V and 0 85V rails It also displays the Virtex 4 junction temperature 4 1 External power connector An external power connector J2 is available on side 2 of the PMC next to the PMC connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered in its stand alone version FM480 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in a
7. the Xilinx termination options to match the signals impedance allows many electrical standards to be supported by this interface All signals are routed as 100 ohm LVDS pairs The VRP and VRN pins on the I O banks connected to the daughter card connector are respectively pulled up and pulled down with 50 ohm resistors in order to ensure optimal performances when using the Xilinx DCI options The VREF pins are connected to 0 85V for DDR2 DCI terminations Please contact 4DSP Inc for more information about the daughter card types available The 120 pin Samtec connector pin assignment is as follows All signals are shown as LVDS pairs in the table but they can be used for any standard that does not breach the electrical rules of the Xilinx I O pad Connector Signal FPGA FPGA Signal Connector pin Name pin pin name pin 1 FP W24 AA23 FP P1 2 3 FP NO Y24 24 FP 1 4 5 FP P270 AA25 AA28 FP P3 6 7 FP 22 AA26 AA29 FP N3 8 9 FP P4 AB30 28 FP P5 10 11 FP AA30 AB28 FP N5 12 13 FP P6 AB22 AD27 P7 14 15 FP N6 AB23 AC27 FPN7 16 17 FP P8 AC29 AC32 FP P9 18 19 FP N8 AC30 AC33 FP N9 20 21 FP P107 AD34 AE32 FP P11 22 23 FP N10 AC34 AD32 FP N11 24 25 FP P12 AE29 AF31 FP P13 26 27 FP N12 AD29 AE31 FP N13 28 29 FP P14 AE33 AF33 FP P15 30 31 FP N14 AE34 AF34 FP N15 32 33 FP P16 AH19 AF29 FP P170 34
8. 1 AF2 Pn4 1059 62 63 4 1062 AD4 Pn4 1060 64 Table 2 Pn4 pin assignment FM480 User Manual March 2006 www 4dsp com 8 FM480 USER MANUAL Joe TT 3 1 2 Virtex 4 device B 3 1 2 1 Virtex 4 device B family and package The Virtex 4 device B is dedicated to Digital Signal Processing applications and can be chosen from the SX or LX family devices Its package is based on Fineline Ball Grid array with 1148 balls In terms of logic and dedicated DSP resources it is available in 5 different sizes SX55 LX40 LX60 LX80 LX100 and LX160 The speed grade and temperature operating range can be chosen upon customer requirements 3 1 2 2 Virtex 4 device B external memory interfaces The Virtex 4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32 bit data bus Please note that the four QDR2 SRAM devices are only available with the LX80 LX100 and LX160 devices For smaller Virtex 4 FPGAs LX40 LX60 and SX55 only three QDR2 SRAM devices are connected to the FPGA 3 1 2 3 Virtex 4 device B interface to Front Panel daughter card The Virtex 4 device B interfaces to the front panel daughter card on the FM480 via a high speed connector 120 I Os are available from the FPGA to from the daughter card Refer to the Front Panel I O section of this document for more details about the daughter card connector electrical characteristics FM480 User Manual March 2006 www 4dsp com 9 FM480 USER MANUAL Joe TT 3 2 FP
9. 35 FP N16 AH18 AF30 N17 36 37 FP 18 18 AG30 FP P19 38 39 FP N18 AG17 AG31 FP N19 40 Table 6 Front Panel IO daughter card pin assignment Bank A Connected to a global clock pin on the FPGA LVDS output not supported Connected to a regional clock pin on the FPGA LVDS output not supported FM480 User Manual March 2006 www 4dsp com 14 FM480 USER MANUAL Joe TT Connector FPGA FPGA Connector pin Differential pin pin Differential pin 41 FP P20 AG32 AJ34 FP P21 42 43 FP N20 AG33 AH34 FP N21 44 45 FP P22 AH32 AJ30 FP_P23 46 47 FP_N22 AH33 AH30 FP_N23 48 49 FP P24 AK31 AK33 FP P25 50 51 FP N24 AK32 AK34 FP N25 52 53 FP P26 AL33 AM31 FP P27 54 55 FP N26 AL34 AL31 FP N27 56 57 FP P28 AM32 AP30 FP P29 58 59 FP N28 AM33 AN30 FP N29 60 61 FP P30 AM30 AH28 FP P31 62 63 FP N30 AL30 AH29 FP N31 64 65 FP P32 AK29 AL28 FP P33 66 67 FP N32 AJ29 AL29 FP_N33 68 69 FP P34 AP29 AN28 FP P352 70 71 FP N34 AN29 AM28 FP N35 72 73 FP P36 AG27 AG28 FP N36 74 75 3 3V 2 5V 1 8V 76 77 3 3V 2 5V 1 8V 0 9V 78 79 3 3V 2 5V 1 8V 3 3V 2 5V 1 8V 80 81 FP_P37 AF28 AJ27 FP_P38 82 83 FP_N37 AE27 AH27 FP_N38 84 85 FP_P39 AM26 AP27 FP_P40 86 87 FP_N39 AM27 AN27 FP_N40 88 89 FP P41 AP25 AL26 FP P42 90 91 FP N41 AP26 AK26 FP N42 92 93 P43 AG25 AF26 FP P44 9
10. 4 95 FP N43 AG26 AE26 FP N44 96 97 FP 45 AL24 AN25 FP 46 98 99 FP N45 AL25 AM25 FP N46 100 101 FP P47 AP24 AK24 FP_P48 102 103 FP_N47 AN24 AJ24 FP_N48 104 105 FP_P49 AG23 AK22 FP_P50 106 107 FP_N49 AF24 AK23 FP N50 108 109 FP P51 AL23 AN22 FP_P52 110 111 FP N51 AM23 AN23 FP N52 112 113 FP P530 AJ17 AP21 FP P54 114 115 FP 53 AH17 AP22 FP N54 116 117 FP 55 AE17 AK21 FP_P56 118 119 FP N55 AE16 AL21 FP N56 120 Table 7 Front Panel IO daughter card pin assignment Bank B and C Connected to a global clock pin on the FPGA LVDS output not supported 2 Connected to a regional clock pin on the FPGA LVDS output not supported 9 is connected to Virtex Il Pro device A and Virtex 4 device B Vbatt pin FM480 User Manual March 2006 www 4dsp com 15 FM480 USER MANUAL HOS V1 0 3 5 2 Power connection to the front panel I O daughtercard The Front Panel I O daughter card on side 1 of the PCB is powered via a 7 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as follows Pin Signal Signal Pin 1 3 3V 3 3V 2 3 5V GND 4 5 12V GND 6 7 12V Table 8 Daughter card power connector pin assignment on PMC side 1 On side 2 of the PCB the daughter card is powered via a 33 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connector s pin assignment is as
11. GA devices configuration 3 2 1 Flash storage The FPGA firmware is stored on board in a flash device The 256Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex Il Pro and Virtex 4 devices are directly configured from flash if a valid bitstream is stored in the flash for each FPGA The flash is pre programmed in factory with the default Virtex Il pro firmware and a Virtex 4 firmware example JTAG Header S29GL256M 256Mbit Flash Clock 50MHz CoolRunner ll CPLD XC2C256 VQ100 Virtex ll Pro device A Figure 2 Configuration circuit 3 2 2 CPLD device As shown on Figure 2 a CPLD is present on board to interface between the flash device and the FPGA devices It is of type CoolRunner ll The CPLD is used to program and read the flash The data stored in the flash are transferred from the host motherboard via the PCI bus to the Pro device A and then to the CPLD that writes the required bit stream to the storage device A 50 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices it will start reading programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from
12. I PLL PMC RA Multi Gigabit Transceiver M 1 2 Related Documents e EEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC e ANSI VITA 39 2003 PCI X for PMC and Processor PMC ANSI VITA 20 2001 Conduction Cooled PMC e EEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family e Xilinx Virtex 4 user quide e Xilinx PCI X core datasheet FM480 User Manual March 2006 www 4dsp com 4 FM480 USER MANUAL Joe TT 1 3 General description The FM480 is a high performance PMC dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements PCI X and backward compatible the FM480 offers various interfaces fast on board memory resources and one Virtex 4 FPGA It can be utilized for example to accelerate frequency domain algorithms with off the shelf Intellectual Property cores for applications that require the highest level of performances The FM480 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document Front Panel IO daughter card VIRTEX FPGA XC4VSX55 XCAVLX40 60 e osm XC4VLX80 100 160 clocks 88 Not on LX40 60 or SX55 Virtex Il Pro XC2VP7 Configuration circuit and JTAG LED x4 FPGA A Local PCI bus interface Power supply DC DC converters
13. PC RISC processor cores is available in the Virtex ll Pro device A This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA 3 1 1 3 Virtex Ill Pro device A external memory interfaces The Virtex Il Pro device A is connected to two 128Mbytes SDRAM devices with 16 bit data bus width These memory resources can be used by the PowerPC core or can serve as data buffers 3 1 1 4 PCI interface The Virtex Il Pro device A interfaces directly to the PCI bus via the PMC P1n P2n and P3n connectors An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system the motherboard PCI X 64 bit 66MHz 133MHz PCI 64 bit 66MHz FM480 User Manual March 2006 www 4dsp com 6 FM480 USER MANUAL 19 TT and PCI 32 bit 33MHz are supported on the FM480 The bus type must be communicated at the time of the order so the right Pro firmware can be loaded into the flash prior delivery The following performances have been recorded with the FM480 transferring data on the bus gt PCI X 64 bit 133MHz 650Mbytes s sustained gt PCI X 64 bit 66MHz 450Mbytes s sustained gt PCI 32 bit 33MHz 120Mbytes s sustained 3 1 1 5 LED Four LEDs are connected to the Virtex Il Pro device In the default FPGA firmware the LEDs are driven by the Virtex 4 device via the Virtex Il Pro Virtex 4 interface The LEDs are located on side 2 of the PCB in the front panel a
14. e system 8 Warranty Basic Warranty included Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty optional 2 Years from Date of Shipment 1 Year from Date of Shipment FM480 User Manual March 2006 www 4dsp com 19
15. n enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J1 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows Pin Signal Signal Pin 1 3 3V 3 3V 2 3 5V 5V 4 5 GND GND 6 7 GND GND 8 9 12V 12V 10 Table 11 External power connector pin assignment FM480 User Manual March 2006 www 4dsp com 18 FM480 USER MANUAL OS vid 5 Environment 5 1 Temperature Operating temperature e OC to 60 Commercial e 40C to 85 C Industrial Storage temperature e 40C to 120C 5 2 Convection cooling 600LFM minimum 5 3 Conduction cooling The FM480 can optionally be delivered as conduction cooled PMC The FM480 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 6 Safety This module presents no hazard to the user 7 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through th
16. rch 2006 www 4dsp com 12 FM480 USER MANUAL Joe T 3 4 Memory resources 3 4 1 QDR2 SRAM Four independant QDR2 SRAM devices are connected to the Virtex 4 device B The QDR2 SRAM devices available on the FM480 are 2M words deep 8Mbytes per memory device Please note that only three QDR SRAM devices are available to the user if the XC4VLX40 XC4VLX60 or XC4VSX55 FPGA device is mounted on board 3 4 2 DDR2 SDRAM Two 8 bit DDR2 SDRAM devices are connected to Virtex Il Pro device A The two memories share a common address bus and can be considered as a single DDR2 SDRAM bank of 128Mbytes with a 16 bit data bus width These memory resources are primarily intended to be accessed by the PowerPC processor in the Virtex Il Pro device A They can however be used for any purpose FM480 User Manual March 2006 www 4dsp com 13 FM480 USER MANUAL Joe T 3 5 Front Panel IO daughter card 3 5 1 Virtex 4 device B to I O front Panel daughter card only available with daughter card purchase The Virtex 4 device B interfaces to a 120 pin connector placed in the Front panel I O area on both side 1 and side 2 of the PCB It serves as a base for a daughter card and offers I O diversity to the FM480 PMC On side 2 of the PCB the connectors and mounting holes placement complies with the SLB standard except for the 2 5V mounting holes that are not present on this module The FPGA banks are powered either by 1 8V 2 5V or 3 3V Using
17. rea LEDO P LED 1 LED2 LED 3 a E FM480 User Manual March 2006 www 4dsp com 7 FM480 USER MANUAL Joe vi 3 1 1 6 Pn4 user I O connector The 64 pin Pn4 connector is wired to the Virtex Il Pro device A All signals are user defined 3 3V LVTLL Connector Signal FPGA FPGA Signal Connector pin name pin pin name pin 1 Pn4 IOO P2 P3 Pn4 101 2 3 Pn4 IO2 P4 P5 Pn4 103 4 5 Pn4 104 P6 P7 Pn4 105 6 7 4 106 R1 R2 Pn4 107 8 9 Pn4 108 R3 R4 Pn4 109 10 11 Pn4 1010 R5 R6 Pn4_1011 12 13 Pn4 1012 P8 R8 Pn4_1013 14 15 Pn4 1014 T1 T2 4 1015 16 17 4 1016 4 4 1017 18 19 4 1018 5 T6 Pn4_1019 20 21 Pn4_ 1020 R7 T7 4 1021 22 23 Pn4 1022 T8 U7 Pn4_1023 24 25 Pn4 1024 U1 V1 4 1025 26 27 4 1026 U3 U4 4 1027 28 29 Pn4 1028 U5 U6 Pn4_ 1029 30 31 Pn4 IO30 V2 V3 Pn4_1031 32 33 Pn4 1032 V4 V5 Pn4_1033 34 35 Pn4_1034 V6 V7 4 1035 36 37 Pn4 1036 W1 W2 Pn4 1037 38 39 Pn4 1038 W3 WA 4 1039 40 41 4 1040 W5 W6 Pn4_1041 42 43 Pn4 1042 Y1 AA1 Pn4_1043 44 45 Pn4 1044 Y3 Y4 4 1045 46 47 4 1046 Y5 Y6 4 1047 48 49 4 1048 N7 N6 Pn4 1049 50 51 Pn4 1050 N5 N4 4 1051 52 53 Pn4 1052 N3 N2 4 1053 54 55 4 1054 AB3 AB4 4 1055 56 57 4 1056 AC1 2 4 1057 58 59 4 1058 AD1 AD2 4 1058 60 61 4 1060 AE
18. sy writing or erasing OFF Flash device is not busy ON CRC error Presumably a wrong or corrupted FPGA bitstream LED 4 has been written to the flash Once on this LED remains on OFF No CRC error detected Table 4 LED board status The LEDs are located on side 2 of the PCB in the front panel area FM480 User Manual March 2006 www 4dsp com 11 FM480 USER MANUAL TT 3 2 3 JTAG A JTAG connector is available on the FM480 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope Please note that three Xilinx devices will be detected in the JTAG chain The JTAG connector is located on side 1 of the PCB in front of Pn3 The JTAG connector pinout is as follows Pini Pin Signal Signal Pin 1 1 8V TMS 4 2 GND TDI 5 3 TCK TDO 6 Table 5 JTAG pin assignment 3 3 Clocks 50MHz oscillator on board connects to a low skew 1 4 clock buffer ICS553 Each FPGA device and the CPLD receive this 50MHz clock By using the DCM resources inside the FPGA clocks are generated for the various interfaces on board Figure 2 shows how the clocks signals between the FPGAs and the CPLD are connected The IO pin number is provided for each device Virtex 4 device B Clock E 50MHz Virtex ll Pro device CPLD XC2C256 VQ100 Figure 3 Clocks FM480 User Manual Ma
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