Errata Sheet
Contents
1. Due to internal improvements the internal timing of the A D converter of the FA and following steps is slightly different from previous versions which is reflected in a different way of specifying the ADC When ADCON 15 12 0000b default the conversion time tc of the A D converter of the FA and following steps is identical to previous steps while the sample time ts is increased by a factor of 1 33 For ADCON 15 12 0000b tc and or ts may be different from previous steps Since the FA GA and HA steps are produced in a different technology than previous steps it is recommended to check the overall ADC accuracy in the target system with respect to the impedance of the analog signal and the analog reference voltage This should be done in particular when the FA GA HA steps are operated at a higher frequency than previous steps Timing of flag SSCTIR SSC Transmit Interrupt Request In master mode the timing of SSCTIR depends on the device step as follows a before step FA flag SSCTIR is set to 1 synchronous to the shift clock SCLK 1 2 bit time before the first latching edge first shifting clock edge when SSCPH 0 When SSCTB is written while the shift register is empty the maximum delay between the time SSCTB has been written and flag SSCTIR 1 is up to 1 2 bit time beginning with step FA when SSCTB has been written while the transmit shift register was empty and the SSC is enabled flag SSCTIR is set to 12. ADD B ADDC B CMP B CMPD1 2 CMPI1 2 SUB B SUBC B AND B OR B XOR B ASHR MOV B MOVBZ MOVBS SCXT PUSH PCALL analysis must be repeated for successor of PUSH PCALL The following instructions most of them with immediate or register Rx addressing modes can never cause a problem when they are successors of PUSH PCALL CPL B NEG B DIV U DIVL U MUL U SHL SHR ROL ROR PRIOR POP RETI updates complete PSW with stacked value RETP updates condition flags PWRDN program restarts after reset SRST program restarts Conditional branch instructions which may evaluate the Z flag as successors of PUSH PCALL JB JNB Z rel directly evaluates Z flag CALLA CALLI JMPA JMPI JMPR with the following condition codes cc_Z cc_EQ cc_NZ cc_NE cc_ULE cc_UGT cc_SLE cc_SGT cc_NET For these branch conditions the branch may be performed in the wrong way For other branch conditions the branch target as well as the linear successor of the branch instruction must be analyzed since these branch instruction don t modify the PSW flags For instructions that have no effect on the condition flags and that don t evaluate the Z flag the instruction that follows this instruction must be analyzed These instructions are NOP ATOMIC EXTxx DISWDT EINIT IDLE SRVWDT CALLR CALLS JMPS branch target must be analyzed RET RETS _ return target must be analyzed value pushed by PUSH PCALL return IP Z flag contains inf
3. PLL Operation A D Converter Characteristics ADCC 2 3 ADC Overload Current During exceptional conditions in the application system an overload current lcan occur on the analog inputs of the A D converter when Vin gt Va OF Van lt Va For this case the following conditions are specified in i Data Sheet Bia 2S MA The P total unadjusted error TUE a 2 LSB is only guaranteed if overload conditions occur on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA It is also allowed to distribute the overload to more than 2 not selected analog input pins Due to an internal problem the specified TUE value is only met for a positive overload current 0 mA lt lv lt 5 mA all currents flowing into the microcontroller are defined as positive and all currents flowing out of it are defined as negative If the exceptional conditions in the application system cause a negative overload current then the maximum TUE can be exceeded depending on value of and Rape Problem Description in Detail 1 Overload Current at analog Channel ANn n e 1 11 and Influence to V If an overload current l occurs on analog input channel ANn then an additional current larer crosstalk current is caused at pin Viper Depending on Rrr the internal resistance of the reference voltage the crosstalk current laper at Microcontroller Division Errata Sh
4. ADC Overload Current DA step only m N 1D gt History List C167CR 4RM since device step AB Functional Short Description Fixed in Problem step ADC 11 Modifications of ADM field while bit ADST 0 i 4 SSC 9 Data Transmission in Slave Mode steps gt FA only BUS 17 Spikes on CS Lines after access with RDCS and or WRCS e BUS 18 PEC Transfers after JMPR Instruction Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 20 of 29 BUS 19 Uniatched Chip Selects at Entry into Hold Mode not in DB and earlier steps __ CPU 21 BELDLIH instructions after Write Operation tointemaliRAM opuze _ zFlagafterPUSHandPoaL ooo o o o Read Access to XPERs in Visible Mode o E Unexpected Remote Frame Transmission ooo nee EES FA Reset ADC 8 CC31 ADC Interference ADC 10 Start of Standard Conversion at End of Injected Conversion SSC 8 Data Transmission in Slave Mode Step EES FA only ES FA POH spikes after XPER write access and external 8 bit Non multiplexed bus EES FA PINS 1 OUTPUT Signal Rise Time DA step only lps Deviation step DC IALEL 1 ALE inactive current 30pA steps gt FA ony CLKOUT rise time steps GA only CLKOUT fall time steps GA only Input Hysteresis Special Threshold step HA only ADCC 2 3 ADC Overload Current steps gt FA only DC VOL 1 Output low voltage Port0 1 4 ALE RD WR test condition 1 6mA AC step
5. ES HA HA e Step HA included e Version C167CR LE in P BGA 176 2 Package included e Documentation Reference updated Data Sheet C167CR SR Data Sheet V3 3 2005 02 User s Manual C167CR Derivatives User s Manual V3 2 2003 05 e Data Transmission in Slave Mode SSC 9 e Edge Selection for Capture Function if CT3 1 and Cl 01b or 10b T5CON D1 Documentation Update e Write access to registers PWx and PPx while bit PTRx 0 PWM D1 Documentation Update Functional Problems ADC 11 Modifications of ADM field while bit ADST 0 The A D converter may unintentionally start one auto scan single conversion sequence when the following sequence of conditions is true 1 the A D converter has finished a fixed channel single conversion of an analog channel n gt 0 i e contents of ADCON ADCH n during this conversion 2 the A D converter is idle i e ADBSY 0 3 then the conversion mode in the ADC Mode Selection field ADM is changed to Auto Scan Single ADM 10b or Continuous ADM 11b mode without setting bit ADST 1 with the same instruction Under these conditions the A D converter will unintentionally start one auto scan single conversion sequence beginning with channel n 1 down to channel number 0 In case the channel number ADCH has been changed before or with the same instruction which selected the auto scan mode this channel number has no effect on the unintended auto scan sequence i e it is not used
6. bit CT3 0 and select the edge type rising falling any in bit field Cl to C167CR User s Manual V3 2 2003 05 p 16 16 PWM D1 Write access to registers PWx and PPx while bit PTRx 0 Clearing the timer run bit PTRx stops the associated counter PTx The level on the individual PWM channel outputs is controlled by comparators according to the formula PWM output signal PTx gt PWx shadow latch While PTRx 0 the PWx and PPx registers are transparent i e a write to PWx and PPx will directly update the shadow registers as long as the corresponding timer run bit PTRx 0 So whenever software changes registers PTx or PWx the respective output will reflect the condition after the change E g loading timer PTx with a value greater than or equal to the value in PWx immediately sets the respective output a PTx value below the PWx value clears the respective output Product and Test Engineering Group Munich Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 29 of 29
7. depends on the program context In most cases it will be sufficient to just analyze the instruction following PUSH or PCALL In case of PCALL this is the instruction at the call target address Support Tool for Analysis of Hex Files For complex software projects where a large number of assembler source or list files would have to be analyzed Infineon provides a tool aiScan22 which scans hex files for critical instruction sequences and outputs diagnostic information This tool is available as part of the Application Note ap1679 Scanning for Problem CPU 22 which can be found via the link to 16 bit Microcontroller Application Notes on http www infineon com c166 family Direct links to documentation and software http www infineon com cmc_upload documents 040 841 ap1679 v1 1 2002 05 scanning cpu22 pdf http www infineon com cgi ecrm dll ecrm scripts public_download jsp 0id 40840 amp parent_oid 8137 Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 7 of 29 Individual Analysis of Assembler Source Code With respect to problem CPU 22 all instructions of the C166 instruction set can be classified into the following groups Arithmetic logic data movement instructions as successors of PUSH PCALL correctly modify the condition flags in the PSW according to the result of the operation These instructions may only cause a problem if the PSW is a source or source destination operand
8. and 2 the previous bus cycle was a read cycle with RDCSy bit BUSCONy CSRENy 1 or a write cycle with WRCS bit BUSCONy CSWENy 1 The position of the spikes is at the beginning of the new bus cycle which is performed via CSx synchronous with the rising edge of ALE and synchronous with the rising edge of RD WR of the previous bus cycle Potential effects on applications when CS lines are used as CE signals for external memories typically no problems are expected since the spikes occur after the rising edge of the RD or WR signal when CS lines configured as RDCS and or WRCS are used e g as OE signals for external devices or as clock input for shift registers problems may occur temporary bus contention for read cycles unexpected shift operations etc When CS lines configured as WRCS are used as Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 9 of 29 WE signals for external devices no problems are expected since a tristate waitstate should be used anyway due to the negative address hold time after WRCS t55 without tristate WS Workarounds 1 Use a memory tristate WS i e leave bit BUSCONy 5 0 in all active BUSCON registers where RD WR CS is used i e bit BUSCONy CSRENy 1 and or bit BUSCONy CSWENy 1 or 2 Use Address CS instead of RD WR CS i e leave bits BUSCONy 15 14 00b for all BUSCONy registers where a non multiplexed bus without tristate W
9. and or high byte of the specific bit addressable IRAM location OFDOOh 2 v i e the 8 bit offset address of the location in the bit addressable IRAM area OFDOOh OFDFFh equals v When the problem occurs the actual result all 16 bits of the BFLDx instruction is bitwise ORed with the byte or word result of the previous instruction or PEC transfer Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 3 of 29 Notes Write operations in the sense of the problem description include implicit write accesses caused by auto increment operations of the PEC source or destination pointers which are located on OFCEOh 0FCFEh in IRAM post increment pre decrement operations on GPRs addressing modes with R or R write operations on the system stack which is located in IRAM In case PEC write operations to IRAM locations which match the above criteria bit addressable or active register bank area PEC pointers not overlapping with register bank area can be excluded the problem will not occur when the instruction preceding BFLDx in the dynamic flow of the program is one of the following instructions which do not write to IRAM NOP ATOMIC EXTx CALLA CALLI JBC JNBS when branch condition false JMPx JB JNB RETx except RETP CMP B except addressing mode with Rwi BCMP MULx DIVx IDLE PWRDN DISWDT SRVWDT EINIT SRST For implicit IRAM write operations caused by auto incr
10. directly after completion of the write operation independent of the selected baud rate When the transmit shift register is not empty when SSCTB was written SSCTIR is set to 1 after the last latching edge of SCLK 1 2 bit time before the first shifting edge of the next character See also e g C167CR User s Manual V3 1 p 12 5 The following diagram shows these relations in an example for a data transfer in master mode with SSCPO 0 and SSCPH 0 It is assumed that the transmit shift register is empty at the time the first character is written to SSCTB Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 26 of 29 write to SSCTB first character write to SSCTB next character SCLK MTSR case a SSCTIR 1 in previous device steps A case b SSCTIR 1 in current and future device steps Typically in interrupt driven systems no problems are expected from the modified timing of flag SSCTIR However when flag SSCTIR is polled by software in combination with other flags which are set cleared at the end or at the beginning of a transfer e g SSCBSY the modified timing may have an effect Another situation where a different system behaviour may be noticed is the case when only one character is transferred by the PEC into the transmit buffer register SSCTB In this case 2 interrupt requests from SSCTIR are expected the PEC COUNT 0 interrupt and the SSCTB empty interru
11. 2 the transmit buffer SSCTB of the slave has not been written prior to the start of the reception initiated by the master asserting the shift clock SCLK and 3 a specific time window phase delay is hit by the serial shift clock SCLK in relation to the internal system clock of the slave Therefore this synchronization problem will occur in particular when the slave device is clocked on XTAL1 by an external clock generation circuit which is independent from the clock generation circuit of the master i e slave and master clocks are asynchronous When the problem occurs this results in missing bits in the character received in SSCTB and in duplicated bits in the character transmitted on pin MRST of the slave As a consequence interrupt generation in the slave is delayed by the number of missed bits Workaround For systems using the falling edge of SCLK as latching edge see condition 1 above always write to the transmit buffer SSCTB prior to any reception in slave mode of the SSC module For the second and all following characters e g write a dummy character to SSCTB in the receive interrupt routine or use a PEC transfer triggered by the transmit interrupt request to write to SSCTB In this case the critical synchronization path is not used and the problem will not occur CPU 21 BFLDL BFLDH Instructions after Write Operation to internal IRAM The result of a BFLDL BFLDH BFLDx instruction may be incorrect if the following co
12. Infineon technologies Microcontrollers Errata Sheet March 30 2005 Release 1 1 Device SAK C167CR L 33 M SAF C167CR L 33 M SAB C167CR L 33 M SAK C167CR 4R 33 M SAF C167CR 4R 33 M SAB C167CR 4R 33 M SAK C167CR 16R 33 M SAF C167CR 16R 33 M SAB C167CR 16R 33 M SAK C167SR L 33 M SAB C167SR L 33 M SAK C167CR LE Stepping Code Marking ES HA HA HA Package P MQFP 144 8 C167 M P BGA 176 2 C167 E This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur The current documentation is Data Sheet C167CR SR Data Sheet V3 3 2005 02 User s Manual C167CR Derivatives User s Manual V3 2 2003 05 Instruction Set Manual V2 0 2001 03 Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 1 of 29 Change summary to Errata Sheets Rel 1 0 for C167CR SR devices with stepping code marking ES HA HA to this Errata Sheet Rel 1 1 for C167CR SR devices with stepping code marking
13. PER access and external 8 bit Non multiplexed bus X12 POH spikes after XPER write access and external 8 bit Non multiplexed bus ES FA DA step only PINS 1 OUTPUT Signal Rise Time DA step only ES FA AC DC Short Description Fixed in Deviation step DC IALEL 1 ALE inactive current 30 LA steps gt FA only El AC PLL 1 PLL base frequency GA GA T JA HA steps only k AC PLL 2 PLL base frequency 8 MHz GA GA T JA steps with date code gt 0114 DC tc8 5 CLKOUT rise time steps gt GA only DC tc9 5 CLKOUT fall time steps gt GA only Input Hysteresis Special Threshold step HA only ADCC 2 3 ADC Overload Current steps gt FA only m 7 gt ALE active current 1000A DA step only DC IRWL 1 RD WR active current 600UA DA step only DC IP6L 1 Port 6 active current 600 A DA step only a he YM W W TI gt m m z fa gt gt DC IPOL 1 Port 0 configuration current 110uA DA step only AC t5 1 ALE high time TCL 15ns DA step only m N n z gt AC t12 1 WR WRH low time with RW delay 2TCL 12ns DA step only AC t13 1 WR WRH low time no RW delay 3TCL 12ns DA step only AC 138 1 ALE falling edge to CS 7ns DA step only AC 148 1 RDCS WRCS low time with RW delay 2TCL 12ns DA step only m m v JV a gt gt m o o gt m m ee oe oe ee ee ee ee 7 7 gt gt AC t49 1 RDCS WRCS low time no RW delay 3TCL 12ns DA step only ADCC 2 2
14. Registers after Reset After any reset the contents of the CAN Message Objects 1 15 MCR UAR LAR MCFG Data 0 7 and the Mask of Last Message Registers LMLM UMLM may be undefined instead of unchanged reset value X instead of U This problem depends on temperature and the length of the reset and differs from device to device The problem is more likely but not restricted to occur at high temperature and for long hardware resets gt 100 ms Workaround Re initialize the CAN module after each reset Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 13 of 29 Application Hints Note on Interrupt Register behaviour of the CAN module Due to the internal state machine of the CAN module a specific delay has to be considered between resetting INTPND and reading the updated value of INTID See Application Note AP29024 Interrupt Register behaviour of the CAN module which can be found via the link to 16 bit Microcontroller Application Notes on http Awww infineon com c166 family Direct Link http www infineon com cgi ecrm dll ecrm scripts public_download jsp o0id 10178 amp parent_oid 53087 Handling of the SSC Busy Flag SSCBSY In master mode of the High Speed Synchronous Serial Interface SSC when register SSCTB has been written flag SSCBSY is set to 1 when the baud rate generator generates the next internal clock pulse The maximum delay between the time SSCTB has been w
15. S is configured i e bit BUSCONYy 5 1 BUS 18 PEC Transfers after JMPR instruction Problems may occur when a PEC transfer immediately follows a taken JMPR instruction when the following sequence of 4 conditions is met labels refer to following examples 1 in an instruction sequence which represents a loop a jump instruction Label_B which is capable of loading the jump cache JMPR JMPA JB JNB JBC JNBS is taken 2 the target of this jump instruction directly is a JMPR instruction Label_C which is also taken and whose target is at address A Label_A 3 aPEC transfer occurs immediately after this JMPR instruction Label_C 4 inthe following program flow the JMPR instruction Label_C is taken a second time and no other JMPR JMPA JB JNB JBC JNBS or instruction which has branched to a different code segment JMPS CALLS or interrupt has been processed in the meantime i e the condition for a jump cache hit for the JMPR instruction Label_C is true In this case when the JMPR instruction Label_C is taken for the second time as described in condition 4 above and the 2 words stored in the jump cache word address A and A 2 have been processed the word at address A 2 is erroneously fetched and executed instead of the word at address A 4 Note the problem does not occur when the jump instruction Label_C is a JMPA instruction the program sequence is executed from internal ROM Flash Example1 Label_A instructio
16. Transmission CAN 9 Contents of Message Objects and Mask of Last Message Registers after Reset CPU 21 BFLDL H Instructions after Write Operation to internal IRAM CPU 22 Z Flag after PUSH and PCALL c B g B Arithmetic Overflow by DIVLU instruction EES FA c ES FA B i BE EES BE B E B E X10 POH I O conflict during XPER access and external 8 bit Non multiplexed bus X12 POH spikes after XPER write access and external 8 bit Non multiplexed bus EES FA Step BE until step DB only PINS 1 OUTPUT Signal Rise Time DA step only EES FA AC DC Short Description Fixed in Deviation step DC IALEL 1 ALE inactive current 30 A steps gt FA only o AC PLLA PLL base frequency max 6 MHz GA GA T JA HA steps ony AC PLL2 PLL base frequency 8 MHz GA GA T JA steps with date code gt 0114 DCto8 5 CLKOUT risetime steps2GAony S CLKOUT fall time steps gt GA only a Input Hysteresis Special Threshold step HA only Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 18 of 29 ADCC 23 EESJF ALE high time TCL 15ns DA step only AC t15 1 RD to valid data in 3TCL 25ns step BE only AC t16 1 ALE low to valid data in 3TCL 25ns step BE only F AC t34 1 CLKOUT rising edge to ALE falling edge 12ns step BE only AC t38 2 ALE falling edge to CS 10ns step BE only ALE falling edge to CS 7ns DA step only E RDCS WRCS low time wit
17. about potentially critical instruction sequences This tool is included in AP1628 Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 5 of 29 Scanning for Problem CPU 21 which can be found via the link to 16 bit Microcontroller Application Notes on http www infineon com c166 family Direct links to description and software http www infineon com cmc_upload 0 000 018 484 ap162804 ScanningCPU 21 pdf http Awww infineon com cgi ecrm dll ecrm scripts public_download jsp o0id 18468 amp parent_oid 53087 CPU 22 Z Flag after PUSH and PCALL The Z flag in the PSW is erroneously set to 1 by PUSH reg or PCALL reg rel instructions when all of the following conditions are true a for PUSH reg instructions the contents of the high byte of the GPR or E SFR which is pushed is 00h and the contents of the low byte of the GPR or E SFR which is pushed is gt 00h and the contents of GPR Rx is odd where x 4 msbs of the 8 bit reg address of the pushed GPR or E SFR Examples PUSH R1 coding F1 EC incorrect setting of Z flag if contents of R15 is odd and OOFFh contents of R1 0001h PUSH DPP3 coding 03 EC incorrect setting of Z flag if contents of RO is odd and OOFFh gt contents of DPP3 0001h b for PCALL reg rel instructions when the contents of the high byte of the GPR or E SFR which is pushed is 00h and when the contents of the low byte of the GPR or E SFR w
18. ace Pins PORTO 1 port 4 port 6 RD WR ALE WRH BHE CLKOUT while bit PDCR 4 NBPEC controls Non Bus Pins port 2 port 3 port 7 port 8 RSTOUT RSTIN in bidirectional mode The reset value 0 selects fast edge mode to ensure compatibility with previous versions and steps Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 25 of 29 Port 5 Digital Input Control via register PSDIDIS Beginning with the FA step the digital input stages on port 5 may be disconnected from pins used as analog inputs via register P5DIDIS A D Converter Due to correction of the former problem ADC 7 injected conversions will no longer be aborted by the start of a standard conversion The following table summarizes the ADC behaviour in this situation for all possible combinations of conversion requests Note that a conversion request as discussed in this context is activated when the respective control bit ADST or ADCRQ is toggled from 0 to 1 i e the bit must have been zero before being set Conversion New requested conversion in progress Standard Injected Standard Abort running conversion and start Complete running conversion requested new conversion start requested conversion after that Injected Complete running conversion Complete running conversion start requested conversion after that start requested conversion after that Bit ADCRQ will be 0 for the second conversion
19. ation of a watchdog timer reset in bit WDTR in register WDTCON indication of other reset sources and types software reset long short hardware reset etc in status flags in the low byte of register WDTCON is provided While in previous steps only reset values 0000h or 0002h could occur for WDTCON beginning with the FA steps further values may occur in the low byte of WDTCON Therefore programs written for previous steps which evaluate the contents of WOTCON after reset and which explicitly test bit WDTR either via bit instructions or via mask operations will work identically on the FA and following steps However programs which assume that all other bits in the low byte of WDTCON except bit WDTR are always 0 which is true for previous steps and therefore e g test WDTCON with byte or word operations may work differently on the FA and following steps The following table summarizes the behaviour of the reset source indication flags LHWR SHWR SWR WDTR WDTCON 4 WDTCON 3 WDTCON 2 WOTCON 1 Long HW Reset Short HW Reset SRST instruction WDT Reset EINIT instruction SRVWDT instruction Legend 1 flag is set 0 flag is cleared flag is not affected flag is set when bi directional reset option is enabled Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 24 of 29 XBUS Peripheral Enable Bit XPEN SYSCON 2 does not apply to C167SR Bit SYSCON 2 has been modified into a general XBUS Pe
20. ct to the size of the components for an external crystal oscillator circuit In any case it is recommended to check the safety factor of the oscillator circuit in the target system See Application Note AP2420 Crystal Oscillator of the C500 and C166 Microcontroller Families which can be found via the link to 16 bit Microcontroller Application Notes on http www infineon com c166 family Direct link http www infineon com cmc_upload documents 009 746 ap242005 pdf External Bus Controller By default the CS signals when used as address CS signals are switched nominally 1 TCL after the address for an external bus access is driven This ensures a defined transition from active to inactive state without glitches Optionally controlled by bit CSCFG SYSCON 6 1 the leading edge of the CS signals may be generated in an unlatched mode i e the CS signals are directly derived from the addresses and are switched in the same internal clock phase as the addresses This allows more time for the chip enable access time tce of external devices however glitches may occur on CS lines while the addresses are changing Port Driver Control Register Beginning with the FA step the driving capability of the pad drivers can be selected via software in register PDCR ESFR address OFOAAh Two driving levels fast edge mode reduced edge mode can be selected for two groups of pins Bit PDCR 0 BIPEC controls the edge characteristic of Bus Interf
21. eet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 16 of 29 pin V Can cause an additional unadjusted error AUE to all other analog channels In case Rre lt 490 Ohm Rire lt LSB 2 I ovf 3 the maximum possible additional error AREF AREF OVmax to all other channels is smaller than 0 5 LSB with the condition of 5 mA at ANn OVmax Relation between liker and loy at ANn larer OVE 3 I ne 1 11 AREF AREF Note The influence to the reference voltage V rer caused by loy shift of V Vann Varer and the influence is minimum for Vann 490 Ohm and 0 5 LSB is calculated for the worst case at V arer IS Maximum for OV ne 1 11 The condition R ee lt AREF V AINn AREF 2 Values of ovi 3 Symbol Max Overload factor 3 0001 o Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 17 of 29 History List C167CR LM since device step BA Functional Short Description Fixed in Problem step ADC 11 Modifications of ADM field while bit ADST 0 a SSC 9 Data Transmission in Slave Mode steps gt FA only a Spikes on CS lines after access with RDCS and or WRCS not in BE and O earlier steps BUS 18__ PECtansfersatter MPR BUS 19__ Unlatched Chip Selects at Entry into Hold Mode not in BE and earlier steps PWRDN 1__ Execution of PWRDN Instruction while pin NMI high Read Access to XPERs in Visible Mode CAN 7 Unexpected Remote Frame
22. ement operations of the PEC source or destination pointers the problem can only occur if the value of mask8 of BFLDL or data8 of BFLDH OFyh y 0 Fh and the range which is covered by the context pointer CP partially or completely overlaps the PEC source and destination pointer area OFCEOh OFCFEh and the address of the source or destination pointer which is auto incremented after the PEC transfer is equal to the address of GPR Ry included in case 3a For system stack write operations the problem can only occur if the system stack is located in the bit addressable portion of IRAM OFDOOh OFDFFh or if the system stack can overlap the register bank area i e the register bank area is located below the system stack and the distance between the contents of the context pointer CP and the stack pointer SP is lt 20h Workaround 1 When a critical instruction combination or PEC transfer to IRAM can occur then substitute the BFLDx instruction by a an equivalent sequence of single bit instructions This sequence may be included in an uninteruptable ATOMIC or EXTEND sequence to ensure completion after a defined time b an equivalent byte or word MOV or logical instruction Note that byte operations to SFRs always clear the non addressed complementary byte Note that protected bits in SFRs are overwritten by MOV or logical instructions Workaround 2 When a critical instruction combination occurs and PEC write operations t
23. h RW delay 2TCL 12ns DA step only EE RDCS WRCS low time no RW delay 3TCL 12ns DA step only EES DA ADCC 2 2 ADC Overload Current DA and DB step only EES FA E E E E E E E E E E S S S S S S S S S EES EES S F FA History List C167SR LM since device step BA Functional Short Description Fixed in Problem step ADC 11 Modifications of ADM field while bit ADST 0 i SSC 9 Data Transmission in Slave Mode steps gt FA only BUS 17 Spikes on CS lines after access with RDCS and or WRCS not in BA and earlier steps a a sus 18 PEC transfers afterMPR ooo d Bus 19 Unlaiched Chip Selects at Entry into Hold Mode not in BA and earlier steps BFLDL H Instructions after Write Operation to internal IRAM Z Flag after PUSH and PCALL fon a owp 1 Function of Bit OWDDISISYSCON 4 notin BA and earlier steps PWRDN 1_ Execution of PWRDN instruction while pin nMi hioh Jo X9 Read Access to XPERs in Visible Mode ko Jump instruction in EXTEND sequence bao CPU 9 PEC Transfers during instruction execution from Internal RAM Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 19 of 29 CPU 11 Stack Underflow during Restart of Interrupted Multiply CPU 17 Arithmetic Overflow by DIVLU instruction ES FA RST 1 System Configuration via POL O during Software Watchdog Timer Reset POH I O conflict during X
24. he PLL stays in the PLL base frequency The CPU clock source is only switched back to the XTAL1 oscillator clock after a hardware reset This can be achieved via a normal hardware reset or via a software reset with enabled bidirectional reset It is important that the hardware reset is at least active for 1 ms after that time the PLL is locked in any case Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 14 of 29 Note on Early Unlatched Chip Select Option As described in the User s Manuals e g C167CR User s Manual V3 1 2000 03 p 9 11 an early unlatched address chip select signal SYSCON CSCFG 1 becomes active together with the address and BHE if enabled and remains active until the end of the current bus cycle Early address chip select signals are not latched internally and may toggle intermediately while the address is changing These effects may also occur on CSx lines which are configured as RDCSx and or WRCSx signals BUSCONx CSRENx 1 and or CSWENx 1 The position of these transitions spikes is at the beginning of an external bus cycle or an internal XBUS cycle indicated by the rising edge of signal ALE The width of these transitions is 5 ns measured at a reference level of 2 0 V with Vdd 5 0 V The falling edge of the spike occurs in the same relation to RD WR WRH WRL and to other CS signals as if it was an address chip select signal with early chip select op
25. hich is pushed is odd This may lead to wrong results of instructions following PUSH or PCALL if those instructions explicitly e g BMOV Z JB Z or implicitly e g JMP cc_Z JMP cc_NET evaluate the status of the Z flag before it is newly updated Note that some instructions e g CALL have no effect on the status flags such that the status of the Z flag remains incorrect after a PUSH PCALL instruction until an instruction that correctly updates the Z flag is executed Example PUSH R1 incorrect setting of Z flag if R15 is odd CALL proc_xyz Z flag remains unchanged is a parameter for proc_xyz proc_xyz JMP cc_Z end_xyz Z flag evaluated with incorrect setting end_xyz Effect on Tools The Hightec C166 tools all versions don t use the combination of PUSH PCALL and the evaluation of the Z flag Therefore these tools are not affected The code generated by the Keil C166 Compiler evaluates the Z flag only after MOV CMP arithmetic or logical instructions It is never evaluated after a PUSH instruction PCALL instructions are not generated by the C166 Compiler Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 6 of 29 This has been checked with all C166 V3 xx and V4 xx compiler versions Even the upcoming V5 xx is not affected by the CPU 22 problem The assembler portions of the C166 V3 xx and V4 xx Run Time Libraries the RTX166 Full and TX166 Tiny Rea
26. higher or V3 120 or insert nop in nested loops e g as follows void test int i int k while k nop while i In the TASKING C166 Software Development Tools the code sequence related to problem BUS 18 can be generated in Assembly The problem can also be reproduced in C language by using a particular sequence of GOTOs With V6 0r3 TASKING tested all the Libraries C startup code and the extensive set of internal test suite sources and the BUS 18 related code sequence appeared to be NOT GENERATED To prevent introduction of this erroneous code sequence the TASKING Assembler V6 0r3 has been extended with the CHECKBUS18 control which generates a WARNING in the case the described code sequence appears When called from within EDE the Assembler control CHECKBUS18 is automatically activated BUS 19 Unlatched Chip Selects at Entry into Hold Mode Unlike in standard latched configuration the chip select lines in unlatched configuration SYSCON CSCFG 1 are not driven high for 1 TCL after HLDA is driven low but start to float when HLDA is driven low OWD 1 Function of Bit OWDDIS SYSCON 4 The status of bit OWDDIS SSYCON 4 has no effect on the oscillator watchdog i e the oscillator watchdog can not be disabled or enabled by bit OWDDIS The oscillator watchdog can only be disabled by a low level on pin OWE 84 An internal pull up holds this pin high in case it is left unconnected thus enabling the oscillato
27. in this auto scan sequence Note When a conversion is already in progress and then the configuration in register ADCON is changed the new conversion mode in ADM is evaluated after the current conversion the new channel number in ADCH and new status of bit ADST are evaluated after the current conversion when a conversion in fixed channel conversion mode is in progress and after the current conversion sequence i e after conversion of channel 0 when a conversion in an auto scan mode is in progress In this case it is a specified operational behaviour that channels n 1 0 are converted when ADM is changed to an auto scan mode while a fixed channel conversion of channel n is in progress see e g C167CR User s Manual V3 1 p 17 5 Workaround When an auto scan conversion is to be performed always start the A D converter with the same instruction which sets the configuration in register ADCON Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 2 of 29 SSC 9 Data Transmission in Slave Mode During data reception in slave mode of the SSC module sporadically the shift clock supplied by the external master on pin SCLK may not be properly recognized due to a synchronization problem when all of the following conditions are true 1 the latching edge for the serial data is the falling edge of SCLK i e both bit SSCPO 1 and bit SSCPH 1 or SSCPO 0 and SSCPH 0 in register SSCCON and
28. ing JMPR JMPA JB JNB JBC JNBS instruction or 3 change the loop structure such that instead of jumping from Label_B to Label_C and then to Label_A the jump from Label_B directly goes to Label_A Notes on compilers as reported by compiler manufacturers In the Hightec compiler beginning with version Gcc 2 7 2 1 for SAB C16x V3 1 Rel 1 1 patchlevel 5 a switch m bus18 is implemented as workaround for this problem In addition optimization has to be set at least to level 1 with u1 The Keil C compiler versions 2 V4 02 in combination with directive FIXPEC when OPTIMIZE 7 is selected and version 3 120 including the associated run time libraries do not generate or use instruction sequences where a JMPR instruction can be the target of another jump instruction i e the conditions for this problem do not occur With other versions the problem may occur e g in nested for while loops when the inner loop looks as follows Example i while while variable constant lt last statement is a modification of variable value gt ie Example ii for for variable lt 100 variable The critical JMPR JMPR sequence does not occur when a for loop is used with constant initialization e g while for variable 0 variable lt 100 variable Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 11 of 29 Recommendation use V4 03 or
29. ized here for easier reference Incremental position sensor interface For each of the timers T2 T3 T4 of the GPT1 unit an additional operating mode has been implemented which allows to interface to incremental position sensors A B Top0 This mode is selected for a timer Tx via TxM 110b in register TxCON x 2 3 4 Optionally the contents of T5 may be captured into register CAPREL upon an event on T3 This feature is selected via bit CT3 1 in register TSCON 10 Oscillator Watchdog The Oscillator Watchdog OWD monitors the clock at XTAL1 in direct drive and prescaler mode In case of clock failure the PLL Unlock OWD Interrupt Request Flag XP3IR is set and the internal CPU clock is supplied with the PLL basic frequency This feature can be disabled by a low level on pin Vpp OWE Bit OWDDIS SYSCON 4 allows to disable this feature via software on device steps where problem OWD 1 is fixed Bidirectional Reset Optionally an internal watchdog timer or software reset will be indicated on the RSTIN pin which will be driven low for the duration of the internal reset sequence RSTIN will also be driven low for the duration of the internal reset sequence when this reset was initiated by an external HW reset signal on pin RSTIN This option is selectable by software via bit BDRSTEN SYSCON 3 After reset the bidirectional reset option is disabled BDRSTEN SYSCON 3 0 Reset Source Indication in Register WOTCON Besides indic
30. l Time Operating system do also not contain any evaluation of the Z flag after PUSH or PCALL The TASKING compiler V7 5r2 never generates a PCALL instruction nor is it used in the libraries The PUSH instruction is only used in the entry of an interrupt frame and sometimes on exit of normal functions The zero flag is not a parameter or return value so this does not give any problems Previous versions of TASKING tools V3 x and higher are not affected versions before 3 x are most likely not affected Contact TASKING when using versions before V3 x Since code generated by the C166 compiler versions mentioned before is not affected analysis and workarounds are only required for program parts written in assembler or instruction sequences inserted via inline assembly Workaround for program parts written in assembler Do not evaluate the status of the Z flag generated by a PUSH or PCALL instruction Instead insert an instruction that correctly updates the PSW flags e g PUSH reg CMP reg 0 updates PSW flags note CMP additionally modifies the C and V flags while PUSH or MOV leaves them unaffected JMPR cc_Z label_1 implicitly tests Z flag or PCALL reg procedure_1l procedure_1 MOV ONES reg updates PSW flags JMPR cc_NET label_1 implicitly tests flags Z and E Hints for Detection of Critical Instruction Combinations Whether or not an instruction following PUSH reg or PCALL reg rel actually causes a problem
31. n x Begin of Loop instruction x 1 Label_B JMP Label_C JMP may be any of the following jump instructions JMPR cc_zz JMPA cc_zz JB JNB JBC JNBS jump must be taken in loop iteration n jump must not be taken in loop iteration n 1 Label_C JMPR cc_xx Label _A End of Loop instruction must be JMPR single word instruction jump must be taken in loop iteration n and n 1 PEC transfer must occur in loop iteration n Example2 Label_A instruction x Begin of Loop1 instruction x 1 Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 10 of 29 Label_C JMPR cc_xx Label_A End of Loop1 Begin of Loop2 instruction must be JMPR single word instruction jump not taken in loop iteration n 1 i e Loop2 is entered jump must be taken in loop iteration n and n 1 PEC transfer must occur in loop iteration n Label_B JMP Label_C End of Loop2 JMP may be any of the following jump instructions JMPR cc_zz JMPA cc_zz JB JNB JBC JNBS jump taken in loop iteration n 1 A code sequence with the basic structure of Example was generated e g by a compiler for comparison of double words long variables Workarounds 1 use aJMPA instruction instead of a JMPR instruction when this instruction can be the direct target of a preceding JMPR JMPA JB JNB JBC JNBS instruction or 2 insert another instruction e g NOP as branch target when a JMPR instruction would be the direct target of a preced
32. nd the data of the corresponding message object is prevented Then the pre charge values of the internal hidden buffer are transmitted instead this causes a remote frame transmission with identifier 0 11 bit and data length code 0 This behavior occurs only when the transmit request of message object n is pending and the transmit requests of other message objects are not active single transmit request If this remote frame loses arbitration to a data frame with identifier 0 or if it is disturbed by an error frame it is not retransmitted Effects to other CAN nodes in the network The effect leads to delays of other pending messages in the CAN network due to the high priority of the Remote Frame Furthermore the unexpected remote frame can trigger other data frames depending on the CAN node s configuration Workarounds 1 The behavior can be avoided if a message object is not updated by software when a transmission of the corresponding message object is pending TXRQ element is set and the CAN module is active INIT 0 If a re transmission of a message e g after lost arbitration or after the occurrence of an error frame needs to be cancelled the TXRQ element should be cleared by software as soon as NEWDAT is reset from the CAN module 2 The nodes in the CAN system ignore the remote frame with the identifier 0 and no data frame is triggered by this remote frame CAN 9 Contents of Message Objects and Mask of Last Message
33. nditions are true at the same time 1 the previous instruction is a PEC transfer which writes to IRAM or any instruction with result write back to IRAM addresses OF200h 0FDFFh for 3 Kbyte module OF600h 0FDFFh for 2 Kbyte module or OFAOOh OFDFFh for 1 Kbyte module For further restrictions on the destination address see case a or case b below 2 the BFLDx instruction immediately follows the previous instruction or PEC transfer within the instruction pipeline back to back execution i e decode phase of BFLDx and execute phase of the previous instruction or PEC transfer coincide This situation typically occurs during program execution from internal program memory ROM OTP Flash or when the instruction queue is full during program execution from external memory 3 the 3 byte of BFLDx mask 8 field of BFLDL or data8 field of BFLDH and the destination address of the previous instruction or PEC transfer match in the following way a value of mask8 of BFLDL or data8 of BFLDH OF yh y 0 Fh and the previous instruction or PEC writes to the low and or high byte of GPR Ry or the memory address of Ry determined by the context pointer CP via any addressing mode b value of mask8 of BFLDL or data8 of BFLDH 00h 0EFh and the lower byte v of the contents v of the IRAM location or E SFR or GPR which is read by BFLDx is 00h lt v lt 7Fh and the previous instruction or PEC transfer writes to the low
34. o IRAM locations which match the above criteria bit addressable or active register bank area can be excluded then rearrange the BFLDx instruction within the instruction environment such that a non critical instruction sequence is generated Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 4 of 29 Workaround 3 When a critical instruction combination or PEC transfer to IRAM can occur then replace the BFLDx instruction by the instruction sequence ATOMIC 1 BFLDx This means e g when BFLDx was a branch target before ATOMIC 1 is now the new branch target In case the BFLDx instruction is included at position nin an ATOMIC or EXTEND sequence with range operator m n m 2 4 n lt m then insert repeat the corresponding ATOMIC or EXTEND instruction at position n with range operator z where z m n 1 Po Range of original ATOMIC EXTEND statement Position of BFLDx 1 2 3 4 within ATOMIC EXT sequence 2 workaround workaround workaround workaround E ae eee 2 ee ee ee a e eee eee T case can not occur Tool Support for Problem CPU 21 The Keil C166 Compiler V3 xx generates BFLD instructions only in the following cases when using the _bfld_ intrinsic function at the beginning of interrupt service routines when using pragma disable at the end of interrupt service routines when using the chip bypass directive FIX166 The C166 Compiler V4 xx uses the BFLD instructi
35. on for Capture Function if CT3 1 and Cl 01b or 10b In contrast to the current documentation in the User s Manuals the edge selection for the capture function of the contents of T5 into register CAPREL triggered by transitions on pins T3IN or T3EUD works as described below This applies to configurations where bit CT3 1 and bit field Cl 01b or Cl 10b Other functions are not affected Changes to the current documentation are marked in bold italic letters see description of register T5CON in chapter GPT2 Auxiliary Timer T5 of the User s Manual Bit Bit Field Function CT3 Timer 3 Capture Trigger Enable 0 Capture trigger from pin CAPIN 1 Capture trigger from T3 input pins Cl Register CAPREL Capiure Trigger Selection depending on bit CT3 0 0 Capture disabled 0 1 Positive transition rising edge on CAPIN or positive transition rising edge on T3IN if TZ3EUD 0 negative transition falling edge on T3IN if T3EUD 1 positive transition rising edge on T3EUD if T3IN 0 negative transition falling edge on T3EUD if T3IN 1 1 0 Negative transition falling edge on CAPIN or negative transition falling edge on T3IN if TZ3EUD 0 positive transition rising edge on T3IN if T3EUD 1 negative transition falling edge on T3EUD if T3IN 0 positive transition rising edge on T3EUD if T3IN 1 1 1 Any transition rising or falling edge on CAPIN or any transition on T3IN or T3EUD The foll
36. on to optimize bit field struct accesses Release C166 V4 10 offers a new directive called FIXBFLD that inserts an ATOMIC 1 instruction before every BFLD instruction that is not enclosed in an EXTR sequence Detailed information can be found in the C166 HLP RELEASE TXT of C166 Version 4 10 The C166 Run Time Library for C166 V3 xx and V4 xx uses BFLD instructions only in the START167 A66 file This part of the code should be not affected by the CPU 21 problem but should be checked by the software designer The RTX166 Full Real Time Operating system any version does not use BFLD instructions For RTX166 Tiny you should rebuild the RTX166 Tiny library with the SET FIXBFLD 1 directive This directive is enabled in the assembler source file RTX166T A66 After change of this setting rebuild the RTX166 Tiny library that you are using in your application The Tasking support organization provides a v7 0r1 A166 Assembler build 177 including a check for problem CPU 21 with optional pec no_pec feature This assembler version can also be used to check code which was generated with previous versions of the Tasking tool chain A v7 0r1 C166 Compiler build 368 offering a workaround for problem CPU 21 is also available from Tasking The scan tool aiScan21 analyzes files in hex format plus user supplied additional information locator map file configuration file checks whether they may be affected by problem CPU 21 and produces diagnostic information
37. only ALE active current 1000UA DC IRWL 1 RD WR active current 600uA DC IP6L 1 Port 6 active current 600 uA DC IPOL 1 Port 0 configuration current 110uA problem not in AC step Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 21 of 29 DC HYS 1__ Input Hysteresis 300mV restriction not effective in production test AC t5 1 ALE high time TCL 15ns AC t12 1 WR WRH low time with RW delay 2TCL 12ns EES FA AC t13 1 WR WRH low time no RW delay 3TCL 12ns AC 148 1 RDCS WRCS low time with RW delay 2TCL 12ns EES F AC t49 1 RDCS WRCS low time no RW delay 3TCL 12ns AC 138 1 ALE falling edge to CS 7ns ADCC 2 2 _ ADC Overload Current History List C167CR 16RM since device step AA Functional Short Description Fixed in Problem step ADC 10 Start of Standard Conversion at End of Injected Conversion EES FA ADC 11 Modifications of ADM field while bit ADST 0 a SSC 9 Data Transmission in Slave Mode steps gt FA only I BUS 17 Spikes on CS lines after access with RDCS and or WRCS stepes gt FA only BUS 18 PEC transfers after JMPR BUS 19 Unlatched Chip Selects at Entry into Hold Mode not in step AA Function of Bit OWDDIS SYSCON 4 not in step AA Function of Bt OWDDISISYSCON notinstep AA EESFA Access to internal ROM with EXTS EXTSR instructions EES FA Arithmetic Overflow by DIVLU instruction CPU 21 BFLDLIH instructions after Wri
38. ormation whether intra segment target address 0000h or not TRAP both trap target and linear successor must be analyzed since Z flag may be incorrect in PSW on stack as well as in PSW at entry of trap routine For bit modification instructions the problem may only occur if a source bit is the Z flag and or the destination bit is in the PSW but not the Z flag These instructions are Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 8 of 29 BMOV BMOVN BAND BOR BXOR BCMP BFLDH BFLDL problem only if bit 3 of mask 0 i e if Z is not selected BCLR BSET problem only if operand is not Z flag JBC JNBS wrong branch if operand is Z flag PWRDN 1 Execution of PWRDN Instruction while pin NMI high When instruction PWRDN is executed while pin NMI is at a high level power down mode should not be entered and the PWRDN instruction should be ignored However under the conditions described below the PWRDN instruction may not be ignored and no further instructions are fetched from external memory i e the CPU is in a quasi idle state This problem will only occur in the following situations a the instructions following the PWRDN instruction are located in external memory and a multiplexed bus configuration with memory tristate waitstate bit MTTCx 0 is used or b the instruction preceding the PWRDN instruction writes to external memory or an XPeripheral XRAM CAN and the in
39. owing table shows for CT3 1 under which conditions a capture trigger is generated for a transition on T3IN or T3EUD depending on the level on the respective other input T3EUD or T3IN Level on respective T3IN Input T3EUD Input other input Rising Falling Rising Falling T3EUD or T3IN High capture if CI 10 capture if Cl 01 capture if Cl 10 capture if Cl 01 Low capture if Cl 01 capture if Cl 10 capture if Cl 01 capture if Cl 10 In other words a capture trigger is generated for Cl 01 whenever the two inputs change from the same to a different logic state A capture trigger is generated for Cl 10 whenever the two inputs change from a different to the same logic state As an equivalent representation a capture trigger is generated when the following logic equation is true Cl Capture if 01 T3IN XOR T3EUD 0 1 10 T3IN XOR T3EUD 1 0 Applications that require a capture event associated with an interrupt request from register CAPREL only for transitions on pin T3IN independent of the status of pin T3EUD or only for transitions on pin T3EUD independent of the status of pin T3IN respectively may use the following configuration Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 28 of 29 externally connect pin T3IN to pin CAPIN or pin T3EUD to pin CAPIN respectively enable the capture trigger from pin CAPIN
40. pt in the FA and newer steps the second interrupt request SSCTB empty is always systematically generated before the first one PEC COUNT 0 has been acknowledged by the CPU such that effectively only one interrupt request is generated for two different events before step FA when the PEC transfer is performed with sufficient margin to the next clock tick from the SSC baud rate generator and no higher priority interrupt request has occurred in the meantime the PEC COUNT 0 interrupt will be acknowledged before the SSCTB empty interrupt request is generated i e two interrupts will occur based on these events However when the PEC transfer takes place relatively close before the next clock tick from the SSC baud rate generator or a higher priority interrupt request has occurred while the PEC transfer is performed the PEC COUNT 0 interrupt may not be acknowledged before the SSCTB empty interrupt request is generated such that effectively only one interrupt request will be generated for two different events In order to achieve a defined and systematic behavior with all device steps the SSC receive interrupt which is generated at the end of a character transmission may be used instead of the SSC transmit interrupt Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 27 of 29 Documentation Updates to C167CR User s Manual V3 2 2003 05 p 10 30 ff T5CON D1 Edge Selecti
41. r watchdog in direct drive or prescaler mode X9 Read Access to XPERs in Visible Mode The data of a read access to an XBUS Peripheral XRAM CAN in Visible Mode is not driven to the external bus PORTO is tristated during such read accesses Note that in Visible Mode PORT1 will drive the address for an access to an XBUS Peripheral even when only a multiplexed external bus is enabled CAN 7 Unexpected remote frame transmission The on chip CAN module may send an unexpected remote frame with the identifier 0 when a pending transmit request of a message object is disabled by software Detailed Description There are three possibilities to disable a pending transmit request of a message object n 1 14 e Set CPUUPDn element e Reset TXRQn element e Reset MSGVALn element Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 12 of 29 Either of these actions will prevent further transmissions of message object n The symptom described above occurs when the CPU accesses CPUUPD TXRQ or MSGVAL while the pending transmit request of the corresponding message object is transferred to the CAN state machine just before start of frame transmission At this particular time the transmit request is transferred to the CAN state machine before the CPU prevents transmission In this case the transmit request is still accepted from the CAN state machine However the transfer of the identifier the data length code a
42. ripheral Enable bit i e it controls both the XRAM and the CAN module When bit SYSCON 2 0 default after reset and an access to an address in the range EFOOh EFFFh is made either an external bus access is performed if an external bus is enabled or the Illegal Bus Trap is entered In previous versions the CAN module was accessed in this case Systems where bit SYSCON 2 was set to 1 before an access to the CAN module in the address range EFOOh EFFFh was made will work without problems with all steps of the C167CR Clock System e In total 8 different clock configuration options are selectable during reset on POH 7 5 direct drive prescaler 0 5 PLL factors 2 3 4 5 1 5 2 5 Some options are configured via settings on POH 7 5 during reset which would have selected Direct Drive in previous steps for details see Appendix in Errata Sheet V1 x of respective device Reset Configuration CPU Frequency Notes POH 7 5 fcpu fxtal F 011 fxtal 1 Direct Drive 010 fxtal 1 5 1 001 fxtal 2 Prescaler Operation 1 000 fxtal 2 5 1 1 Note previous steps have selected Direct Drive when POH 7 5 OXX i e the level on POH 6 and POH 5 during reset was not evaluated e In addition in each of the steps FA GA GA T HA the internal oscillator circuit Type_RE has been improved and adjusted to the respective technology The Type_RE oscillator is compatible to the Type_R oscillator with respe
43. ritten and flag SSCBSY 1 is up to 1 2 bit time SSCBSY is cleared 1 2 bit time after the last latching edge When polling flag SSCBSY after SSCTB has been written SSCBSY may not yet be set to 1 when it is tested for the first time in particular at lower baud rates Therefore e g the following alternative methods are recommended 1 test flag SSCRIR receive interrupt request instead of SSCBSY in case the receive interrupt request is not serviced by CPU interrupt or PEC e g loop BCLR SSCRIR clear receive interrupt request flag MOV SSCTB xyz send character wait_tx_complete JNB SSCRIR wait_tx_complete test SSCRIR JB SSCBSY wait_tx_complete test SSCBSY to achieve original timing SSCRIR may be set 1 2 bit time before SSCBSY is cleared 2 use a software semaphore bit which is set when SSCTB is written and is cleared in the SSC receive interrupt routine Oscillator Watchdog and Prescaler Mode The OWD replaces the missing oscillator clock signal with the PLL clock base frequency In direct drive mode the PLL base frequency is used directly fcpu 2 5 MHz In prescaler mode the PLL base frequency is divided by 2 fcpu 1 2 5 MHz PLL lock after temporary clock failure When the PLL is locked and the input clock at XTAL1 is interrupted then the PLL becomes unlocked provides the base frequency 2 5 MHz and the PLL unlock interrupt request flag is set If the XTAL1 input clock starts oscillation again then t
44. structions following the PWRDN instruction are located in external memory In this case the problem will occur for any bus configuration Note the on chip peripherals are still working correctly in particular the Watchdog Timer will reset the device upon an overflow Interrupts and PEC transfers however can not be processed In case NMI is asserted low while the device is in this quasi idle state power down mode is entered Workaround Ensure that no instruction which writes to external memory or an XPeripheral precedes the PWRDN instruction otherwise insert e g a NOP instruction in front of PWRDN When a multiplexed bus with memory tristate waitstate is used the PWRDN instruction should be executed out of internal RAM or XRAM BUS 17 Spikes on CS Lines after access with RDCS and or WRCS Spikes of about 5 ns width measured at V 0 9 Vcc from Vcc down to Vss worst case typically about 0 8 Vcc 4 0 V Vcc 5 0V may occur on Port 6 lines configured as CS signals in default configuration as latched chip selects SYSCON 6 CSCFG 0 The spikes occur on one CSx line at a time for the first external bus access which is performed via a specific BUSCONx ADDRSELx register pair x 1 4 or via BUSCONO x 0 when the following two conditions are met 1 the previous bus cycle was performed in a non multiplexed bus mode without tristate waitstate via a different BUSCONy ADDRSELy register pair y 1 4 y x or BUSCONO y 0 y x
45. te Operation to internal RAM PWRON 1 Execution of PWRDN Instruction while pin NMI high SSC 8 Data Transmission in Slave Mode Step EES FA only ES FA CAN 7 Unexpected Remote Frame Transmission ed CAN 9 Contents of Message Objects and Mask of Last Message Registers after Reset Read Access to XPERs in Visible Mode POH spikes after XPER write access and external 8 bit Non multiplexed bus EES FA Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 22 of 29 AC DC Short Description Fixed in Deviation step ALE inactive current 30 A steps gt FA only AC PLL1 PLL base frequency GA GA T JA HA stepsony J PLL base frequency 8 MHz GA GA T JA steps with date code gt 0114 CLKOUT rise time steps GA only CLKOUT fall time steps gt GA only Input Hysteresis Special Threshold step HA only RD to valid data in 3TCL 25ns ALE low to valid data in 3TCL 25ns EES FA Aci98 2 _ ALETalingedgetoCS tong lera ADCC 2 3 ADC Overload Current steps gt FA only Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 23 of 29 Functional Improvements Documentation Updates Compared to the BA step the following feature enhancements have been implemented in the FA and GA and all following steps of the C167CR SR They are described in detail in the respective chapters of the C167CR Derivatives User s Manual V3 2 2000 05 and are summar
46. tion When CS lines configured as RDCS and or WRCS are used e g as output enable OE signals for external devices or as clock input for shift registers problems might occur temporary bus contention during data float times may be solved by tristate wait state unexpected shift operations etc When CS lines configured as WRCS are used as write enable WE signals for external devices or FIFOs internal locations may be overwritten with undefined data When CS lines are used as chip enable CE signals for external memories usually no problems are expected since the falling edge of the spikes has the same characteristics as the falling edge of an access with a regular early unlatched address CS signal At this time the memory control signals RD WR WRH WRL4 are on their inactive high levels Microcontroller Division Errata Sheet C167CR SR LM 4RM 16RM ES HA HA 1 1 Mh 15 of 29 Deviations from Electrical and Timing Specification The following table lists the deviations of the DC AC characteristics from the specification in the C167CR SR Data Sheet V3 3 2005 02 Problem Parameter Symbol Limit Values Values Unit Test short name nin Tmax __loonton DC IALEL 1 ALE inactive current lve Ee DC tc8 5 CLKOUT rise time ee of 4 DC tc9 5 CLKOUT fall time Toes of 4 DC HYS 350 Input Hysteresis HYS Special Threshold AC PLL 1 PLL base frequency bi see User s i Manual chapter ig Clock Generation
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