UG-200 - Analog Devices
Contents
1. Now d a 5Ta la q aede oats J TA TUNS ECTS T suHosp amp 8 ssi 2 8 ano ENI F aana TT 7 Ae Nz z T amp ashasi E 2223 nal T ENITuUMd EOE 28 8 T Z2 t092 TTY ONS s 9 9 q a quale et ts asa wa ETESTS SWHOSP 5 3 SE T 3 gno anih gne nedE qt NITE BA B asnas gt 9023 Nal zi ENI HMd cWZIT 23 E ZUY Tday andu hd a gt Q AI i Mii 5 SUHOSp S u lava fe UNSU 7 dvd TONS Tauag ind z T Us oo Ea geno NIE sit 513 n vai ino NI E 8 n UNS E E WA Ipa gTa SUHOSP asasi p Um nz e T E 6 er s 7 7 aaau acae za 23 20348021d045 2223 eaan mee Taanerind 9 seve TES Sz UND i Tp Teed e sla 8 Ada SATA a Pi is 14 area 4 gd x SUHOG ETE caz 5 5 e SWHOS 5 a ud e ina raaos z T TIGA TONS zanne z T mvg e HoLa E gano ai aT S823 z EU E e T e ENI MMd L3 2024902 TAO Te2n anov fo Sar andu SaRETS SWHOSP as T 7 ang e siha CE 1ng e aoe E eagov Lna 5v2 anou 1023 T maa ganga ina g szpe TES SZ ud E gazi NOd Sep 2 co c vc i an a SWHOSr lo e T SNOT LOANNOD 1na ganya 023 Hd3MOd IUNOI LdO UUE di Ues aezas LAT Kazzidua ana di vzs di vzs di ues e THS ve enrama sk a 3K g TNI HMd s Uu F E oaza Ji sas2. Tezeng 1 E ki ra meu car S Tate a sr me S ING le Xe AA AMA I 8 HNOT y Letu pur als WA 1 NIU n seti Bare HERE 2 eat anu a ao a ono BTS poege 6st AK CA a Y ETT T votes 2 Uuu Eg Iud e B INI v O o ii ea Ina tindaka ang a beta ao J IHUN3 7 wo diua a EC B gerd JW3 1S x d BUS zwa Iwa ezta baan wg anw KAA ji nede anna Sars aera i E anra anta II I gaTH sata 1013 o TT EMI RI EET 2019 fi away L J 325 Tid NOU EM ae Lak s Lnodku pio l anre Sete car SERI anta vata Tani emo ofna Vous cas zx i INI eain exu 9015 9812 ING any k angu Fa sa el 10 Ba WA apo ST8 lo maius Ael cres dere 352 NS Figure 17 DUT Analog Input Circuits Rev 0 Page 10 of 28 810 9760 a72 713 AG ING HETHE ELEH aNu A N9U ING i ant a vu A ONS N7W197LdO 9029 5 ANSY NS do T 330 guni n 04 T c ING 5 y PL am NO 280 Antia orn Bac E BaZa d x19 LO A sec away E s o MEL 8 E TS h e Aede aaag L4 C HOLY TIIDSO IWNOTLdo M3WBHOJXK HOJ WHO NTTIWE 803 dUO W99 anov TW3 1S xX d C OWS N X10 1dO A m c 15 me uozl gezu s T w ING ci GNOU BOA aQ2 6S Ta maa asi Ant a I anto 3 F 1 INL 1L Gas caeco aec 112 935 Tad ING ANG 58 TlW3 1S x d r gus A 16 ano9 equ iy
3. 0 Page 22 of 28 Figure 30 Ground Plane Layer 7 Rev 0 Page 23 of 28 09436 030 ADDS DNL O GUD DD 3b3A Oo enD Oo 373A YA enD n 1 8A VADDI DNL Ld Oo enD 30A iem e EA Le gt S Q N fmm A mi o 10 m Nn Figure 31 Bottom Side Layer 8 Rev 0 Page 24 of 28 18A BADD DNL 4a B 09436 031 ORDERING INFORMATION BILL OF MATERIALS Table 1 Item Qty Reference Designator Description Manufacturer Part Number 1 1 9467CE01A PCB 2 38 C101 C102 C104 C105 C106 C107 C108 Capacitor 0 1 uF 0402 X7R Murata GRM155R71C104KA88D C109 C110 C111 C201 C202 C204 C207 ceramic C208 C209 C210 C302 C303 C313 C314 C315 C316 C317 C318 C319 C320 C321 C322 C323 C428 C431 C600 C601 C700 C701 C702 C703 3 7 C112 C200 C704 C705 C706 C707 C714 Capacitor tantalum 10 uF AVX TAJA106KO10RNJ 10 V 10 SMD 4 1 C308 Capacitor 1800 pF 25 V Panasonic ECJ 0EB1E182K ceramic 0402 SMD 5 1 C309 Capacitor ceramic 0 033 uF Panasonic 0402YD333KAT2A 1096 16 V X5R 0402 6 1 C310 Capacitor 1500 pF 0402 Panasonic ECJ 0EB1E152K 25 V ceramic X7R 7 55 C400 C401 C402 C403 C404 C405 C406 Capacitor ceramic 0 1 uF Murata GRM033R60J104KE19D C407 C408 C409 C410 C411 C412 C413 6 3 V X5R 0201 C414 C415 C416 C417 C418 C419 C420 C421 C422 C423 C424 C4
4. R610 196 Rev 0 Page 25 of 28 Item Qty Reference Designator Description Manufacturer Part Number 24 2 R117 R118 Resistor 5 60 O 1 16 W 196 Vishay Dale CRCW04025R60FNED 0402 SMD 25 2 R119 R120 Resistor 15 O 1 20 W 5 Panasonic ERJ 1GEJ150C 0201 SMD 26 2 R206 R207 Resistor 33 0 1 10 W 5 Panasonic ERJ 2GEJ330X 0402 SMD 27 4 R105 R106 R111 R112 Resistor 33 O 1 10 W 5 Panasonic ERJ 2GEJ330X 0402 SMD 28 5 R200 R201 R600 R601 R602 Resistor 10 0 kO 0402 Panasonic ERJ 2RKF1002X 1 16 W 1 29 2 R127 R128 Resistor 0 0 O 1 20 W 0201 Panasonic ERJ 1GEOROOC SMD 30 6 R204 R205 R303 R307 R308 R700 Resistor 249 O 0402 Panasonic ERJ 2RKF2490X 1 16 W 1 31 10 R300 R304 R305 R306 R309 R603 R604 Resistor 1 00 kO 0402 Panasonic ERJ 2RKF1001X R605 R701 R702 1 16 W 1 32 1 R704 Resistor 750 O 1 10 W 596 Panasonic ERJ 2GEJ751X 0402 SMD 33 1 R703 Resistor 316 0 0402 Panasonic ERJ 2RKF3160X 1 16 W 196 34 1 R301 Resistor 4 12 kO 0402 Panasonic ERJ 2RKF4121X 1 10 W 196 35 1 R302 Resistor 5 1 kO 0402 Panasonic ERJ 2GEJ512X 1 16 W 596 36 1 R316 Resistor 200 O 1 10 W 196 Panasonic ERJ 2RKF2000X 0402 SMD 37 2 R103 R130 Resistor 20 O 1 20 W 596 Panasonic ERJ 1GEJ200C 0201 SMD 38 2 R311 R313 Resistor 100 O 1 10 W 596 Panasonic ERJ 2GEJ101X 0402 SMD 39 2 T101 T104 XFMR 1 1 impedance ratio Minicircuits ADT1 1WT 40 2 T103 T200 B
5. a narrow band band pass filter with 50 Q terminations and an appropriate center frequency Analog Devices uses TTE Allen Avionics and K amp L band pass filters USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the evaluation board set up the ADC data capture block using the following steps 1 Open VisualAnalog on a PC AD9467 should be listed in the status bar of the New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 3 VisualAnalog New Canvas New Existing Recent Categories C AD9255 LI L Cl AD8261 EP P C3 AD9265 je FFT Two Tone Average AD9266 Two Tone AD9411 CJ AD3430 C3 AD9432 C3 AD9433 C3 AD9434 C3 AD9444 C3 AD9445 CJ AD9446 C3 AD9447 CJ AD9460 C3 AD9461 SREB Check for Updates AD9467 16 Bit 250 MSPS device found 09436 003 Figure 3 VisualAnalog New Canvas Dialog Box 2 After the template is selected a message box opens asking if the default configuration can be used to program the FPGA see Figure 4 Click Yes and the window closes If a different program is desired follow Step 3 VisualAnalog i VisualAnalog will now attempt to program the on board FPGA with a default file for the AD9467 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Benes clicking Yes please
6. au eu mu sn ws ws an ge maune oo P Ld Si einst man a fuaa s a E uw gt i kazamum 09436 012 Figure 12 VisualAnalog FFT Graph Full Scale Signal Applied Rev 0 Page 8 of 28 Figure 14 SPI Controller BUFFER 36 BUFFER 107 09436 013 09436 014 gt Graph AD9467 Average FFT 9 2 2010 1 14 28 PM fie m ew ele mg 15M 30M 45M GOM 75M SM 105M 120M 09436 016 Figure 16 Typical FFT AD9467 With Buffer Current Optimized 09436 015 kasasar Figure 15 SPI Controller SPI Controller BUFFER 36 BUFFER 107 Drop Down Setting Rev 0 Page 9 of 28 EVALUATION BOARD SCHEMATICS AND ARTWORK 2 A anw T E weuasasiarcoz BA gt lz ND oN 2 or Nezara L zET 1nodius E 3 9 g 104 kan aa NS TETH rn z anov 4 rtr Dg B gt H3 15 X d r Bus gar 4 Shoe Ina anay a st anto NIU WAL v ii x o NI VM poss i hd o e 1NT T1OU rag ur v T C s T Teeoqg noo ING ES Vi z rat Eo uir a o o imT Tao E E z k glow e MO Ux e 9 19 1 Hio HNO2T anr a UND y vari cato RTE aan I 8 E anta 8 Na 2812 Aa ina e 9 o e H Ow rua ig x a r eus n z Sr NE eit anu Q v B Or s 2015 AN
7. for circuit board support SAMTEC RICHCO SNT 100 BK G H CBSB 14 01 Rev 0 Page 27 of 28 NOTES A ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection Alas circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood MA 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temporary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPO
8. u z vd kbs 4029 o o E E T 1MT T1U8 taze Lu T ZL ING d A15 1do CL NG 33d ZA E Circuit Figure 18 DUT Passive Default Clock Rev 0 Page 11 of 28 6110 9860 A andu ANTA cc2 A NTA anr g usos uM Tu KE eee ated AS N ante ante Teo ated OOT SSY NTA ante s Lo azea STED Te anta ant a 5 o i alo e b n u Lo stu inr zA le 2 zeae SFE Ten S a J c ITE a S ps e 3 a SES Ui n AMA yw WV AAK as STEN ou ra S Ede auag w gu N SNI 1df1OO 30 331 114 dWhnd 39ul Aani a n2 ING 20D GNOU 227 ani TIES NDU Zd2Hv LTSbl e ani a uo ned nm S ed s EE gsn oass g1 OCS aan E 852 L15606 9052 gA1n0 N 41n0 S ST msn Ias ex Bino Lane Ose Esmas gt x m T gS1n0 N S1no Eid GNO ws1no sino 6vc bre Ni 1 08 v T MEL garu soca BSITIO N SITIO ntdc aano anra iiri usino sino g 472 H 1n07N v1nO N13938b 2 ING uv1no7e4no N72N E 733 Saco NTELNO N7dd e D3 i 4nt Eine ante v n uno e 12 INI zino 1H W737271d0 AGG TS AGD TS ABO T 8 vac2 NIT NANAS NI ue Sacue secH paru 1 Tino m EH s kah MI d i2 140 ooer prd Ps SdE9 nedE Ganu U NDU BARS Ts Ex N3389 UBIG9VTGENT LL GADA I K N
9. 25 C426 C427 C429 C430 C432 C433 C434 C435 C437 C438 C439 C440 C441 C442 C443 C444 C445 C446 C447 C448 C449 C450 C451 C452 C453 C454 C455 C456 C457 8 8 C708 C709 C710 C715 C716 C717 C718 Capacitor ceramic 4 7 uF Murata GRM188R60J475KE19D C720 6 3 V X5R 0603 9 2 C713 C719 Capacitor 10 000 pF 0402 Panasonic ECJ 0EB1C103K 16V ceramic X7R 10 1 C116 Capacitor ceramic 1 8 pF Murata GRM0335C1E1R8CD01D 25 V COG 0201 11 2 CR300 CR702 LED green USS type 0603 Panasonic LNJ314G8TRA 12 5 CR700 CR701 CR703 CR704 CR705 Rectifier SIL 2A 50 V DO Micro S2A TP 214AA Commercial Components Corp 13 1 CR200 Diode Schottky dual series Avago HSMS 2812BLK 14 8 E700 E701 E702 E703 E704 E705 E706 Bead core 3 2 x 2 5 x 1 6 Panasonic EXCCL3225U1 E707 SMD T R 45 Q 100 MHz 15 1 F700 Polyswitch 1 10 A resetfuse Tyco Raychem NANOSMDC110F 2 SMD 16 1 FL700 EMI filter LC block choke coil Murata BNX016 01 17 3 J100 J102 J201 SMA end launch COAX Samtec SMA J P H ST EM1 18 2 J300 P600 CONN PCB header 8 pin Samtec TSW 104 08 T D double row 19 1 J700 Power supply connector Switchcraft RAPC722X 20 1 L105 Inductor SM 10 nH Coilcraft 0603CS 10NXJLW 21 3 P100 P200 P300 Conn PCB BERG HDR ST Samtec TSW 103 08 G S male 3P 22 2 P501 P502 CONN_PCB 60 pin RA Tyco 6469169 1 connector 23 13 R107 R110 R123 R124 R125 R129 R310 Resistor 00 0402 1 16 W Panasonic ERJ 2GEOROOX R312 R314 R315 R606 R608
10. AM ENE 45 60 120 es RS 9 DNI una 100 PS L PS L pco_c n L x x x ES IF 8 E e e a B4 SDO USB uu bs ror zr ir csm us a8 s o Es 3 3 Rz 5 3 d a a BB n a 8 agl 9 FPGA CSB ALE 12 FPGA_SCLK Basic cu L BB a Saja uou D2 3 C M bs PR ST DAD cal a Jig pa for c ul 677 cs u bs o D8 9 C c 5 3 e lo i D18 11 C cz 335 bz D12 1 3 T ce a Dis idc cal 2 g D14 15 T ce D14 18 C cols OR T cle 12 OR C ce 18 PS02 P582 BUE pen BG 1 pei x sells 8 la j c c n Q ffi a lt ror u lu rr u ilo a Ks 9g a a i3 a jja PS 2 P502 ag 6469169 1 AND 469169 1 Figure 21 Digital Output Interface Rev 0 Page 14 of 28 09436 021 1VDD1_DUT cceo r AGND poo eau NG m m s 5 b gt 5 5 vec AVDD1_DUT ia prle e RE 4 Poo fa 3jaz p raja 1 BOK sno Y Ce ston 835 ps E Cz a 2 6 SDI USB Cs RGND AGND SCLK USB Ca REUS Cs 1 GOK CSELUSR C2 a e TSW 184 08 G D PMDDE DUT ei AGND UBaL 1UF Y s vc AVDD 3P3U e ini Yije SCLK bris 3 e pn rela css SND E sox NCTWZL6PEXx ig a a AGND Figure 22 SPI Interface Circuitry Rev 0 Page 15 of 28 Rea6 cSB e css nur 9 vid FPGA CSB DNI Reap sDI0 B sp10_put 9 m FPGA SDIO p DNI R510 m a sicLK_DUT L Rett FreA sak DNI 09436 022 20 9 v60
11. ANALOG DEVICES Evaluation Board User Guide UG 200 One Technology Way lt P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 lt Fax 781 461 3113 e www analog com Evaluating the AD9467 16 Bit 200 MSPS 250 MSPS ADC FEATURES Full featured evaluation board for the AD9467 SPI and alternate clock options Internal and external reference options VisualAnalog and SPI Controller software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter 2 switching power supplies 6 0 V 2 5 A CUI EPS060250UH PHP SZ included PCrunning Windows 98 2nd ed Windows 2000 Windows ME or Windows XP USB 2 0 port recommended USB 1 1 compatible AD9467 evaluation board HSC ADC EVALCZ FPGA based data capture kit DOCUMENTS NEEDED AD9467 data sheet HSC ADC EVALCZ data sheet High Speed Converter Evaluation Platform FPGA based data capture kit AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interface to High Speed ADCs via SPI SOFTWARE NEEDED VisualAnalog SPI Controller GENERAL DESCRIPTION This document describes the evaluation board for the AD9467 which provides all of the support circuitry required to operate the AD9467 in its various configurations The application software used to interface with the device is also described The AD9467 data sheet av
12. C to operate with the default internal reference in the 2 5 V p p full scale range A separate external reference option using the ADR130 is also included on the evaluation board Populate R400 with a 0 Q resistor Note that ADC full scale ranges from 2 0 V p p to 2 5 V p p are supported by the AD9467 Clock Circuitry The default clock input circuitry is derived from a simple transformer coupled circuit using a high bandwidth 1 1 impedance ratio transformer T201 that adds a very low amount of jitter to the clock path The clock input is 50 0 terminated and ac coupled to handle single ended sine wave types of inputs The transformer converts the single ended input to a differential signal that is clipped before entering the ADC clock inputs The evaluation board can be set up to be clocked from the crystal oscillator Y200 This oscillator is a low phase noise oscillator from Vectron VCC6 QCD 250M000 If this clock source is desired install C205 and C206 and remove C202 Jumper P200 is used to disable the oscillator from running A differential LVPECL or LVDS clock driver can also be used to clock the ADC input using the AD9517 U300 Populate C304 C305 C306 and C307 with 0 1 uF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default dock path inputs The AD9517 has many SPI selectable options that are set to a default mode of operation Consult the AD9517 data sheet for more information about t
13. HEE ana taany BEEN andu HEISE Gast era Es s iss s fl fa a Afe ja S e o Tana A NOU am aod NES wuah 22 Sep antal ante L anro L anre anre L anto L anre 4nt a nh Coe 28v2 9sv gt sera bawa ite Se 5av2 vara 225 85 cn 4 e n 1na dansa T A T ra1 auou e e e e santa Ants Puka A4nr a Anr a Pula AnT a Aanr a Espo 2sr9 1892 asro 81v9 ST gera caya e e e e e e 1na zdune A ano d d ant ml an1a anta anta nT anta L antra L anta L anra ant o L anra EZE T awa aera T PSI e i sewa zeva swa EST PCI zara ae he A nou antak ante anra L anta L amice L antca anrea L antal antal anra L anre T anto L anta ved ebro zvo Tovo avr Berd 2209 ver Tero 9103 TRI Sov Tero e e e e e e e e e e e INA TAA A ansv d e e t e e e e e e T e anta anro L antca L antal anre L anta L anta ama anre D ante L anto L antca anta L anro L anta aero Lev Sera vera ey zero Bevo 6237 sera T evo T Berd T stro To o ji ser T oaro T e e e e e e Ld e e e e 1na ragae Figure 20 DUT Circuitry Rev 0 Page 13 of 28 OPTIONAL TERMINRTION peo t__ BRAK DM eoc 180 O1 DNI DB 1 T RSAT DNI pesi_c igo saa D2 3 T leroy eal D2 3 C 140 D4 5_1 ayy pa DA 8 C 120 D6 7_1 ayy DNE 16 76 100 De s T Bag NI ne s c 100 5i Dimani RRAS DNI m s 1 c 100 wanazi R507 DNI Di2 13 C 120 disp UN
14. NV 5 SEWA S o Tr ssudAg Ant caca ap 2 wasa Y EH zig TNG Www do TN yt qs e Wa PT T E2 y NW bans TAH NI43N CC Anta A eaca SV Noi GNogNET v 1 onis 1225724394 ING maca dAdo 1388 3 Teed rl pa S T08g61 5 oaen i eo T oaeu ngag aqnu META GE 2 1 j BEd L IflIOMIO ILUd 20 12 IUNOTI LdO Rev 0 Page 12 of 28 Figure 19 DUT Active Clock Circuit 0Z0 9 760 anga Bn kk ae b hdd 1na tugae im l IE IE NETE lali s oe fra e lo m aken ken Ja lo fv l SU22u09222222002222 5g28822222222222222 ELETE IATE PAD W9 271 28 28 ne 1 c mwani Z2 ved Z2 na 1 T Popp ZA pagan s aa punp 22 ana tagnw a n2 3 T les areren 23 wana n4 s c bo 27s muDDa 24 45 17 67 i amp vn n10 sasen 25 ne 1 c viros B5 26 VIN POS NIU 090 ico 54 27030 ANI Lwa 28 co ones Ba E 275 80 mpi dSO31 NId Z avon 82 1 8780 ET hrei avon EL Lcd ao netic 2976004277609 wnn 52 ortara trr um 5a ant a zerera 22 ni2 12 c Gunns PB gevo ametseta AJA REFERENCE S7 ostverd aa 1412 6 avon BB 59 o iste D14 15 T auon 55 z E I 1NG zrnuae TAJI 1na raane 3 Ree i HEEFEEEHTEEHHTEEPTE
15. SES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material conte
16. a pasu 2249 T8209 1 9 TBXNH gas 86219 KUW Uc Sang Ael ego A lddNS lt a sMOe et Figure 23 Power Supply Circuitry Rev 0 Page 16 of 28 Evaluation Board User Guide A0 ina 20QAv Aede QQAV ing TOGAY ina adaya o gt ps J102 THESE C107 ee 71 asd Ri12 2R1205 2 GAD es o gt TIOR 425 e c IN Pag m 2 e N E vum mui 000000 T F E A 1 e o Oupa CUSTOMER wa EVALUATION BOARD PEJ LES o 10 00000 oooooo P600 Uo v 000000 c 2 zy im gt 49 P200 000000 eee 000000 000000 o o e OD ES dium 09436 024 Figure 24 Top Layer 1 Rev 0 Page 17 of 28 ENS E EN x EE EE m p 9 9 9 Figure 25 Ground Layer 2 Rev 0 Page 18 of 28 eo 5 eo 09436 026 Figure 26 Power Plane Layer 3 Rev 0 Page 19 of 28 uu es ot Oa ASA l 29 AN A SLA EA ON 9 9 EN IANA NAN x NAN AIN AA Figure 27 Ground Plane Layer 4 Rev 0 Page 20 of 28 8 8 WI K Figure 28 Ground Plane Layer 5 Rev 0 Page 21 of 28 x N N r S ZN AN AT AS 09436 028 UG 200 Evaluation Board User Guide 09436 029 Figure 29 Power Plane Layer 6 Rev
17. ailable at www analog com which provides additional information should be consulted when using the evaluation board All documents and software tools are available at http www analog com fifo For any questions send an email to highspeed converters analog com 09436 001 Figure 1 AD9467 250EBZ Evaluation Board and HSC ADC EVALCZ Data Capture Board PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev 0 Page 1 of 28 TABLE OF CONTENTS Fedtur ss ea Equipment Needed sss Documents Needed sss Software Needed ses General Description seen Typical Measurement Setup sss Revision History sse Evaluation Board Hardware Power Supplies eee qt REVISION HISTORY 10 10 Revision 0 Initial Version NA ae 1 Input Signalaren GAN ERR sadana iang awa 1 Output Signals sadasa ian kani nen CIE Nan Asan WA NE as 82 1 Default Operation and Jumper Selection Settings 5 TOREM 1 Evaluation Board Software Quick Start Procedures 6 aga aaa gaya 1 Configuring the Board eee KA AOA 1 Using the Software for Testing sse SAA WAHAYA 2 Evaluation Board Schematics and Artwork 10 NE PT F 3 Ordering Information essent 25 8 3 Billof Materials te nte
18. alun 1 1 impedance ratio Macom MABA 007159 000000 41 1 T105 Balun 1 1 impedance ratio Anaren BD0205F5050A00 42 1 DUT1 IC ADI LFCSP 10 mm x Analog Devices AD9467BCPZ 250 10 mm plus EPAD 43 1 U100 IC 2 6 GHz ultralow Analog Devices ADL5562ACPZ R7 distortion differential IF RF amplifier 44 1 U300 IC ADI 12 output CLK GEN Analog Devices AD9517 4BCPZ with INT 1 6 GHZ VCO 45 1 U400 IC voltage ref precision Analog Devices ADR130AUJZ series SOT23 6 46 1 U600 IC tinylogic UHS dual buffer Fairchild NC7WZO07P6X 47 1 U601 IC tinylogic UHS dual buffer Fairchild NC7WZ16P6X 48 2 U700 U701 IC regulator 0 8 V to 5 0 V Analog Devices ADP1708ARDZ R7 low dropout CMOS SO8 49 1 U702 IC ADI low dropout CMOS Analog Devices ADP1706ARDZ 3 3 R7 linear regulator 50 1 U703 IC ADI low dropout CMOS Analog Devices ADP1706ARDZ 1 8 R7 linear regulator 51 1 Y200 250 MHz XTAL 3 3 V LVPECL Vectron VCC6 QCD 250M000 OSC Rev 0 Page 26 of 28 Item Oty Reference Designator Description Manufacturer Part Number 52 53 MP101 MP102 MP103 MP104 MP105 MP106 MP107 MP111 MP112 MP113 MP114 Part of assembly 100 mil jumpers place into P100 Pin 2 to Pin 3 P200 Pin 1 to Pin 2 J300 Pin 3 to Pin 4 P600 Pin 1 to Pin 2 Pin 3 to Pin 4 Pin 5 to Pin 6 Pin 7 to Pin 8 Part of assembly insert snap into the large holes from the bottom side of board 14 mm height dual locking standoffs
19. hen connecting the analog input source it is recommended to use a multipole narrow band band pass filter with 50 O terminations Analog Devices uses TTE and K amp L Microwave Inc band pass filters The filter should be connected directly to the evaluation board OUTPUT SIGNALS The default setup uses the FIFO5 high speed dual channel FIFO data capture board HSC ADC EVALCZ For more information on this board and its optional settings visit http www analog com fifo Rev 0 Page 3 of 28 WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY irises ANALOG INPUT PC RUNNING ADC ANALYZER OR VisualAnalog USER SOFTWARE SIGNAL SYNTHESIZER 09436 002 Figure 2 Evaluation Board Connection Rev 0 Page 4 of 28 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the evaluation board for the AD9467 Power Circuitry Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P700 Analog Input Front End Circuit The evaluation board is set up for single ended analog input connection with an optimum 50 Q impedance match of 350 MHz of bandwidth For a different bandwidth response the input network needs to be changed or modified XVREF XVREF is set to 1 25 V This causes the AD
20. hese and other options Dx Dx Ifan alternative data capture method to the setup shown in Figure 2 is used optional receiver terminations R500 to R509 can be installed next to the high speed backplane connector P502 Rev 0 Page 5 of 28 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9467 either on the evaluation board or at the system level design Both the default and optional settings are described CONFIGURING THE BOARD Before using the software for testing configure the evaluation board as follows l Connectthe evaluation board and the HSC ADC EVALCZ as shown in Figure 1 and Figure 2 2 Connect one 6 V 2 5 A switching power supply such as the CUI Inc EPS060250UH PHP SZ included to the evaluation board 3 Connect one 6 V 2 5 A switching power supply such as the CUI EPS060250UH PHP SZ included to the HSC ADC EVALCZ board 4 Connect the USB cable to J6 on the HSC ADC EVALCZ board to the PC 5 On the evaluation board place jumpers on all four pin pairs of P600 to connect the SPI bus 6 Onthe evaluation board ensure that P200 is jumpered to the off setting to use the on board 250 MHz Vectron VCC6 oscillator 7 On the evaluation board use a clean signal generator with low phase noise to provide an input signal to the desired channel Use a 1 m shielded RG 58 50 Q coaxial cable to connect the signal generator For best results use
21. in a nondefault condition E704 E705 E706 E707 can be removed to disconnect the switching power supply This enables the user to bias each section of the board individually Use P700 and P701 to connect a different supply for each section At least one 1 8 V supply is needed with a 1 A current capability for 1 8 V AVDDI and 1 8 V DRVDD however it is recommended that separate supplies be used for both analog and digital domains An additional supply is also required to supply 3 3 V to the DUT 3 3 V AVDD2 This should also have a 1 A current capability To operate the evaluation board using the SPI and alternate clock and amplifier options a separate 3 3 V analog supply is needed in addition to the other supplies The 3 3 V supply or 3 3 V 3P3V_AVDD should have a 1 A current capability INPUT SIGNALS When connecting the ADC clock and analog source use clean signal generators with low phase noise such as Rohde amp Schwarz SMA or HP8644B signal generators or the equivalent Use a 1 m shielded RG 58 50 0 coaxial cable for making connections to the evaluation board Enter the desired frequency and amplitude refer to the specifications in the AD9467 data sheet If a different or external ADC clock source is desired follow the instructions in the Clock Circuitry section or use the on board crystal oscillator Y200 Typically most Analog Devices Inc evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock W
22. make sure the HSC ADC EVALC is powered with the correct supply and the board is connected to the computer Also make sure the dipswitch U4 on the HSC ADC EVALC is set to the following configuration M0 ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light Do not show this message again 09436 004 Figure 4 VisualAnalog New Canvas Message Box 3 To view different channels or change features to settings other than the default settings click the Expand Display button located on the top right corner of the VisualAnalog window as shown in Figure 5 and Figure 6 This process is described in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual Once you are finished click the Collapse Display button EXPAND DISPLAY BUTTON 09436 005 ws ui mI wa Figure 5 VisualAnalog Window Toolbar Expand Display Button Rev 0 Page 6 of 28 asu e COLLAPSE DISPLAY BUTTON gt mELI m g ee aaa as et tis TST ITT Tis 09436 006 Figure 6 VisualAnalog Main Window Expanded Display 4 Program the FPGA of the HSC ADC EVALCZ board to a setting other than the default setting as described in Step 3 Then expand the VisualAnalog display and click the Settings button in the ADC Data Capture block see Figure 6 The ADC Data Capture Settings box opens see Figure 7 menu and select the appropriate configura
23. nt of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIABILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive la
24. oller software by going to the Start eee Figure 10 09436 010 Figure 10 VisualAnalog Window Toolbar Run Button Applying Input Signal and Optimizing SFDR Apply the input signal as follows 1 Apply the input signal so that the fundamental is at the desired level examine the Fund Power reading in the left panel of the VisualAnalog FFT window See Figure 11 and Figure 12 gt Graph AD9467 Average FFT 9 2 2010 1 11 54 PM 105M 120M Ham 4 Power 100 448 dBc Ham 5 Power 105 166 dBc Ham 6 Power 112 019 dBc Worst Other Frequency 91 545 MHz Worst Other Power 92 926 dBFS Noise Hz 155 968 dBFS Hz Average Bin Noise 120 153 dBFS r Figure 11 VisualAnalog FFT Graph No Signal or Very Low Signal Applied 09436 011 9 Figure 13 Typical FFT AD9467 No Buffer Current Optimization 2 To optimize SFDR performance use Register 36 and Register 107 to change the buffer current setting In the ADCBase 0 tab of the SPI Controller find the BUFFER 36 BUFFER 107 box Use the drop down list box to select the best current if necessary See the AD9467 data sheet the AN 878 Application Note and the AN 877 Application Note for reference WA es rw cnm r mr i u 1 EE m EET m E El m E 3 ras acm ome SS om z E D ne
25. retener 2D Rev 0 Page 2 of 28 EVALUATION BOARD HARDWARE The AD9467 evaluation board provides all of the support circuitry reguired to operate the AD9467 in its various modes and configurations Figure 2 shows the typical bench charac terization setup used to evaluate the performance of the AD9467 It is critical that the signal sources used for the analog input and clock have very low phase noise 1 ps rms jitter to realize the optimum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance see the AD9467 data sheet See the Evaluation Board Software Quick Start Procedures section to get started and Figure 17 to Figure 31 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V 2 5 A maximum output Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz The other end is a 2 1 mm inner diameter jack that connects to the PCB at P700 Once on the PC board the 6 V supply is fused and conditioned before connecting to low dropout linear regulators that supply the proper bias to each of the various sections on the board When operating the evaluation board
26. tion Note that the CHIP ID 1 field should be filled to indicate whether the correct SPI Controller configuration file is loaded see Figure 8 o ae goon It erem crm 09436 008 Figure 8 SPI Controller CHIP ID 1 Box 2 Clickthe New DUT button in the SPI Controller see ADC Data Capture Settings Figure 9 Genera Capture Board Device FIFO Fill Poll Full Flag Emo ones Fill Delay ms fo Maximum Poll Time ms o SENG FER Z S NEW DUT BUTTON Program File j Devices VisualAnalog Hardware HSC_ADC_EVALC MELA Browse Auto control FPGA data capture mode Capture data from RAM Ee Figure 7 ADC Data Capture Settings Capture Board Tab 5 Selectthe Capture Board tab and browse to the appropriate programming file Next click Program the DONE LED D6 in the HSC ADC EVALCZ board should then turn on E 6 Exitthe ADC Data Capture Settings box by clicking OK Figure 9 SPI Controller New DUT Button Setting Up the SPI Controller 3 Click the Run button in the VisualAnalog toolbar see After the ADC data capture board setup has been completed set up the SPI Controller 1 menu or double clicking the SPI Controller software desktop icon If prompted for a configuration file select the appropriate one If not check the title bar at the top of the SPI Controller window to determine which configura tion is loaded If necessary choose Cfg Open from the File Rev 0 Page 7 of 28 Open the SPI Contr
27. ws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG09436 0 10 10 0 DEVICES www analog com Rev 0 Page 28 of 28
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