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2. 40 0 25 85 125 ky DoclD14771 Rev 10 77 127 Electrical characteristics STM8S105xx 78 127 Figure 22 Typical HSI accuracy vs Von 4 temperatures 1 00 7 0 50 0 00 4 E g 3 ase ee aa Ki 2 1 00 4 1 50 4 2 00 4 l 25 3 35 4 45 5 55 Von V Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and T4 Table 35 LSI oscillator characteristics LSI oscillator wakeup time LSI oscillator power consumption 1 Guaranteeed by design not tested in production DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics 10 3 5 Figure 23 Typical LSI accuracy vs Vpp 4 temperatures 5 00 T T T T T T 2 25 3 3 5 4 45 5 55 Von V D Memory characteristics RAM and hardware registers Table 36 RAM and hardware ES RK Data retention mode Halt mode or reset rr 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production refer to Operating conditions for the value of ViT max Refer to the Operating conditions section for the value of Vu ve Flash program memory data EEPROM memory General conditions T 40 to 125 C Table 37 Flash program memory data EEPROM memory Se ese ee ee Operating voltage all modes fopy lt 16 MHz 2 95
3. Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in the table below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 12 Option bytes Option Option Option bits Factory name byte no default 0x4800 Read out OPTO ROP 7 0 00h protection ROP 0x4801 User boot OPT1 UBC 7 0 00h code UBC 0x4802 NOPT1 NUBC 7 0 FFh 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO function remappin 0x4804 AFR g NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh 0x4805h Miscell OPT3 Reserved HSI LSIL_EN IWDG WWDG WWDG 00h option TRIM _HW _HW HALT NOPT3 Reserved NHSI NLSI_ NIWDG NWWDG NWW TRIM EN _HW _HW G_HALT Clock OPT4 Reserved EXT CLK CKAWU PRS C1 PRS CO option SEL NOPT4 Reserved NEXT NCKA NPRSC1 CLK WUSEL 0x4809 HSE clock OPT5 HSECNT 7 0 startup 0x480A NOPTS NHSECNT 7 0 0x480B ae Reserved 50 127 DoclD14771 Rev 10 a STM8S105xx Option bytes Option Option Option bits Factory name byte no default 0x487E Bootloader SE BL 7 0 Table 13 Option byte description OPTO ROP 7 0 Memory readout pr
4. Software tools STMB8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code DoclD14771 Rev 10 121 127 STM8 development tools STM8S105xx 14 2 1 14 2 2 14 3 122 127 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and co
5. C for standard ports two high suffix 3 sink ports and two open drain ports simultaneously 3 32 pin package with output on eight standard ports and two high sink ports simultaneously Ambient temperature Maximum power for 6 suffix version dissipation Ambient temperature Maximum power for 3 suffix version dissipation range 130 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 60 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics To calculate Pomax T a use the formula Pomax Tymax Ta Oya See Thermal characteristics with the value for Tj given in the current table and the value for Oja given in Thermal characteristics 3 Refer to Thermal characteristics OT nax is given by the test limit Above this value the product behavior is not guaranteed Figure 11 fopymax Versus Vpp Cpu MHz Functionality not 16 guaranteed inthisarea 12 2 95 4 0 5 0 5 5 Supply voltage Table 20 Operating conditions at power up power down jamma O E peme E Power on reset threshold Brown out reset hysteresis Brown out reset threshold 0 Guaranteed by design not tested in production ky DoclD14771 Rev 10 61 127 Electrical characteristics STM8S105xx 10 3 1 VCAP external capacitor Stabilization for the main regulat
6. The following section intends to give an overview of the basic features of the device functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers SG Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing 20 addressing modes SG indexed indirect addressing mode for look up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfe
7. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVEGRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately voidany warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com DoclD14771 Rev 10 127 127
8. yy STM8S105xx Access line 16 MHz STM8S 8 bit MCU up to 32 Kbytes Flash integrated EEPROM 10 bit ADC timers UART SPI PC D mo gt lt LQFP48 7x7 TH VFQFPN32 5x5 LQFP32 7x7 1 SDIP32 400 ml UFQFPN32 5x5 Features Core 16 MHz advanced STM6 core with Harvard architecture and 3 stage pipeline Extended instruction set Memories Medium density Flash EEPROM Program memory up to 32 Kbytes data retention 20 years at 55 C after 10 kcycles Data memory up to 1 Kbytes true data EEPROM endurance 300 kcycles SG RAM Up to 2 Kbytes Clock reset and supply management SG 2 95 V to 5 5 V operating voltage Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Power management Low power modes wait active halt halt Switch off peripheral clocks individually Permanently active low consumption power on and power down reset September 2010 Interrupt management SG Nested interrupt controller with 32 interrupts SG Up to 37 external interrupts on 6 vectors Timers 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM SG Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization SG
9. 32 lead very thin fine pitch quad flat no lead package 5 X 5 o eeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeeees 111 Figure 51 32 lead ultra thin fine pitch quad flat no lead package 5 X 5 eeeeceeseeeeeeeeteeeeeeeeneeees 111 Figure 52 32 lead shrink plastic DIP 400 ml package ou ceeeneeeeeeeeeeeeeeeeeeteeeeeeenaaeeeeeeenieeeeenenaees 112 Figure 53 STM8S105xx access line ordering information scheme 116 ky DoclD14771 Rev 10 7 127 Introduction STM8S105xx 8 127 Introduction This datasheet contains the description of the device features pinout electrical characteristics mechanical data and ordering information For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 8 For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STM8 core please refer to the STM8 CPU programming manual PM0044 DoclD14771 Rev 10 ky STM8S105xx Description 2 Description The STM8S105xx access line 8 bit microcontrollers offer from 16 to 32 Kbytes Flash program memory plus integrated true data EEPROM They are referred to as medium density devices in t
10. 7 0 of OPT2 Electrical characteristics Updated VCAP specifications updated Table 15 Table 18 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 29 Table 35 and Table 42 added current consumption curves removed Figure 20 typical HSE frequency vs fcpu 4 temperatures updated Figure 13 Figure 14 Figure 15 Figure 16 and Figure 17 modified HSI accuracy in Table 33 added Figure 44 modified fSCK tV SO and tV MO in Table 42 updated figures and tables of High speed internal RC oscillator HSI replaced Figure 23 Figure 24 Figure 26 and Figure 39 Package information Updated Table 58 Thermal characteristics 1 and removed Table 57 Junction temperature range Updated Figure 53 STM8S105xx access line ordering information scheme Document status changed from preliminary data to datasheet Standardized name of the VFQFPN package Removed wpu from DC pins in Pinout and pin description Added UFQFPN32 package silhouette to the title page Features added unique ID Clock controller updated bit positions for TIM2 and TIM3 Beeper added information about availability of the beeper output port through option bit AFR7 Analog to digital converter ADC1 added a note concerning additional AIN12 analog input STM8S105 pinouts and pin description added UFQFPN32 package details updated default alternate function of PB2 AIN2 TIM1_CH3N pin in the Pin descript
11. PC6 HS SPI_MOSI VDDIO 2 VssIO_2 PC5 HS SPI_SCK PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 UART2_CK PE5 SPI_NSS HS high sink capability 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function a DoclD14771 Rev 10 23 127 Pinout and pin description STM8S105xx Figure 5 LQFP VFQFPN UFQFPN 32 pin pinout 1 HS high sink capability NRST OSCIN PA1 OSCOUT PA2 Vss VCAP VDD Vppo H AIN12 PF4 ONOaarkr an bei O 9i w Ei vn Zz SEN uas 2 EES St a Zit Dass D NN Of OM sae 2ee2 FFERERSE EE ooo o o GE E E d si 223222 F oO 0 sg o ON e Ge AA AA AADA a O BS E amp amp E 32 31 30 29 28 27 26 25 e 24 9 10 11 12 13 14 15 16 23 22 21 20 19 18 0 17 VDDA VSSA I2C_ SDA AIN5 PB5 VC SCU AIN4 PB4 TIM1_ETR AIN3 PB3 TIM1_CH3N AIN2 PB2 TIM1_CH2N AIN1 PB1 TIM1_CH1N AINO PBO PC7 HS SPI_MISO PC6 HS SPI_MOSI PCS HS SPI_SCK nn PC4 HS TIM1_CH4 PC3 HS TIM1_CH3 PCS HS TIM1_CH2 PC1 HS TIM1_CH1 UART2_CK PE5 SPI_NSS 2 alternate function remapping option If the same a
12. Table 58 Thermal characteristics Ss es EE Thermal resistance junction ambient LQFP 48 7x 7mm Thermal resistance junction ambient LQFP 44 10x 10mm Thermal resistance junction ambient LQFP 32 7x 7mm Thermal resistance junction ambient VQFPN 32 5x5mm 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org DoclD14771 Rev 10 ky STM8S105xx Thermal characteristics 12 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature T amaz 82 C measured according to JESD51 2 Ippmax 15 MA Vpp 5 5 V Maximum 8 standard I Os used at the same time in output at low level with Io 10 mA VoL 2 V Maximum A high sink I Os used at the same time in output at low level with l 20 mA VoL 1 5 V Maximum 2 true open drain I Os used at the same time in output at low level with Io 20 mA Vos 2 V Pintmax 15 MA x 5 5 V 82 5 mW Promax 10 mA x 2 V x8 HD mA x 2 V x 2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 MW and Piomax 360 mW PDm
13. register 1 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 532A TIM3_PSCR TIM3 prescaler register 42 127 DoclD14771 Rev 10 ky STM8S105xx Memory and register map 0x00 532B TIM3_ARRH TIM3 auto reload register high 0x00 532C TIM3_ARRL TIM3 auto reload register low 0x00 532D TIM3_CCR1H TIM3 capture compare register 1 high 0x00 532E TIM3_CCRIiL TIM3 capture compare register 1 low 0x00 532F TIM3_CCR2H TIM3 capture compare register 2 high 0x00 5330 TIM3_CCR2L TIM3 capture compare register 2 low 0x00 5331 to Reserved area 15 bytes 0x00 533F 0x00 5347 to Reserved area 153 bytes 0x00 53DF 0x00 53E0 to ADC1 ADC_DBxR ADC data buffer registers 0x00 53F3 ky DoclD14771 Rev 10 43 127 Memory and register map STM8S105xx 0x00 53F4 to Reserved area 12 bytes 0x00 53FF 0x00 5406 ADC_TDRH ADC Schmitt trigger disable 0x00 register high 0x00 5407 ADC_TDRL ADC Schmitt trigger disable 0x00 register low 0x00 5408 ADC_HTRH ADC high threshold register 0x03 high 0x00 5409 ADC_HTRL ADC high threshold register low 0x00 540A ADC_LTRH ADC low threshold register 0x00 high 0x00 540B ADC_LTRL ADC low threshold register low 0x00 540C ADC_AWSRH_ ADC analog watchdog status 0x00 register high 0x00 540D ADC_AWSRL_ ADC analog watchdog status 0x00 register low 44 127 DoclD14771 Rev 10 ky STM8S105xx Memory and register map 6 2 3 0x00 540E ADC _AWC
14. 5 5 execution write erase Standard programming time ms including erase for byte word block 1 byte 4 bytes 128 bytes DoclD14771 Rev 10 79 127 Electrical characteristics STM8S105xx Fast programming time for 1 block 3 0 128 bytes Erase time for 1 block 128 bytes Hh Erase write cycles program 10k memory Erase write cycles data memory T 125 C 300k 1 0M Data retention program memory after 10k erase write cycles at T4 85 C Data retention data memory after 10k erase write cycles at T4 85 C Data retention data memory after 300 k erase write cyclesat T 125 C Supply current Flash programming or erasing for 1 to 128 bytes 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte Data based on characterization results not tested in production 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 38 I O static characteristics Se ko FEEF Input low level Vbp 5 V 0 3 0 3 x Vpp voltage 80 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Rise and fall time 10 90 Standard and high sink Os
15. 8 bit basic timer with 8 bit prescaler Auto wake up timer 8 Window and independent watchdog timers Communications interfaces SG UART with clock output for synchronous operation Smartcard IrDA LIN SPI interface up to 8 Mbit s e VC interface up to 400 Kbit s Analog to digital converter ADC SG 10 bit 1 LSB ADC with up to 10 multiplexed channels scan mode and analog watchdog Os SG Up to 38 I Os on a 48 pin package including 16 high sink outputs Highly robust I O design immune against current injection Development support SG Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging Unique ID 96 bit unique key for each device Table 1 Device summary STM8S105xx STM8S105K4 STM8S105K6 STM8S105S4 STM8S105S6 STM8S105C4 STM8S105C6 DoclD14771 Rev 10 1 127 www st com Contents STM8S105xx Contents 1 MGW OCU CUIONA eege CEA ANERE 8 2 Description EE 9 3 Block TE LU NEE 11 4 Product OvervieW xcscscscasccsasenectenseresensecetncearenepsatcatne as ares eee 12 4 1 Central processing unit STM8 ou eect ee cteee terete eee eee nunnia eaeeeeeetaaeeeeeenaeeeeee 12 4 2 Single wire interface module SWIM and debug module DM ceeeeteeeeeeeees 12 4 3 Interrupt Controller 13 4 4 Flash program and data EEPROM Memory 13 4 5 COCK COMMONS vrlini a aa aea SERA 14 4 6 Power management cecceceeecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaeeee
16. BEEP AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate functions 1 Port B5 alternate function I C_SDA port B4 alternate function sf SCL AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate functions 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1_NCC3 port B1 alternate function TIM1_CH2N port BO alternate function TIM1_CHI1N AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate function 1 Port D7 alternate function TIM1_CH4 AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port DO alternate function TIM1_BKIN AFR2 Alternate function remapping option 2 DoclD14771 Rev 10 53 127 Option bytes STM8S105xx Option byte no Description 0 AFR2 remapping option inactive Default alternate function 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AER Alternate function remapping option 1 0 AFR1 remapping option inactive Default alternate functions 1 Port A3 alternate function TIM3_CH1 port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 0 AFRO remapping option inactive Default alternate function 1 Port D3 alternate function ADC_ETR 0 Do not use more than one remapping
17. SWIM clock control register ObXXXX XXX0 DoclD14771 Rev 10 35 127 Memory and register map STM8S105xx 36 127 0x00 50CE to Reserved area 3 bytes 0x00 50D0 0x00 50D1 WWDG WWDG_CR WWDG control register BEE 50D2 WWDG_WR WWDR window register 0x00 50D3 to Reserved area 13 bytes 0x00 50DF 0x00 50E0 IWDG IWDG_KR IWDG key register Oxxx 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 50E2 IWDG_RLR IWDG reload register 0x00 50E3 to Reserved area 13 bytes 0x00 50EF x00 50Fo 50F0 AWU AWU_CSR1 AWU control status register 1 0x00 50F 1 AWU_APR AWU asynchronous prescaler 0x3F buffer register 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 50F3 BEEP BEEP_CSR BEEP control status register 0x00 50F4 to Reserved area 12 bytes 0x00 50FF DoclD14771 Rev 10 ky oos 5202 oss 5203 STM8S105xx Memory and register map 0x00 5208 to Reserved area 8 bytes 0x00 520F DoclD14771 Rev 10 37 127 Memory and register map STM8S105xx 38 127 0x00 521E I2C_PECR rc packet error checking register 0x00 521F to Reserved area 17 bytes 0x00 522F 0x00 5230 to Reserved area 6 bytes 0x00 523F 0x00 524C to Reserved area 4 bytes 0x00 524F 0x00 5250 TIM1 TIM1_CR1 TIM1 control register 1 0x00 5251 TIM1_CR2 TIM1 control register 2 DoclD14771 Rev 10 ky STM8S105xx Memory and register map 0x00 5255 0x00 5256 0x00 5257 0x00 525E 0x00 525F TIM1_SR1 TIM1 statu
18. V standard ports Von Vou V Voo Vou V lon mA 88 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Figure 36 Typ Vpp Von Vpp 3 3 V high sink ports 10 3 8 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 42 NRST pin characteristics VIL NRST NRST input low level voltage VIH NRST NRST input high loL 2 mA level voltage Vou NRST NRST output low level voltage SS tI FP NRST NRST input filtered pulse hu FP NRST NRST input not filtered pulse ky Rpu nrsT NRST pull up resistor DoclD14771 Rev 10 89 127 Electrical characteristics STM8S105xx nt ke ka Jk kk Je onnpen NRST output pulse 3 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 37 Typical NRST Vu and Vi ve Vpp 4 temperatures Ves wy 90 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Figure 38 Typical NRST pull up resistance vs Von 4 temperatures NRESET pull up es tarce W Figure 39 Typical NRST pull up current vs Vpp 4 temperatures 25 3 3 5 4 Vee M 45 55 NRESET Pull Up ourrent The reset netwo
19. code Preferable format for programing code is Hex s19 is accepted If data EEPROM programing is required a seperate file must be sent with the requested data v Important See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation Device type memory size package check only one option FASTROM device 16 Kbyte 32 Kbyte VFQFPN32 STM8S105K4 STM8S105K6 LQFP32 STM8S105K4 STM8S105K6 LQFP44 STM8S105S4 STM8S105S6 LQFP48 STM8S105C4 STM8S105C6 Conditioning check only one option Tape amp reel or Tray Special marking check only one option No Yes Authorized characters are letters digits and spaces only Maximum character counts are VFQFPN32 1 line of 7 characters max a LQFP32 2 lines of 7 characters max and g LQFP44 2 lines of 7 characters max and R LQFP48 2 lines of 8 characters max and i Temperature range 40 C to 85 C or 40 C to 125 C Padding value for unused program memory check only one option oF Ox83 TRAP instruction opcode Ox75 Illegal opcode causes a reset when executed OPTO memory readout protection check only one option Disable or Enable OPT1 user boot code area UBC Ox __ fill in the hexadecimal value refering to the datasheet and the binary format below FASTROM code name is assigned by STMicroelectronics a
20. control register 1 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 7F98 DM_CSR1 DM debug module control status register 1 0x00 7F99 DM_CSR2 DM debug module control status register 2 0x00 7F9A DM_ENFCTR DM enable function register 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F Accessible by debug module only ky DoclD14771 Rev 10 47 127 Interrupt vector mapping STM8S105xx 7 Interrupt vector mapping Table 11 Interrupt mapping Description Wakeup from Vector active halt keck FF kk LL es pe emeena Les pe peee woos kk ff Jeer es rome fw Jee E f f ee CT ks LL a underflow trigger break e freemen rw kb LL es DESEN 48 127 DoclD14771 Rev 10 ky STM8S105xx Interrupt vector mapping ot Description Wakeup from Vector block active halt zb ff see is oe femmes LL Fer el pee E E ee ST ks LL Fei 21 UART2 Receive register DATA 0x00 805C FULL 22 ADC1 ADC1 end of conversion 0x00 8060 analog watchdog interrupt Reserved 0x00 806C to 0x00 807C S Except DA ky DoclD14771 Rev 10 49 127 Option bytes STM8S105xx 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy
21. ky DoclD14771 Rev 10 117 127 Ordering information STM8S105xx 118 127 UBC bitO UBC bit1 UBC bit2 UBC bit3 UBC bit4 UBC bit5 OPT2 alternate function remapping AFRO check only one option AFR1 check only one option AFR2 check only one option AFR3 check only one option AFR4 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D3 alternate function ADC_ETR 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port A3 alternate function TIM3_CH1 port D2 alternate function TIM2_CH3 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port DO alternate function CLK_CCO ag Note If both AFR2 and AFR3 are activated AFR2 option has priority over AFR3 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port DO alternate function TIM1_BKIN 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D7 alternate function TIM1_CH4 DoclD14771 Rev 10 ky STM8S105xx Ordering information AFRS check only one option AFR6 check only one option AFR7 check only one option OPT3 watchdog WWDG_HALT check only one option WWDG_HW check only one option I
22. oo ee eect eee e teeter etna teeeeneeeeaeeenaey 88 Figure 36 Typ Vpp Voy Vpop 3 3 V high sink porte oo eee ener reer ene e tees eeneeneaeeeeay 89 Figure 37 Typical NRST Mu and Vip VS Von 4 temperatures 90 Figure 38 Typical NRST pull up resistance vs Vpp 4 temperatures o oo eee eens 91 Figure 39 Typical NRST pull up current vs Von 4 temperatures ooo eee eee ee tenses 91 Figure 40 Recommended reset pin protection oo cccecceceeeceeeeeecneceeeeeeeeeeeseceaeaaecaeeeeeeeeeeseesecseccaaeeeeeees 92 Figure 41 SPI timing diagram slave mode and CPHA 0 ou eeeceeeeeeeeeeeeeeeeeeneeeeeeeneeeeeesenaaeeeseenaeeees 94 Figure 42 SPI timing diagram slave mode and EE 94 Figure 43 SPI timing diagram master EE 95 Figure 44 Typical application with CC bus and timing diagram EE 96 Figure 45 ADC accuracy characteristics 0 ceceeeccceeeeeeeeeeeeneeeeeeeeaeeeeeeeaaaeeeeeeeaeeeeeeeaeeeeseeeseeeeeeeaas 100 Figure 46 Typical application with ADC cccccecceccceeeeeeeeececeeecaeeeeeeeeeesecseceaeaaeceeeeeeeeeeesecsecninaneesees 100 Figure 47 48 pin low profile quad flat package xt 104 6 127 DoclD14771 Rev 10 ky STM8S105xx List of figures Figure 48 44 pin low profile quad flat package o oo ee eee eeceeeeceeecee cee eeeeeeeeeteeceneaecaeeeeeeeeeeeeesecncaceeeeeeeees 106 Figure 49 32 pin low profile quad flat package 7 X 7 oeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeaeeeeeeenaeeeeeeeneeeeenenaaes 107 Figure 50
23. pe t D ky DoclD14771 Rev 10 25 127 Pinout and pin description STM8S105xx Type ce ST He wo N Kai N e gt Ki N A A wo a P N N Bi Ei N D N es CO a ER wo x Ei D N A a N CH N N N e gt N N Ki 26 127 Main function Default alternate Alternate after reset function function after remap option bit Timer 2 TIM3_ CH1 channel 3 AFR1 VO Ayalog input 12 Analog power supply Analog ground Port B7 Analog input 7 O Analog input 6 E Analog input 5 Gr Spa AFR6 Analog input 4 e sc AFR6 Analog input 3 TIM1_ ETR AFR5 2 O Analog input 2 TIM1_CH3N AFR5 2 Analog input 1 TIM1_CH2N AFR5 Analog input 0 TIM1_CH1N AFR5 O Analog input 8 x DoclD14771 Rev 10 ky STM8S105xx Pinout and pin description LQFP48 LQFP44 LQFP32 1 N BSS N N Kai TI 2 2 30 23 2 31 32 33 34 35 36 LA Eet 3 3 34 wo 3 l 4 PES SPI_ I O NSS 1 0 DoclD14771 Rev 10 Main function Default alternate Alternate after reset function function after remap option bit Analog input a SPI master slave select Timer 1 channel 1 UART2 synchronous clock Timer 1 channel 2 Timer 1 channel Timer 1 channel SPI clock O 3 fe ba S
24. 1 4 TIM4 PCKEN1 0 PCKEN2 A PCKEN2 0 4 6 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources Wait mode n this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset SG Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower SG Halt mode in this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset ky DoclD14771 Rev 10 15 127 Product overview STM8S105xx 4 7 4 8 4 9 16 127 Watchdog timers The watchdog system is based on two independent timers providing maximum security to
25. 10 3 12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization 100 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics 10 3 12 1 Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs FESD Functional electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard FTB A burst of fast transient voltage positive and negative is applied to Von and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 EMC design guide for STMicrocontrollers 10 3 12 2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalificati
26. 105xx Package information 11 5 32 lead UFQFPN package mechanical data Figure 51 32 lead ultra thin fine pitch quad flat no lead package 5 x 5 bp PIN 1 IDENTIFIER LASER MARKING gt B __ ZJo 100 c m lt q j SEATING QJo 080 c PLANE lele 100 ely A 0 100 c A B lt 0 0500 C 0 100 C A B 3 500 0 100 PIN 1 CORNER H AOB8_ME 1 Drawing is not to scale 2 All leads pads should be soldered to the PCB to improve the lead pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and solder this backside pad to PCB ground 4 Dimensions are in millimeters Table 56 32 lead ultra thin fine pitch quad flat no lead package mechanical data RE E 0 500 0 550 550 oam 600 omg 0197 om 0217 0 0236 0236 N om o b Io 0 250 0 300 0 0071 0 0098 0 0118 ky DoclD14771 Rev 10 111 127 Package information STM8S105xx 11 6 112 127 1 inches Min e Max fmin fye Je 4 850 5 000 5 150 0 1909 0 1969 0 2028 3 200 3 450 0 1260 a 0 1457 pe y p i bell ber Values in inches are converted from mm and rounded to 4 decimal digits 4 850 5 000 5 150 0 1909 0 1969 0 2028 1 SDIP32 package mechanical data Figure 52 32 lead s
27. 19 127 Ordering information STM8S105xx 120 127 EXTCLK check only one option 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN OPT5 crystal oscillator stabilization HSECNT check only one option 2048 HSE cycles 128 HSE cycles 8 HSE cycles 0 5 HSE cycles OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte check only one option Refer to the UM0560 STM8L S bootloader manual for more details Disable 00h Enable 55h Comments Supply operating range in the application Notes Date Signature DoclD14771 Rev 10 ky STM8S105xx STM8 development tools 14 14 1 14 2 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM68 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STic
28. 5 disable time Data output Slave mode valid time after enable edge Data output Master mode valid time after enable edge Data output Slave mode hold time after enable edge Master mode after enable edge 1 Values based on design simulation and or characterization results and not tested in SE 2 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z ky DoclD14771 Rev 10 93 127 Electrical characteristics STM8S105xx Figure 41 SPI timing diagram slave mode and CPHA 0 NSS input SU NSS Fa te SCKy gt th NSS _ CPHA 0 i of _f S CPOL 0 SCK Input OO ER V m ln O E ee See 2 EE E We Zen MISO TECOS tsu Sl 4 INPUT LG Ti S ths ai14134 Figure 42 SPI timing diagram slave mode and CPHA 4 NSS input Ss fi SU NSS lt gt te sck UE eech CPHA 1 a CPOL 0 d l x CPHA 1 i i o CPOL 1 l i i 7 a i z im d i ee SO gt e tee ISCH ab Wu th SO lt gt Ke SCK dis Ee MISO OUTPUT CC weer O wepour f as our LSB our me za vdla Wei INPUT j ai14135 1 Measurement points are made at CMOS levels 0 3 Vpp and 0 7 Vpp a 94 127 DoclD14771 R
29. 5xx 108 127 Table 54 32 pin low profile quad flat package mechanical data inches mm Je min Je e Je be we DESS a te e Set Feel Te ve Fa Fa Fee CC bel Fe bel Fe Sea Fe Tess SI po Il SI pe es C Jean oasis o o pe C C E a C E e bel 1 pe Values in inches are converted from mm and rounded to 4 decimal digits DoclD14771 Rev 10 ky STM8S105xx Package information 11 4 32 lead VFQFPN package mechanical data Figure 50 32 lead very thin fine pitch quad flat no lead package 5 x 5 Seating plane S Cl aaa c l4 aen A3 Pin 1 ID R 0 30 Bottom view 42_ME 1 There is an exposed die pad on the underside of the VFQFPN package It is recommended to connect and solder this backside pad to PCB ground 2 All leads pads should be soldered to the PCB to improve the lead pad solder joint life Table 55 32 lead very thin fine pitch quad flat no lead package mechanical data min be Je we e we 0 30 0 0071 0 0098 0 0118 5 15 0 1909 0 1969 0 2028 ky DoclD14771 Rev 10 109 127 Package information STM8S105xx inches ho e de 0 1260 D 0 1457 0 1909 0 1969 0 2028 Typ 0 0118 0 0157 0 0197 Values in inches are converted from mm and rounded to 4 decimal digits min Je we SES SESCH 1 110 127 DoclD14771 Rev 10 ky STM8S
30. Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFR7 DoclD14771 Rev 10 ky STM8S105xx Product overview 4 10 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver 16 bit up down and up down autoreload counter with 16 bit prescaler SG Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break 4 11 TIM2 TIM3 16 bit general purpose timers SG 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 Timers with 3 or 2 individually configurable capture compare channels PWM mode e e e SG interrupt sources 2 or 3 x input capture output compare 1 x overflow update 4 12 TIM4 8 bit basic timer
31. I RC osc 128 kHz Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 22 Total current consumption with code execution in run mode at Vpp 3 3 V fopu fmaster 16 MHz HSE crystal osc 16 MHz DoclD14771 Rev 10 63 127 Electrical characteristics STM8S105xx 64 127 L mode code executed from RAM Supply current in run mode code executed from Flash fopu faster 128 125 kHz fopu faster 128 15 625 kHz fopu faster 128 kHz fopu faster 16 MHz fopu faster 2 MHz fopu faster 128 125 kHz fopu faster 128 15 625 kHz DoclD14771 Rev 10 HSE user ext clock 16 MHz HSI RC osc 16 MHz HSE user ext clock 16 MHz HSI RC osc 16 MHz HSI RC osc 16 MHz 8 LSI RC osc 128 kHz HSE crystal osc 16 MHz HSE user ext clock 16 MHz HSI RC osc 16 MHz HSI RC osc 16 MHz 8 HSI RC osc 16 MHz HSI RC osc 16 MHz 8 STM8S105xx Electrical characteristics saloons i 128 kHz Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 10 3 2 2 Total current consumption in wait mode H a lt Table 23 Total current consumption in wait mode at Von D Supply l fopy fmaster 16 HSE crystal osc current in MHz 16 MH
32. Load 50 pF Input leakage current analog and digital Analog input leakage current Leakage current in adjacent I O 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data based on characterization results not tested in production Figure 24 Typical Vu and Vu VS Vpp 4 temperatures Vif Vin V ky DoclD14771 Rev 10 81 127 Electrical characteristics STM8S105xx 82 127 Figure 25 Typical pull up resistance vs Vpp 4 temperatures Pull up resistance kQ 25 3 3 5 4 45 5 5 5 6 Voo V Figure 26 Typical pull up current vs Vpp 4 temperatures Pull up current uA 1 The pull up is a pure resistor slope goes through 0 Table 39 Output driving current standard ports cae Output low level with four pins 1 07 sunk _ DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics p E ER Output low level with eight pins sunk Output high level with four pins sourced Output high level with eight pins sourced 1 Data based on characterization results not tested in production 1 Table 40 Output driving current true open drain ports Output low level with two pins sunk Data based on characterization results not tested in production Table 41 Output driving current high sink ports Output low level with four pins sunk O
33. N synch break detection break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support SPI Maximum speed 8 Mbit s fmaster 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin DoclD14771 Rev 10 19 127 Product overview STM8S105xx 4 14 3 20 127 PC DC master features Clock generation Start and stop generation SG DC slave features Programmable 12C address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz DoclD14771 Rev 10 STM8S105xx Pinout and pin description 5 Pinout and pin description Table 5 Legend abbreviations for pinout tables l Input O Output S Power supply Output HS High sink SSES sped O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset Port and control Input float floating wou weak pull up configuration Output T True open drain OD Open drain PP Push pull Reset sale Bol
34. PE5 SPI_LNSS 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented indicates an exclusive choice not a duplication of the function DoclD14771 Rev 10 3 alternate function remapping option If the same alternate function is shown twice it a STM8S105xx Pinout and pin description 1 2 T True open drain P buffer and protection diode to Vpp not implemented Figure 4 LQFP 44 pin pinout NRST OSCIN PA OSCOUT PA2 VSSIO_1 Vss VCAP VDD VDDIO_1 HS PA4 HS PAS HS PA6 fo RS S x l EI Zz E i al 2 al Haq 2 S S E E TNE a S 50 58 Dass l3a JC aa Si Io o Saiz ze22 80 EREEERS RECO see P2GGL DFE ESSLLSLILIEEL C zo e oe D ooOOoO oO mo o aooacataaoaoaan 44 43 42 41 40 39 38 37 36 35 34 H 33 32 31 30 29 28 27 26 ovVOAaAROAND 25 Ei 24 23 2 13 14 15 16 17 18 19 20 21 22 PB7 PB6 PB5 VDDA VSSA IN4 PB4 N2 PB2 N1 PB1 NO PBO AIN7 N6 N5 A AIN9 PE6 C_SCL A Ve We MM1 T IM1_CH1N TIM TIM PG1 PGO PC7 HS SPI_MISO
35. RH ADC analog watchdog control register high 0x00 540F ADC_AWCRL_ ADC analog watchdog control register low 0x00 5410 to Reserved area 1008 bytes 0x00 57FF 1 Depends on the previous reset source 2 Write only register CPU SWIM debug module interrupt controller registers Table 10 CPU SWIM debug module interrupt controller registers pee pen status DoclD14771 Rev 10 45 127 Memory and register map STM8S105xx 46 127 Address Register label Register name Reset status 0x00 7FOA ocr Condition code register 0x00 7FOB to Reserved area 85 bytes 0x00 7F5F 0x00 7F60 CFG_GCR Global configuration register 0x00 7F70 E ITC_SPR1 Interrupt software priority register 1 0x00 7F71 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F 0x00 7F90 el DM_BK1RE DM breakpoint 1 register extended OxFF 0x00 7F72 0x00 7F73 enn 7F74 oons 7F75 one 7F76 x00 77 TF77 one 7F91 DM_BK1RH DM breakpoint 1 register high byte DM_BK1RL DM breakpoint 1 register low byte 0x00 7F92 DoclD14771 Rev 10 ky STM8S105xx Memory and register map Address Register label Register name Reset status 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended OxFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0x00 7F96 DM_CR1 DM debug module
36. S Voo HSI RC osc fcpy 16 MHz long MA np YN NP H H wk m H u N Voo M aiS362 72 127 DoclD14771 Rev 10 d D STM8S105xx Electrical characteristics Figure 16 Typ Ippqwe1 VYS Vpp HSE user external clock fcpy 16 MHz bawn MA Nool 25383 Figure 17 Typ Ippqwe1 VS fcpu HSE user external clock Vpp 5 V lbowrynse MA 0 5 10 15 20 fepu MHz ailS3e4 DoclD14771 Rev 10 73 127 Electrical characteristics STM8S105xx Figure 18 Typ Ippwe1 VS Von HSI RC osc fcpy 16 MHz lpowenxsi MA Voo V 10 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T4 Table 32 HSE user external clock characteristics fuse ext User external clock source E frequency Vusen OSCIN input pin high level voltage Vuen OSCIN input pin low level voltage OSCIN input leakage current 1 Data based on characterization results not tested in production 74 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Figure 19 HSE external clocksource HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external co
37. SG 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source CPU clock SG interrupt source 1 x overflow update Table 4 TIM timer features Counter Prescaler Counting CAPCOM Complem i mode channels outputs Any integer from 1 to Up 4 3 65536 down Any power of 2 from Up 3 1 to 32768 Any power of 2 from Up 2 1 to 32768 ky DoclD14771 Rev 10 17 127 Timer synchronization chaining Product overview STM8S105xx Timer Counter Prescaler Counting CAPCOM Complem Timer synchronization Any power of 2 from 1 to 128 4 13 Analog to digital converter ADC1 The STM8S105xx products contain a 10 bit successive approximation A D converter ADC1 with up to 10 multiplexed input channels and the following main features Input voltage range 0 to Vppa Conversion time 14 clock cycles Single and continuous and buffered continuous conversion modes Buffer size n x 10 bits where n number of input channels Scan mode for single and continuous conversion of a sequence of channels Analog watchdog capability with programmable upper and lower thresholds Analog watchdog interrupt External trigger input Trigger from TIM1 TRGO End of conversion EOC interrupt e Note Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC_DRH ADC_DRL registers 4 14 Communication interfaces The foll
38. STM8S105xx access line block diagram 11 Flash memory organisation 14 LOQFP AG pIM PINOUL sisien iota aE E E E NEE engine aa 22 LQFP 44 pin pinout 02 ce cece eee eecececee cae ce ee cette ee eecaaeaaeceeeeeeeeeeesceaaaaeaeeeeeeeeeeeseesessecsueeeeeeees 23 LQFP VFQFPN UFQFPN 32 pin pinout ee ce eeeeeeeeeeeeeeeeeeeceeeeeeeeeeeeeeeseeeeesaeeseeeeeeseeeeseneeess 24 SDIP 32 piN PINOUT ceeded scvaliecnede cnc ctenacsdaesccuissaaensaetadececsenansadantaeedadeaetsedaneastiebadsnaedebcandevsdtuaedennaee te 25 Memor Map een EENEEEEEEEEEEEENEE SEENEN SEENEN EE ERENNERT 30 Supply current measurement conditions 56 Pin loading e ele te EE 57 Pin input volage EE 57 fep max VOISUS Vpp sisemisse a urie e SEENEN ENEE then A Ead 61 Extermnal capacitor Cep eeens aaea aa rE e Kenon KEE EEEa eaa aea aka Eaa Kaa Ena 62 Typ IppRun VS Vpop HSE user external clock fopy 16 MHZ oo eee 71 Typ lbprun YS fopu HSE user external clock Vpp DN ENEE 72 TYP Ippruny YS Vpop HSI RC osc fopy 16 MHZ eet estates aseneensanienenes 72 Figure 16 Typ Jona YS Vpop HSE user external clock fopy 16 MHZ oo eee 73 Figure 17 Typ Ippqwet VS fcpu HSE user external clock Von DN NENNEN 73 Figure 18 Typ ack vs Vpp HSI RC osc fopy 16 MHZ oo eee ete eer eee reer ene eseeeeeneeseeeeaees 74 Figure 19 ASE external CloCkSOUICE ses disieeciuieietenwli Anniina A REEE idan ions 75 Figure 20 HSE oscillator circuit diagram 76 Fi
39. Table 2 STM8S105xx access line features Updated part numbers in Table 2 STM8S105xx access line features USART renamed UART1 LINUART renamed UART2 Added Table 7 Pin to pin comparison of pin 7 to 12 in 32 pin access line devices Removed STM8S102xx and STM8S104xx root part numbers corresponding to devices without data EEPROM Updated STM8S103 pinout in Section 5 2 on page 29 Added low and medium density Flash memory categories Added Note 1 in Table 17 Current characteristics Updated Table 12 Option bytes Updated STM8S103 pinout in Section 5 2 on page 29 Updated number of High Sink I Os in pinout TSSOP20 pinout modified PD4 moved to pin 1 etc Added WFQFN20 package Updated Option bytes Added Memory and register map Removed STM8S103x products separate STM8S103 datasheet created Updated Electrical characteristics Added SDIP32 silhouette and package to Features and SDIP32 package mechanical data updated Pinout and pin description Updated Vpp range 2 95 V to 5 5 V on Features Amended name of package VQFPN32 DoclD14771 Rev 10 123 127 Revision history STM8S105xx 124 127 pen wen owe 10 Jun 2009 E 21 Apr 2010 i Added Table 5 on page 22 Updated Auto wakeup counter Updated pins 25 30 and 31 in Pinout and pin description Removed Table 7 Pin to pin comparison of pin 7 to 12 in 32 pin access line devices Added Table 14 Description of alternate function remapping bits
40. VDD VDD 47kQ 47kQ STM8S105xx 100 Q WMM SDA 100 Q IC bus START REPEATED START o a Lem i START eum p e ges Ce E SDa P lt Ee tr SDA ai be tguspa Cu STOP ai tsu STA STO lt gt th STA HF tW SCEL gt th SDA roy tw SCLH SCL PH Le HSC gt i tsu STO ai15385b 1 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Von 96 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics 10 3 11 10 bit ADC characteristics Subject to general operating conditions for Vpopa faster and T unless otherwise specified Table 45 ADC characteristics cke ken Jecke ADC clock frequency Vppa 2 95 to 5 5 V el ao MHz Positive reference voltage 2 75 Vppa 4 5 to 5 5 V 1 0 lt oO CH lt Wu el er a gt 1 V SSA 0 5 2 VAIN Conversion voltage range V SSA Devices with VREF external VReF VRer pins Cape Internal sample and hold capacitor ts Sampling time Le 4 MHz 0 75 fapc 6 MHz Wakeup time from standby D tcony Total conversion time fapc 4 MHz including sampling time Negative reference voltage CH 7 7 0 10 bit resolution Le 6 MHz 2 33 f Data guaranteed by design not tested in production 2 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external source The internal resistance of the analog source must allow t
41. WDG active 1 Reset generated on halt if WWDG active EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles DoclD14771 Rev 10 ky STM8S105xx Option bytes Option byte no OPT2 BL 7 0 Bootloader option byte For STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 STM8L S bootloader manual for more details For STM8L products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 bytes These option bytes control whether the bootloader is active or not For more details refer to the UM0560 STMB8L S bootloader manual for more details Table 14 Description of alternate function remapping bits 7 0 of OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate function 1 Port D4 alternate function
42. WDG_HW check only one option LSI_EN check only one option HSITRIM check only one option OPT4 wakeup PRSC check only one option CKAWUSEL check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1_NCC3 port B1 alternate function TIM1_CH2N port BO alternate function TIM1_CHI1N 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port B5 alternate function I2C_SDA port B4 alternate function 12C_SCL 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D4 alternate function BEEP No reset generated on halt if WWDG active Reset generated on halt if WWDG active WWDG activated by software WWDG activated by hardware IWDG activated by software IWDG activated by hardware LSI clock is not available as CPU clock source LSI clock is available as CPU clock source 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register for 16 MHz to 128 kHz prescaler for 8 MHz to 128 kHz prescaler for 4 MHz to 128 kHz prescaler 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU DoclD14771 Rev 10 1
43. a 4 ke a i UO ground SPI master out slave in SPI master in slave out Timer 1 break input 2c data GC clock Configurable clock output 27 127 Pinout and pin description STM8S105xx LQFP48 LQFP44 LQFP32 41 37 38 PD1 Main function Default alternate Alternate after reset function function after remap option bit Wd O Timer 3 TIM1_BKIN AFR3 CLK_CCO AFR2 channel 2 n O X SWIM data interface T O Timer 3 TIM2_CH3 channel 1 AFR1 Timer 2 ADC_ ETR channel 2 AFRO Timer 2 BEEP output AFR7 41 PD4 TIM2_ CH1 BEEP 44 PD7 TLI OR CH4 1 A pull up is applied to PF4 during the reset phase This pin is input floating after reset release I I I I a o o wo channel 1 2 UART2 data transmit O UART2 data receive O Top level interrupt TIM1_ CH4 AFR4 x 1x x 1x x 1x x 1x A EI 2 aIN12 is not selectable in ADC scan mode or with analog watchdog 3 In 44 pin package AIN9 cannot be used by ADC scan mode 4 In the open drain output column T defines a true open drain UO P buffer and protection diode to Von are not implemented 5 the PD1 pin is in input pull up during the reset phase and after internal reset release 5 1 1 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one o
44. acterized with all Os tied to Vss 10 3 2 7 Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T4 HSI internal RC fepy faster 16 MHz Table 31 Peripheral current consumption TIM1 supply current TIM2 supply current E 70 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics en ke kk ke see E ADC1 supply current when converting Data based on a differential lbp Measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential lbp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production Data based on a differential lbp Measurement between reset configuration and continuous A D conversions Not tested in production 10 3 2 8 Current consumption curves The following figures show typical current consumption measured with code executing in RAM Figure 13 Typ Ipp runy VS Vpp HSE user external clock fcopy 16 MHz Itoue MA a s250 ky DoclD14771 Rev 10 71 127 Electrical characteristics STM8S105xx Figure 14 Typ Ippiruny VS fcpu HSE user external clock Vpp 5 V loqnunsse MA 10 fepu MHz ai15381 Figure 15 Typ Ippyruny V
45. ax 82 5 mW 360 mW Thus Ppmax 443 mW T Jmax for LQFP32 can be calculated as follows using the thermal resistance O j Teen 75 C 59 C W x 464 mW 75 C 27 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 106 C In this case parts must be ordered at least with the temperature range suffix 6 DoclD14771 Rev 10 115 127 Ordering information STM8S105xx 13 13 1 116 127 Ordering information Figure 53 STM8S105xx access line ordering information scheme E le SE em S 10 K 4 6 C TR Product class Family type S Standard Sub family type 105 access line STM8S105x Pin count K 32 pins S 44 pins C 48 pins Program memory size 4 16 Kbytes 6 32 Kbytes Package type B SDIP T LQFP U VQFPN Temperature range 3 40 C to 125 C 6 40 C to 85 C Package pitch No character 0 5 mm C 0 8mm Packing No character Tray or tube TR Tape and reel 1 Fora list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST sales office nearest to you STM8S105 FASTROM microcontroller option list last update September 2010 Customer Address DoclD14771 Rev 10 ky STM8S105xx Ordering information Contact Cs DEE Reference FASTROM
46. cted the injection current must be limited externally to the lins Piny Value A positive injection is induced by Viy gt Vpp while a negative injection is induced by Vin lt Vsg For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected Negative injection disturbs the analog performance of the device See note in 2C interface characteristics When several inputs are submitted to a current injection the maximum Zu unn is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with Zlw un Maximum current injection on four I O port pins of the device Table 18 Thermal characteristics pone em Storage temperature range 65 to 150 ere Maximum junction temperature Operating conditions The device must be used in operating conditions that respect the parameters in the table below In addition full account must be taken of all physical capacitor characteristics and tolerances DoclD14771 Rev 10 59 127 Electrical characteristics STM8S105xx Table 19 General operating conditions fopy Internal CPU clock frequency Von Vpp_10 Standard operating voltage Cexz Capacitance of at 1 MHz external capacitor ESR of external capacitor ESL of external capacitor Power dissipation at 44 and 48 pin devices TA 85 C for suffix with output on eight 6or TA 125
47. cy with Ran lt 10 KQ Rams Vppa 3 3 V sesssssssssnsenissrssrnsrnssnnrnnnrnnrnsnrnnnnnnnnnrnnennne 99 4 127 DoclD14771 Rev 10 ky STM8S105xx List of tables Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 d Ee E WEE 101 EM etter geesde N EE aoa at 102 ESD absolute maximum ratings 103 Electrical sensitivities 103 48 pin low profile quad flat package mechanical data cccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeteees 104 44 pin low profile quad flat package mechanical data cccecceeeeeeeeeeeeeeceeeeeeeeeeeeeeteees 106 32 pin low profile quad flat package mechanical data cccceceeeceeceeseeceeeceeeeeeeeteeeeeseneees 123 32 lead very thin fine pitch quad flat no lead package mechanical data eeeee 111 32 lead ultra thin fine pitch quad flat no lead package mechanical data 00008 111 32 lead shrink plastic DIP 400 ml package mechanical data e i eceeeeeeenteeeeeeeneaes 112 Thermal characteristics ooo cssecssesssssssesssseeesecseessecsseesevsseessesssessnsssnssnessnssnsessesteseeseesees 114 Document revision history 123 DoclD14771 Rev 10 5 127 List of figures STM8S105xx List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15
48. d X pin state after internal reset release Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release ky DoclD14771 Rev 10 21 127 Pinout and pin description STM8S105xx 5 1 22 127 STM8S105 pinouts and pin description Figure 3 LQFP 48 pin pinout NRST OSCIN PA1 OSCOUT PA2 VSSIO_1 Vss VCAP VDD VDDIO_1 TIM3_CH1 TIM2_CH3 PA3 HS PA4 HS PA5 HS PA6 TIM1_BKIN CLK_CCO BEEP ADC_ETR TIM2_CH3 PD5 UART2_TX TIM2_CH1 C_SDA TIM3_CH2 TIM2_CH2 HS TIM3_CH1 HS SWIM HS TIM3_ HS CLK_CCO c_ScL PD7 TLI TIM1_CH4 PD6 UART2_RX PD4 HS PD3 HS PD2 PDI PDO PEO PEI PE2 48 47 46 45 44 43 42 41 40 39 38 e n oroark on Ei 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 T T SU PE3 TIM1_BKIN VYN N NUU o o o o Do io g o bo E OG now zt N AGGRHHVRDGLS antaadaagaaa fa S gt S6HF 5025 SS E ise Se Zz Z 2242222228 KEEN SEKR Aorsa OSES wre S JJ Ess EEE PG1 PGO PC7 HS SPI_MISO L PC6 Hs SPI_MOSI VDDIO 2 Vssio_2 PC5 HS SPI_SCK PC4 HS TIM1_CH4 PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 UART2_CK
49. e is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8
50. eeeeneeeeeeeeeeeeeteees 92 10 3 10 UC interface characteristics cecccssccesseessesssesssessstessesssessessseeseeen 95 10 3 11 10 bit ADC characteristics 0 0 0 0 ccccceeeeeceecceeceeeeeeeeeeeeeeeeeenneaeeeeeeeeeees 97 10 312 EMC characteristics lt c dveiseeiete eceidiscguivineecaeceeddeeiee aavaad eeteatieetes 100 11 Package information WE 104 11 1 48 pin LQFP package mechanical data cceccecceceeeeeeeeeeeeeeeeneaeeeeeeeeeeeteneeenenea 104 11 2 44 pin LQFP package mechanical data c c ccecceceeeeeeeeeeeeeeceeeaeeeeeeeeeeeeeteeeneaae 106 11 3 32 pin LQFP package mechanical data ccccecccececeeeeeeeeeeeeeeeeeeeeeeeeeeeteeestnaeeateees 107 11 4 32 lead VFQFPN package mechanical data ecceeeeeeeeeeeceeeeeeeenneeeeeeeneeeeeeeeaas 109 11 5 32 lead UFQFPN package mechanical data o oo eee eee eeeeeeeeeeeteeeeeeetaeeeeeee 111 11 6 SDIP32 package mechanical data ooo eeceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseeenaeeeeneeaaeees 112 12 Thermal characteristics sccccicsescasccisesnissnaeccsnivnsasunbacutancsecasesacuwbassansdenspcunnvssensanene 114 12 1 Reference document ou cccccescseseceesesecececeecececeeeeceeceeesesseaeaeaessaseseseaseseseseceeeeeeeseees 114 12 2 Selecting the product temperature range 115 13 Ordering information ME 116 13 1 STM8S105 FASTROM microcontroller option list cccececceeeeeeeeeeeteeeeentenaeees 116 14 STM8 development tools ssasasssssnnn
51. emperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T 25 C and T4 Tama given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 Typical values Unless otherwise specified typical data are based on T 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in the following figure Figure 8 Supply current measurement conditions 5Vor3 3V 4 m m VDDA VDDIO VSS VSSA Vssio MAMA DoclD14771 Rev 10 ky STM8S105xx Electrical charac
52. er TIM1 General purpose timers TIM2 and TIM3 Basic timer TIM4 SPI I 2c UART Window WDG Independent WDG ADC a 10 127 DoclD14771 Rev 10 STM8S105xx Block diagram 3 2 Block diagram Figure 1 STM8S105xx access line block diagram SN Reset block gt XTAL 1 16 MHz Clock controller Reset Ge Reset k RC int 16 MHz Detector POR BOR Wi RCint 128 kHz Clock to peripherals and core Window WDG STMB8 core ee gt Independent WDG Single wire Lt Debug SWIM 9 Up to 32 Kbytes debug interf lt gt program Flash Master slave autosynchro ae UART2 T gt LIN master m 1 Kbytes SPI emul lt gt data EEPROM 5 Ge 2c lt gt Up to 2 Kbyt 400 Kbit s I s p to ytes mA a T gt RAM ge bai H 8 Mbit s SPI lt D 5 gt Boot ROM 3 lt 16 bit advanced control Ce timer TIM1 SE 16 bit general purpose timers TIM2 TIM3 Up to 10 channels A e gt ADC1 lt gt gt 8 bit basic timer TIM4 1 2 4 kHz Beeper gt beep L AWU timer Up to 4 CAPCOM channels 3 complementary outputs Up to 5 CAPCOM a channels DoclD14771 Rev 10 11 127 Product overview STM8S105xx 4 4 1 4 2 12 127 Product overview
53. ev 10 STM8S105xx Electrical characteristics Figure 43 SPI timing diagram master mode High NSS input ott CPHA 0 f 2 CPOL 0 f i x CPHA 0 i D CPOL 1 ee Se ee Oe eem ee wm Topp i V 2 CPOL 0 N f Geisel N x CPHA 1 i i i d Hl CPOL 1 e EE ee S oe tw SCKH Leck ges GE DE vn MECH a thy h MOSI VE gt MEPR ai14136 1 Measurement points are made at CMOS levels 0 3 Vpp and 0 7 Vpp 10 3 10 C interface characteristics Table 44 E characteristics SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time ky DoclD14771 Rev 10 95 127 Electrical characteristics STM8S105xx Symbol Parameter START condition hold time Lues Repeated START condition setup time STOP condition setup time twsto sta STOP to START condition time bus free e Capacitive load for each bus line Nees must be at least 8 MHz to achieve max fast C speed 400kHZz 2 Data based on standard 1 C protocol requirement not tested in production 3 The maximum hold time of the start condition has only to be met if the interface does not stretch the low time The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Figure 44 Typical application with VC bus and timing diagram 1
54. f eight AFR alternate function remap option bits When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers 28 127 DoclD14771 Rev 10 ky STM8S105xx Pinout and pin description Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 ky DoclD14771 Rev 10 29 127 Memory and register map STM8S105xx 6 6 1 30 127 Memory and register map Memory map Figure 7 Memory map 0x00 0000 0x00 07FF 0x00 4000 0x00 43FF 0x00 4800 0x00 487F 0x00 5000 0x00 57FF 0x00 6000 0x00 67FF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 FFFF 0x01 0000 0x02 7FFF RAM 2 Kbytes A 512 bytes stack Reserved 1 Kbyte data EEPROM 0x00 4400 0x00 47FF Reserved Option bytes 0x00 4900 0x00 4FFF Reserved GPIO and periph reg 0x00 5800 0x00 SFFF Reserved 2 Kbytes boot ROM 0x00 6800 0x00 7EFF Reserved CPU SWIM debug ITC registers Flash program memory 16 to 32 Kbytes Reserved The following table lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case DoclD14771 Rev 10 a STM8S105xx Memory and register ma
55. g in data memory possible while executing code in program memory SG User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to the figure below The size of the UBC is programmable through the UBC option byte in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas Main program memory Up to 32 Kbytes minus UBC SG User specific boot code UBC Configurable up to 32 Kbytes DoclD14771 Rev 10 13 127 Product overview STM8S105xx 4 5 14 127 The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot
56. gh a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching SG Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext DoclD14771 Rev 10 ky STM8S105xx Product overview 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated Configurable main clock output CCO This outputs an external clock for use by the application Table 3 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers Peripheral Peripheral Peripheral Peripheral clock clock clock clock PCKEN1 7 TIM1 PCKEN1 3 UART2 PCKEN2 7 PCKEN2 3 PCKEN1 6 TIM3 PCKEN1 2 PCKEN2 6 PCKEN2 2 PCKEN1 5 TIM2 PCKEN1 1 PCKEN2 5 PCKENZ2 1 PCKEN
57. gure 21 Typical HSI accuracy at Vpp 5 V vs 5 temperatures oo eee cece settee etre ee etaeeteees 77 Figure 22 Typical HSI accuracy vs Vpp 4 temperatures 78 Figure 23 Typical LSI accuracy vs Vpp 4 temperatures 79 Figure 24 Typical Vu and Vu VS Vpp 4 temperatures nsssesnssnssenssisnnsinsnissnnsrinrnnsrnsrnnnrnnnnrnnerenet 81 Figure 25 Typical pull up resistance vs Vpp 4 temperatures ooo teeter etree ee tae ete 82 Figure 26 Typical pull up current vs Von 4 temperatures ooo eee tee ee ete ee teeter ta aeenaes 82 Figure 27 Typ Vo Vpp 5 V Standard ports oo eee cee e eee errr nee eene eter aeeetneee etna eeteaaeeaas 84 Figure 28 Typ Vo Vpp 3 3 V Standard ports ooo ee ee era eee eet a ae eeteeee teas eetaaaeeees 85 Figure 29 Typ VoL Mon 5 V true open drain ports oo eee eee tree ee eeeeeteeeeneeeeeetiaey 85 Figure 30 Typ VoL Mon 3 3 V true Open drain portS oo eee eee ere reer eee eteeeeeneeereeeeay 86 Figure 31 Typ Vo Vpp 5 V high sink ports oo ee eect errr nee eeee eterna eeteaee etna eeteaaeeaas 86 Figure 32 Typ Vo Vpp 3 3 V high Sink ports ooo eee ee eae renee eta ae ee teeee tee aeeetaaeeaes 87 Figure 33 Typ Mop Mou Vpop 5 V Standard ports oo cern ree ree eteeeteeeeneeneeriaey 87 Figure 34 Typ Vpop Von Vpop 3 3 V Standard ports oo eee eee crete renee tne eteeeeneeereeenaey 88 Figure 35 Typ Vpp Voy Vpop 5 V high sink Ports
58. he capacitance to reach its final voltage level within ts After the end of the sample time tg T oO CH oa oa E E T ge ch DoclD14771 Rev 10 97 127 Electrical characteristics STM8S105xx 98 127 changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming Table 46 ADC accuracy with Ran lt 10 KQ Vbpa 5 V Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Data based on characterisation results not tested in production ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current ky DoclD14771 Rev 10 STM8S105xx Electrical characteristics Any positive injection current within the limits specified for Ju ue AN Zu upmn in the HO port pin characteristics section does not affect the ADC accuracy Offset error Table 47 ADC accuracy with Ram lt 10 KQ Rain Vppa 3 3 V Gain error 7 Differential linearity error Integral linearity error 1 Data based on characterisation results not tested in production ADC accuracy vs negative injection current Injecti
59. he STM8S microcontroller family reference manual RM0016 All devices of the STM8S105xx access line provide the following benefits SG Reduced system cost Integrated true data EEPROM for up to 300 k write erase cycles High system integration level with internal clock oscillators watchdog and brown out reset Performance and robustness 16 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system Short development cycles Applications scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation and a wide choice of development tools 8 Product longevity Advanced core and peripherals made in a state of the art technology A family of products for applications with 2 95 to 5 5 V operating supply Table 2 STM8S105xx access line features STM8S105C4 STM8si105Ss6 STM8S105S4 STM8S105K6 STM8S105K4 44 44 32 STM8S105C6 Maximum number 38 of GPIOs Ext Interrupt pins 35 Timer CAPCOM channels Timer complementary outputs A D Converter 10 channels High sink I Os 16 Medium density Flash Program memory bytes Data EEPROM 1024 bytes RAM bytes 2K wo 3 a x 32K 2 DoclD14771 Rev 10 9 127 Description STM8S105xx Device STMm8s105C6 STM8S105C4 STM8S105S6 STM8S105S4 sTmss105K6 STM8S105K4 Peripheral set Advanced control tim
60. hrink plastic DIP 400 ml package TE E EI 32 17 76_ME Table 57 32 lead shrink plastic DIP 400 ml package mechanical data inches a EE SE e DoclD14771 Rev 10 ky STM8S105xx Package information inches ne Je fm e we E R 9 906 10 410 11 050 0 3900 0 4098 0 4350 2 540 3 048 3 810 0 1000 0 1200 0 1500 1 Values in inches are converted from mm and rounded to 4 decimal digits p 27 430 27 940 28 450 1 0799 1 1000 1 1201 DoclD14771 Rev 10 113 127 Thermal characteristics STM8S105xx 12 12 1 114 127 Thermal characteristics The maximum chip junction temperature Tj max Must never exceed the values given in Operating conditions The maximum chip junction temperature T Jmax in degrees Celsius may be calculated using the following equation Timax z James T Pomax 3 Oja Where Tamax is the maximum ambient temperature in C Oyj is the package junction to ambient thermal resistance in C W S Ppmax is the sum of Pintmax and Piiomax Pomax Pintmax i Promax Pintmax is the product of Ipp andVpp expressed in Watts This is the maximum chip internal power Promax represents the maximum power dissipation on output pinsWhere Pyomax 2 No ol 2 Vpp VoH y on taking into account the actual Vor loL and Vollen Of the I Os at low and high level in the application
61. ic interference EMl Emission tests conform to the IEC61967 2 standard for test software board layout and pin loading Table 49 EMI data General Monitored conditions frequency Semi Peak level Vpp 5V Ta 25 C LQFP48 package conforming to IEC61967 2 SAE EMI level Data based on characterization results not tested in production 130 MHz 1 10 3 12 4 Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 102 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics 10 3 12 5 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 50 ESD absolute maximum ratings Symbol Conditions Vesp HBm Electrostatic discharge Ty 25 C voltage Human body model conforming to JESD22 A114 Vespicpm Electrostatic discharge T 25 C conforming voltage Charge device to JESD22 C101 model 1 Data based on characterization
62. ion for STM8S105 microcontrollers table Option bytes added description of STM8L bootloader option bytes to the option byte description table DoclD14771 Rev 10 ky STM8S105xx Revision history pnw owe Added Unique ID Operating conditions added introductory text removed low power dissipation condition for T4 replaced Cgexrt by VCAP and added ESR and ESL data in table general operating conditions Total current consumption in halt mode replaced max value Of Ibp at 85 C from 20 pA to 25 pA for the condition Flash in powerdown mode HSI clock after wakeup in the table total current consumption in halt mode at Vpp 5 V Low power mode wakeup times added first condition 0 to 16 MHZ for the twu wr Parameter in the table wakeup times Internal clock sources and timing characteristics In the table HSI oscillator characteristics replaced min and max values of AC Ce factory calibrated parameter and removed footnote 4 concerning further characterization of results Functional EMS electromagnetic susceptibility IEC 1000 replaced with IEC 61000 Designing hardened software to avoid noise problems EC 1000 replaced with IEC 61000 Electromagnetic interference EMI SAE J 1752 3 replaced with IEC61967 2 Thermal characteristics Replaced the thermal resistance junction ambient temperature of LQFP32 7X7 mm from 59 C to 60 C in the thermal characteristics table Added 32 lead UFQFPN package mecha
63. lternate function is shown twice it indicates an exclusive choice not a duplication of the function 24 127 DoclD14771 Rev 10 d STM8S105xx Pinout and pin description Figure 6 SDIP 32 pin pinout ADC_ETR TIM2_CH2 PD3 HS BEEP TIM2_CH1 PD4 HS UART2_TX PD5 D 32 H PD2 HS TIM3_CH1 TIM2_CH3 31 H PD1 HS Swim 30 D PDO HS TIM3_CH2 TIM1_BKIN CLK_CCO UART2_RX PD6 4 29 PC7 HS SPI_MISO TIM1_CH4 TLI PD7 5 28 PC6 HS SPI_MOSI NRST 6 27 PC5 HS SPI_SCK OSCIN PA1 7 26 D PC4 HS TIM1_CH4 OSCOUT PA2 8 25 PC3 HS TIM1_CH3 HS Vss 9 24 PC2 HS TIM1_CH2 vcaP 10 23 PC1 HS TIM1_CH1 UART2_CK Vpp J 11 22 PES SPI_LNSS Vppio 12 21 H PBO AINO TIM1_CH1N AIN12 PF4 13 20 PB1 AIN1 TIM1_CH2N Vppa 14 19 D PB2 AIN2 TIM1_CH3N Vssa 15 18 PB3 AIN3 TIM1_ETR I2C_SDAJAIN5 PB5 16 17 PB4 AIN4 I2C_SCL 105_ai15057 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function LQFP48 LQFP44 LQFP32 e 6 Pin description for STM8S105 microcontrollers Main function Default alternate Alternate after reset function function after remap option bit Resonator crystal in ae Ed Port A2 Resonator crystal out pe pe p
64. mponents In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 33 HSE oscillator characteristics External high speed oscillator frequency c Recommended load capacitance 6 0 startup 1 6 stabilized 6 0 startup 1 2 stabilized IDD HSE HSE oscillator power C 20 pF consumption f 16 MHz osc 7 C 10 pF fosc 16 MHz Om Oscillator transconductance tsu HsE TT Startup time Vpp is stabilized Cis approximately equivalent to 2 x crystal Cload fo oO ko ky DoclD14771 Rev 10 75 127 Electrical characteristics STM8S105xx 2 small R value Refer to crystal manufacturer for more details 3 Data based on characterization results not tested in production The oscillator selection can be optimized in terms of supply current using a high quality resonator with 4 tsu HsE S the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 20 HSE oscillator circuit diagram fHSE to core Q Consum
65. n with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at anytime without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT
66. nesessseesrrrrrrnnseessrens 53 Table 15 Unique ID registers 96 bits c cceccscsecescncneeeeeeceeectedeccaneneddecneeneneeacenaeedeecnnseeedennesenedecnanenenesea 55 Table 16 Voltage characteristics 0 0 ec tert irre eee ne eee einer eet NAE EE eee naeee eee EE Enna 57 Table 17 Current CharactenistiCs sc seecesiiiee etd ioir eni SEENEN EE EEEE E 58 Table 18 Thermal characteristics 0 0 eee re ne ne eee teers e eta aeee eee naeee eee eaeeeeer ead 59 Table 19 General operating conditions 60 Table 20 Operating conditions at power Up POWer COWN 61 Table 21 Total current consumption with code execution in run mode at Vpp 5 Vo uu 62 Table 22 Total current consumption with code execution in run mode at Vpp 3 3 V ee 74 Table 23 Total current consumption in wait mode at Vpp 5 Vo cece eee eee etter ee eeee tener eeeeeeeeeeetes 65 Table 24 Total current consumption in wait mode at Vpp 3 3 V ssssssssssssissrssrnsrsrnnnrnsrnnrissrnnrnnrennrnnennnn 66 Table 25 Total current consumption in active halt mode at Vpp DN eee ee cece esse eter ener eneeeeeeeees 66 Table 26 Total current consumption in active halt mode at Vpp 3 3 Vo eee eee eter reneeeeeeeeeees 67 Table 27 Total current consumption in halt mode at Vpp DN ee eee ee eee re eee e renee ee eteeeeeetes 68 Table 28 Total current consumption in halt mode at Vpp 3 3 Voce eee eee errr ene ereeeneeeeeeeeeees 69 Table 29 Wakeup EE 69 Table 30 Total current consum
67. ng negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for li ue AND Zu upmn n HO port pin characteristics does not affect the ADC accuracy ky DoclD14771 Rev 10 99 127 Electrical characteristics STM8S105xx Figure 45 ADC accuracy characteristics 1022 h LSB IDE AL 7 1024 NO P OAD 4 1 2 3 4 5 6 7 02110221023 1024 VDD 4 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line E7 Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one E Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 46 Typical application with ADC VDD STM8 V R T 0 6 V e Was AINx l y 10 bit A D conversion EE CH HK YT IL An Losy Watya Cape
68. nical data Added STM8S105 FASTROM microcontroller option list 21 Sep 2010 10 Table 5 Legend abbreviations for pinout tables updated reset state removed HS T and Table 6 Pin description for STM8S105 microcontrollers added footnotes to the PF4 and PD1 pins Table 8 I O port hardware register map changed reset status of Px_IDR from 0x00 to 0xXX Table 9 General hardware register map Standardized all address and reset state values updated the reset state values of the RST_SR CLK_SWCR CLK_HSITRIMR CLK_SWIMCCR IWDG_KR UART2_DR and ADC_DRx registers replaced reserved address 0x00 5248 with the UART2_CR85 Figure 40 Recommended reset pin protection replaced 0 01 uF with 0 1 uF ky DoclD14771 Rev 10 125 127 Revision history STM8S105xx bas bee Updated Figure 44 Typical application with 12C bus and timing diagram 1 Updated footnote 1 in Table 46 ADC accuracy with RAIN lt 10 kQ VDDA 5 V and Table 47 ADC accuracy with RAIN lt 10 KQ RAIN VDDA 3 3 V STM8S105 FASTROM microcontroller option list removed bits 6 and 7 from OPT1 user boot code area UBC added disable to 00h and enable to 55h of OPTBL bootloader option byte Figure 50 32 lead very thin fine pitch quad flat no lead package 5 x 5 replaced note 1 and added note 2 126 127 DoclD14771 Rev 10 ky STM8S105xx 2 Please Read Carefully Information in this document is provided solely in connectio
69. nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnnm 121 14 1 Emulation and in circuit debugging tools 121 14 2 SoftWare e e E 121 d ENEE 122 14 2 2 C and assembly toolchain 122 14 3 Programming Tools i222 0000 122 15 R vision IStOTY isis vcsce cscs ces acces dec ee ee 123 ky DoclD14771 Rev 10 3 127 List of tables STM8S105xx List of tables Table el 1 Table 2 STM8S105xx access line features oo eee eeceeee terete eee ee tees eee taeeeeeeeeeeeeeetaeeeeeeeaeeeeeeeaaes 9 Table 3 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers 15 Table 4 TIM timer TICE 17 Table 5 Legend abbreviations for pinout tables 21 Table 6 Pin description for STM8S105 microcontrollers ccccccceeececcececeeeeseeseseseeaeseaeaeaeaeeeseseeesees 25 Table 7 Flash Data EEPROM and RAM boundary addresses 106 Table 8 I O port hardware register map ccccceceeeeeeeeeececeeeeeee eee eeee cece aaaecaeeeeeeeeeeeeesececeneeeeeeeeeereeeeees 111 Table 9 General hardware register map oo eect eee ett ee eee ene e ee ee tae ee eee tne eee ee eeee eee neeeeeetnaeeeeeetaa 34 Table 10 CPU SWIM debug module interrupt controller registers cceeeeeeeeeeeceeceeeeeeeeeeeeeentenaeees 112 Table 11 Ile Ter e e e BEE 48 Table 12 Option bytes 55 Table 13 Option byte description gu ENNER A EEE REE 51 Table 14 Description of alternate function remapping bits 7 0 Of OPT2 ssesssssseesene
70. ntrol the building of your application directly from an easy to use graphical interface Available toolchains include Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com SG Raisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD14771 Rev 10 ky STM8S105xx Revision history 15 Revision history Table 59 Document revision history ben ee 05 Jun 2008 Initial release 23 Jun 2008 12 Aug 2008 17 Sep 2008 05 Feb 2009 27 Feb 2009 d 12 May 2009 Corrected number of high sink outputs to 9 in I Os on Features Updated part numbers in
71. on tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as Corrupted program counter Unexpected reset Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring See application note AN1015 Software techniques for improving microcontroller EMC performance Table 48 EMS data Symbol Parameter Conditions Voltage limits to be applied on any VO pin to Vbo 5 V Ta 25 C fmaster 16 MHz induce a functional conforming to IEC 1000 4 2 disturbance Ver Fast transient voltage _ ee 8 burst limits to be applied Vonc 9 V Tas 25 C faster 16 AIA through 100 pF on Vpp MHz conforming to IEC 1000 4 4 ky DoclD14771 Rev 10 101 127 Electrical characteristics STM8S105xx and Maes pins to induce a functional disturbance Data obtained with HSI clock configuration after applying HW recommendations described in AN2860 EMC guidelines for STM8S microcontrollers 10 3 12 3 Electromagnet
72. option in the same port 2 Refer to pinout description 54 127 DoclD14771 Rev 10 ky STM8S105xx Unique ID 9 Unique ID The devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited SG For use as serial numbers For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memory SG To activate secure boot processes Table 15 Unique ID registers 96 bits Unique ID bits 7 e 5b ff bp 2 p p 0x48CD y co ordinate U_ID 7 0 Ox48CE op the wafer U_ID 15 8 Ox48CF Y co ordinate U_ID 23 16 ox48D0 on the wafer U_ID 31 24 0x48D1 U_ID 39 32 0x48D2 U_ID 47 40 0x48D3 U_ID 55 48 Lot number ky DoclD14771 Rev 10 55 127 Electrical characteristics STM8S105xx 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 56 127 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient t
73. or is achieved connecting an external capacitor Cer to the Vcap pin Cer is specified in the Operating conditions section Care should be taken to limit the series inductance to less than 15 nH Figure 12 External capacitor Cy c ESL Ges EES ESR 1 ESR is the equivalent series resistance and ESL is the equivalent inductance 10 3 2 Supply current characteristics The current consumption is measured as described in Pin input voltage 10 3 2 1 Total current consumption in run mode Table 21 Total current consumption with code execution in run mode at Von 5 V Ipp RuN Supply fopu fMASTER HSE crystal osc current in run 16 MHz 16 MHz mode code executed from RAM HSE user ext clock 16 MHz HSI RC osc 16 MHz fopy fmaster 128 HSE user ext clock 125 kHz 16 MHz HSI RC osc 16 MHz 62 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics cke ones i fe fopu fmaster 128 15 625 kHz fopu fMASTER 128 kHz fopu fMASTER current in run mode code A0 MEE executed fromFlash fopu waeren 2 MHz fopu fmaster 128 125 kHz fopu fmaster 128 15 625 kHz fopu fMASTER 128 kHz HSI RC osc 16 MH3z 8 LSI RC osc 128 kHz HSE crystal osc 16 MHz HSE user ext clock 16 MHz HSI RC osc 16 MHz HSI RC osc 16 MHz 8 HSI RC osc 16 MHz HSI RC osc 16 MHz 8 LS
74. otection ROP AAh Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 to 1 defined as UBC memory write protected 0x02 Page 0 to 3 defined as UBC memory write protected 0x03 Page 0 to 4 defined as UBC memory write protected Ox3E Pages 0 to 63 defined as UBC memory write protected Other values Reserved Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 AFR 7 0 Refer to following table for the alternate function remapping decriptions of bits 7 2 OPT3 HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register ky DoclD14771 Rev 10 51 127 Option bytes STM8S105xx 52 127 OPT4 OPT5 LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG_HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG_HALT Window watchdog reset on halt 0 No reset generated on halt if W
75. owing communication interfaces are implemented e UART2 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode LIN2 1 master slave capability SPI Full and half duplex 8 Mbit s PC Up to 400 Kbit s 4 14 1 UART2 Main features One Mbit s full duplex GC SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder 18 127 DoclD14771 Rev 10 ky STM8S105xx Product overview 4 14 2 LIN master mode LIN slave mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fepy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver SG Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fepy 16 LIN master mode Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame LIN slave mode Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated initial clock deviation 15 Synch delimiter checking 11 bit LI
76. p Table 7 Flash Data EEPROM and RAM boundary addresses Size bytes Start address End address Flash program memory 0x00 8000 0x00 FFFF Data EEPROM 1024 0x00 4000 0x00 43FF 6 2 Register map 6 2 1 UO port hardware register map Table 8 I O port hardware register map ee status 0x00 5002 5002 0x00 5003 5003 0x00 5008 5004 0x00 5006 5006 ky DoclD14771 Rev 10 31 127 0x00 5007 5007 0x00 5008 5008 0x00 5009 5009 0x00 5005 PB_ODR Port B data output latch register Memory and register map STM8S105xx 32 127 a status x00 5006 500C x00 5000 500D 000 5011 5011 0x00 5012 5012 0x00 5013 5013 0x00 5015 5015 0x00 5016 5016 0x00 5017 5017 0x00 5014 PE_ODR Port E data output latch register 000 5018 501A PF_IDR Port F input pin value register PF_DDR Port F data direction register PF_CR1 Port F control register 1 DoclD14771 Rev 10 ky 0x00 5018 501B x00 5016 501C STM8S105xx Memory and register map ll aoe E status sl Im Port F control Port F contol register2 2 om 0x00 5020 5020 0x00 5021 5021 0x00 5022 5022 0x00 5024 5024 0x00 5025 5025 0x00 5028 5026 0x00 5023 PH_ODR Port H data output latch register 0x00 5028 502A 0x00 5028 502B 0x00 5020 502C DoclD14771 Rev 10 33 127 Memory and register map STM8S105xx 6 2 2 General hardware register map Table 9 General hardware register map 0x00 5050 to Reserved a
77. program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation Data i Data memory area 1 Kbyte EEPROM memory Option bytes Programmable area f UBC area f from 1 Kbyte Remains write protected during IAP 2 first pages up to 32 Kbytes 1 page steps Medium density Flash program memory up to 32 Kbytes Program memory area Write access possible for IAP Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock faster coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching Clock sources can be changed safely on the fly in run mode throu
78. ption control Rm im o i CL1 io ae G SE Resonator E a ahs L Resonator Oz OSCOUT STM8 HSE oscillator critical g equation 2 2 Qmerit 2 xM x fuse Rm 2C0 C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification Du C12 C Grounded external capacitance Im 77 merit 10 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and T4 High speed internal RC oscillator HSI Table 34 HSI oscillator characteristics to Jee 76 127 DoclD14771 Rev 10 STM8S105xx Electrical characteristics cke ks k kk ACCy4g Accuracy of HSI User trimmed with 1 07 oscillator CLK_HSITRIMR register for given Vpp and T4 conditions Accuracy of HSI Vbp 5V Ta 25 C on f fro oscillator factory Gelee Vop 5V 25 CS Tas 2 0 2 0 85 C 2 95 lt Vpps 5 5 V 40 C 3 0 3 0 lt T 125 C LGuusn HSI oscillator 1 0 us wakeup time including calibration Ibps HSI oscillator power 170 250 pA consumption Refer to application note 2 Guaranteed by design not tested in production 3 Data based on characterization results not tested in production Figure 21 Typical HSI accuracy at Vpp 5 V vs 5 temperatures be max
79. ption and timing in forced reset state ooo eceeeeeeenteeeeeeentteeeeeeeaes 103 Table 31 Peripheral Current consumption 70 Table 32 HSE user external clock characteristics eccceeeeeee eee eeeneeeeeeeneeeeeeeneeeeeeeeaeeeeeeenaeeeeeeeaas 74 Table 33 HSE oscillator characteristicS cencscenisciniiriiini ee irene EAEE EAE EEE EE 75 Table 34 HSI oscillator characteristics 76 Table 35 LSI oscillator CharacteristiCS 00 0 ccc ee eters ee nee eee eee seen EEEE 78 Table 36 RAM and hardware registers 79 Table 37 Flash program memory data EEPROM Memory 79 Table 38 I O static Characteristics 0 0 erent ete eerie ee eee nents teee eee teeeeerenieeeeernieeeeeread 80 Table 39 Output driving current Standard ports 0 0 e eect eee eetne teers eaters eeeaaeeeeeeeaeeeeeeeaeeeeeeeaaas 82 Table 40 Output driving current true open drain Ports oo eee eeceeee eee eeee eee eeeecaeeeeeeeaeeeeeeenaeeeeeeeaes 83 Table 41 Output driving current high SINK ports oo eee eee eee e ee tee ee etree eee ee teat ee eeeeaeeeeeeenaeeeeeeenaas 83 Table 42 NRST pin characteristics ccceccccceceeceeeeeeeeeeceeaeeeeeeeeeeeeesecaaaaaecaeeeeeeeeeeseceecceesaeeeeeeeeeeeeeteeed 89 EIERE EEN 92 Table 44 EE 95 Table 45 ADC characteristics qcccccrcsnenicriarnitini kitini n E AREARE EEE 97 Table 46 ADC accuracy with Ran lt 10 KQ Vppa DN sssessssssssssnssnsnnnssnsrinsrnnrnnrissnnnrrnrnnsrnnrnnsrnennsennnent 98 Table 47 ADC accura
80. r between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming DoclD14771 Rev 10 ky STM8S105xx Product overview 4 3 4 4 SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers R W to RAM and peripheral registers in real time SG R W access to all resources by stalling the CPU Breakpoints on all program memory instructions software breakpoints Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on 6 vectors including TLI SG Trap and reset interrupts Flash program and data EEPROM memory Up to 32 Kbytes of Flash program single voltage Flash memory SG Up to 1 Kbytes true data EEPROM Read while write Writin
81. rea 10 bytes 0x00 5059 0x00 505A Flash FLASH_CR1 Flash control register 1 0x00 505B FLASH_CR2 Flash control register 2 0x00 505C FLASH_NCR2_ Flash complementary control register 2 0x00 505D FLASH FPR Flash protection register 0x00 505E FLASH _NFPR Flash complementary OxFF protection register 0x00 505F FLASH _IAPSR Flash in application 0x00 programming status register 0x00 5060 to Reserved area 2 bytes 0x00 5061 0x00 5062 Flash FLASH _PUKR Flash program memory unprotection register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 5065 to Reserved area 59 bytes 0x00 509F 0x00 50A0 ITC EST CH External interrupt control register 1 0x00 50A1 EXTI_CR2 External interrupt control register 2 34 127 DoclD14771 Rev 10 ky STM8S105xx Memory and register map 0x00 50A2 to Reserved area 17 bytes 0x00 50B2 0x00 50B3 ast RST_SR Reset status register Oxxx 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50C6 CLK_CKDIVR _ Clock divider register 0x00 50C7 CLK_PCKENR71 Peripheral clock gating register OxFF 1 0x00 50C8 CLK_CSSR Clock security system register 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 50CA CLK_PCKENR2 Peripheral clock gating register OxFF 2 0x00 50CB CLK_CANCCR CAN clock control register 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming 0x00 register 0x00 50CD CLK_SWIMCCR
82. results not tested in production 10 3 12 6 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 51 Electrical sensitivities Static latch up class Ta Ta 0 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard ky DoclD14771 Rev 10 103 127 Package information STM8S105xx 11 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 11 1 48 pin LQFP package mechanical data Figure 47 48 pin low profile quad flat package 7 x 7 D1 D3 37 24 48 Pin 1 identification 1 12 e 5B_ME Table 52 48 pin low profile quad flat package mechanical da
83. rk shown in the following figure protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in the I O port pin characteristics section Otherwise the reset is not taken into account internally DoclD14771 Rev 10 91 127 Electrical characteristics STM8S105xx Figure 40 Recommended reset pin protection VDD STM8 RPU External reset S NRST Filter Internal reset circuit _ 0 1 UF optional 10 3 9 SPI serial peripheral interface Unless otherwise specified the parameters given in the following table are derived from tests performed under ambient temperature fmaster frequency and Vpp supply voltage conditions taster 1 faster Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 43 SPI characteristics frequency c SCK t t SCK SPI clock rise and fall time tisck twsckH SCK high and Master mode 1 low time t w SCKL 1 Data input Master mode setup time Data input Slave mode setup time 92 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics es Fe Fe fan ar Data input hold Master mode time Data input hold Slave mode Luso Um Data output Slave mode 3x access time tMASTER tuis So M3 Data output Slave mode 2
84. s 34 6 2 3 CPU SWIM debug module interrupt controller registers 45 7 Interrupt vector MAPPING ccccscccccssdcsctccensecasacsssdssosecensetccescoetsccsesecnacasstsscdssnesensesecend 48 8 Option YS cise cece see EE 50 9 Unigue EE 55 10 Electrical characteristics uuaugseee egeee deeg EEGEN 56 10 1 Parameter Conditions eegene uertasabatiedaanvadd eddi 56 10 1 1 Minimum and maximum values ccccececececeeeeteeeeceeceeeeeteeeeeeeeees 56 ABER 56 2 127 DoclD14771 Rev 10 ky STM8S105xx Contents 10 1 3 Kee Hl 56 10 1 4 Typical Current CONSUMPTION 56 10 1 5 Loading Capacitor ssscrcnreiniiiinr aii oA EE ER 57 10 1 6 Pin input voltage 57 10 2 Absolute maximum ratings 57 10 3 Operating conditons arssinat aN ARANNA 59 10 3 1 VCAP external capacitor 2 0 cccccceeeeeceeeeeeceeeeeeeeeeeteetececnneeeeeeeeeeeeey 62 10 3 2 Supply current characteristics ccccececeeceeeceeceeeeeeeeeeeseesecneeeeeeeeees 62 10 3 3 External clock sources and timing characteristics 74 10 3 4 Internal clock sources and timing characteristics eee 76 10 3 5 Memory cCharacteristicS 79 10 3 6 I O port pin characteristics cecceeceeeceeeccecceeeeeeeeeeeeecseeaaeeeeeeeeeeeees 80 10 3 7 Typical output level curves ooo ccceecceeeeeeeecceeeceeeeeeeeeeeeeceenanaeeeeeeereeey 84 10 3 8 Reset pin characteristics A 89 10 3 9 SPI serial peripheral interface ccccccecceceeeeeeeeeee
85. s register 1 0x00 TIM1_SR2 TIM1 status register 2 0x00 TIM1_EGR TIM1 event generation register TIM1_CCMR1_ TIM1 capture compare mode 0x00 register 1 TIM1_CCMR2_ TIM1 capture compare mode 0x00 register 2 TIM1_CCMR3_ TIM1 capture compare mode 0x00 register 3 TIM1_CCMR4_ TIM1 capture compare mode 0x00 register 4 TIM1_CCER1 TIM1 capture compare enable 0x00 register 1 TIM1_CCER2 TIM1 capture compare enable 0x00 register 2 ky DoclD14771 Rev 10 39 127 0x00 5252 TIM1_SMCR TIM1 slave mode control 0x00 register 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 Memory and register map STM8S105xx 0x00 526C 0x00 526D TIM1_CCRIiL TIM1 capture compare 0x00 register 1 low TIM1_CCR2H_ TIM1 capture compare 0x00 register 2 high TIM1_CCR2L TIM1 capture compare 0x00 register 2 low TIM1_CCR3H TIM1 capture compare 0x00 register 3 high TIM1_CCR3L TIM1 capture compare 0x00 register 3 low TIM1_CCR4H TIM1 capture compare 0x00 register 4 high TIM1_CCR4L TIM1 capture compare register 4 low 0x00 5270 to Reserved area 147 bytes 0x00 52FF 0x00 5300 TIM2_CR1 TIM2 control register 1 40 127 DoclD14771 Rev 10 ky 0x00 5262 TIM1_ARRH TIM1 auto reload register high 0x00 5263 TIM1_ARRL TIM1 auto reload register low 0x00 5264 TIM1_RCR TIM1 repetition counter 0x00 register 0x00 5265 TIM1_CCR1H TIM1 capture compare 0x00 regis
86. seneeeeeeseeeaaeeeeeeeaeeeeseenaaeees 15 4 7 Watchdog timers sccccsrsiiiniiiieriniaiii eeeeeutieeceetuiaeseeeuuideeecetiaaeeeeetinedcoutisaceeeiaeece 16 4 8 Auto wakeup Reen 16 CHE E 16 4 10 TIM1 16 bit advanced Control timer cceceece cece cee ce cece eee eececeaeeeeeeeeeeeeeteetentaaaeess 17 4 11 TIM2 TIM3 16 bit general purpose timers 2 0 0 eececeee ee eeeeeeeceeeceeeeeeeeeeteessenteeaeeees 17 4 12 TIM4 8 bit basic timer ooo ee e eee cece eeeeeeeee cece eee ee eee ee cee eaaeeeeeeeeeeeeeeeeseceaeaaeaeeeseeeeeeeneeeeaes 17 4 13 Analog to digital converter ADC1 ooo ecient eee ttee eee tnieee eee tiieeeeeetaeeeeeenneeeeerene 18 4 14 Communication interfaces ccccccecceccececeeeeeeeeeeeeecaeeeeeeeeeeseeeeceacaaeeeeeeeeeeeeeseeeeenaees 18 4 14 11 ARTZ cies nite dises etic nile iin ae ea a 18 RE TT WEE 19 ANAS PC E 20 5 Pinout and pin description cwssssssicceccccecececensscsscnsestssssseccesesecceeceecsnnandesencssesssesecesnoes 21 5 1 STM8S105 pinouts and pin description 22 5 1 1 Alternate function remapping ecceccececeeeeeeeeeeeeaeceeeeeeeeeteeeeeeeaed 28 6 Memory and register Map sssseeeeeeeeeeeeeeeeeeeeeeeeeeeeseseneeneeeeeeeeeeeeeeeneeeeeeeeeeeees 30 6 MOMOry Map ME 30 6 2 Register MAP EE 31 6 2 1 I O port hardware register map ccccccecceeeeeeeeeeecceeeeeeeeeeeeeteeeseenaees 31 6 2 2 General hardware register Map eceeeeeeeeeeeeeeeeeeeeeeeeeeenaeeeseeenaee
87. ta inches a E 0 050 0 0020 0 0059 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 Ma 0 0079 8 800 9 000 9 200 0 3465 0 3543 0 3622 Cam 1 350 1 400 1 450 0 0531 0 0551 0 0571 104 127 DoclD14771 Rev 10 ky STM8S105xx Package information inches penes ne Je fm e we et Pl 0 500 0 0197 0 450 0 600 0 750 0 0177 0 0236 0 0295 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14771 Rev 10 105 127 Package information STM8S105xx 11 2 106 127 44 pin LQFP package mechanical data Figure 48 44 pin low profile quad flat package D1 D3 A 34 22 E f r E3 E1 E 44 Pin 1 identification 4 OI c ah 4Y_ME Table 53 44 pin low profile quad flat package mechanical data inches E C a o fe e DoclD14771 Rev 10 el 7 STM8S105xx Package information 11 3 inches incre ne Je fm we we SESCH RSA 1 Values in inches are converted from mm and rounded to 4 decimal digits 32 pin LQFP package mechanical data Figure 49 32 pin low profile quad flat package 7 x 7 fe gt D1 D3 A 24 174 T S Je A b i ASS E3 E1 E LES 32 ASS b Pin 1 identification 1 8 C Be e 5V_ME DoclD14771 Rev 10 107 127 Package information STM8S10
88. ter 1 high STM8S105xx Memory and register map ve kk kee ka 0x00 5305 TIM2_CCMR1_ TIM2 capture compare mode 0x00 register 1 0x00 5306 TIM2_CCMR2_ TIM2 capture compare mode 0x00 register 2 0x00 5307 TIM2_CCMR3_ TIM2 capture compare mode 0x00 register 3 0x00 5308 TIM2_CCER1 TIM2 capture compare enable 0x00 register 1 TIM2 capture compare enable 0x00 register 2 E E 0x00 530D TIM2_ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2_ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2_ CCR1H TIM2 capture compare 0x00 register 1 high 0x00 5310 TIM2_ CCRIiL TIM2 capture compare register 1 low ky DoclD14771 Rev 10 41 127 Memory and register map STM8S105xx 0x00 5311 TIM2_CCR2H TIM2 capture compare reg 2 0x00 0x00 5312 TIM2_ CCR2L TIM2 capture compare register 2 low 0x00 5313 TIM2_CCR3H TIM2 capture compare register 3 high 0x00 5314 TIM2_ CCR3L TIM2 capture compare register 3 low 0x00 5315 to Reserved area 11 bytes 0x00 531F 0x00 5320 TIM3 TIM3_CR1 TIM3 control register 1 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 5325 TIM3_CCMR1_ TIM3 capture compare mode 0x00 register 1 0x00 5326 TIM3_CCMR2_ TIM3 capture compare mode 0x00 register 2 0x00 5327 TIM3_CCER1 TIM3 capture compare enable 0x00
89. teristics 10 1 5 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure Figure 9 Pin loading conditions STM8 PIN 50pF tt 10 1 6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure Figure 10 Pin input voltage STM8 PIN 10 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 16 Voltage characteristics ee Input voltage on true open drain pins PE1 PE2 ky DoclD14771 Rev 10 57 127 Electrical characteristics STM8S105xx 58 127 Seed fas ft Variations between different power pins ET Vssx Vssl Variations between all the different ground pins je Electrostatic discharge voltage see Absolute maximum ratings electrical sensitivity A power Vpp Nope Vppa and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 lins Pin Must never be exceeded This is implicitly insured if Vu maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the lins Piny Val
90. the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 KHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter SG Used for auto wakeup from active halt mode SG Clock source Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
91. ue A positive injection is induced by Viy gt Vpp while a negative injection is induced by Vin lt Vsg For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected Table 17 Current characteristics en kee ki ke Lesser Ek Total current out of Vss ground lines sink 2 e EE EE Zle Total output current sourced sum of all UO and control 200 pins for devices with two Vppio pins Total output current sourced sum of all I O and control 100 pins for devices with one Vppio pin Total output current sunk sum of all I O and control pins for devices with two Vgsio pins Total output current sunk sum of all I O and control pins for devices with one Vggio pin 3 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics 10 3 por er lINJ PIN 9 Injected current on NRST pin teg a Injected current on OSCIN pin Injected current on any other pin ZliNu PIN i Total injected current sum of all I O and control pins Data based on characterization results not tested in production All power Vpp Nope Vppa and ground Vss Vssio Vssa pins must always be connected to the external supply 3 10 pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppio Vssio pins 4 lins Pin Must never be exceeded This is implicitly insured if Vu maximum is respected If Vin maximum cannot be respe
92. utput low level with eight pins sunk Output low level with four pins sunk Output high level with four pins ljo 10 mA sourced Vpp 3 3V DoclD14771 Rev 10 83 127 Electrical characteristics STM8S105xx Ess EE Output high level with eight pins sourced Output high level with four pins sourced Data based on characterization results not tested in production 10 3 7 Typical output level curves The following figures show typical output level curves measured with output on a single pin Figure 27 Typ Vo Vpp 5 V standard ports lo mA 84 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Figure 28 Typ Vo Vpp 3 3 V standard ports lo mA Figure 29 Typ Vo Vpp 5 V true open drain ports lo mA DoclD14771 Rev 10 85 127 Electrical characteristics STM8S105xx Figure 30 Typ VoL Vpp 3 3 V true open drain ports Va V lo mA Figure 31 Typ Vo Vpp 5 V high sink ports la mA 86 127 DoclD14771 Rev 10 STM8S105xx Electrical characteristics Figure 32 Typ Vo Vpp 3 3 V high sink ports lo mA Figure 33 Typ Vpp Von Vpp 5 V standard ports Vo Vou V ky DoclD14771 Rev 10 87 127 Electrical characteristics STM8S105xx Figure 34 Typ Vbo Von Vpp 3 3
93. wakeup times Table 29 Wakeup times Data based on characterization results not tested in production 0 to 16 MHz WW Wakeup time from wait mode to run mode Wakeup time active halt mode to run mode Wakeup time active halt mode to run mode Wakeup time active halt mode to run mode Wakeup time active halt mode to run mode Wakeup time from halt mode to run fopu fmaster 16 MHz MVR voltage Flash in operating regulator 5 mode on MVR voltage Flash in regulator on power down model MVR voltage Flash in operating regulator 5 of mode MVR voltage Flash in regulator off power down model Flash in power down model DoclD14771 Rev 10 ae 1 0 2 0 69 127 Electrical characteristics STM8S105xx be Fe i WE E E e Data guaranteed by design not tested in production 2 twurwel 2 X master 7 X 1 fopu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register Configured by the AHALT bit in the FLASH_CR1 register Plus 1 LSI clock depending on synchronization 10 3 2 6 Total current consumption and timing in forced reset state Table 30 Total current consumption and timing in forced reset state I SE current in reset state tRESETBL Reset pin release to vector fetch Data guaranteed by design not tested in production Char
94. y the AHALT bit in the FLASH_CR1 register Table 26 Total current Eege in active halt mode at Vpp 3 3 V i Power down HSE crystal mode osc 16 MHz LSI RC osc 128 kHz Operating LSI RC osc mode 128 kHz Power down mode Symbol Parameter Conditions 2 lboan Supply l Operating HSE crystal current in mode OSC active halt mode 16 MHz LSI RC osc 200 320 128 kHz ky DoclD14771 Rev 10 67 127 Electrical characteristics STM8S105xx Power down HSE crystal LSI RC osc 128 kHz Operating LSI RC osc mode 128 kHz Power down mode Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH_CR1 register 10 3 2 4 Total current consumption in halt mode Table 27 Total current consumption in halt mode at Von 5 V Parameter Conditions Supply current Flash in operating mode HSI in halt mode clock after wakeup Flash in powerdown mode HSI clock after wakeup Data based on characterization results not tested in production 68 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Table 28 Total current consumption in halt mode at Vpp 3 3 V Parameter Supply current in halt mode 1 Conditions Flash in operating mode HSI clock after wakeup Flash in powerdown mode HSI clock after wakeup 10 3 2 5 Low power mode
95. z wait mode HSE user ext clock 16 MHz HSI RC osc 16 MHz fopy fuaster 128 HSI RC osc 125 kHz 16 MHz fopy fuaster 128 HSI RC osc 15 625 kHz 16 Ms fopy fmaster 128 LSI RC osc Sie 128 kHz 0 Data based on characterization results not tested in production 2 D WFI Default clock configuration measured with all peripherals off ky DoclD14771 Rev 10 65 127 Electrical characteristics STM8S105xx Table 24 Total current consumption in wait mode at Vpp 3 3 V Supply fcpu fmaster 16 HSE crystal osc current in MHz 16 MHz wait mode HSE user ext clock 16 MHz HSI RC osc 16 MHz fopy fuaster 128 HSI RC osc 125 kHz 16 MHz fepu fmaster 128 HSI RC osc 15 625 kHz 16 MHZz 8 fopu fMasteR LSI RC osc 128 kHz 128 kHz 1 2 Data based on characterization results not tested in production Default clock configuration measured with all peripherals off 10 3 2 3 Total current consumption in active halt mode Table 25 Total current consumption in active halt mode at Vpp 5 V i Flash mode Clock source 2 Supply Operating HSE crystal current in mode OSC active halt mod 16 MHz 66 127 DoclD14771 Rev 10 ky STM8S105xx Electrical characteristics Symbol conditions 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured b

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