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SH7751R Solution Engine TM (MS7751RSE01) User`s Manual

Contents

1. 1 3 4 5 7 8 PCI CONNECTORS m SV 12V 12V 12V CNs jy TRST m TRST 23 A7 25 D6 Bl py TRST OA 23 A4 25 D6 21 B6 23 A6 25 D6 TCK B2 aav 2 21 B6 23 A2 25 D6 TCK B2 12y 2 GND TMs TMS 21 C6 23 A7 25 C6 B3 GND TMs 43 21 C6 23 A4 25 C6 21 B6 23 A6 TDO B4 tor 4 m TDI 21 86 23 7 25 6 21 B6 23 A2 TDO B4 A4 21 B6 23 A4 25 C6 BS 5V 5V LAS o BS 5V 5V AS 2 B6 INTA 046 m PCI INTB 10 B2 15 E2 23 A6 25 A6 B6 INTA amp 046 10 B2 15 E2 23 A2 25 A6 10 B2 15 E223 A725 A6 PCI INTCE INTBH INTCH m PCI INTD 10 82 15 2 23 6 25 6 10 B2 15 E223 A425 A6 PCLINTD m 7 INTB4 INTC 10 B2 15 E2 21 D2 23 A2 25 A6 10 2 15 2 21 92 23 7 25 6 PCLINTA BS INTD HAS 10 B2 15 E223 A425 A6 PCI INTB m 8 INTD 8 23 EA PRSNT1 0 23 F
2. 1 2 3 4 5 6 7 A_A 25 0 8A5 D 31 0 Tiga A16 36 CN1 GND A16 A Al7 106 18 37 17 S E3 CKIO m CKIO A18 A_A19 107 3 A A20 38 5 GND A20 A21 108 51 4 A22 39 A DI DO 22 A_A23 109 A_D2 5 A_A24 40 A_D3 D2 A24 A25 110 55 A D4 6 4 41 GND A DS A D6 7 pe S CS A DACKO m 42 DACKO A D7 im 8 qua 5 78 S C8 ADACK1 DACK1 3 GND 8 C6 13 D2 DREQO DREQO e 113 ADS 9 DE 44 A 79 8 C6 13 D2 DREQI DREQI D8 8 5 8 7 13 86 CS 6 0 GND D9 Rana cael 14 DIO 10 A_CSO 45 A DI 80 8 5 8 7 13 83 CS 6 0 a GND D10 CS0 AG us Hesi D12 pi C2 46 Cs 81 5 A_CS3 16 A D14 12 pa A_CS4 47 DIS 82 Dis 685 117 GND CS6 48 GND ER 118 A DI6 49 GND AUDIT 84 pi E
3. SV 33V SVSB 33VSB 5V sv 5 SVSB U19 LA 23 17 24 3 24 7 25 2 U19 U19 U19 LA23 KBCLK UH m 20 E2 M20 PWG 26 05 vcc A4 LB E E LA22 UP m KBDATA 20 D2 A3 12 s TIL 618 Pe 52 24 8 LA21 MSCLK MSCLK 20 E2 INIT INIT 10 82 16 D7 A2 OTH OTH ora oT LA20 12 m MSDATA 20 E2 cpurst 020 m CPURST 10 B2 16 D7 vcc A1 66 b N 9 KBINH 16 KBINH 27 E2 IGNNEJ O IGNNE 10 B2 16 D7 vcc 14 H20 LA18 INTR a INTR 10 82 16 D7 GN GN GND GND LAI7 13 m USBP0 20 82 NMI 10 C2 16 D7 vCC 3A1 cB G19 omg 4 7 SA 19 0 24 A3 24 A7 25 B2 USBP0 m USBP0 20 B2 A20MJ A20M 10 C2 16 D7 _3 0 9 AV 336 SA19 USBP1 E22 m USBP1 20 C2 SA18 USBP1 13 m USBP1 20 C2 RSM RSTJ OKS m RSM RST 16 E7 26 B5 p 6 E e 2 Avr C 2 AD HI8 gt gt gt SA17 OVCRI a OVCR 20 04 SMIJ a SMI 16 F4 glee mS al 12 MS lt 118 e PIS Rosy SA16
4. 1 2 3 5 6 7 8 SYSTEM BUS 3 3V lt gt 3 3V END A101 2834945 ONDA 1018 21 28 34 39 45 3 3V 7 18 31 42 A A 5 0 13 42 A D 3I 0 13 A2 SN abords _ 36 0 8 5 13 83 13 86 1A5 4C46A3 AD5 0 051 V A4 4 A7 5 B3 6 E3 7 A4 11 C2 3110 047 1 7 4 4 6 CS 6 0 U57 47 A1 Y 47 Bi 2 A_D31 4B4 EXTCSO m 47 yi 2 2 2 2 2 3 A_D30 4B4 EXTCSI m 46 42 3 5 A_D29 44 A3 ys 5 A4 Y4 A4 B4 28 A4 ya n ME D27 G A6 B6 5 _ 26 G HD74ALVCHIG244T AT _ 25 HD74ALVCHIG244T 051 8 12 057 Yl Yl 2 Ya G 484 EXTCS6 m 2 2 A3 DIR 1 B7 6 A2 BS m 38 A3 ys 11H m A BS 13 B6 A4 Y4 HD74ALVCH16245T 1 B7 6 C5 RD 37 A4 y4 2 a ARD 13 B3 U47 G 3 A D23 806 HD74ALVCHIG244T 2 B2 14 A_D22 HD74ALVCHIG244T 051 16 VATG EA 057 A_WEI3 0 13 83 13 86 Ad E D20 WE3 36 Ty a vi MEC A 019 WE2 35 ay 55 A6 20 18 WEL 33 A4 Y4 A7 MEO 32 1A4 Y4 ds 23 A 016 G 2 HD74ALVCHIG244T G HD74ALVCHIG244T 051 DIR 057 1 yi 9
5. PAGE 4 1 2 3 4 5 8 SDRAM 1 A4 4 A7 6 E3 7 A4 8 A4 11 C2 D 31 0 Ce j C 2 2 7 M3 M4 MS M6 15 20 por 59 D31 15 20 A13 55 D23 15 20 53 D15 15 20 53 D7 14 21 2 pos 50 D30 A14 2 12 50 D22 A14 21 an 50 D14 A14 21 2 50 D6 A13 35 ai pos 5 D29 A13 35 Au pos 47 D21 A13 35 A pos 47 D13 A13 35 ay pos 47 05 12 2215 pos 4 D28 A12 22 rg 4 D20 12 2 pos 4 D12 A12 331810 pos 4 D4 All 34 027 34 ag LL D19 A11 34 pos LL D11 All 34 LL D3 A10 33 8 D26 A10 33 L 018 10 33 D10 A10 33 s poz 8 D2 A9 32 7 pon D25 A9 32 a7 poi 5 D17 A9 32 7 01 D9 A9 32 7 Dol D1 8 31 poo 2 D24 AS 31 poo 2 D16 AS 31 DQO D8 8 31 Doo DO
6. 1 2 3 4 5 6 7 12V 12V 12V 12V 5V 25 SD 7 0 15 EA 24 A7 25 A2 SD 7 0 15 EA 24 A3 25 A2 CN10 SA I9 0 16 B2 4 A7 25 B2 CN SA 19 0 16 82 24 25 2 Bl GND VOCHCK IOCHK 16 2 24 7 25 4 Bl GND VOCHCK 16 2 24 43 25 4 15 E724 A5 RST_DRV m B2 RESETDRV 507 15 E724 A2 RST DRV m B2 RESETDRV SD7 asy SD6 asy 06 15 7 24 5 25 2 1809 B4 05 15 7 24 2 25 2 IRQ9 m 05 BS sy SD4 BS sy SD4 15 D724 BSQS CA DREQ2 m DRQ2 SD3 15 D724 B22S CA DREQ2 w B6 Sp3 7 qw SD2 BT 02 16 C2 24 B5 25 B4 NOWS m BS Lows SD 16 C2 24 B2 25 B4 NOWS 8 ows 501 B9 2V spo SD0 4 B GND IOCHRDY m IOCHRDY 16 C2 24 B7 25 B4 510 GND IOCHRDY m IOCHRDY 16 C2 24 B3 25 B4 16 D224 BS25 BA SMEMW SMEMW AEN 16 D2 24 B7 16 D224 B225 BA SMEMW LSMEMW AEN m AEN 16 D2 24 B3 16 D224 B525 BA SMEMR 2 SMEMR SA19 16 D224 B225 BA SMEMR Bl2 JSMEMR SA19 16 D2 24 B5 25 B2 IOW 3 SA18 16 D2 24 B2 25 B2 IOW BI ow SA18 16 D2 24 B5 25 B2 IOR m Bl4 ior SA17 16 D2 24 B2 25 B2 IOR m 4 on SA17 15 7 24 5 DACK3 m 5 DACK3 SA16 I15 E724 B m BIS DACK3 SA16 15 D724 BS
7. 1 3 4 6 7 PC CARD I O PORT 3 3V 33V 11 C4 P_D 15 0 CN18 CN1S 11 A4 25 0 1 CNI7 x 2 av 42 sy 35 xp 1 3 43 pkAkyprpe 36 opus 4 44 DRAKUPTDI P Dii 37 115 SH RXD m wposcpn 45 prpamesour 38 pp 105 SH TXD m 6 46 WAKEUP PTDS P 39 105 SH SCK m e 7 sckoiscri 47 ys P 40 pi mpuscerz 3 11 D4 P P DIS 4 D15 49 TxDI SCPT2 49 PTGO P_CE2 42 oe 10 sckuscers 50 11 D4 P_OE P_VS1 43 VS1 1 Vss 51 PTG2 P IORD 44 RFU IORD e 12 vs 52 ncs A9 P IOWR 45 Rrusowrs 13 IRO4PTH4 53 prea PAT 46 a 14 yrusiApTRG 54 prcs AB 18 us 15 pre 55 pres Ald P A19 48 16 Tcrcer 56 11 D4 WE WE P_A20 49 A20 Vss 5 Vss 11 E4 P RDY READY IREQ PA 50 n 13 v 53 11 C7 11 F4 12 B3 CARD_VCC Vee 11 C7 11 F4 12 B2 CARD_VCC 51 12 E7 PORTO x 19 PrcpiNTO e Tavs 11 D7 12 B3 CARD VPP 11D7 12 B2 CARD VPP 52 vpp2 12 E7 PORTI 20 60 avs 22 53 an 12 E7 PORT2 m 21 prczen 61 P A25 54 an 12 E7 PORT3 m 22 prczen 62 PSA24 55 12 D7 PORT4 m 23 prcapmra 63 25 5
8. 16 44 KBDATA 16 A4 KBCLK m 16 44 MSDATA 16 A4 MSCLK m 2 3 4 5 sV U7 FLI CN6 1 GND 00138 9 1112 1 ve 2 7 BLM31P500SPT 2 IN OUT2 4 DATA 3 6 UTE 3 IN2 OUT1 at 22 27 DATA 1 227 2 4 ac 8 SEAT 4 Y 9 02 s OT KS GND TPS2014D 5 z 5 Ve rg 2 5 EA nF DATA 9 57 7 GND GND S gt DATA AS muss GND UB1112C D1 GND Q 5y US rer 1 oursL8 9 e 1112 2 7 BLM31P500SPT 1 Do Not Stuff 9 IN OUT2 ales rcis RAS 3 6 es EE n R28 Ms S ud a 1 2 le 40 EN oco OT ss R 0 al 5 OF s TPS2014D E as rg 48 gt a leo ow Sah EE xN SN i GND GND a _ R16 R 27 t Ri7 R 27 t t r R25 t R26 2 1 2 a a a a 356 OT qd OTT ES ES ASI gd 9 dp x a a mm gt e lez pipe 54 11 DA a SV 5 Le e o N a eS 2 rd xU 025 1 n 1 OVCR 16 B4 HD74LVCOST 3 3V 14 GND 7 sv 14 a gt BLMG3IP500SPT 5 Le BLM31PS00SPT i CNS 9
9. A 25 18 CS 6 0 INPUT ROMSEL DBG INPUT CSOEN CS6EN INPUT PCE OUTPUT 5 CSO Area FLCE OUTPUT TADPCS OUTPUT ECSO OUTPUT ECS1 OUTPUT CS2 Area OUTPUT 5 CS6 Area SWCS OUTPUT EDCS OUTPUT BCRCS OUTPUT ECS6 OUTPUT BEA BEB OUTPUT 5 BUS control BEGIN TABLE A 25 18 CS 6 0 CSOEN DBG ROMSEL CS6EN gt EPCE FLCE TADPCS ECSO ECS1 PC CS SWCS LEDCS BCRCS ECS6 BEA EB R T L B Bn ne ne ne ne ne ne S M 5 E F D E E C S E C E 5 AAAAAAAA 0 D S 6 pes due OQ UW DOR C 2 5 22222211 SCCSSSS E B E E C C S S C C S E 5 54321098 6543210 N G L N E E S 0 1 5 S S S 6 A B CSO Area B OQOxxxxxx 0 9 X gt 21 40 50 0 O0 ls B QlIxxxxxxt 5 205 dy OR 07 05 07 05 1 B 1111110 0 0 0 x gt 0 0 0 1 0 0 0 0 0 0 1 0 B QO xxxxxx 1111110 0 0 1 x gt 0 1 0 B Oltxxxxxx B ITILITOQ U 0 gt d 0 0 0 0 0 2 B TIYLITITOU 0 04 205 904 04 12220 05 004 504 07 3X B ITITIITQU Q 4 gt 9 1 04 0 B OTxxxxxx 054 gt 15 20
10. 74148 INTO an lt INT1 id SIN 2N EONO NI3 CN GSNO C INT4 4N AON gt IRLO SIN ES NsN A1N INT6 6N AON O 3 BNOR2 INT7 IRL1 NT Qm 9 50 2 Ew IRL2 74148 INT8 aN INT9 i NO 2N EOND lt INT11 IRL3 4 O 5N AINO SINE 6N A2N O INT15 ACN C ENCODER IRL Encoder irl enc SLOT_IRQ 8 1 ILCRA 15 0 ILCRB 15 0 SIRQ 3 0 ILCRC 15 0 INTA INTC INTD ILCRD 15 0 NMI INTR ILCRE 15 0 INPUT SLOT_IRQJ8 1 INIT INPUT ILCRA 15 0 CPURST ILCRB 15 0 lt IGNNE lt A20M INPUT PC_SIRQI3 0 ILCRF 15 0 INPUT ILCRC 15 0 TIRQ 15 0 INPUT INTB INPUT INTC INPUT INTD ILE RDI15 0 INPUT NH NMI INPUT To INTR input ILCRE 15 0 level sel4 SLOT 8 INA OUT 15 0 b IRQA 15 0 SLOT IRQ7 c INB 810 1806 JJNc SLOT IRQ5 JJNp TCRAT5 01 15 0 level_sel4 SLOT_IRQ4 INA OUT 15 0 D IRQB 15 0 SLOT_IRQ3 INB SLOT IRQ2 INC Neil SLOT_IRQ1 IND TCRBT5 01 15 0 level_sel4 PC_SIRQ3 OUT 15 0 D lt IRQC 15 0 PC_SIRQ2 A INB SIRQ1 INC PC_SIRQO ILCRC 15 0 SEL 15 0 level_sel4 INTA
11. Go Go G2 G2 Ko o2 P2 B2 i NC NC NC ND ND NC NC NC NC ND ND NC NC 1 2 3 4 5 7 10 11 12 13 14 15 16 17 18 19 20 5V 59 11 Bus Controller Setting SH7751R bus controller has 21 registers Set the set values to each of 21 registers by using user programs when using various kinds of Solution Engine hardware For the bus controller setting refer to monitor program source START SRC of sample software on the attached CD ROM 60 12 SH 7751R CPU Bus Interface Table12 1 lists the pin assignment of the SH7751R CPU bus interface CN20 SH7751R bus signal data bus address bus control signal is output to CPU bus interface connector directly These signals can be used for tracing SH7751R signal to the emulator Connector Model Name WR 120PB VF 1 JAE Table12 1 Pin assignment of SH7751R CPU bus interface CN20 10 2 PAS i 4 DAS GND _ 0 GND A6 AT 1 AS A9 AIO O Au 12 gt A2 A3 A4 AS GND GND A6 9 10 19 RSTOUT 7 1 14 17 oo 61 13 Usage of Monitor Program 13 1 Usage of Monitor Program 1 How to Connect the Host System Connect the serial port of the host system to CN2 of the Solution Engine via a RS 232C cross cable After completion of serial connection start com
12. 1 4 5 7 8 3 3V 3 3V 3 3V 3 3V U35 U35 U35 B D 3L0 7 5 9 7 10 4 035 H TCK 10K 10 4 1021 537 1044 3 B_D6 DATA1 199 m SLOT IRQI 8 D8 CONF DONE CONF DONE 10 E2 1022 38 CONFIG 074 CONFIG 10 E2 DATA2 0 m SLOT IRQ2 8 D8 CEO 1023 32 VCCINTA 5 DATA3 H m SLOT IRQ3 8 08 4 TDO_10K 49 LED 7 0 10 05 MSELI DATA4 112 m SLOT IRQ4 8 D8 vccioo 1024 4 LED MSELO 7 DATAS 113 m SLOT IRQS 8 C8 e 1025 42 LED6 1045 78 5 114 m SLOT IRQ6 8 C8 CLKUSR 7 m PCL INTA 15 2 21 02 23 2 23 7 25 6 1026 LEDS 1046 79 B_D4 vecios 5 4 100 8 m PCI INTB 15 E223 A423 A625 A6 1027 4 LEDA 1047 90 B_D3 DATA7 m SLOT IRQ7 8 C8 101 5 m PCLINTC 15 2 23 2 23 7 25 6 vccio2 45 1048 91 B_D2 1066 m SLOT IRO8 8 8 102 10 m PCL INTD 15 2 23 4 23 6 25 6 1028 46 LED3 1049 82 BD 1067 118 SIROO 11 A6 11 E2 RDY Busy H 1029 47 LED2 1050 83 B 1068 5 PC SIRO1 11 A6 11 E2 103 2 1030 38 LED1 GNDINTS 84 9 1069 20 PC SIRO2 11 A6 11 E2 104 13 1031 49 LEDO GNDIO4 35 B A 23 0 4 2 7 3 9 5 1070 121 m PC SIRO3 11 A6 11 E2 INIT DONE 14 GNDIO2 59 1051 6 DEV CLR 0122 RESET 3 A7 15 1032 5 1052 87 123 GNDINTO 16 9 52 1053 88 5 DED_IN2 124 m STATUSI VAS 105 27 a INIT 16 D7 16
13. gt lt 44 68 Ku 173 23 20 32 68 88 36 51 3048 7 62 12 7 5 D BeceM 918 76 cV K 1533 315 1 4455 46 e gt 9822 re I gt LLL lt 806 znr sn at g 5999916555011 gt le eee 9201999962 NS N Qe LZN2 04 Er 00 0922 24 ZW i e t B B B M Q ZZNI b 00 409LOZZN e nS t 5 i VEND H 4 Ea na id B SE e belies 58 fe E same
14. M1543C SCD PVT USB connector CN7 Top CNO Bottom CN1 U2 SP211E Us U4 05 E SP2TTECA SP2ITECA SH7751R I O connector 0018 CN19 0018 z gt AM79C973A SH7751R CPU bus Interface i Lr ea s SH7751R E10A connector C41 U9 CBTD3384 IDEM U10 CBTD3384 U13 M uPD45128841 CN8 Ul PCI Slot 1 CBTD3384 HD6417751R CY2308SC 1 For EPM ETE U14 EPM7128ATC 100 7 CBTD3384 M5 HAD279949 uPD45128841 000000000000000000000000000000 000000000000000000000000000000 00000000000000000000000000000 Expansion slot U15 CBTD3384 CN18 Port yF HO C 5 0V PCI slot 16bit general purpose I PCI Slot 2 switchO Z For OSC2 SH7751R For FCT3805 SW5 SW4 CN 17 CARD 16bit general SLOT urpose Switch1 U28 U29 30 U31 LVC245A LVC245A LVC245A LVC245A MR SHPC 01 U20 021 022 023 LVC244A LVC244A LVC244ALV
15. 18 SI BESET 1 R62 2 R 10K PERR m PCLPERR 14 02 RESET SH RESET 2 7 3 7 9 a SH 105 SERR 0128 PCI SERR 14 D2 HD6417751RF240 om SH MRESET 1 5 SH7751R 3 7 R 10K 123 1 R3S 2 3 TA m SH INTA 1 D7 SH IDSEL 102 PCIGNTS 0114 m PCI GNT4 15 2 25 7 PCIGNT3 OLS m PCLGNT3 23 B725 B7 PCIGNT2 0116 m PCI GNT2 23 425 7 0126 m PCLGNTI 21 D225 B7 117 PCIREQ4 PCI REQ4 IS E225 A7 PCIREQ3 OHS MD10 3 C4 pCIREQ2 0121 m MD9 3 04 PCIREQI 0127 m PCLREQI 25 47 HD6417751RF240 SH7751R 1 7 7 27 2000 14 39 PAGE 1 1 2 3 4 6 7 8 VCC 3 3V 012 vec vec vec CND 201 m SH NMI 26 85 vppo 239 vsso 240 14 _
16. Connector Model Name DM11351 Z3 Figure 7 7 25 pin D sub parallel connector CN4 4l 7 2 5 Keyboard Mouse controller 1 keyboard KBC register map Table7 7 lists a register map of a keyboard controller KBC Base address initial value of the keyboard controller register is h 60 Set the configuration data as section 7 2 2 controller Table 7 7 keyboard controller KBC register map Read Write Address 2 Register Name Description Register Name Description h 00000060 DBBOUT DBBOUT Clear Data h 00000064 STATUS STATUS Set Command 2 Keyboard Mouse interface connector CN5 pin assignment Figure7 8 shows pin assignments and functions of a keyboard mouse interface connector CN5 Mouse connector pin assignment PinNo Sima ro Reserved Connecter Model Name MH11061 D2 ro Pin No 6 Top Mouse Board side Reserved Figure7 8 Keyboard mouse interface connector CN5 42 7 2 6 RTC controller 1 Register map Table7 8 lists the register map of RTC controller Base address initial value of RTC register address is h 70 Base address initial value of RTC register address cannot be changed Table7 8 Register map of RTC controller h 00000070 Address Register h 00000071 Table 7 8 Register map of RTC controller h 00 Seconds _hOE hFF GeneralpurposeRAM 43 7 2 7 Floppy disk controller Register
17. GND 10 HD74ALVCHIG244T ACCS G0 8 7 13 3 13 6 HD74LVC244AT Us2 1 AA 2 ics 056 yi eta y gt 2 2 2 e a v2 7 e244 3 2 5 2 E3 SLOT_CKIO m 26 a4 ya 23 m ACKIO 13 2 ya 3 4 46 HD74ALVCHIG244T HD74LVC244AT GND 1 2834 39 45 33V 33V 33V 33 33V 33V 33V 33V 33V 33V 33V 33V sliz li ali aliz slig glie ol Be Beg Be OTT OTT OTT OTT OTT OTT OTT OTT OTT OTTA a DC uut uu OT La Tal or ali Or mo GND GND GND GND GND GND GND GND GND GND GND GND 7 27 2000 14 39 8 1 2 3 6 5 B D 3L0 7 A5 10 C4 10 A6 9 4A277A3 107B6 A 23 0 g 9 Qis A 1 9 B_D31 z 1 di 18 Q14 28 B_D30 sws 045 17 26 1 516 P yi 18 B Dis aie 0121 24 B 028 4202008 1P30 4
18. 33V 33V s 33V 33V u 33V 33V 33V 33V A4 A4 A4 A4 N s AS 26 n AS 26 AS 26 b wales a sthas yl 55 2 25 55 alee Sa 2 55 25 95 oli A3 24 ay erm OTT 74 1An oT gl 24 a ST tt OTT 24 ay ops 2 23 449 2 23 a 9 A2 23 A0 9 2 23 a 9 csi s S GND x S GN GND GN GN csi S GN ooo or 33V 33V 33V 33V 33V 33V Pe me 33V 33V m o cas 8 o cas OWE sie 6 4 8 9 pom 81 e Sz 2 pow 51 55 315 9 pow 415 OT 32 oT aE OTH STIS ODE B NROP 38 eer 48 E Es Sa uu CLK CLK CLK CLK 37 37 CKE 37 CKE 37 CKE uPD45128841 GND GND uPD45128841 GND GND uPD45128841 uPD45128841 GND GND 3 3V 1 3 9 14 27 43 49 3 3V31 3 9 14 27 43 49 3 3V 1 3 9 14 27 43 49 3 3V 1 3 9 14 27 43 49 GND 6 12728 41 46 52 54 GND56 12 28 41 46 52 54 GND 6 12 28 41 46 52 54 GND 6 12728 41 46 52 54 1 A7 4 C4 6 A3 CS 6 0 1 B7 6 D5 RAS m e e 1 B7 6 C5 RD m e 1 7 4 2 6 5 RDWR m 1 B7 6 D5 DQM3 m 1 B7 6 D5 DQM m 1 B7 6 D5 DOMI m 1 7 6 5 DQMO 2 E3 SD_CKIO1 m 2 E3 SD CKIOO m CKE 7 27 2000_14 39 5 1 2 TADP64 SH4 1 A5 4 A5 4 C4 5 B3 7 A2 8 A2 11 A2 1 A7 4 C4 5 D2 8 A6 1 B7 7 B6 8 B6 11 D2 1 A7 4 E5 7 A6 8 B6 11 E2 1 A4 4 A7 5 B3
19. Apis 44 14 E3I5 D221 D223 D2 PC BEl B44 Apis A44 PADIS PAD14 45 ADM aav A45 4 845 ADM aav LA4 46 GND AD13 46 146 3 46 PADIS 2 B4 apn A47 2 BJ ADD A47 PADII B48 GND 248 PAD10 B48 GND AS e GND Apo 449 apg A489 PADS PADS 852 ang 552 m PC BEO 14 6 15 02 21 02 23 7 PADS 52 ADS 09532 14 A6 15 D2 21 D2 23 E4 PAD 53 Ap aav LAS3 PAD7 53 Ap aav AS B54 33y ape A54 B54 33y A54 PAD6 PADS BSS A55 PADS BSS 55 PAD4 PAD3 B56 Apa GND 456 PAD3 856 Apa GND 456 557 GND Ap2 A57 557 GND Ap2 A57 PAD2 PAD1 BS8 ADI Apo 58 PADI BS8 ADI Apo 58 PADO e 1553 4 B59 sy 459 25 C6 ACK64 0 m B60 ACK644 REQ64 CA m REQ6440 25 06 25 C6 ACKGAMI m 60 ACK64 amp REQ64 DA 25 6 e 551 HA o Bol sy A6l B62 L 62 B62 sy AG EH06001 GL V EH06001 GL V GND GND 23 A2 PRSNTIMO m GND GND PADI9 1 R9 2 dr REPE C 0 1UF PIDSEL1 0 EM 23 A6 PRSNTI m i PAD17 i S 2 m PIDSELO 23 B6 PRSNT2 1 m 9 C 0 1UF 7 27 2000_14 39 PAGE 23
20. INPUT NAND4 BAND3 INPUT Y po OUTPUT INPUT NAND4 OUTPUT NAND4 o OUTPUT NOT NOT 7 INPUT NAND4 OUTPUT NQT NQT INPUT NAND4 p OUTPUT NOT NOT INPUT NAND4 OUTPUT v YON Y1N Y2N Y3N Y4N YSN Y6N Y7N AND2 INPUT AND2 NPUT ID 15 0 095 0 WIRE ID15 WIRE ID7 WIRE ID14 WIRE ID6 WIRE ID13 WIRE ID5 WIRE ID12 WIRE ID4 WIRE ID11 WIRE ID3 WIRE ID10 WIRE ID2 WIRE ID9 WIRE ID1 WIRE ID8 WIRE IDO Xo ID register idr ON 1N 2N 3N 4N 5N 6N 7N EIN INPUT 74148 NAND8 OUTPUT EON OUTPUT GSN gt OUTPUT gt AIN OUTPUT A2N MacroFunctior INA INB INC IND SEL 15 0 INPUT So T A INPUT To B INPUT C INPUT Tso D INPUT SEL 15 0 level sel A IN SEL 15 12 SELIS 0 level sel B IN OUT 15 0 SEL 11 8 SEL 3 0 level sel IN OUT 15 0 SEL j leELD3 0 level_ sel D IN OUT 15 0 SEL 3 0 SEL 3 0 OUTB 15 0 OUT 15 0 OUTPUT QUT 15 0 NOR4 QUT 15 0 level_sel4 Level Select 4ch ILCRA 15 0 D 15 0 Se a JLCRA 1
21. PCI IDE FLOPPY 5 e eoe wn 85 5 CN14 Z x CNIS 1 1 en use 1 15AS PIDED I5 0 or nRESET 15 05 SIDED I5 0 6 nRESET GND 15 E2 16 F2 19 A4 22 F2 MIS43 RST m 1 8 2 GND 15 E2 16 F2 19 A2 22 F2 1543 RST 1 8 2 GND 15 84 DENSEL m 2 DENSEL PIDED7 2 LESER DATAS SIDED7 2 ER PIDEDS 3 6 4 DATAS SIDEDS 3 6 4 paras r Fares 4 R33 5 BU ATG SIDED6 4 R 33 5 5 DATAS 5 GND EIDED 1 NR 8 6 DATA9 SIDED9 1 6 DATA9 6 DRATEO PIDEDS 2 1 7 DATAE SIDEDS 2 1 7 E DATAR GND HIDEDIO gt 6 8 DATAIO SDED10 5 8 DATAIO 15 B4 INDEX m 8 nINDEX PIDED4 4 R33 5 9 1 DATAA SIDED4 4 R
22. 4 GNT 0159 m PCLGNTI I E225 B7 AM79C973A VC CZAT vssB1 Am79C973A VC 2 5 an vssBo 5 PAR 50 PPAR 14 D3 15 D2 23 D4 23 D7 FRAME 019 m PERAME 14 D3 15 D2 23 C4 23 C7 25 B6 Vsse 164 4 IRDY 020 m PIRDY 14 D3 15 D2 23 C2 23 C6 25 B6 vsss 144 4 TRDY 022 m PTRDY 14 D3 15 D2 23 C4 23 C7 25 B6 vss4 100 025 PSTOP 14 D3 15 D2 23 D4 23 D7 25 B6 vss3 8 IDSEL m IDSELO 21 83 vss2 62 DEVSEL 4 PDEVSEL 14 03 15 02 23 02 23 06 25 86 vssi 34 4 vsso 18 9 PERR 027 m PPERR 14 D3 23 D2 23 D625 BG AM79C973AVC SERR OA m PSERR 14 D3 15 D2 23 D2 23 D6 25 B6 Am79C973A VCGIS AM79C973AVC Am79C973AVC RU PADIG 1 2 a IDSELO 21 E2 R 100 7 27 2000_14 39 PAGE 21 1 2 3 4 5 6 7 8 LAN CONNECTORS 21 46 452 U3 CN7 15 Tx4 HH 1 Tx z M cmr 2 Tx x u 21A6 TX m 16 Tx 19 3 RX 152 415 in 4 971 8 74 1 7 5 21 46 RX m RD RX 9 cn CT 6 21 46 m 2 Rp RX 7 8 a 777 1081 al GND FG LEDI K ach a
23. 4 3 3V 20 1124 SU e GND 10 ND sv SN74CBT3383PW 4 Gxp our 5 HD74LVC244AT Do Not Stuff 1 2 TOOL R203 R207 I 055 yen m 4 2 F 27MHZ 199355 D E 3 D4 101516 A0 co 2 aha cin 17 E2 SH_CTS2 m Al c r 2128 1 2 MD7 1 1 10 Dren C 0 1UF MD8 0 ee 17 D2 SH RTS2 m A2 p 52 d SU MD10 0 wos 23 B225 B6 PCI REQ2 m A3 5 GND 33V mm mm M 851 Sol ML 851 Ml 23 B625 B6 PCI REQ3 m 21 a4 ca o BO 0 5 MD6 105 8 9 r r 9 BI pi 9 a 105 z zm x 14152 pm 15 8 CS 1 i m4 x Do Not Stuff 18 g3 a VEA sw SS cmo R205 R209 22 1 p B a VE2 1 5 016 m SCIFO 4 C2 2 15 one a SCIFI 4 02 ate whelete ate ese BX ROMSEL 402 Soh 521 521 asi s 4 13 S22 950 SSL 524 924 4 BE VOC 13 24 10 0 DBG 4 02 ki a SN74CBT3383PW m CS0EN 4 C2 toot e m CS6EN 4D2 7 10 ar a a e OO e 4 D2 GND GND GND GND GND aD se 5 e OO m 4 D2 33v CHS 08B Rod SW5 2 SCIF1 SW5 5 CSODIS 1 2 SW5 1 SCIFO ON on board resource enable OFF OFF 9 600bps 0 on bord resource disable OFF ON 19200bps uso 19 wii ON OFF 38400bps SW5 6 CS6EN ON ON 115 200 ON CS6 on board resource enable PRE PRE SWEJ ROMSEL OFF CS6 on
24. B BS A3 Y3 DIR GNDi0 1 B7 6 C5 15 A3 va 5 B RD 4 2 9 5 10 6 A4 Y4 HD74LVC245AT 1A4 ya 3 030 G CNDAO 2 AL pi H8 B 925 CNDAO HD74LVC244AT 3 A2 B2 17 B_D22 HD74LVC244AT 4143 16 D21 YI 5 M B4 5 B_D20 35 6 MET B DI9 A3 7 46 Bo 3 15 A4 Y4 8 1 7 2 B_D17 9 MET B DI6 a HD74LVC244AT e 022 1 pr CNDAO Al YI HD74LVC245AT 2 2 029 2 pi 13 B_DI5 M Y4 ie miU B D14 gf hen G GND 10 A4 B4 HD74LVC244AT 6 as Bs 4 B DH i 13 B DIO Al 87 12 Bp 33V 33V 33V 33V 33V 33V 33V 33V A2 2 9 ag ps B_D8 A3 4 Y4 3 a 5z a 5z 5 lt Se Q Se Be Se 1 pm NDA 5 11 O gal 5 31 5 71 0 71 9 71 S 33 G NDAD HD74LVC245AT 5 9 5 eU QT HD74LVC244AT U28 021 2 B1 H BD GND GND GND GND GND GND GND GND 3 A2 B2 7 B_D6 A2 2 4 16 95 5 M B4 5 B_D4 A4 Y4 6 as Bs 4 13 B_D2 8 1 7 p 12 E HD74LVC244AT 9 A8 ps 11 GND 4 BA B BEN m DOE 4 B4 AB DIR 1 pr CNDAO HD74LVC245AT 7 27 2000_14 39 PAGE 7
25. oo 106 GND 10 AO 5 7 10 7 E e OO HD74LVC244AT 2155 5 9 U46 32 ByTE VPP ora CHS 08B Tu Ha y gt 4 B2 EPROMCE mw cg E i ND IP10 13 A2 y2 7 B D10 4 C2 7 B8 10 C6 BRD m GND D3I IP9 15 5 BD 5 sv A3 Y3 M27CI60F1 np IPS 17 4 y4 3 B D8 e e 9 pat 7A7 10 C6 WE 3 0 CN21 19 led GND i0 WE3 8 HD74LVC244AT WE2 2 2 1C26 0210 GS4 swo CN22 1 16 1 7 2049 18 BD 25515 6 4 2 y2 16 B D6 oo 1 5 6 A3 M BDS 1C26 0210 GS4 45550 1 4 8 4 y4 2 gp4 e100 6 u 1 33V 20 50 GND 10 670 010 HD74LVC244AT 3 0 0 U44 CHS 08B Ha y 2 TP2 13 45 y2 7 BM 1 1 15 43 5 BDI IPO 17 y4 3 BDO 5 19 33V 20 4B4 SWRDI e G GND 10 RT RTE 7 27 2000 14 39 PAGE 9
26. 38 D20 108 2 1029 37 m A BEN 8 D4 A9 18 A7 5 D19 109 13 GND2 38 4 AB 19 A6 3 Dis 1010 4 vcco 39 AT 20 As pai 2 D17 TMS 15 a ISP TMS 4 12 1030 40 m EXTCS SAG A6 21 a4 22 Di6 1011 H6 m EPROMCE 9 5 1031 4 x EXTCSI 8 A6 22 A3 1012 11 1032 42 Ad 23 A2 vecioi 18 9 3 A3 24 1A1 1013 219 1033 m EXTCS6 8 86 2 25 RYBY 15 1014 22 1034 45 33V 1015 2 1035 46 1 0 2 47 BYTE T 1016 22 BAL 1036 47 8 88 RU egg E 1017 3 m B RD 7 8 9 5 10 6 1037 48 8 8 To 3285 OE ZEE 1018 3 1038 9 8 08 WES Ho WE 9 97 1019 25 1039 50 m SLOT WAIT3 8 08 CND27 46 5 EPM7128ATC100 EPM7128ATC100 RESET EPM7128A 1 4 EPM7128A 2 4 ze 25 0 V AS A A5 5 B3 6 A3 7 A2 8 A2 11 A2 016 YP7601x 016 YP7601x CS 60 VATSID2 A38 A6 vccio4 51 9 1059 76 AD M2 1040 52 m SCIEO 3 C7 1060 77 A20 AM 9 DOIS A 1 55 D15 1041 53 m SCIFI 3 07 1061 78 16 A1g pow 5 1042 54 m ROMSEL 3 C7 1062 9 A22 19 17 A17 pais 41 1043 55 DBG 3 C7 1063 90 28 18 48 A16 DQ12 3 m 1044 56 m CSOEN 3 C7 1064 91 24 A17 1 415 pau 26 1045 57 m CS6EN 3 07 vecios 82 16 2 A14 DQ10 54 Dio 1046 3 07 1065 83 A25 15 3 AI3 poo 32 D GND4 52 4 1066 84 CS2 AM 4 A12 30 D8 1047 60 OPTI 3 C7 1067 85 Css A13 5 AH 4 D7 1048 61 GND6 4 12 6 A10 2
27. E 2 2 3 GND KeyBoard FLS 4 5V undder 1 2 5 9 KCLK 00SPT 6 181 N C BLM31A700SPT 8 Nc 9 GND Mouse FL10 10 sy upper 1 2 11 9 MCLK BLM31A700SPT 12 N C e E E ae el 2 MH11061 D3 al z 82 g EE gr gl z eer abe SFR Sy Se ST 1 o ip O iy 5 i2 O gt gt gt gt gt gt O wu 0 wu OP wu OF OP SS 1 1 e e FG10 1 reu 1 55 8 BLM31P500SPT USB 0 undder USB 1 upper MS7751RSE01 0 7 27 2000 14 39 20 1 2 3 4 5 6 7 8 LAN CONTROLER PAD 31 0 14 A6 15 A2 23 B2 23 B3 23 B7 23 B6 3v e U6 06 EBD 7 0 22 D3 U6 U6 1 162 EBD7 125 RX 22 2 vpp pCig 199 4 9 9 AD30 165__PAD30 EBD6 Rx 127 a RX 227B2 vpD Pcr 161 T Ap29 166 PAD29 EBDS TX 19 a TX 22 42
28. GND P NC7 e 5 GND sv 140 Ns KX14 140K5D1 14 KX14 140K5D1 KX14 140K5D1 i KX14 140K5D1 GND ER 3 3V ve 1 25 g 8 C6 13 B3 A DREQU m 8 C6 13 B6 DREQI 2 7 3 6 4 5 M R 10k 8 06 13 83 13 86 WAIT 3 0 WATO 10558 WAITI 2 725 3 6 1 4 5 1 masc R 10k 8 C6 13 C3 13 C6 A IRQIS 1 A IRQI 1 22 g 4 1803 2 7 1805 3 6 1807 4 5 4 R 10k 2 1 21 g 1804 2 7 1806 3 6 1808 4 5 R 10k 7 27 2000 14 39 PAGE 13 1 2 3 4 5 6 7 3 3V PCI lt gt 5 PCI 1A2 PCI 2 0 PAD 31 0 15 A2 21 A2 23 B2 23 B3 23 B7 23 B6 09 015 PCI AD31 3 A0 po 2 PAD31 1A2 PCI C BEOR m 3 A0 po 2 m PC BEO 15 02 21 02 23 4 23 7 PCI AD30 4 a PAD30 PCL AD7 ails PAD PCI AD29 TI ml PAD29 PCI AD6 ale mL PAD6 PCLAD28 8 nl PAD28 PCI ADS 8 3 B3 9 PADS ja MEC PCI AD4 4 pa 10 PAD4 IC BE Rl 0211 SN74CBTD3384PW SN74CBTD3384PW U9 015 PCI AD27 M 15 PAD27 PCI AD3 M IB PAD3 PCI AD26 Ua Bi 16 PAD26 PCI AD2 Bi 16 PAD2 PCL AD25 18 m PAD25 PCLADI 18 45 B2 19 PADI PCI AD24 21 3 20 PAD24 PCI a3 20 PADO PCI C BE3 m 22 A4 3 PC BE
29. N N N 5 55 m an T N AT51_25MHZ N N 21 MS7751RSE01 Parts list 4 MAKER ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ITACHI IPEX ULSE ENGINEERING n ITACHI CYPRESS ALTERA MARUBUN IDT HITACHI gt gt 9 T ITACHI HITACHI HITACHI N S EPSON ALTERA HITACHI HITACHI HITACHI HITACHI HITACHI HITACHI TI EPSON NDK n 133 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R198 SW5 SW6 SW7 SW8 SW9 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 2 U4 U5 S 92 7 08 9 U10 U11 U14 U15 N M add 20 U21 U22 U23 U43 44 U45 U46 U49 U54 U56 U58 24 25 26 27 28 U29 U30 U31 32 U37 U38 U40 caa cia ccu c 1 X2 3 eke ci SH7751R Solution Engine MS7751RSEO01 User s Manual Publication Date 4 Edition Nov 2002 Published by Platform Design Dept Hitachi ULSI Systems Co Ltd Edit by Platform Design Dept Hitachi ULSI Systems Co Ltd Copy right Hitachi ULSI Systems Co Ltd 2002 All rights are reserved Printed in Japan
30. Table3 1 Functions of SW4 Function SW4 1 Microcomputer SW4 1 to SW4 3 is connected to mode pins to 2 and this switch SW4 2 operating mode selects clock operating mode of the SH7751R SW4 3 setting switch SW4 1 SW4 2 SW4 3 D 0 2 Clock remarks operating mode as E iu shipment x Diei we e i OFF SW4 5 must be used in OFF state SW4 6 Endian select switch SW4 6 is connected to mode pin MDS of the SH7751R and select big SW4 4 Area bus width SW4 4 and SW4 5 are connected to mode pins and MD4 and select SWA 5 select switch bus width of CSO Bus width is fixed to 32 bit SW4 4 and endian or little endian ON Big endian OFF At shipment Little endian 15 5 DIP Switch for setting baud rate SW5 Figure3 5 shows DIP switch for setting the baud rate SW5 Table3 2 lists the functions of the switch As listed in Table3 2 this switch can select the baud rate of the SH7751R on chip SCIF ROM placed at area0 Eu SW5 5 SW5 7 SW5 8 are not used SW5 6 SW5 4 SW5 3 SW5 2 SW5 1 Figure 3 5 DIP Switch for setting the baud rate SWS 16 Table3 2 SWS Functions SH77S1R SCIF baud rate select switch ROM select switch CS6 on board resource select switch For test Not used Select the baud rate of SH7751R on chip SCIF2 SCI with FIFO SW5 1 OFF SW5 2 OFF At shipment 9600b
31. ojo 92 Go Go Go Go e ei n e e nd NINININ NINININININININ asf 5 EISS 5 18 alalla o N 5 5 w D74LVC374AT P211ECA 081 79C973AVC PS2014D N74CBTD3384PW D6417751RF167 N Q re N 199 un lt oo gt a Q T E KJ EN n a 5 1 21 312 DT49FCT3805PY M1543C B1 N E ol o NY AIO Oj N 1 HD74LS245FP CA 5 m 1 oo 4 4 HD74LVC245AT T m 3 T Og BE RUE g te Q ola 5 4 ME gt N o lt n a gt Q gt g x Ad 21 gt a A BR N N 1 1 1 1 1 2 N oo UA HD74ALVCH16245T oj gt HD74ALVCH16244T N74CBT3383PW Z x oo lt Al S 7 B 8 S zm ue d
32. 26 7 2 Serial Control 36 7 3 Super I O Control 49 74 Memory Block _ 52 75 General purpose switches 53 7 6 8 bit LED 54 8 Interrupt Controller 55 9 Expansion Slot 56 9 1 Expansion Slot Pin Assignments 56 9 2 Expansion Slot Connector configuration 58 9 3 Daughter Board Dimensions 58 4 10 11 12 13 14 15 Connector CN18 59 Bus Controller Setting 60 SH7751R CPU Bus interface 61 Monitor program usage 62 13 1 Monitor program usage 62 13 2 Monitor program function 71 Description of Command 72 Appendix 80 15 1 Board Dimension 81 15 2 Circuit Diagram 83 15 3 FPGA Logic 110 15 4 Parts List 130 5 1 1 1 2 1 Features The Solution Engine is a system capable of efficiently developing software and hardware for systems that employ the Hitachi SH7751R SH 4 32 bit SuperH series microcomputer Features of the Solution Engine The Solution Engine has the following features 1 the information concerning this board including the circuit diagrams various connector specifications and the internal logic of the FPGA used with the board are contained in the manual 2 The specification of this board is
33. 80 324 8 A Enlarged view Enlarged view 79 E97 re 89927 54 un zh IND 8 6 6 9 j CON 0 9 4 7 ue f w He LZND 00 09LDZZN ZW ZZN r9 999 9934 00L 09LZZM ae i LEND 3 1 gt gt E z ise B E25 e L B a u z T 3 F n o z M lt N oo I m N aR pog N PP 19 9 44 9 9 4 9 pepe e ooh 4 2 se
34. gt z 2 S c 3 5 oo Em aa ps Eu pn E eo so lo so ho To 56 Table 9 2 Expansion Slot Pin Assignments Column B i RR e p CCT ls p GND g gt 42 DACKI 43 DREQI 44 45 CSI 5 gt B46 5 47 Q 52 WEI B53 55 WAITI EE gt 56 WAIT3 57 B58 IRQ2 B59 IRQ4 B60 IRQ6 E oo al gt olslelglala gt gt gt gt 2 Z 2 5 2 z B61 IRQ8 N lt gt 5V gt B64 SV B65 5V gt B66 5V _ E E E pe LE E Eod om pe ees ese one e E bebe onis ne 57 9 Expansion Slot Connector Configuration Figure9 1 shows a connector configuration of the expansion slot As shown in Figure9 1 an additional daughter board can be connected on top of the daughter board by mounting connectors on both sides of the daughter board Maximum 4 daughter boards can be connected by using the expansion slot Figure9 1 Expansion Slot Connector Configuration Daughterboard side connector 4 14 140 5 1 made by JAE Daughterboard 2 Daughterboard side connector 3 KX15 140K4D1 made
35. hg 9 6 QU oo eo Q ON N M N mm e ee e ole ee ele oe ele ele F Me oO N H 99699 ole o9 6994999996666060999 47 SHOES ee S pos c AP EEE SS 1 db bobo Fe ole ee e eje e e ee e ele ole oe ole e e e ele ole e e e e 8o Zeb 44 4 6 RB B RARE O tt B bebe4d 4h RR esses sess segs Bebes ee MAR RR se I Bel V ax V V V MS7751RSE01 External dimensions 1 2 3 4 8 D 31 0 4 A7 5 B3 6 E3 1 A4 8 A4 11 C2 A 25 0 AJA5 A C4 5 B3 6 A3
36. 00 m INDEX 19 B6 PIDED2 02 WB a IRRX 27 05 AD17 DENSEL 16 m DENSEL 19 A6 PIDEDI spi UB a IRRXH 27 D6 AD16 PIDEDO 113 IRTX 27 06 ADIS pp 8 m PD7 17 B2 XD 7 0 15 E2 16 E2 WS PD6 17 82 2 a PIDEA2 19 D2 XD7 AD13 pps 8 PDS 17 82 PIDEA1 2 m PIDEA1 19 D2 XD6 ADI2 pps US PD4 17 82 m PIDEAO 19 D2 ADIL pps 18 PD3 17 C2 PIDECS3J a PIDECS3 19 D2 XD4 ADIO FAD10 pp2 Y7 PD2 17 C2 PIDECSIJ m PIDECSI 19 D2 XD3 AD9 PDI 17 82 PIDEIOR OC m PIDEIOR 19 C2 XD2 ADS PDO 17 B2 PIDEIOwJ 062 m PIDEIOW 19 C2 XDI AD7 SLCTINJ DW10 SLCTIN 17 C2 PIDERDY 5 m PIDERDY 19 C2 AD6 INIT OW a INIT 17 C2 PIDEDRQ G3 PIDEDRQ 19 C2 ADS AUTOFDJ m AUTOFD 17 B2 m PIDEDAK 19 D2 IRQIs m IRQIS 24 D2 24 D5 25 E2 STROBJ OW STROB 17 82 SIDED IS 0 19 44 16014 G17 m 24 D2 24 D5 25 E2 AD3 Busy U2 m BUSY 17 C2 SIDED15 SIDEDIS FERRJ DS20 m FERR 16 D7 AD2 OD ACK 17 C2 SIDED14 SIDED14 mou N16 m 24 D2 24 D5 25 E2 ADI pe V PE 17 C2 SIDED13 SIDEDIS IRQ10 8 m 18010 24 D2 24 D5 25 E2 ADO sLcr 75 m SLCT 17 C2 SIDED12 SIDED12 IRQo IRQ9 24 2 24 5 25 2 ERRORJ 0010 ERROR 17 C2 SIDED11 18087 RTC_IRQ 16 E3 CBEJ3 m PC BE3 14 B3 21 D2 23 C2 23 C6 SIDED10 SIDED10 IRQ7 W20 m IRQ7 24 C2 24 C5 25 C2 O m PC BE2 14 C3 21 D2 23 C2 23 C6 SIN2 4 m SI
37. 1 q GND 7 i U40 U41 B gt CLK jo 1 10 9 HD74LVCIAT ek __ abt HD74LS02FP 33V 14 CLR SVSB 14 GND 7 GND 7 F h HD74HC112FP U40 U41 33VSB 16 GP d 13 12 12 HD74LVCMT HD74LS 33V 14 GND 7 27 2000_14 39 1 2 3 4 5 6 7 33V 5V 5VSB 12V 5V CNI6 LLL e 2 SVSB use 33VSB LM10851T 3 3 COM 4 IN OUT 5v 5 COM GND 6 a Se sv 4 1 Sei ORT com U37 U37 97 PW Ok 8 1 2 3 ot mPW OK 26 C2 x9 5VSB i6 HD74LVC14T HD74LVC14T a 12V 33VSB 14 33VSB 14 i H 9 T 2 9 PW OK 2662 com 13 ps on 14 com 15 gt 33V p VCC 1 A LMS1585ACT ADJ 16 a PS ON 26 C5 5 gt 17 IN OUT e 17 18 I 5V ADJ a GND nm S gt 3E 19 5 5 55 zt Re SV SNNT 20 1 zg 5 41 SUN 5V
38. 12 Ethernet may encounter an abrupt drop of signal level and the line cannot be connected depending on the number of hub line connections or cable length So that if the Solution Engine is connected to a hub reduce the number of lines connected to a hub to a minimum to ensure reliable operation 13 The ROM emulator controls reset and NMI while the ROM emulator is used Do not actuate reset switch SW2 and abort switch SW3 during the ROM emulator is used 1 14 15 16 The free warranty period of the system is one year from the delivered day But it is limited to systems that are being used under normal condition such as environment condition the way to operate the Solution Engine The warranty is void in the following cases a Any problems of system caused by natural disaster b Systems that are modified and repaired by user c Any problems caused by improper handling Do not reprovide the Solution Engine to the people who use the Solution Engine to hinder international peace and safety and do not use the Solution Engine for such aims personally and do not have third parties use the Solution Engine for such aims For exporting the Solution Engine follow Foreign Exchange and Foreign Trade Control Low and prescribed procedure 2 Components of the Solution Engine Open the package and check the contents to match against the packing list Table 0 1 lists the components of the Solution Engine Figure 0 1 shows the cont
39. 16 B DH ads 21 B_D27 36 84 4 TP29 6 y 14 d 19 B_D26 4555 1P28 8 4 y 2 BDL ds oo 17 B D25 Sook 4 08 15 024 Fool 166 GND 0 29 B 23 HD74LVC244AT A10 q 27 B 22 045 A9 Qs 25 B D21 1P27 as 3 B D20 1P26 y2 7 AT 20 B_DI9 25 15 y3 5 BD oz 18 B DIS sv IP24 17 y4 3 B D8 s 91126 B DI7 9 e A4 Qo 4 B_DI6 19 33V 20 GND A3 5 E HD74LVC244AT A2 sv 2 dz d Al a a e SW7 U43 5 1 16 1P23 2 18 BD Al Y 8155 20 05 TP22 4 a3 y2 16 B D6 BYTEVED 4 1P21 6 43 14 B DS RUNE E 40 04 P20 8 A4 y4 B D4 OE 0 12 31 oo 9 M27C160F1 GND 6 m lc 337700 SCO GND 70 010 HD74LVC244AT 8 U43 9 Qis A 1 9 B DI5 CHS Gan 1 19 Nn B D14 IPIS RAM y2 BD AT 013 26 15 43 5 BDI at op L2 6 17 4 y4 3 BDO dis 21 d B DIO Ee _ 33V 20 4A4 SWRDO e GND 10 A13 9 7 9 E HD74LVC244AT A12 os 15 B_D8 Au o2 B D7 A10 Qe 27 D6 5 d os B Ds 23 B D4 AS Q4 8 I i m os 120 B D3 7159 U46 A6 Q2 H8 BD ols IPIS 2 y 18 n 16 B Di 255515 4 2 16 4 dd B_DO 4 IPB 6143 y M n 45555 1 1P12 y4 2 BDD 3 512 Al d 1 33 20
40. 3 4 z 55 3 3VSB 14 33VSB 14 GND 7 GND 7 Tun S EX OF SKHHAK a Power SW GND BU 33VSB U38 U38 R158 1 2 13 12 pon m RSM RST 16 85 16 7 R 22K zi HD74LVC14T HD74LVC14T BE 3 3VSB 14 3 3VSB 14 GND 7 GND 7 D T n gt SVSB a 2 lt U42 SVSB 821 039 R140 2784 31 05 1 3 R 10K 2 27 84 HD74LS132FP 5VSB 14 GND 7 c 2 6 27 B4 PW OK Q CLR 3 3YSB 15 HD74HCIDEP 33VSB 3 3VSB 16 GND 8 R 10K a 5 RI U39 SW2 m U41 27 D2 RESET SW m 2 1 CPU RESET 3 A6 4 45132 HD74LS02FP S SVSB 14 3 4 a Be GND 7 SVSB 14 038 U38 oT an GN 5 9 8 PWG 16 A5 O gt E 3 SKHHAK a L Reset sw 555 HD74LVC14T HD74LVC14T RI 3 3VSB 14 3 3VSB 14 d GND GND 7 TP2 ROM ICE Reset Probe Of 15 D 040 U40 9 6 D6 RSTOUT m Id 2 3 ot HD74LS132FP HD74LVC14T HD74LVC14T SSH SB 3 3V 14 3 3V 14 GND GND 7 3 3VSB GND 7 33VSB a a 58 325 ES ES 2 5 Sw3 U39 U40 e bd 13 3 os m NMIIN 605 2 to TADP64 3 O a HD74LSI32FP HD74LVC14T ae SVSB 14 3 3V 14 n e ST al ROM ICE NMI Probe O GND 7 GND 7 Maro i SKHHAK a 1 from TADP64 E NMI SW 3 3V Normal mode 3 TADP64 used mode 1 R159 2 SH NMI 2 42 R 10k to SH7751R 33VSB U40 1 R137 2 5 9 8 10 HD74LVC14T HD74LS02FP PRE 5VSB 14 GND 7
41. 4 Mbyte Flash ROM model name MBM29LV160T 90PFTN Fujitsu EPROM 2 Mbyte mounted EPROM model name MX27C8100PC 10 MACRONIX Ethernet 10 100BASE TX Ich Controller model name Am79C973AVC AMD PCMCIA 1 slot TOMCA Contr model name MRSHPCO V2 Controller SH7751R on chip SCIF Super I O Serial 2ch Parallel Ich IDE 2ch FDC Ich USB 2ch PS2 Keyboard Mouse 2ch Expansion Board mounted Controller model M1543C B1 ALi Monitor FLORA310 or equivalent Windows95 or Windows98 is equipped Program System Host RS 232C interface 9 pin connector used Interface Transfer speed 9600 19200 38400 115200bit s Command 17 commands ML Memory Load RR Register Read RW Register Write RC Register Clear ME Memory Edit G Go BS Breakpoint Set and etc Solution Engine CD ROM User s manual and etc Note MS7751RSEO1 can be execute external 81MHz except for PCMCIA as maximum 66MHz specification Table 1 2 Power Supply Dimensions and Environmental Factors of the Solution Engine Environment Operating conditions Temperature 10 35 degree C Humidity 30 85 RH no condensation Ambient gas Should not have corrosive DC3 3V 5 0V 12V the shelf power supply for ATX should be used Current consumption consumption 1A tem porar temporary value eee 304 8mmx 243 84mm 2 Setting the Solution Engine After opening the package set the Solution Engine as fo
42. Ex gt 24 25 35 22 8 2 5y EN SD e 5V 5 nu TPA sv al NES C184 i G4 U32 1 2 Bly vec M 4 9 8 5 GND GND GND GND gt 5 HD74LVCIAT v GND gl aie 3 3V 14 SP211ECA OT s GND 7 L ES U32 HD74LVCIAT 3 3V 14 GND 7 U32 HD74LVCIAT 33Vi14 GND 7 7 27 2000 14 39 MS7751RSE01 0 PAGE 17 1 4 6 SERIAL COM1 2 G4 G4 1 1 Drs LP CS OT an G4 G4 14 ci c2 H6 4 1 2 RD 2 64 3 15D4 SOUT m TIIN TIOUT ien e TxD 15 EA DTRI w 6 mour 3 9 4 DTR 20 1 GY 5 15 04 16 7 m T3IN T3OUT GND 21 rain T4OUT 28 9 6 DSR 9 7 RTS G4 8 15 EA m RIOUT RIIN em e CTS 15 D4 SINI 5_ R2OUT R2IN 9 9 Rr aes m 7 65 15 4 DSRI R3OUT R3IN 0 11351 73 2 Massa 2 23 64 E m E E x i 15 EA CTSI w R4OUT R4IN a z 42 BB COMI 15 E4 19 R
43. FPGA SH7751R EPM7128 ATC100 PortI O connector CN18 ai 5 connector CN2 PCI BUS Bus slot CN9 RS232C Driver I 4 FDD connector CN15 IDE connector CN13 4 J SuperI O 4 Ps2 connector CNS IDE connector CN14 MI543C C 4 PRN connector CN4 USB connector CN6 SCI connector CN3 4 SCI connector CN12 ISA BUS RS232C Driver ISA Bus slot bus slot CN10 CN11 Figure6 1 Block diagramofthe Solution Engine 7 Function Block 7 1 Ethernet Control 1 Block description Figure7 1 shows a block diagram of the Ethernet control block The Ethernet control block has a controller Am79C973A manufactured by AMD serial EPROM NM93C46 and a pulse transformer H1081 manufactured by Pulse Engineering and provides Ethernet interface at IOBASE T 100BASE TX via RJ 45 connector CN7 Other features include LEDs CN7 LED1 CN7 LED2 LED14 LED15 used to indicate the presence of reception signals In addition a 25MHz crystal oscillator is mounted as the operation clock of Am70C973A Am79C973A Reap p 1 PCI bus System bus Figure 7 1 Ethernet Control Block Diagram 26 Memory Map Figure 7 2 shows a memory map of the Ethernet controller Am79C973AVC uses 32byte h 00 h 1F on PCI bus Address of the memory map is offset address Address on the PCI bus is decided by adding the set PCI base address Am79C973AVC ca
44. MSR Modem Status Register RBR Receiver Buffer Register THR Transmitter Holding Register DLM Divisor Latch MSB IER Interrupt Enable Register h 3 h 000002FB R W X LCR Line Control Register h 6 h 000002FE R W X MSR Modem Status Register h 7 h 000002FF SCR Scratch Register DLAB is bit7 of LCR Don t care X Serial interface connector section 2 9 pin D sub connector CN3 pin assignment Connector Model Name DM11351 Z3 3 Transmit Data 4 o Data Terminal Ready 5 ooa 6 psr 1 DatasetReady 7 rts o Reqest ToSend Ps fers iens I Ring Indicator Figure7 5 9 pin D SUB connector CN3 pin assignment 2 10 pin connector CN12 pin assignment Connector Model Name HIF3C 10PA 2 54DSA Function Carrier Detect Receive Data Data Terminal Ready Data Set Ready Request To Send Clear To Send Ring Indicator 10 No Connect Figure7 6 10 pin connector CN12 pin assignment 39 7 2 4 Parallel controller 1 Register map Table7 5 1 and 2 list a memory map of IEEE 1284 parallel controller register of M1543C B1 super I O controller Base address initial value of parallel controller register is h 378 Set the configuration data as shown in section 7 2 2 Superl O controller to change base address Table 7 5 1 Parallel port register Compatible Parallel Port Enhanced Parallel P
45. al 5 a 39 29 9202 BR Be Sl Be own Be Cl Be Be 7 87759 87 54 17784 25 88 ss GND GND Oy a D ea a 3 ue ue ae ue 5 E 15V 20ohm 225 EG GND GND GND GND GND GND GND CN30 sv 26 A POWER SW m POWER GND FFC 2AMEPIB E 3 x CN28 E SV_ 26 C2 RESET SW m RESET i CN25 2 GND is 1 15 sv FFC 2AMEPIB 15 87 IRRXH m 2 pm CN27 15 B7 IRRX m 3 IRRX 1 R164 2 1 4 9 SPEAKER GND R 68 2 5 2 15 B7 IRTX m e IRTX 1 R165 gt 3 rod 15 B7 OVCROFF OVCROFF 4 svV FFC 6AMEPIB 189 16 4 25 2 SPKR w e 5z FFC 4AMEPIB R 2 2K N a o dz 2604116 3 33V G GND VBAT CN32 5 5 CN26 1 RN 2 VBAT a R170 R IK mU I 2 1f is 2 2 GND Ssa R 330 x ES T 2 N C HL32 A2 2 N 3 GND CR2032 Holder HL32 A2 Specification 16 A4 KBINH m 4 KEYLOCK Les U37 U27 GND FFC SAMEP1B 5 pcs Hj 10 fall HD74LVCIAT HD74LS07EP als 3 3VSB 14 5Vil4 sot 25 SND 7 GND 7 821 821 a CN29 U27 1 AM 2 le U37 U27 19D4 SIDE LED m o c 2 ACT Te Bo sa GND 7 mpz4Ls07Fp FFC2AMEPIB HD74LVC14T HD74LS07EP 3 3VSB 14 SVi14 027 GND 7 GND 7 SV_ 19 D2 PIDE LED ee 3 of LEDI7 037 1 01835 1 POWER rND 7 HD74LS07FP SML OMT Hu HD74LVCIAT U27 GND LED16 GSP 2 i 81823 112016 3ND 7 5V l4 8 ND SML 210MT U37 GND7 HD7
46. 0 RESET u N INPUT NMI RES TIRQ 15 0 INPUT INTR INPUT INIT CPURST INPUT IGNNE INPUT A20M 5 0 15 0 IRL 3 0 OUTPUT gt IRL 3 0 D 15 0 Di5 0 Do 15 0 RDA 15 0 _ Al7 1 INPUT BCRCS INPUT RD WE 1 0 INPUT RES led_reg B D 15 0 WD 15 0 RD 15 0 RDC 15 0 INPUT lt CS B_RD RD B_WEH O WE 1 0 SRESET RES LED 7 0 gt LED 7 0 LED 7 0 BCRCS pees lt LEDCS wae B_RD RDA 5 RDB 15 0 RDC 15 0 Xo st_led NOT moor o a TO wear aP RESET SLP gt LED STBY So NOT OUTPUT gt LED STANDBY NORM OUTPUT NORMAL Peripheral controler YP76020 WD 15 0 RES WE 1 0 reg16 Do 15 0 Q 15 0 RDA 15 8 WIRE WIRE 5 0 CS CS RD RD WE 1 0 WE 1 0 INPUT CLR INPUT CS INPUT So RD meur o w 0 RD 15 8 RD 7 0 RDA 15 0 LED 15 0 RD 15 0 OUTPUT RD 15 0 LEDJ7 0 OUTPUT LEDJ7 0 LED 15 8 NOT LED 7 0 Debug LED register led reg SUBDESIGN st_led ST 1 0 INPUT RES SLP STBY NORM OUTPUT BEGIN TABLE ST 1 0 gt RES SLP STBY NORM 00 gt 0 0 0 1 BOT gt 0 0 1 0 zx T 0 0 B 11 gt 1 0 0 0 END TABLE END SLOT_IRQ 8 1
47. 1 16 PAD10 PCL AD9 18 mi PAD9 PCI ADS 21 43 20 PADS 22 1A4 23 POBE 041 SN74CBTD3384PW 7 27 2000_14 39 PAGE 14 1 3 4 5 M1543C B1 PART 1 PAD 31 0 14 A6 21 A2 23 B2 23 B3 23 B7 23 B6 U19 U19 U19 PIDED IS 0 19 2 019 SD 15 8 24 3 24 7 25 4 AD31 RDATAJ 003 a RDATA 19 C6 PIDED15 PIDEDIS AD30 PAD30 WGATEJ a WGATE 19 C6 PIDED14 PIDEDES AD29 WDATAJ OW a WDATA 19 C6 PIDED13 DD AD28 HDsELJ 092 HDSEL 19 D6 PIDEDI2 EM AD27 DIRJ DP DIR 19 B6 PIDED1 AD26 OW m STEP 19 C6 PIDED10 EE AD25 DSKCHGJ OB DSKCHG 19 D6 PIDED9 AD24 DRVIJ OH DRVI 19 86 PIDEDS AD23 DRV0J DRVO 19 B6 PIDED7 SD7 m PWR EN 20 A2 AD22 Morij O84 MOTI 19 86 PIDED6 m GPIO6 16 D7 AD21 MOT9j MOTO 19 B6 PIDEDS sps X2 m CH2 DETECT 19 04 AD20 PDA WPROTJ OV a WPROT 19 C6 PIDED4 04 W12 m CHI DETECT 19 02 ADI9 TRK0J OY 19 C7 PIDED3 sp3 719 m OVCROFF 27 D6 AD18 INDEXJ
48. 10 Mom od LEDI A m 921 Sat oT ee gt Roa LED2 K a a 5 12 LED2 A e e e 406549 1 LFF GND GND lee GND FG RE 4 89 I 777 GND_FG 3 3V 3 3V a 1 RS 2 952 R LSK 5V E SV R7 1 2 1 8 R LSK 2104 EECS w CS ee 2104 EESK m e 2 sk 102 3 Ny 21 D4 EEDI x 3 pucr d pa 2104 EEDO GN 5 e w NM93C46M8 SML 210MT TE GND 21D4 LED2 m 21A4 EBD 7 0 2184 15 8 21 84 EBA 7 0 UL M10 EBA7 3 10912 LAT LA4 9 DOAA 6 4 20 LAG LA3 16 aig 0014 EBAS 7 30 LAS LA2 U anm 41 EBA4 8 ap LA4 LAL 48 A16 pon 35 EBA3 13 so 12 LA3 LAO 1 Ais 0011 2 M 15 LA2 EBDAIS 2 4 34 EBA1 17 ap 16 LAL EBDA14 3 443 poo 22 EBAO 18 19 LAO EBDAI3 4 ayy Dos EBDAD 5 s Hg TM EBDAI 6 449 D06 GND 10 EBDAIO 7 ag 05 EBDA9 8 HD74LVC374AT AS DQ4 EBDAS 18 47 EBA7 19 6 Do 20 As pot EBAS 21 4 ol EBA4 2 EBA3 23 a2 EBA2 24 ay EBAI 25 15 7 BYTE 21 C4 EROMCS m 26 21 C4 m 28 21 C4 EBWE Uo wg m GND 27 46 15 E2 9 A2 9 A4 1543 RST m 12 RESET MBM29LVIGUTPFTN DoNotStuff M10 7 27 2000_14 39 PAGE 22
49. 2000 14 39 PAGE 16 GND GND GND 1 2 3 4 5 PARALLEL SERIAL SH7751R SCIF SV_ e r e ee e r D nes a Mim 4 yer T Mou Z 7 7 Ss ot Y iM 1 5 g 15 C4 STROB m 1554 AUTOFD m 2 T ee 15 04 PDO 3 9 Y 15 C4 PDI m 4 5 8 R 33 RES ES 515 Iw NR7 R 5 15 C4 w 1 8 9 alse OT aS RES 15 B4 PDS m 2 i e 9 185 Sy a 1 nstrobe a wn 1299 15 84 PD6 m 3 6 9 4 2 82 UTE a ND 2 patal ee 15 B4 PD7 w 4 5 2 w ee Bom a CE 3 Daa R 33 e 8 97 4 zug de G
50. 32Bit SWAIT 16MB Real capacity 4MB h 00000000 h 003 FFFFF 16MB Real capacity 4MB h 01000000 h 013FFFFF 32MB h 02000000 h 03FFFFFF EPROM MX27C8100PC 10 MACRONIX x2 or equivalent 42pin socket x2 FlashROM MBM29LV160T 90PFTN FUJITSU x2 1 ROM emulator can be connected 2 SW5 3 SWS 4 can change the place of EPROM and Flash ROM 3 8Mbit EPROM can be used 27 8100 10 MACRONIX x2 Expansion 0 Expansion slot CSO assert 64MB Expansion areal Expansion slot CS1 assert h 04000000 h 07FFFFFF Areal Expansion Areal On expansion connector Expansion 64MB Area2 Expansion area2 Expansion slot CS2 assert h 08000000 On expansion h OBFFFFFF connector SDRAM Area Expansion Area4 Area3 Device Model name UPD45128841G5 A75 9JF ELPIDA x4 64MB Real capacity 64MB h 0C000000 h OFFFFFFF 128M SDRAM 64MB h 10000000 h 13FFFFFF Expansion Area4 Expansion Area4 Expansion slot CS4 assert Figure5 Memory map 22 Area7 Expansion Area5 on expansion connector 16Bit Peripheral device control register SH7751R incorporated 64MB h 14000000 h 17FFFFFF 16MB h 18000000 h 1 8FFFFFF 16MB h 19000000 h 19FFFFFF 16MB h 1A000000 h TAFFFFFF 16MB h 1B000000 h 1BFFFFFF h 1C000000 h 1CFFFFFF H 1D000000 h 1IDFFFFFF 1 000000 h 1E1F0000 h 1E200000 h 1E200
51. 33 5 9 9 PIDEDI1 15 8 10 DATAN 1 9 8 10 15 84 MOTO 10 MTRO PIDED3 2 1 DATAS SIDED3 2 7 PIDEDI2 I 3 6 12 pATAI2 SIDEDI2 53 6 12 pATAI2 15 B4 DRVI m 12 ADRO PIDED2 4 R 33 5 13 DATAZ SIDED2 4 R 33 5 13 DATAZ 13 1 42 g 14 DATA 1 50 8 DATAIB mE ORV a 14 pri 2 7 l5 DATAT SIDED1 2 1 I5 ATI 18 ND EIDEDIA 3 6 16 DATA14 SIDEDI4 3 6 16 pATA14 15 84 MOTI 16 nMTRI PIDEDO 4 R33 5 17 DATAO SIDEDO 4 R 33 5 17 3 A TAG 17 GND PEDIS 1 NR 8 18 DATAIS SIDEDIS 15 8 18 DATAIS 15 A4 DIR 18 nDIR 15 C5 PIDEDRQ 2 e GND 15 5 SIDEDRQ 2 7 e GND e GND 15 C5 PIDEIOW 6 20 NC 15 85 SIDEIOW 20 N C 15 B4 STEP 20 15 5 PIDEIOR 4 RS 5 21 SIDEIOR 4 R33 5 21 21 DREQ 15 85 SIDEIOR DREQ 21 GND 1 RI51 2 22 1 R176 2 22 ware 22 2 GND e 22 GND 15 A4 nWDATA R 5 6K 1 R150 2 RIS R 5 6K 1 RIS gt 23 ae 23 cun 23 R 10K R 10K GN 24 24 GND 1S A4 WGATE 24 awGATE 25 25 25 GND 26 GND e 26 GND 15 B4 m 26 nTRKO 1 R1S3 gt R 47 B 1 R178 2 R 47 gt 15 05 PIDERDY E ET IORDY 15 85 SIDERDY IORDY 27 GND 35v 1 diei 28 ALE Sv 28 ALE 1584 WPROT m 6 28 WP 1 R154 2 29 nDACK 1 R179 2 29 nDACK 29 MEDIA mo R 1K 3 GND R
52. 7 A4 8 A4 11 C2 A 25 0 CS 6 0 CN20 TCN 1 TVccl TVccl Reserve IBS WE 3 0 D 31 0 A2 A3 4 5 24 25 0 1 CSS CS6 GND GND CS1 54 1050 Reserve DO D1 D2 D3 D11 TVcc2 TVcc2 WR 120PB VF 1 1 B7 4 E2 5 D2 7 A6 8 E2 1 B7 4 E5 5 D2 7 B6 8 B6 11 D2 1 B7 5 D2 1 B7 5 D2 1 B7 5 D2 1 B7 5 D2 1 B7 5 D2 4 D2 26 5 26 02 26 85 DOMI DQM2 DQM3 RAS TADPCS NMI IN RSTOUT OUT 2 E3 TADP CKIO 33V CN20 TCN 22 e 9 e 9 D12 6 pp DB 4 Dis D14 65 D15 66 pis D16 67 pre 7 68 8 o D19 70 71 GND 72 GND D20 73 pao D21 74 pa D22 75 02 D23 76 D24 TH D25 78 ys D26 79 D27 80 p 4 51 GND 8 GND
53. A5 53 1054 539 4 GcLk1 125 106 m CPURST 16 07 16 5 0 4 1055 90 INs 126 m STATUSO VAS 107 9 a IGNNE 16 D7 16 A5 GCLK0 54 1056 24 B A2 GNDINTs 127 108 20 a INTR 16 D7 16 B5 INI 6 4 1057 2 BAT 128 109 21 NMI 16 D7 16 B5 GNDINTI 27 vecints 33 GNDIOG 129 1010 22 A20M 16 D7 16 B5 GNDINT2 9 vccios 4 1071 130 a IRL3 2 A2 2 F4 1011 23 1033 59 1058 FS 1072 131 m IRI2 2 F42 A2 vccio1 24 1034 0 1059 96 1073 122 m IRLI 2 F42 A2 25 vccios 1 9 B D 31 0 7 A59 A7 10 A6 1060 97 B WEI S0 7 A79 ES 1074 433 m 2 F42 A2 1012 26 1035 DIS 1061 98 BRD 4 C2 7 B8 9 E5 14 LED 7 0 1205 w Z 1036 8 B D14 1062 39 B_WEO 1075 135 LED7 1014 28 1037 64 B 1063 100 B WEI 1076 136 LED6 1015 29 1038 45 2 1064 101 a LEDCS 4 A4 1077 137 LEDS 1016 22 LED RESET 10 D7 GNDIO3 6 4 1065 102 BCRCS 4B2 1078 138 m 1017 2 m LED SLEEP 10 07 1039 67 B Du GNDINT4 193 GNDIO7 139 1018 2 m LED STANDBY 10 D7 1040 8 B 10 GNDIOs 104 4 1079 140 1019 33 m LED NORMAL 10 E7 1041 69 B D9 195 x TDI 10K 10 4 RS DAL 34 TMS 10 10 84 1042 70 B_D8 o6 ws pi STATUS 035 STATUS 10 E2 vccio4 2 17 a DCLK 10 E2 cs 18 1020 36 1043 2 B pATAo 108 m DATAO 10 2 EPF10K30ATC144 EPF10K30ATC144 EPFIOK30ATCIA4 EPF10K30ATC144 E
54. ALi The Super I O control block provides various input device interface The Super I O controller has the following functions 1 PCI device ISA bus interface PCI to ISA Bridge IDE interface IDE Master M5229 USB interface USB M5237 Power management unit PMU M7101 2 Super I O Serial interface UARTI UART3 Parallel interface Parallel Port RTC Lithium battery can be connected Keyboard interface PS2 Mouse interface PS2 FIR interface UART2 FDD interface FDC The Super I O control block has a 14 3181MHz crystal oscillator OSC1 and 48MHz crystal oscillator OSC5 as the operation clock Transfer speed baud rate of serial interface is generated based on 1 8462MHz The Super I O control block has a 32 768KHz crystal oscillator for RTC x2 SH7751R M1543C BI RS 232C CI Bus PCIC Serial connector CN3 CNI2 Parallel Parallel connector CN4 Keyboard Mouse lt gt connector CN5 lt gt USB connector CN6 IDE connector CN13 CN14 FDD connector CN15 Backup battery socket CN32 14 3181MHz Figure7 4 Super I O control block 36 7 2 2 Super I O controller To use various kinds of M1543C Bl embedded modules it is necessary to set configuration data base address and etc to M1543C Set M1543C BI configuration data as follows This configuration data includes using not using each of modules interruption allocation and base address setting of modules of PCI
55. AM79C973AVC Aps 53 PADS BLMGIPSO0SPT Am79C973A VC 4 5 FLI3 R31 55 EBCLK 66 1 2 pvppp 18 Vs p PADS ea R 10K BLM31PS00SPT AD3 EROMCS a EROMCS 22 82 U6 Ap2 58 PAD2 8 65 m AS EBOE 22 2 128 vssBi6 171 60 PAD1 64 CIWP BLMSIPSQOSPT 163 ADI EBWE a EBWE 22 82 vssB15 165 Apo 6 PADO pvpprx 22 9 vssB14 152 4 12 EECS 22 02 pvppnx 126 9 3 141 CIBE3 114 m PC BE3 14 B3 15 D2 23 C2 23 C6 EEDrLED0 135 m EEDI 22 03 pvppco 14 5 12 6 4 CBE2 17 m PC BE2 14 C3 15 D2 23 C2 23 C6 EEDO LED3 130 a EEDO 22 03 E vsspi1 109 4 32 m 14 F3 15 D2 23 D2 23 D6 140 a EESK 22 02 16 Se oe oe g 2z vssB10 15 mm CN sal 48 PC BEOR 14 A6 15 D2 23 E4 23 E7 LEp2 139 m LED2 22 2 pvssP 29 9 5 22 vsspo 94 123 E E E 80 pvssx 123 VssBs 80 158 5 9 137 s B gt E copy 68 CLK a PCI CLK2 2 05 XCLK XTAL CIN AM79C973AVC al Se 2 se 2 vssb7 58 3 1 zu Am79C973A V CGIS Spat oT Ee vsspe 57 156 22 a al 9 a 9 cope 49 INTA m PCLINTA 10 B2 15 E2 23 A2 23 A7 25 A6 VSSBs D 557 a PCI RST 1 A2 23 B4 23 B7 o vssB4 37 sna 29 Cis d vssB3 4 REQ 0160 a 25 47 xTAL2 1 1 2 ND vssp2
56. AUDCK m 1 AUDCK vpps 255 4 vsss 226 4 2 GND 190 209 210 E E E E B 3 IRL3 a IRL3 2 F4 10 C7 VDD7 VSS7 e gt z 9 104 AUDATAO m AUDATAO Sm ze zs ze TREZ 018 112 2F4107C7 vppe 5 vsse 176 vers OT al OT ei Oral IRLI 0188 a IRLI 2 F4 10 C7 vpps 15 4 vsss 146 4 Sms 2478 104 AUDATAI 5 AUDATAI 0187 a IRLO 2 F4 10 C7 1H vss4 12 GND vpp3 7 vss3 28 9 GND GND GND 1C4 AUDATA2 7 AUDATA2 213 TCLK 2 84 vpp2 vss 9 e GND 7 vssi adv aav 33V 53 1 C4 AUDATA3 m 9 AUDATA3 7 vsso GND 1D4 AUDSYNC m AUDSYNC 256 T E E 12 EXTAL m EXTAL 3 87 alee g 237 s 27 158 s L GND KE 07 91 9 41 04 1 OFT OFT B N C IP n2 ie 247 M 248 al 5 al al V 5 5 14 2 5019 248 e 14 GND vppqis F233 vssQis 234 4 1 Inc 255 vppQi7 2 4 VSSQ17 22249 END GND GND GND 1 GND vppaie 207_ 55016 208 107207 TCK m 17 TCK 192 e 191 18 lt 5 VSSQ15 33V 33V 33V 33V 33V Tabs GND vppol4 18 vssQ14 184 4 10727 HDI TMS mw TMS 145 VDDQ13 16 4 vssQia 170 e 2 194 157 158 U EQ U ES UD BS URS UR 21 EXTAL2 VDDQI2 e VSSQ12 e 215 glee 55 2 pl 27 1 D72 E
57. B3 24 B7 25 B4 110 2 a PCS 16 C4 P20 L9 1 R8 2 R 10K AEN m AEN 24 B3 24 B7 OSCI4M a 14M 16 06 19 SLED 16 04 lt s 14 lt 19 3 U32 K12 1 885 2 R 10K x 3 SMEMWJ a SMEMW 24 B2 24 B5 25 B4 CLK32KO m CLK32KO 16 F4 K a SQWO 16 C5 6 1 R303 1 888 2 R 10K SMEMRJ a SMEMR 24 B2 24 B5 25 B4 an CLK 14M 1604 GND6 KH THRM 16 C5 Tow 1 15 N20 1 2 R 33 K10 1 27 2 10 IOWJ a TOW 24 B2 24 B5 25 B2 CLK32K1 9 GNDs K1 m GPIO6 15 B7 AVIS C 22PF ED K9 R 10K IORJ IOR 24 B2 24 B5 25 B2 R Care SG 8002JC 14R3181M PTCB GND4 3v REFRSHJ OY REFRSH 24 B2 24 B5 25 B4 Su ND 1 our vec 4 e DE GND3 22 4 W18 Tn U32 U32 Ju 1 R amp 2 SYSCLK a SYSCLK 24 C2 24 C5 eu GND2 Jl a PCIREQ 16 B5 R17 Am N19 1 2 2 3 1 2 3 11519 95 5 I 1 1 2 R 10K 2 TC TC 24 C2 24 C5 25 D2 CLK32K2 GND OUT ANY OSC 24 C2 24 C5 GND1 IO FERR 15 07 R16 8 F 32 768KHZ C 22PF x 19 1 2 R BALE a BALE 24 C2 24 C5 MIS43C C F 14 3181MHZ GNDo 9 6 Wa a INIT 10 B2 16 A5 SBHEJ OHS SBHE 24 D3 24 D7 1543 68 GNU Ge M1543C 1 Y gt E m CPURST 10 B2 16 A5 Mies 515 Mie 24 D2 24 D5 25 B4 122 123 2 10 iud M1543C 8 8 1 A 2 Pane IGNNE 10 B2 16 A5 1016j DPI m 1016 24 D2 24 D5 25 B4 S e 1 YA 2 m m INTR 10 B2 16 B5
58. Command ML Memory Load Load objects from the host ML offset address Example Ready ML Ready 2ML 000000 Note Program can be loaded by specifying offset addressing only when loaded program does not use absolute addressing only when loaded program is relocatable The operation is not guaranteed when loading a program that executes jumps by absolute addressing by using offset addressing Therefore do not use offset addressing but load to linking address 72 Function FL Flash Load Write data and programs to Flash ROM Format offset Example Ready gt FL Write FL command to Flash ROM as follows 1 Make Flash ROM image on SDRAM Make Flash ROM image on SDRAM by copying Flash ROM data to the first 4 Mbyte area of the SDRAM address 2 Download S format object file Transfer MOTOROLA S format object file on PC to SDRAM MOTOROLA S format object files should be transferred to the following SDRAM address SDRAM address ZMOTOROLA 5 format address SDRAM top address H 0c000000 offset Upper 4 bits of MOTOROLA S format address are ignored 3 Delete FlashROM data Delete all Flash ROM data after the transfer 4 Writing Write first 4 Mbyte data of the SDRAM address to Flash ROM 5 Changing place between Flash ROM and EPROM Change the place between EPROM and Flash ROM by DIP switch setting after writing Programs written to Flash ROM can b by changing the place H 00000000 MOTOROLA Sj Transfer H
59. D28 83 pas D29 84 D30 85 D31 86 Da 87 RD WR 85 RD WEO 89 TWEO WEI 99 rw GND 4 2 GND 93 VTWE2 WES 94 rw 95 CAS0 96 ICASI 97 CAS2 98 CAS3 99 RAS 100 Reserve 101 enD 102 GND 103 Reserve 104 Reserve CS2 105 esp CS3 106 ss 107 ROMCSI 106 am 109 RSTOUT 19 NMIOUT e lll e 112 GND 113 Reserve 114 115 Reserve 116 RoOMCS31 H7 ROMCS21 118 ROMCS4 P 120 WR 120PB VF 1 GND 7 27 2000 14 39 PAGE 6 1 2 5 6 7 SYSTEM BUS 3 3V lt gt 5V B AD3 0 4 29 5 10 86 B D 3I 0 9 7 10 4 10 6 WE S0 9 5 10 6 1A54C46A3 A 25 0 023 1 A4 4 A7 5 B3 6 E3 8 A4 11 C2 D 31 0 U31 1A76E4 WE SO U20 8 B_D31 Al YI 2 2 A2 B2 17 B_D30 A2 2 B3 16 B_D29 A3 A4 Y4 A4 B4 5 B_D28 A4 Y4 _ 33V 20 as pee Ll G GND 10 A6 Be 3 166 GND 10 HD74LVC244AT AT B7 2 B_D25 HD74LVC244AT U23 AS ps AL B_D24 U20 Al Yi 1 B7 4 E2 6 C5 RDWR m 1 RDWR 2 2 G 1 B7 6 A2 13 A5
60. GND GND 7 27 2000 14 39 2 1 2 3 4 SV_ D2 m 083 kH U49 4E2 SCK2 g 3 40 co 2 E 188355 26 CS CPU 2 Al y 8 m SH RESET 1 E5 2 C7 3 D1 E SW MDHONYORED eo 1702 SH TXD2 m J A1 cars 3152 e a2 y2 16 m RESETO 4 E5 4 D4 SW4 2 MD1 ON 0 OFF 1 1 10 6 14 n SWHEMDAONSOFED l o ia 17 E2 SH_RXD2 gt ML tant A3 3 m RESET 10 87 SW4 5 MD4 ON 0 OFE 1 8 3 04 CE2A 16 4 Y4 m RESET2 8 E2 11 D5 11 F2 AC 2 8 oben SW4 6 MDS ON 0ORF 1 amp TE 1 CIR Anja 20 b SW4 a m mw wo 1 G GND 10 19 0412 4 po po Do 105 HD74LVC244AT eo ott i Bl 9 a 105 U49 oo 14 2 105 y e100 18 p3 12 a 105 y2 22 B4 29 a Mp4 105 T 4 e150 SG 8002DC 20M PTCB 17 A4 y4 3 m EXTAL 2B23D1 CHS 06B 13 xe
61. HD74ALVCH16245T 1 C7 SH DACKI 30 A1 yi 9 A DACK1 13 86 2 2 U48 107 SH DACKO m 29 a2 20 13 83 Al 1 2 A 015 13D2 13 B6 DREQI m 27 A3 2 m SH DREQI 1 A4 Y4 A2 B2 3 13D2 13 B3 DREQO m 26 M ya 23 m SH DREQO 1 C7 Hn ME A_D13 G A4 ADL 406 HD74ALVCHIG244T AS Bs 8 HD74ALVCHIG244T Us2 A6 5 13 E2 13 C3 13 C6 058 Al YI AT p 14 1808 2 AI 18 m SLOT IRQS 10 B7 A2 2 8 ps 12 8 A_IRQ7 4 1A2 y2 16 m SLOT IRQ7 10 B7 A3 06 6 A3 m SLOT IRQ6 10 A7 A4 Y4 G A_IRQS 8 A4 y4 2 SLOT IRQS 10 A7 DIR G HD74ALVCH16245T HD74ALVCHIG244T 048 HD74LVC244AT Us2 B1 3 A D7 U58 Al Y A2 2 14 06 y SLOT_IRQ4 10 A7 A2 Y2 A3 16 ADS 13 ay 7 m SLOT IRQ3 10 47 A4 g4 17 A D4 15 5 m SLOT IRQ2 10 47 A4 Y4 AS Bs 9 A_D3 AIROD 17 44 4 3 m SLOT IRQI 10 7 AR pe 20 02 G AT A DI se HD74ALVCHIG244T AS ps 23 HD74LVC244AT U52 13 D2 13 B3 13 B6 WAIT 3 0 056 Al y B 484 ABEN m 206 AWAITS 2 aj y a SLOT WAIT3 4 C4 A2 Y 484 AB DIR m 24 pm A WAIT 4 ay y2 16 m SLOT WAITZ 404 1 B7 A E2 6 C5 RDWR m 33 A3 16 m A RDWR 13 B6 HD74ALVCH16245T AWAIT 6 43 ys 14 m SLOT WAITI 4 04 2 m 32 1A4 ya E A RES 13 C3 A WAITU ya 2 m SLOT WAITO 4 04 254 lt a 33V 0 59 G
62. IK 30 GND 15 A4 m 30 ARDATA 1 R1553 R 47 31 1 R180 2 R 47 m 16 B4 SIRQI INTRQ 16 84 SIRQ2 31 INTRO e 31 GND E 1 g 32 1 52 g 32 32 15 C5 PIDEDAK nIOCSI6 15 85 SIDEDAK 32 MOCSI6 15 A4 HDSEL nHDSEL 15 85 PIDEA1 m 2 T 33 ADRI 15 5 SIDEA1 2 7 33 ADRI 33 MEDIA mi 15 05 PIDEAO m 3 ANY u 34 NC 15 85 SIDEAO 3 Y 6 3 NC 1584 DSKCHG 34 nDSKCHG 15 85 PIDEA2 4 5 35 ADRO 15 05 SIDEA2 4 5 35 HIF3FC 34PA 254DSA 36 ADR2 36 ADR2 FDDUF SON 1 NR45 g B aS 1 NR53 g 15 C5 PIDECSI nCS0 15 E5 SIDECSI 37 nCs0 15 05 PIDECS3 m 2 38 nCs2 15 5 SIDECS3 m 2 38 nCs2 3 6 39 Asp 3 6 39 4 R35 s 40 lt 4 R33 5 40 c tan A GND 27 F2 PIDE LED a HIF3FC 40PA 254DSA 277E3 SIDE LED T HIF3FC 40PA 254DSA 15 87 CHI DETECT w 1 GND PRIMARY IDE 15 B7 CH2 DETECT m 1 2 9 NI SECONDARY IDE 1 RI2 gt R 0 1 R166 2 R20 R 10K 5 R 10K 5 EZ 2102 at Fg D T OTE GND S T Ge alo alo 7 27 2000 14 39 19 1 USB KEYBOARD MOUSE 15 B7 PWR EN 16 B4 USBP0 16 B4 USBP0 16 B4 USBP1 16 B4 USBP1
63. OUTHE O IRQD 15 0 INTB INB ING INTD IND JLCRD 15 0 eErt5 o INT 15 0 INT 15 0 OUTPUT gt lt INT 15 0 INPUT So BNORS INPUT So CPURST IRQA 15 0 INPUT IGNNE IRQB 15 0 INPUT A20M IRQC 15 0 NEUE ILCRF 15 0 IRQD 15 0 IRQE 15 0 IRQF 15 0 INPUT TIRQ 15 0 TIRQ 15 0 J vec level_sel4 1 OUT 15 0 p F NO IRQE 15 0 INB NMI SNG JLCRE S 0 15 0 level_sel4 INA OUT 15 0 o IRQF 15 0 CPURST JJNg IGNNE UNE A20M ZING ILCRF 15 0 SEL 15 0 IRQ Level Controler level cnt OR8 Al7 1 A 7 1 DA 15 0 Do 15 0 OUTPUT gt Do 15 0 BCRCS INPUT BCRCS DB 15 0 RD INPUT RD DC 15 0 ILCRA 15 0 OUTPUT ILCRA 15 0 gt INPUT WE 1 0 DD 15 0 Do 15 0 ILCRB 15 0 OUTPUT ILCRB 15 0 RES WPUT RES DE 15 0 ILCRC 15 0 OUTPUT ILCRC 15 0 DF 15 0 ILCRD 15 0 OUTPUT ILCRD 15 0 6115 01 INPUT Di 15 0 DG 15 0 ILCRE 15 0 OUTPUT ILCRE 15 0 DH 15 0 ILCRF 15 0 OUTPUT 5 ILCRF 15 0 ILCRG 15 0 oureur gt ILCRG 15 0 ilora Anis JLCRH 5 0 gt iW CRH 15 0 Dit
64. Register Secondary h 3F4 MISC AT Register Primary 2 40 pin connector CN13 Cn14 pin assignment Table7 13 shows pin assignments of 40 pin connector CN13 CN14 Table7 13 Pin assignment of 40 pin connector CN13 CN14 ro 2 mK CQ 1 GND ROS sus I 35 A0 ae 2 EE ET Os 1 0 GND CSO Connector Model Name HIF3C 40PA 2 54DSA 0000000000000000 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 ay of ELE Figure7 10 40 connector CN6 46 7 2 9 USB control 1 Register map Table7 14 1 and 2 show the USB controller register map of SuperI O interface Base address initial value of USB control register address is h 00000000 Set configuration data shown in section 7 2 2 SuperI O controller to change base address Table 7 14 1 Register map of USB controller Default Value hOO HcRevision R h 00000110 h 04 HcControl h 00000000 h 10 HclInterruptEnable R W h 00000000 HcPeriodCurrentED h 00000000 HcBulkHeadED h 00000000 HcFmInterval h 00002EDF h 44 HcLSThreshold h 00000000 h 01000002 HcRhDescriptorA h 01000003 h 4C HcRhDescriptorB R W h 00000000 HcRhStatus h 00000000 HcRhPortStatus0 h 00000000 h 58 HcRhPortStatus 1 R W h 00000000 HcRhPortStatus2 h 00000000 Table7 14 2 Register map of USB controller Default
65. Shadow Shadow h 02000000 h 02000000 Expansion slot Expansion slot h 03FFFFFF h 03FFFFFF 5 3 ON 5 3 SW5 4 ON SW5 4 Figure7 13 Area 0 memory map 52 7 5 General purpose Switch Figure7 14 shows a configuration of general purpose switches SW6 to SW9 can detect ON or OFF state from the registers h B9000000 h 19000000 1 2 and h B9000002 h 19000002 1 2 allocated on the memory map This switch is useful for setting IP addresses Read addresses h B9000000 h 19000000 1 2 and h B9000002 h 19000002 1 2 by 16bit access This register is a read only register Physical address when MMU is used 2 When MMU is used do not cache at the time of TLB entry TLB entry C bit 0 General purpose switch area address h B9000000 h 19000000 1 2 SW6 W v 5 8030552050318 3160365 Switch ON Read 0 from bit of corresponding switch Switch OFF Read 1 from bit of corresponding switc General purpose switch area address h B9000002 h 19000002 1 2 AAS Switch ON Read 0 from bit of corresponding switch Switch OFF Read 1 from bit of corresponding switch oz Figure7 14 Configuration of General purpose Switches 53 7 6 8 bit LED Figure7 15 shows the configuration of the 8 bit LED LED1 to LEDS are capable of controlling LED ON OFF by writing data to the register 000000 1 000000 1 2 allocate
66. Two Alias Register DATA3 0000h PCI DATA Register Three Alias Register Z o lt es 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2 lt 33 Table7 3 Configuration of the bus configuration register Programmability Mnemonic Default Reserved Reserved for Am79C975 0000h Reserved for Am79C975 Yes Yes Yes Yes No No No Yes Yes T 4 Ethernet Line Monitor LED CN7 LED1 CN7 LED2 LED14 to LED15 LEDs CN7 LED1 CN7 LED2 LED14 to LED15 indicate the line condition of Ethernet Function of each LED is as follows CN7 LED1 This LED indicates that the line is normally connected When lit the line is normally connected CN7 LED2 This LED indicates the state of reception of the Solution Engine When lit packet is being received LED 14 This LED does not light in initial state LED15 This LED indicates the state of transmission of the Solution Engine When lit packet is being transmitted 34 RJ 45 Connector CN7 Pin Assignments Figure 7 3 shows the pin assignments and functions of RJ 45 connector Type RJHS 5381 Maker Amphenol CN7 LED1 Transmit Data Transmit Data Figure 7 3 RJ 45 connector 35 7 2 Super I O control 7 2 1 Block Diagram Figure7 4 shows a block diagram of the Super I O control block The Super I O control block has a controller M1543C B1 manufactured by
67. Value h 100 HceControl Register R W h 00000000 h 104 Hcelnput Register h 000000xx h 108 HceOutput Register h 000000xx h 10C HceStatus Register h 00000000 47 Pin assignment of USB interface connector CN6 Figure7 11 shows pin assignments and functions of USB interface connector CN6 Connecter Model Name USB1112C D1 Pin assignment of USB connector CN6 PinNo Signal I DATA GND Board side Figure7 11 USB interface connector CN6 48 7 3 PCMCIA Control 1 Block description Figure7 12 shows a PCMCIA control block As shown in figure7 13 the PCMCIA control block has a controller Marubun supplied MR SHPC 01 V2 a 68 pin IC card connector molex supplied 53409 6810 and a power control IC TI supplied TPS2211IDB The PCMCIA control block provides ATA card interface and I O card interface via a 68 pin IC card connector This controller provides system interface with ATA card based on PC card standard 97 and I O card This controller has following features Support 68 pin card slot based on PC card standard97 2 memory windows and one I O window incorporated Card access timing adjustment function incorporated Read Write buffer incorporated Endian control on chip circuit Support 5 0V 3 3V card External buffer is not necessary Interrupt steering function incorporated Power down function incorporated Suspend function incorporated Marubun supplied System Bus Interface PCMCIA controll
68. Y Use IDE Y Connect IDE cable to CN13 primary and CN14 secondary N Connect FDD Y Connect FDD to CNIS Set jumper pin Connect ATX power supply to the Solution Engine Installation is completed Figure2 1 Installing the Solution Engine 2 1 Connecting the host system To use the monitor program connect the host interface connector CN2 to the host system via an interface cable Figure2 2 shows how to connect the host system Host Interface Cable 9 pin cross cable Host System FLORA310 or equivalen Figure 2 2 Connecting the host system 1 Host Interface Cable For example Figure 2 3 shows the wire connection when FLORA310 is connected to the Solution Engine The Solution Engine can be connected to the host system via an off the shelf 9 pin cross cable FRORA310 Solution Engine 9pin connector CN2 2Pin RxD RxD 2Pin 3Pin TxD ae TxD 3Pin SPin GND 5 7Pin RTS RTS 7Pin 8Pin CTS CTS 8Pin DTR 4Pin DSR Figure 2 3 Wire connection between FLORA310 and the Solution Engine 2 Transfer Speed Setting 9600 19200 38400 and 115200 bit s can be selected as a transfer speed with DIP switches SWS 1 SW5 2 on the Solution Engine Set the DIP switch according to the transfer rate For specifications of the DIP switch refer to Section 3 1 4 DIP switch SW5 for setting baud rate 3 Host Interface Connector CN2 Figure 2 4 shows the pin assignments of the host interface
69. board resource disable 3 12 9 2 5 ON Boot EPROM 2C7 3 A7 SH RESET m D Q D Q Oro fi 1 8 3 6 SV N mod n n iNormal mode CK QO OFF DBG mode CLR 3 3 14 3 3 14 GND 7 GND 7 HD74LVC74T HD74LVC7AT aft 1 R80 gt mu n CE2A 3 A3 3 B7 EXTAL e 1 R78 2 Win a CE2B 3 A3 1 RB 2 22 x 101516 3 B3 OSC3 33V SG 8002JC 3R6864M PCCB 1 ogsT VCC 4 2 3 GND OUT m CLK 3M 4 D4 F 3 6864MHZ 159 C 0 1UF MS V 25V GND 7 27 2000 14 39 PAGE 3 1 2 3 4 6 SYSTEM CONTROL FPGA FLASH MEMORY 1 A5 4 C4 6 A3 25 0 D 31 0 1 A4 5 B3 6 E3 7 A4 8 A4 11 C2 33V 33V MI 016 YP7601x B_A 23 0 7 A39 A5 10 BG 016 YP7601x AA 9 A19 DOIS A L 45 Dat LL 26 A20 16 A18 014 43 D30 101 2 1020 27 LEDCS 10 C6 A19 17 A17 4t 029 vccioo 2 1021 18 48 A16 12 32 D28 4 m ISP TDI 4 F2 1022 2 A17 l 15 36 m 102 1023 30 16 2 Ald 1 34 226 103 6 1024 3 15 3 AI pgs 32 D25 104 7 1025 32 9 C2 4 lan 30 D24 105 8 1026 33 9 F2 A13 5 lau 4 D23 106 2 BCRCS 10 C6 34 A12 6 A10 2 022 107 1027 mBBEN 704 7 A9 pos 40 1H 1028 36 m AB DIR 7 DAS DA 10 8 ag
70. by JAE Daughterboard side connector 2 14 140 5 1 made by JAE gt Daughterboard 1 Daughterboard side connector 1 KX15 140K4D1 made by JAE p gt Solution Engine side connector KX14 140K5D1 made by JAE gt Solution Engine 9 3 Daughter Board Dimensions Figure9 2 shows the dimensions of the daughter board to be mounted on the Solution Engine When a user design a daughter board originally design the board with dimensions shown in figure9 2 Figure9 2 Daughterboard Dimensions unit mm 58 10 I O Connector CN1S Table 10 1 lists the functions of I O connector CN18 I O port timer output pin and SCI signals are connected to the I O connector Use this connector to control by using the I O port Solution Engine side connector 8800 080 170S KEL I O board side connector 8810 080 170L right angle KEL 8810 080 170S straight KEL Table 10 1 I O Connector Functions Signal Name Pin No Pin No z 28g zzz 21 22 23 24 25 26 27 Z z Z Z 2Z Z i gOizzzzzuzzzgglzzxEzuuzz alalalalala ZZ 3 BE EN 5 DC NEN Log di ONG I 10 Nc u GND porc GND Nee ij 15 NC i NO 7 18 dur CUNG uj lt
71. connector CN2 and the list of signals te S 3 pp Oups Seid 4 DTR output data terminal ready ut Ps figs 9 NC Figure 2 4 Pin Assignments CN2 10 2 2 Connecting the E10A emulator This Solution Engine has a debugging chip Note on the SH7751R and SH7751R E10A emulator can be used Figure2 5 shows how to connect the E10A emulator The PCMCIA card emulator that is main unit of SH7751R E10A emulator can be connected to the connector CN19 via H UDI port Hitachi User Debug Interface The E10A emulator connectable to the Solution Engine is as follows For more details on the connecting method and the E10A emulator setup refer to the following manual Hitachi Co Ltd E10A emulator HS7751RKCMO02H PCMCIA Note Debugging chip is same as actual chip E10A main unit PCMCIA card HS7751RKCM02H User Interface connector Figure 2 5 Connecting the E10A emulator 1 2 3 Connecting the power supply 1 Connecting ATX power supply SH7751R Solution Engine uses ATX power supply option product as a power supply Connect the power supply to as shown in figure2 6 Notes Before connecting the power adapter recheck the board and cable are correctly connected and check the jumper pins and DIP switch are correctly set AC 110V power supply Figure 2 6 Connecting the power source 12 3 Switch Functions 3 1 Switch SWn functio
72. device and Super I O 1 Configuration of PCI device Configuration of PCI device is performed by configuration cycle of PCI bus For data of configuration register of each device refer to SuperI O M1543C manual PCI device number of each device is as follows ISA bus interface IDSEL AD18 IDE interface IDSEL AD27 USB interface IDSEL AD31 IDSEL AD28 2 Configuration of SuperI O Perform configuration of SuperI O as follows Address described below is address of PCI I O area 1 Write 0x51 and 0x23 to CONFIG PORT 0x000003FO0 twice By this FDC37C935A enters into configuration data setting mode 2 Set INDEX to INDEX PORT 0x000003F0 and set configuration data from DATA PORT 0x000003F1 3 After setting configuration data go out of configuration data setting mode by writing 0xBB to CONFIG PORT Refer to manual of super I O M1543C B1 for details on configuration data 37 7 2 3 Serial Controller 1 Register Map Table 7 4 lists the memory map of M1543C B1 super I O serial controller Base address initial value of serial controller register is UART1 h 03F8 UART3 h 02F8 Set the configuration data as shown in section 7 2 2 Controller Table 7 4 M1543C Super I O serial controller register map h 0 h 000003F8 R 0 RBR Receiver Buffer Register THR Transmitter Holding Register DLM Divisor Latch MSB IER Interrupt Enable Register CN LCR Line Control Register
73. map Address h 000003F0 h 000003F1 h 000003F2 h 000003F3 h 000003F4 h 000003F5 h 000003F6 h 000003F7 Table7 10 lists the register map of a super I O floppy disk controller FDC Base address initial value of the Superl O floppy disk controller is h 3F0 Set configuration data shown in section 7 2 2 SuperI O controller to change base address Table 7 10 Register map of the floppy disk controller FDC Register Register oe Status RegisterA Status RegisterB a TDR Reef 1 CC DIR Digital Input Register R Configuration Control Register Pin assignment of a floppy disk interface connector CN15 Table 7 11 lists pin assignments of the floppy disk interface connector pin CN15 Table 7 11 Pin assignment of the floppy disk interface connector pin CN15 Pin Signal name No ignal n 1 0 ND D Figure7 9 floppy disk interface pin connector CN15 45 7 2 8 IDE controller 1 Register map Table7 12 lists the IDE controller register map of super I O interface Base address initial value of IDE controller register address is h 170 secondary and h 1FO primary Set configuration data shown in section 7 2 2 Superl O controller to change base address Table 7 12 IDE controller register map Bank1 Register Set h 170 Task File Register Secondary h IF0 l Task File Register Primary h 374 MISC AT
74. the offset 2 The object file data of address from H 0000 to H OFFF is not transferred to user memory when specifying the offset 1000 Flash ROM data is not changed when specifying the offset 1000 and writing the object file with address from H 0000 to H OFFF to Flash ROM 74 Function RR Register Read Read all registers Format RR Example Ready gt RR Function RW Register Write Writes to the corresponding register Format RW lt regname gt data Example Ready gt RW RO 12AB Function Clears all registers to 0 Example Ready gt RC 75 ME Memory Edit Word access Long word access Format ME lt address gt option Example Ready ME 000000 Ready ME 000000 W Ready ME 000000 L Command MD Memory Dump Dumps memory Displays in ASCII code MD start address end address Example Ready gt MD Ready MD 0 Ready MD 0 200 A Fills by specified data MF start address end address option Example Ready gt MF Ready MF 000000 000200 Ready MF 000000 000200 55 76 Function DA Disassemble Disassembles from the specified address DA start address Example Ready gt DA 000000 Command Executes from the specified address None Format G start address Example Ready G 000000 Step from specified address Option start address Example Ready gt S AC000000 TI
75. wait status Ready gt me ac 100000 AC100000 03 AC100001 61 68 11 Writing to the Flash ROM Use the fl command to transfer the user program to user RAM and to write to Flash ROM Input the fl in command standby mode as follows To write to Flash ROM erase Flash ROM and start writing to Flash ROM Figure13 2 shows the procedure to execute user programs from Flash ROM after completion of writing user programs to Flash ROM Offset is necessary When offset is not used set offset to 0 Ready gt fl offset After input following transfer request message is output from the monitor program and the message is displayed on the host system screen Flash ROM data copy to RAM Please Send A S format Record After the message is displayed send the S format object file by using the file transfer function of communication software S format object file has address information Place object program according to this address information If it is relocatable file which address is not specified in object file specify offset address with the fl command Specify the address within the user area shown in figurel3 1 Following message is displayed on the host system screen after completion of loading to memory In this example program is loaded from h A0000000 address of area3 Start Addrs A0000000 End Addrs A00044BE Transfer complete Erasion of Flash ROM is started and the following message is disp
76. 0 B 0000100000000000 B 0001000000000000 B 0010000000000000 B 0100000000000000 B 1000000000000000 Ne Ne Ne Ne Ne Ne Ne Ne e MS7751RSE01 Parts list 1 QTY DEVICE MAKER REFDES GRM39F104Z25PT MURATA C1 C2 C3 C28 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C42 C44 C46 C47 C48 C49 C50 C53 C55 C56 C58 C59 C60 C61 C62 C63 C64 C65 C67 C68 C69 C70 C72 C73 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C95 C96 C99 C100 C106 C107 C110 C113 C116 C117 C118 C119 C120 C121 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C164 C167 C168 C169 C174 C177 C178 C179 C180 C181 C182 C183 C184 C187 C188 C189 C191 C192 C193 C194 C195 C196 C197 C198 C199 C200 C201 C204 C205 C208 C222 C223 C225 23 GRM39CH101J50PT MURATA C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C24 C25 C26 C27 C51 C162 C163 GRM39CH181J50PT MURATA C20 C21 C22 C23 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 269M1602226M C29 C30 C94 C109 269M1602335M C41 C71 C151 C170 GRM39F103Z50PT T C43 C45 C54 C57 C66 GRM39CH470J50PT T C52 C74 C171 C172 SME25VB100M NIKKEM 97 98 105 111 MURATA A A I 4 TA C101 C102 C103 C104 2 oRwseF4TSZ2SPT MURATA CIOSCIH TA GRM39C
77. 0 5 540 502 50 0 4 05 054 0 0 1 B 1111110 0 1 0 x gt 0 0 0 1 0 0 0 0 0 0 1 0 B Qxxxxxx 1 1 20 20 2452 0 054 09270 02 841111110 942 hp 2 070 0 50 0 0 0 12 d 0 QW ci 0 Oy 20 20 320 1111110 1 x x x gt 0 0 0 1 0 0 0 0 0 0 1 0 51 1111101 x x x 0 gt 0 0 0 0 1 0 0 0 0 0 1 0 o oe oe oe oe oe 995 oe oo oo oe oe CSOEN DBG ROMSEL CSOEN DBG ROMSEL CSOEN DBG ROMSEL CSOEN DBG ROMSEL CSOEN 54 06 OFF OFF OFF o oe oe oe oe oo oo B 00xxxxxx 01 10 K 11 CS2 Area 5 CS4 Area 55 56 0 01 10 11 END TABLE 11 1 1 Br 11 101 011 011 011 011 011 11101 11
78. 000 R5_BANK 00000000 6 00000000 R7_BANK 00000000 Control Registers SSR 600000E0 SPC AC10003A GBR 00000000 SR 700000E1 VBR 00000000 MD RB 1 1100 01 System Registers MACH 00000000 MACL 00000000 PR 00000000 PC AC10003A Step user program Step the program transferred to user memory with the s command Input the s command as follows Ready gt s ac100000 When the s command is executed instruction of executed address is displayed Ready gt s ac100000 AC100000 0009 NOP Ready gt 67 10 Set Breakpoint Set a breakpoint with the bs command Input the bs command as follows The breakpoint is set at address h AC100010 by inputting the bs command When the program is executed under this condition a break is occurred at address h AC100010 and user program is aborted This break is generated by replacing the instruction of the said address with an illegal instruction It is impossible to break read only memory Ready gt bs ac100010 Use the bi command to disable the breakpoint set previously Ready bi PC Break Address 0000 AC100010 Using the be command enables the breakpoint disabled by the bi command Ready gt be PC Break Address 0000 AC100010 Change memory contents Use the me command to change memory data Input the me command as follows If characters other than hexadecimal number are input the program come out of the me command and goes into command
79. 00000FFF H 00000000 H 003FFFFF H 01000000 H O013FFFFF 871 2X 25 H 0c000000 O 5 57 22224 73 offset The transfer address for downloading MOTOROLA S format object files to SDRAM can be adjusted by specifying the of on command input The final Flash ROM address can be specified by adjusting the transfer address 1 When running the program written to Flash ROM right after power on reset 1 Place the program at area 0 of SH microcomputer to run the program on Flash ROM Link the program to place the program at area 0 on MOTOROLA S format object file generation 2 It is necessary to set the offset to 0 to download the object generated in process 1 Ttansfer the object to top address of SDRAM by setting the offset to 0 Example Ready gt FL 0 H 00000000 5 1 H 0c000000 MOTOROLA S format object fik d H OcO00FFF SDRAM d 2 When writing the data of address H 1000 to address H 0 1 MOTOROLA S format object file should be transferred to the following SDRAM address SDRAM address MOTOROLA format address SDRAM top address H 0c000000 9ffset Specify the offset to write the object of address H 1000 to address H 0 Obtain the offset as follows offset MOTOROLA S format address SDRAM top address H 0c000000 SDRAM address H 1000 H c000000 H c000000 H 1000 Example Ready gt FL 1000 NOTE 1 Be sure to specify the offset It is impossible to write normally without specifying
80. 02 25 2 18010 m 03 LA22 15 C7 24 D5 25 E2 mor LA21 15 C7 24 D2 25 E2 IRQU m D4 mor LA21 24 D5 25 E2 IRQI2 D5 rRon gt LA20 24 D2 25 E2 IRQI2 w DS mor LA20 15 C7 24 D5 25 E2 IRQIS m D6 mors LA19 15 C7 24 D2 25 E2 18015 w D6 LA19 15 7 24 05 25 2 18014 m 07 moi4 LAIS 15 C7 24 D2 25 E2 IRO14 m D7 LA18 15 E7 24 D5 DACKO m DS DACKO 1 17 15 E7 24 D2 DACKO m 085 DACKO 15 D7 24 D5 25 C4 DREQO m 09 MEMR x MEMR 16 D2 24 D725 F2 15 D724 D225 CA DREQO D DRQO MEMR 16 D224 D325 F2 15 7 24 05 DACKS m D10 packs MEMW DC m MEMW 16 02 24 07 25 2 I5 E724 D DACKS m D10 _pACK5 MEMW m MEMW 16 02 24 03 25 2 15 D724 DS2S CA DREQS DH pros 08 15 D724 D225 CA DREQS Di pros 08 15 7 24 05 DACK6 m 2123 pACK6 559 15 E7 24 D2 DACKG m 0127 pACK6 09 15 D7 24 D5 25 C4 DREQ6 D13 SD10 15 D7 24 D2 25 C4 DREQ6 D13 SD10 15 7 24 05 DACK7 m 4 pACK7 SDI IS E724 D DAck7 SDH 15 D7 24 E5 25 C4 DREQ7 D1S 7 SD12 15 07 24 2 25 4 DREQ7 015 7 5012 D16 SD13 D16 SD13 24E5 25 C4 MASTER m MASTER 04 24A E225 CA MASTER m MASTER 5014 t 1018 GND 015 018 GND 015 z R MCR60A 98D 254DS LAI23 17 16 A2 24 E7 25 F2 MCR60A 98D 254DS LAI23 17 16 A2 24 E3 25 F2 77 1 era er SD IS S 15 7 24 7 25 4 SD 15 8 15 7 2
81. 0FF h 1E20010 h 1E200227 H 1E200228 h 1E23FFFF h 1E240000 h 1E27FFFF H E280000 h 1FFFFFFF Expansion Area5 Card controller LSI area manufactured by MARUBUN Model name MR SHPC 01 V2 General purpose area switch Area for debug LED Test mode area PCI memory space Access area PCIC register PCI configuration register area PCIC register PCIC local register area PCII O space Access area Figure5 1 Memory map Expansion Area5 Expansion slot CS5 assert Memory and register must access to this area This area reads general purpose register x2 Area for debug LED Single LED x8 Area for testing the Solution Engine This address is not open to users Do not access to this area 2 3 3 3V Bus 5V Bus PCI Bus 6 Hardware Configuration Figure6 1 shows the block diagram of Solution Engine As figure6 1 shows there are 3 3V bus 5V bus and PCI bus Memory including SDRAM and Flash ROM are connected to 3 3V Bus to execute user program at high speed EPROM is 5V bus interface EPROM is connected to SH via 5 conversion buffer This PCI Bus used SH7751R PCIC M1543C B1 Am79C973AVC and 2slot of PCI bus slot are connected to PCI bus 24 ST AUD connector CN19 _ PCMCIA 3 3V Interface 4 70 5V Interface card slot CN17 8bitLED 16bit DIP IMB switch EPROM MX27C 8100PC 10 HD74LVC244AT RJ 45 CN7
82. 10IS16 076 a PIOIS16 12 2 025 CRESET 227 P RESET 1 3 86 RA2S XCINPACK Of m PINPACK 12 03 2 O P VS2 12 C3 HD74LVC08T 88 a 3 3V 14 39 XVSI a P_VSI 12 B3 GND 7 89 8 xcvccs 50 a 11 05 3 04 MDS 93 ENDIAN xcvccs 8 a 5 11 05 5 TEST 78 11 05 cvppo 7 m VPPO 11 05 I sle 1 11177 CARD PW m CARD PW GOOD v Em 35 CARD VCCI 9 m CARD 11 7 12 82 12 83 2 E3 PCIC CKIO m 91 CARD vcc2 43 63 3 47 RESET m X T CARD VCC3 s 5 g o 5 o SZ MR SHPC 01 OT TU OT TL OT TL 5 Q Q o o Q 3 3V 14 55 90 127 E a a a a GND 1 18 57 56 73 92 109 121 131 140 7 27 2000_14 39 GND GND GND GND PAGE 11
83. 1101 111101 11101 11011 01111 X X X X X X X X OGOGO gt H OGO G OOOO gt lt gt o oe o oe oe R SHPC 01 o oe o oe o oe OR2 RES_WAIT INPUT RES_WAIT PC_RDY INPUT PC_RDY lt SWAIT 3 0 gt SWATT S 0 PC CS INPUT PC CS BEA INPUT BEA BOR6 PC RDY NAND2 RES_WAIT PC CS lt SWAIT3 ams BNAND2 DFF SWAIT2 A BEA SWAIT1 DD ore SWAITO gine CKIO INPUT RES INPUT DFF PRN D Q CLRN RDY OUTPUT gt RDY RDY Wait controler wait_cnt NOT BNAND2 RES To CLK_3M INPUT CLK SM WAIT OUTPUL J gt RES WAIT RES INPUT RES VGC OR2
84. 19 Exp P DIS 15 vns 50 RD DI9 85 pio in D20 16 A GET 51 D21 86 8 B8 A_BS BS D20 8 B7 13 B6 A WE 3 0 e l GND D21 121 A_D22 17 A_WE0 52 A_D23 87 8 7 13 83 WE 3 0 7 GND D22 023 EWE 12 18 A_WE2 53 88 WE2 e GND 123 wks A D24 19 54 A_D25 89 D24 8 D6 13 D2 13 B6 WAIT 3 0 4 GND D25 um 124 D26 20 A WAT 55 D27 90 8 D6 13 D2 13 B3 WAIT 3 0 22222 14 GND D26 WAITO D27 EWANI 125 A_D28 21 WAIT2 56 A_D29 91 WAITI D28 WAIT2 D29 A WAIB 126 A_D30 22 D30 8 C6 13 E2 13 C6 A IR 57 16 A_D31 22 x 13 2 IRQIS 1 GND D31 EERS 127 33V 5 A IRQI 58 93 8 C6 13 E2 13 C3 180 8 1 127 GND k 3 3V IRQ1 3 3V A IRQ2 128 RQ2 24 aav 1803 59 Ros 33V 94 1 ay 1804 129 25 x 5 60 95 Q 25 433V 1806 130 26 1807 61 96 Q A0 Al 1808 131 Ros A_A2 2 La SV 62 sy A A3 97 A3 132 3 _ 4 28 4 63 sv 5 98 As m A A_AG 29 5 64 7 99 iu 30 65 100 5 e GND 8 E3 A RES RES GND T 135 M A8 31 as 66 9 101 1 es A A_A10 325 2 0 4 67 A AIL 102 rg 2 33 Ap 6 xe A_A13 103 4 AM 69 15 104 A15 a 35 lt 70 105 NC6 e
85. 2 D6 62 m ISP 4 2 GCLK1 87 m FPGA CKIO 2 E3 AT 7 A9 pos 40 Ds 1049 63 88 10 8 Ag po4 38 D4 1050 m FROMCE 4 5 GCLR C82 m RESETO 3A7 A9 18 A7 35 1051 65 TADPCS 6 05 OEYGCLK2 30 CLK 3M 383 AS 19 A6 DQ2 33 D2 Vccros 66 31 AT 20 As pai 2 D1 1052 4 1068 32 0 A6 21 A4 22 DO 1053 8 a 72 1069 3 esr AS 22 1054 99 PCRDY 11 86 11 02 1070 24 54 4 23 1055 0 24 ay 1056 3 a RDWR 1 B7 5 D2 6 C5 7 A6 8 E2 1071 2 25 A0 1057 72 SH SCK2 3 43 1072 97 C86 33V 3 73 TDO 4 2 1073 98 1 872 47 BYTE d GNDs 4 1074 9 260 CE AV 1058 75 18 1075 100 RDY 1107 0 e 38 EPM7128ATC100 EPM7128ATC100 WEL Ho WE o 9 Eu T EPM7128A 3 4 EPM7128A 4 4 ONT As a 402 m 4 0 RESET 5 1 B7 6 C5 RD MBM29LV160TPFTN END 7 pi 3 A7 m REDAY BUSY z 3 3V CN23 402 ISP m l TCK 2 GND 482 ISP m 3 TDO 4 Vec 33V 33V 33V 33V 4 B2 ISP TMS m TMS NC NC 12 55 e 8 NC 5 91 Osi 0 91 gt gt gt gt dA2 ISP TDI w 9 TOI asi al E l 19 GND FFC 10BMEP1B GND GND GND GND 7 27 2000 14 39
86. 2 U26 Avccs B 9 m CARD 11 F4 12 B2 12 B3 010 CD10 Avcc2 12 2 5 11 EL SD9 CD9 9 5V1 AVCCI 158 08 CDs 6 STFA SD7 CD7 SD6 CD6 e 33V 1 05 4 33V 2 SD4 CD4 19 m CARD VPP 12 B2 12 B3 SD3 CD3 E SD2 CD2 oo A EM 8 1 CDI 11 E4 VCC3 VCCDI oT aS 550 11 F4 VCCS m lcj vccpo 8 11 F4 VPPI m 1 B7 6 A2 BS m 62 xBs XCCE2 025 P 12 B3 11 F4 0 w 15 vpppo 492 PECS 7 xcs XCCEI P 12 82 1 B7 6 C5 RD w XSRD XCIORD OA a PIORD 102 83 L160 SHDN GND WEE 502 XSWEI XCIOWR 53 a PIOWR 12 B3 TPS2211DB U25 ius XSWEO XCOE 026 POE 1282 GRD 1 3 ERN e pc Em 5 CARD PW 11 F2 4D2 11 B6 PC RDY m XSWAIT XCWE PGM P WE 12 82 m LI uvm epee 256 4 HD74LVCOST 1A76E4 WE 3 0 CBVD2_SPKR E PBVD2 12 C3 m by 3v 10 B7 11 A6 PC SIRQ3 SIRQ3 CBVDI STSCHG a PBVDI 1203 GND 7 10 B7 11 A6 PC SIRQ2 142 SiRQ2 XCCD2 077 P CD 12 03 a 025 PE Z r E 10 B7 11 A6 PC SIRQI 1437 SIRQI P CDI 12 43 BR a 55 m gtiaie gt 29 10 B7 11 A6 PC SIRQO m 14 51800 BSY IREQ D PRDY 12 2 pa wp OTA 5 XCREG 0 PREG 12 03 E B 9 HD74LVCOST 3 25 3 3V 14 11 BS SSPKR OUT SSPKR_OUT XCCWAIT a PWAIT 12C3 GND 7 11 BS SLED OUT m 835 SLED_OUT CWP X
87. 23 2 250 OSC2 33V P 1 RIO 2 R 22 1 RS8 2 VSS PLL2 259 4 SG 8002JC 33M PCCB 4 m PCLCLK2 2102 1072 87 HDI TCK m Me HD6417751RF240 1 om vec 3 e oas 7 1 2 m 15 2 um SH7751RG 7 1072 87 HDI TMS mw 1 2 3 gt I 2 P 19 1 R100 2 R 10K GND out 5 INB OBI m PCI 1A2 12 opp 18 R22 15 R57 gt F 33MHZ OEB 2 1D72 C7 TDI m 1 2 PCI Clock 33MHz 27 R 10K C72 2 3 PCI Clock SH7751R CKIO 3 Res i gt os4 5 1 D72 C7 1 2 C 0 1UF 14 R 10K 0 OBS Lik V 2sV RS GRD 13 1072 87 HDI TRST m 1 33V R 10K UB i GNDQ CKIO w 1 REF 2 1 2 SLOT CKIO 8 82 5 3 1 R4 2 R 22 16 20 CLKA2 m PCIC CKIO 11 F2 e l cue 22 16 14 1 R45 2 R 22 ae s FBK CLKA3 m SD 5 04 IDT49FCT3805PY 15 1 RN 2 R 22 CLKA4 m SD CKIO0 5 02 cn R22 1 2 R46 t CLKB1 1 Wy 2 TET m FPGA 404 Do Not poster CLKB2 1 2 m TADP_CKIO 6 5 R210 I R 10K CLKBS O a R44 t 7 1 2 R eria tt 1 2 R HUF CY2308SC 1 Los ND 33V413 O GND m GND S 12 33V 1 5672 TCLK 2A2 33V 33V 33V 33V 1 859 2 R 10K T 9 IRL3 2 2 10 7 1 R56 2 R 10K eco a IRL2 2 A2 10 C7 E rt a gt gt n P gt lt gt gt 2 a IRLI 2 A2 10 C7 Si sm _ 1 R50 2 R 10K I OTT OT OT sf IRLO 2 2 10 7 a 5 al 5 al alo R 10K GND GND
88. 3 15 02 21 02 23 2 23 6 22 a4 23 POBE 01 3 BE 01 SN74CBTD3384PW SN74CBTD3384PW U10 GND PCI AD23 3 A0 2 PAD23 PCI AD22 8115 PAD22 PCL AD21 ape ml PAD21 PCL AD20 8 ml PAD20 Mag 10 d pe SN74CBTD3384PW 010 PCI AD19 14 A0 Bo 15 PADI9 PCI ADIS 71 81116 PADIS PCI AD17 18 mL 7 PCI AD16 21 3 20 PAD16 1A2 C BE2 m 22 a4 25 2 15 02 21 02 23 2 23 6 13 5 24 GND 12 SN74CBTD3384PW Un 102 PCI FRAME m 3 Tao Bo 2 m PFRAME 15 D2 21 E2 23 C4 23 C7 25 B6 1D2 PCLIRDY m 4 A B1 5 m PIRDY 15 02 21 2 23 2 23 6 25 6 12 TRDY m 7 A2 p2 6 m PTRDY 15 D2 21 E2 23 C4 23 C7 25 B6 1 2 PCI DEVSEL m 8 B3 2 m PDEVSEL 15 02 21 2 23 02 23 06 25 86 1D2 5 m H a4 g4 PSTOP 15 D221 E223 D423 D7 25 B6 041 SN74CBTD3384PW Un 112 PCI LOCK m 14 49 po 15 m PLOCK 23 D223 D625 B6 1E2 PCI PERR m 17 pi 16 m PPERR 21 E223 D223 D625 B6 12 SERR m 18 A2 2 9 m PSERR 15 D221 E223 D223 D625 B6 102 PCI 21 20 PPAR 15 D2 21 E2 23 D4 23 D7 22 ag 23 BOBE SN74CBTD3384PW 1 2 m 3 0 2 m PCBE1 15 02 21 02 23 02 23 06 PCI ADIS 4 a 5115 PADIS PCL AD14 71 ml 4 PCLADI3 8 43 nl PADI3 PCI ADI2 ja MEC 2 1 5V 24 BE GND D SN74CBTD3384PW PCI AD11 M 15 PAD11 PCI AD10 Ua
89. 4 3 25 4 a a sv GND GND 1 R20 2 R220 CN10 B1 B3 R 47 1 R221 2 R221 CN10 B29 B31 R 47 1 R225 R222 CN10 D16 D18 R 47 GND 7 27 2000 14 59 24 1 2 5 6 7 8 SV SV_ 33 15 E424 A3 24 A7 SD 7 01 15 7 24 324 7 15 8 SD7 1 56 g SD8 1 35 8 1 NR38 g E 1 NRH g 9 9 10 B215 E221 D223 A223 A7 PCLINTA 9 1 F2 21 D2 PCLREQI m SD6 2 7 e SD9 2 7 10 2 15 2 23 4 23 6 PCLINTB m gt 7 1 E2 15 E2 PCLREQ4 m 2 E 05 3 6 lt SD10 3 6 4 10 B2 5 E223 A223 A7 PCLINTC m 3 6 4 3 ame 15 C7 24 A2 24 A5 IRQS w 4 5 SD11 4 5 10 B215 E223 A423 A6 PCLINTD w 4 5 4 5 R 82K R 82K R 27K R 82K NRS7 NR36 NRI6 NRI2 SD4 SD12 1 4 3 B3 23 B2 PCI REQ2 mg E 5 18221002 PCI m 8 SD3 7 5015 2 7 3 B323 BG6 PCI REQ3 m 2 7 1E2 23 B4 PCI m 2 7 502 3 6 9 SD14 3 6 4 14 D3 15 D2 21 E2 23 C4 23 C7 PFRAME 3 6 4 1E2 23 B7 GNT3 m 3 6 SD1 X 015 X S 14 03 15 02 21 2 23 2 23 6 PIRDY 1 E2 15 E2 PCI GNT4 m EM x NR9 5 NRS NR18 16 B2 24 A3 24 A7 SA 19 0 8 16 C2 24 B2 24 B5 NOWS 1 8 14 D3 1
90. 419 M u oe lt MM ds 22 22 DA 44 Pod Pod 9o 4 4 N ee 4 ee 69 19 e e e ej 44 48 085555555548 8 Bee 9 Sesee f nje SA Wax V V V V C De 999 8 B 44 sss esses e esses gs oe sss eh B n 68 Y un j gt f S 9 S H 76 7SL gt 9 04 AT x OL EE ZZ 79 E7Z MS7751RSE01 External dimensions PCB EDGE CNS L7 9 9 9 9 6 6 013 149 9 9 9 9 25 1 9 4 12 CN3 T 910 CN4 45 16 23 42 75
91. 4LS07FP U27 HD74LVC14T 9 8 RG GND7 HD74LS07FP GND 3 3 5 14 GND QD 7 27 2000 14 39 27 25 18 CS 6 0 ROMSEL DBG CSOEN CS6EN RDWR PC_RDY SWAIT 3 0 CKIO RES CLK_3M SCIF 1 0 B A1 B RD INPUT A 25 18 EPCE INPUT INPUT decoder INPUT INPUT INPUT INPUT So OUTPUT CS 6 0 FLCE OUTPUT TADPCS OUTPUT OUTPUT PC CS SWCS LEDCS BCRCS OUTPUT OUTPUT NOT ECSO ECS1 OUTPUT OUTPUT ROMSEL ECS6 OUTPUT DBG CSOEN BEA OUTPUT CS6EN BEB OUTPUT UU UUU UU UUUU OUTPUT INPUT wait_cnt INPUT INPUT PC_CS BEA INPUT PC_RDY RDY SWAIT 3 0 RES WAIT PC CS BEA CKIO RES gt DIR OUTPUT INPUT INPUT INPUT SWCS res_wait CLK 3M RES WAIT RES cpg CLK 3M SCK gt OUTPUT SEL 1 0 NAND3 OUTPUT INPUT E NAND3 OUTPUT gt L gt gt SCK gt SWRD1 EPCE FLCE TADPCS PC_CS LEDCS BCRCS ECSO ECS1 ECS6 BEA BEB Main controler YP76010 SUBDESIGN decoder
92. 5 D2 21 E2 23 C4 23 C7 PTRDY m 2 7 e 16 C2 24 B3 24 B7 IOCHRDY 2 7 14 D3 15 D2 21 E2 23 D2 23 D6 PDEVSEL m 2 7 1 16 D2 24 B2 24 B5 IOW 3 6 4 16 D2 24 B2 24 B5 SMEMW 3 6 4 14 D3 15 D2 21 E2 23 D4 23 D7 PSTOP m 3 6 9 SA18 5 16 D2 24 B2 24 B5 SMEMR 4 5 14 D3 23 D2 23 D6 PLOCK 4 5 R 82K R 27K m NR10 FN NR24 NRI9 16 D2 24 B2 24 B5 IOR m 1 8 16 D2 24 B2 24 B5 REFRSH m 14 D3 21 E2 23 D2 23 D6 PPERR m l 5 SA17 2 7 16 D2 24 D2 24 D5 Mio 2 T 1 14 D3 15 D2 21 E2 23 D2 23 D6 PSERR mw 2 T SA16 3 6 lt 16 D2 24 D2 24 D5 1016 3 6 3 ANN S SA15 4 5 24 2 24 5 MASTER 4 5 a 4 5 R 82K R 27K 9 NRI3 ares R9 NR28 SA14 1 8 16 C2 24 A3 24 A7 IOCHK m 1 2 23 E2 ACK64 0 m 1 8 SA13 2 7 R A7K 2 7 23 E4 REQ64 0 m 3 6 o 23 E6 ACK64 1 m 3 6 SAIL 4 5 4 5 23 E7 REQ64 1 R 82K 1 R104 2 9 R 27K 15 07 24 2 24 5 DREO7 1 g R 5 6K R97 gt 1 R9 2 15 D7 24 C2 24 C5 IRQ7 m 9 15 D7 24 D2 24 D5 DREOG 234 PSDONE 0 m Sim 3 7 R 5 6K R8T 2 R 5 6K R48 2 9 15 D7 24 D2 24 D5 DREOS 2307 m 3 E R 5 6K R32 R 5 6K 1 RM 2 15 D7 24 C2 24 CS IRQ6 m 15 D7 24 B2 24 B5 DREO3 9 23 04 PSBORO m 9 549 4 5 15 D7 24 B2 24 B5 DREQ2 Bes el Bis 23 D7 PSBO I ROSE AC 5 R 8 2K R 5 6K 1 R33 gt R 5 6K R20 gt 15 D7 24 B2 24 B5 DREQI m 9 21 C6 23 A4 23 A7 TMS 9 1 NRIS g R 5 6K R79 gt R 5 6K 1 R2T 2 15 D7 24 C2 24
93. 6 s 12 D7 PORTS m 2A PTCS PINTS P VS2 57 12 D7 PORT6 m 25 prcupINT 8 AVss P RESET 58 Reser 12 D7 PORT7 m 26 prement e 66 vss P WAIT 59 warn e 2 15 67 INPACK 60 RFUINPACK 28 68 NsPTLS P REG 61 usc 29 preopints 69 ANGDAUPTLG P BVD2 62 pvD2SPKR 30 prevents 70 ANZDA0WPTL7 P_BVD1 63 BVD1 STSCHG 3 PTF2 PINT10 33V AVss P_D8 64 32 e 22 avs P DI 65 33 e 73 Ave D2 EDO 66 34 presmivris 74 Avec 1 4 101516 m WP IOIS16 11 E4 P CD2 67 epos 35 preepintia 75 GND e exp 36 76 53409 6810 53409 6810 sv 637 Vss 77 4 38 78 39 v 79 40 80 8800 080 170S 8800 080 170S 10 C7 LED 7 0 US4 Al yi H8 a PORT7 12 65 A2 16 PORT6 12 05 A3 14 a PORTS 12 5 A4 ya 2 a PORTA 12 C5 bao HD74LVC244AT 054 Al yi 2 PORT3 12 85 A2 Y2 1 PORT2 12 85 3 a PORTI 12 85 A4 3 PORTO 12 85 Boe NDIO HD74LVC244AT MS7751RSE01 0 7 27 2000 14 39 PAGE 12
94. 6 ee NR21 NR23 NR31 NR32 NR33 NR34 NR54 NR55 NR58 NR59 NR60 NR61 NR62 NR63 SG S002C T4R3ISIN PTCB SG 80021C 33M PCCB S RO0DIC SRGROANEPOCE _ SG R002DC 20N PTCE SG S0021C48M PCCB 250116 4 MCROSEZHIIS2 63 MCR03EZHJ103 ROHM R3 Rd R5 R24 R29 R30 R31 R34 R36 R37 R38 R43 R50 R55 R56 R57 R58 R59 R60 R62 R63 R64 R65 R66 R67 R68 R69 R70 R74 R75 R76 R77 R78 R80 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R98 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R116 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 R128 R131 R135 R137 R139 R140 R142 R143 R144 R145 R150 R157 R159 R166 R168 R171 R172 R173 R174 R175 R199 R201 R203 R204 R207 R208 R210 R211 IMCRosmzmm205 po 9 Le meena Rom mo MCROSEZHTISS a 17 MCRO3EZHJ562 ROHM R14 R18 R19 R20 R21 R32 R33 R48 R49 R53 R54 R79 R81 R97 R104 R151 R176 13 MCRO3EZHJ102 R15 R132 R133 R134 R136 R141 R148 R154 R162 R179 R182 R183 R215 RICROSEZHTETO 13 MCRO3EZHJ000 HM R27 R28 R35 R115 R117 R138 R156 R181 R200 R202 R205 R206 R209 73 13 MCRO3EZHJ220 ROHM R41 R42 R44 R45 R46 R47 R51 R52 R99 R100 R101 R102 R103 132 QTY DEVICE 7 p oo n COP AT Ny lt lt lt lt lt lt lt AAA A A AA Sle
95. 7 A2 8 A2 11 A2 UR UR U12 UR CS 6 0 4 C4 5 D2 6 A3 8 A6 PCICLK 125 a PCI CLK0 205 D31 STATUS1 242 m STATUSI 10 87 56 PCIRST 0124 a PCI RST 21 D2 23 B423 B7 D30 STATUSO m STATUSO 10 87 Css D29 CS4 CBE3 139 m 14 B2 D28 A25 C BE2 152 PCLC BE2 14 02 D27 A24 163 PCLC BEM D26 A23 174 m PCI C BEO 14 AS D25 22 CS0 PCLAD 31 0 14 A4 D24 A21 WE 0 AES G EA 7 A6 8 B6 1 UE2 AD31 PCI AD31 D23 A20 BS BS 6 A2 7 B6 8 B6 11 D2 AD30 PCI AD30 p22 A19 RD WR RDWR 4 E2 5 D2 6 C5 7 A6 8 E2 AD29 PCI AD29 D21 18 4 E5 5 D2 6 C5 7 B6 8 B6 11 D2 AD28 PCL AD28 D20 AIT WE3 AD27 PCLAD27 D19 A16 WE2 AD26 PCLAD26 8 15 WEI AD25 PCI AD25 7 A14 WE0 AD24 PCLAD24 D16 A13 AD23 PCI AD23 D15 A12 RAS O a RAS 5 D2 6 D5 AD22 PCLAD2 D14 AD21 PCLAD21 DB A10 CAS3 074 DQM3 5ID2 6 DS AD20 PCI AD20 D12 A9 CAS2 073 DOM2 5 D2 6 D5 ADI9 PCI 19 8 CASI DOMI 5 D2 6 D5 ADIS PCL ADIS D10 A7 CASO 236 DQMO 5 D2 6 C5 PCI ADI7 AD16 PCLADIG D8 AS Roy 725 RDY 4 E4 ADAG PCI 15 in dd AD14 PCLADI4 D6 A3 5 CKE 5 02 AD13 PCLADIS Ds A2 9 a 2 82 ibi PCI AD12 D dd ADII PCL ADIT D3 0 DREQI 0244 m SHDREQI 8 8 AD10 PCLADIO D2 DREQO O23 SH DREQU 8 C8 AD9 PCLAD9 DI BREQ 0203 SH 107 DACK1 236 x SH 8 66 ADS PCLADS BACK 0202 a SH BACK 107 DACKo 235 SH 8 6 AD7 PCLADT DR
96. 7 HDI TRST m TRST iei IN IN IN 164 vppon 436 vssqu 46 OT GL STR OTR STR OTT 22 131 132 Oa 45 23 EE FB vssQio 132 107207 TDI m TDI T 19 vssoo 129 4 24 C150 2 193 1 2 vppos 105 vssos 196 Expo GONDU GND 07 HDI m 25 F XL768KHZ 33 4 vssQ 94 4 26 GND 79 vssq 30 1D7 2 E7 m 27 ASEBRK 67 68 28 lt Soc 33v vssQs 6 e 28 GND T 4 35 vsso4 56 29 195 1 2 5 4 vssos 2 e 30 GND spo 253 1 73 2 R 33 29 30 31 VDD CPG y 22 vssq2 30 1E5 3 A7 3 D1 SH RESET nRESET VDD PLLI 251 1 2 1 15 vssQ1 16 e 32 GND 249 1 R71 gt R 33 3 4 33 VDD PLL2 9 e me VDDQ0 vssQo 4 e e 33 GND A Do Not Stuff 871 872 HD6417751RF240 HD6417751RF240 e 34 GND B VIE SH7751R 6 7 SH7751R 7 7 35 4 18 36 oe de 95 33V 33V GND 2 E DX20M 36S 5 gt a 5 Hitachi UDI port g 68 a a o qi o obs ros oF 552 U18 5 gt 1 fA EA E m B vss Rrc 196 9 10 TNA 2 Spe 254 9 8 1 R103 2 DE VSS CPG 9 9 OEA OA2 Wy A m PCI CLK4 23 86 aay vss PLL1 252 9 aad 2 4 1 2 m PCI CLK3
97. A m 9 pRSNTI A9 B10 Rsv LA B10 Rsv o 2324 PRSNT240 pRSNT2 23 FA PRSNT2HI pRSNT2 512 512 GND 42 813 4B 4 513 GND 4B 4 Rsv rsy AM B14 Rsv rsy 815 GND RST 5 m RST 1 2 21 02 23 87 545 GND RST OMS 1 A2 21 D2 23 B4 215 PCI CLK3 816 ep 205 PCI CLK4 6 crk 16 4 BU GND GNT m PCI GNT2 1 E2 25 B7 4 BU GND GNT m PCI GNT3 1 E2 25 B7 3 3 25 86 PCI REQ2 8 REQ 18 4 3 B3 25 B6 PCI REQ3 BIS REQ A PAD 31 0 e BD prsy PAD 31 0 14 A6 15 A2 21 A2 23 B2 23 B7 23 B6 PAD 31 0 BD rsy 14 A6 15 A2 21 A2 23 B2 23 B3 23 B6 14 A6 15 A2 21 A2 23 B3 23 B7 23 B6 PAD3I B20 Apao 420 14 A6 15 A2 21 A2 23 B2 23 B3 23 B7 mE B20 Apao A20 mE PAD29 B21 aav LAN PAD29 B21 aay LAM 522 GND 028 A22 822 GND AD28 A22 PAD27 B23 AD27 LA23 PAD27 B23 Ap apy LA23 PAD25 BM Apos GND LA24 PAD25 BM anos GND LA24 B25 say AD24 A25 B25 say Ap24 A5 14 B3 15 D2 21 D2 23 C6 B260 C IBE3 msgr 426 m PIDSELO 23 83 14 B3 5 D221 D223 C2 PC BE3 B26 C IBE3 IDSEL 426 23 F3 PAD2S B27 AD23 33V 27 PAD23 B27 ADOS A27 525 AD22 28 525 GND Ap22 A28 PAD2I B2 Apo PAD21 29 apo Apo PAD20 PA
98. AK1 238 SH 107 AD6 PCLAD6 AUDATA3 228 m AUDATA3 287 MDS RTS2 214 MD8 3 04 237 SH DRAKO ADS PCLADS AUDATA2 227 m AUDATA2 2A7 MD7 CTS2 218 MD7 3 04 AD4 PCLAD4 AUDATA1 224 m AUDATAI 2 7 6 204 6 3 B4 246 HDI 2 07 AD3 ADS AUDATA0 223 m AUDATAO 2 A7 232 MDS 3 04 TDI 5 m TDI 2 D72 C7 AD2 2 AUDSYNC 2D m AUDSYNC 2 B7 MD4CE2B 231 MD4 3 B4 2 m HDI 2 D72 B7 AD1 PCLAD1 AUDCK 220 m AUDCK 2 7 MD3 CE2A 230 3 B4 rs 1 m HDI TMS 2 D72 B7 AD0 PCLADO HD6417751RF240 MD2 RXD2 211 MD2 3 A4 TRST 0199 HDI T 2 E72 B7 5 7751 2 7 MDU TXD2 216 MDI 3A4 ASEBRK 255 m ASEBRK 2 E72 C7 PAR 62 m PCI PAR 14 D2 MDO SCK2 217 MDO 3A4 HD6417751RF240 SH7751R 4 7 PCIFRAME 2152 m PCLFRAME 14 02 206 SH TXD 12 5 IRDY 2154 PCLIRDY 14 D2 212 a SH 12 A5 A155 215 1 RM 5 TRDY PCLTRDY 14 D2 SCK SH SCK 12 A6 m SH INTA 1 E2 RA 1 R66 2 R 10K PCISTOP PCI STOP 14 D2 9 a SH BREQ 105 160 gu 113 1 R65 2 R 10K ae PCILOCK PCLLOCK 1402 SLEEP SH SLEEP 9 SH BACK 105 122 197 1 R70 2 R 10K IDSEL a SH IDSEL VET CA a SH SH 107 1 R69 2 R 10K DEVSEL m PCI DEVSEL 14 D2 9 SH X 1 R36 2 R 10K MRESET SH MRESET I E7 SH SLEEP 1 05 perp
99. BS Breakpoint Set Set breakpoint Format BS address Example Ready gt BS 000000 BD Break Delete Deletes breakpoints Format B D Example Ready gt BD 45 lt address gt BC Break Clear Deletes all breakpoints None Format BC Example Ready gt BC BE Break Enable Breaks at breakpoints Format BE Example Ready gt BE 78 BI Break Ignore Ignores breakpoints Format BI Example Ready gt BI Function Describes the monitor system commands Describes concerned items in detail number Ready gt h lt WDisplay help menu 1 General 2 Register 3 Break Point BR BD 4 Memory ME MD 5 Disassemble 6 Start User Program G S H elp number or class for more information Memory Load M em L Memory Edit em E dit startAdrs size W L Memory Dump em D ump startAdrs endAdrs ASCIIcode A Memory Fill startAdrs endAdrs Data Data Flash Load F lash L oad offsetAdrs 79 15 Appendix 15 1 Board Dimension 81 82 Contains Solution Engine dimensions 15 2 Circuit Diagram P 83 P 109 Contains a circuit diagram of the Solution Engine It is a useful reference for designing system 15 3 FPGA Logic Contains internal FPGA logic 1 YP76010 on the Solution Engine P 110 P 115 Contains internal FPGA logic 2 YP76020 on the Solution Engine P 116 P129 15 4 Parts List P 153 P 156 Contains parts lists
100. Before running the program set the stack pointer for the program loaded into memory to R15 Because h CF00000 has already been set to R15 change the setting as follows to set a stack pointer at different location Ready gt rw r15 CEF0000 After completion of register setting the information about all registers is displayed as follows and enter into command prompt status General Registers RO 200000000 00000000 R4 00000000 00000000 R8 00000000 00000000 R2 00000000 00000000 R6 00000000 R7 00000000 R10 00000000 R11 00000000 R12 00000000 R13 00000000 R14 00000000 15 0 0000 00000000 R1_BANK 00000000 R2 00000000 R3_BANK 00000000 4 00000000 R5_BANK 00000000 6 00000000 R7_BANK 00000000 Control Registers SSR 600000E0 SPC 00000000 GBR 00000000 VBR 00000000 Ready gt 65 Dump memory contents Confirm the command transferred to user memory by using the md command Input the md command as follows Ready gt md ac100000 When the md command is executed the data of the area address H AC100000 HAC1000FE in this example of 256 bytes is dumped from the address input on the command line AC100000 03 61 21 41 13 62 21 42 23 63 21 43 33 64 21 44 AC100010 43 65 21 45 53 66 21 46 63 67 21 47 73 68 21 48 AC100020 83 69 21 49 93 6A 21 4A A3 6B 21 4B B3 6C 21 4C AC100030 C3 6D 21 4D D3 6E 21 4E FF C3 IC DO IC D1 01 21 100040 DO 1D D2 01 22 58 00 I
101. C244 00000000000000000 00000000000000000 00000000000000000 00000000000000000 U19 O CNII CNIO ISA Slot 2 ISA Slot 1 1543 024 For M1543C U34 CR2032 holder E CR2032 TPS2211 M8 27 160 27 800 CN23 oo0G0G oonono EPFIOK30ATC 144 2 40pin IDE connector Primary y CN13 IDE 1 FDD connector GO O OO OO 0 CN15 FDD OO 0O 0 G OO0 OO0 O GO0 0O0O00 OG Go0 GO DCAS19931 CN24 ooooon oooooo o o o o Q o Q Q Q CN14 IDE 2 SW1 sw2 SW r1 Poa Bod Po9 00000000 O Pod 00000000 d 02 bg 00000 40 System LED Connector for LED for PC P 5 1 Abort IDE connector Secondary ower SUPPY Reset Reset etc ATX power 8 bit LED ARD switch switch switch Figure1 2 SH7751R Solution Engine External view 1 4 Software Configuration The Solution Engine has a monitor program in EPROM The monitor program displays memory data and executes programs transferred to user memory The user program can be executed and evaluated by connecting the host system For connection between host system and the Solution Engine terminal software suc
102. C5 IRQS 9 15 D7 24 D2 24 D5 DREQO 21 B623 423 A7 TDI w SA8 2 7 R 5 6K RS EK MTS 3 6 s 1 RI8 2 15 D7 24 C2 24 C5 1804 21 86 23 2 23 6 TCK s R 5 6K R19 2 5 23 A4 23 A7 TRST m R 82K R 5 6K 1 NRU g 15 D7 24 C2 24 C5 IRQ3 SA6 2 7 SAS 3 6 1 16 D2 24 C2 24 C5 TC 4 5 R 82K SA4 1 NRO 3 SA3 2 7 1 SA2 3 6 1 SA1 4 5 1 R 82K SA0 1 268 LA23 2 7 1 15 C7 24 D2 24 D5 IRQIO m 3 6 4 LA22 4 5 1 R 82K 1 27 g 15 C7 24 D2 24 D5 IRQU 9 LA21 2 7 24 D2 24 D5 IRQI2 m 3 6 4 LA20 4 54 R 82K 1 29 g 15 C7 24 D2 24 D5 18015 w 9 LA19 2 7 15 C7 24 D2 24 D5 IRQI4 m 3 6 4 LA18 4 54 R 82K LA17 1308 16 D2 24 D3 24 D7 x 2 7 16 D2 24 D3 24 D7 3 6 16 C4 27 D2 SPKR m 4 AN 5 16 2 24 24 7 23 17 7 27 2000_14 39 PAGE 25 GND 7 PAGE 26 1 2 3 4 5 33VSB a ES x gwi U38 U38 277C2 POWER SW 5 1 2 2 3 55 m PWRBIN 16 85 4 HD74LVC14T HD74LVCIAT
103. D19 B30 AD19 GND 3 PADI9 B30 GND 9 B3 433 Apis 31 B3 assay Apis A1 PADIS PAD17 B3 apis A32 PAD17 32 pg apis LA32 PADI6 147C3 15 D2 21 D2 23 C6 2 33 C BE2 433v 433 147C3 15 D2 21 D2 23 C2 2 B33 C BE2 433v A33 eB3 GND FRAME 0434 m PFRAME 14 D3 15 D2 21 E2 23 C7 25 B6 334 GND DA34 14 D3 15 D2 21 E2 23 C4 25 B6 14 03 15 02 21 2 23 6 25 86 PIRDY m B35 IRDY 4359 14 D3 15 D2 21 E2 23 C2 25 B6 PIRDY B35 IRDY 435 4 B36 TRDY 5836 m PTRDY 14 D3 5 D2 21 E2 23 C7 25 B6 B36 asy TRDY 436 14 D3 15 D2 21 E2 23 C4 25 B6 14 D3 15 D2 21 E2 23 D625 B6 PDEVSEL DEVSEL GND 37 14 D3 15 D2 21 E2 23 D225 B6 PDEVSEL 837 DEVSEL GND 437 4 e B38 GND stop 438 m PSTOP 14 D3 15 D2 21 E2 23 D7 25 B6 4 838 GND 5538 14 D3 15 D2 21 E2 23 D4 25 B6 14 D323 D625 B6 PLOCK B39 Locks 433y A32 14 D323 D225 B6 PLOCK B39 rocks A32 14 D321 E223 D625 B6 B40 pERR 5 40 m PSDONE 0 25 06 14 D321 E223 D225 B6 PPERR 40 pERR spone A a 25 C6 B4 55 sBo x PSBOM0 25 06 Bal 433 sBo 25 06 14 03 15 02 21 2 23 06 25 86 PSERR SERR AE 14 D3 15 D2 21 E2 23 D2 25 B6 PSERR SERR AE 33v PAR 4483 m PPAR 14 D3 15 D2 21 E2 23 D7 asy PAR 44 14 D3 15 D2 21 E2 23 D4 14 E3 15 D2 21 D2 23 D6 BHO
104. F 42 33 4F 43 4F 83 4F 100050 93 4 4F C3 4F D3 4F 4F 32 00 AC100060 3E 40 42 00 4E 40 82 08 8E 49 92 09 9E 48 A2 08 AC100070 AE 49 B2 09 BE 48 C2 08 CE 49 D2 09 DE 48 E2 08 AC100080 EE 49 F2 09 FE 48 F7 4F E7 4F D7 4F C7 4F B7 4F 100090 A7 4F 97 4F 87 4F 47 AF 37 4F 83 OF OD 31 25 33 AC1000A0 4C 45 6D 47 09 00 FD AF 09 00 00 00 02 00 00 00 1000 0 00 00 11 OC FF FF 00 00 10 00 11 OC 36 9F EA BB 1000 0 20 50 0A 04 CC 18 41 10 04 CF 28 47 F1 FC 1F AF AC1000D0 20 1E 04 43 95 45 D3 A8 79 10 88 CS 97 47 D1 2D 1000 0 82 86 80 70 B3 A2 6A 02 B7 FA 81 72 7D 22 1B B9 1000 0 DO 00 0A 00 98 04 97 AC EA 2F 9C 40 83 18 13 BB 66 Execute user program Execute the program transferred to user memory with the g command Input the g command as follows Ready gt g ac 100000 When the g command is input h AC100000 is set to the program counter PC and the program is executed from address h AC100000 When either Ctrl C key or the Abort switch SW2 is pressed the information about all registers is displayed as follows and the user program execution is suspended General Registers RO 200000000 00000000 R2 00000000 00000000 R4 00000000 00000000 R6 R8 00000000 00000000 00000000 R7 00000000 R10 00000000 R11200000000 R12 00000000 R13 00000000 R14 00000000 15 0 0000 00000000 BANK 00000000 R2 00000000 R3_BANK 00000000 4 00000
105. FC I0BMEPIB 1 R133 2 LL RK GND GND GND GND GND GND GND GND 7 27 2000 14 39 10 1 2 3 4 5 6 7 8 MR SHPC 01 V2 1A54C46A3 A 25 0 017 P_A 25 0 12 2 3 SA25 CCA25 1 R120 2 SA24 CCA24 m PC SIRO3 10 7 11 2 SA23 CCA23 nod 1 R121 2 SA22 CCA22 x PC SIRO2 10 87 1 2 SA21 CCA21 RE 1 RI2 gt eee SA20 CCA20 PC SIRO1 10 87 11 2 SA19 CCAI9 1 R123 gt SA18 CCA18 m PCSIRQO 10 B7 11 E2 SA17 CCA17 FK 1 R199 EET SA16 CCA16 PC RDY 4D2 11D2 SAIS 5 RoHS SA14 CCA14 GND aav SA13 CCA13 EED SA12 CCA12 1V E2 SLED OUT 1 2 1725 CARD LED SAH RD swrziOMr SA10 CCA10 SA9 CCA9 CN31 1 R169 gt 1 SA8 CCA8 9 SPEAKER SA7 CCA7 nii 2 NC 1 R167 gt SA6 CCA6 2 GND Q2 R 68 SA5 CCAS 45V 1 63 4 g SA4 CCA4 11 E2 55 OUT m OF FEC 4AMEPIB 22 N S noosa SA3 CCA3 ST as SA2 CCA2 2904116 3 5 SA1 CCA1 540 CCA0 GRD SD 4 5 3 6 7 4 8 4 0131 0 P D IS0 12 2 015 CDI5 SD14 CD14 SD13 CD13 33V 5 DV SD12 CD1
106. H220J50PT C122 C123 C149 C150 GRM39CH471J50PT TA C185 C186 C202 C203 N gt 130 MS7751RSE01 Parts List 2 QTY DEVICE MAKER REFDES TDK C224 JAE CNI Fis i CGG20CHGFIOIK KX14 140K5D1 DMII351 Z3 1 DM11351 Z3 2 17 1 DM11351 Z3 3 MH11061 D3 UB1112C D1 20 RJHS 5381 EH06001 GL V MCR60A 98D 254DS 23 HIF3FC 10PA 254DSA HIF3FC 40PA 254DSA HIF3FC 34PA 254DSA 26 1 MOLEX 29 1 DX20M 36S IC26 0210 GS4 YAMAICHI 32 2 FFC 10BMEP1B FOXCONN HRS HRS HRS KEL JAE FFC 6AMEPIB HONDA FFC 5AMEP1B HONDA 35 2 FFC 4AMEPIB CN8 CN9 CNIO CNII CN13 CN14 CN15 CN20 CN21 CN22 CN23 CN24 CN27 CN31 HONDA SONY 38 1 RLS 73 ROHM DI FL1 FL2 FL3 FL4 FL5 FL6 FL7 FL12 FL13 FL14 PL15 FL16 FL17 FL18 FL19 FL20 FL8 FL9 FL10 FL11 109322 PRECKDIP fa SML 210MT ROHM LED1 LED2 LED3 LED4 LEDS LED6 LED7 LEDS LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 48 2 MX27C8100PC 10 MACRONIX M7 M8 9 so CALERA 51 9 MNR14E0ABJ102 MNR14E0ABJ330 14 822 NR1 NR2 NR3 NR4 NR8 NR24 NR30 NR37 NR46 R6 NR7 NR39 NR40 NR41 NR42 NR43 NR44 NR45 NR47 NR48 R52 NR53 NR9 NRIO NR11 NR12 NR13 NR14 NR15 NR17 NR20 NR26 NR27 NR29 NR35 NR36 NR56 NR57 MS7751RSEO1 Parts List 3 55 1
107. IDECS3J ORS a SIDECS3 19 04 packje OP a DACK6 24 D2 24 D5 INTAJ MI OF m PCI INTA 10 B2 21 D2 23 A2 23 A7 25 A6 DODI OL DCD1 18 B2 SIDECSIJ OLL a SIDECSI 19 D4 DACKJs 0520 DACKS 24 D2 24 D5 INTBISO m PCI INTB 10 B2 23 A4 23 A6 25 A6 18 B2 SIDEIORj a SIDEIOR 19 C4 DACKB OS DACK3 24 B2 24 B5 INTCISI CES PCLINTCH 10 82 23 2 23 7 25 6 MIS43C SIDEIOWJ SIDEIOW 19 C4 DACKR 0116 DACK2 24 C2 24 C5 INTDJS2 OF m PCLINTD 10 B2 23 A4 23 A6 25 A6 1543 2 8 SIDERDY Ml m SIDERDY 19 C4 0117 DACKI 24 B2 24 B5 SIDEDRQ 4 SIDEDRQ 19 C4 E20 a DACKO 24 D2 24 D5 PCICLK 8 m PCI CLK1 205 SIDEDAKJ OS m SIDEDAK 19 D4 PCIRSTY OF m M1543 RST 16 F2 19 A2 19 A4 22 F2 1543 110 m RST DRV 24 2 24 5 M1543C 1543 3 8 M1543C 1543 1 8 XD 7 0 U24 SD 7 0 24 A3 24 A7 25 A2 M1543C 4 8 2 3 4 AS A6 AT 8 LDo G XDIR x 1 010 HD74LS245FP 7 27 2000 14 39 15 1 2 3 4 5 6 7 8 M1543C B1 PART 2
108. JKFF A JKFF DFF PRN PRN PRN J Q J Q b D Q WAIT K K CLRN CLRN CLRN RES CLK_3M Reset wait control res_ wait 3M SCK OUTPUT gt SCK sELI1 0 P 0 T 4to1sel CLK_115R2K A OUT SCK CLK_115R2K CLK 38R4K B CLK_19R2K C 7 CLK_9R6K D SEL 1 0 SEL 1 0 dy PRN PRN JPRN 76R8K 7688 K CLRN CLRN CLK 38R4K CLK 19R2K VC Fd JKFF AND2 KF 6 PRN PRN PRN E CLK 9R6K K K 5 CHR CLRN CLRN Clock pulse generetor cpg SLOT_IRQ 8 1 PC_SIRQ S 0 PCI INTB PCI INTC PCI INTD NMI INTR NIT CPURST IGNNE A20M A 7 1 BCRCS B_RD B WE 1 0 RESET LEDCS STATUS 1 0 irc ber2 RDB 15 0 B D 15 0 5 7 SLOT_IRQI 8 1 BUS Di 15 0 15 0 A 7 1 INPUT 3 0 A 7 1 INPUT INTA ERS N RD P x E eum e B WE 1 0 WE 1 0 INPUT INTC ane lt TIRQ 15
109. MEMWJ EP MEMW 24 D3 24 D7 25 E2 GND YS 2 a NMI 10 C2 16 B5 MEMRj a 24 D3 24 D7 25 E2 1 a A20M 10 C2 16 B5 222220865022 33 R 10K M1543C SG 8002JC ASM PCCE 33VSB M1543C 5 8 l ous VCC 1 R106 2 C ley 15 B7 15 E2 XDI7 0 a RSM 16 B5 26 B5 er 3 1 R96 2 1 R107 gt R 10K IRQ RTC IRO 15 D7 GND OUT m USBCLK 16 B4 ACPWR 16 C5 Ife R 33 1 R108 2 R 10K at F 48MHZ DOCK 16 C5 1 R110 2 R 10K E x WIK a SMBCLK 16 C4 23 1 2 gt Do Not Stuff 1 2 R sow Xe R116 R139 Weit m SMBDATA 16 04 1 2 PW 16 E2 ae 1 RI39 gt R 10K 1 RI gt MOT 16 F2 a RI 16 C5 R 10K R 10K 1 RM 2 XALM 16 F2 GND R 10K GND rae 5 166 PWOK w ed RTC T am 16 4 RTCAS m M As 24 4 E 16 B4 wo 16 B5 ZZ 16 C4 RTCRW m 15 Rw TPS TPR 16 C4 RTCDS Y ps 20 604 BIOSA16 wm 16 85 STP wm lo ES zi XATM 22 XATM gt gt 1 STP 1 16 E6 XALM m 9 XALM glee 3m 164 CLK32KO g O 16 B5 PCLSTP g HO 261 Ha 15 E2 9 A2 9 A4 M1543_RST w 18 RESET OTi TP4 TP13 16 E6 MOT 1 wor cnp 12 n 16 B5 SMI ag lo 16 85 SUSTATT mw a ed Pe RTC 6593 1186 IP nile 1685 HO 16 5 OFF PWRI m l TPS TPIS al a Z Do Not Statt 16085 SLEEP e O 16 5 OFF PWR2 7 27
110. N2 18 D2 SIDED9 SIDED9 IRQ6 V19 1806 24 C2 24 C5 25 C2 m PC BE1 14 E3 21 D2 23 D2 23 D6 sourz W4 m SOUT2 18 D2 SIDEDS SIDEDS IRQs U7 IRQS 24 C2 24 C5 25 C2 CBEJo PC BEOR 14 A6 21 D2 23 E4 23 E7 RTS2 16 C7 18 D2 SIDED7 SIDED7 IRQ4 020 1804 24 C2 24 C5 25 D2 crszj CTS2 18 D2 SIDED6 SIDED6 1RQ3 016 a IRQ3 24 C2 24 C5 25 D2 FRAME 85 m PERAME 14 D3 21 E2 23 C4 23 C7 25 B6 OV a DTR2 16 C7 18 D2 SIDEDS SIDEDS TRDYJ 26 m PTRDY 14 D3 21 E2 23 C4 23 C7 25 B6 DSR2j DB DSR2 18 D2 SIDED4 DREQ7 619 m DREQ7 24 2 24 5 25 4 IRDYJ OS m PIRDY 14 D3 21 E2 23 C2 23 C6 25 B6 DCD2 18 D2 SIDED3 SIDEDS DREQ6 C20 m DREQ6 24 D2 24 D5 25 C4 sropj 086 PSTOP 14 D3 21 E2 23 D4 23 D7 25 B6 RD 18 E2 SIDED2 SIDED2 DREQs E18 m DREQS 24 D2 24 D5 25 C4 DEVSELJ O m 14 D321 E223 D2 23 D625 B6 SIDED1 SIDEDI DREQ3 W16 DREQ3 24 82 24 5 25 4 sini 6 m SINI 18 B2 SIDEDO SIDEDO DREQ2 V2 m DREQ2 24 B2 24 B5 25 C4 SERRJ 046 m PSERR 14 D3 21 E2 23 D2 23 D6 25 B6 sour1 6 SOUTI 18 A2 DREQI 17 DREQI 24 B2 24 B5 25 C4 PAR P7 m PPAR 14 D3 21 E2 23 D4 23 D7 RTs a RTS1 16 C7 18 A2 SIDEA2 1 2 m SIDEA2 19 D4 DREQo E18 DREQO 24 D2 24 D5 25 C4 PHLDAJ 08 m PCI GNT4 1 2 25 87 OWS a CTSI 18 B2 14 m SIDEA1 19 D4 PHOLD m PCI REQ4 1 E2 25 A7 DTRIJ Ove DTRI 18 A2 sipgAo L3 m SIDEAO 19 D4 pack CCI8 a DACK7 24 D2 24 D5 DSRIJ 096 DSRI 18 B2 S
111. ND Data3 gt n 855 Su SN 5 Datad E ky a 6 o me DataS wn E 1 lt Data6 5 8 7 9 Data8 15 C4 m 10 aa 15 C4 BUSY m Busy E 15 04 N 12 PError N 15 C4 SLCT m a gt 13 Select gt oF 14 a d nAutoFd E DE a 1504 ERROR m ale 15 nFault INIT 1 6 g E SE al 16 15 C4 INIT e e EE re nlnit 2 7 s 5 17 15 C4 PD2 e e mc e HPA nSelectin SUCTIN 3 le B ER lt E P 15 C4 SLCTIN m ere a 55 a GND 15 04 PD3 4 5 a Be OTT et GND R 33 A ZR uw 20 1 GND FG5 a ae 21 1 2 GND FG6 22 GND BEN 23 ez GND GND 24 Em 3 GND CE 35 GND G4 G4 DM11351 Z3 3 GND PRN gt Us gt 2 5 5 25 OT Ge cx OT a G4 G4 14 c c2 16 A cp 9 2 RxD 7 2 lt SH TXD2 m TIIN TIOUT ien TxD 3 B3 SH RTS2 6 4 DTR rai 0 20 T3OUT b 5 GND 4 Tour 28 DSR e e 7 RTS 5 8 9 G 8 22 SH RXD2 m RIOUT RIIN 9 CTS 5 4 9 Az 3B3 SH CTS2 R2OUT R2IN 26 27 26 R30UT R3IN el BE 419 0 11351 73 1 uw N i 22 RaoUT RAIN 3 opi GND SH SCIF 7 19 RsouT RsIN 18 n
112. OS CA DREQ3 m B16 psos SAIS 15 D724 B22S CA DREQ3 m B16 pro3 SA15 15 E7 24 B5 DACKI m DAckt SAH 15 E7 24 B2 DACKI m DACKI SAH 15 D7 24 B5 25 C4 DREQI BI8 pRon SA13 15 D7 24 B2 25 C4 DREQI 815 prow SA13 16 D224 B525 BA REFRSH m B19 REFRESH SA12 16 D224 B225 BA REFRSH m B19 REFRESH SA12 16 D2 24 C5 m B20 syscLK 16 D2 24 C2 SYSCLK m B20 syscLK SAI 15 D7 24 C5 25 C2 1807 21 moz SA10 15 D7 24 C2 25 C2 IRQ7 w B21 qo SA10 15 07 24 5 25 2 IRQG m 9 B22 TROe SA9 15 D7 24 C225 C2 IRO6 22 SA9 15 07 24 5 25 2 IRQS m B23 IRQS SA8 15 D7 24 C2 25 C2 5 m B23 TROs SA8 15 07 24 5 25 02 184 B24 SA7 15 D7 24 C2 25 D2 IRO4 m B24 SA7 15 D7 24 C5 25 D2 IRQ3 m 25 SA6 15 D7 24 C2 25 D2 IRQ3 m B25 SA6 15 E7 24 C5 DACK2 m B26 2 SA5 15 E7 24 C2 DACK2 m B26 _pACK2 SA5 16 02 24 5 25 02 TC m B27 4 16 D2 24 C2 25 D2 TC m B27 SA4 16 02 24 5 BALE m B28 BALE SA3 16 D2 24 C2 BALE m B28 BALE SA3 B29 asy SA2 e 2 SA2 16 D6 24 C5 OSC B30 osc SA1 16 D6 24 C2 OSC B30 osc SA1 531 GND SA0 SA0 16 D2 24 D5 25 B4 MI6 Dic _MEMSCI6 SBHE OC SBHE 16 D2 24 D7 16 D2 24 D2 25 B4 MI6 DIC MEMSCIG SBHE OC SBHE 16 D2 24 D3 16 02 24 05 25 4 1016 m D2 yocsis LA23 LA23 16 D2 24 D2 25 B4 1016 m D2 yOCS16 LA23 15 7 24 05 25 2 16010 m 03 LA22 15 7 24
113. PC_SIRQ S 0 INTA INTB INTC INTD NMI INTR INIT CPURST IGNNE A20M TIRQ 15 0 Di 15 0 A 7 1 BCRCS RD WET 1 0 RES level cnt gt gt INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT ILCRA 15 0 ILCRB 15 0 ILCRC 15 0 ILCRD 15 0 ILCRE 15 0 ILCRF 15 0 gt INPUT SLOT_IRQ 8 1 SIRQ 3 0 INTA INTB INTC INTD NMI INT 15 INTR INIT CPURST IGNNE A20M ILCRA 15 0 ILCRB 15 0 ILCRC 15 0 ILCRD 15 0 ILCRE 15 0 ILCRF 15 0 TIRQ 15 0 irl enc 0 ON TS 0 1 ilcr INPUT Em INPUT INPUT INPUT f INPUT o INPUT Di 15 0 Do A 7 1 ILCRA BCRCS ILCRB RD WE 1 0 ILCRD ILCRE ILCRF ILCRG RES 5 0 5 0 5 0 15 0 15 0 5 0 15 0 5 0 15 0 IRL 3 0 b OUTPUT ILCRA 15 0 ILCRB 15 0 ILCRC 15 0 ILCRD 15 0 ILCRE 15 0 ILCRF 15 0 ILCRG 15 0 ILCRH 15 0 OUTPUT Do 15 0 IRL S 0 Interrupt Controler irc Di 15 0 A 7 1 BCRCS RD WET 1 0 RES 74138 _ Difts 0 gt INPUT 7 1 gt mer BCRCS INPUT RD 0 RES reg16 Di t5 0 Dilf5 0 Do 15 0 cs
114. PFIOK30A 4 EPF10K30A 2 4 EPF10K30A 3 4 EPF10K30A 4 GND c GND 3 3V 3 3V EDU IED R188 LED8 R184 LED9 LED 2 1 bit7 1UC2 LED RESET i 21 02 RESET R 560 SML OMT R 560 SML OMT R189 LED7 R185 LED10 LEDS 2 1 bit 10 C2 LED SLEEP w i zu 2 SLEEP R 560 SML OMT R 560 SMLZ OMT TED R190 LED6 R186 LEDS 1 2 1 q 2 bits 10 C2 LED STANDBY 1 21 q 2 STANDBY Mil YE 33V R 560 SMLJ OMT R 560 SMLJ OMT LED R191 LEDS R187 LED12 10 D6 DATAO 1 DATA vcc2 e 1 R145 gt LED4 1 W 21 2 bit 10 C2 LED NORMAL 1 2 E u NORMAL S 10 D6 DCLK w 9 2 pcrk 7 R 10K ai SML 210MT 4 SML 210MT oe Ss N 10 02 STATUS m 3 ok casco Wh 1 R135 gt LED3 1 210433 10 2 DONE m 466 GND gt R 10K me SML 210MT EPC1441PC8 BED 1 2 1 2 GND OUR Wi R 560 SML OMT 33v GND 10 2 10K g LEDI 1 R1943 1 2 LED CN24 PS YP7602x R 10K 4 T4 SCLE R 560 SMLZ OMT 2 GND LEDO 1 8195 2 1 pw 2 bah SI CONF DONE R 560 SMLZ OMT 4 e 10 46 CONFIG m 33V 33V 33V 33V 33V 33V 33V aav Tj N C STATUS T 1 2 8 E R132 R IK qo Me EL ZR 555 g 55 sites 56 s 2 5 225 glag 2 9 DATAO oT ers STE OTR O CTRL OTRA 1 R141 R IK 19 al OP QT T 1 R134 4 R 1K F
115. Pin name Connected State Function J3 ATX power supply is in ON state and power supply is 1 3 provided to the Solution Engine all the time 1 2pin closed 13 Power supply switch SW1 on the Solution Engine controls ON OFF of ATX power supply at shipment ea 2 3 closed Expansion slot 5V power supply J4 Table3 6 shows the function of the expansion slot 5V power supply jumper J4 As shown table3 6 this jumper connects pins A66 and A67 of the expansion slot to 5V power supply on the Solution Engine When mounting LSI or IC that need analog 5V power supply analog 5V power can be provided from pins A66 and A67 of the expansion slot by closing J1 Signals of address bus and data bus output to the expansion slot are 3 3V Mount 3 3 V 5V interface IC on daughterboard if 5V interface is necessary Table 3 6 Function of the expansion slot 5V power supply jumper J4 Jumper Pin Jumper Pin gt name Connected State Function Pins A 66 and A67 of the expansion slot are connected J4 1 2 to A 5V of the Solution Engine In this state A 5V power is provided to the daughterboard Closed Power supply switch on the Solution Engine controls ON OFF of ATX power 19 3 3 Description of test pin TPn Table 3 7 lists the function of test pins Table 3 7 Test Pin Functions For test Flash Ready Busy RESET IN Connect RESET probe when using IC socket equipped ROM emulation NMI IN Conn
116. S 0 oureur gt i CRA 15 0 WE 1 0 Nm T CS RES NPUT RES d fe4 d fe4 NOT NOT NOT NOT D15 scum 58 65 So ILCRA15 D7 o o ILCRA7 D14 To D Qo To ILCRA14 D6 D2 ILCRA6 NOT NOT NOT NOT D13 o Di Oi gt o ILCRA13 D5 o Di o ILCRA5 NAL NOT NQT NOT D12 To Do 00 To ILCRA12 D4 To D Q0 150 ILCRA4 CS ENA CS ENA WE1 CLK WEO CLK RES CLR RES SLOT_IRQ8 Level 15 SLOT_IRQ6 Level 11 dffe4 dffe4 D11 So ILCRA11 D3 Lo To ILCRA3 NOT NOT D10 Tso D To ILCRA10 D2 02 ILCRA2 D9 Bo Di Qi Too ILCRA9 D1 o0 Di OQ Bo ILCRA1 D8 bor San ILCRA8 Do Do ILCRAO cS ENA Gs ENA WE1 CLK WEO CLK RES CLR RES CLR SLOT IRQ7 Level 14 SLOT IRQ5 Level 10 Interrupt Level Control Register A ilcra SUBD IN ESIGN level_sel EL 3 0 OUT 15 0 BEGIN TABLE gt gt gt c h to n 1 h 2 n 5 he hg h a ha h d h e END END m SEL 3 0 INPUT OUTPUT OUT 15 0 B 0000000000000001 B 0000000000000010 B 0000000000000100 B 0000000000001000 B 0000000000010000 B 0000000000100000 B 0000000001000000 B 0000000010000000 B 0000000100000000 B 0000001000000000 B 000001000000000
117. SH7751R Solution Engine MS7751RSEO01 User s Manual MS7751RSEO1 M Hitachi ULSI Systems Co Ltd Cautions 1 Products and product specifications are subject to change without notice 2 Hitachi ULSI Systems Co Ltd makes every attempt to ensure that the information of this manual is correct and reliable however Hitachi ULSI Systems Co Ltd takes no responsibility for damages or infringement of patent rights or other rights derived from the use of the information product or circuit 3 This manual does not authorize the use of the patent rights or other rights of third parties or Hitachi ULSI Systems Co Ltd 4 No one is permitted to reproduce or duplicate in any form the whole or part of this document without written approval from Hitachi ULSI Systems Co Ltd 5 The product overview described in this manual may differ slightly from the actual product Notes on Using the SH Solution Engine This section contains topics to be carefully read and considered when using the SH Solution Engine referred to as Solution Engine of the Hitachi ULSI systems Solution Engine Components 1 After opening the package check the following items to confirm that everything is in place a Solution Engine main unit b CD ROM A set of software User s manual c Monitor EPROM for big endian d Software license agreement How to connect the Solution Engine 2 Before connecting the power supply cables development eq
118. USBCLK m USBCLK 16 E6 STPCLKj a STPCLK 16 4 vcc_c OT Gt o m p SA15 SLEEP SLEEP 16 F4 S e a AIS i K16 se ap 15 SA14 ROMKBCSJ ROMKBCS 16 7 ZZ a 77 16 85 36 SA13 SERIRQ D16 m SERIRQ 16 C7 Cpu sTpj CPU CPU STP 16 F5 xp COND ND SA12 sirqi DP a SIRO1 19 C2 pcrsrpj a 16 F5 vcc SAH SIRQ2 m SIRQ2 19 C4 SUsTATIj m SUSTATI 16 F5 SA10 xprR 14 XDIR 15 2 16 7 PWRBTNJ 0120 a PWRBTN 26 A5 5 R SA9 BIOSA17 13 m BIOSA17 16 E4 PCIREQJ 5 2 a PCIREQ 16 D7 SA8 16 814 m BIOSA16 16 F4 sowo 815 SOWO 16 D7 ss 5 SA7 Posy OPS PCS 16 C7 EU a OFFPWRI 16 Fs SA6 OFF_PWR2 117 OFF PWR2 16 F5 vBAT 5 SAS sPKR D17 m SPKR 25 F2 27D2 FMI a RI 16 E7 SA4 SPLED SLED 16 D7 THRMJ E16 THRM 16 D7 2 SA3 ACPWR E20 ACPWR 16 E7 SA2 SMBCLK M16 SMBCLK 16 E7 pockj CE a DOCK 16 E7 GNpis 2 a RTS2 15 D4 18 D2 ids 1 R125 2 R 10K wie SA1 SMBDATA x SMBDATA 16 E7 M1543C GND14 DTR2 15 D4 18 D2 SA0 1543 7 8 ceNps FM es RTS1 15 D4 18 A2 Cii M9 1 R86 2 R 10K SU MET RTCAS m RTCAS 16 E2 4 9 ROMKBCS 16 84 10 B14 L12 1 R87 2 R 10K IOCHKJ IOCHK 24 A3 24 A7 25 C4 RTCRW RTCRW 16 F2 112 _ SERIRQ 16 B4 Nowsj NOWS 24 B2 24 B5 25 B4 RTCDS RTCDS 16 F2 GND10 11 9 2 XDIR 15 F2 16 B4 14 IOCHRDY 24
119. VDD PCI6 2 15 1 a 90 Se ig 028 167 PAD28 EBD4 Tx 121 a TX 22 A2 vDD pCls 51 4 pa OTI OTI UI Ap27 168 PAD27 EBD3 spi 122 pci 40 St 5 170 PAD26 124 31 AD26 EBD2 si 4 e vVDD_PCB 3 e 6 RIO E Ap2s 72 PAD25 EBDI 1 ARA 2 PCD 23 AD24 173 PAD2A EBDO EP 15 AD23 PADS EBDA IS 8 22 03 3 VDD PCIO 7 AD PAD22 TTE EBDAIS AD21 8 BAD EBDAI4 mE pwu 147 p20 2 PAD20 abii EBDA13 pu 45 L Ae 2 150 Api 11 PADI9 EBDA12 won 0146 138 _ apis 12 PADIS EOD EBDA11 pc 155 L 2 R vppp3 s N AD17 14 PADI7 EBDA10 PEDE VAUXDET 104 2 9 4 OTIL mm OTTA 16 PADI6 83 E E E AD16 EBDA9 GND 1 4 5 23 PADIS EBDAS 148 a 23 2 23 6 25 06 35 BADIA EBA 7 0 22 D2 53 a TDI 23 A4 23 A7 25 C6 AD13 36 PAD13 EBUA_EBA7 15 TDO 23 2 23 6 AD12 38 PADI2 _ TMs 19 TMS 23 A4 23 A7 25 C6 154 4 39 PADI 107 ADU EBUA_EBAS 4 197 4 4 PAD10 A143 70 UE URS 0 EBUA_EBA4 EAR O VDD3 e a Pe alm 158 TN IN Apo 42 mE EBUA EBA3 2 54 9 gt 22 47 PADS 26 E E E ADS EBUA 2 ax vpp1 26 9 50 PAD EBUA_EBA1 vppo 10 6 ADe 52 nade EBUA_EBAO pvppa H 9 1 2
120. a summary of the proposals presented by Real Time OS manufacturers and many middleware development manufacturers This is why hardware is configured so as to render OS and middleware easily portable 3 Ethernet controller PCMCIA controller serial controller and other peripherals are off the shelf purchases 4 Because Ethernet PCMCIA serial controllers and similar hardware are loaded on the board system development is easier with these pieces of hardware applied 5 The Solution Engine has the expansion slot outputting address bus and control signals of the SH7751R so that a user s hardware can be connected 6 The Solution Engine has an I O bus which carries an SH7751R port and the output of the timer output terminal 7 The Solution Engine has CPU bus interface connector so as to trace SH7751R bus signal Debugging Function The Solution Engine has a monitor program on the board The monitor program has the following debugging functions Execution and pause of user programs The program can be executed from an optional address When the following condition arises the user program halts a When a break point is detected b When the Reset switch or Abort switch is pressed 2 Display and change of register contents The contents of the general purpose register can be displayed and changed as required 3 Display and change of memory contents Memory contents can be expressed in mnemonic or hexadecimal numbers and changed as requi
121. d on the memory map These LEDs are useful for checking the operation of programs Read and write to address h BA000000 h 14000000 1 2 in 16 bit width land 0 written to each register become invalid because nothing is connected to D7 D0 Physical address when MMU is used 2 When MMU is used do not cache at the time of TLB entry TLB entry C bit 0 8bit LED h B9000000 h 19000000 1 2 Nothing is connected Write Corresponding LED is turned ON or OFF depending on data of 1 0 written in register Write 1 LED is ON Write 0 LED is OFF Figure7 15 Configuration of 8 bit LED 54 No fl ESI 8 Interrupt Controller The SolutionEngine has the interrupt controller FPGA1 U17 that determines the priority of interrupts output from each device Table8 1 lists the outputs of IRL3 IRLO signals of SH controlled by the interrupt controller Table8 1 Interrupt Level Cross Reference Table Interrupt SH7751R pin state Abort switch NMI signal Expansion slot SLOT_IRQ7 0001 Expansion slot IRQ7 setting Super I O INTR 0011 Super I O Expansion slot SLOT_IRQ6 1 0100 Expansion slot IRQ6 signal Expansion slot SLOT_IRQ5 10 0101 Expansion slot IRQ5 signal MR SHPC 01 IRQ1 PCIC SIRQI 0110 MR SHPC 01 register setting Not defined EE 0111 i i Expansion slot SLOT_IRQ4 1000 Expansion slot IRQ4 signal SLOT_IRQ3 1001 Expansion s
122. ect NMI probe when using IC socket equipped ROM emulator For test Super I O For test Super I O 20 4 LED Functions Power LED LED17 This LED indicates that the power is supplied correctly Function is as follows LED ON Power is supplied to the Solution Engine LED OFF Power is not supplied to the Solution Engine CPU Status LED LED9 LED12 This LED indicates CPU operation Function is as follows LED9 ON CPU is in RESET mode LED10 ON CPU is in SLEEP mode LED11 ON CPU is in STANBY mode LED12 ON CPU is under operating condition PC card detection LED LED13 This LED indicates that the PCMCIA controller detects the PC card normally LED ON PC card is detected LED OFF PC card is not detected Ethernet line monitor LED CN7 LED1 CN7 LED2 LED14 LED15 This LED indicates presence or absence of transmit signal and receive signal and connected condition of Ethernet line For mode details on LED refer to Section7 Function block HDD access LED LED16 This LED indicates access condition to HDD Function is as follows LED ON Accessing to HDD LED OFF Not accessing to HDD 8 bit LED LED1 LEDS This LED is 8 bit LED that can turn ON and OFF LED via register allocated to memory map of the Solution Engine For mode details on usage refer to Section7 Function block 21 5 Memory map Figure5 1 shows the memory map of the Solution Engine ROM Area Area for and EPROM Flash memory
123. ents of the Solution Engine Table 0 1 Solution Engine components SH7751R Solution Engine m Hardware 2 CD ROM Software User s manual C compiler Trial Version driver software source file various header file User s manual Monitor EPROM Monitor EPROM for big endian Vx xB x2 included Software License Agreement Condition to use software SH7751R Solution Engine main unit Q Monitor EPROM for big endian Software license agreement Figure0 1 Components of the Solution Engine 3 Table of Contents Notes on Using the SH Solution Engine 1 Components of the Solution Engine 3 Table of Contents 1 Features of the Solution Engine 1 1 1 Features of the Solution Engine 1 1 2 Debugging Function 1 1 3 System Configuration 2 1 4 Software Configuration 4 1 5 Solution Engine Specifications 5 2 Setting the Solution Engine 6 2 1 Connecting the Host System 9 2 2 Connecting the E10A Emulator 11 2 3 Connecting the Power 12 3 Switch Functions 13 3 1 Switch SWn Functions 13 3 2 Jumper Pin Functions 18 3 3 Test Pin Functions 20 4 LED Functions 21 5 Memory Map 22 6 Hardware Configuration 24 7 Function Blocks 26 7 1 Ethernet Control
124. er PC card bus I F MR SHPC 01 core Card SLOT a d z e Power Supply Control Circuit TPS2211IDB Figure7 12 PCMCIA I F control block 49 2 68 pin IC Card Connector CN17 Pin Assignments Table 7 15 lists the pin assignments of the 68 pin IC card connector CN17 Table 7 15 Pin Assignments of 68 pin IC Connector CN17 EI SESE ET ese s m s m 5 oe Ear rame FEE NIE ee ee ee Ds m x m a ae gt ae eese e ew 50 Register Map Table 7 16 shows a memory map of PCMCIA control register All registers should be accessed in word size Table7 16 Control Register value h B83FFFEA h l 83FFFE4 1 2 H 0000 Set operating mode of PCIC h B83FFFE6 h 183FFFE6 1 2 H 000C Control option function h B83FFFE8 i Mo h l 83FFFE8 1 2 H 03BF Monitor input signal from card h B83FFFEA I h B83FFFEC I us h 183FFFEC 1 2 H 0000 Interrupt control register Control interrupt occurrence condition h B83FFFEE 2 Control card power low power h 183FFFEE 172 g Mint SM a FER id h B83FFFFO H 7FC0 Memory window 0 Control system address area for 183 0 1 2 Control register 1 memory access h B83FFFF2 H 7FCO Memory window 1 Control system address area for h 183FFFF2 1 2 Control register 1 mem
125. er Pin Connected State Function Input 33MHz to SH7751 PCICLK at shipment 19 o 1 2pin closed Power supply is not provided to SH7751 PCICLK n ilo 2 3pin closed Test jumper2 J2 This jumper is the jumper for testing NMI pin Table3 4 shows the function of the jumper for testing NMI pin Use this jumper while pins 1 2 are closed When pins 2 3 are closed the microcomputer does not work Close pins1 2 and connect NMI clip to TP3 while ROM emulator is used Table3 4 Function of the jumper for testing NMI pin J2 Jumper Pin Jumper Pin Connected State Function J2 Abort switch can control NMI pin of the SH7751 at shipment 1 3 Close 1 2pin and connect NMI clip to when connecting ROM emulator by using ROM socket 1 2pin closed Abort switch makes NMI pin of the SH7751 unconnected J2 NMI pin is connected to CPU bus interface Qm 3 Close 2 3pin when connecting ROM emulator by using CPU 2 3pin closed bus interface connector 18 4 Test Jumper3 J3 This jumper is the jumper for testing ATX power supply control Table3 5 shows the function of the jumper for testing ATX power supply control Use this jumper with 2 3pin closed When 1 2pin is closed ATX power is in ON state at all times and the power supply switch on the Solution Engine become invalid Table3 5 Function of the jumper for testing ATX power supply control Jumper Pin Jumper
126. h as hyper terminal mounted as a standard accessory of Windows 95 can be used The source programs input by using various editors can be converted into machine language by using the C compiler the assembler the linkage editor and the object converter Figurel 3 shows software configuration when the Solution Engine is connected to the host system For more details on the functions and the usage of the supplied software refer to ReadMe txt in the CD ROM Host system OS Host syste C compiler SHC EXE Interface software Cross assembler ASMSH EXE Hyper terminal etc Linkage editor LNK EXE Serial interface Monitor program Solution Engin User program execution 5 Reverse assembler Break function Memory control functio control function function Figure 1 3 Software Configuration when connected to the Host System 1 5 Solution Engine Specifications Tablel 1 lists the functional specifications of the Solution Engine Table1 2 lists the specifications for the power supply dimensions and environmental factors Table 1 1 Functional Specifications of the Solution Engine Specifications Subject device SH7751R SH 4 PCI System Clock Operation frequency Internal 240MHz External 60MHz Maximum 81MHz 20MHz oscillation module is equipped Oscillation module model name SG 8002DC 20M PTCB SEIKO EPSON User memory 64 MByte SDRAM Cycle time 10ns SDRAM model name uPD45128841G5 A75 9JF ELPIDA ROM Flash ROM
127. he host system screen after connecting the Solution Engine to the host system via a RS232C cross cable and the monitor program is started C Copyright 1999 2005 Hitachi Ltd All rights reserved H elp for help messages x x means monitor program version n is changed depending on endian A Little endian B Big endian 63 Download user program Use the ml command to transfer the user program to user RAM Input ml in response to a command prompt as follows Ready gt ml After inputting the command the following transfer request message is output from the monitor program and the message is displayed on the host system screen Please Send A S format Record When the message is displayed send the S format object file by using the file transfer function of the communication software Address information is also added to the S format object file Allocate the object program according to this address information For it is a relocatable file that does not have specified address in object file specify the offset address with the ml command as follows The specified address should be within the user area shown in Figure 13 1 Upon completion of loading into memory the following message is displayed on the host system screen In this example the program is loaded from address H AC100000 of area 3 Start Addrs AC100000 End Addrs AC1000BC Transfer complete Display and change register contents
128. it s SW5 1 ON SW5 2 OFF 119200bit s SW5 1 OFF SW5 2 ON 38400bit s SW5 1 ON SW5 2 ON 115200bit s Select ROM placed h 0000000 h OOFFFFFF and h 01000000 h 01 FFFFFF SW5 3 ON SW5 4 ON At shipment h 00000000 h 003FFFFF EPROM h 01000000 h 013FFFFF Flash ROM SW5 3 OFF SW5 4 ON h 00000000 h 003FFFFF Flash ROM h 01000000 h 013FFFFF EPROM SW5 3 ON SW5 4 OFF h 00000000 h 003FFFFF CPU bus I F connector CN20 h 01000000 h 013FFFFF Flash ROM SW5 3 ON SW5 4 OFF h 00000000 h 003FFFFF CPU bus I F connector CN20 h 01000000 h 013FFFFF EPROM Select whether to use peripheral LSI of CS6 area on the Solution Engine SW5 6 ON At shipment Use peripheral LSI of CS6 area SW5 6 OFF Peripheral LSI MR SHPC 01 placed at CS6 area is allocated at CS1 All space of CS6 is allocated to expansion slot This switch can be used for evaluating a daughterboard using CS6 This switch is for testing SW5 5 ON SW5 7 ON SWS 8 ON At shipment Do not change the factory shipped setting 17 Jumper Pin Jn Functions Test Jumper J1 This jumper is the jumper for testing SH7751R PCIC Table 3 3 shows the function of the jumper for testing SH7751R PCIC This jumper must be used while pins 1 2 are closed When pins 2 3 are closed microcomputer does not work Table3 3 Functions of the jumper for testing SH7751R PCIC J1 Jumper Pin Jump
129. layed Flash chip erase After completion of erasing Flash ROM the following message is displayed and writing is started Flash chip erase complete Program After completion of writing command prompt is displayed on the screen Program complete Flash write complete Ready 69 Power supply is N connected to CN16 Y Remove power supply from CN16 Connect the host system via RS 232C cable 9pin cross cable N Little endian Mount Vx xB EPROM on 42 pin IC socket M7and M8 Turn OFF SW4 6 Use big endian mode Y Big emdian Mount Vx xB EPROM on 42 pin IC socket M7and M8 Turn ON SW4 6 Turn ON SW5 3 SW5 4 Connect power supply adapter to CN16 Start up hyper terminal on the host system Turn ON reset switch SW2 Starting message is displayed on the host system screen Y Write to FlashROM by using the FL command N Execute the program written to the Flash ROM Y Disconnect the power adapter from CN16 Turn OFF SW5 3 and turn ON SW5 4 Connect the power adapter to CN16 Turn ON Reset SW SW2 Comletion of writing Remove the power adapter from CN16 Confirm the cable connection and communication protocol Connect the power adapter to CN16 Figurel3 2 Procedure to write to Flash ROM 70 13 2 Monitor Program Function List Table 13 2 lists the commands of the monitor program Table 13 2 List of Monitor Functions Memory 71 14
130. llows 1 Choosing the debugging environment The Solution Engine has a monitor program stored in EPROM Connect the host system equivalent of FLORA310 to use the monitor program The monitor program is an implementation of the basic functions including reference and change of memory data and execution of programs Use E10A emulator for trace of user programs and other debugging 2 Connecting a daughterboard When using a daughterboard connect the cable to the expansion slot CN1 on the Solution Engine 3 Connecting the modem Connect the modem to M1543C COMI connector CN3 M1543C COMI connector outputs all signals necessary for connection of the modem 4 Connecting the LAN Connect the LAN to the RJ 45 connector CN7 via the Ethernet hub 5 Connecting the I O board Use the I O connector CN18 to use SH s general purpose I O port The I O connector outputs all general purpose ports of the microcomputer 6 Setting Jumper Pins and DIP SW Set jumper pins and the DIP SW according to the operating condition 7 Connecting the power supply Connect power supply cable of ATX power to CN16 Do not connect to CN16 while ATX power supply remains connected to 110 Notes 1 Before connecting ATX power supply to the 110V AC power following upon completion of Steps 1 through 7 above recheck that connection of the board and a cable and setting of jumper pins and DIP switches are correct 2 When using Etherne
131. lot IRQ3 signal Not defined 1010 a SLOT_IRQ2 1011 Expansion slot IRQ2 signal Not defined m 1100 Expansion slot SLOT_IRQ1 Expansion slot IRQ1 signal 1110 MR SHPC 01 register MR SHPC 01 IRQO PCIC_SIRQO 55 9 Expansion Slot CN1 9 1 Expansion Slot Pin Assignments Table 9 1 lists the pin assignments of the expansion slot SH bus signals data bus address bus and control signals are connected to the expansion slot via buffers 74ALVCH16244T 245T Electrical level is 3 3V When LSI or the IC that need 5V interface are mounted mount the IC with 3V SV interface on the daughter board The symbols listed in Table 9 1 have the following meanings OUT Output IN Input BO Buffer output BI Buffer input P UP Pull up Table 9 1 Expansion Slot Pin Assignments Column A Pin Assignment Pin Assignment Remarks Remarks a Al6 o o d gt e g g c c alyl y gt d a d d d 351515 5 513 T WEO A53 WE2 W AITO BI P UP WAIT2 BI P UP IRQI BI P UP IRQ3 BI P UP IRQ5 BI P UP A61 IRQ7 BI P UP Option RES FE Spare pin Option Option Spare pin IN EPERE amp 2 gt o gt n d IN IN Option ojo SI d Option Reserve OU gt 6 gt gt
132. munications software Any communication software for personal computer communications can be used Hyper terminal Windows terminal and etc Set communication software as listed in the table13 1 The transfer rate can be selected with the DIP switch SW5 1 5 2 on the Solution Engine For details refer to Section 3 1 4 DIP Switch for setting baud rate SW5 This monitor program outputs CR LF as a line feed code Table 13 1 Communication specifications Control flow Xon Xoff Data communication speed 9600 19200 38400 115200 bit s 2 Monitor Program Specifications Figure13 1 shows the address map of the monitor program Do not write at the area used by the monitor program H ODF00000 H ODFFFFFF For more details of each memory area refer to Section 5 Memory Map 62 h 00000000 Monitor Program ROM area h 0001FFFF 32bit bus width h 00020000 h O3FFFFFF h 04000000 Areal Expansion Areal Option bus width h 08000000 2 Option bus width h 0C000000 User Area Monitor Program Use Area h ODFFFFFF SDRAMarea h 0E000000 64bit bus width Work Memory h OFFFFFFF Peripheral Device Control Area 4 Register Area 16bit bus width h 14000000 per rea Expansion Area 5 Option Bus Area h 18000000 dedo Area for PCMCIA 16bit bus width Figure 13 1 Memory Map Real Memory Space Starting Monitor Program The following starting message is displayed on t
133. n be assigned to both memory and I O because Am79C973AVC is connected to device number0 IDSEL AD 16 DWIO 0 DWIO 1 h 00 h 00 APROM APROM h 10 RDP h 10 RDP h 16 hic BDP Figure 7 2 Ethernet memory map BDP h 18 27 Am79C973AVC PCI Configuration register Table 7 1 shows a configuration of the PCI configuration register The PCI configuration register is assigned to allocate Am79C973AVC on the PCI bus Table 7 1 Configuration of DP83902A Register 28 Control and Status register Table7 2 shows a configuration of Control and Status register CSR sets address of CSR to RAP and accesses from RDP Table7 2 Configuration of Control and Status register 9 15 CSRI5 MODE Mode Register see register description 16 T i 18 CRBAL Current RCV Buffer Address Lower Note RAP Addr 01 02 03 05 07 10 12 13 14 5 5 0 B NN EN 06 O 10 2 u undefined value R Running register S Setup register T Test register all default values are in hexadecimal format 29 Table7 2 Configuration of Control and Status register RAP CXBC Current Transmit Byte s www 56 CSRS6 uuuuuuuu Reserved 5r csrs7 58 CSR58 SWS Software Style S 5 Reed 6 CSR60 uuuu uuuu PXDAL Previous XMT Descriptor Address Lo
134. n of the bus configuration register Programmability Mnemonic Default MSRDA 0005 MSWRA 0005h M 0002h Miscellaneous Configuration No No N Yes LEDO 00COh LEDO Status LEDI 0084h LED Status Yes Yes Yes Yes LED2 0088h LED2 Status 7 LED3 0090h LED3 Status Z o o jo 0000h Full Duplex Control 105 IOBASEL N A IOBASEU BSBC 9001h Burst and Bus Control EECAS 0002h EEPROM Control and Status INTCON N A Reserved PCILAT FFO6h PCI Latency PCISID 0000h PCI Subsystem ID SW 0000h Software Style Y PCISVID 0000h PCI Subsystem Vendor ID SRAMSIZ 0000h SRAM Size SRAMB 0000h SRAM Boundary z Y Y SRAMIC 0000h SRAM Interface Control EBADDRL Expansion Bus Address Lower EBADDRU Expansion Bus Address Upper Ye Ye N STVAL FFFFh Software Timer Value n PHY Management Data 0000h No No Yes No Yes Yes Yes Yes No Yes No No No Yes Yes Yes No Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes lt 5 Yes Yes es 2 2 EA m 1045 16 EA 387 s 20 2 23 EM 25 26 27 28 29 30 32 EA p 36 2 o gg DATA2 0000h PCI DATA Register
135. ns 1 Power supply switch SW1 This switch is to turn ON and OFF power supply of SH7751R Solution Engine This switch is a push button switch Power supply is turned to ON or OFF by pushing this switch Figure 3 1 Power supply switch 2 Reset Switch SW2 This switch is to reset microcomputer This switch is a push button switch The microcomputer is reset by pushing this switch Reset is cleared by releasing this switch Notes While ROM emulator is used ROM emulator controls reset of the microcomputer Do not operate the reset switch when connecting the ROM emulator Figure 3 2 Reset switch 13 3 Abort switch SW3 This switch controls NMI pin of the microcomputer This switch is a push button switch NMI pin is turned to Low by pushing this switch NMI pin is turned to High by releasing this switch Notes ROM emulator controls NMI pin while ROM emulator is used Do not operate the abort switch when connecting ROM emulator Figure 3 3 Abort switch SW3 14 4 DIP switch for setting microcomputer operating mode S W4 Figure3 4 shows the DIP switch for setting microcomputer operating mode SWA Table3 1 shows switch functions This switch is connected to mode pins MD0 MD9 of the SH7751R This switch can select the operating mode and endian as shown in table3 1 This switch must be switched while the power supply is in OFF state mm Figure3 4 DIP switch for setting microcomputer operating mode SW4
136. o 1068 Q 15 0 RD MWE I 0 WET1 0 RES 24 CLR 3 reg16 0115 1 pits o Do 15 0 Ste 68 Q 15 0 RD wef1 0 RES CLR reg16 Di5 0 lpi5 0 Do 15 0 105 Q 15 0 RD BD WE I L0 WE 1 0 RES CLR i reg16 0115 1 Dil15 0 Do 15 0 0 Q 15 0 RD WEN wef1 0 ES Qj olR cso NOT cst 1 YIN 2 B Y2N E Y3N e 4 G1 YAN T NOT pu zBORCS BNANDS G2AN YSN NOT Cee 5 G2BN e As e To 3 8 DECODER i reg16 DoA 15 0 Di 15 0 0115 0 091570 DoE 15 0 TIRQ 15 0 cs4 cs Q 15 0 RD MWE I 0 _ 0 ORES CLR reg16 DoB 15 0 Di 15 0 515 0 6915 0 DoF 15 0 CSS CS als RD RD wef1 0 RES CLR P reg16 DoC 15 0 Di 15 0 6115 01 Do i5 0 DoG 15 0 086 cs Q 15 0 RD BD WE I L0 wen o RES CLR idr DoD 15 0 CS7 CS 65 0 DoH 15 0 RD RD Po poris o 5 0 jns o OR8 DoA 15 0 DoB 15 0 DoC 15 0 DoD 15 0 DoJ15 0 DoE 15 0 gt DoF 15 0 DoG 15 0 DoH 15 0 RD So 88 lt WEI1 0 NOT WE 1 0 TIRQ 15 0 gt TIRQ 15 0 Board control register 2 bcr2 INT 15 0 INTITS 0 D ouu D IRL 3 0
137. ort EPP h 0 h 00000378 Data Port h 1 h 00000379 Status Port h 2 h 0000037A Control Port h 3h 000087B ADDR EPP Address Port h 4n 0000037 DATAO j EPP Data Port h 5 000087D 1 DATAI EPPData Port h 6h 000057 DATA2 EPP Data Port2 h 7h 0000037F DATA EPP Data Por Table7 5 2 Parallel port register Extended Capacities Parallel Port EPC Name h 000 h 00000378 data Data Register 000 001 ecpAFifo ECP FIFO Address 011 h 001 h 00000379 h 002 h 0000037A Control Register h 400 h 00000778 cFifo Parallel Port Data FIFO 010 ecpFio ECP FIFO Data tFifo Test FIFO cofigA Configuration RegisterA h 401 h 00000779 Configuration RegisterB h 402 h 0000077A Extended Control Register 40 25 pin D sub parallel connector CN4 pin assignment Table7 6 lists pin assignments and functions of 25 pin D sub connector CN4 Table7 6 25 D sub parallel connector CN4 pin assignment name 1 STROBE STB WRITE 2 VO PDO i O 3 DI 4 12 1 175 5 5 WO pps 2 7 105 MOIPDS 8 Jp 0 i 2 C 0 10 1 ACK u Busy I Busy IE UP 0 0 0 5 7 13 SLCT I ISLCT 14 AUTOFD VO AFD DSTRB 15 ERR I ERR UO NT IO SLIN ASTRB 2 2 e Hi 2121212 i Q S O OS ISIS IO oae Z Z
138. ory access h B83FFFF4 H 7FC0 I O window Control system address area for I O h 183FFFF4 1 2 Control register 1 access h B83FFFF6 Memory window 0 h 183FFFF6 1 2 H 0000 Control register 2 Control access condition to card h B83FFFF8 Memory window 1 m h 183FFFF8 1 2 H 0000 Control register 2 Control access condition to card h B83FFFFA i T O window aA h 183FFFFA 1 2 H 0000 Control register 2 Control access condition to card h B83FFFFC h 183FFFFC 1 2 H 0000 Card control register Control card mode h B83FFFFE Y h 183FFFFE 1 2 H 5333 Chip information register Chip Revision Physical address when MMU is used 2 When MMU is used do not cache at the time of TLB entry TLB entry C bit 0 51 7 4 Memory Block EPROM and FlashROM are placed at area 0 and SDRAM is placed at area3 Figure7 13 shows a memory map of area 0 As shown in figure7 13 the assignment of EPROM M7 M8 and FlashROM M1 M2 can be changed depending on the state of SW5 5 SW5 4 and SWS 3 EPROM and FlashROM are placed at area 0 which bus width is 32 bit Two EPROM and two FlashROM with 16 bit bus width are used to connect to 32 bit bus Assignment of EPROM and FlashROM is as follows High order 16 bits M7 MI Low order 16 bits M8 M2 h 00000000 h 00000000 EPROM M7 M8 h 003FFFFF h 003FFFFF H h 01000000 Flash RO H h 01000000 Flash ROM M1 M2 EPROM M7 M8 MI M2 h 013FFFFF h 013FFFFF
139. red 1 3 System Configuration Figurel 1 shows a system configuration of the Solution Engine Figurel 2 shows an external overview of the Solution Engine Connect a host system a modem and an Ethernet Hub to the Solution Engine according to the debugging environment and peripherals such as a modem User must prepare a host system a modem and an Ethernet hub The host system the modem the Ethernet hub and power supply used to check the operation before shipping are as follows Host system Hitachi FLORA310 and 330 Windows 95 machine with 9 pin serial connector Modem Microcom V 34ES II Ethernet Hub 8 Port Ethernet Hub Power supply ATX power supply Notes Ethernet may encounter an abrupt drop of signal level and the line cannot be connected depending on the number of hub line connections or cable length When connecting the Solution Engine to the hub reduce the number of lines connected to the hub to a minimum to ensure reliable operation Windows is a trademark of U S Microsoft Corporation ais power supply Solution Engine 5V 12V 3 3V AC 110V power supply Host system FLORA310 or equivalent 10BASE T 0000000000 LJ RS 232C cross cable Figure1 1 System configuration of the Solution Engine Ethernet 100 5 IEEE1284 parallel port PS2 connector RJ 45 connector connector Top Mouse Bottom Keyboard LED for LAN cu
140. s 215 01 iLCRA IS 0 L_ILGRAI15 0 _ DA 15 0 CS0 oS CS0 WE 0 J WE 1 0 RD SES RES ilcrb AND3 ilerg AND3 SO 5 0 ILCRB5 L__ILCRBI15 0 _ DB 15 0 515 0 5 0 ILCRG 15 0 LCRGH5 01 DG 15 0 lt CS1 Aces CS1 CS6 Al es CS6 WE 1 0 WE 1 0 RD WE 1 0 WE 1 0 RD RES 4 RES 4 ilcrc AND3 ilcrh AND3 Dins pp5 o iLCRC 15 0 0805 0 DC 15 0 D 5 0 05 0 itcRHn5 CRHTS0L DH 15 0 CS2 CS2 CS7 oS CS7 WE 0 J WE 1 0 RD WE 0 J WE 1 0 RD mE RES mE RES ilcrd AND3 Di 15 0 015207 ILCRDT5 0 2 DB CS3 WE 1 0 0 RD 74138 cs Yon D 930 RES al RES YIN O em s CS3 fy YaN O SO piso iLCRE 15 0 EERENS mm DE 15 0 G YAN 294 4 0 CS4 7 Su BORES i G2AN Y5N P 2 ZWEM we 1 0 RD A G2BN P A Y7N RES RES AS 3 8 DECODER 4 ilcrf AND3 D 5 0 pfi5 iLCRF 15 0 CRFHS 0L DF 15 0 CS5 CS5 WE 1 0 WE 1 0 RD RES dq RES dE CS 7 0 CSI7 0 RD RD Interrupt Level Control Register ilcr G1 G2AN G2BN 4 je OUTPUT NAND4 OUTPUT
141. sIN ST ae Spa VT MES al al 24 op 25 SV EN SD 5V 5 EZ a 55 cL on con on on SES STE 1 2 6 Bly 1 4 a 9 a 9 9 C 0 1uF VV GND 19 gt 5 C198 55 GND GND GND GND GND GND GND GND 1 SP211ECA oru C 0 1uF a G4 G4 813 U2 wo 5 lt OT Fu cn L5 OT Ft RES i G4 G4 CN12 14 ci c2 6 x 9 1 9 2 RxD 7 2 64 4 1504 SOUT2 w TIIN TIOUT n 9 TxD 15 D4 16 C7 DTR2 m 6 T20UT 3 n 4 DTR 15 D4 16 C7 RTS2 20 T30UT L 5 GND 21 rain T40UT 8 6 DSR 9 7 RTS 9 64 8 15 4 DCD2 RIOUT RIIN CTS 15 D4 SIN2 R2IN 4 a 9 5 15 D4 DSR2 26 R30UT 22 10 22 23 64 ux E x HN 15 D4 CTS2 m R4OUT R4IN Re 5 i HIF3FC 10PA 254DSA 19 18 G4 5 8 5 22 2 22 2 87 GND 15 D4 RD m RSOUT RSIN mu Ts Ty vr COM2 al al S 24 on 25 E UE ED T E gt Es Soar EN SD ese 9 82 5 C TN 1 2 69 Bly yec i a al a C 0 1uF VV e NAE 1 1 1 1 1 1 1 C204 amp GND GND GND GND GND GND GND GND 1 SP211ECA as C 0 1uF a V 35V o 7 27 2000 14 39 PAGE 18 1 2 3 4 5 6 7 8
142. t be sure to connect through HUB It may be unable to communicate if the Solution Engine is connected directly to PC via a cross cable Figure 2 1 shows the procedure to install the Solution Engine Start Installation Open the package and check the contents to match against the packing list Use development device Use the limited monitor program N Little endian Y Big endian Remove EPROM MX27C8100 on 42 pin IC socket M7 and M8 from the IC socket Mount monitor EPROM Vx xB for big endian Mount monitor EPROM Vx xA for big endian on a 42 pin IC socket M7 and M8 on a 42 pin IC socket M7 and M8 Turn SW4 6 ON Turn SW4 6 OFF Use ROM emulator Connect ROM emulator to 42 pin IC Connect CN2 to host system via RS232C socket M7 and M8 cable 9pin cross cable N Connect the daughterboard Y Connect the daughterboard to expansion slot CN1 N Use RS 232C connector CN3 Y Connect a cable to RS 232C connector CN3 Use 10 5 N Y Connect 10BASE T cable to CN7 Connect I O board using SH7751 port and private pin Y Connect I O board to CN18 N Use keyboard and mouse Y Connect keyboard and mouse to CNS 4 N Connect USB function device Y Connect USB function device to CN6 Figure 2 1 Installing the Solution Engine Use IEEE1284 board Y Connect IEEE1284 cable to CN4 Mount PCI board Y Mount PCI board to CN8 and CN9 Mount ISA board N Mount ISA board to CN10 and CNI1 N
143. uipment and a daughterboard the power must be turned off 3 Before turning on the power following the connection of cables and other equipment check all connections again to be sure that the wiring and polarity are correct Installation 4 Do NOT touch some parts on board during operating because their temperature is high Whenever you want to touch them you must turn off the power and keep enough time to cool down 5 The Solution Engine is developed for evaluation of products before they are put under the development phase Do not incorporate the Solution Engine into any of the products 6 Do not install the Solution Engine in an area subject to direct sunlight and other areas exposed to heaters or other source of high temperatures 7 Do not choose area subject to extremely dusty condition 8 Usecare to keep the board free from contact with pieces of wire soldering waste and other foreign matter Restriction 9 OS of the host system connected and checked before shipping the Solution Engine is Windows 95 In using Solution Engine by OS other than Windows 95 please use after checking enough 10 Please connect the included power supply adapter to the Solution Engine Although the power supply terminal stand is mounted in Solution Engine please do not use it as much as possible 11 When using Ethernet be sure to connect through a hub It may be unable to communicate if Solution Engine is connected directly to PC via a cross cable
144. wer T CSRG uuum PXDAU Previous XMT Descriptor Address Upper T PXBC Previous Transmit Byte Count 4 4 4 4 44 4 4 4 4 4 34 35 36 37 38 39 0 1 2 3 2 6 7 8 9 50 51 52 53 54 CsR65 uum wuu NXBAU Next XMT Buffer Address Upper T 6 CSRee NXBC Next Transmit Byte Count wwo Revered 2 I i T 6 wmwm Revered O Ooo sasi ESE emm wes Resend C1 30 Table7 2 Configuration of Control and Status register Use T T S 262 5003 Am79C973 i 262 7003 Chip ID Register Lower Am79C9 75 Chip ID Register Upper T 7 7 7 7 7 7 7 7 7 Addr 72 4 76 s 80 81 82 83 1 2 3 5 6 7 8 9 1 2 7 8 2 5 g Q 4 8 83 8 8 9 shes 0 14 CSR104 wuwu wawu Reserve _ Reened 717 7106 Reened Reserve 717 a N 31 Table7 2 Configuration of Control and Status register RAP 1 9 MAC Enhanced Configuration Control T 126 CSRI26 uuuuuuuu Reserved 127 CSRI27 Reserved 4 4 4 4 8 32 Bus Configuration register Table7 3 shows a configuration of the bus configuration register BCR sets address of BCR to RAP and accesses from BDP Table7 3 Configuratio

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