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ISE Simulator (ISim) In-depth Tutorial

1. Ms FOG XS I drp stmach reset 0 le user dcm reset Nu E drp multiplv 7 0 drp divide 7 0 dcm clkt out Is l dem clkFx out i dcm locked Ud period m Default wichg Figure 4 11 Wave Configuration Running the Simulation for a Specified Time You can now run the simulator for a specified time Run the simulation for 5 microseconds us You can do so by either ISE Simulator ISim In Depth Tutorial www xilinx com 29 UG682 v1 0 April 27 2009 Examining the Design 30 XILINX e Typing 5 us in the Simulation Time field on the menu toolbar refer to Figure 4 12 then either Pressing the enter key e Clicking the Run For pt toolbar button or Select the menu command Simulation gt Run for p Sus v Gs i a DO EX ts pg Pun For the time specified an the toolbar Figure 4 12 Simulation Time Field e Typing run 5 us in the Tcl prompt refer to Figure 4 13 then pressing Enter Console This is a Full version of ISim Time resolution is 1 ps I5im runs us Console Breakpoints Search Results Figure 4 13 Sim Tcl Prompt The wave window now shows traces of the signals up to 5 microseconds in simulation time Refer to Figure 4 14 2 000 000 ps clk_in lis drp_start drp change mode 0 le drp_current_mode fo lis drp done lk drp stmach reset i ie user dcm reset T POOKY Bil
2. To add dividers to the wave window 1 Right click anywhere on the wave window select New Divider 2 Enteraname for the divider Use the instructions above to add three dividers named e TEST BENCH e DCM e DRP CONTROLLER Move the TEST BENCH divider to the top of the list by clicking the divider name and holding the mouse button down while moving the cursor to the top of the list Move the other dividers to the bottom of the list Note Divider names can be changed at any time by double clicking on the divider name or pressing the F2 function key and entering a new name Your wave window should be similar to the one shown in Figure 4 18 with groups collapsed 2 O00 O00 ps TEST BENCH is clk in user dcm reset period Wh DRF Test Signals L OCM Test Signals DM DRP CONTROLLER Default wichg Figure 4 18 Wave Window Adding Signals from Sub Modules You will now add signals from the instantiated DCM module Inst drp dcm and the instantiated DRP controller module Inst_drp_statmach in order to study the interactions between these sub modules and the test bench test signals ISE Simulator ISim In Depth Tutorial www xilinx com 33 UG682 v1 0 April 27 2009 Examining the Design XILINX Follow these steps to add the necessary signals 1 In the Instance and Process panel expand the hierarchy by clicking once to the left of each child module refer to Figure 4 19 Simulation objects
3. ma drp diseno f oo000100 lk dcm elk aut lk dcm clkFx aut lis dcm locked 10000 Fs gt El Default wicfg w w Figure 4 14 Wave Window Note www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design Use b u command Edit Zoom Zoom Full View or click the Zoom Full View icon to view the full time spectrum You can use the horizontal and vertical sliders to view the full wave configuration There are assertions from the test bench during the time of simulation Review the Console panel for messages from the test bench Refer to Figure 4 15 Console at 3461664 ps Note drp_demo_tb Test 2 START Set DCM CLKFX OUT 120 MHz 8 332 ns via DRP Cyde M 7 D 5 at 3755 ns 2 Note drp demo tb Test 2 Achieved DCM LOCK at 3766426 ps 3 Instance drp demo tb Warning Console Breakpoints Search Results Figure 4 15 Console Panel In the next tutorial steps you will be analyzing the simulation of the tutorial design in more detail using features from the wave window such as dividers groups cursors and markers Before you continue restart the simulation to clear the wave window and set the simulation time to 0 picoseconds ps Restarting the Simulation To restart the simulation either e Click the Restart a icon in the menu toolbar e Run menu command Simulation gt Restar
4. Debugging the Design Now that you have examined the design using markers cursors and multiple wave configurations you will now use ISim debugging features such as setting breakpoints and stepping through source code in order to debug the design and address the two failing DRP tests Viewing Source Code First take a look at the test bench for the tutorial design and learn how each test is performed To open a source code read only mode either e Select File gt Open to point to the file of choice e Inthe Instances and Processes Panel right click on the design unit described by the source file of interest then select Go to Source Code e Inthe Objects Panel right click on any of the simulation objects declared in the source file of choice then select Go to Source Code e Inthe Source Files Panel viewable by clicking on the Source Files tab double click on the source file of choice 48 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Debugging the Design Use the directions above to open the source code for the tutorial design test bench drp demo tb vhd The source file will be opened using the integrated text editor See Figure 4 46 FA ISim drp_demo_tb vhd i I Ix X File Edit View Simulation Window Help fle PAR ee E x amp vo oO MBA Om Kx Xx EIE EA e P p 1 00us v Ge ii Source Files pm X Objects 0 x ze Simulation Obje
5. Inputs Internal and Outputs for each set of signals recently added Note Use the object icon to the left of the signal name to determine the type of the simulation object Figure 4 23 ISE Simulator ISim In Depth Tutorial www xilinx com 35 UG682 v1 0 April 27 2009 36 Examining the Design XILINX Signals d Input Port 1h Output Port d InOut Bidirectional Port lb Internal Signal iB Constants parameters and generics 18 Variable u Linkage Signal Figure 4 23 Signals and Icons Your wave window should be similar to the one shown inFigure 4 24 with groups collapsed z 000 000 ps TEST BENCH clk in user dcm reset b period b Hh DRP Test Signals b Wh DCM Test Signals Tu Inputs Bm 55 5609 YYY i l Outputs W Internal ARP CONTROLLER CRF CONTROLLER Inputs Outputs P P P Internal T Default wcfg Figure 4 24 Wave Window Changing Signal and Wave Window Properties Next you will change the properties of some of the signals currently shown in the wave window in order to better visualize the behavioral simulation Changing the Signal Name Format By default ISim adds signals to the waveform using the short name hierarchy reference removed For some signals it is important to know which module they belong to You will change the format of the following bus signals from Short to Long listed under the DRP Test Signals group www xilin
6. Set DCM CLEFX OLIT 120 MHz 8 332 ns via DRP Cycle M 7 D 5 at 3755 ns 2 Hote Cfdrp dema Eb Test 2 Achieved DOM LOCK at 3766426 psia Instance fdrp dema kb Warning Test 2 END FAILURE CLEFS actual period does nat match expected Expected 8 332 ns Actual 7 142 ns Search Results Figure 4 38 Test 2 Fails Due To Period Discrepancy Console at 10371 ns Note fdrp demo tb Test 4 START Set DCM CLKFX OUT 400 MHz 2 5 ns via DRP Cycle M 3 D 1 at 10665 ns 2 Mate ffdrp demo Eb Test 4 Achieved DCM LOCK at 10668332 ps 3 Instance Jdrp demo Eb Warning Test 4 END FAILURE CLKFX actual period does not match expected Expected 2 5 ns Actual 3 332 ns Console Breakpoints Search Results Figure 4 39 Test 4 Fails Due To Period Discrepancy In the next few steps you will use the ISim main cursor yellow cursor to zoom in the wave window when one of the failing tests takes place You will also use the cursor to measure the period of signal dcm clkfx out and verify that the test bench is making accurate measurements Zooming In Let us first zoom in when Test 2 starts to review the status of output clock dcm clkfx out To use a cursor for zooming in on a specific area 1 Place the cursor on the desired area You can do so by Dragging the main cursor yellow cursor close to the marker that represents the start of Test 2 marker at time
7. 2009 XILINX Debugging the Design Fixing Bugs in the Design By using breakpoints and stepping you have determined that the incorrect multiply and divide values are assigned to signals drp_multiply and drp_divide in the test bench In the next steps revise the test bench test vectors to use the correct Multiplier and Divider parameters in tests 2 and 4 1 Close the ISE Simulator by selecting File gt Close Note f changes have been made to the wave configuration before the last save ISim will remind you to save changes prior to closing the session Using a text editor open the test bench source file drp demo tb vhd In lines 117 through 127 test vectors for the 4 DRP tests are defined Revise the constant declaration to read changes highlighted in bold TEST VECTORS Test Frequency Period Multiplier Divider constant test vectors vector array ie 1 75 13332 ps 3 4 L 2 120 8332 ps 6 5 3 250 4000 ps 5 2 4 400 2500 ps 4 1 4 Saveand close the file Verifying Bug Fix Now that the test bench source code has been fixed you need to re compile the source code and build a new simulation executable 1 Re launch the ISE Simulator Ifyou are using the Sim ISE Integrated flow in Project Navigator re launch ISim by double clicking on Simulate Behavioral Model If you are using the ISim Standalone flow re launch the ISE Simulator by running the fuse script
8. ae 7 nare t da dan d a dd daf n e a al 28 Addie ES ese arme v tale o zac de a aa seta pian i inta i ride Sates pl ll ai 28 Running the Simulation for a Specified Time 0 0 eee eee 29 Restarting the SIEU la PLOI esae ace aan ai aaa dade Di jacta d dal 31 ACG GlOUDS ia ni ara am tan a d a d alea aceon a e aa n i Rares 32 Addins Divide voe mata ipm ety le alei ra ieri qui pe iale peque e 8 ap atoli ploi 33 Adding Signals from Sub Modules ccne cece ee 33 Changing Signal and Wave Window Properties 0 0 0 essen 36 Changing the Signal Name Format i e a PR stnik nta da da a EG deas 36 Changing the Seal Radix Forma 4 5065s gir Rus odora hase Vo dde hod ade 37 Changing the Siena Color a o ides ie e hoi de E e nad A did A d ned Shes dl di 37 Floatine the Wave WindOW 2s nca e ove seers tte mede mi Beans ooh tS dees 38 Saving the Wave Window Configuration 0 0 cece eee eee 39 Usine Markers PPP odes denne eqie di iii nl loc de n pt ao 40 SI e CONOS nani e Boa ca pt s iu n and d ana i d ia hanes atu a ol ai 4 42 ZOOMING Ms o sur daf Senna one oda e tin intii t ria Leneege nee A 43 MEA ile LENE Boo REN TORRE do i e n ewan ena 8 ae eee ee ee d i ma ua 44 Using Multiple Wave Configurations ceea 46 Debugging the Design cc ea 48 MICWING SO URCE CODES zapacit dani gari mi eet epee dati et ai et TUE 48 Using Breakpoints and Stepping c cn 49 Sete Break PONS TU HC dou at lt
9. 3 461 664 ps The cursor will snap onto the marker e l Click the Previous Marker or Next Marker toolbar icons to quickly move the main cursor from marker to marker Select Edit gt Go To and specify the time when Test 2 starts time 3 461 664 ps The main cursor will now move to this time location ISE Simulator ISim In Depth Tutorial www xilinx com 43 UG682 v1 0 April 27 2009 Examining the Design XILINX 2 Zoom in by either Clicking the Zoom In toolbar icon Selecting the menu command View gt Zoom gt Zoom In Press F8 function key The wave window will zoom in around the area specified by the cursor Use step 2 above repeatedly until you can clearly see DCM test signals dcm_clk0_out and dcm_clkfx_out toggle iss Float tutorial_1 wefg ae File Edit View Simulation Window Help Zn x Lj tf OG wx bd Lv E i e 13 451 664 ps 3 450 000 ps 3 500 000 ps 3 550 000 ps 3600 000 ps 3 650 000 ps 3 700 000 ps 3 750 000 ps TEST BEMCH ck in user dcm reset period LI DAP Test Signals drp start drp change made drp current made drp dene drp stmach reset md fdrp_demo_tbfdrp_rmultiply 7 0 f 06 3 md fdrp_demo_tbfdrp_divide 0 LI DCM Test Signals dcm clkQ aut lis dcm lacked DM L Inputs L Outputs M Internal DRP CONTROLLER b TR Inputs pe X1 3 461 664 ps tutorial 1 wcfq Sim Time 126568 ns Figure 4 40 Wave Windo
10. associated with the currently highlighted design unit will appear in the Objects panel refer to Figure 4 20 You shall first add all input and output ports from the Inst_drp_dcm design unit instantiation onto the wave window Instance and Process Mame il drp demo tb ig uur i CLKFX BliFG INST i cLk BUFG INST il pcM ADV INST Cn 49 3 C 50 1 il Inst drp stmach Lf SYNC PROC CA NEXT STATE DECOE DCM RESET 133 136 139 o u Oe Gu Ge 4 37 Ca std logic 1154 Gal std_logic_arith Gal std_logic_unsigned i lili gt lt Instances and Processes Source Files ES Figure 4 19 Instances and Process Panel Objects 0 x Simulation Objects For Inst drp dem Object Mame value ih clkin_in daddr in LII ILLI dclk in den in LU di in UUW dwe in LU rst in Lu clkF out LU clkO_ouk U drdy out lacked aut clkfb in LU clkFx buf clkO_buF gnd bi Uu Figure 4 20 Simulation Objects Panel To add the input output ports of instance Inst dcm drp to the wave window either Highlight the Inst drp dcm design unit in the Instance and Process panel then right click on the input output ports in the Objects panel Select Add to Wave Configuration from the context menu Refer to Figure 4 21 34 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design ig UUT L clkin SG a li ij c Clase D
11. each other You will change the format of the following signals from their default color to a color of your choice e drp demo tb drp multiply e drp demo tb drp divide ISE Simulator ISim In Depth Tutorial www xilinx com 37 UG682 v1 0 April 27 2009 Examining the Design XILINX To change the color of a signal 1 Inthe wave window right click on the signal name listed under the Name column 2 Select Signal Color then pick a color from the color palette or a custom color by clicking on the ellipsis button Refer to Figure 4 27 Signal Color Reverse Bik Order Show Drivers SL Mew Group Blew Miia Figure 4 27 Changing the Signal Color Floating the Wave Window Depending on your screen resolution you may notice that the wave window has been populated with more signals than the screen can view at one time To alleviate this problem we can increase the viewable area by floating the wave window Following this step will open a new window with just the waveform contents To float a window either e While highlighting an object in the wave window select View gt Float e Click once on the Float Window main toolbar icon SAM Re T Float Window Figure 4 28 Selecting Float from the View Menu e Right click on the wave configuration name tab and select Float Pa Default wichg Close trl F4 Figure 4 29 Selecting Float from the Wave Configuration Name Tab You are done mak
12. followed by the simulation executable fuse_batch bat and simulate_isim bat 2 Once ISim starts load the wave configurations previously saved in Examining the Design tutorial 1 wcfg and tutorial_2 wcfg To load a wave window configuration Select File gt Open and point to the wave configuration files wcfg 3 Weare ready to simulate the design again with the updated test bench Re run the simulation by either Click the Run All toolbar icon d Use the menu command Simulation gt Run All P Type run all on the Tcl prompt ISE Simulator ISim In Depth Tutorial www xilinx com 53 UG682 v1 0 April 27 2009 54 Debugging the Design XILINX If the test vectors in the test bench were properly revised the simulation should run to completion showing that all tests passed Figure 4 52 Console at 12667500 ps Hate drop dena tbi DRP Cycle Tests Completed Summary i Test 1 PASS est 2 PASS Test 3 PASS Test 4 PASS Console Breakpoints Search Results Figure 4 52 Console Showing That All Tests Passed What s Next This completes the ISE Simulator ISim In Depth Tutorial Refer to the Additional Resources section in the Preface for more detailed information and discussion on the ISE Simulator www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009
13. list the sources based on their order of dependency fuse automatically resolves the order of dependencies and processes the files in the appropriate order Note You can browse to the completed folder of the tutorial files for a completed version of the project file for comparison purposes Building the Simulation Executable In this simulation step fuse will use the project file created in the previous section to parse compile and link all the sources for the design Following completion of these steps a simulation executable will be created which will allow you to run the simulation in the ISim GUI Using fuse The typical fuse syntax is as follows fuse incremental prj project file o simulation executable labrary top units where incremental requests fuse to compile only the files that have changed since the last compile prj specifies an Sim project file to use for input o specifies the name of the simulation executable output file e library top unit specifies the top design unit Complete the following steps to parse compile and elaborate the tutorial design using fuse 1 Browse to the folder scripts from the downloaded files 20 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX 4 5 Preparing the Simulation Open the batch file fuse batch bat using a text editor This fuse command is incomplete Using the syntax i
14. will need to add signals to the wave window so you can observe the signal status You will add all available simulation objects from the testbench to the wave window which include Input Clock clk in This is a 100 MHz clock generated by the test bench and will be the input clock into the Digital Clock Manager DCM Dynamic Reconfiguration Ports DRP drp These are signals associated with the DCM DRP feature The test bench asserts and monitors these signals to control and review the DCM DRP functionality DCM Output signals dcm These are output clocks from the DCM To add these signals to the wave window www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design 1 Right click on the drp demo tb instance unit in the Instances and Processes panel Refer to Figure 4 10 2 Select Add to Wave Configuration Instances and Processes e D x objects Simulation Object e Site d Instance and Process Name i Us l aia Ue EE ij LILIT Close Database 5 87 E i7 Collapse l 79 std logic 1164 Search RU std logic arith 39 std logic unsignec pum Go To Source Code fe Add To Wave Configuration Figure 4 10 Add to Wave Configuration All visible simulation objects from the drp_demo_tb test bench will now show up in the wave configuration Refer to Figure 4 11 I drp start drp change made ie drp current mode
15. 2 17 In this window you can set different simulation properties such as simulation runtime waveform database file location and whether you would like to use a customer simulation command file to launch the simulation 3 Forthe purposes of this tutorial we will disable the feature that runs the simulation for a specified amount of time right from the start of the simulation Uncheck the property Run for Specified Time and click OK Refer toFigure 2 17 E Process Properties Sim Properties Switch Mame Property Mame Use Custom Simulation Command File Custom Simulation Command File Run for Specified Time L Simulation Run Time 1000 ns waveform Database Filename CiPrajecks Tsim Tutarialdrp dema tb isim beh wdb d Specify Top Level Instance Names drp dema tb Property display level Standard Display switch names Default Figure 2 17 Sim Properties Window Launching Behavioral Simulation You are now ready to launch the ISE Simulator to perform a behavioral simulation of the tutorial design To launch the simulator double click on Simulate Behavioral Model The ISim Graphical User Interface GUI Figure 2 18 will appear shortly after the design is successfully parsed and compiled 14 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Simulating the Design 5 ISim Default wcfg a File Edit View Simulation Window H
16. Button Add Existing Source Files Look in sources do j ji dr p dem vhd i drp_demo vhd My Recent jdrp demo tb vhd Passe drp stmach vhd dr p tb pkg vhd Places 2 bly Network File name drp tb pkg vhd dip dem vhd drp demo Files of type Sources Ext vhd vhdl iv h vh sco sc v Cancel Figure 2 6 Add Existing Source Files 10 Remove the check boxes under the column Copy to Project so the source files are not copied into the project directory 11 Click Next to continue 8 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Simulating the Design ES New Project Wizard Add Existing Sources Adding existing sources is optional Additional sources can be added after the project is created using the Project Add Source or Project Add Copy of Source commands Add existing sources Source File Copy to Project Add Source SFOS PEC TO UST ECE UE TSC TO UST SCTE eT GOTO IE 1 drp tb pkg vhd z drp_dem vhd Remove 3 drp demo vhd 4 drp demo tb vhd 5 amp drp stmach vhd 6 Figure 2 7 Remove the Check Boxes 12 Review the Project Summary page and make sure that the settings match those shown in Figure 2 8 13 Click Next to continue ES New Project Wizard Project Summary Project Navigator will create a new project with the Following specifications Project Project Name I im Tutorial Project Pat
17. E Eutarial 1 wcfg Figure 4 42 Floating Ruler Feature Using Multiple Wave Configurations Depending on the resolution of the screen a single wave window may not display all the signals of interest at the same time You can resolve this problem by opening multiple wave windows each with their own set of signals and signal properties To open a new wave window e In ISim select File gt New In the resulting pop up window select Wave Configuration and click OK Figure 4 43 e Ablank wave configuration will be shown p Hew E Wave Configuration Figure 4 43 New Wave Configuration To move dividers groups and simulation objects to the new wave configuration 1 While pressing the Ctrl key highlight objects you want to move to the new wave window Right click on either of the selected signals and select Cut Enable the new wave configuration untitled 1 by clicking on its corresponding window tab 4 Right click in the Name column area of the wave configuration and select Paste 46 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design Use the instructions above to move all the simulation objects associated with the DCM and DRP Controller units to a new wave window dividers groups etc Upon completion of this task select File gt Save As to save this wave configuration as tutorial 2 wcfg You should now have two wave windo
18. HOL Figure 4 46 Integrated Text Editor Using Breakpoints and Stepping A breakpoint is a user determined stopping point in the source code used for debugging the design with ISim When simulating a design with set breakpoints simulation of the design stops at each breakpoint in order to verify the design behavior Once the simulation stops an indicator is shown in the text editor next to the line of source code where the breakpoint was set allowing you to compare the wave window results with a particular event in the source code Another useful ISim debugging tool is the Stepping feature With stepping you can run the simulator one simulation unit at the time This is helpful if you are interested in learning how each line of your source code affects the results in simulation We can use both of these debugging features to learn how the DRP cycle is performed during Test 2 in an attempt to debug the failing test Setting Breakpoints Begin by first setting a breakpoint around the first signal assignment performed during each of the DRP cycle tests ISE Simulator ISim In Depth Tutorial www xilinx com 49 UG682 v1 0 April 27 2009 Debugging the Design 50 XILINX To set a breakpoint 1 Open the source code which will contain the breakpoint 2 Go to an executable line in the source code which will contain the breakpoint 3 Adda breakpoint by either e Right clicking anywhere on the executable line and selecting To
19. ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LO
20. Note You can load the saved wave window configuration using the menu command File gt Open This feature is useful when you have se tup a wave configuration that you will reuse in future simulation sessions of the design You are ready to simulate the design again with the updated wave configuration Re run the simulation by either e UseRun All from the main toolbar e Use the menu command Simulation gt Run All e Type run all on the Tcl prompt The simulation will run for about 13 microseconds us After the simulation is complete use the menu toolbar icon to zoom to full view The wave configuration should look similar to iss Float tutarial 1 wcfg x ee File Edit View Simulation Window Help A5 x 1g Ed ez XP oo 3 FMEA JS x Eg f db yu il 10 000 000 ps F 5 is clk in o user dcm reset a ib period 10000 Fs C o DRP Test Signals r drp start j drp change mode E drp current made Hl drp dene drp stmach reset La mA idrp dema tb drp multiply 7 0 p EM drp demo tb drp divide 7 0 LI DCM Test Signals dem clka aut dem clkFx out les dcm lacked DM be L 1 Inputs gt B outputs L 1 Internal DRP CONTROLLER 3 L Tamka HE Eutarial 1 wcfg im Time 12667 ns Figure 4 32 Wave Configuration Using Markers The self checking test bench used in this design performs 4 different tests to showcase the functionality of the DCM Dynamic Reconfiguration feat
21. SS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners ISE ISim In Depth Tutorial www xilinx com UG682 v1 0 April 27 2009 Revision History The following table shows the revision history for this document Date 04 27 09 Version 1 0 Initial Xilinx release Revision UG682 v1 0 April 27 2009 www xilinx com ISE ISim In Depth Tutorial ISE ISim In Depth Tutorial www xilinx com UG682 v1 0 April 27 2009 Table of Contents Revision History S eo cuarto at a ata Acta ai d ay eul d ada a Bal i alai a i a ii Preface About This Tutorial About the ISE Simulator ISim In Depth Tutorial Luuee vii T tortial Contents 2 2 ooo poco seats eccerts asec DUO S APP rame pado ped tat vii Tu torial FIOWS IET vii Using ISim trom ISE Project Navigator inc ra are ae ae i i nt ies pn re ais TA vii Usine Dim S tandalgrie s tasare aan aes dab deco d da a la ela et n viii Additional Resources cce eee viii Chapter 1 Overview of the ISE Simulator ISim Overview of ISim ee RR rs Vhpb comp VICSCOMD recte im ed dote rea diaqpus Sina diac id barat aa e SUR IGG sora sia a eeu Ghee tee d nl ini
22. Summary 108 Properties Project File I5im Tutorial ise Im Hierarchy _ Module Level Utilization u drp demo l 3 8 ISim Tutorial 2 C Timing Constraints m 7 ISim_Tutorial Project Status Errors and Warnings O Synthesis Messages Fi Translation Messages Fi Map Messages _ Place and Route Messages eiline Default be O Timing Messages tegy unlocked drp_demo Behavioral be 7 Bitgen Messages Design Summary iReports amp All Current Messages Design Utilities Design Properties User Constraints eM Enable Enhanced Design Summary Synthesize XST H LL Display Incremental Messages dai i Implement Design Enable Message Filtering Synthesis Report Generate Programming File Optional Design Summary Contents Configure Target Device L Show Clock Report Update Bitstream with Processor Data Shaw Failing Constraints C Show warnings HN a i dle E xe5vix3n 3ff324 i N ia ros Clock Report a A Static Timing vic amp J fi Zu fn a Ke me H ad Place and Route Libraries E Design Summary Console CA x Launching Design Summary Report Viewer Console Errors Warnings Figure 2 10 SE Project Navigator Design Summary Next you need to create a user VHDL library for a VHDL package drp tb pkg vhd used by the test bench of this design The VHDL package contains VHDL functions used by the 10 ww
23. a ani ata Ba a sanatate Pad eri 8 aa da ai ta Simulation Executable as ivi dope Guan ex RES aa ia Se ei S tari la a 1 Il e iA ee or e dou A Ol A nt rte dn dat ee ee Chapter 2 Using ISE Simulator from ISE Project Navigator Overview of ISim ISE Integrated Flow 00 00 cece eee Geline Slanted P RRERE SOLU dle Be querela s n eausa adum dert e ti ui td ta tt o ate i a dea Installing the Tutorial Design Files ce Design Description uui eim ba ure ad e soia e i i dl de a ina aa 0 PUNCHOMAWIDIOCKS d eod dang od der ai aaa oa pi e ae ud Design 5elr Che eking Test Bench 2 455 529 sce trae me A oo aici a ne d de SUGAR dieas Simulating the D661 O01 5 ccs senectecers Id sal da n o d d opera ad a dn vita USE Creating a Project in ISE Project Navigator 0 0 cece cee eee Using New Project Wizarde s 62 0h6e055e 5444485 A npr AG PEERS 8 IR IA a ees Creaune VEIDE DIDEAUJ x23 esi eee pea bob ee oe ee eee d e dig da he gees es NMoving VHDL files toa bibrary 466224655546 rm eens Sea rera Launching a Behavioral Simulation 3 2a ounce opum 9 Da Sed e ai Setting Behavioral Simulation Properties cc Chapter 3 Running ISE Simulator ISim Standalone Overview of ISim Standalone Flow s e ASC tii e SUA E ee BO Wwale ReguIeIDells uas 96255457 n ae o bo tee See ca EEE A a Installing the Tutorial Design Files 0 00 ee eee
24. atabase ig c ij D Collapse CH is Search Ca NETT Configuration ig Inst Qs iza To Source Code Figure 4 21 Add to Wave Configuration e Select the input output ports of the Inst drp dcm design unit while holding the Ctrl key Then drag and drop the signals to the wave window e Enter the wave add Tcl command in the Sim Tcl prompt For example wave add drp dcm tb uut drp dcm Note By default all types of simulation objects variables constants etc are displayed in the Objects panel You can filter the type of simulation objects shown in this panel Use the Objects panel toolbar to filter by inputs outputs bi directional internal constants and variables Toggle the desired object type by clicking on the corresponding icon ad 1 WB 13 Figure 4 22 Inputs outputs bi directional internal constants and variables 3 Youcan move the recently added signals if they do not appear directly under the DCM divider While holding Ctrl Shift key click once on the first added DCM signal clk_in and the last added DCM signal gnd_bit Once all signals are selected move the signals under the DCM divider by holding the mouse button and placing the mouse cursor right under the divider name Repeat the steps above for input output ports of Inst_drp_statmach instantiated design unit Additionally you can also create groups for the signals recently added Using the instructions provided for adding groups define groups
25. clock to a different frequency The following table shows the desired output frequency and Multiplier Divider parameters used for each test Table 2 1 Desired Output Frequency and Multiplier Divider Parameters Used For Each Test Test Freq MHz Period ps Multiplier M Divider D 1 75 13 332 3 4 2 120 8 332 6 5 3 250 4000 5 2 4 400 2 500 4 1 e In each test the test bench will compare the expected clock period and the clock period measured during simulation Based on the comparison results messages to the simulator will be written indicating success or failure e Upon completion of the simulation a summary report is provided listing which tests passed or failed Note For more details on the functionality of this design refer to the in line comments included in the sources of the design Simulating the Design Thanks to an intuitive integrated flow you can easily and quickly perform behavioral and timing simulations of your design in the ISE Project Navigator software Using the integrated flow you can quickly set up simulation properties and launch the ISim software with a few clicks of the mouse We shall demonstrate how ISim can be launched using the ISE Project Navigator by first creating an ISE project for the tutorial design We will then set some behavioral simulation properties and launch the ISim simulator to perform a behavioral simulation of the design Creating a Project in ISE Proje
26. containing completed script simulation and wave configuration files as well as a completed ISE 11 project of the tutorial design for comparison purposes Design Description This tutorial provides a design which the reader can use to become familiar with performing some basic simulation steps while using the ISim software The tutorial design is a simple demonstration of the Dynamic Reconfiguration feature of the Virtex9 5 Digital Clock Manager DCM Using the Virtex 5 DCM the design generates an output clock using the following relationship Output Clock Input Clock Multiplier Divider Using the Dynamic Reconfiguration Ports DRP in the DCM the design allows the user to re define the Multiplier and Divider parameters to generate different output frequencies Functional Blocks The tutorial design consists of the following functional blocks 18 drp dcm drp dcm vhd Virtex 5 DCM macro with internal feedback frequency controlled output duty cycle correction and Dynamic Reconfiguration ability The CLKFX OUT output provides a clock that is defined by the following relationship CLKFX OUT CLKIN IN Multiplier Divider For example using a 100 MHz input clock setting the Multiplier factor to 6 and Divider factor to 5 produces a 120 MHz CLKFX OUT output clock Using the DRP ports of the DCM the Multiplier M and Divider D parameters can be dynamically redefined to produce different CLKFX OUT frequenc
27. ct Navigator We will use the New Project Wizard in ISE Project Navigator to quickly create an ISE project for the tutorial design Note Read Installing the Tutorial Design Files to obtain the files required for this design Using New Project Wizard Follow these steps to create an ISE project using the New Project Wizard 1 Launch the ISE Project Navigator by double clicking on the Xilinx ISE 11 desktop icon ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 www xilinx com 5 amp XILINX Simulating the Design ilins ISE 11 Figure 2 1 Xilinx ISE 11 2 Click the New Project button to launch the New Project Wizard 3 Provide a name and an appropriate location for the project Refer to Figure 2 2 4 Click Next to continue 23 New Project Wizard Create New Project Specify project location and type Enter a name locations and comment For the project Mame ISim Tutorial Location C Projects Sin_Tutorial m Description Select the type of top level source For Ehe project Top level source type HDL Figure 2 2 New Project Wizard 5 Inthe window select the device and project properties 6 Change the settings to match the settings shown inFigure 2 3 7 Click Next to continue www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Simulating the Design ES New Project Wizard Device Properties Spec
28. cts Far 9 Company Xilinx Inc Engineer Eddie Vergara BUFG vhd iE i DCM ADW vhd drp dem vhd Object Mame value drp dema hd lig ckfx edge cu 1066 drp demo tb vhd 15 clkFx_edge_pr 1066 drp_stmach vhd 2 drp tb pkg vhd hj test result TRUE numeric std vhd wS test vectors 1 prmtvs b vhd Lb Message null prmbvs p vhd std logic 1164 vhd std logic arith vhd std logic unsigned vhd textia hd timing b vhd timing p vhd unisim VCOIMP Fu unisim VPKG vhd Create Date 08 38 05 03 16 2009 Design Name DEP Demo Test Bench Module Name drp demo th Behavioral Project Name DRP Demo Target Devices xc5vlx3 Wool sEEEbVENRSE la gs al escription The DEP Demo Test Bench provides the system clock C DEP state machine start signals to change the output frequency based on provided Multiplier Divider value library IEEE use IEEE STD LOGIC 118642 A LL hull drp demo Eb vhd Instances an Sour go Console 04 x at 10371 ns Note rp demo FbiJ Test 4 START Set DCIM CLEFX OUT 400 MHz 2 5 ns via DRP Cycle M23 D 1 at 10665 ns 2 Note Jdrp demo Eb Test 4 Achieved DCM LOCK at 10668332 ps 3 Instance drp demo Eb Warning Test 4 END FAILURE CLKFX actual period does nat match expected Expected 2 5 ns Actual 3 332 ns Console Breakpoints Search Results Sim Time 12668 ns Ln 1 coli
29. drp_start r drp_change_mode drp currenk made gt drp_done lk drp stmach reset p EM dip demo tbjdrp multiply 7 0 j3 p EM drp_derna_thjdrp_divide 7 0 i E OCM Test Signals ies dem_clkO_out ies dcm clkFx out lli dem locked DOM P L 1 Inputs Ld L7 Outputs L 1 Internal Go To Time 10371ns v ZE Futarial 1 wcfg Using Cursors The ISim Console reports that Test 2 and Test 4 failed Figure 4 37 10000 Fs Figure 4 36 Wave Window Console DRP Cycle Tests Completed Summary Test 1 PA55 Test 2 FAIL Test 3 PASS Test 4 FAIL Console Breakpoinks Search Results a 7 GI P p too Se nl ki 10 p00 000 ps im Time 12667 ns Figure 4 37 Console Report Test 2 and Test 4 Failed In Test 2 and 4 a Dynamic Reconfiguration DRP write cycle is performed in order to change the multiply and divide factors of the Digital Frequency Synthesizer and set new clock output CLKFX frequencies 120 MHz and 400 MHz respectively However at the end of the DRP cycle the test bench measured a period that did not match the expected period Tests 2 and 4 fail due to the period discrepancy Figure 4 38 Figure 4 39 42 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Examining the Design Console Breakpoints Console at 3461664 ps Note drp demo tbs Test 2 START
30. e in the Console Indicating That the Simulator Has Stopped Stepping through Source Code You first need to verify that in Test 2 the appropriate Multiplier and Divider parameters are being set correctly via the drp_multiply and drp_divide bus signals You will use stepping to step through the source code line by line and review how the drp_multiply and drp_divide bus signals are assigned to the DCM DRP ports To step through a simulation either e Click on the Step Gz toolbar icon e Select Simulation gt Step e Type step in the Tcl prompt 1 Use the instructions above to step through the design As you step through the source code pay close attention to each of these events drp_multiply and drp divide bus signals are assigned values from a constant test vectors drp start asserts in order to start a DRP cycle drp multiply bus signal is assigned to the 8 uppermost bits of bus signal DI IN while drp divide bus signal is assigned to the 8 lowermost bits of the same bus ISE Simulator ISim In Depth Tutorial www xilinx com 51 UG682 v1 0 April 27 2009 Debugging the Design XILINX 52 The DRP controller drp stmach vhd leaves idle mode and moves to the next DRP cycle step clearing the DCM status registers In the tutorial 2 wave window expand the DCM Inputs bus Continue stepping through the simulation until the di in bus signal is updated with a new value you may need to zoom in considerab
31. e instructions above to make groups for the following signals 1 Allsignals in the drp demo tb design unit that start with drp Name the group DRP Test Signals 2 Allsignals in the drp demo tb design unit that start with dcm Name the group DCM Test Signals Expand all the created groups Your wave window should be similar to the one shown in Figure 4 17 clk_in ie user dcm reset W period i0000 fs b WM DFPTestSignals P Mh pcMTestsignals El Default wichg Figure 4 17 Wave Window Note f your signal groups do not match the figure shown above you can use the following techniques to fix them Ifyou included an unrelated signal you can cut it from the group and paste it into the main list Ifyou created the group but missed a signal in the main list simply drag and drop the signal into the group The signal will then be placed inside the group e You can undo the group by using the Edit gt Undo menu command www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design You can start over by ungrouping a group Right click on the group you wish to ungroup then select Ungroup Adding Dividers Soon you will be adding signals from other design units in order to better analyze the functionality of this design To better visualize which signals belong to which design units we can add dividers to separate the signals by design unit
32. e windows so they can be reviewed at the same time 2 Restart the simulation by pressing the Restart icon in the ISim menu toolbar 3 Runthe simulation by pressing the Run All toolbar icon www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Debugging the Design The simulation runs near the start of the first test Focus changes to the text editor while it shows with a yellow indicator Ly the last line of source code the simulator executed 183 i ES lw ial ee ei sual iD cbxwcuEdesE tii IL ale 154 185 drp multiply lt conv std logic vectori t 156 drp divide lt conv std logic vectori tee A 2 Figure 4 49 Yellow Indicator Shows the Last Line of Source Code the Simulator Executed Additionally a message will appear in the Console indicating that the simulator has stopped including the line of source code last executed by the simulator 4 We know Test 1 finishes successfully when we ex ned the design earlier As such we can skip debugging this test Press the Run All toolbar icon to continue forward to Test 2 The simulation now stops at the start of Test 2 Console at 3461664 ps Mate ridrp demo tb Test 2 START Set DCM CLEFX OUT 120 MHz 8 332 ns via DRP Cycle M 7 D 5 Stopped at time 3461664 P5 File rkohlerledv work prajecks designs simulatian T5im in I 5im Console _ Breakpoints Search Results Figure 4 50 Messag
33. ects sources drp_dermo vhd Ha CiProjects sources drp_demo_th vhd Ha CiProjects sources drp_stmach vhd Design Files Libraries Figure 2 15 Source Libraries Launching a Behavioral Simulation Now that the ISE project has been created for the tutorial design we can proceed to setup and launch a behavioral simulation using ISim Setting Behavioral Simulation Properties Follow these steps to set behavioral simulation properties in ISE 1 Inthe Sources for drop down menu select Behavioral Simulation Highlight the tutorial design test bench drp_demo_tb by clicking the file name You should now see the simulation processes available for the design in the Processes pane Refer to Figure 2 16 ISE Simulator ISim In Depth Tutorial www xilinx com 13 UG682 v1 0 April 27 2009 Simulating the Design XILINX Design eps df Sources For Behavioral Simulation vi JE Hierarchy rSim Tutorial B EA xcovix3 3fF324 A aa drp_dema_tb behavioral 0 Projects sou UUT drp demo Behavioral C Praje m Inst drp dcm drp dcm BEHAVTO m Inst drp stmach drp stmach Be Processes drp demo tb behavioral HE 15im Simulator Behavioral Check Syntax Simulate Behavioral Model Ae AA OB m Design Files Libraries Figure 2 16 Process Pane 2 Right click on Simulate Behavioral Model under the Sim Simulator process and click on Properties The ISim Properties window comes up Refer toFigure
34. eee De sign Description 225299 ara aa ni po Daia Ead diria aia il sp na PUMCHOMAWDIOCKS m ac ate e sa dd 1 ao es at i e ai i la EE EENEN Design Selle Check Test Bench uua pice at e ae at dt a di s ar addu ca i atit aci ISE Simulator ISim In Depth Tutorial www xilinx com UG682 v1 0 April 27 2009 XILINX Preparing the Simulation 19 Creatine an oun Project File osos cs priu rdg aU dO PEU a patios ario apr ali 20 d 19 Building the Simulation Executable 0 ee eee eee 20 lcs C ea es aed oad Ge baa es eh ee ee eee eee eos 20 Simulating te ESIC ceisia renie irae aice tone ma mene a d eu NE dena 21 Running the Simulation Executable 4 4 45 exe RR sete ese trate na a 21 Chapter 4 Using ISE Simulator ISim Graphical User Interface Overview of Sim Graphical User Interface 0 00 0008 23 Exploring the User Iinlerlaces oce ora hou de socat dacii det bb ead E d Ed ows acea 24 Mail 1OGI Dat sera esa one ia ag eee ed c2Ooeenee antes eae A ee ores pee bes 24 Instances and Processes Panel 2 cee eee te eee eee eens 24 Source EI e N Sel e avatare clan a seed foe dm im dm a i das EENE EEE PEET 25 ORCS RANE M 25 Weave VWIN0OW ae css ceai aa a NEETER EER e i s 26 DEX BCLILOIE MD 27 Break DON e vi e ae ia ma eee ee Gaus oho ys Aa al Pee EM d 27 GO AI ae bans sa e i i dt aula Ben at t nt Ri e ae ea EEE a ai E ee ia 28 Examining the DESI 7
35. eles a i d pd 9 3 dea 49 Stepping through Source Code a ce a see Fei I 2o ae e n ne i ote hoes eae 51 Fixing Dup sante Design ona santa eg eer ORO a Sti mq Ea qq S ed RECIPE IE qES 53 Vening DUE TIX ra vortex ipta pert B Oran Aidan Adi mandi tae papi Moon Aaa a d 53 lads RE ci d alai 54 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Preface About This Tutorial About the ISE Simulator ISim In Depth Tutorial The ISim In Depth Tutorial provides Xilinx PLD designers with a detailed introduction of the ISE Simulator ISim software After you have completed the tutorial you will have a thorough understanding of how to analyze and debug your design via HDL simulation using ISim Note This tutorial is designed for running the ISim software on a Windows environment Some modifications may be required to run certain steps successfully in other operating systems Tutorial Contents This tutorial covers the following topics Chapter 1 Overview of the ISE Simulator ISim introduces the ISim software environment including the ISim compilers linker simulation executable and Graphical User Interface Chapter 2 Using ISE Simulator from ISE Project Navigator explains how to launch a functional simulation through the ISE Project Navigator software Chapter 3 Running ISE Simulator ISim Standalone guides you through a typical procedure for
36. elp ax OPA XX 9a MI ZANA Instances and Processes 0 amp X Objects O Fx p Simulation Objects for drp_demo_tb Mielac me a c Snes se ihana UD Ga Instance and Process Name En E zI 2 E 2 iJ drp demo tb Object Name Value W std logic 1164 US ck in 0 Jl std logic arith US drp start 5 std logic unsigned US drp change 0 Jg textio e drp_current_ 0 Jy drp tb pkg u drp done U Jg numeric std Ag drp stmach r O 3 vital timing Ue user dcm reset 0 19 vital primitives 23 drp multiply 00000000 5 vcomponents 2 drp divide ooooo000 2 vpkg La dcm clk out U o dcm clkfx out U La dcm locked u LB period 10000 ps 2 Instances and Processes Source Files gt Default wefg Console O x This is a Full version of ISim Time resolution is 1 ps ISim Console Breakpoints Search Results Sim Time Ons Figure 2 18 ISim GUI What s Next Continue on to Chapter 4 Using ISE Simulator ISim Graphical User Interface to learn more about the ISim GUI features and tools for analyzing and debugging HDL designs ISE Simulator ISim In Depth Tutorial www xilinx com 15 UG682 v1 0 April 27 2009 Simulating the Design XILINX 16 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Chapter 3 Running ISE Simulator ISim Standalone Overview of ISim Standalone Flow ISim offers a standalone flow which you can use to simulate your design without
37. ew signals in the wave window utilize ISim commands to run simulation examine the design and debug as necessary 5 ISim Default wcfg a File Edit View Simulation Window Help 8 X Dee amp B XA Oa A PANG SH PPKP R 1 1 OO gt p 1 00us v Gs Il Instances and Processes 0 amp X Objects O Gx p c Simulation Objects For drp demo tb 2 a SS G Bl BIG WR m t Bh Pun Instance and Process Name E E E ER A i drp demo tb Object Name Value P D std logic 1164 US dk in 0 79i std logic arith US drp start 0 5 std logic unsigned Ug drpchange 0 2 Jg textio b drp current 0 Jg drp_tb_pkg e drp_done U N Jg numeric std Lg drp_stmach_r O il vital Eiming Us user dcm reset 0 Ud 19 vital primitives 23 drp multiply 00000000 9 vcomponents drp_divide 00000000 LH vpkg dcm clkO out fi Ug dcm clkfx out U La dcm locked u LS period 10000 ps lt gt Instances and Processes Source Files lt gt Default wefg Console O Gx This is a Full version of ISirn Time resolution is 1 ps ISim gt Console Breakpoints Search Results Sim Time 0 ns Figure 4 1 ISim GUI ISE Simulator ISim In Depth Tutorial www xilinx com 23 UG682 v1 0 April 27 2009 Overview of ISim Graphical User Interface XILINX 24 XILINX Exploring the User Interface Main Toolbar OPER si XBOX oa MERA PR PARA es da 0 Flos vi I a Figure 4 2 Main Toolbar The toolbars a
38. fuse will use to create a simulation executable Following completion of this step the ISim Graphical User Interface GUI can be launched by running the simulation executable Creating an ISim Project File ISE Simulator ISim In Depth Tutorial The typical syntax for an ISim project file is as follows UG682 v1 0 April 27 2009 www xilinx com 19 Preparing the Simulation XILINX verilog vhdl library name lt file name 1 v vhd where e veriloglvhdl indicates that the source is a Verilog or VHDL file Include either verilog or vhdl e library name indicates the library that a particular source on the given line should be compiled work is the default library e lt file name is the source file or files associated with the library Note While more than one Verilog source file can be specified on a given line only one VHDL source can be specified on a given line Complete the following steps to build an ISim project file for the tutorial design 1 Browse to the folder scripts from the downloaded files Open the project file simulate isim prj with a text editor 2 The project file is incomplete List the missing sources using the syntax guidelines shown above Missing sources drp dcm vhd VHDL source file It should be compiled to work library drp tb pkg vhd VHDL package file It should be compiled to drp tb lib library 3 Save and close the file Note You need not
39. ggle Breakpoint Highlighting the line by performing a left click on the line number then using the menu command View Breakpoint Toggle Breakpoint Clicking the text editor toolbar breakpoint icon Use the instructions above to set a breakpoint at line 185 in drp_demo_tb vhd see Figure 4 47 Doing so will cause the simulator to stop every time the signal drp_multiply is assigned a value cm LL 5 183 1 Set Multiplier and Divider values A 154 185 drp multiply lt com std logic wector t 35 186 drp divide lt conv std logic vectori tes e Figure 4 47 Setting a Breakpoint at Line 185 in drp demo tb vhd Note You can manage breakpoints by clicking on the Breakpoints tab next to the Console tab All set breakpoints will appear in this list From here you can Delete selected breakpoint Delete all breakpoints Go to the line of source code for selected breakpoint Breakpoints X 4 Fy e nM X Delete Del 4 Delete All Breakpoints BES So To Source Code Console Breakpoints Figure 4 48 Breakpoints Tab Re run the simulation with the breakpoint enabled by following these steps 1 Bring to focus the ISim main window Note Debugging with the breakpoints and stepping feature works best when you are able to review the console output and the wave windows at the same time Use the float feature of the ISim panels or resize the windows of the simulator to best accommodate th
40. h C Projects IS5im Tutorial Working Directory Description Top Level Source Type HDL Device Device Family Virtexs Device xciwvlx3 Package ff324 Speed 3 Synthesis Tool XST VHDL Verilocdg Simulator ISim VHDL Verilog Preferred Language VHDL Manual Compile Order false Enhanced Design Summary enabled Message Filtering disabled Display Incremental Messages disabled Figure 2 8 Project Summary 14 In the next window make sure that the association and libraries have been properly specified for the tutorial sources Compare your settings with the settings shown inFigure 2 9 ISE Simulator ISim In Depth Tutorial www xilinx com 9 UG682 v1 0 April 27 2009 Simulating the Design XILINX 15 Click OK to finalize the New Project Wizard and start using ISE with the tutorial design files ise Adding Source Files The Following allows you to see the status of the source Files being added to Ehe project and allows vou to specify the Design view association For sources which are successfully added to the project File Marne Association Library e drp demo vhd dro demo tb vhd Q drp_stmach vhd dro tb pha vhd Figure 2 9 Status of Source Files and Associations zu ISE Project Navigator C YProjectsiSim_TutoriallSim_Tutorial xise Design summary 1 Ji x x X File Edit View Project Source Process Tools Window Help zx Nel Dee ay oy Be Design Overview 0 0 E
41. his is a Full version of ISim Time resolution is 1 ps ISim run all Console Breakpoints Search Results Figure 4 9 Console Panel The Console panel enables you to view a log of messages generated by ISim and to enter Tcl standard and ISim specific commands at the command prompt Examining the Design In this section you will perform several steps to further analyze the functional behavior of the tutorial design These include 28 Running and restarting the simulation to review the design functionality using signals in the wave window and messages from the test bench shown in the Console Panel Adding signals from the test bench and other design units to the wave window so their status can be monitored Adding groups and dividers in order to better identify signals in the wave window Changing signal and wave window properties to better interpret and review the signals in the wave window Using markers and cursors to highlight key events in the simulation and to perform zoom and time measurement features Using multiple wave window configurations to further enhance your ability of reviewing multiple signals in one simulation session Adding Signals Note Skip this step if you completed the Running ISE Simulator ISim from the ISE Project Navigator AII visible simulation objects from the test bench should have been automatically added to the wave window Prior to running for a specified time in the simulator you
42. ies For the purposes of this tutorial it suffices to show how the Multiply and Divide parameters are provided to the DCM via the 16 bit wide DI IN port DI IN 15 8 2M 1 DI IN 7 0 D 1 For example for an M D factor of 6 5 DI IN 0504h drp_stmach drp stmach vhd This module describes a Dynamic Reconfiguration Controller The DRP controller asserts and monitors the DCM DRP signals in order to perform a dynamic reconfiguration cycle A dynamic reconfiguration cycle is started by asserting the drp start signal Following this step the DRP Controller asserts the appropriate DCM DRP pins in order to complete a full Dynamic Reconfiguration cycle Signal drp done indicates a successful completion of a dynamic reconfiguration cycle drp demo drp demo vhd www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Preparing the Simulation This is the top module of the tutorial design which connects the DCM macro and the DRP controller modules to the external I O ports drp demo tb drp demo tb vhd Self checking HDL test bench Refer to Design Self Checking Test Bench for more information Design Self Check Test Bench To test the functionality of this design a self checking test bench has been provided Refer to source file drp demo tb vhd in the sources folder A selt checking test bench contains a validation routine or function that compares sampled values from the simulatio
43. ify device and project properties Select the device and design Flow Far the project Property Mame Product Category Family Device IEI Package Speed Top Level Source Type Synthesis Tool amp 5T VHDL Verilog Simulator ISim VHDL Verilog Preferred Language Manual Compile Order Enable Enhanced Design Summary Enable Message Filtering m pi F lt M M nnanaaaa Display Incremental Messages Figure 2 3 Change the Settings 8 Click Next in the next window No new sources will be created for the tutorial design ES New Project Wizard Create New Source You may optionally create one source at this time You can add existing sources on the next page and later create additional sources with the Project gt New Source command Create a new source Source File 2 Remove Figure 2 4 Add Sources 9 Inthe next window point to the sources for the tutorial design Click the Add Source button to select the sources provided for the tutorial design ISE Simulator ISim In Depth Tutorial www xilinx com 7 UG682 v1 0 April 27 2009 Simulating the Design XILINX E New Project Wizard x Add Existing Sources Adding existing sources is optional Additional sources can be added after the project is created using the Project Add Source or Project Add Copy of Source commands Add existing sources Source File Copy to Project Add Source Remove Figure 2 5 Add Source
44. ing VHDL files to a Library Follow these steps to move the VHDL package file to the drp tb lib VHDL library 1 In the Sources Pane select the Libraries tab to switch to the Libraries Pane Refer to Figure 2 13 Libraries 0 x E Source Libraries M drp tb lib EI 4 verilog Ha CiProjects sources drp_dem vhd Ha CiProjects sources drp_denma vhd m CiPrajecksNsaurcesidrp dema Eb vhd Ha CiProjects sources drp_stmach vhd Ha CiProjects sources drp_tb_pkg vhd Design Files Libraries Figure 2 13 Select the Libraries Tab 2 Expand the work library by clicking once on the hierarchy separator Refer to Figure 2 13 Right click on the VHDL file drp tb pkg vhd and select Move to Library In the Move to Library dialog box select drp tb lib as the library into which you will move the VHDL package drp tb pkg vhd file 5 Click OK Refer to Figure 2 14 12 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Simulating the Design HE ES Move to Library Move Ehe Following Files CiProjects sources drp_tb_pkg vhd To which library drp tb lib Figure 2 14 Move to Library Window You can now observe that a new VHDL library drp tb lib contains a VHDL package file drp tb pkg vhd Refer to Figure 2 15 Libraries 08 x gt Source Libraries A drp tb lib CiProjects sources drp_tb_pkg vhd verilog d work Ha CAProjects sources drp_dem vhd Ha CProj
45. ing modifications to the wave window The wave window should now look similar to Figure 4 30 Test bench groups are expanded 38 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design z 000 O00 ps amp 000 O00 ps TEST BEMCH clk_in user dcm reset period LER DRF Test Signals drp start drp change made lk drp current made drp done drp stmach reset p EM idrp demo tbidrp multiply 7 0 i Dn d nz jdrp demo tbjdrp divide 7 0 i Dn LIA OCM Test Signals k derm_clkO_out lk dcm clkFx aut Ys dcm locked DCM L 1 Inputs P L 1 Outputs L 1 Internal DRP CONTROLLER in EI Eg Default wicg Figure 4 30 Wave Window Saving the Wave Window Configuration You can save the current state of the wave window wave configuration so it is available for use in future ISim simulation sessions of your design To save the wave configuration 1 Use File gt Save As to assign a name to the current wave configuration Refer to Figure 4 31 Edit View Sirmulatii L New Cr A e Open Ctrl g 3 Close P Y H Save Ctrl 5 Figure 4 31 Saving the Wave Window Configuration 2 Save the current wave configuration as tutorial 1 wcfg The wave configuration is now saved for future use ISE Simulator ISim In Depth Tutorial www xilinx com 39 UG682 v1 0 April 27 2009 Examining the Design XILINX
46. launching a functional simulation using the Sim compiler linker and simulation executable outside of the ISE Project Navigator environment Chapter 4 Using ISE Simulator ISim Graphical User Interface introduces you to the ISim GUI by examining debugging and verifying a functional simulation Tutorial Flows This tutorial presents two flows in which ISim can be used for performing a functional Behavioral simulation e Using ISim from ISE Project Navigator e Using ISim Standalone Using lSim from ISE Project Navigator In this flow you will launch ISim via one of the simulation processes available in the ISE Project Navigator This flow works best when an ISE Project Navigator project is created in order to implement the design in a Xilinx FPGA or CPLD This flow is useful when your design involves sources that are not HDL schematics cores etc and requires Project Navigator to properly convert these sources to HDL source files which ISim can compile ISE Simulator ISim In Depth Tutorial www xilinx com vii UG682 v1 0 April 27 2009 Additional Resources XILINX Follow these chapters if you are interested in this flow e Chapter 1 Overview of the ISE Simulator ISim e Chapter 2 Using ISE Simulator from ISE Project Navigator e Chapter 4 Using ISE Simulator ISim Graphical User Interface Using ISim Standalone In this mode you will primarily simulate your design by creating your own ISim p
47. ly in order to observe the change At around 3 465 ns the bus should be updated from 0203h to 0604h Note Change the radix of bus signal di in to Hexadecimal to verify this value change a Float tutorial 2 vwcfg a File Edit View Simulation Window Help DPR SIX BBX Oe MEBAMNS ew PE F L Inputs 3 465 O00 ps Lg clkin_in b daddr_in 6 0 L liga dclk in I den in 890 a di_in 15 0 I dwe in Dea G4 T ELE Liga rst in Figure 4 51 Expanding the DCM Inputs Bus in the Tutorial 2 Wave Window 4 The output clock frequency of this design dcm clkfx out is dependent on the multiply and divide factors provided by the user For Test 2 we use the following parameters and expected output clock frequency Table 4 1 Parameters and Expected Output Clock Frequency Test Freq MHz Period ps Multiplier M Divider D 2 120 8 332 6 5 You may recall that for M 6 and D 5 di in 15 0 bus value should be 0504h Notice that the status of di in in Test 2 is 0604h Test 2 fails because an incorrect M D factor is provided via the drp multiply and drp divide signals in the test bench 5 You can repeat the steps above to determine the cause of failure for Test 4 You will determine that the failure is also due to incorrect assignments of the multiply and divide signals in the test bench www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27
48. m is a Hardware Description Language HDL simulator that enables you to perform functional and timing simulations for VHDL Verilog and mixed language designs This ISE Simulator environment is comprised of the following key elements e Vhpcomp VHDL compiler e Vlogcomp Verilog compiler e fuse HDL elaborator and linker e Simulation Executable e isimgui ISim Graphical User Interface vhpcomp vlogcomp vhpcomp and vlogcomp parse and compile VHDL and Verilog source files respectively The object code generated by the compilers is used by HDL linker fuse to create a simulation executable fuse The fuse command is the Hardware Description Language HDL elaborator and linker used by ISim fuse effects static elaboration on the design given the top design units and then compiles the design units to object code The design unit object files are then linked together to create a simulation executable fuse can link design units compiled previously with vhpcomp or vlogcomp Alternatively fuse can automatically invoke vlogcomp and vhpcomp for each VHDL or Verilog source code listed in a project file prj This method allows for compilation of sources on the fly Simulation Executable The Simulation Executable is generated by the fuse command To run the simulation of a design in ISim the generated simulation executable needs to be invoked When ISim is run inside the ISE Project Navigator interface ISE takes care of invoki
49. m COMP vhd unisim VPKG vhd Instances and Pracesses Source Files pasa ee a m Figure 4 4 Sources Files Panel The Source Files panel displays the list of all the files associated with the design The list of files is provided by the fuse command during design parsing and elaboration which is run in the background for GUI users The HDL source files are available for quick access to the read only source code Objects Panel Objects 0 xX Simulation Objects For drp_demo_tb Object Name E clk_in b drp stark b drp change b drp current Mo drp_done lo drp stmach r user dcm reset DODODODD oooo0000 b dcm clk out LU lo dcm clkFx out U 1 dcm lacked Uu 1B period 10000 ps Figure 4 5 Objects Panel The Objects panel displays all ports and signals associated with the selected instances and processes in the Instances and Processes panel At the top of the panel the Simulation Objects displays which instance process is selected in the Instances and Processes panel whose objects and their values are listed in the Objects panel The table columns are defined as follows e Object Name Displays the name of the signal accompanied by the symbol which represents the type of object it is ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 www xilinx com 25 Overview of ISim Graphical User Interface XILINX e Value The value of the signals at the current simula
50. n against expected results Preparing the Simulation The self checking test bench provided for this design performs the following functions Generates a 100 MHz input clock for the design system clock clk in Performs four different tests in order to dynamically change the output frequency of the design In each test a DRP cycle is started using the drp start signal to set the output clock to a different frequency The following table shows the desired output frequency and Multiplier Divider parameters used for each test Table 3 1 Desired Output Frequency and Multiplier Divider Parameters Used For Each Test Test Freq MHz Period ps Multiplier M Divider D 1 75 13 332 3 4 2 120 8 332 6 5 3 250 4000 5 2 4 400 2 500 4 1 e In each test the test bench will compare the expected clock period and the clock period measured during simulation Based on the comparison results messages to the simulator will be written indicating success or failure e Upon completion of the simulation a summary report is provided listing which tests passed or failed Note For more details on the functionality of this design refer to the in line comments included in the sources of the design ISim offers a standalone flow which you can use to simulate your design without setting up a project in ISE Project Navigator In contrast to the ISE Integrated Flow you will manually create an ISim project file which
51. nformation provided above edit the command line so it includes the following options a Useincremental compilation b Usesimulate isim prj as the project file c Usesimulate isim exe as the simulation executable d Use work drp demo tb as the top design unit for simulation Save and close the batch file Double click on the fuse batch bat file to run fuse Once fuse completes compiling source code elaborating design units and linking the object code a simulation executable simulate isim exe should be present in the scripts folder Note You can browse to the completed folder for a completed version of the fuse batch file for comparison purposes Simulating the Design In this simulation step you will launch the ISim Graphical User Interface by running the simulation executable which was generated by the fuse tool in the previous section Building the Simulation Executable After this step is complete you will be able to use the ISim GUI to explore the design in more detail Running the Simulation Executable The typical syntax used when launching the simulation executable is as follows Simulation executable gui wcfg wave configuration file wdb waveform database file where gui launches Sim in Graphical User Interface mode wcfg specifies the Wave Configuration file for setting up the waveform wdb specifies the file name of the simulation database output file Default simulation execu
52. ng the generated simulation executable A command line user needs to explicitly invoke the generated simulation executable to effect simulation The simulation executable effects event driven simulation and has rich support for driving and probing simulation using Tcl ISE Simulator ISim In Depth Tutorial www xilinx com 1 UG682 v1 0 April 27 2009 Overview of ISim XILINX Note The ISE Simulation Executable has a exe extension in both Linux and Windows The default executable naming format is x exe isimgui exe isimgui exe isimgui on Linux is the ISim Graphical User Interface It contains the wave window toolbars panels and the status bar In the main window you can view the simulation visible parts of the design add and view signals in the wave window utilize ISim commands to run simulation examine the design and debug as necessary 2 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Chapter 2 Using ISE Simulator from ISE Project Navigator Overview of ISim ISE Integrated Flow The Xilinx ISE software provides an integrated flow with the Xilinx ISE Simulator ISim that allows simulations to be launched directly from the Xilinx Project Navigator ISE All simulation commands that prepare the ISim simulation are generated by ISE Project Navigator and automatically run in the background when simulating a design using this flow Getting Started ooftware Requi
53. nitors the DCM DRP signals in order to perform a dynamic reconfiguration cycle A dynamic reconfiguration cycle is started by asserting the drp start signal Following this step the DRP Controller asserts the appropriate DCM DRP pins in order to complete a full Dynamic Reconfiguration cycle Signal drp done indicates a successful completion of a dynamic reconfiguration cycle drp demo drp demo vhd This is the top module of the tutorial design which connects the DCM macro and the DRP controller modules to the external I O ports drp demo tb drp demo tb vhd Self checking HDL test bench Refer to Design Self Checking Test Bench for more information www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Simulating the Design Design Self Checking Test Bench To test the functionality of this design a self checking test bench has been provided Refer to source file drp demo tb vhd in the sources folder A self checking test bench contains a validation routine or function that compares sampled values from the simulation against expected results The self checking test bench provided for this design performs the following functions e Generates a 100 MHz input clock for the design system clock clk in e Performs four different tests in order to dynamically change the output frequency of the design In each test a DRP cycle is started using the drp start signal to set the output
54. onstration of the Dynamic Reconfiguration feature of the Virtex 5 Digital Clock Manager DCM Using the Virtex 5 DCM the design generates an output clock using the following relationship Output Clock Input Clock Multiplier Divider Using the Dynamic Reconfiguration Ports DRP in the DCM the design allows the user to re define the Multiplier and Divider parameters to generate different output frequencies Functional Blocks The tutorial design consists of the following functional blocks drp dcm drp dcm vhd Virtex 5 DCM macro with internal feedback frequency controlled output duty cycle correction and Dynamic Reconfiguration ability The CLKFX OUT output provides a clock that is defined by the following relationship CLKFX OUT CLKIN IN Multiplier Divider For example using a 100 MHz input clock setting the Multiplier factor to 6 and Divider factor to 5 produces a 120 MHz CLKFX OUT output clock Using the DRP ports of the DCM the Multiplier M and Divider D parameters can be dynamically redefined to produce different CLKFX OUT frequencies For the purposes of this tutorial it suffices to show how the Multiply and Divide parameters are provided to the DCM via the 16 bit wide DI IN port DI IN 15 8 2M 1 DI IN 7 0 D 1 For example for an M D factor of 6 5 DI IN 0504h drp_stmach drp stmach vhd This module describes a Dynamic Reconfiguration Controller The DRP controller asserts and mo
55. rements To use this tutorial you must install the following software 1 ISE WebPACK 11 or 2 Oneofthe ISE Design Suite 11 Editions Logic DSP Embedded System For more information about installing Xilinx software see the SE Release Notes and Installation Guide at http www xilinx com support software_manuals htm Installing the Tutorial Design Files Design files for this tutorial can be downloaded from http www xilinx com support techsup tutorials tutorials11 htm After you have downloaded the tutorial project files from the Web unzip them into an easily accessible directory with full read and write permissions The contents of the tutorial project files are as follows e sources Folder containing all the HDL files necessary for a functional simulation of the design e scripts Folder containing incomplete script files to run the simulation These script files will be completed as you go through the tutorial e completed Folder containing completed script simulation and wave configuration files as well as a completed ISE 11 project of the tutorial design for comparison purposes ISE Simulator ISim In Depth Tutorial www xilinx com 3 UG682 v1 0 April 27 2009 Design Description XILINX Design Description The ISim In Depth Tutorial provides a design which the reader can use to become familiar performing some basic simulation steps while using the ISim software The tutorial design is a simple dem
56. roject files and running the HDL linker and simulation executable in a command line or batch file mode This flow is useful for users not using Project Navigator to manage their HDL design The following chapters will help you understand this flow e Chapter 1 Overview of the ISE Simulator ISim e Chapter 3 Running ISE Simulator ISim Standalone e Chapter 4 Using ISE Simulator ISim Graphical User Interface Additional Resources viii To find more detailed information and discussions on ISE Simulator ISim topics covered in this tutorial refer to the following documents e Sim Help is available from the ISim software e Sim User Guide accessible from the Software Manuals page on the Xilinx website http www xilinx com support documentation sw manuals xilinx11 plugin ism pdf e Software Manuals To find additional documentation see the Xilinx website at http www xilinx com literature To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support To discuss topics of interest with other Xilinx users see the Xilinx User Community Forum at http forums xilinx com xXInx www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Chapter 1 Overview of the ISE Simulator ISim Overview of ISim The Xilinx ISE Simulator ISi
57. se IEEE SID LOGIC UNSIGNED ALL 20 21 entity drp demo is ia je 23 lock and Reset ad clk in in STD LOGIC 25 drp stmach reset in STD LOGIC 26 user dcm reset in STD LOGIC 27 28 DRP User Interface 70 drn start in Tn E he Il gt Default wicfg drp demo vhd Figure 4 7 Text Editor The text editor window is available for easy access to the HDL source files used in the simulation Basic steps available are e Opening HDL source files read mode only e Viewing HDL source files e Setting breakpoints to source files for debugging e Step through the source code using stepping Breakpoints Panel Breakpoints x T CiPrajeckts saurces drp dema Eb vhd 181 Console Breakpoints Search Results Figure 4 8 Breakpoints Panel The Breakpoints panel displays a list of all breakpoints currently set in the design For each breakpoint set in your source files the list in the breakpoints panel identifies the file location file name and line number You can delete a selection delete all breakpoints and go to the source code from the Breakpoint panel toolbar icons or context menu For more information see Chapter 4 Debugging the Design in the ISim User Guide http www xilinx com support documentation sw_manuals xilinx11 plugin_ism pdf ISE Simulator ISim In Depth Tutorial www xilinx com 27 UG682 v1 0 April 27 2009 Examining the Design XILINX Console Panel Console T
58. setting up a project in ISE Project Navigator In this flow you 1 Prepare the simulation project by manually creating an Sim project file in order to create a simulation executable using fuse 2 Start the ISim Graphical User Interface by running the simulation executable generated by fuse Getting Started ooftware Requirements To use this tutorial you must install one of the following software e ISEWebPACK M 11 or e One of the ISE Design Suite 11 Editions Logic DSP Embedded System For more information about installing Xilinx software see the SE Design Suite 11 Installation Licensing and Release Notes http www xilinx com support sw_manuals xilinx 11 irn pdf Installing the Tutorial Design Files Design files for this tutorial can be downloaded from http www xilinx com support techsup tutorials tutorials 11 htm After you have downloaded the tutorial project files from the Web unzip them into an easily accessible directory with full read and write permissions The contents of the tutorial project files are as follows e sources Folder containing all the HDL files necessary for a functional simulation of the design e scripts Folder containing incomplete script files to run the simulation These script files will be completed as you go through the tutorial ISE Simulator ISim In Depth Tutorial www xilinx com 17 UG682 v1 0 April 27 2009 Design Description XILINX completed Folder
59. t e Type restart in the Tcl prompt The wave window should look like the one shown in Figure 4 16 2 000 000 ps ck in lk drp start lk drp change made li drp current made lk drp dene lk drp stmach reset W user dcm reset E drp divide 7 0 lk dcm clkQ aut lk dcm clkFx out Default wicfg Figure 4 16 Wave Window ISE Simulator ISim In Depth Tutorial www xilinx com 31 UG682 v1 0 April 27 2009 Examining the Design 32 XILINX Adding Groups In the next steps you will be adding signals from other design units in order to better analyze the functionality of this design However soon after you add additional signals to the wave window the size of the wave window will not be large enough to display all signals in the same view Reviewing all signals would require the use of the vertical scroll bar in the wave window repeatedly making the review process rather tedious We can remedy this situation by collecting signals into a group With a group you can collectively show or hide signals of similar purpose To group signals in the wave configuration 1 While holding down the Ctrl key select signals on the wave window of similar purpose Right click on either of the selected signals Select New Group Enter a name for the group i e DRP Test Signals A collapsed group will be created in the wave window To expand the group click once to the left of the group name Use th
60. table name is x exe Complete the following steps to launch the simulation ll 2 Browse to the folder scripts from the downloaded files Open the batch file simulate isim bat using a text editor The batch file is intentionally blank Using the syntax information provided above edit the batch file so it includes the following settings a Simulation Executable name simulate isim exe b Launch in GUI mode c Setsimulation database output name to simulate isim wdb Note A wave configuration file is not provided in the tutorial files This file will be created Save and close the file Double click on the simulate isim bat file to run the simulator ISE Simulator ISim In Depth Tutorial www xilinx com 21 UG682 v1 0 April 27 2009 Preparing the Simulation XILINX The ISim GUI will now open and load the design The simulator time will remain at 0 ns until you specify a run time Note You can browse to the completed folder for a completed version of the simulate_isim bat batch file for comparison purposes 22 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Chapter 4 Using ISE Simulator ISim Graphical User Inte Overview of ISi rface m Graphical User Interface The ISim Graphical User Interface GUI contains the wave window toolbars panels and the status bar In the main window you can view the simulation visible parts of the design add and vi
61. tion time or at the main cursor as determined by the Sync Time toolbar icon e Data Type Displays the data type of the corresponding simulation object logic or an array Wave Window mE clk_in drp skart drp change made drp currenk made drp done drp skmach reset user dcm reset drp multiply 7 0 A drp divide 7 0 amp derm_clkO_out EI a Default wichg Figure 4 6 Wave Window The Wave window displays signals buses and their waveforms Each tab in the Wave window represents a wave configuration which consists of a list of signals and buses their properties and any added wave objects such as dividers cursors and markers In the user interface the signals and buses in the wave configuration are being traced during simulation and therefore the wave configuration is used to drive the simulation and to then examine the simulation results Since design and simulation data are contained in a database simulation data is not affected when adding signals to or removing signals from the wave configuration 26 www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Overview of ISim Graphical User Interface Text Editor Po Description This unit connects instantiatiorns s lz aioe and IDEF controller to the extern UG l rary DEEE LTO CSE IEEE SID LOGIC 1164 ALL 1 amp 8 use IEEE SID LOGIC ARITH ALL 19 u
62. ure Follow the next steps to mark each time a new test has started with markers in the wave window 1 Inthe Console panel identify the simulation times when each test has started For example Test 2 starts at about 3 46 microseconds 3 461 664 ps as shown by this segment of the ISim console ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design at 3461664 ps Note drp_demo_tb Test 2 START Set DCM_CLKFX_OUT 120 MHz 8 332 ns via DRP Cycle M 7 D 5 Figure 4 33 Console Window 2 From the menu select Edit gt Go To to move the main yellow cursor when the first test bench test is performed It should be about 1 150 ns 30 To Wave Objects d Markers k Figure 4 34 Edit gt Go To si gt Go To Time 1150 ns wv xi Eubarial 1 wcFg Figure 4 35 Go To Time 3 Add a marker at this time To add a marker either Ir Usethe Add Marker H8 icon in the main toolbar Use the menu command Edit gt Markers gt Add Marker 4 Repeat these steps for all 4 tests performed by the test bench The wave window should look similar to Figure 4 36 ISE Simulator ISim In Depth Tutorial www xilinx com 41 UG682 v1 0 April 27 2009 Examining the Design amp XILINX ee Float tutorial 1 wcfg File Edit View Simulation Window Help TEST BENCH i clk_in je user dcm reset m period LER DRP Test Signals amp
63. vailable in the ISim main window consists of many functionally different toolbars Each of these toolbars offers access to frequently used commands e File and Edit menu commands e Window and View menu commands e Simulation menu commands The main window toolbar icons are located near the top of the user interface Instances and Processes Panel Instance and Process Mame ij uur id Inst drp dcm i CLkFX BuFG INST i cLk BLUFG INST il DCM ADw INST Cn 43 Ls gt C 50 id Inst drp stmach Lf SYNC PROC CH NEXT STATE DECOE Li DCM RESET CH 133 C 136 F a lil gt x Instances and Processes Source Files E Figure 4 3 Instances and Processes Panel The Instances and Processes panel displays the block instance and process hierarchy associated with the wave configuration open in the Wave window Instantiated and elaborated entities modules are displayed in a tree structure with entity components being ports signals and other entities modules www xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 amp XILINX Overview of ISim Graphical User Interface Source Files Panel Source Files 0 x BLIFG whd DEM_ADY vhd drp dem vhd drp demo vhd drp demo tb vhd drp stmach vhd drp tb pkg vhd numeric skd vhd prmbvs b vhd prmbvs p vhd std logic 1164 vhd std logic arith vhd std logic unsigned vhd textia hd timing b vhd timing p vhd unisi
64. vide 7 0 I LI DCM Test Signals dcm clt aut I edm ot dcm lacked DCM L Inputs I L 7 Outputs b W Internal DRP CONTROLLER b E Inputs pup pA a fei tutorial 1 wcfg Sim Time 12568 ns Figure 4 41 Time Delta Using the cursors we measure a 7 142 ps time difference between two rising edges of the dcm clkfx out output clock This translates to a 140 MHz clock signal Test 2 fails due to the frequency discrepancy expected is 75 MHZ Repeat the same steps above to analyze the Test 4 failure You should observe that while the test bench expects a frequency of 400 MEZ the actual frequency measured is 300 MHz Note Use the Floating Ruler feature available from the wave window toolbar to display a hovering ruler over the wave configuration This feature is available when performing a time measurement using cursors between two endpoints The zero 0 ps on the ruler is placed at the first time endpoint This feature is useful when making multiple time measurements with respect to the first endpoint ISE Simulator ISim In Depth Tutorial 45 UG682 v1 0 April 27 2009 Examining the Design XILINX lk drp stmach reset p BA idrp demo tbidrp multiply 7 0 5 p EM idrp demo tbjdrp divide 7 0 i da LI DCM Test Signals lk dcm clk aut dcm clkFx out lk dcm locked DCM A Inputs P L 1 Outputs L 1 Internal DRF CONTROLLER DRP CONTROLLER X1 3 773 568 ps x2 3 766 426 ps PAX 7 142 ps F
65. w Measuring Time You can use the main cursor to measure time between two endpoints You will use this feature to confirm the test bench calculations reported in the console during Test 2 by measuring the period of dcm clkfx out after the DRP cycle has completed signal drp done is asserted Io measure time using cursors 1 Use the Snap to Transition toggle button til to easily snap the cursor on to transition edges 44 ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design 2 Press and hold the left mouse button in an area around the first clock rising edge following DRP cycle completion drp done signal asserted The main cursor will snap to the rising edge of dcm clkfx out 3 While holding the button move the mouse over to the next clock rising edge A second marker should appear 4 The time between the two defined endpoints will appear at the bottom of the wave window as a time delta refer to Note Use Zoom In _ for better performance of the time measurement feature iss Float tutorial 1 wcfg BE File Edit View Simulation Window Help E8 X La d 3 750 000 ps 3 770 DD ps 800 000 ps ra TEST BENCH ll ck in i B user dcm reset i o lle period Duc 10000 Fs i RE DRP Test Sigrials ep drp start A E drp change made I E drp current made I Hl drp dene drp stmach reset 0 mA idrp demo tbjdrp multipl 7 0 f 06 na jdrp demo tbjdrp di
66. w xilinx com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Simulating the Design test bench to perform verification routines Once the VHDL library is created move the VHDL package file from the work library to the newly created VHDL library Creating VHDL Library Follow these steps to create a VHDL library 1 In Project Navigator select Project gt New Source The New Source Wizard opens 2 Select VHDL Library as a source type 3 Type drp tb lib for the VHDL library name Refer to Figure 2 11 4 Click Next to continue se Hew Source Wizard Select Source Type Select source type File name and its location 4 IP CORE Generator amp Architecture Wizard Implementation Constraints File Schematic z3 User Document verilag Module 14 Verilog Test Fixture drp tb lib File name Hg WHOL Module VHDL Library P YHEL Package E 1ProjectsISirn_Tutorial Vai VHDL Test Bench f Embedded Processor Location Add ta project Figure 2 11 Select Source Type 5 Click Finish to complete the New Source Wizard ISE Simulator ISim In Depth Tutorial www xilinx com 11 UG682 v1 0 April 27 2009 Simulating the Design XILINX lise Hew Source Wizard EI Summary Project Navigator will create a new skeleton source with the Following specifications Add ta Project Yes Source Type VHDL Library Source Mame drp tb lib Figure 2 12 New Source Wizard Mov
67. ws that should look similar to Figure 4 44 and Figure 4 45 3 Float tutorial 1 wcfg al File Edit wiew Simulation Window Help DPARSIiXDBXO oa MIBAMSIEANIAAKA Bi em i OAS dD oo vjos Il a e x 2 000 000 ps S 6 000 000 ps 8 000 000 ps 10 QOO 000 ps 12 000 TEST BENCH i clk in ye user_dcm_reset period LA DRP Test Signals we drp start b ROO wX ye drp_change_mode U drp_current_mode yl we drp done i drp stmach reset p BA jd demo tb drp multiply 7 0 p EM dp demo tb drp divide 7 0 Y E DCM Test Signals we dem_clkO_out is dem clkfx out we dcm locked X1 12 668 332 ps tutorial 1 wcfg Sim Time 12668 ns Figure 4 44 Wave Window ISE Simulator ISim In Depth Tutorial www xilinx com 47 UG682 v1 0 April 27 2009 Debugging the Design XILINX 5 Float tutorial _2 wcfg a File Edit view Simulation Window Help DBA 3 X BBXO oa MI ERORI ANR AAA lalea I gt 3100s v Gs a Name Value D ps 2 000 000 ps s 6 000 000 ps 8 000 000 ps 0 000 000 ps 12 000 DCM Y L 7 Inputs a clkin_in p PF daddr_in 6 0 a dclk in a den in s di in 15 0 rk ROO XY mat sa dwe_in r MEE gt Mb Outputs E Internal DRP CONTROLLER hi L 1 Inputs sa clk E x ga start p reset a new freq mode a drp ready a dcm locked Ls L 1 Outputs a L 7 Internal X1 12 668 332 ps lt gt lt gt TO tutorial 2 wcfg Figure 4 45 Wave Window
68. x com ISE Simulator ISim In Depth Tutorial UG682 v1 0 April 27 2009 XILINX Examining the Design e drp multiply e drp divide To change the signal name format 1 Inthe wave window right click on the signal name listed under the Name column 2 Select Name Long Refer to Figure 4 25 Signal Color d Custom m m m Figure 4 25 Change the Signal Name Format Note You can perform a format change on multiple signals with fewer clicks by Selecting multiple signals using Ctrl Shift Applying the format change via the right click context menu Changing the Signal Radix Format Some signals are better interpreted if seen in hexadecimal rather than in binary For example the signals drp multiply and drp divide are bus signals that are best interpreted in hexadecimal format rather than binary You will change the format of the following signals from Binary to Hexadecimal e drp demo tb drp multiply e drp demo tb drp divide To change the radix of a signal 1 Inthe wave window right click on the signal name listed under the Name column 2 Select Radix then the radix type you wish to interpret the signal in Refer to Figure 4 26 iL ANL Signal Color d Hexadecimal Reverse Bit Order Unsigned Decimal Figure 4 26 Changing the Radix of a Signal Changing the Signal Color ISim allows you to change the signal color in the wave window to help you quickly identify similar signals from

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