MPC5604EEVB64 Evaluation board User Manual
Contents
1. o 6551 C552 C548 C547 C519 C518 99 ee 4 4 m cmo fom d d ce cat yy 4 0 1UF O 01UF 0 1UF O 01UF 0 01UF 000 000 O00PF 000 O00PF 000 VDD ADR GND GND GND 6545 0544 VDD HV ADR C542 6543 T ij PES T m 0 01UF 50 HDR em O00PF 1000 33V VSSA 9 J20 1 HDR TH 1X3 V IN HE HDR 1X2 TH 2129 18 1 2V R513 219 V BALLAST IN RES 1 C537 C538 C541 C540 C539 5 5 06528 05 530 6526 0524 525 Fre Wes Um VDD LV rid tiiti 25 m E al E m al ad m al m HDR TH 1X3 i 0 01UF o 1UF 0 1UF 0 01UF 0 01UF 000 O00PF 000 000 000 5 1booPF 3 1 4 4 8 HDRTH1X3 5 9 1 gt ooo GND GND GND GND us ng 8 88 80 z 9 2 8 5005 128 9 2 aaa a 08 AO 3 D 11 DSPI SIN EIRQJO GPIO OySAIO DJO as J 8089 9 98 PORT Ai2. DNP 5 AUDIO INTERFACE OMNIVISION VIDEO INTERFACE 3199 33 PU DATAS 2 3004 J45 SAIO DATA2 gt 3 o 02 208 5 00 27 9 3 VID DATAS CON VID 298 DATAO CON VID 3 L6o L3 Q2 CON VID 3 tT Soe 3 VID DATAS 5 lt CON 3 93 SYNC 1 i PO VID DATA 1940047 CON VID DATAIO _ 15 00 15 Loo VID PWDN pol 2 50 1 TI VID TIC DATA AUD TIC CLK 19 20 4199443 VIRO DATA DM Pan eet os AUD ICI DATA 21 0 O22 VID HSYNC Ht oot VID IC CLK po 1 1 DATA 9 2100 2 VID VSYNC 119944 1 pals 2 00 28 VID 20199 19 80 ES ETGT 5 5 1 199 5 4 SYNC 9 200 2 VID DATAS Loot VID DATA2 98 MCLK oo Bx po AUD am oek too 3 28 20 127 po AUD DATA ae 0 0 FX po 3 SAI2 DATAO 3g 0 0 45 98 VIDEO INTERFACE SAZ BOLK Stools SA SYNC
3. 99 HDR 1X2 TH 5 Di R502 10K ay 2 1 7 83V 99 HDR 1X2 TH 0500 vA Bm HDR TH 1X8 9 LINC RX 1 8 GFIA 1 4Pin Header 1 4 UART A TX x IH i A LINC VSUP LINCUN 219 2 x 5 o LINC TX DO cub 5 I 416 C500 C501 R504 10 0K GND M 1000PF 0 1UF 3 UART RX Em GND GND GND 2259 O 1 UNO RXD I oH GND 22 LIN Molex Connector CONPLUG 4 33V 99 HDR X2 TH C505 C507 our toooPF 1 L___ Ld 7 GND 2 C503 H 3 4 4 0 1UF 2 9 gt 0 1UF yo 5 cz SND Me C2 eue R iN fi eg i R2IN 15 33V RIOUT DART ATX gt nzour INVALID 35 GND rare FORCEOFF EN 14 FORCEON 7 v GND C502 0 1UF GND a 2 223 GND 2 freescale semiconductor ICAP Classification FIUO x Drawing Title MPC5604 EVB Page Title LIN amp SCI PHYSICAL INTERFACE Size Document Number Rev c SCH 27073 PDF SPF 27073 Ai Date Wednesday October 12 201 Sheet 10 of 13
4. Place CAPS as close to JTAG INTERFACE connector pins as possible but do NOT fit caps at board assembly C506 DNP 4 47PF C504 DNP 3 3V k 9 JTAG Connector 4 P5 TDI 1 2 0 lt oo 315044 85 9615 f oo pg 8 1 JTAG RST B lt JTAG RST_B EI 5 T8 9 0 14 Oo 3 3V 2 7 R501 10 0K DNP gt R503 10 0K GND 7 JCOMP rona 9 11 TMS 2 freescale semiconductor ICAP Classification FCP FIUO X Drawing Title MPC5604 EVB Page Tille DEBUG INTERFACE Size Document Number Rev SCH 27073 PDF SPF 27073 9 13 Date Wednesday October 12 2011 Sheet 6 1 Power On Reset 7ALVC14AD sw2 KS11R23CQD ITMSTSRDWIGF 33V gt gt JTAG RST_B pg 6 8 11 R4 IND 7ALVC14AD 1 swa KS11R23CQD ok JCOMP 10 ndn PW ON RESET ey e HDR TH AA 15K 1X8 Ri TALVC14AD 12 TALVC14AD 7ALVC14AD Boot Config 3 3V HDR TH 1X3 47 999 R543 4 7K L MC
5. Rag gt gt CON VID VSYNC pg 11 PORT A6 gt gt R38 Sh gt gt SAI2_SYNC 4 RE 0 JP25 10 1 A SF gt gt CON VID HSYNC po 4 11 PORT C2 gt O ixi Res 0 11 PORT S gt gt ETCO R4 gt SAIO_BCLK pa 4 i n Res 0 ime CON VID DATAG pg 4 gg poi PORT gt 1x1 94 0 11 PORT A8 e gt gt pod 942 0 ANA gt SAIZ_DATAO 4 gt gt CON VID DATAS pg 4 16 750 A9 0 4 1 PORT_C4 gt gt gt 80 4 7 R30 0 DNP 878 40 2 SAI2 BCLK pa 4 gt gt MCLK 4 10 gt gt CON VID DATA4 PORT 10 gt R4 ANA gt gt SAI2 MCLK 4 10 dS az CON VID DATA3 pa 4 PORT DNP Uus 1 o HDR 1X1 2 freescale semiconductor 10 Ras GONE DM pi ICAP Classification FCP FIUO Pug X Drawing Title PORT Ai2 gt 4 5604 JP13 Title R48 0 DNP i RESISTOR MUX bod e erm Ss Document Number Rev SCH 27073 PDF SPF 27073 gi 13 Date Wednesday October 12 2011 Sheet 3 1 33V
6. 2X16 SAIZ MCLK 2 00 1 98 ETCO 24 50V ANI3 4g 0 0 50 Pin Numbering on this Omnivision mating connector DNP as female part required on EVB HDR_2x25 is mirror image of the numbering on the Omnivision Daughter Card GND 2 R529 32V m 4 Le gt R532 li polii PORT A13 o VID CLK R535 gt gt VID IIC CLK 4 HORTH1x3 101 p 94 HOR TH 1X8 DATA J36 37 012 0 o 1 o PORT 14 eto pas HDR TH 1X3 47K HDR TH 1X3 101 __ Hoi DATA R540 0 CLK J39 1 HDR TH 1X3 AUD ICO CLK ico 2 R539 0 DATA J40 1 o DATA 9 190 319 o HDR TH 1X8 AUD JIGO DATA gt gt AUD_IICO_DATA pg 4 HDR TH 1X3 i e PORT J25 CK 2 MC FAB pa 7 HDR TH 1X3 gt freescale 59 20 E ICAP Classification FOP FIUO X J26 Drawing Title MPC5604 EVB Page Tile VIDEO amp AUDIO SECTION HCODATA DATA Size Document Number Rev SCH 27073 PDF SPF 27073 Al Date Wednesday October 12 2011 1 oi 18 5 z 1
7. 3 13 B 2JADCO AN ISJCE TRIGGERI GPIO 18yLINO TXICE PPS2 CE ALARMI PORT B2 3 13 B S ADCO AN 14JLINO RX EIRQ 14J GPIO 19J ETIMERO ETC 2 DSPIo SOUT CE PPS1 PORT B3 3 13 53 B 4JFEC DV GPIO 20 35 DV 296 RXD3 34 D3 GPIO 32 B S GPIO 21 FEC TX DO SSCM DEBUG O FEC TXDO pg 5 27 CLK EIRQ TS GPIO 33 B S GPIO 22 FEC TX D1 SSCM DEBUG 1 TXD 08 C2 C 2 VID D OLINO RX EIRQ 1G GPIO 34J ETIMERO TX CE 51 B 7 GPIO 23JFEC TX D2 SSCM DEBUG 2 TXD2 pg 5 08 PORT C3 C 3 VID D 1 CANO RX EIRQ 17 GPIO 3S ETIMERO ETC 1JLINO TX SAI SYNC B B GPIO 24 FEC TX D3 SSCM DEBUG 3 FEC TXD3 pg 5 ls 08 PORT C4 63 CIA CE TRIGGERI MC RGM ABS OyEIRQ 19JGPIO 36JMC CGL MC CGL ETIMEO _ B SJGPIO 25 FEC TX EN SSCM DEBUG 4 4s FEC TX EN 0 5 PORT C5 4 5 ABSI2J EIRQ 2OJGPIO 37 ICO CLK ETIMERO ETC 3JDSPI2 052 B 10JGPIO 26 FEC MDC SSCM DEBUG S FEC MDC 5 04 6 C 6JMC FAB EIRQ 21JGPIO 38 IICO DATA DSPI1 CSO DSPI2 CS3 B TT GPIO 27 FEC MDIO SSCM DEBUG S FEC MDIO R531 10 0K B 12JFEC TX CLK GPIO 28 SSCM DEBUG 7 TX pg 5 ji B I3JFEC DO GPIO 29 RXDO 5 A B 14JFEC RX D1 GPIO 30 57 FEC_RXD1 5 B 15JFEC D2 GPIO 31 FEC R
8. RXD2 PHY N 44 RXD2_PHYAD2 28 2 9 13 RXD1 PHY AG 43 1_ 1 LEDACTCOL_ANEN 25 P 5 13 RXDO PHY 33 RXDO_PHYAD1 LEDLINK ANO W REDA 58 po 5 13 FEC_RX_DV _PHY qox REF MIMODE LEDSPEED AN 27 H RLEDK 55 RX 4 FOF 25 RXER_MDIXEN 25 e 124 99 FEC COL TP5 40 COL PHYADO PFBOUT ib m LEDA FEC CRS ra CRS_LEDCFG m eo E E mo 2 iq BEGINS E 49 0 1UF ruse 79 95 13 MDC PHY AS 31 813 MDIO PHY gt 1 MDIO alb gi EP PF GND RESET 24 tn 33V PWRDN INT RBIAS ey dd e es JTAG RSTB gt 20099 ca 222 SSSSS al al HDR TH 1x3 88888 0000 R9 249 gt R527 gt R526 R528 525 2 R524 gt R523 gt R522 gt RIS gt R520 gt R518 2 R516 gt R514 bii O AUF 0 UF 01UF 10UF 3 22K 22K 9 22K 5 22K 9 22K 5 22K 9 22K 9 22K 22K 9 22K 9 22K 9 22K 4 7K E ebl 55855 33V Q J21 4 v 249 PWONRESTB gt gt GND GND GND GND 7 freescale semiconductor ICAP Classification FOP FIUO X Drawing Title MPC5604 EVB Page Till ETHERNET PHYSICAL INTERFACE AND RJ45 Size Document Number Rev SCH 2707 PDF SPF 27073 At Date Shes 8 oi 18 Wednesday October
9. 11 11 pott pa 11 11 11 11 5 0V 3 3V _ R52 0 FEG TXD3 R53 22 DNP R55 0 FEG TXD2 gt 34 R54 22 DNP R57 0 FEC TXDi 9 4 R56 DNP R58 i FEC 3 3 R58 DNP RET FEG TX X H R60 DNP Re FEC_TX_CLK 33 4 R62 22 DNP 0 FEC_MDC X 22 DNP CONN gt FEC TXD3 PHY gt gt FEC_TXD3_CONN gt gt FEC TXD2 PHY gt gt FEC TXD2 CONN gt gt FEC_TXD1_PHY gt gt FEC_TXD1_CONN gt FEC TXD0 PHY gt gt FEC_TXD0_CONN gt gt FEC TX EN PHY J FEC TX EN CONN TX CLK PHY 3 FEC MDC PHY gt gt FEC_MDC_CONN 1 96 MDC CONN gt z pol 54 2 CONN 5 pos RXDICONN 7 pg CONN RX DV CONN 5 RX CONN RKER TCER 137 TX EN CONN 14 PO 00 CONN 154 FEC_TXD1_CONN 16 pois TXD2CONN 9 17 PU TXD3 CONN 18 213 pele POWER 21 1 HDR TH 1x3 9
10. Features to review the list of board features 4 2 Power The EVB requires an external power supply voltage of 12V DC minimum 1A This allows the EVB to be easily used in a vehicle if required The single input voltage 1 regulated on board using switching regulators to provide the necessary EVB and MCU operating voltages of 5 0 V 3 3 V and 1 2 V For flexibility there are two different power supply input connectors on the EVB as detailed below MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 3 EE Configuration 4 3 Power supply Connectors 2 1 mm Barrel Connector P4 This connector should be used to connect the supplied wall plug mains adapter NOTE If a replacement or alternative adapter is used care must be taken to ensure that the 2 1 mm plug uses the correct polarization as shown in Figure 2 4 V4 12 3 GND Figure 2 2 1 mm Power Connector 2 Way Lever Connector P1 This can be used to connect a bare wire lead to the EVB typically from a laboratory power supply The polarization of the connectors is clearly marked on the bottom site of the EVB Care must be taken to ensure correct connection V 12 GND Figure 3 2 Level Power Connector 4 4 Power Switch SW1 Side switch SW1 can be used to isolate power supply input from the EVB voltage regulators if required Position 1 will turn the EVB OFF e Position 3 will turn the EVB ON MPC560
11. A 6 3 Audio J48 Table 17 Audio Connector Pinout J48 Pin Function 3 3 V GND SAIO_DATA3 GND SAIO_DATA2 GND SAIO_DATA1 GND SAIO_DATAO GND SAIO_BCLK GND SAIO_SYNC GND SAIO_MCLK GND ETC2 AN14 ADC signal GND AUD IIC1 o CO N OD ao N N A REN N e MPC5604EEVB64 Evaluation board User Manual Rev 0 22 Freescale Semiconductor Table 17 Audio Connector Pinout J48 continued Pin Function 20 GND 21 AUD IC1 DATA 22 GND 23 SAI1 DO 24 GND 25 SAI1 BCLK 26 GND 27 ETC1 28 GND 29 SAI1 SYNC 30 GND 31 SAI1 MCLK 32 GND 33 AUD 34 GND 35 AUD IICO DATA 36 GND 37 SAI2 DATAO 38 GND 39 SAI2 BCLK 40 GND 41 SAI2 SYNC 42 GND 43 SAI2 MCLK 44 GND 45 ETCO 46 GND 47 AN13 ADC signal 48 GND 49 5V 50 GND MPC5604EEVB64 Evaluation board User Manual Rev 0 User Connector Descriptions Freescale Semiconductor 23 User Connector Descriptions 6 4 VIDEO J45 Table 18 Video Connector Pinout J45 Pin Function 1 CON VID DATAA 2 CON VID DATA5 3 CON VID DATAG 4 CON VID
12. of 13 Date Wednesday October 12 2011 1 6 7 11 pg 7 11 Ethernet Section 33V J22 HDR 1X2 TH These are 100MHz all lines must be matched and as short as possible R10 225 5 2 2K R5 7 9 R519 1 5K 1 5K c17 c19 GND 49 9 GND GND g 10 100 single phy 8 1454 1 4 TX Resistors Place Cose to PI 25MHZ az xi 34 88 55 C520 RX Resistors Place Close to MCU QZiX2 22 RNIB x2 55 88 25 499 0 1UF J24 4 5 6 yd 25MHZ_OUT 1 0513 FEC_TXDS PHY 3 5 55 TXD3_SNIMODE 17 ETON TD 13 TXD2 PHY us i TXD2 top 5 TD SHIELDI pg 5 13 FEC_TXD1_PHY RS TXDi TDN Lt SHIELD2 5 13 FEC TXD0 PHY 2 t 2 TXDO 96513 FEC TX EN PHY ma 1 TXEN 44 2513 CLK PHY AA TXCUK Hig 5 RDN RD pg 5 13 FEC RXD3 PHY 3 48 ERON 2 po 5 13
13. E 26 31 36 GND SHI 5787170 4 pg 8 13 5 pg 8 13 5 0 8 13 5 pg 8 13 5 8 13 5 0 8 13 CONN 5 8 13 5 11 FEC RXD3 9 4 gt gt FEC RXD3 PHY 8 13 RXD3 CONN 5 pg 11 FEC_RXD2 RXD2 p9 8 13 3 FEC RXD2 CONN 5 11 RXDi X g gt gt FEC_RXD1_PHY po 8 13 gt gt FEC_RXD1_CONN 5 RXDO XX 4 RXDO pg 8 13 gt gt FEC CONN 5 11 gt R90 0 FEC RX DV 8 13 DNP Rot 0 gt gt FEC_RX_DV_CONN 5 FEC RX GLK S 34 R92 0 FEC RX CLK PHY 8 13 11 DNP Re 0 RX CLK CONN 5 R94 22 gt gt FEC MDIO PHY 8 13 DNP 3 FEC MDIO CONN 5 Cn e 2 freescale semiconductor ICAP Classification FCP FIUO PUBI Drawing Title MPC5604 EVB Page Title CONNECTOR SECTION Size Document Number SCH 27073 PDF SPF 27073 Rev 13 Date Wednesday October 12 2011 Sheet 5 of 1
14. GND A 15 GND FEC TX EN MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 19 User Connector Descriptions Table 14 FEC Connector Pinout J33 Pin Function 16 NC 17 NC 18 NC 19 GND 20 GND 21 FEC MDC 22 NC 23 FEC MDIO 24 FEC RX DV 25 GND 26 GND Table 15 MII Connector Pinout J49 Pin Function 1 POWER MII CONN 2 MDIO 3 MDC 4 RXD3 5 RXD2 6 RXD1 7 RXDO 8 RXDV 9 RXCLK 10 RXER 11 TXER 12 TXCLK 13 TXEN 14 TXDO 15 TXD1 16 TXD2 17 TXD3 18 COL 19 CRS 20 POWER MII CONN 21 POWER MII CONN MPC5604EEVB64 Evaluation board User Manual Rev 0 20 Freescale Semiconductor Table 15 Connector Pinout J49 continued Pin Function 22 GND 23 GND 24 GND 25 GND 26 GND 27 GND 28 GND 29 GND 30 GND 31 GND 32 GND 33 GND 34 GND 35 GND 36 GND 37 GND 38 GND 39 GND 40 POWER MII CONN MPC5604EEVB64 Evaluation board User Manual Rev 0 User Connector Descriptions Freescale Semiconductor 21 User Connector Descriptions 6 2 ADC J38 Table 16 ADC Connector Pinout J38 Pin Function GND GND ADCO_AN 11 ADCO AN 13 GND GND ADCO AN 12 ADCO AN 14 GND GND o N
15. Video amp Audio section Sheet 4 MII Connector section Sheet 5 Debug Interface section Sheet 6 Reset amp Clock section Sheet 7 Ethernet Physical Sheet 8 Interface and RJ45 CAN Physical Interface Sheet 9 LIN amp SCI Physical Sheet 10 Interface MPC5604E SoC Sheet 11 LED amp Switch section Sheet 12 User connectors Sheet 13 MPC5604EEVB64 Evaluation board User Manual Rev 0 Schematic Diagrams Freescale Semiconductor 27 12 mana 33 80 HDR 1 1 1 1 J4 o Power supply input and filter AP dene 1X1 HDR 1X1 HDR 1X1 HDR 1X1 1 e 10 o ws ot JP o onnector 2 HOR 1Xi HOR 1X1 HDR 1X1 P4 Fi EX 1 12V IN VSwihed 0001 aw 2 VFused gt 1 JP20 we apt Oey NOR a POWER SWITCH E bi e HDR 1X1 HDR 1X1 HDR 1X1 HDR 1X1 a a 02 B130LB 13 GBUF 2
16. 1000UF fot we lot 511 o Pi 0 1UF 1000PF 1 2 Lever gt Connector 2 o B 5 4 Distribute Evenly over the board GND CON 2 TB GND GND Power Supply 3 3V Power Supply 5 0 V 07 141485 D10 1 2 1N4148WS al pey e u12 4 8 IN 2 3 3V 4 ES 8 2 2 1 15 soy 3 veo i 24 1 Slm wH O1UF 4 l 6 6 5 5VFB PG AA PG FB R23 00K 7 lt 40 2K 24 1000 7 EN lt 40 2K C27 C28 c26 C24 C29 71 cao 71 C34 C35 c36 c32 T c39 MP2380 LI 4 21 E 2380 698 10UF 10UF O 1UF 1 0 UF R20 0 1UF 47UF 47UF 10UF 10UF 0 1UF 1 0 UF R50 j 0 1UF 47UF 10 0K D8 10 0K D15 B5300 g B530C R22 13K 7 68K E 4 4 4 4 4 4 4 4 V GND GND GND GND 50 lt lt De D16 LED GREEN LED GREEN Power Supply 1 2V R21 R79 100 249 3 o C10 GND GND o VREG 1 2 x w 2 i HDR TH 1 3 1 1 2 50V vec sw Nn pee pa k Tt ons R7 100 0 7 162K aan E uie d 1 2 cis 71 T oe 0 1UF n 2380 40UF 100 1 0 UF 0 1UF 47UF 4 47UF 10 0K 06 B530C R5 324K 4 4 4 4 4 GND GND 2 freescale semiconductor ICAP Classification FCP FIUO X Drawing Title MPC5604 EVB Page Title POWER SECTION Size Document Number Rev SCH 27073 PDF SPF 27073 Date Wednesday October 12 201
17. 3 Alt VID D 10 EIRQ T GPIO 1JSAIo D 1 DSPIT SOUT 85 2 5 z 98 PORT A2 A 2 VID D SJETIMERO ETC SJEIRQI2 GPIO 2 SAIo D 2yDSPH 5 5 D O Se 2 al d x pg 3 PORT A 3JVID D B DSPI2 SIN EIRQ SGPIO S SAIo D S SAI2 D 0 4 Qo 8 3 PORT A4 3 D 7 ETIMERO ETC 3 EIRQI4JGPIOI4 SAlo SYNC DSPI2 SOUT 28 8 ry 5 sl PQ3 PORT T0 A S VID CLK ETIMERO ETCI4JEIRQISJ GPIO SAIt SYNC DSPI2 5 5 00 54 5 25 PQ3 PORT A6 36 A 6 VID D OETIMERO ETCT JEIRQIS GPIO SJ SAI2 SYNC DSPI2 CSOVID VSYNC i2 8 PORT 4 AU7 VID D 1 ETIMERO ETCI2yEIRQ 7JGPIO 7 SAIo BCLK DSPI2 CS VID HREF 88 8 es 3 3 PORT A8 5 AIBJVID D 6JLINI RX EIRQ B GPIO S SAI BCLK DSPI CSO SAI2 00 gt gt gt 3 PORT 9 28 lS VID DIS EIRG SGPIO S SAI BCLKDSPI CST LINT TX 08 10 27 A 10 VID_D 4 DSPIO_SIN EIRQ 10 GPIO 10VSAi2_MCLK ETIMERO_ETC 5 9 PORT AI D SJLINO RX RX GPIO 11J CANO TX DSPIO CST DSPIi 50 gt 08 PORT Ai2 A 12 VID D 2 CANO RX EIRQ 11 GPIO 12 LINO TX DSPIO CSO LIN1 TX zi PORT Ai3 A 13yEIRQ 12 GPIO 3 lICi CLK FCUO FIOyDSPIO CSO 8 pg 4 Ai4 ei AL14JDSPIO SIN EIRQ 13 GPIO 14 IIC1 DATA FCUO F 1yDSPIO CS1 gt 17 PORT Ai5 A TSJDSPIt SCK ETIMERO ETC OJ EIRG 18 GPIO 15 DSPIO 5 MCLK B OJADCO AN M GPIO 16 CANO TX CE ALARM2 SAIt BCLK PORT BO 3 13 B TJADCO AN 12 CANO RXITRIGGER2 GPIO 17 SATi DIO PORT B
18. B Date Wednesday October 12 2011 Sheet 1 How to Reach Us Home Page www freescale com Web Support http Awww freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MPC5604EEVB64UM Rev 0 10 2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconduct
19. DATA 5 CON VID DATA8 6 CON VID DATA9 7 CON VID DATA10 8 CON VID DATA11 9 VID PWDN 10 NC 11 VID DATA 12 NC 13 VID CLK 14 CON VID HSYNC 15 GND 16 CON VID VSYNC 17 GND 18 CON VID CLK 19 MC RGM ABSO 20 5V 21 GND 22 5V 23 CON_VID_DATA2 24 CON_VID_DATA3 25 NC 26 NC 27 NC 28 NC 29 NC 30 NC 31 GND 32 GND MPC5604EEVB64 Evaluation board User Manual Rev 0 24 Freescale Semiconductor 6 5 6 6 6 7 6 8 User Connector Descriptions NMI J29 Table 19 NMI Connector Pinout J29 Pin Function 1 GND 2 NMI 3 3V LINFLEX P7 Table 20 LINFLEX Connector Pinout P7 Pin Function 1 12V 2 LINC VSUP 3 LINC LIN 4 GND FlexCAN P6 Table 21 FLEXCAN Connector Pinout P6 Pin Function 1 CANH 2 CANL 3 GND 2 clock selection J27 J28 J36 J37 439 440 Table 22 Routing 0 to Video Connector video usecase Signal description Jumper Reference Configuration Description 0 clock 425 2 3 Port C5 routed to J39 as signal 439 1 2 signal routed to J28 J28 2 3 is selected for Video clock 0 data 426 2 3 Port C6 routed to J40 as DATA signal J40 1 2 DATA signal routed to J37 J37 2 3 DATA is selected for Video data MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconduct
20. J9 FITTED D WAKE CAN Transceiver WAKE Position 1 2 is connected to GND REMOVED WAKE is not connected and available on Pin 2 J9 FITTED D STB CAN Transceiver STB is Position 3 4 connected to 5 V REMOVED STB is not connected and available on Pin 4 J9 FITTED D EN CAN Transceiver is Position 5 6 Enabled REMOVED EN is not connected available on Pin 6 Access to the Error and inhibit signals from the transceivers is provided on J14 NOTE You must do the fitting of the jumper headers carefully as they can easily be fitted in the incorrect orientation 4 11 RS232 Configuration 43 J7 J8 The EVB has a single MAX3223 RS232 transceiver device providing RS232 signal translation for the MCU LINFlex channel The RS232 output from the MAX3223 device is connected to a DB9 connector allowing a direct RS232 connection to a PC or terminal Connector P2 provides the RS232 level interface for MCU SCI LINFlex The connector pinout is detailed below MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 11 Configuration NOTE The hardware flow control is not supported on this implementation V GND Figure 9 RS232 Physical Notifies Connector The MPC5604E LINFlex also provides hardware LIN master capability which is supported on the EVB via LIN transceiver Jumpers J7 and J8 are provided to isolate the MCU LINFlex signals from the RS232 interface as described below Th
21. MII lite connector Crystal clock JTAG One LIN and one UART interface selectable through Jumper setting One FlexCAN interface External Interrupts ADC connector NOTE Before the EVB is used or power is applied please read the complete document on how to correctly configure the board Failure to correctly configure the board may cause irreparable component MCU or VB damage Configuration This section details the configuration of each of the EVB functional blocks Throughout this document all of the default jumper and switch settings are clearly marked with 0 and are shown in blue text This should allow a more rapid return to the default state of the EVB if required The EVB is designed with ease of use in mind and is segmented into functional blocks as shown below Detailed silkscreen legend is used throughout the board to identify all switches jumpers and user connectors MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor Configuration Ethernet MII connector Pew ew Sou bow eu Seu hod n iin User SW amp LED Figure 1 Evaluation board silkscreen legend 4 1 Processor The MPC5604E processor is the fundamental control chip on the MPC5604EEVB64 This is a version 1 Power Architecture running at a maximum core speed of 64 MHz The MPC5604EEVB64 allows you to fully evaluate the feature set ofthe MPC5604E MCU Refer to Section 3
22. RGM FAB pg gt R544 GND 3 3V HDR TH 1X3 R547 99 1 4 7K olaf gt R548 4 7K GND L MC ABSO TALVC14AD 33V HDR TH 1X3 246 99 R545 poen m lt pa 3 4 gt R546 47K GND AA 15K LED RED ps o pa 4 Clock Circuit REMOVE XTAL jumper when driving EXTAL from Oscillator Module or External Source HDR TH 1X3 J31 output lt pg it C555 3 ie crystal output JI EXTAL J 1 T 18pF E R534 D Me 1 0M 25MHZ bas j 9536 0 XTAL J 4 y 18pF GND 9 crystal 11 HORTHIXS HDR 1X2 TH J34 11 33V C554 Em i 4l 0 01UF vi 8MHz Note Internal Pull Up on Pin 1 a H GND vcc 5 2 HDR TH 1X3 J32 OSC MOD SS GND EVB EXTAL EXTAL SMA CON_1_SMA al 3 SMA style CH Connector 9538 100 J35 T AAA GND STRAIGHT SMA CONNECTOR PLACE NEAR TO SOC 2 freescale semiconductor ICAP Classification FCP FIUO PUBI Drawing Title MPC5604 EVB Page Title RESET amp CLOCK SECTION Size Document Number SCH 27073 PDF SPF 27073 Rev Sheet 7
23. VDD BALAST is powered from 1 2 V external regulation mode J20 2 3 1 VDD BALAST resistor is connected J21 2 3 1 JTAG RST is connected to Ethernet PHY MPC5604EEVB64 Evaluation board User Manual Rev 0 18 Freescale Semiconductor Table 13 Default Jumper Positions User Connector Descriptions d Default Setting Description J22 1 2 Power on Ethernet PHY is enabled J23 1 2 Power on VDD HV ADR is enabled J30 2 3 Use on board 8 0 MHz crystal J31 1 2 Use on board 8 0 MHz crystal J32 2 3 Use on board 8 0 MHz crystal J34 1 2 Use on board 8 0 MHz crystal J41 1 2 3 3 V connected to FEC MII connector J44 2 3 is tied to ground J46 2 3 MC RGM ABS2is tied to ground J47 2 3 MC RGM FAB is tied to ground 6 User Connector Descriptions This section details the pinout of the EVB user connectors The connectors are 0 1 inch pitch turned pin headers and are located at various locations on the EVB They are grouped by port functionality and the PCB legend shows the respective port number adjacent to each pin 6 1 FEC J33 J49 Table 14 FEC Connector Pinout J33 Pin Function GND GND FEC_TXD3 FEC_RXD2 FEC_TXD2 FEC_RXD3 0 RXD1 o BI Ww N TXD1 0 FEC_TX_CLK ER N EC_RX_CLK
24. oH JP23 O C558 auk SPST PBNO GND 33V GND HDR TH 1X3 User switches gt 2 freescale semiconductor ICAP Classification FCP FIUO PUBI x Drawing MPC5604 EVB Page Title LED amp SWITCH SECTION Size Document Number Rev c SCH 27073 PDF SPF 27073 Ai Date Wednesday October 12 201 Sheet 12 of 13 1 x FEC J33 Hook 58 TXD3 PHY 54 00 65 FEC RXD2 PHY 5 8 58 TXD2 PHY o otg FEC_RXD3 PHY pg 5 8 58 TXDO PHY 19 94 15 RXDIPHY 58 PO 58 TXDi PHY FEC_RXDO PHY 58 258 TX CLK PHY lt 130 0 14 FEC RX PHY pg 5 8 oo P958 TX EN PHY 19 o 20 0 5 8 MDC 55 E 5 068 PHY lt lt 5599155 gt gt FECRXDVPHY po58 GND GND ADCO Hook po 3 11 PORT_BO lt 5100 6 82 3 11 Hoo po 3 11 PORT Bi 7loo 5 gt gt PORT_B3 pg 3 11 2X5 GND R533 33V GND Cx 2 freescale semiconductor ICAP Classification FCP FIUO PUBI x Drawing Tit MPC5604 EVB Page Title USER CONNECTORS Size Document Number Rev 5 27073 PDF SPF 27073
25. pairs TVss LV CORO X Figure 4 Internal regulation mode External regulation mode In this mode the Ballast supply is shorted to 1 2 V 10 generated from an external regulator The I O supply and the MCU supply continues to be at 3 3 V 10 MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 5 Configuration Pads Pins Vss HV 100 X Vdd HV IO0 X 1 Vdd Ballast0 1 1 2V 1 15V 1 32V Power Supply e g switched or linear relaxed Figure 5 External regulation mode The FlexCAN circuity also has 5 V supplier to the transceiver Table 1 MCU Power Supply Jumpers internal regulation mode Power Domain Jumper Position Description 1 2V J18 X This supplies VDD LV VDD LV supply pins 3 3V J19 1 2 This supplies V BALLAST IN VDD S BALAST supply pin 3 3V J20 2 3 D VDD S BALAST routed via V BALLAST IN HDR BALAST resistor 3 3 V J16 1 2 D This supplies VDD HV VDD HV supply pins 3 3V J23 1 2 D ADC reference voltage 3 3 V VDD ADDR The jumper configuration shown in Table 1 details the default state D of the EVB In this configuration all power is supplied from the regulators MPC5604EEVB64 Evaluation board User Manual Rev 0 6 Freescale Semiconductor Configuration Table 2 MCU Power Supply Jumpers external regulation mode Power Doma
26. purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2011 All rights reserved 5 2 lt semiconductor Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Freescale Semiconductor MPC5604EEVB64
27. 0 PORT 9 routed to SAI2 R44 00 PORT A10 routed to SAI2 MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 17 Default Jumper Summary Table Table 12 Resistor and capacitor to be Value Description populated R70 00 PORT B1 routed to SAI1 DATAO R72 00 PORT BO routed to SAI1_BCLK R76 00 PORT A15 routed to SAI1 MCLK R78 00 PORT 4 routed to SAIO MCLK Sahara SGTL5000 audio daughter card uses I2C interface for configuration For this purpose J27 J28 J39 and J37 should be connected correctly For pin definitions see Section 6 8 2 clock selection J27 J28 J36 137 J39 140 5 Default Jumper Summary Table Table 13 Default Jumper Positions Bd edt Default Setting Description J2 REMOVED 1 Master Mode Pullup disable J3 1 2 1 Power on SCI is enabled J4 1 2 1 Power for User switches is disabled J5 1 2 1 Power on LIN is enabled J6 1 2 1 CAN TXD is connected to MCU J7 2 3 1 UART TXD is connected to MCU J8 2 3 1 UART RXD is connected to MCU J9 1 2 3 CAN control signals are on 3 4 5 6 J10 1 2 1 CAN RXD is connected to MCU J11 1 2 1 Power on CAN PHY is enabled J12 1 2 1 Power on CAN PHY is enabled J13 2 3 1 1 2 power supply switch is supplied from 12 V J15 1 2 1 VPP TEST should be grounded J16 1 2 1 VDD HV is enabled J18 1 2 1 VDD LV is enabled external regulation mode J19 2 3 1
28. 1 She 2 oi 3 5 7 1 0 H AA gt gt CON VID 11 R7 0 11 PORT A15 gt 3 VID PWDN pa 4 11 PORT A0 gt 976 AA gt gt SAM A 27 8 10 gt gt VID pg 11 PORT 1 gt 825 SAID pa 4 10 5 gt VID DATAS 4 11 PORT 2 SS r R34 0 er des pott 11 13 PORT BO CANO TXD pg 9 R72 gt gt CON VID pg 4 VA X SAM 4 11 PORT gt RE DNP aad D gt SAIO_DATA3 pot poii3 PORT Bi gt 4 CANO 9 i 10 gt gt SAM DATAO 4 I Sar gt CON VID DATA7 4 PORT A4 4 R36 0 HE 2D 840 SYNG at 11 13 PORT B2 SAS 10 R74 0 DNP 75 OHM 1 2 gt gt CON VID po 4 cb dm gt gt 4 PORT 5 y R Reo 0 aN XSAN SYNC pg 11 13 PORT BS a 10 Res DNP 10 AVV gt gt ETC2 14
29. 12 2011 1 HDR 1X2 TH oo CAN interface PIN QV CAN V 1 2 d os 71 es 0 1UF 1000PF CAN 12V 12 1 w 1 csi 1 1000 1 1 33V 7 2 T 53 C516 C515 F E GND 1000PF lo Ji4 1 2 us 958 2 888 ERR D M CANH H2 CANA CANH ide CANACANL 2 H 2 22 ino GND lt RXD spur 1 Roo 3 as S im o 604 60 4 EN A TATORT y HDR 1X2 TH C510 GND 0 01UF 33V d GND 1 2 oo 9 GND 3 4 519216 7 2 freescale semiconductor ICAP Classification FCP FIUO x Drawing Titi MPC5604 EVB Page Title CAN PHYSICAL INTERFACE Size Document Number c SCH 27073 PDF SPF 27073 Date Wednesday October 12 201 Sheet 9 of LIN Interface SCI Interface J2 Master Mode Pullup Enable
30. 4EEVB64 Evaluation board User Manual Rev 0 4 Freescale Semiconductor Configuration 4 5 Power Status LEDs and Fuse When Power is applied to the EVB the Green Power LEDs adjacent to 5 V and 3 3 V of the voltage reg ulators show the presence of the supply voltage Green LED D9 3 3 V for EVB supply Green LED D16 5 V for EVB supply If there is no power to the MCU it is possible that either power switch SW1 is in the OFF position or that the fuse F1 has blown The fuse will blow if power is applied to the EVB in reverse bias where a protection diode ensures that the main fuse blows rather than causing damage to the EVB circuitry If the fuse has blown check the bias of your power supply connection then replace fuse F1 with a 20 mm 2 A fast blow fuse 4 6 supply routing and Jumpers J16 J18 J19 J20 J23 The EVB is designed to run the MCU at two supported regulation modes Internal regulation mode In this mode the I O supply Ballast supply and ADC supply are at the same potential of typical 3 3 V 10 To reduce power dissipation on the chip the possibilities of connecting the I O supply with the Ballast supply via a small resistor 2 5 Q is being explored This will lead to the Ballast supply being lower than the I O supply Pads Pins Te vss 100 X Vdd HV 100 X Vdd HV S Ballast0 1 Pi LT A 33V POR B Vdd LV REGCORO Vdd LV CORO X ao 3 supply
31. Freescale Semiconductor User Manual Document Number MPC5604EEVB64UM MPC5604EEVB64 Evaluation board User Manual For MPC5604E Evaluation Validation by Pavel Bohacik MSG Application Engineering 1 Introduction The MPC5604EEVB64 Evaluation Board EVB is based on the e200z0 Power Architecture This board is shipped with the 5604 64 pin LOFP MCU populated to allow the evaluation ofthe full functionality of this part This board is designed as a validation platform with the maximum flexibility Where possible it is also designed for power and speed but the primary goal of this system is to allow main usecases of this processor 2 References e MPC5604ERM Reference Manual e 5604 Data Sheet Freescale Semiconductor Inc 2011 All rights reserved gt Contents 1 REICICNESS 1 EVB ESSI BS ode dee comes 2 Configuratii siaaa ipi gnia d kadit hindad eika 2 Default Jumper Summary Table 16 User Connector 18 Bugs 26 Vey oe 2 freescale semiconductor EVB Features 3 EVB Features The following is a list of evaluation board features MPC5604E External Interfaces 4 Video Encoder Wrapper connected to Omnivision connector Serial Audio Interface connected to the Audio connector Onboard Ethernet physical interface plus
32. XD2 5 o 0 678 JTAG RSTB gt 15 RESET 8 14 lt re 7 EXTAL E 13 g u 25 XTAL XTAL 8 gt 2 35 2 R512 100 43 T00 E g 8 zz 41 TCK 2 gg pole 5 TMS 9 a 98 pgs TDI 2 asl Sao PW ON RESET Miar 4 55 2 583 7 8 PW z 9 lt gt gt gt gt gt gt gt gt gt NMLB 14 Sa Sq er oo wo ooo 8 98 98 000 gt Le FFS 88 amp 1501 VSSA 6000HM GND VSSA VDD_ADR alib 77 m 2 freescale semiconductor L500 6000HM ICAP Classification FOP FIUO Pug X Drawing Title MPC5604 EVB Page Title soc Size Document Number Rev SCH 27073 PDF SPF 27073 Date 1i of 13 Wednesday October 12 2011 1 User LED s 33V HDR 1X1 YELLOW LED RNB 5 c 4 1 8 2 7 i PH 49 9 49 9 HDR 1X1 YELLOW LED NSD 5 4 3 6 4 5 l see 49 9 499 HDR 1X1 YELLOW LED 6 x A 1 8 2 7 1 Pie 499 RN6B 499 HDR 1X1 YELLOW LED 3 6 4 5 Je 499 RN6D 499 LED s are SMD 1206 Yellow HDR TH 1X3 33V 342 GND ooo gt R542 10 0K HDR 1X1 dua a 2 JP22 ___ SPST NO GND gt R54 10 0K HDR 1X1 w
33. e LIN slave mode can be enabled by removing jumper J2 4 13 Ethernet 4 13 1 Ethernet Physical Interface J22 The EVB is fitted with a National Semiconductor DP83848C Ethernet physical interface U10 and a RJ45 connector with integrated activity LEDs and magnetics 724 The National Semiconductor DP83848C physical interface is connected to the MII on the MPC5604E This is a fixed connection with no means of isolation Pullups are also present on some of these signals These are detailed in the table below Please be aware of this when using the related GPIOs Table 8 Pull up Pull down resistors for Ethernet Physical Port Pin Pull Direction Strength FEC_CRS Down GND 22 FEC RX ER Down GND 22 FEC RX DV Down GND 22 FEC RXDO Down GND 22 MPC5604EEVB64 Evaluation board User Manual Rev 0 14 Freescale Semiconductor Configuration Table 8 Pull up Pull down resistors for Ethernet Physical Port Pin Pull Direction Strength FEC RXD1 Down GND 22 RXD2 Down GND 22 FEC RXD3 Down GND 22 FEC TX EN Down GND 22 FEC TXDO Down GND 22 FEC TXD1 Down GND 22 FEC TXD2 Down GND 22 FEC TXD3 Down GND 22 FEC MDC Up 3 3 V 1 5 KQ FEC MDIO PHY Up 3 3 V 1 5 The voltage domain that is used by the GPIO should be set to 3 3 V when power is applied to the physical interface Power can be r
34. emoved from the physical interface via J22 Table 9 Ethernet Physical Interface Power Supply Enabled J22 Jumper Position PCB legend Description J22 PHY PWR REMOVED FITTED D PHY PWR The DP83848C Ethernet Physical Interface is powered from the 3 3 V SR The DP83848C Ethernet Physical Interface is not powered 4 13 2 Ethernet connector 449 An universal 40 pin Connector is also provided on the board to provide possibility to connect customer Ethernet Physical Interface to MPC5604E interface signals Since this connector is normally used by the Ethernet PHY daughter cards of standard PHY vendors this provides a flexibility of supporting validation with multiple PHY vendors Connector pin definition is located in the Section 6 1 FEC J33 J49 below Following resistors must be populated to enable connection between 5604 and connector on board MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 15 Configuration Table 10 Resistor configuration for MPC5604E MII interface routed to MII connector Resistor to DE Value Description populated R62 00 FEC TX CLK routed to FEC TX CONN R60 00 FEC TX EN routed to TX CONN R58 00 FEC TXDO routed to FEC_TXDO_CONN R56 00 FEC TXD1 routed to TXD1 CONN R54 00 FEC TXD2 routed to TXD2 CONN R53 00 FEC_TXD3 rou
35. ere is also a global power jumper J3 controlling the power to the RS232 transceiver Table 6 RS232 Control Jumpers Jumper Position Description J3 FITTED D Power is applied to the SCI PWR MAX3223 transceiver No power is applied to the REMOVED MAX3223 transceiver J7 2 3 D MCU TXD is routed to MAX3223 MCU TXD signal is REMOVED disconnected from RS232 LIN MCU is routed to MAX3223 signal is disconnected from RS232 LIN J8 2 3 D REMOVED The default configuration enables SCI RS232 compliant interfaces with no hardware flow control are available at DB9 connector P2 If the MCU is configured such that SCI is set as a normal I O port then MPC5604EEVB64 Evaluation board User Manual Rev 0 12 Freescale Semiconductor Configuration the relevant jumpers must be removed to avoid any conflicts occurring If required jumper J3 be used to completely disable the SCI transceiver 4 12 LIN Configuration J2 J5 J7 48 The EVB is fitted with one Freescale MCZ33661EF LIN transceiver The LINFlex module incorporates a UART mode and as such the LIN transceiver are connected to the TX and RX signals of SCI via UART For flexibility the LIN transceiver 1 connected to a standard 0 1 connector P7 and to one pin molex connector J1 at the top edge of the PCB as shown in the figure below For ease of use the 12 V EVB supply is fed to pinl of the P7 header and t
36. he LIN transceiver power input to pin 2 This allows the LIN transceiver to be powered directly from the EVB supply by simply linking pins 1 and 2 of header P7 using a 0 1 jumper shunt Ensure P7 is added before running LIN as it is not the default on the EVB 1 VDD UNREG LIN VSUP LIN GND LIN Figure 10 LIN physical Interface Connector P7 Along with the MCU signal routing jumpers J7 J8 there is jumper J5 to enable or disable the LIN transceiver and jumper J2 which determines if the LIN transceiver is operating in master or slave mode as defined in the table below MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 13 Configuration Table 7 Jumper Position Description J2 FITTED LIN transceiver is configured for LIN Master mode LIN transceiver is configured for LIN Slave mode REMOVED D 5 FITTED D The LIN transceiver is enabled The LIN transceiver is disabled MCU LIN TXD is connected to SCI TX MCU LINO TXD is connected to LIN Physical LIN RXD is connected to SCI TX LIN RXD is connected to LIN Physical REMOVED J7 2 3 D 1 2 J8 2 3 D 1 N Jumper J5 do not route power to LIN transceivers they only control an enable line on the LIN device Power to the LIN transceiver is supplied via connector P7 Pin 2 The Default LIN configuration is with the module enabled in master mod
37. in Jumper Position Description 1 2V J18 1 2 D This supplies VDD LV VDD LV supply pins 3 3V J19 2 3 D This supplies V BALLAST IN VDD S BALAST supply 3 3V J20 2 3 D VDD S BALAST routed via V BALLAST HDR BALAST resistor 3 3V J16 1 2 D This supplies VDD HV VDD HV supply pins 3 3V J23 1 2 D ADC reference voltage 3 3 V VDD HV ADR The jumper configuration shown in Table 2 details the default state D of the EVB In this configuration all power supplied from the regulators 47 MCU clock control Main Clock Selection J30 J31 432 J34 EVB supports three possible MCU clock sources The local 25 MHz oscillator circuit Y2 e 8 MHz Oscillator module Y 1 on the EVB driving the MCU EXTAL signal e An external clock input to the EVB via the SMA connector driving the MCU EXTAL signal The clock circuity is shown in the diagram below Please refer to the appropriate EVB schematic for specific jumper numbers and circuity MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor 7 Configuration 3 3V EVB Clock Circuity Local Crystal Circuit Y2 Figure 6 EVB Clock Selection Table 3 Table Clock source jumper selection J30 J31 J32 J34 Jumper Position PCB Legend Description J34 Y1 PWR FITTED D EVB oscillator module Y1 is powered REMOVED EVB oscillator module Y1 is not powered J32 OSC SEL 1 2 EXTAL SMA SMA externa
38. l square wave input 2 3 D OSC MOD 8 MHz Oscillator is routed from Y1 J30 1 2 Y2 MCU clock is Y2 XTALIN Must Match J31 2 3 D GND GND J31 1 2 D EVB EXTAL MCU clock is selected by Must Match J30 J68 2 3 Y2 MCU clock is Y2 XTALOUT MPC5604EEVB64 Evaluation board User Manual Rev 0 Freescale Semiconductor Configuration NOTE The MPC5604E clock circuity is 3 3 V based Any external clock signal driven into the SMA connector must have a maximum voltage of 3 3 V 4 8 Reset Boot Configuration J44 J46 J47 The MPC5604E has 3 boot configuration jumpers BOOTCFG that determine the boot location of the MCU based at POR Power On Reset This is shown in the Table 4 Table 4 BOOTCFG Control J47 FAB J44 ABSO J46 ABS2 Boot ID Boot Mode 1 2 2 3 2 3 Serial Boot LinFlex without autobaud 1 2 1 2 2 3 Serial Boot FlexCAN without autobaud 1 2 2 3 1 2 Serial Boot via LinFlex or FlexCAN autobaud 2 3 Valid SC Single Chip 2 3 Not Valid Safe Mode 4 9 NEXUS The EVB supports a standard JTAG cable with a 14 pin 0 1 walled header footprint 4 9 1 Debug Connector Pinouts The EVB is fitted with 14 pin JTAG connector The following diagram shows the 14 pin JTAG connector pin out 0 1 keyed header TDI 1 2 VSS TDO3 4 VSS TCLK5 6 VSS RESET 9 10 TMS VDDE2 11 12 VSS RDY 13 14 JCOMP Figure 7 MPC5604E JTAG Connector MPC5604EEVB64 Eval
39. or 25 Known Bugs List Table 23 Routing IIC1 to Video Connector video usecase Signal description Jumper Reference Configuration Description 1 clock J27 1 2 Port A13 routed to J28 J28 1 2 CLK signal is selected for Video clock 1 data J36 1 2 Port A14 routed to J37 J37 1 2 DATA signal is selected for Video data Table 24 Routing 0 to Audio Connector audio usecase Signal description Jumper Reference Configuration Description 0 clock 425 2 3 Port C5 routed to J39 as signal J39 2 3 signal selected for Audio clock 0 data 426 2 3 Port C6 routed to J40 as DATA signal J40 2 3 DATA signal selected for Audio data Table 25 Routing IIC1 to Video Connector audio usecase Signal description Jumper Reference Configuration Description 0 clock 427 2 3 signal is selected for audio clock 0 data J36 2 3 IIC1 DATA signal is selected for audio data 7 Known Bugs List None 8 Schematic Diagrams This section shows the schematic diagram of the MPC5604EEVB64 Following are the topics covered in the schematic MPC5604EEVB64 Evaluation board User Manual Rev 0 26 Freescale Semiconductor Table 26 Schematic sections Power section Sheet 2 Resistor MUX Sheet 3
40. or products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer
41. stor and capacitor to be Value Description populated R31 100 PORT 9 routed to CON VID DATA5 R45 100 PORT A10 routed to CON VID DATA4 R47 100 PORT 11 routed to CON VID DATA3 R49 100 PORT A12 routed to CON VID DATA2 R77 100 PORT A15 routed to VID PWDN L6 750 PORT CA routed to Most of the Omnivision camera evaluation boards are configured via I2C interface For this purpose J27 J28 J39 and J37 should be connected correctly For pin definitions see Section 6 8 I2C clock selection 727 J28 736 J37 J39 140 4 14 1 Audio Connector EVB has a possibility to connect Sahara SGTL5000 daughter card to Audio connector J48 Audio signals are routed to Serial Audio Interface module of MPC5604E Connector pin definition is located in the Section 6 3 Audio J48 below Following resistors and capacitors have to be populated to enable connection between 5604 and Audio connector on board Table 12 Resistor and capacitor to be Value Description populated R64 00 PORT C3 routed to ETC1 R66 00 PORT 2 routed to ETCO R32 00 PORT 0 routed to SAIO_DATAO R25 00 PORT 1 routed to SAIO DATA1 R34 00 PORT A2 routed to SAIO DATA2 R27 00 PORT routed to SAIO_DATA3 R36 00 PORT A4 routed to SAIO SYNC R29 00 PORT 5 routed to 5 1 SYNC R38 00 PORT A6 routed to SAI2 SYNC R40 00 PORT routed to SAIO_BCLK R42 00 PORT 8 routed to 5 12 DATAO R30 0
42. ted to TXD3 CONN R82 00 FEC RXD3 routed to RXD3 CONN R84 00 FEC RXD2 routed to RXD2 CONN R86 00 FEC RXD1 routed to RXD1 CONN R88 00 FEC RXDO routed to RXDO CONN R90 00 DV routed to FEC RX DV CONN R92 00 FEC RX CLK routed to FEC RX CLK CONN R94 00 FEC MDIO routed to MDIO CONN 4 14 Video Connector J45 EVB has a possibility to connect Camera module to Video connector J45 Camera signals are then routed to the Video Encoder Wrapper module of MPC5604E Video connector fits to standard connector used on Omnivision camera evaluation boards Connector pin definition is located in the Section 6 4 VIDEO 345 below Following resistors and capacitors have to be populated to enable connection between 5604 and Video connector on board Table 11 Resistor and capacitor to be Value Description populated R33 100 PORT 0 routed to CON VID DATA11 R26 100 PORT 1 routed to CON VID DATA10 R35 100 PORT 2 routed to CON VID DATA9 R28 100 PORT routed to CON VID DATA8 R37 100 PORT A4 routed to CON VID L4 750 PORT A65 routed to VID CLK R39 100 PORT A6 routed to CON VID VSYNC R41 100 PORT routed to CON VID HSYNC R43 100 PORT A8 routed to CON VID DATAG MPC5604EEVB64 Evaluation board User Manual Rev 0 16 Freescale Semiconductor Configuration Table 11 Resi
43. uation board User Manual Rev 0 Freescale Semiconductor 9 Configuration NOTE In order to preserve the ability to accurately measure power consumption of the MCU pins the JTAG connector reference voltages will be sourced directly from the 3 3 V regulator 4 10 Configuration J10 J11 J12 J6 49 The EVB has NXP TJA1041T high speed CAN transceiver the MCU CAN channel This operate with 3 3 V I O from the MCU For flexibility the CAN transceiver I O is connected to a standard 0 1 connector and DB9 connector at the top edge of the PCB Connectors P6 and P3 provides the CAN bus level signal interface for CAN A The pin out for these connectors is shown below CANA CANH CANA CANL Figure 8 CAN physical interface connector MPC5604EEVB64 Evaluation board User Manual Rev 0 10 Freescale Semiconductor Configuration Table 5 CAN Control Jumpers J10 J11 J12 J6 J9 Jumper Position PCB Legend Description J11 FITTED D e 5V is applied to CAN transceiver VCC REMOVED No5V power is applied to CAN transceiver J12 FITTED D 12V Power is applied to CAN transceiver VBAT No 12 V power is applied REMOVED to CAN transceiver J6 FITTED D TX MCU CAN TXD is connected to CAN controller REMOVED MCU CAN TXD is NOT routed to CAN controller J10 FITTED D RX MCU CAN RXD is connected to CAN controller REMOVED MCU CAN RXD is NOT routed to CAN controller
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