ISL54206AIRTZ-T
Contents
1. L10 2 1x1 6A 10 LEAD ULTRA THIN QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 5 3 10 PIN 1 INDEX AREA 2 10 HA PIN 1 ID 0 05 MIN Br N gu 4X 0 20 MIN 8 T 10 l 0 80 I 10X 0 40 oA 2 9 i 6 6050 10 X 0 20 4 TOP VIEW CI AIB BOTTOM VIEW Mic SEE DETAIL X semp P PACKAGE MAX 0 55 i OUTLINE 10X 0 60 0 10 c 0 10 MIN SEATING PLANE 0 08 2 00 2 00 0 SIDE VIEW 1 30 125 REF 6X 0 50 yb l 2 50 Mm TYPICAL RECOMMENDED LAND PATTERN DETAIL X NOTES 1 Dimensioning and tolerancing conform to ASME Y14 5M 1994 2 All Dimensions are in millimeters Angles are in degrees Dimensions in for Reference Only 3 Unless otherwise specified tolerance Decimal 0 05 Lead width dimension applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip 5 Maximum package warpage is 0 05mm 6 Maximum allowable burrs is 0 076mm in all directions 7 Same JEDEC MO 255UABD except No lead pull back MIN Package thickness 0 45 not 0 50mm Lead Length dim 0 45mm max not2. 0 11 0 4 Ri 320 320 0 707VnMs Vpp 3V 0 10 0 3 REPRE M Y 0 09 2 6 2 2 0 08 z E 0 2 a T 0 07 AA D wn Vpp 2 7 E 2 5Vp p Vpp 3 6 Vpp 3V 2Vp p 0 05 1 0 04 0 20 200 2k 20k 20 200 20k FREQUENCY Hz FREQUENCY Hz FIGURE 8 THD N vs SUPPLY VOLTAGE vs FIGURE 9 vs SIGNAL LEVELS vs FREQUENCY FREQUENCY 0 5 0 5 r 320 320 1 2 FREQ 1 2 V 3V v DD 0 4 D 5 m 5 2 2 z 2 4 0 2 0 2 0 1 0 1 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 0 10 20 30 40 50 OUTPUT VOLTAGE Vp p OUTPUT POWER mW FIGURE 10 THD N vs OUTPUT VOLTAGE FIGURE 11 THD N vs OUTPUT POWER FN6515 3 12 intersil October 28 2010 ISL54206A Typical Performance Curves TA 25 Unless Otherwise Specified Continued D D Signals V VOLTAGE SCALE 0 5V DIV 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 gt Time 10 8 5 TIME SCALE 10ns DIV FIGURE 12 EYE PATTERN 12MBps WITH SWITCHES IN THE SIGNAL PATH 13 intersil FN6515 3 October 28 2010 ISL54206A Typical Performance Curves TA 25 Unless Otherwise Specified Continued 40 3 5 2 5 tn D D Signals V o VOLTAGE SCALE 0 5V DIV 0 0 1 0 20 3 0 40 50 6 0 70 8 0 gt Time 10 8 5 TIME SCALE 10ns DIV FIGURE 13 EYE PATTERN 12MBps WIT
3. 0 85V to 0 85V Note 14 Flatness RFLAT ON VDD 3 0V IN 0 5V CTRL 1 4V Icomx 40mA 25 0 03 0 05 VL or Vg 0 85V to 0 85V Note 13 Full _ 0 07 4 intersil FN6515 3 October 28 2010 ISL54206A Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV 1 4V VINL 0 5V VcTRLH 1 4V 0 5V Note 11 unless otherwise specified Boldface limits apply over the operating temperature range 40 C to 85 C Continued TEMP MIN MAX PARAMETER TEST CONDITIONS C Notes 12 15 Notes 12 15 UNITS Discharge Pull Down Vpp 3 6V IN CTRL 3 6V or 25 50 Resistance RR Vcom 0 85V 0 85V VL or Vg 0 85V 0 85V Vp and Vp floating Measure current through the discharge pull down resistor and calculate resistance value USB Switches D D Analog Signal Range Vpp 3 6V IN 1 4V CTRL 1 4V Full 0 VDD V VANALOG ON Resistance ron Vpp 5 0V IN Vpp CTRL Vpp Icomx 1mA 25 17 7 Vp or Vp 5V See Figure 4 ON Resistance ron Vpp 4 2V IN Vpp CTRL Vpp Icomx 1mA 25 19 5 Vp or Vp 4 2V See Figure 4 ON Resistance ron Vpp 2 85V IN Vpp CTRL Vpp Icomx 1mA 25 26 Vp or Vp 2 85V See Figure 4 ON Resistance ron Vpp 3 3V
4. Peak Current USB Switches Pulsed ims 10 Duty Cycle 100mA ESD Rating Human Body gt 7kV Machine Model gt 400V Charged Device gt 1 4kV Latch up Tested JEDEC Class LevelA at 85 C Thermal Information Thermal Resistance Typical 034 C W C W 10 Ld uTQFN Notes 7 8 145 90 10 Ld TDFN Notes 9 10 55 16 Maximum Junction Temperature Plastic Package 150 C Maximum Storage Temperature Range 659 to 150 Pb Free Reflow Profile see link below http www intersil com pbfree Pb FreeReflow as Operating Conditions Temperature 40 C to 85 C CAUTION Do not operate at or near the maximum ratings listed for extended periods of time Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTES 6 Signals on D D L R COM COM CTRL IN exceeding Vpp or GND by specified amount are clamped Limit current to maximum current ratings 7 03A is measured with the component mounted on a high effective thermal conductivity test board in free air See Tech Brief TB379 for details 8 For 05c the case temp location is taken at the package top center 9 0jA is measured in free air with the component mounted on a high effective thermal conductivity t
5. ISL54206A Switches shown for IN Logic 0 and CTRL Logic 1 Truth Table Pin Descriptions ISL54206A ISL54206A IN CTRL L R D D PIN FUNCTION 0 0 OFF OFF 1 VDD Supply 0 1 ON OFF 2 IN Digital Control Input 1 X OFF ON 3 COM Voice and Data Common Pin IN Logic 0 when lt 0 5V Logic 1 when 21 4V with 2 7V to 4 COM Voice and Data Common Pin Mp when lt 0 5 or Floating Logic 1 when 21 4V 3 GND Ground Connection with 2 7V to 3 6V supply 6 R Audio Right Input 7 L Audio Left Input 8 D USB Differential Input 9 D USB Differential Input 10 CTRL Digital Control Input Audio Enable PD Pad Tie to Ground or Float TDFN package only 2 intersil FN6515 3 October 28 2010 ISL54206A Ordering Information PART NUMBER PART TEMP RANGE PACKAGE PKG Note 5 MARKING C Pb Free DWG ISL54206AIRTZ Note 3 06AZ 40 to 85 10 Ld 3mmx3mm TDFN L10 3x3A ISL54206AIRTZ T Notes 2 3 O6AZ 40 to 85 10 Ld 3mmx3mm TDFN Tape and Reel L10 3x3A ISL54206AIRUZ T Notes 2 4 40 to 85 10 Ld 2 1mmx1 6mm yTQFN Tape Reel L10 2 1x1 6A ISL54206AEVAL1Z Evaluation Board NOTES 2 Please refer to TB347 for details on reel specifications 3 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds
6. 0 42mm The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature FN6515 3 October 28 2010 19 intersil ISL54206A Package Outline Drawing L10 3x3A 10 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE 1 gt e v gt D Rev 5 3 10 2 0 REF 3 00 A PIN 1 INDEX AREA 8X 0 50 BSC B 1 A s PIN 1 J UJ 10X 0 30 INDEX AREA 300 T m M B 1 50 S L 1 0 15 2 4 ONN 0 10 W C a 10 5 05 MC 10 0 25 TOP VIEW 2 30 230 2 30 BOTTOM VIEW 0 80 MAX SEE DETAIL XE 4 010C 2 90 Y E SEATING PLANE F 1 50 0 08 C SIDE VIEW bod 10 X 0 50 Lo H HH 0 2REF 8X 0 50 1 7 4 L 10X 0 25 1 0 00 MIN 0 05 MAX TYPICAL RECOMMENDED LAND PATTERN DETAIL X NOTES Dimensions are in millimeters Dimensions in for Reference Only Dimensioning and tolerancing conform to ASME Y14 5m 1994 Unless otherwise specified toleranc
7. IN 1 4V CTRL 1 4V 1mA 25 23 5 30 Vp or Vp 3 3V See Figure 4 Full E 35 ON Resistance ron Vpp 3 6V IN 1 4V CTRL 1 4V 40mA 25 4 6 5 Q Vp or Vp OV to 400mV See Figure 4 Full a 6 5 Matching Between Vpp 3 6V IN 1 4V CTRL 1 4V Icom 40mA 25 0 06 0 5 Channels Aron Vp or Vp Voltage at max Roy over signal range Full 0 55 of OV to 400 Note 14 i ron Flatness RFLaT on 3 6V IN 1 4V CTRL 1 4V 25 0 4 0 6 Q Icomx 40mA Vp or Vp OV to 400 Full E 1 0 13 OFF Leakage Current Vpp 3 6V IN OV CTRL 3 6V Vcom or 25 10 10 nA 1D OFF or Ip OFF Vcom 0 5V OV VD or Vp OV 0 5V VL and Full 70 70 nA Vg float ON Leakage Current Ipy Vpp 3 3V IN 3 3V CTRL OV or 3 3V Vp 25 30 8 30 nA or Vp 2 0V and Vg float Full 300 300 nA DYNAMIC CHARACTERISTICS Turn ON Time ton Vpp 2 7V 500 Cj 10pF See Figure 1 25 67 ns Turn OFF Time torr Vpp 2 7V 500 10pF See Figure 1 25 48 ns Break Before Make Time Vpp 2 7V 500 C 10pF See Figure 2 25 18 ns Delay tp Skew tskgw 3 3V IN 3 3V CTRL OV or 3 3V 25 50 ps R 450 C 10pF tr 750ps at 480Mbps Duty Cycle 50 See Figure 7 Total Jitter tj Vpp 3 3V IN 3 3V CTRL or 3 3V 25 210 ps RL
8. headphone connected at the COM pins Table 1 shows the negative voltage generated at the D D lines as you increase the audio amplitude across the headphone load TABLE 1 AUDIO SIGNAL D D VOLTAGE V AMPLITUDE 25 C 85 C 800 0 22 0 27 880 0 24 0 3 1 08Vp p 0 3 0 34 2Vp p 0 41 0 44 2 25Vp p 0 47 0 5 4Vp p 0 83 0 85 The USB specification USB Specification Rev 2 0 Chapter 7 Section 7 1 1 states that a USB transceiver must be able to tolerate a 1V signal at its D D differential inputs The data in the table shows that the 1V level is never exceeded during audio operation and should have no impact on the long term reliability of the USB transceiver ISL54206A Operation The following discussion discusses using the ISL54206A in the typical application shown in the block diagrams on page 9 Vpp SUPPLY The DC power supply connected at VDD pin 1 provides the required bias voltage for proper switch operation The part can operate with a supply voltage in the range of 2 5V to 5 5V In a typical USB Audio application for portable battery powered devices the Vpp voltage will come from a battery or an LDO and be in the range of 2 7V to 3 6V For best possible USB full speed operation 12Mbps it is recommended that the Vpp voltage be 22 5V in order to get a USB data signal level above 2 5V LOGIC CONTROL The state of the ISL54206A device is determined by
9. high impedance When nothing is plugged into the common connector or a headphone is plugged into the common connector the will sense that there is no voltage at the VBUS pin of the connector and will drive and hold the IN control pin of the ISL54206A low As long as the CTRL Logic 1 the ISL54206A part will be in the audio mode and the audio drivers of the media player can drive the headphones and play music USB Mode If the IN pin Logic 1 and CTRL pin Logic 0 or Logic 1 the part will go into USB mode In USB mode the D and D 50 switches are ON and the L and R audio switches are OFF high impedance When a USB cable from a computer or USB hub is connected at the common connector the uprocessor will sense the presence of the 5V VBUS and drive the IN pin voltage high The ISL54206A part will go into the USB mode In USB mode the computer or USB hub transceiver and the MP3 player or cell phone USB transceiver are connected and digital data will be able to be transmitted back and forth When the USB cable is disconnected the uprocessor will sense that the 5V VBUS voltage is no longer connected and will drive the IN pin low and put the part back into the Audio or Low Power Mode Low Power Mode If the IN pin Logic 0 CTRL pin Logic 0 the part will be in the Low Power mode In the Low Power mode the audio switches and the USB switches are OFF high impedance In th
10. normal USB operation Vpp is in the range of 2 7V to 3 6V and IN Vgus voltage from computer or USB hub is in the range of 4 4V to 5 25V the clamp circuit is not active and no current will flow through the clamp into the Vpp supply In a USB application the situation can exist where the Vpgus voltage from the computer could be applied at the IN pin before the Vpp voltage is up to its normal operating voltage range and current will flow through the clamp into the Vpp power supply bus This current could be quite high when Vpp is OFF or at OV and could potentially damage other components connected in the circuit In the application circuit a 22kO resistor has been put in series with the IN pin to limit the current to a safe level during this situation It is recommended that a current limiting resistor in the range of 10kQ to 50kQ be connected in series with the IN pin It will have minimal impact on the logic level at the IN pin during normal USB operation and protect the circuit during the time is present before Vpp is up to its normal operating voltage Note No external resistor is required in applications where the voltage at the IN pin will not exceed Vpp by more than 2 55V 11 intersil FN6515 3 October 28 2010 ISL54206A Typical Performance Curves TA 25 C Unless Otherwise Specified
11. reference stereo signals with minimal insertion loss and very low distortion Crosstalk between the audio switches over the audio band is 110dB Over a signal range of 1V 0 707Vpms with Vpp gt 2 7V these switches have an extremely low resistance variation They can pass ground referenced audio signals with very low distortion 0 0696 THD N when delivering 15 6mW into a 320 headphone speaker load See Figures 8 Figures 9 Figures 10 and Figures 11 THD N performance curves These switches are uni directional switches The audio drivers should be connected at the L and R side of the switch pin 7 and pin 8 and the speaker loads should be connected at the COM side of the switch pin 3 and pin 4 The audio switches are active turned ON whenever the IN voltage is lt 0 5 and the CTRL voltage to 1 4V Note Whenever the audio switches are ON the USB transceivers need to be in the high impedance state or static high or low state USB Switches The two USB switches D D are bidirectional switches that can pass rail to rail signals When powered with a 3 6V supply these switches have a nominal row of 4 60 over the signal range of OV to 400mV with a row flatness of 0 40 The roy matching between the D and D switches over this signal range is only 0 060 ensuring minimal impact by the switches to USB high speed signal transitions As the signal level increases the ron resistance increases At signal level of 3
12. the voltage at the IN pin pin 2 and the CTRL pin pin 10 Refer to Truth Table on page 2 These logic pins are 1 8V logic compatible when Vpp is in the range of 2 7V to 3 6V and can be controlled by a standard The CTRL pin is internally pulled low through resistor to ground and can be left floating or tri stated by 10 intersil FN6515 3 October 28 2010 ISL54206A the uprocessor The CTRL control pin is only active when IN is logic 0 The IN pin does not have an internal pull down resistor and must not be allowed to float It must be driven High or Low The voltage at the IN pin can exceed the Vpp voltage by as much as 2 55V This allows the Vays voltage from a computer or USB hub 4 4V to 5 25V to drive the IN pin while the Vpp voltage is in the range of 2 7V to 3 6V An external pull down resistor is required from the IN pin to ground when directly driving the IN pin with the computer VBUS voltage See USING THE COMPUTER VBUS VOLTAGE TO DRIVE THE IN PIN on page 11 Logic Control Voltage Levels IN Logic 0 Low when IN lt 0 5V IN Logic 1 High when IN gt 1 4 CTRL Logic 0 Low when lt 0 5 or floating CTRL Logic 1 High when gt 1 4 Audio Mode If the IN pin Logic 0 and CTRL pin Logic 1 the part will be in the Audio mode In Audio mode the L left and R right audio switches are ON and the D and D 50 USB switches are OFF
13. 3V the switch resistance is nominally 230 The USB switches were specifically designed to pass USB 2 0 high speed 480Mbps differential signals typically in the range of OV to 400mV They have low capacitance and high bandwidth to pass the USB high speed signals with minimum edge and phase distortion to meet USB 2 0 high speed signal quality specifications See high speed eye diagram Figure 15 The USB switches can also pass USB full speed signals 12Mbps with minimal distortion and meet all the USB requirements for USB 2 0 full speed signaling See the full speed eye diagrams Figures 12 thru 14 The maximum signal range for the USB switches is from 1 5V to Vpp The signal voltage at D and D should not be allowed to exceed the Vpp voltage rail or go below ground by more than 1 5V The USB switches are active turned ON whenever the IN voltage is 21 4V Note Whenever the USB switches are ON the audio drivers of the CODEC need to be at AC or DC ground or floating to keep from interfering with the data transmission USB Switch Cell Off Isolation Due to the unique internal architecture of the ISL54206A part the USB switch cell has limited off isolation to a negative signal at the COM side of the part When driving an audio signal into the L and R inputs a small negative voltage will appear at the D and D lines as the audio signal transitions below ground With a USB transceiver connected at the D D pins and with a 320
14. 450 10pF 750ps at 480Mbps Propagation Delay tpp Vpp 3 3V IN 3 3V CTRL OV or 3 3V 25 250 x ps 450 10pF See Figure 7 Crosstalk Vpp 3 3V IN OV CTRL 3 3V 320 25 110 dB Channel to Channel f 20Hz to 20kHz or Vi 0 707VnMs R to COM L to COM 2Vp p See Figure 6 Total Harmonic Distortion f 20Hz to 20kHz Vpp 3 0V IN OV CTRL 25 0 06 VL or Vg 0 707 2Vp p RL 320 USB Switch 3dB Signal OdBm 0 2Vpc offset RL 509 Cj 5pF 25 630 MHz Bandwidth D D OFF Capacitance f 1MHz Vpp 3 3V IN OV CTRL 3 3V 25 6 Vp or Vp Vcomx OV See Figure 5 5 intersil FN6515 3 October 28 2010 ISL54206A Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV 1 4V VINL 0 5V VcTRLH 1 4V 0 5V Note 11 unless otherwise specified Boldface limits apply over the operating temperature range 40 C to 85 C Continued TEMP MIN MAX PARAMETER TEST CONDITIONS Notes 12 15 Notes 12 15 UNITS L R OFF Capacitance f 1MHz Vpp 3 3V IN CTRL OV or 25 9 pF CROFF 3 3V VL or Vg Vcomx See Figure 5 COM ON Capacitance f 1MHz Vpp 3 3V IN 3 0V CTRL OVor 25 10 pF Cc
15. H SWITCHES IN THE SIGNAL PATH 14 intersil FN6515 3 October 28 2010 ISL54206A Typical Performance Curves TA 25 Unless Otherwise Specified Continued D D Signals V VOLTAGE SCALE 0 5V DIV gt o 0 0 1 0 20 3 0 40 50 6 0 70 8 0 gt Time 10 8 8 TIME SCALE 10ns DIV FIGURE 14 EYE PATTERN 12MBps WITH SWITCHES IN THE SIGNAL PATH 15 intersil FN6515 3 October 28 2010 ISL54206A Typical Performance Curves Ta 25 C Unless Otherwise Specified Continued VOLTAGE SCALE 0 1V DIV 1 1 1 w N Lal NORMALIZED GAIN dB 1 0 5 0 4 0 3 0 2 0 1 gt Boo 92 D m m 0 2 t 0 3 0 4 0 5 0 0 0 2 0 4 0 6 0 8 1 0 122 1 4 1 6 1 8 2 0 gt Time 10 9 5 TIME SCALE 0 2ns DIV FIGURE 15 EYE PATTERN 480MBps USB SIGNAL WITH SWITCHES IN THE SIGNAL PATH USB SWITCH Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL POWERED UP GND TRANSISTOR COUNT 98 PROCESS Submicron CMOS 50 VIN 0 2Vp p to 2Vp p 1M 10M 100M 1G FREQUENCY Hz FIGURE 16 FREQUENCY RESPONSE 16 intersil FN6515 3 October 28 2010 ISL54206A Revision History The revision history provided is for informational purposes only and is believed to be accurate but not warranted Please go to web to make sure you have th
16. UT FIGURE 7A MEASUREMENT POINTS FIGURE 7 SIGNAL GENERATOR 320 Signal direction through switch is reversed worst case values are recorded Repeat test for all switches FIGURE 6 AUDIO CROSSTALK TEST CIRCUIT VDD 15 80 DIN 1430 15 880 DIN 1430 GND tro tri Delay Due to Switch for Rising Input and Rising Outpu tfi Delay Due to Switch for Falling Input and Falling Outp tskew 0 Change in Skew through the Switch for Output Signa tskew i Change Skew through the Switch for Input Signals FIGURE 7B TEST CIRCUIT SKEW TEST 8 intersil FN6515 3 October 28 2010 ISL54206A Application Block Diagrams USB AND HEADPHONE JACK x Q lt 5 2 r a lt 2 e 7 2 ISL54206A HCONTROLLER USB HIGH SPEED TRANSCEIVER USB HIGH SPEED TRANSCEIVER LOGIC CONTROL VIA VBUS VOLTAGE FROM COMPUTER OR USB HUB Detailed Description The ISL54206A device is a dual single pole double throw SPDT analog switch device that can operate from a single DC power supply the range of 2 5V to 5 5V It was designed to function as a dual 2 to 1 multiplexer to select between USB differential data signals and audio L and R stereo signals It comes in tiny UTQFN and TDFN packages for use in MP3 players PDAs cell phones and other personal media players The part consists of two audio switches and two 5 USB switches The audio switche
17. die attach materials and 100 matte tin plate plus anneal e3 termination finish which is RoHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 4 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and NiPdAu plate e4 termination finish which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 5 For Moisture Sensitivity Level MSL please see device information page for ISL54206A For more information on MSL please see techbrief TB363 3 intersil FN6515 3 October 28 2010 ISL54206A Absolute Maximum Ratings VDD to GND m RE bbe E TER 0 3 to 6 0V Input Voltages D D L R 6 2V to Vpp 0 3V Note 6 222 RR kem a 2V to 5 5V CTRL Note 6 0 3 to Vpp 0 3V Output Voltages COM COM Note 6 2V to Vpp 0 3V Continuous Current Audio Switches 150 Peak Current Audio Switches Pulsed 1ms 10 Duty Cycle Max 300mA Continuous Current USB 40
18. e Decimal 0 05 Angular 2 50 Dimension applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip Tiebar shown if present is a non functional feature The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature Compliant to JEDEC MO 229 WEED 3 except exposed pad length 2 30mm 20 intersil FN6515 3 October 28 2010
19. e between L and or between and D 15 Parameters with MIN and or MAX limits 100 tested at 25 C unless otherwise specified Temperature limits established by characterization and are not production tested 6 intersil FN6515 3 October 28 2010 ISL54206A Test Circuits and Waveforms VDD tr 20ns LOGIC tf 20ns INPUT ov SWITCH INPUT VINPUT 90 SWITCH OUTPUT ov Logic input waveform is inverted for switches that have the opposite logic sense FIGURE 1A MEASUREMENT POINTS VINPUT SWITCH INPUT VOUT Repeat test for all switches C includes fixture and stray capacitance L Vout V INPUT LAS m FIGURE 1B TEST CIRCUIT FIGURE 1 SWITCHING TIMES VDD LOGIC INPUT ov VOUT SWITCH 90 OUTPUT ov eg tD FIGURE 2A MEASUREMENT POINTS CTRL D or D Repeat test for all switches includes fixture and stray capacitance FIGURE 2B TEST CIRCUIT FIGURE 2 BREAK BEFORE MAKE TIME Ron V1 100mA VLORR Repeat test for all switches FIGURE 3 AUDIO Ron TEST CIRCUIT Ron V1 40mA CTRL D OR D Repeat test for all switches FIGURE 4 USB Ron TEST CIRCUIT 7 intersil FN6515 3 October 28 2010 ISL54206A Test Circuits and Waveforms continued VDD CTRL AUDIO OR USB IMPEDANCE ANALYZER OV or VDD Repeat test for all switches FIGURE 5 CAPACITANCE TEST CIRCUIT DIN DIN OUT O
20. e latest Rev DATE 10 19 10 REVISION FN6515 3 CHANGE In USB Switch Cell Off Isolation on page 10 changed 2nd sentence of 2nd paragraph from With a USB transceiver connected at the D D pins and with a 32W headphone to With a USB transceiver connected at the D D pins and with 320 headphone 09 24 2010 FN6515 2 Added section titled USB Switch Cell Off Isolation to page 10 06 15 2010 FN6515 1 On page 1 Added The Land R 50kQ resistors to ground are not shown to Application Block Diagram Removed 2 50kQ resistors which were tied to L and R next to CODEC block Updated Pb free bullet in Features On page 2 Added PD to Pin Descriptions table Updated Pb free notes in Ordering Information per new verbiage based on lead finish Added TB347 link to ordering information for reel specifications On page 4 Added Latch up to Abs Max Ratings Added Theta JC to Thermal Information Changed 10 Ld p TQFN Theta JA from 130 to 145 Changed 10 Ld TDFN Theta JA from 110 to 55 Added applicable Theta JC notes Added standard over temp note to common conditions of spec table Boldface limits apply On page 5 Changed ON Leakage Current Ip room temp and full temp limits from Room temp MIN TYP MAX from 10 2 10nA to 30 8 30nA Full temp MIN MAX from 75 75nA to 300 300nA On page 6 Changed Positive Supply Current IDD Low Power State room temp and full temp limits from Ro
21. est board with direct attach features See Tech Brief TB379 10 For 0jc the case temp location is the center of the exposed metal pad the package underside Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV 1 4V VINL 0 5V VcTRLH 1 4V 0 5V Note 11 unless otherwise specified Boldface limits apply over the operating temperature range 40 C to 85 PARAMETER TEST CONDITIONS TEMP MIN MAX Notes 12 15 Notes 12 15 UNITS ANALOG SWITCH CHARACTERISTICS Audio Switches L R Analog Signal Range Vpp 3 0V IN 0 5V CTRL 1 4V Full 1 5 1 5 V VANALOG ON Resistance Vpp 5 0V IN OV CTRL Vpp Icomx 40mA 25 2 47 VL or Vg 0 85V to 0 85V See Figure 3 ON Resistance Vpp 4 2V IN OV CTRL Vpp 40mA 25 2 50 VL or Vg 0 85V to 0 85V See Figure 3 ON Resistance Vpp 2 85V IN OV CTRL Vpp 40mA 25 2 87 VL or Vg 0 85V to 0 85V See Figure 3 ON Resistance Vpp 3 0V IN 0 5 CTRL 1 4V Icomx 40mA 25 2 65 4 0 VL or Vg 0 85V to 0 85V See Figure 3 Full 5 5 Matching Between Vpp 3 0V IN 0 5V CTRL 1 4V Icomx 40mA 25 0 02 0 13 Channels or Vg Voltage at max ron over signal range of Full 0 16
22. intersil MP3 USB 2 0 High Signal Handling ISL54206A The Intersil ISL54206A dual SPDT Single Pole Double Throw switches combine low distortion audio and accurate USB 2 0 high speed data 480Mbps signal switching in the same low voltage device When operated with a 2 7V to 3 6V single supply these analog switches allow audio signal swings below ground allowing the use of a common USB and audio headphone connector in Personal Media Players and other portable battery powered devices The ISL542064 logic control pins are 1 8V compatible which allows for control via a standard ucontroller With a Vpp voltage in the range of 2 7V to 3 6V the IN pin voltage can exceed the Vpp rail allowing for the USB 5V voltage from a computer to directly drive the IN pin to switch between the audio and USB signal sources in the portable device The part has an audio enable control pin to open all the switches and put the part in a low power state The ISL54206A is available in a small 10 Ld 2 1mmx1 6mm ultra thin UTQFN package and a 10 Ld 3mmx3mm TDFN package It operates over a temperature range of 40 C to 85 C Application Block Diagram ISL54206A LOGIC USB AND HEADPHONE JACK peed Switch with Negative Features High Speed 480Mbps and Full Speed 12Mbps Signaling Capability per USB 2 0 Low Distortion Negative Signal Capability Control Pin to Open all Switches and Enter Low Power State Low Distortion Headph
23. is state the device draws typically 1nA of current USING THE COMPUTER VOLTAGE TO DRIVE THE IN PIN External IN Pull Down Resistor Rather than using a microprocessor to control the IN logic pin you can directly drive the IN pin using the Vays voltage from the computer or USB hub In order to do this you must connect an external resistor from the IN pin to ground When a headphone or nothing is connected at the common connector the external pull down will pull the IN pin low putting the ISL54206A in the Audio mode or Low Power mode depending on the condition of the CTRL pin When a USB cable is connected at the common connector the voltage at the IN pin will be driven to 5V and the part will automatically go into the USB mode When the USB cable is disconnected from the common connector the voltage at the IN pin will be pulled low by the pull down resistor and return to the Audio Mode or Low Power Mode depending on the condition of the CTRL pin Note The voltage at the IN pin can exceed the Vpp voltage by as much as 2 55V This allows the Vays voltage from a computer or USB hub 4 4V to 5 25V to drive the IN pin while the Vpp voltage is in the range of 2 7V to 3 6V External IN Series Resistor The ISL54206A contains a clamp circuit between IN and VDD Whenever the IN voltage is greater than the Vpp voltage by more than 2 55V current will flow through this clamp circuitry into the Vpp power supply bus During
24. oM ON 3 3V Vp or Vp Vcomx See Figure 5 POWER SUPPLY CHARACTERISTICS Power Supply Range Vpp Full 2 5 5 5 V Positive Supply Current Vpp 3 6V IN OV or 3 6V CTRL 3 6V 25 6 8 Ipp Full 2 z 10 Positive Supply Current Vpp 4 2V IN OV or 4 2V CTRL 4 2V 25 6 Ipp Positive Supply Current Vpp 5 0V IN OV or 5 0V CTRL 5 0V 25 8 Ipp Positive Supply Current Vpp 3 6 IN OV CTRL OV or float 25 4 25 nA Ipp Low Power State Full 150 nA DIGITAL INPUT CHARACTERISTICS Voltage Low Vint VcTRLL Vpp 2 7V to 3 6V Full g 0 5 V Voltage High Vpp 7 2 7V to 3 6V Full 1 4 V VCTRLH Input Current Vpp 3 6V IN OV CTRL OV Full 50 20 50 nA Input Current ItNH Vpp 3 6 IN 3 6V CTRL OV Full 50 20 50 Input Current ICTRLH Vpp 3 6V IN CTRL 3 6V Full 2 1 1 2 CTRL Pull Down Resistor Vpp 3 6 IN OV CTRL 3 6 Full 4 RCTRL NOTES 11 Input voltage to perform proper function 12 The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data sheet 13 Flatness is defined as the difference between maximum and minimum value of ON resistance over the specified analog signal range 14 Row matching between channels is calculated by subtracting the channel with the highest max row value from the channel with lowest max valu
25. om temp TYP MAX from 1 7nA to 4 25nA Full temp removed MAX of 140nA Added TYP of 150nA On page 4 to page 6 Updated standard over temp Note 15 in MIN MAX columns of the Electrical Specifications table On page 19 Updated POD L10 2 1X1 6A to most recent revision Changes were Convert to new format by moving dimensions from table onto drawing Corrected leadframe thickness in Detail x from 0 2 REF to 0 125 REF Corrected Note 4 to read between 0 15mm and 0 30mm it previously read between 015mm and 0 30mm Corrected the word indentifier in Note 8 to read identifier On page 20 Updated POD L10 3x3A to most recent revision Changes were to add Typical Recommended Land Pattern amp convert to new format by moving dimensions from table onto drawing no dimension changes 06 25 2007 FN6515 0 Initial Release 17 intersil FN6515 3 October 28 2010 ISL54206A Products Intersil Corporation is a leader in the design and manufacture of high performance analog semiconductors The Company s products address some of the industry s fastest growing markets such as flat panel displays cell phones handheld products and notebooks Intersil s product families address power management and analog signal processing functions Go to www intersil com products for a complete list of Intersil product families For a complete listing of Applications Related Documentation and Related Parts please
26. one Audio Signals THD N at 20mW into 32QLoad 0 1906 e Cross talk Audio Channels 20Hz to 20kHz 110dB Single Supply Operation Vpp 2 5V to 5 5V 3dB Bandwidth USB Switches 630MHz Available in EUTQFN and TDFN Packages Pb Free RoHS Compliant Compliant with USB 2 0 Short Circuit Requirements Without Additional External Components Applications see page 18 and Other Personal Media Players Cellular Mobile Phones e PDA s e Audio USB Switching Related Literatu re see page 18 Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices SMDs e Application Note AN1337 ISL54206AEVAL1iZ Evaluation Board User s Manual HCONTROLLER USB HIGH SPEED TRANSCEIVER NOTE The L and R 50k9 resistors to ground are not shown October 28 2010 1 FN6515 3 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2007 2010 Rights Reserved other trademarks mentioned are the property of their respective owners Uu r Ul 4 o 9 gt ISL54206A Pin Configurations note 1 ISL54206A 10 LD pTQFN TOP VIEW ISL54206A 10 LD TDFN TOP VIEW NOTE VDD IN COM COM GND 1
27. s can accept signals that swing below ground They were designed to pass audio left and right stereo signals that are ground referenced with minimal distortion The USB switches were designed to pass high speed USB differential data signals with minimal edge and phase distortion The ISL54206A was specifically designed for MP3 players cell phones and other personal media player applications that need to combine the audio headphone jack and the USB data connector into a single shared connector thereby saving space and component cost Typical application block diagrams of this functionality is shown above The ISL54206A has a single logic control pin IN that selects between the audio switches and the USB switches This pin can be driven Low or High to switch between the audio CODEC drivers and USB transceiver of the MP3 player or cellphone The ISL54206A also contains a logic control pin CTRL that when driven Low while IN is Low opens all switches and puts the part into a low power state drawing typically 1nA of Ipp current A detailed description of the two types of switches is provided in the following sections The USB transmission and audio playback are intended to be mutually exclusive operations 9 intersil FN6515 3 October 28 2010 ISL54206A Audio Switches two audio switches L R are switches that can pass signals that swing below ground by as much as 1 5V They were designed to pass ground
28. see the respective device information page on intersil com ISL54206A To report errors or suggestions for this datasheet please go to www intersil com askourstaff FITs are available from our website at http rel intersil com reports search php For additional products see www intersil com product tree Intersil products are manufactured assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 18 n FN6515 3 Intersil October 28 2010 15 L54206A Package Outline Drawing
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