MVME410 Dual Parallel Port Module User`s Manual
Contents
1. Port 1 Direction Headers 35 16 8 Port 2 Direction Headers J8 19 8 8 6 Port 2 Direction Headers J10 Jll Interrupt Select Headers J12 Jl3 sooo Base Address Select Header Jl4 777 LED Control Header JIS i599 HE cs Typical DPP Interface Cabling Diagram Typical Printer Driver Routine 3 Sheets DPP Module Block Dragram s 777 I O Channel Memory Map e e e e I O Channel Side Timing Signal Diagram Peripheral Side Timing Signal Diagram 3 sheets DPP Module Parts Location Diagram DPP Module Schematic Diagram 2 Sheets LIST OF TABLES Dual Parallel Port Module Specifications Peripheral Signal Specifications DPP Module 19005 Headers J3 and J4 Configurations Headers J5 and 16 Configuratio2. The Read Strobe with E Restore mode of the PIA will cause a 250 ns pulse that is shorter than the minimum time required by the Centronics data Strobe line This requires that the Set Reset CA2 mode be used to control the data strobe line to a Centronics printer The FAIL LED indicator may use PB7 of port 1 If so PB7 may not be used for peripheral devices 4 7 MODULE I O TIMING Table 4 2 and Figure 4 3 show the performance characteristics of the DPP from the I O Channel side All data transfers on the I O Channel are between the master and a slave and are initiated by the master All data transfers are asynchronous and rely on two interlocked signal lines STB and XACK STB is generated by the master and initiates data transfer XACK is generated by the addressed slave to indicate that the data transfer has been acknowledged TABLE 4 2 1 0 Channel Timing Signal Characteristics TIMING PARAMETER VALUE IN NANOSECONDS NUMBER DESCRIPTION TYPICAL MAX 1 STB low to XACK low 990 1300 2 STB high to XACK high 122 184 4 6 STB XACK FIGURE 4 3 1 0 Channel Side Timing Signal Diagram 4 8 MODULE PERIPHERAL TIMING Timing characteristics for the PIA are contained in the PIA data sheet However the signals used on the DPP peripheral side are buffered Buffers introduce delays that make some of the characteristics at the peripheral connectors different from the characteristics at the PIA Those characteristics which are m
3. KKK ttt DUTPUT PARAMETERS NONE 2 4t 4t 1 3 3 46 3 3 3 36 JE 36 3 4 3E 3E 36 3 dE dE 2 3E 4 EHE 4 3 2 2 3 3 dE dE dE 2 IE 4 IE dE 4 1E 3 1 46 3 HE 2 4 4 3E REGISTERS ALTERED NONE 4 3 46 He dt 46 4 4 3 36 5 2 3334 3 dE 3 1 3E 3 dE 36 dE dE AAA dt t dE 2 E 3E 2 2 X 3 4E 3 36 3 1E 3E 3E 3E 3E E 4E 3E 4 464 1E 3E 3 THISPR EQU 1000 START OF THIS PROGRAM PBASE EQU F801E1 BASE ADDRESS OF PARALLEL PORT 1 PDATA EQU 0 OFFSET OF A PDATB EQU 4 OFFSET OF B PCNTRLA EQU 2 OFFSET OF A PCNTRLB EQU 6 OFFSET OF B SIDE CONTROL REG FROM BASE PSTATA EQU PCNTRLA OFFSET OF A SIDE STATUS REGISTER FROM BASE PSTATB EQU PCNTRLB OFFSET OF B SIDE STATUS REG FROM BASE PDDRA EQU PDATA OFFSET OF A PDDRB EQU PDATB OFFSET OF B ORG THISPR INITPIA DS W INITSAVE MOVE AD A7 GET SOME WORKING REGISTERS MOVE SR A7 SAVE 48200 STATUS REG LEA PBASE AB POINT AB AT PORT 1 INITDDRA MOVE MOVE INITCTRA MOVE INITDDRB MOVE MOVE INITCTRB MOVE INITRSTR MOVE MOVE RTS FIGURE 3 1 8 38 PCNTRLA AQ SFF PDDRA AO 4 93C PCNTRLA AQ 638 PCNTRLB AQ 600 PDDRB AQ 63C PCNTRLB AQ A7 SR 47 AQ POINT AT DDRA DDRA MAKES PERPH DATA A OUTPUTS CA2 OUTPUT HIGH RIGHT NOW SET FLAG ON LOW TO HIGH INT DISABLED POINT AT DDRB DDRB MAKES PERPH DATA B INPUTS CB2 0UTPUT H
4. IDK IDK IDK 45V 44 LSH2 LS164 6 1 LIZ NC U4 D y 4 l P2CBL aA PI CT CK ON 8 teu BY ie IQ 5V Bass Di ys Da Za K a 8 0 p 112 3 4 Bee V n I R3F U3F 2 I gt CK IDK 5V srl VA P2CB2 BR gt O ISO UIA UI4B UI4E LSI4 LSI4 L514 T PI CiI8 STEX po CSTBI 3 N 4 CSTBXI Sol PICA2 3 RIB IDK T 5V LS24 5 6 7 AQ 2 PIPA 98 gt PI CIQ WTR 0000 7 US 3 PIPA Ji 3T PI Clo Al 4 PIPA JI 35 5 PIPAS 3 6_PIPA4 Ji 31 lt 7 PIPAS 9 8 PIPAG J1 27 Pi Al6 2 9 PIPAT 5 5V E oe DRH UT V AN x Enc LS682 UI3C Re UI3B P an AI 2 3 L338 ef MK a ae Si 0 Uli 2_PI AIC GLU B 8 C 6415 XIX 5 5 PI C2 AS 4 d Ha H PAS AG 5 Lili LI 18 2 PIPBZ 3 ALS B 5 Jes CIORESXI A ii 3 PIPBI J1 21 PAM AG E 4 2 5V 2 51585 TAT PI CI4 AS 5 5 65 i PAIS Ad B 50 OF RSE SR3D SR3C Se A O Pp Ta o PIPB4 B 0 04 IDK IDK IDK ea A Ba ES AD E A T PIPB5 Ji 13 zur LSb4 6 5 4 3 1115 8 PIPBl Ji 11 A B bia NC 7 18 9 PIPBT 8 AR KE Eq n EL 45V Pi Co XACK X 70 o3 fs AN U36 ME gt LS244 DP e PLCS IORESX 8 2 Nc Ll Oe 4 Jie 2 EA BE y Pi C4 INTI 5 V R3A 6 INT4 IDK E T a8 NC 9 5V Pi C2 21735 UIs U3C E 5V Mr V 63EW3I26B
5. REV D SH 2 OF 2 FIGURE 5 2 DPP Module Schematic Diagram Sheet 2 of 2 5 11 5 12 SUGGES TION PROBLEM Were REPORT Motorola welcomes your comments on its products and publications Please use this form To Motorola Inc Microsystems 2900 S Diablo Way Tempe Arizona 85282 Attention Publications Manager Maildrop DW164 Product _ B u Da Manual COMMENTS Please Print Name lt lt lt Title Company OA Division Street gt Mail Drop _____________ Phone City NNNM SENDER State Zip For Additional Motorola Publications Microsystems Field Service Support Literature Distribution Center 800 528 1908 616 West 24th Street 602 829 3100 Tempe AZ 85282 602 994 6561 A MOTOROLA MOTOROLA Semiconductor Products Inc PO BOX 20912 e PHOENIX ARIZONA 85036 e A SUBSIDIARY OF MOTOROLA INC 16809 1 PRINTED IN USA 2 84 MPS 2M
6. actions initiated by that signal occur on a high to low transition Throughout this manual the X in the signal mnemonic of peripheral Signals i e PXCBl PXCB2 denotes the following X 1 denotes Jl front panel connector X 2 denotes J16 front panel connector A UJ N N N IN N NS N N N N N N N fo w Ww WINE e 0 o mm de WWW WWW WWW Dd I gt DS OBS SSS SES e o 9 9 o o 00 OY UN BWW WWD gt 0 OO J OY US WN Ne WN gt TABLE OF CONTENTS GENERAL INFORMATION INTRODUCTION FEATURES SPECIFICATIONS 0000000000000000000000000000000000000000 GENERAL DESCRIPTION 000000000000000000000000000000000 RELATED DOCUMENTATION 00000000000000000000000000000000 o e o o e o HARDWARE PREPARATION AND INSTALLATION INSTRUCTIONS INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION 000000000000000000000000000000000 LED Monitor Header J2 Port 1 Direction Headers J3 J4 Port 1 Direction Headers J5 J6 Port 2 Direction Headers J8 J9 00000000000000000 Port 2 Direction Headers J10 J11 Interrupt Select Headers J12 J13 Base Address Selection Header J14 LED Control Header J15 INSTALLATIO
7. and the buffers are strapped programmed as inputs The programmed direction of the lines and the strapped programmed direction of the buffers should be the same For direction strapping see the port 1 information in Chapter 2 PBO PB7 relate to P1PBO P1PB7 in the same way that PAO PA7 relate to PlPAO0 P1PA7 with the following exception When J15 is strapped such that PB7 controls the FAIL LED indicator then PB7 is severed from P1PB7 and it may be programmed as an output even though the direction of the P1PBO P1PB7 buffers may be inputs In this configuration driving PB7 low turns on the FAIL LED and driving PB7 high turns off the FAIL LED 4 5 PARALLEL PORT 2 Parallel port 2 is identical to parallel port 1 except that port 2 does not have a FAIL LED indicator connectable to PB7 Therefore the special case covered in the port 1 explanation with respect to the LED does not apply to port 2 4 5 4 6 LIMITATIONS Following are certain options of the MC6821 which are not supported by the DPP a b The direction of port 1 CA2 or port 2 CA2 is hardware strappable but not dynamically alterable The data direction registers must be configured to set their corresponding peripheral data lines to be a block of eight inputs or a block of eight outputs depending on the hardware option that is being used The direction of individual peripheral data lines is not allowed to differ from that of the whole set of eight peripheral data lines
8. parallel interface between an 1 0 Channel bus master and one or two printers with a Centronics interface The DPP employs an MC6821 chip to latch output printer data drive printer control lines and monitor printer handshake and status lines The MC6821 data sheet contains additional information on the MC6821 The DPP provides two general purpose parallel printer ports Figure 4 1 is a block diagram of the DPP As shown in Figure 4 1 the DPP has a common I O Channel interface section and two parallel port sections Each of the parallel port sections consists of a peripheral interface adapter PIA with TTL buffers that provide drive capability on the peripheral side The two parallel ports are identical except for a FAIL LED indicator that is strappable to port l 4 3 I O CHANNEL INTERFACE The 1 0 Channel interface section provides map decoding logic access control logic and interrupt logic An explanation of each follows 4 3 1 Map Decoding Logic The DPP is strap selectable to appear at any 10 byte block within the first 100 byte block of the I O Channel memory map as shown in Figure 4 2 If the selected base address is 500 the 10 block byte upper boundary is one bit less than 520 Each port appears twice in the 10 byte area To set the base address of the DPP see block select header J14 information in Chapter 2 Table 4 1 shows the addresses of the registers within each of the DPP parallel ports with respect to the DPP base add
9. 0 0070 0060 0050 0040 0030 0020 0010 0000 OFFSET FROM DPP MODULE BASE ADDRESS F O O F NN N WKF siU AO a ITI OOO gt UO QUO U tu NOTE TABLE 4 1 CONTROL REGISTER BIT CRA 2 2 O Xxx di bb Do x X gt lt x HL Do DIO X x x QO gt lt x lt dI x X x HO X x XS x n X x x x r OK Xx lt x Lo x DPP Module Register Addresses REGISTER Control register B Data direction register Peripheral register B Control register A Data direction register Peripheral register A Control register B Data direction register Peripheral register B Control register A Data direction register Peripheral register A Control register B Data direction register Peripheral register B Control register A Data direction register Peripheral register A Control register B Data direction register Peripheral register B Control register A Data direction register Peripheral register A X denotes a don t care condition 4 4 PORT PP FP B N N N N N N F FF FF BF S iF N N N N N N 4 4 PARALLEL PORT 1 Parallel port 1 employs an MC68B21 PIA for its logic functions The MC6821 Data Sheet explains how to use it Pay particular attention to the sections that deal with programming the PIA In addition to the information provided in the PIA manual the following information is necessary to use the DPP All the peripheral data and peripheral control lines on the PIA are buffered with TTL drivers rece
10. 0 C29 C30 C1 C2 C3 TABLE 5 1 I O Connector Pl Pin Assignments SIGNAL MNEMONIC GND All Al0 A6 A4 A2 D7 D6 D4 D2 12V Reserved 12V 5V INT4 INT3 INT2 SIGNAL NAME AND DESCRIPTION GROUND ADDRESS bus bit 11 One of 11 input signals used to Selectively access the DPP ADDRESS bus bit 10 Same as bit All on pin All ADDRESS bus bit 8 Same as bit All on pin All ADDRESS bus bit 6 Same as bit All on pin All ADDRESS bus bit 4 Same as bit All on pin All ADDRESS bus bit 2 Input signal used to select port 1 when low and port 2 when high during a DPP cycle DATA bus bit 7 Bidirectional signal used to transmit data between the I O Channel master and the DPP during read and write cycles DATA bus bit 6 Same as bit D7 on pin A20 DATA bus bit 4 Same as bit D7 on pin A20 DATA bus bit 2 Same as bit D7 on pin A20 Not used by DPP Not used by DPP Not used by DPP 5 Vdc Power Used by the module logic circuits INTERRUPT REQUEST 4 One of four active low output signal lines used by the DPP to interrupt the 0 Channel master INTERRUPT REQUEST 3 Same as signal INT4 on pin Cl INTERRUPT REQUEST 2 Same as signal INT4 on pin Cl 5 2 PIN NUMBER C4 C5 C6 C12 C13 C14 C15 C16 C17 C18 C19 C21 C22 C23 C24 TABLE 5 1 I O Connector Pl Pin Assignments cont d SIGNAL MNEMONIC INT1 IORES
11. 0000000000000000000000 GENERAL DESCRIPTION 0000000000000000000000000000000000 1 0 CHANNEL INTERFACE ses Map Decoding LoglO asian Access Control Logic Interrupc LOGIC sn PARALLEL PORT l 0000000000000000000000000000000000000000 PARALLEL PORT 2 000000000000000000000000000000000000000 LIMITATIONS 0 MODULE 1 0 TIMING oo u MODULE PERIPHERAL TIMING 000000000000000000000000000000 2 1 2 1 2 1 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 11 2 12 2 12 2 12 3 1 3 1 el 4 1 4 1 4 1 4 1 4 1 4 2 4 5 4 5 4 6 4 6 4 7 CHAPTER 5 U OF UOT OF OFF uu o 9 o H GN ND DH FIGURE 1 1 TABLE 2 1 2 2 TABLE OF CONTENTS cont d SUPPORT INFORMATION INTRODUCTION 9993999 999599 44 CONNECTOR SIGNAL DESCRIPTIONS 1 0 Channel Connector peripheral Connectors doo WR E TES V wee ease cx PARTS LIST 45949949949 79 9 DIAGRAMS LIST OF ILLUSTRATIONS Dual Parallel Port Module zus u DPP Module Header Location Diagram LED Monitor Header JJ Port 1 Direction Headers J3 J4
12. 002 PSTROBE MOVE B 34 PSTRB AQ MAKE DATA STROBE GO LOW 95 0000185656 2 MOVE B 3C PSTRB AQ THEN HIGH 96 97 00001050 082800070002 PACKNGE BTST B 7 PACKN AQ IF CHARACTER NOT ACKNOWLEDGED 98 02201262 8 856 5 PACKNGE THEN WAIT FOR IT TO BE 99 100 0001064 46DF PRSTR MOVE W A7 SR RESTORE 68000 STATUS REGISTER 101 001066 4CDF0104 MOVEM L AT D2 A RESTORE REGISTERS 102 103 001 6A 4E75 PRTRN RTS 104 195 END MOTOROLA M6 S8000 ASM VERSION 1 30SMD 90 RTTLIO DRIVER SA 98 09 82 14 52 12 SYMBOL TABLE LISTING SYMBOL NAME SECT VALUE SYMBOL NAME SECT VALUE INITCTRA 00001014 PDATA 00080008 INITCTRB 00001026 PDATB 4 INITDDRA 0000100A PDDRA 22220 INITDDRB B000101A PDDRB 00000004 INITPIA 00001086 PRDY 864 INITRSTR PRSTR 4 INI TSAVE 29801800 PRTRN 2020021004 PACKN 00000002 PSAVE 00001032 PACKNCLR 0000104E PSEND B002104C PACKNGE 0222105 PSTATA 0 2 222 2 PBASE F801E1 PSTATB 20000006 PCHAR 00001932 PSTRB 00000092 PCNTRLA 20008062 PSTROBE 00001050 PCNTRLB 00000006 THISPR 00001000 FIGURE 3 1 Typical Printer Driver Routine Sheet 3 of 3 CHAPTER 4 FUNCTIONAL DESCRIPTION 4 1 INTRODUCTION This chapter provides the overall block diagram level descriptions for the Dual Parallel Port Module A general description provides an overview of the module followed by a detailed description of each section of the DPP 4 2 GENERAL DESCRIPTION The DPP is designed to provide a
13. 1 Same as pin 25 except bit AO DATA STROBE An output pulse used to clock data from the MPU to the printer logic The pulse is active low am at least 1 0 us wide ACKNOWLEDGE A low level input pulse indicating the input of a character into memory or the end of a functional Operation TABLE 5 3 DPP Module Parts List MOTOROLA PART NUMBER DESCRIPTION 84 W8126B01 Printed wiring board 21SW992C0 25 Capacitor ceramic 1 uF 6 50 Vdc 23NW9618A33 Capacitor electrolytic 22 uF 6 25 Vdc 48NW9612A34 Indicator light red 5 Vdc 28NW9802D76 Connector right angle 50 pin 28NW9802D04 Header single row post 3 pin 28NW9802D01 Header double row post 2 pin 28NW9802E30 Header single row post 4 pin 28NW9802E41 Connector socket 50 pin 28NW9802C63 Header double row post 12 pin 28NW9802C43 Header double row post 8 pin 28 W4262B01 Connector socket 50 pin Stacked on J1 5 5 TABLE 5 3 DPP Module Parts List cont d REFERENCE MOTOROLA DESIGNATION PART NUMBER DESCRIPTION Pl 28NW9802E05 Connector plug 64 pin R1 R2 R6 51NW9626A22 Resistor network 5 10k ohm R3 R4 R5 R7 51NW9626A37 Resistor netwrk 9 10k ohm U1 U9 U11 U12 51NW9615E96 I C SN74LS245 U2 U3 U17 51NW9615F02 I C 74LS244N U4 51NW9615H93 I C SN74LS641N U5 51NW9615H92 I C N74LS112N U6 51NW9615F41 I C DM74LS164N U7 51NW9615H41 I C SN74LS682N 0 51NW9615D85 I C MC68B21P U13 51NW9615G38 I C SN74LS38N U14 51NW9615E93 I C SN74LS14N U15 51NW9615G12 I C SN7
14. 4LS375N U16 51NW9615C56 I C SN74S08N U18 51NW9615E98 I C SN74LS373N 09NW9811A22 Socket I C DIL 40 pin use at U8 and U10 29NW9805B17 Jumper shorting insulated use at J2 J5 J8 J10 J12 J13 J15 576 8 S L S 0 ha CN HD HD y FIGURE 5 1 DPP Module Parts Location Diagram NOTES FOR REFERENCE DRAWINGS REFER TO BILL S OF MATERIAL 2 UNLESS OTHERWISE SPECIFIED ALL RESISTORS ARE IN OHMS 5PCT 1 4 WATT ALL CAPACITORS ARE IN UF ALL VOLTAGES ARE DC 3 INTERRUPTED LINES CODED WITH THE SAME LETTER OR LETTER COMBINATIONS ARE ELECTRICALLY CONNECTED A DEVICE TYPE NUMBER IS FOR REFERENCE ONLY THE NUMBER VARIES WITH THE MANUFACTURER 5 SPECIAL SYMBOL USAGE X DENOTES ACTIVE LOW SIGNAL C2 DENOTES ON BOARD SIGNAL 6 INTERPRET DIAGRAM IN ACCORDANCE WITH AMERICAN NATIONAL STANDARDS INSTITUTE SPECIFICATIONS CURRENT REVISION I A PART TYPES ARE ABBREVIATED IN THE FIELD OF THE DRAWING FOR FULL PART TYPE REFER TO TABLE DENOTES PWB HEADER CONNECTOR DENOTES FRONT PANEL CONNECTOR DENOTES PWB FRONT PANEL CONNECTOR 6 JI FRONT J7 PANEL PWB A TABLE me A o 10 vi masas i9 u2 45044 i8 uva 745244 19 Us us I U 74LSII2 8 741564 7 66882 7445245 I vid 406882 UH 7415245 12 02 74 5245 U3 741538 T 741514 Ui5 7415375 8 vie
15. 74528 74159244 1 26 8 7415373 28 NIN Nm FREE min no ilari Li BEA ATEN IA RENE ie 54 51 ul _ DI E HIGHEST NUMBER NOT USED USED REFERENCE DESIGNATIONS 5V C9 ca icr Lee ics Lcs 1 03 tc2 Lei 22 UU LPLPULVUVVY 5V Ady 6 JI 7 J1 45 NC CRESERVED J1 49 NC CRESERVED Nc c 2v ENC NOT USED ett A3 NC A PZCAI J7 47 JI6 47 2e 62 E J7 43 J16 43 28 P2PAI 7 37 Jl6 37 261 P2 PAZ J7 35 4 016 5 07 53 16 53 261 PZPA3 26 P2PA4 a 47 31 261 P2PAS 07 25 gt Jl6 29 261 P2PAG 7 27 1627 261 P2PA7 J7 25 P2PBO J7 23 06 23 P2PE J7 2 P2PB2 J7 1 2E __P2PB4 7 15 25 P2PB7 J7 9 SEI 2 TED NC CRESERVED 63EW3126B REV D SH I OF 2 FIGURE 5 2 DPP Module Schematic Diagram Sheet 1 of 2 5 9 5 10 3 24 DO D ID PI C23 DI IDE PI A23 D2 de lt D PI C22 D3 S PI A22 D4 dt D o n T5549 106 PI A TN 2 22 pis D MC68B2 am po Pao 2 5 P PA3 IDS 6 P2PA4 IDG ST PI Pie 106 3 P2PAT C 2 P2PRA 3 ice 4w P2PB2 c 5 P2PB3 ice ewP2PB4 cc Te POPES lt 5V 45V CIEN E Bg P PBo ice Rae R H A es eel i que u PEPBT OS 18 8 7 6 5 4 3 2 IDK iK 052 CBI RSH 2856 lt RSF lt RSE 2852 2R5C 8 AOE DIR pra 8 0 USA Ub IDK IDK DK
16. B IRQ2A or IRQ2B will drive which I O Channel interrupt line INT1 INT4 One any combination or all of the PIA signals can be connected to a single I O Channel interrupt line at the same time but a single PIA signal Should not be connected to more than one I O Channel interrupt line The two headers comprise four sets of six contacts 1 6 and 7 12 Each set of six contacts controls one PIA to I O Channel connection The factory configuration of each header is shown in Figure 2 7 Table 2 6 lists the jumper configurations that determine PIA signal to I O interrupt line connections FIGURE 2 7 Interrupt Select Headers J12 J13 2 8 TABLE 2 6 Headers J12 and J13 Configurations HEADER PINS JUMPER CONNECTED REMARKS J12 1 3 IRQ1A connected to INT2 J12 2 4 1 IRQ1A connected to INTI J12 3 5 IRQ1A connected to INT3 J12 4 6 IRQlA connected to INT4 J12 7 9 1 IRO1B connected to INT2 J12 8 10 IRQ1B connected to INT1 J12 9 11 IRQ1B connected to INT3 J12 10 12 IRO1B connected to INT4 J13 1 3 IRO2A connected to INT2 J13 2 4 IRQ2A connected to INTI 313 3 5 1 IRQ2A connected to INT3 J13 4 6 IRQ2A connected to INT4 J13 7 9 IRQ2B connected to INT2 J13 8 10 1 IRQ2B connected to INTI J13 9 11 IRO2B connected to INT3 J13 10 12 IRQ2B connected to INT4 NOTE 1 Factory installed jumper placement 2 3 7 Base Address Select Header J14 Header J14 can be config
17. IGH RIGHT NOW SET FLAG ON LOW TO HIGH INT DISABLED RESTORE 68800 STATUS REGISTER RESTORE AB Typical Printer Driver Routine Sheet 1 of 3 Et MOTOROLA 1163000 ASM VERSION 1 3BSMD 58 RTTLIO DRIVER SA 08 09 82 14 52 12 49 dt d t de HE Ae IE AE DEAE AE AE AE AE AE AE AE EE IE HE AE IE dt E AE ME dE dE DE E de 4 EAE E EE AE AE IE IE EAE AE EAE AE AE AE E IEEE DE di NN NK 91 VM 2 PRINTER DRIVER USING THF RTTLIO PARALLEL PORT 1 1 52 ikki Li Li hii aE AE AE DE AE E AE DAE E DE AE DE E HE DE AE AE DE AE HE GE A a AE AE a DE AE E a AE AE DE FEAE I HE AE AE 53 FUNCTION Send the character contained in D to a Printer through 54 an RTTLIO board Board strapped to appear at Block 15 If the 99 Printer is not selected then return from this subroutine with Di B 96 Non zero If the printer is selected and the character is sent 57 successfully then return with D1 B zero Ab 58 3E 4t ME IE 1277 77 ME AE AE CoP rrr errr rere NA AA A A A AA A aNd EAE IE IE IE IE HE HE AERE 99 INPUT PARAMETERS D B CONTAINS THE ASCII CODE OF THE CHARACTER TO 60 BE SENT 61 4404004004 IE AE AE AE MEAE AE AE AC AE HE AE AE EAE ETE EAE AE EIE SE SEDE AE AERE AE MEAE IE DE IE AE AE IE AE AE 44 EIE E EIE IE GE 62 OUTPUT PARAMETERS BIT 8 OF Di 8 IF THE PRINTER IS NOT SELECTED 63 BIT 1 OF Di 1 IF THE PRINTER IS OUT OF PAPER Di B 81 IF 64 THE PRINTER WAS SELECTED WAS NOT OUT OF PAPER AND THE CHARACTER 63 WAS SEN
18. ION This chapter provides the connector signal descriptions parts list and associated parts location diagram and a schematic diagram for the Dual Parallel Port Module 5 2 CONNECTOR SIGNAL DESCRIPTIONS The DPP has three interface connectors one to connect it to the I O Channel and two to connect it to Centronics printer compatible interface peripheral devices 5 2 1 I O Channel Connector The I O Channel connector Pl on the DPP is a standard DIN 41612 triple row 64 pin male connector The backplane ribbon cable uses the female connector Table 5 1 lists the connector Pl pin assignments Additional information on this connector can be obtained from the I O Channel Specification Manual 5 2 2 Peripheral Connectors Front panel connectors Jl and J16 on the DPP are double row 50 pin male connectors They mate to a female ribbon connector such as a 3M 3425 5000 Table 5 2 lists the front panel connectors Jl and J16 pin assignments by pin number Signal mnemonic and signal name and description 5 3 PARTS LIST Table 5 3 lists the components of the DPP A parts location diagram for the module is provided in Figure 5 1 This parts list reflects the latest issue of DPP module at the time of printing 5 4 DIAGRAMS Figure 5 2 is the schematic diagram for the DPP PIN NUMBER Al Al0 A17 A19 A24 A25 A31 A32 C11 C20 C25 C31 C32 All A12 A13 A14 A15 A16 A21 A22 A23 A26 C26 A27 C8 C10 C27 A28 C28 A29 A3
19. MVME410 D2 VME410 Dual Parallel Port Module User s Manual QUALITY e PEOPLE PERFORMANCE MVME410 D2 AUGUST 1983 MVME410 DUAL PARALLEL PORT MODULE USER S MANUAL The information in this document has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies Furthermore Motorola reserves the right to make changes to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit Gescribed herein neither does it convey any license under its patent rights or the rights of others I Omodule is a trademark of Motorola Inc Second Edition Copyright 1982 by Motorola Inc First Edition October 1982 SAFETY SUMMARY SAFETY DEPENDS ON YOU The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the equipment Motorola Inc assumes no liability for the customer s failure to comply with these requirements The safety precautions listed below represent warnings of certain dangers of which we are aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equip
20. N INSTRUCTIONS cascos iii Installation in VME Chassis oo 8 7 8 Installation in 5 Slot I Omodule Card Cage e o 0 e e e e e e 9 9 9 e o e 0 e e e e o o SE O OPERATING INSTRUCTIONS INTRODUCTION 0 e INDICATOR e e e s e s e e OP ERATING P ROCEDURE 0 e o 0 e FUNCTIONAL DESCRIPTION INTRODUCTION 000000000000000000000
21. T SUCCESSFULLY IF NO ACKNOWLEDGE IS EVER RECIEVED THEN THIS 66 RDUTINE IS NEVER EXITED 67 4t MEAE IEEE MEAE IE EIE HE 2727272 2 772 2 AE AE IE MEDIE AE AE IE AE IEEE AE 4E IE EIE IE IE NK aaa aa aaa 68 REGISTERS ALTERED D1 B amp 9 00 3 IEEE EAE IEEE AE AE AE IE IE AE EIE AE UE AE E IAE AE IE AE E UE EIE EHE EAE AE IEEE IEEE IE E IEEE EE 70 71 72 00080002 PACKN EQU PSTATA OFFSET OF A SIDE STATUS REC FROM BASE 73 00000082 PSTRB EGU PENTRLA OFFSET OF A SIDE CONTROL REG FROM BASE 232202294 PRDY EQU PDATB OFFSET OF B SIDE PERIPHERAL DATA RES FROM BASE 76 000010323 0 PCHAR DS W a 77 00001032 98 PSAVE MOVEM L A7 GET SOME WORKING REGISTERS 78 00001036 4BE7 MOVE W SR A7 SAVE 68000 STATUS REGISTER 79 6 00001039 41F900F801E1 LEA PBASE AQ AB BASE ADDRESS OF PORT 1 81 82 0000103555 64 MOVE 8 PRDY AQ D2 GET THE STATUS OF PAPER AND SELECT 83 00001042 3 AND 8 70000001 1 D2 PAPER OUT BIT 1 SELECT BIT 84 00001046 2 MOVE 8 D2 DI SAVE RESULTS IN Di AS OUTPUT PARAMETER 85 00001048 5302 SUB B 4 01 D2 IF PRINTER NOT SELECTED OR PAPER OUT 84 00001044 6610 BNE 8 PRSTR THEN RETURN WITH Di 384581 ERROR 87 88 00001046 80 PSEND MOVE B D PDATA AQ ELSE SEND CHARACTER TO PRINTER 89 98 00001046 8 PACKNCLR MOVE B PDATA AQ D2 DO DUMMY READ OF PIA PERIPHERAL DATA 91 REGISTER IN ORDER TO CLEAR ACKNOWLEGDE FLAG 92 FIGURE 3 1 Typical Printer Driver Routine Sheet 2 of 3 v t 93 94 00001059 117600340
22. XACK CLK A9 A7 Al AO STB D5 D3 DI SIGNAL NAME AND DESCRIPTION INTERRUPT REQUEST 1 Same as signal INT4 on pin Cl INPUT OUTPUT RESET Active low input signal used to reset the DPP TRANSMIT ACKNOWLEDGE Active low output signal used to advise the I O Channel master that write data is latched or read data is available CLOCK Free running input signal used by the DPP for internal synchronization and timing ADDRESS bus bit 9 Same as bit All on pin All ADDRESS bus bit 7 Same as bit All on pin All ADDRESS bus bit 5 Same as bit All on pin All ADDRESS bus bit 3 Not used ADDRESS bus bit 1 Same as bit All on pin All ADDRESS bus bit 0 Same as bit All on pin All STROBE The high to low transition of this input signal indicates to the DPP that an I O Channel cycle is starting The low to high transition indicates to the DPP that the current I O Channel cycle has ended WRITE An input signal that is low when the I O Channel is in a write cycle and high when the I O Channel is in a read cycle DATA bus bit 5 Same as bit D7 on pin A20 DATA bus bit 3 Same as bit D7 on pin A20 DATA bus bit 1 Same as bit D7 on pin A20 DATA bus bit 0 Same as bit D7 on pin A20 5 3 TABLE 5 2 Peripheral Connectors Jl and J16 Pin Assignments PIN SIGNAL NUMBER MNEMONIC SIGNAL NAME AND DESCRIPTION 1 PXCB2 INPUT PRIME A low level output signal which clears the prin
23. annel compatible Single wide VME board form factor Centronics printer standard interface compatible Two MC6821 Peripheral Interface Adapter PIA buffered ports Each port capable of driving two of four I O Channel interrupt lines 16 peripheral data lines per port each capable of sinking 24 mA Four peripheral control lines per port two input only and two individually configurable as input or output Each group of eight peripheral data lines is hardware strappable as input only output only or bidirectional under software control Will interface two asynchronous parallel data hard copy printers to the I O Channel Operates with I O Channel master to drive hard copy printers Self test FAIL LED indicator 1 3 SPECIFICATIONS General specifications for the DPP are given in Table 1 1 Table 1 2 gives peripheral signal specifications LL EEE lt e w m m w m 9 090 lt 4 x lt o th Dual Parallel Port Module FIGURE 1 1 CHARACTERISTIC Power requirements Temperature Operating otorage Relative humidity PhySical characteristics PC board only Height Depth Thickness PC board with connectors and board stiffener Height Depth Thickness Dual Parallel Port Module Specifications SPECIFICATIONS 5 Vdc 6 762 mA typical 991 mA maximum 0 to 70 C 409 to 85 C 0 to 90 non condensing 6 30 in 160 mn 3 94 in 100 mm 0 59 in 15 m
24. athode Ray Tube CRT causes a high velocity scattering of glass fragments implo sion To prevent CRT implosion avoid rough handling or jarring of the equipment Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves DO NOT SUBSTITUTE PARTS OR MODIFY EQUIPMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification of the equipment Contact Motorola Microsystems Warranty and Repair for service and repair to ensure that safety features are maintained DANGEROUS PROCEDURE WARNINGS Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment WARNING Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting 14260 PRINTED IN USA 6 81 MPS 300 PREFACE Unless otherwise specified all address references are in hexadecimal throughout this manual An asterisk following the signal name for signals which are level Significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge Significant denotes that the
25. d in a 5 slot I Omodule card cage as follows Ae Turn all equipment power OFF CAUTION CONNECTING MODULES WHILE POWER IS APPLIED MAY RESULT IN DAMAGE TO COMPONENTS ON THE MODULE If card cage in part of VERSAmodule chassis remove card slot cover plate Insert DPP in slot and secure with two captive screws Peripheral connection to DPP port 1 and or port 2 is accomplished by mating a double row 50 pin female ribbon connector such as a 3M 3425 5000 to male connectors Jl and J16 on the DPP front panel as shown in Figure 2 10 Printer cable assembly Motorola part number M68KVMPRTCE can be used Connect the other end of the ribbon cable to a printer with a Centronics printer compatible interface Equipment power may be turned ON 2 12 CENTRONICS PRINTER 1 0 CHANNEL MASTER DPP Pl MODULE I O CHANNEL FAILO J16 FIGURE 2 10 Typical DPP Interface Cabling Diagram 2 13 2 14 CHAPTER 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides the necessary information to initialize and operate the Dual Parallel Port Module in a typical system 3 2 INDICATOR The DPP contains one indicator a front panel red FAIL LED If header J15 is jumpered between pins 2 3 the FAIL indicator will illuminate when an 0 Channel reset or a software controlled module failure occurs 3 3 OPERATING PROCEDURE Following is a typical procedure showing how to use the DPP to interface w
26. e Headers direction direction direction direction direction direction direction direction FACTORY CONFIGURATION 2 3 192 l 2 1 2 No jumper No jumper 2 4 7 9 3 5 8 10 No jumper 2 3 2 3 2 Port 1 Direction Headers J3 J4 Headers J3 and J4 together control the direction of signal lines PICA2 and PIPAO PIPA7 The factory configuration of each header is shown in Figure 2 3 Table 2 2 lists the jumper configurations that determine whether the lines are inputs or outputs J3 J4 FIGURE 2 3 Port 1 Direction Headers J3 J4 TABLE 2 2 Headers J3 and J4 Configurations HEADER PINS JUMPER CONNECTED REMARKS J3 none PlCA2 is not used P1PA0 P1PA7 are outputs J4 1 2 J3 none PlCA2 is not used P1PA0 P1PA7 are inputs when U8 39 CA2 is high and outputs when U8 39 CA2 is low J4 2 3 J3 none PlCA2 is an input PIPAO PIPA7 are inputs J4 3 4 J3 none P1CA2 is an input P1PA0 P1PA7 are outputs 4 1 2 4 J3 none PICA2 is not used PlPAO PlPA7 are inputs J4 none 33 1 2 PlCA2 is an output PIPAO PIPA7 are inputs J4 none J3 1 2 1 PlCA2 is an output PlPAO PlPA7 are outputs J4 1 2 1 NOTE 1 Factory installed jumper placement 2 3 3 Port 1 Direction Headers J5 J6 Headers J5 and J6 together control the direction of signal lines PICB2 and P1PBO P1PB7 The factory configuration of each header is shown in Figure 2 4 Table 2 3 lists the jumper configurations that determine whether the li
27. inter interface and a general purpose 16 bit parallel data I O port or two general purpose 16 bit parallel data I O ports Two PIA s with buffers on their peripheral sides are employed to implement the two parallel data ports In addition to having an 1 0 Channel interface each of the PIA s is capable of driving up to two of the I O Channel interrupt lines A front panel FAIL LED indicator is provided to indicate a module malfunction The user must provide a connector compatible I O Channel backplane or ribbon cable for DPP connection to the I O Channel master Refer to the I O Channel Specification Manual Motorola publication number M68RIOCS for interfacing and backplane information The user must also provide compatible cables for DPP connection via front panel connectors to peripheral devices 1 5 RELATED DOCUMENTATION The Input Output Channel Specification Manual M68RIOCS is applicable to the DPP 1 5 1 6 CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION INSTRUCTIONS 2 1 INTRODUCTION This chapter provides unpacking hardware preparation and installation instructions for the Dual Parallel Port Module 2 2 UNPACKING INSTRUCTIONS NOTE If shipping carton is damaged upon receipt request carrier s agent be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing or reshipping the eq
28. ith a Centronics printer a Apply power to the system equipment b Select the printer c If the VERSAmodule contains VERSAbug EPROM s then the VERSAbug 2 0 Printer Attach PA command can now be used d Figure 3 1 is a typical driver routine that can be used to drive the printer 3 1 6 MOTGROLA 16000 ASM VERSION SON Q 000012800 08881884 0000100A 00001010 00001014 0000101A 00001020 00001026 0000102C 0000192E 00001030 200901000 F801E1 00000000 00000004 00000002 00000006 00000002 00000004 20000090 00000024 00001000 00000000 2F08 40E7 41F909F801E1 11708038802 10BCODBFF 1 1 6 1 64 1 46DF 205F 4E73 1 39911 50 RTTLIO DRIVER SA 08 09 82 14 52 12 VMO2 RTTLIO PARALLEL PORT 1 INITIALIZATION ROUTINE IE HE TEE HE 4 IE MI HE HEHE TE HE 4 E FE SIDE PERIPHERAL DATA REC FROM BASE SIDE PERIPHERAL DATA REG FROM BASE SIDE CONTROL REGISTER FROM BASE SIDE DATA DIRECTION REG FROM BASE SIDE DATA DIRECTION REG FROM BASE FUNCTION Initialize Parallel Port 1 of the RTTLIO for driving a printer k Jt HE 2 4 3 3 36 3 3 dE HE 3 2 dE 2 2 2 X 3 3 3 t 3E 1E 3E E 09 2 3E IE 2 5 dE dE 2 5 E 2 5 3 5 0 2 2 2 dE 1 dE RHR INPUT PARAMETERS NONE Me 4 3 3 3E 3 4E 3 96 4 SE 1 3E 3 HE IE
29. ivers Because these lines are buffered care must be taken to make the directions of the peripheral line coming from the PIA compatible with the direction of the buffer on that line CAl U8 40 and CBl U8 18 are buffered to become PICAl and 1 respectively Their buffers are always inputs as defined by the PIA therefore no buffer fight can ever exist on these lines CA2 U8 39 and CB2 U8 19 are buffered to become PICA2 and PICB2 respectively Each one can be programmed as an input or as an output in the PIA Each PIA TTL buffer is hardware strappable as an input or as an output Therefore the possibility of a buffer fight exists for one case only when the line is programmed as an output by the PIA and its TTL buffer is strapped as an input Consequently the programmed direction of the line and the strapped direction of the line should be the same For direction strapping see the port 1 information in Chapter 2 PAO PA7 are buffered to become P1PAO P1PA7 respectively The direction of each one of these lines is individually programmable within the PIA However the direction of their buffers is not individually strappable in hardware The buffers for these lines are strapped as either all inputs or as all outputs or they are strapped so that their direction is an input when CA2 is at a logic high or an output when CA2 is at a logic low The possibility for a buffer fight exists for any case in which a line is programmed as an output
30. m 7 40 in 188 mm 5 12 in 130 mm 0 83 in 21 mm TABLE 1 2 Peripheral Signal Specifications SIGNALS 1 CHARACTERISTIC SPECIFICATIONS PlPA0 PlPA7 High level input voltage 2 volts dc minimum P2PAO P2PA7 Low level input voltage 0 8 volts dc maximum P2PBO P2PB7 P1CA1 P1CB1 High level output voltage with 2 volts de minimum P2CA1 P2CB1 IOH 15 mA Low level output voltage with 0 5 volts dc maximum IOL 24 mA Off state output current with 10 uA maximum high level output voltage applied Off state output current with 200 uA maximum low level output voltage applied High level input current with 20 uA maximum VIH 2 7 volts dc Low level input current with 0 2 mA maximum VIL 0 4 volts dc NOTE 1 Refer to schematic diagram Peripheral signals P1CA2 P1CB2 P2CA2 and P2CB2 have the same specifications except that the off state characteristics do not apply Any of the signals that are configured as inputs except PXCAl and PXCBl should not be allowed to float therefore any input signals not driven by the peripheral should be held in either a high state or a low state 1 4 1 4 GENERAL DESCRIPTION The DPP is an 1 0 Channel compatible dual printer interface module This module conforms to the single wide VME board form factor and connects to the 1 0 Channel with a 64 pin DIN standard connector The DPP is used to expand the resources of an I O Channel master to include two printer interfaces one pr
31. ment in your operating environment GROUND THE INSTRUMENT To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground The equipment is supplied with a three conductor ac power cable The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the equipment in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove equipment covers Component replacement and internal adjust ments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present USE CAUTION WHEN EXPOSING OR HANDLING THE CRT Breakage of the C
32. ne P2CA2 is an input P2PA0 P2PA7 are outputs J9 1 2 3 4 J8 none P2CA2 is not used P2PAO P2PA7 are inputs J9 none J8 1 2 P2CA2 is an output P2PA0 P2PA7 are inputs J9 none J8 1 2 1 P2CA2 is an output P2PA0 P2PA7 are outputs J9 1 2 1 NOTE 1 Factory installed jumper placement 2 6 2 3 5 Port 2 Direction Headers J10 J11 Headers J10 and 111 together control the direction of signal lines P2CB2 and P2PBO P2PB7 The factory configuration of each header is shown in Figure 2 6 Table 2 5 lists the jumper configurations that determine whether the lines are inputs or outputs J10 J11 FIGURE 2 6 Port 2 Direction Headers J10 J11 TABLE 2 5 Headers J10 and 711 Configurations HEADER PINS JUMPER CONNECTED REMARKS J10 none P2CB2 is not used P2PBO P2PB7 are outputs Jll 1 2 J10 none P2CB2 is not used P2PBO P2PB7 are inputs when U10 19 CB2 is high and outputs when 010 19 CB2 is low J11 2 3 J10 none P2CB2 is an input P2PBO P2PB7 are inputs J11 3 4 210 none P2CB2 is an input P2PBO P2PB7 are outputs Jil 1 2 3 4 J10 none P2CB2 is not used P2PBO P2PB7 are inputs J11 none J10 1 2 1 P2CB2 is an output P2PB0 P2PB7 are inputs J11 none 1 J10 1 2 P2CB2 is an output P2PB0 P2PB7 are outputs 1 2 NOTE 1 Factory installed jumper placement 2 7 2 3 6 Interrupt Select Headers J12 J13 Headers J12 and J13 together determine which PIA signal or signals 12012 IRQ1
33. nes are inputs or outputs J5 J6 FIGURE 2 4 Port 1 Direction Headers J5 J6 TABLE 2 3 Headers J5 and J6 Configurations HEADER PINS JUMPER CONNECTED REMARKS J5 none P1CB2 is not used PIPBO PIPB7 are outputs J6 1 2 J5 none P1CB2 is not used P1PBO P1PB7 are inputs when U8 19 CB2 is high and outputs when U8 19 CB2 is low J6 2 3 J5 none P1CB2 is an input PlPBO PlPB7 are inputs J6 3 4 J5 none P1CB2 is an input PIPBO PIPB7 are outputs J6 1 2 3 4 JS none PlCB2 is not used P1PBO P1PB7 are inputs J6 none J5 1 2 1 PlCB2 is an output PIPBO PIPB7 are inputs J6 none 1 J5 1 2 P1CB2 is an ouput PlPBO PlPB7 are outputs J6 1 2 NOTE 1 Factory installed jumper placement 2 5 2 3 4 Port 2 Direction Headers J8 J9 Headers J8 and J9 together control the direction of signal lines P2CA2 and P2PA0 P2PA7 The factory configuration of each header is shown in Figure 2 5 Table 2 4 lists the jumper configurations that determine whether the lines are inputs or outputs J8 J9 FIGURE 2 5 Port 2 Direction Headers J8 J9 TABLE 2 4 Headers J8 and J9 Configurations HEADER PINS JUMPER CONNECTED REMARKS J8 none P2CA2 is not used P2PA0 P2PA7 are outputs J9 1 2 J8 none P2CA2 is not used P2PA0 P2PA7 are inputs when U10 39 CA2 is high and outputs when U10 39 CA2 is low J9 2 3 J8 none P2CA2 is an input P2PAO P2PA7 are inputs J9 3 4 J8 no
34. ns o oa Headers J8 and J9 Configurations Headers 110 and 7111 Configurations Headers J12 and J13 Configurations 00000000000000000000 Header J14 Configurations weccccccccccvcccccccccvccsececes Header J15 Configurations sooo DPP Module Register 345055085 gt 777 I O Channel Timing Signal Characteristics Peripheral Timing Signal Characteristics I O Connector Pl Pin Assignments Peripheral Connectors Jl and J16 Pin Assignments DPP Module Parts LiSt 0000000000000000000000000000000000 ii Page 5 1 5 1 5 1 5 1 5 1 5 1 1 2 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 10 2 11 2 13 3 2 4 2 4 3 4 7 4 8 5 7 5 9 1 3 1 4 2 3 2 4 2 5 2 6 2 7 2 9 2 10 2 11 4 4 4 6 4 7 5 2 5 4 5 5 CHAPTER 1 GENERAL INFORMATION 1 1 INTRODUCTION This manual provides general information hardware preparation and installation instructions operating instructions functional description and support information for the MVME410 Dual Parallel Port Module referred to as DPP throughout this manual The DPP is shown in Figure 1 1 1 2 FEATURES Features of the DPP are listed below Motorola I O Ch
35. ost important are given in Table 4 3 Refer to Figure 4 4 for the related timing diagrams TABLE 4 3 Peripheral Timing Signal Characteristics TIMING PARAMETER VALUE IN NANOSECONDS NUMBER DESCRIPTION TYPICAL MAX 1 Control output pulse width 250 2 Rise and fall time for PXCB1 PXCB2 N A 3 Delay time PXCAl active transition 1036 to PXCA2 poSitive transition 4 Delay time data valid to PXCB2 14 negative transition 5 Control output pulse width 250 6 Delay time PXCBl active transition 1036 to PXCB2 positive transition 7 Interrupt input pulse time 500 8 Interrupt response time 1025 4 7 READ MODE PXCA2 CONDITIONS CONTROL REGISTER A BIT 5 CRA 5 CRA 3 1 CRA 420 READ MODE PXCAI X PXCA2 CONDITIONS CRA 5 1 CRA 3 CRA 4 0 FIGURE 4 4 Peripheral Side Timing Signal Diagram Sheet 1 of 3 WRITE MODE PXPBO PXPB7 O PXCB2 CONDITIONS CRB 5 CRB 3 I CRB 4 0 NOTE CB2 GOES LOW AS A RESULT OF THE POSITIVE TRANSITION OF E WRITE MODE PXCB2 CONDITIONS CRB 5 CRB 3 1 CRB 4 0 FIGURE 4 4 Peripheral Side Timing Signal Diagram Sheet 2 of 3 WRITE MODE PXCBI PXCB2 CONDITIONS 68 8 5 CRB 3 CRB 420 INT RESPONSE 4 gt PXCBI 2 INTX 8 NOTE INTX THE 1 0 CHANNEL INTERRUPT INT I INT 4 THAT IS DRIVEN BY IROX B ASSUMES THE INTERRUPT ENABLE BITS ARE SET FIGURE 4 4 Peripheral Side Timing Signal Diagram Sheet 3 of 3 4 10 CHAPTER 5 SUPPORT INFORMATION 5 1 INTRODUCT
36. ress 4 3 2 Access Control Logic The access control logic provides an asynchronous 1 0 Channel to a synchronous MC68B21 interface The interface operation is transparent to software on the I O Channel master 4 1 4 3 3 Interrupt Logic Each of the two PIA s has two lines IRQlA and 22013 and IRQ2A and IRQ2B One or more of these signals can be strapped to drive one of the 0 Channel interrupt lines INT1 INT4 The various combinations are controlled by interrupt select headers J12 and J13 see Chapter 2 If a port is connected to a printer it may be software configured to drive IRQ1A when the printer gives an acknowledge and or to drive IRQ1B when the printer indicates a fault condition Interrupts cannot be caused by the BUSY PAPER OUT or SELECT lines from the printer They are brought in only as peripheral data inputs to the B side of the PIA PARALLEL BUS 2 PARALLEL BUS 1 8 DATA P1 P1 CAI A DATA P1 B DATA P2 lg P2CA1 A DATA P2 v O N D gt PORT 1 PIA AND BUFFERS AND BUFFERS CONTROL MO CHANNEL INTERFACE DATA 8 DRESS 12 ERES INT1 INT4 CHANNEL CONNECTOR FIGURE 4 1 DPP Module Block Diagram 4 2 The DPP is jumper selectable to appear at any 10 byte block of memory in this area FIGURE 4 2 I O Channel Memory Map 4 3 0100 SOOFO 500120 50020 50000 50080 50020 0090 008
37. ter buffer and initializes the logic Not used by all printers 10 50 even numbers 3 GND GROUND 5 PXCBl FAULT A low level input signal that indicates a printer fault condition such as paper empty light detect or a deselect condition Not used by all printers 7 41 Reserved N A 45 49 8 None No connection 9 PXPB7 N A 11 PXPB6 N A 13 PXPB5 N A 15 PXPB4 N A 17 PXPB3 N A 19 PXPB2 BUSY An input signal indicating that the printer cannot receive data 21 PXPBl OUT OF PAPER A high level input indicating the printer is out of paper 23 PXPBO SELECT A high level input signal indicating that the printer is selected 25 PXPA7 PERIPHERAL DATA LINE PD8 Output data to printer from PA7 of PIA 27 PXPA6 PERIPHERAL DATA LINE PD7 Same as pin 25 except bit A6 29 PXPA5 PERIPHERAL DATA LINE PD6 Same as pin 25 except bit AS 31 PXPA4 PERIPHERAL DATA LINE PD5 Same as pin 25 except bit A4 33 PXPA3 PERIPHERAL DATA LINE PD4 Same as pin 25 except bit A3 35 PXPA2 PERIPHERAL DATA LINE PD3 Same as pin 25 except bit A2 5 4 TABLE 5 2 Peripheral Connectors Jl and J16 Pin Assignments cont d PIN SIGNAL NUMBER MNEMONIC 37 PXPAl 39 PXPAO 43 PXCA2 47 PXCA1 REFERENCE DESIGNATION C1 C2 C3 C4 C5 C6 C7 C8 C9 DS1 Jl J2 J3 J5 J8 J10 J4 J6 J9 J11 J15 J7 J12 J13 J14 J16 SIGNAL NAME AND DESCRIPTION PERIPHERAL DATA LINE PD2 Same as pin 25 except bit Al PERIPHERAL DATA LINE PD
38. uipment 2 3 HARDWARE PREPARATION This section describes the hardware preparation of the DPP module prior to system installation The DPP has been factory tested for system operation and is shipped with factory installed jumpers These factory installed jumper connections should be verified to ensure that the components are properly configured for system operation The DPP is configured to interface the I O Channel master with Centronics printer compatible equipment There are 13 headers on the DPP as shown in Figure 2 1 They are J2 J6 and J8 Jl5 Table 2 1 lists each header its function and factory installed jumper configuration For signal names such as PICA2 etc refer to the schematic diagram 2 1 gt ET 6 6 FIGURE 2 1 J8 J u CC DPP Module Header Location Diagram HEADER NUMBER J2 J3 J4 J5 J6 J8 J9 J10 Jll Jl2 Jl3 Jl4 J15 LED monitor Port Port Port Port Port Port Port Port 1 2 P1CA2 PICA2 PICB2 PICB2 P2CA2 P2CA2 P2CB2 P2CB2 FUNCTION PIPAO PIPA7 P1PAO P1PA7 PlPBO PlPB7 P1PBO P1PB7 P2PAO P2PA7 P2PA0 P2PA7 P2PBO P2PB7 P2PBO P2PB7 Interrupt select Interrupt select Base address select LED control 2 3 1 LED Monitor Header J2 Header J2 is jumpered between pins 2 and 3 as shown in Figure 2 2 and should not be altered FIGURE 2 2 J2 LED Monitor Header J2 2 3 DPP Modul
39. urations that select the desired condition J15 FIGURE 2 9 LED Control Header J15 TABLE 2 8 Header J15 Configurations PINS CONNECTED REMARKS 2 3 1 FAIL LED is functionally operational and signal P1PB7 is disabled 1 2 Signal P1PB7 is enabled and FAIL 3 4 LED is disabled NOTE 1 Factory installed jumper placement If J6 1 and 2 are connected and J15 2 and 3 are connected then J15 4 should be connected to J15 3 2 11 2 4 INSTALLATION INSTRUCTIONS When the DPP has been configured as desired by the user it is ready to be installed in a VME chassis or an I Omodule 5 slot card cage 2 4 1 Installation in VME Chassis The DPP is installed in a VME chassis as follows Ae b Ce d Ce 2 4 2 Turn all equipment power OFF CAUTION CONNECTING MODULES WHILE POWER IS APPLIED MAY RESULT IN DAMAGE TO COMPONENTS ON THE MODULE Insert DPP in any single width card slot Secure in place with two captive screws Peripheral connection to DPP port 1 and or port 2 is accomplished by mating a double row 50 pin female ribbon connector such as a 3M 3425 5000 to male connectors Jl and J16 on the DPP front panel as shown in Figure 2 10 Printer cable assembly Motorola part number M68KVMPRICE can be used Connect the other end of the ribbon cable to a printer with a Centronics printer compatible interface Equipment power may be turned ON Installation in 5 Slot I Omodule Card Cage The DPP is installe
40. ured to have the DPP occupy any 10 byte block within the first 100 byte block of the 1 0 Channel memory map see Figure 4 2 Each of the two ports appears twice in the 10 byte block The factory configuration of the header is shown in Figure 2 8 Table 2 7 lists the jumper configurations that select the desired location within the I O Channel memory map 2 9 FIGURE 2 8 Base Address Select Header J14 TABLE 2 7 Header J14 Configurations PINS CONNECTED REMARKS 1 2 3 4 5 6 7 8 Base address is 00 1 2 3 4 5 6 Base address 15 0 1 2 3 4 7 8 Base address is 20 1 2 3 4 Base address is 30 1 2 5 6 7 8 Base address is 0 1 2 5 6 Base address is 50 1 2 7 8 Base address is 0 1 2 Base address is 70 3 4 7 5 6 7 8 Base address is 80 3 4 5 6 Base address is 90 3 4 7 8 Base address is SAO 3 4 Base address is SBO 5 6 7 8 Base address is C0 5 6 Base address is 0 7 8 Base address is SEO none 1 Base address is 0 NOTE 1 Factory installed jumper placement 2 10 2 3 8 LED Control Header J15 The configuration of header 215 controls front panel FAIL LED indicator DS1 and Signal P1PB7 When the LED can be turned on by the LED signal the P1PB7 signal is disabled refer to the schematic diagram in Chapter 5 When the P1PB7 signal is enabled the LED signal is low and will hold the LED off The factory configuration of the header is shown in Figure 2 9 Table 2 8 lists the jumper config
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