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1. PIN 1 INDEX DETAIL X 7 SEATING PLANE Y does not include dambar protrusion of 0 08 max per side JEDEC STANDARD ISSUE DATE YY MM DD DRAWING NO SPZG NO ITEM NO MS 022 03 04 16 06605 0001 4 SPZG001006 001 02 Fig 2 1 PMQFP100 1 Plastic Metric Quad Flat Package 100 leads 14 x 20 x 2 7 mm Ordering code QB Weight approximately 1 7 g Micronas June 11 2003 6251 617 1Al 9 CDC1631F E ADVANCE INFORMATION 2 2 Pin Assignment Pin Functions Pin Pin Pin Functions Bus LCD Port Port Basic No No Basic Port Port LCD Bus Mode Mode Special Out Special In Function Function Special In Special Out Mode Mode SEG7 3 U7 3 91 90 04 0 WP7 5 4 0 ADB8 SEG7 2 U7 2 92 89 U4 1 SEG4 1 ADB9 SEG7 1 U7 1 93 88 U4 2 SEG4 2 ADB10 SEG7 0 07 0 94 87 04 3 SEG4 3 ADB11 UVSS 95 86 U4 4 UARTO RX WP8 SEG4 4 ADB12 UVDD 96 85 04 5 UARTO TX SEG4 5 ADB132. UART1 and UART2 Synchronous Serial 2 SPIO and SPI1 1 SPIO 2 SPIO and SPI1 1 SPIO 2 SPIO and SPI1 Peripheral Interfaces Full CAN modules V2 0B 3 CANO CAN1 and CAN2 with 1 CANO with 3 CANO and with 1 CANO with 2 CANO and CAN1 with 256 byte 256 byte object RAM each 256 byte object 256 byte object RAM each 256 byte object object RAM each LCANO0009 LCANOOOF RAM LCANOO09 RAM LCANOOOF 0009 DIGITbus 1 master module 1 master module 1 master module Input amp Output Universal Ports select up to 52 I O or 48 LCD segment lines 2192 segments able as 4 1 mux LCD in groups of two configurable as I O or LCD Segment Backplane lines or Digital I O Ports Universal Port Slew Rate HW preselectable Stepper Motor Control 5 Modules 24 dl dt controlled ports Modules with High Cur rent Ports 8 bit PWM Modules 5 Modules PWMO PWM1 3 Modules 5 Modules PWMO PWM1 2 Modules 5 Modules PWMO PWM1 PWM2 PWM3 and PWM4 PWMO PWM1 PWM2 PWM3 and PWM4 PWMO PWM1 PWM2 PWM3 and PWM4 PWM2 Audio Module with auto v decay SW selectable Clock out 2 Polling Flash Timer Out put 1 High Current Port output operable in Power Saving Mode NOLLVINHOJNI 3ONVAGV 1 11 91909 IVL 2Z19 1929 008 LL eunr SEUOJOIN Table 1 1 CDC16xxF Family Feature List continued This Device Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC
3. ADB7 SEG3 7 T2 OUT U3 7 97 84 U4 6 CC2 IN CC1 OUT SEG4 6 ADB14 ADB6 SEG3 6 CC1 OUT U3 6 98 83 U4 7 CC1 IN SEG4 7 ADB15 ADB5 SEG3 5 U3 5 99 82 U5 0 CCO IN CO1 SEG5 0 ADB4 SEG3 4 TO OUT WPO U3 4 100 81 U5 1 INT TEST IN 0 SEG5 1 ADB3 5 CC2 OUT U3 3 1 80 U5 2 LCD CLK IN AM PWM SEG5 2 ADB2 SEG3 2 U3 2 2 79 U5 3 LCD SYNC IN AM OUT SEG5 3 ADB1 SEG3 1 CO1 U3 1 3 78 U5 4 IRQ SEG5 4 ADBO SEG3 0 U3 0 4 77 U5 5 ABORTQ coo SEG5 5 SEG6 7 CANO TX MULTI TEST IN U6 7 5 76 U5 6 PINT3 WP6 PWM2 SEG5 6 SEG6 6 PINT1 OUT CANO RX WP1 U6 6 6 75 U5 7 PINT3 PINTO OUT SEG5 7 SEG6 5 T1 OUT SPI0 D IN U6 5 7 100 91 90 81 74 U2 0 SEG2 0 ADB16 5 6 4 SPI0 D OUT U6 4 8 73 U2 1 SEG2 1 ADB17 TEST 9 72 U2 2 SEG2 2 ADB18 RESETQ 10 71 U2 3 SEG2 3 ADB19 XTAL2 11 70 U2 4 SEG2 4 ADB20 XTAL1 12 69 U2 5 SEG2 5 ADB21 VSS 13 68 U2 6 SEG2 6 ADB22 VDD 14 67 U2 7 SEG2 7 ADB23 SEG6 3 SPIO CLK OUT SPIO CLK IN 06 3 15 66 AVSS SEG6 2 T1 OUT PINT2 IN WP5 U6 2 16 65 AVDD SEG6 1 LCD CLK OUT PINT1 IN WP4 U6 1 17 64 VREF SEG6 0 LCD SYNC OUT PINTO IN WP3 U6 0 18 63 PO 1 digital input WEQ 5 1 7 017 19 62 P0 2 P0 2 digital input CEQ SEG1 6 WP2 01 6 20 61 P0 3 PO 3 digital input ITSTOUT SEG1 5 LCD CLK OUT 01 5 21 31 40 41 50 60 P0 4 P0 4 digital input SEG1 4 LCD SYNC OUT Ut 4 22 59 PO 5 PO 5 digital input PH2 BP3 01 3 23 58 P0 6 P0 6 Compar inp OEQ BP2 U1 2 24 57 P0 7 BE BP1 01 1 25 56 P0 8 RDY BPO ITSTOUT U1 0 26 55 P0 9 STOPCLK SM
4. Design value only the actually observable hysteresis may be lower due to system activity and related supply noise 4 When the ERM is active this time value is increased by 0 121 fXTAL e g 15 125 ns at 8 MHz When the ERM is active this time value is decreased by 0 121 fXTAL e g 15 125 ns at 8 MHz 9 Measured with external clock Add 170 at 4 MHz 200 uA at 10 MHz for operation on typical quartz with SR3 XTAL 0 Oscillator RUN mode a 14 June 11 2003 6251 617 1Al Micronas ADVANCE INFORMATION CDC1631F E 3 4 Recommended Crystal Characteristics See Chapter 3 4 of document CDC16xxF E Automotive Controller Family User Manual CDC1605F E Automotive Controller Emulator Specification 2AI Micronas June 11 2003 6251 617 1Al 15 CDC1631F E ADVANCE INFORMATION 4 CPU RAM ROM and Banking MCM Alternative Native PQFP100 phys addr Bottom Boot Config log addr DE log adar Reserved 002000 008000 OOO 0200007 2012000 7777777 Reserved 20800002 982000 mirrored ROM FFFFFF Fig 4 1 Address Map 16 June 11 2003 6251 617 1Al Micronas ADVANCE INFORMATION CDC1631F E 5 Core Logic 5 1 Control Register CR The Control Register CR serves to configure the ways by which certain system resources are accessed during opera tion The main purpose is to obtain a variable system config uration during IC test Upon each HIGH transition on the RESETQ p
5. are not software pro grammable The data in address locations OOFFAOH through OOFFC3H were used to define their respective hard wired Hardware Options during mask production and can only be altered by changing a production mask for this IC For verification purposes it is recommended to have an application code in ROM that runs with FLASH parts as well which is automatically the case if FLASH parts have been used for software develop ment and tests before This implies reading of loca tions OOFFAOh through 00FFC3h directly after reset to activate the Hardware Options settings in FLASH and EMU parts as well 18 June 11 2003 6251 617 1Al Micronas ADVANCE INFORMATION CDC1631F E Micronas June 11 2003 6251 617 1Al CDC1631F E ADVANCE INFORMATION 7 Data Sheet History 1 Advance Information CDC1631F E Automotive Control ler June 11 2003 6251 617 1 First release of the advance information Originally created for the HW ver sion CDC1631F E1 Micronas GmbH Hans Bunte Strasse 19 D 79108 Freiburg Germany P O Box 840 D 79008 Freiburg Germany Tel 49 761 517 0 Fax 49 761 517 2174 E mail docservice micronas com Internet www micronas com Printed in Germany Order No 6251 617 1Al All information and data contained in this data sheet are without any commitment are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create an
6. of the reset pulse which is output at pin RESETQ following an internal reset If pin TEST is 1 the first reset after power on is short The following resets are as programmed by RESLNG If pin TEST is 0 all resets are long TSTTOG TEST Pin Toggle Table 5 2 This bit is used for test purposes only If TSTTOG is true in IC active mode pin TEST can toggle the multifunction pins between Bus mode and normal mode Table 5 4 Some commonly used settings for address location OOFFF3h A copy is automatically transferred to the CR during RESET exit Code TEST Operation Mode Pin FFh 0 Stand alone with internal ROM or Flash ABh 1 External program storage connected to multifunction pins in Bus Mode Micronas June 11 2003 6251 617 1Al 17 CDC1631F E ADVANCE INFORMATION 6 Hardware Options 6 1 Functional Description Hardware Options are available in several areas to adapt the IC function to the host system requirements clock signal selection for most of the peripheral modules from fosc to fosc 2 plus some internal sig nals see table in Chapter Hardware Options of document CDC16xxF E Automotive Controller Family User Manual interrupt source selection for interrupt inputs 5 6 7 13 14 and 15 Special Out signal selection for some U and H ports Rx Tx polarity selection for SPI and UART modules U Port Slow Mode selection In ROM parts Hardware Options
7. 1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Timers amp Counters 16 bit free running CCCO with 3CAPCOM counters with Capture Compare modules 16 bit timers 1 TO 8 bit timers 2 T1 and T2 Real Time Clock with v hours minutes and sec onds Miscellaneous Scalable layout in CAN v v RAM and ROM Various HW options selectable at random Most options SW programmable copy from user program storage during system start up Mask pro grammed according to user specifica tion Most options SW programmable copy from user program storage during system start up Mask programmed according to user specification Core Bond Out v Supply Voltage 4 5 V to 5 5 V Temperature Range Tease 40 C to 105 Tamb 40 C to 85 Package Type Ceramic PMQFP100 1 Ceramic PMQFP100 1 177PGA 0 65mm pitch 177PGA 0 65mm pitch Bonded Pins 176 100 176 100 1 11 91909 NOLLVINHOHNI 3ONVAGV SEUOJIN 219 1629 6002 LL eunr 1 2 Abbreviations AM CAN CAPCOM CPU DMA ERM IR LCD PO6COMP PINT PSM PWM RTC SM SPI TO T1 T2 UART Audio Module Controller Area Network Module Capture Compare Module Central Processing Unit Direct Memory Access Module EMI Reduction Module Interrupt Controller Liquid Crystal Display Module P0 6 Alarm Comparator Port I
8. 5 HVpp 0 7 V lin Input Current all Inputs 0 2 mA lo Output Current U Ports 5 5 mA H Ports 60 60 mA loshsl Duration of Short Circuit in Port SLOW U Ports except indefinite S Mode to UVSS or UVDD U3 2 in DP Mode Tj Junction Temperature under Bias 45 115 C Ts Storage Temperature 45 125 C P max Maximum Power Dissipation 0 8 W 1 This condition represents the worst case load with regard to the intended application Stresses beyond those listed in the Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only Functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions Characteristics of this specification is not implied Exposure to absolute maximum ratings conditions for extended periods may affect device reliability June 11 2003 6251 617 1Al Micronas ADVANCE INFORMATION CDC1631F E 3 2 Recommended Operating Conditions Table 3 2 UVSS HVSS1 HVSS2 AVSS 20V Symbol Parameter Pin Name Min 1 Unit Vpp Supply Voltage VDD 4 5 5 5 5 V Port Supply Voltage UVDD Analog Supply Voltage AVDD HVpp SM Supply Voltage 1 HVDD1 4 75 5 5 25 V SM Supply Voltage 2 HVDD2 AVpp Voltage Difference between VDD VDD AVDD 0 2 0 2 V and AVDD resp UVDD UVDD dAVpp AVDD Ripple Peak t
9. ADVANCE INFORMATION MICRONAS CDC1631F E Automotive Controller ES E GS BITIA lt MICRONAS CDC1631F E ADVANCE INFORMATION Contents Page Section Title 3 1 Introduction 3 1 1 Features 7 1 2 Abbreviations 9 2 Package and Pins 9 2 1 Package Outline Dimensions 10 2 2 Pin Assignment 11 2 3 External Components 12 3 Electrical Characteristics 12 3 1 Absolute Maximum Ratings 13 3 2 Recommended Operating Conditions 14 3 3 Characteristics differing from Characteristics described in document CDC16xxF E Auto motive Controller Family User Manual 15 3 4 Recommended Crystal Characteristics 16 4 CPU RAM ROM and Banking 17 5 Core Logic 17 5 1 Control Register CR 18 6 Hardware Options 18 6 1 Functional Description 20 7 Data Sheet History 2 June 11 2003 6251 617 1Al Micronas SEUOJIN IV L 419 LG29 00 LL eunr 1 Introduction The IC is a single chip controller for use in automotive applications The CPU on the chip is an upgrade of the 65C02 with 16 bit internal data and 24 bit address bus The chip consists of timer counters an interrupt controller a multichannel A D converter a stepper motor and LCD driver CAN interfaces and PWM outputs Family User Manual 6251 606 2Al 1 1 Features Table 1 1 CDC16xxF Family Feature List This document provides device specific information General information on ope
10. AsE 40 C to 105 fXTAL 10 MHz Symbol Parameter Pin Name Min 1 Unit Test Conditions Package Ripjc Thermal Resistance from 7 3 CM Junction to Case Thermal Resistance from 51 CM Junction to Ambient Supply Currents CMOS levels on all Inputs no Loads on Outputs difference between any two VDDs within 0 2 V Ippr VDD FAST Mode Supply VDD 19 mA Current lbs VDD SLOW Mode Supply VDD 1 2 mA all Modules OFF 2 6 Current Ippp VDD DEEP SLOW Mode VDD 0 9 all Modules OFF 9 Supply Current IDDI VDD IDLE Mode Supply VDD 50 75 uA 4 MHz 9 Current 60 90 fagi 10 MHz 6 70 100 uA internal RC oscill Ippw VDD WAKE Mode Supply VDD 0 30 50 uA Current Ulppa UVDD Active Supply Cur UVDD 0 3 mA no Output Activity rent LCD Module ON Alppa AVDD Active Supply Cur AVDD 0 2 0 4 mA ADC ON ERM OFF rent 1 2 mA ERM ON fyqq 8 4MHz Alppq Quiescent Supply Current AVDD 0 1 10 ADC and ERM OFF Ulppq UVDD 0 1 10 uA no Output Activity LCD Module OFF Hlppq Sum of all 0 1 20 uA no Output Activity HVDD1 SM Module OFF HVDD2 1 Typical values describe typical behavior at room temperature 25 C unless otherwise noted with typical Recommended Operating Conditions applied derived from device characterization not 100 tested 2 Value may be exceeded with unusual Hardware Option setting 3
11. B1 H1 5 27 54 H2 0 SMC COMP SMC2 VPQ SMB1 H1 4 28 53 H2 1 SMC2 VPA SMB2 H1 3 29 52 H2 2 5 VDA SMB2 SMB COMP H1 2 30 51 H2 3 SMC1 DB7 SME1 PWM2 H1 1 31 50 H2 4 WP9 PWMO DB6 SME1 PWMO H1 0 32 49 H2 5 Pol HVDD1 33 48 HVSS2 HVSS1 34 47 HVDD2 DB5 SME2 H0 5 35 46 H3 0 PWM1 DB4 SME2 SME COMP H0 4 36 45 H3 1 DB3 5 1 H0 3 37 44 H3 2 SMD COMP SMD2 DB2 5 1 H0 2 38 NC not connected 43 H3 3 SMD2 DBI SMA2 H0 1 39 leave vacant 42 H3 4 SMD1 DBO SMA2 SMA COMP H0 0 40 41 H3 5 SMD1 Fig 2 1 Pin Assignment for PMQFP100 1 Package 10 June 11 2003 6251 617 1Al Micronas ADVANCE INFORMATION CDC1631F E 2 3 External Components 100 nto 150 n 45V C 100nto150n 45V System C Ground 5 V Analog V 4 7k Resetq 9 System Ground Fig 2 2 Recommended external supply and quartz connection for low electromagnetic interference EMI To provide effective decoupling and to improve EMC behav ior the small decoupling capacitors must be located as close to the supply pins as possible The self inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self resonant fre quency of the decoupling network A frequency too low will reduce decoupling effectiveness increase RF emissions and may affect device operation adversely XTAL1 an
12. d XTAL2 quartz connections are especially sensi tive to capacitive coupling from other printed circuit board signals It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor to prevent fast RESETQ transients from being coupled into XTAL2 to prevent XTAL2 from coupling into RESETQ and to guarantee a time constant of gt 200 us sufficient for proper Wake Reset functionality Micronas June 11 2003 6251 617 1Al 11 CDC1631F E ADVANCE INFORMATION 3 Electrical Characteristics 3 1 Absolute Maximum Ratings Table 3 1 UVss HVss HVss2 AVss 0V Symbol Parameter Pin Name Min Max Unit Vsup Core Supply Voltage VDD 0 3 6 0 V Port Supply Voltage UVDD Analog Supply Voltage AVDD SM Supply Voltage 1 HVDD1 SM Supply Voltage 2 HVDD2 AVpp Voltage Difference between VDD and VDD AVDD 0 5 0 5 V AVDD resp UVDD UVDD IsuP Core Supply Current VDD VSS 100 100 mA Port Supply Current UVDD UVSS lAsup Analog Supply Current AVDD AVSS 20 20 mA IHsup SM Supply Current HVDD1 HVSS1 380 380 mA T 105C Duty Factor 0 71 HVDD2 HVSS2 Vin Input Voltage U Ports UVss 0 5 UVpp 0 7 V XTAL RESETQ TEST PO Ports UVss 0 5 AVppt0 7 V VREF H Ports HVgs 0
13. in internal hardware reads data from the address location OOFFF3h and stores it to the CR The state of the TEST pin at that time specifies which program storage source is accessed for this read Table 5 1 Control byte source TEST Control byte source 0 or NC internal ROM standard for stand alone operation 1 external via multifunction pins in Bus MFM Multifunction Pin Mode Table 5 2 Table 5 2 TSTTOG and MFM usage in mask ROM parts mode for test purposes only The system will thus start up according to the configuration defined in address location OOFFF3h automatically copied to register CR TSTTOG MFM TEST pin Multifunction Pins 0 0 x Bus mode 1 0 0 Bus mode 1 normal mode x 1 x normal mode TSTROM TestROM Table 5 3 IROM Internal ROM Table 5 3 Table 5 3 TSTROM and IROM usage in mask ROM parts TSTROM IROM selected program storage 1 1 internal ROM CR Control Register 0 internal TestROM 7 6 5 4 3 2 1 0 x 0 external via Multifunction pins IRESLNGITSTTOG x TSTROM IROM IRAM ICPU 1t Bus mode Value of 00FFF3h Res IRAM Internal RAM r w1 Enable internal RAM r wO Disable internal RAM RESLNG Reset Pulse Length ICP Internal CPU r w1 Pulse length is 4095 FxTAL n is ie E fhe Pulse length is 16 FxTaL r wO Disable internal CPU This bit specifies the length
14. nterrupt Module Power Saving Module 8 Bit Pulse Width Modulator Module Real time Clock Stepper Motor Control Module Serial Synchronous Peripheral Interface 16 Bit Timer 0 8 Bit Timers 1 and 2 Universal Asynchronous Receiver Transmitter NOLLVINHOJNI 3ONVAGV 1 11 91909 CDC1631F E ADVANCE INFORMATION Reset Alarm Sea Patch Module RESETQ Watchdog Banking Clock G 650816 XTAL1 XTAL2 F x Oscillator CPU EL Power Saving 16 Inputs Module Interrupt Controller Audio Module 2KB RAM VREF FE AVDD Multiplier AVSS 8 by 8 bit 10 Bit ADC PPort0 LCD Control Bit Timer 1 1 Bit Timer 2 EP Bit s 1 Bit CAPCOM 2 M 16 16 81 Timer 0 Timer 0 UART 0 a Out 0 T Out 1 l Br Bit CAPCOM 0 Stepper Motor 6 E I 6 8 Bit PWM 2 n 1 8 PWM 0 N a I 6 2 8 Bit PWM 1 T HVDD1 HVSS1 HVDD2 LHVSS2 Scalable within wide limits CAN 0 Fig 1 1 Block Diagram of CDC1631F E June 11 2003 6251 617 1Al UVDD UVSS s8 n qi a 6 8 a 5 ai e Ji n 2 SI t n n e n Hi ar Jr Micronas ADVANCE INFORMATION CDC1631F E 2 Package and Pins 2 1 Package Outline Dimensions
15. o Peak AVDD 200 mV TxTAL XTAL Clock Frequency XTAL1 4 12 MHz XTAL Clock Frequency XTAL1 4 10 MHz using ERM Tj Junction Temperature 40 110 C Vi Low Input Voltage U Ports 0 51 Vpp V H Ports PO Ports TEST Vin High Input Voltage U Ports 0 86 V H Ports PO Ports TEST Reset Active Input Voltage RESETQ 0 9 V Reset Active Input Voltage during RESETQ 0 6 V Power Saving Modes and Wake Reset RVim Reset Inactive and Alarm Active RESETQ 1 6 2 1 V Input Voltage RVin Reset Inactive and Alarm Inactive RESETQ 2 9 V Input Voltage WRVin Reset Inactive during Power RESETQ UVpp V Saving Modes 0 4V VREF ADC Reference Input Voltage VREF 2 56 V POV PO ADC Input Port Input Voltage PO Ports 0 VREFi V Clock Input from External Generator Clock Input Low Voltage XTAL1 0 2 Vpp V XVin Clock Input High Voltage XTAL1 0 8 Vpp V DxrAL Clock Input High to Low Ratio XTAL1 0 45 0 55 1 Typical values describe typical behavior at room temperature 25 unless otherwise noted with typical Recommended Operating Conditions applied derived from device characterization not 100 tested Micronas June 11 2003 6251 617 1AI 13 CDC1631F E ADVANCE INFORMATION 3 3 Characteristics differing from Characteristics described in document CDC16xxF E Automotive Controller Family User Manual Table 3 3 UVgg HVss1 HVs52 AVgg 0 V 4 5 V lt Vpp AVpp UVpp lt 5 5 V 4 75 V lt gt lt 5 25 V Tc
16. rating the IC can be found in the document CDC16xxF E Automotive Controller This Device Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Core CPU 16 bit 65C816 featuring software compatibility with its 8 bit NMOS and CMOS 6500 series predecessors CPU Active Operation FAST SLOW and DEEP SLOW FAST and SLOW Modes Power Saving Modes WAKE and IDLE CPU Inactive EMI Reduction Mode selectable in FAST mode Oscillators 4 MHz to 12 MHz Quartz RC 4 MHz to 12 MHz Quartz RAM 6 KB 2KB 6 KB 2 75 KB 4 6 KB ROM ROMIess 256 KB Flash 64 KB ROMIess 256 KB Flash 90 KB 128 KB 216 KB external pro bottom boot external pro bottom boot gram storage configuration gram storage configuration with up to internal 2 KB with up to internal 2 KB 16 MB internal Boot ROM 16 MB internal Boot ROM 2 KB Boot 2 KB Boot ROM ROM Multiplier 8 by 8 bit v NOLLVINHOHNI 3ONVAGV 1 11 91909 IV L 419 LG29 008 LL eunr SEUOJOIN Table 1 1 CDC16xxF Family Feature List continued This Device Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Digital Watchdog v Central Clock Divider v Interrup
17. t Controller 16 inputs 15 priority levels expanding NMI Port Interrupts including 4 inputs Slope Selection Port Wake Up Inputs 10 including Slope Level Selection Patch Module 10 ROM locations 5 ROM loca 10 ROM locations 5 ROM loca 6 ROM locations tions tions Boot System allows in system downloading of allows in system downloading of code and data into RAM via serial code and data into RAM via serial link link Analog Reset Alarm Combined Input for Regulator Input Supervision Clock and Supply Supervision v 10 bit ADC charge balance type 9 channels 5 channels selectable as digital input ADC Reference VREF Pin Comparators PO6COMP with 1 2 AVDD reference LCD Internal processing of all analog voltages for the LCD driver 1 11 91909 NOLLVINHOHNI 3ONVAGV SEUOJIN IV L 419 LG29 008 LL eunr Table 1 1 CDC16xxF Family Feature List continued puts This Device Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Communication DMA 1 DMA Channel for serving the gt 1 Channel for serving the 1 DMA Channel for serving the Graphics Bus interface Graphics Bus interface Graphics Bus interface UART 3 UARTO UART1 and UART2 1 UARTO 3 UARTO UART1 and UART2 1 UARTO 3 UARTO
18. y liability Any new issue of this data sheet invalidates previous issues Product availability and delivery are exclusively subject to our respective order confirmation form the same applies to orders based on development samples deliv ered By this publication Micronas GmbH does not assume responsibil ity for patent infringements or other rights of third parties which may result from its use Further Micronas GmbH reserves the right to revise this publication and to make changes to its content at any time without obligation to notify any person or entity of such revisions or changes No part of this publication may be reproduced photocopied stored on a retrieval system or transmitted without the express written consent of Micronas GmbH 20 June 11 2003 6251 617 1Al Micronas
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