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1. ES 24 4 5 PO HH 26 CHAPTER5 BOARD SETUP AND TEST DESIGNS 27 5 1 B atd 56 55 202252 a 27 5 2 Test Designs Using Stratix GX FPGA Development Kit Platform 28 6 APPENDIX M 35 6 1 Revision HiStoty en HERE ERR ERNEUT EE ELTE sania SS EE HE ER TH EET ET CREE EUER UR 35 VAS n UNI Iu REM 35 2 Terasic DUAL XAUI User Manual www terasic com Chapter 1 Introduction This board is intended to be used by customers to implement and design 10G Ethernet systems based on transceiver host boards that support XAUI interfaces This mezzanine card is intended to be part of an openly sold Development Kit and can be bundled with packages of Software and IP Cores It will have 2 full duplex 10G SFP channels with a XAUI backend interface The XAUI to SFP HSMC provides a hardware platform for developing embedded systems based on XAUI based Altera GX based devices At the time of this document the devices that support XAUI are Arria GX Arria II GX Stratix II GX and Stratix IV GX 1 1 Features Figure 1 1 shows the photo of the Dual XAUI to SFP HSMC board The important features are listed below Two independent XAUI interfaces from the HSMC to th
2. DUAL XAUI User Manual World Leading FPGA Based Products and Design Services 1010101010001010101010101010101001010101110101001010100100101 1010101010001010101010101010101001010101110101001010100100 1010101010001010101010101 010101001010101110101001010100100101010101010010101010101 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010 010101001011010101101100010H110100010 t f 7 1010101010001010101010101010101001010101110101001010100100 10101010100010101010101010101010010101011101010010101001001010101010100101010101010101010101001011010 ter www terasic com Copyright 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS Z CHAPTER 1 INTRODUCTION o 3 1 1 Mn 3 I2 Getting 4 CHAPTER 2 ARCHITECTURE o n sss 5 A1 Block Diagram ere a E E a N 6 CHAPTER3 DESCRIPTION B n 8 3 1 HSMG Expansion COnnectoE tac ERR RI ee 8 4 17 4 1 Featured Device BCM8727 etie a besos eda eo siete tenir 17 4 2 General User Input Output nini er net e YR i saa ee e Ed 22 43 23 4 4 Memory DEVICES C
3. USER LED G6 USER LED G7 USER LED RO USER LED RI USER LED R2 USER LED R3 USER LED R4 USER LED R5 USER LED R6 USER LED R7 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS User LED Green 6 User LED Green 7 User LED Red 0 User LED Red 1 User LED Red 2 User LED Red 3 User LED Red 4 User LED Red 5 User LED Red 6 User LED Red 7 www terasic com Chapter 4 Components This section introduces all of the important components on the XAUI to SFP HSMC board 4 1 Featured Device BCM8727 U6 The BCM8727 is dual channel 10 GbE SFI to XAUI transceiver that incorporates an Electronic Dispersion Compensation EDC equalizer supporting line card applications The 8727 is a multi rate PHY targeted for SMF or copper twin ax applications interfacing to both limiting based and linear based SFP and SFP modules 8727 is fully compliant to 10 GbE IEEE 802 3aq standard and also supports 1000BASE X for 1 GbE operation The 8727 is developed using an all DSP high speed front end providing the highest performance and most flexibility for line card designers An on chip microcontroller implements the control algorithm for the DSP core All signal names and 8727 pin positions are located in Table 3 1 Table 4 1 BCM8727 Schematic Net Connections Board Reference Signal Name IO Standard Function Pin U6 K9 CONFIGO 1 CMOS Configuration mode channel 1 bit 0 Int
4. 17 LEDs 0 2 and 4 6 should all be ON and LEDs 3 and 7 should be OFF 18 Unplug the cable from any SFP port 19 LEDs 3 and 7 should turn ON NOTE If the test doesn t pass for example with the 12 meter SFP cable it is ok to try different settings of USER DIPSW T7 3 in step 12 above to make the test pass To test the daughter card LEDs observe they follow LEDs 15 8 on the host board in step 8 above Pressing user pb 0 reverses the color of USER LEDS 0 3 on the daughtercard Pressing user pb 1 reverses the color of USER LEDS 4 7 on the daughtercard MDIO Functionality Check 1 Open the Quartus II hsmc loopback qar file 2 After completing one of the test designs above open the signal tap design a With the hsmc loopback qar project open locate the signal tap file named hsmc loopback sfp2 mdio stp or possibly hsmc loopback sfp3 mdio stp This file can be found under the Files tab in the Project Navigator window within Quartus II b Make sure the JTAG is setup 3 Set USER DIPSW 7 0 XXXX01 11 to read back chip rev chip ID and microcode ID 4 In the upper left tool bar in Signaltap click on the Run Anaylsis button 5 Press and release user pb 1 6 Press and release user pb 2 7 Scroll to the net named mdio read data w 8 Zoom in to view the values and find the value of 8727h 33 Terasic DUAL XAUI User Manual www terasic com www teragic com dick to insert time bar 1664
5. Signal Name IO Standard Function Reference U18 1 GND GND Address bus bit 0 U18 2 GND GND Address bus bit 1 U18 3 GND GND Address bus bit 2 U18 4 GND GND Ground U18 5 SMB SDA 3 3V Serial Data U18 6 SMB SCL 3 3V Serial Clock U18 7 GND GND Write Protect U18 8 VCC 3 3V 3 3V Power Supply 24 Terasic DUAL_XAUI User Manual www terasic com www teragic com JAN DTE RYAN Table 4 5 256 Kbit Serial SP EEPROM 25LC256IST Pinout Board Signal Name IO Standard Function Reference U14 1 SS NI 3 3V Chip Select Active low UIS SS N2 014 2 MISO1 3 3 Serial Data Output U15 2 MISO2 U14 3 Pull up resistor to 3 3V Write Protect Active low U15 3 3 3V U14 4 GND GND Ground U15 4 U14 5 MOSII 3 3V Serial Data Input U15 5 MOSI2 014 6 SCKI 33V Serial Clock Input U15 6 SCK2 U14 7 Pull up resistor to 3 3V Hold Input Active low U15 7 3 3V 14 8 3 3 3 3V Supply Voltage U15 8 Table 4 6 4 Kbit Serial I2C EEPROM 24LC08B Pinout Board Signal IO Standard Function Reference U10 1 GND GND Address bus bit 0 U11 1 U10 2 Pull up resistor to 3 3V Address bus bit 1 U112 3 3V U10 3 Pull down GND Address bus bit 2 011 3 resistor to GND U10 4 GND GND Ground U11 4 U10 5 SMBSDAI1 3 3V Serial Data 011 5 SMBSDA2 U10 6 SMBSCLI 3 3 Serial Clock U11 6 SMBSCL2 U10 7 Pull down GND Write Protect DTI resistor to GND U10 8 VCC 3 3V 3 3V Power Supply U11 8 25 Terasic DUAL_XAUI User Manual www ter
6. 1600 1536 1472 1408 134 1280 1216 1152 H 5 4000 0008 12h Ah interface x2 mdio interface 12 data 0000h 0000h 00908 1088 0001h 1792 1728 8727h terface _x2 mdio_irterface__sfp_12 mdio_read_data_w mdio interface x2 mdio intertace stp 12 pre m 0 _ 2 jnerface sfp 12Irst release cr 00h interface x2 mdio interface sfp 12lstate I TIT T Figure 5 4 Signal Tap Display 34 Terasic DUAL XAUI User Manual www terasic com www Ceragic com Chapter 6 Appendix 6 1 Revision History Version Change Log V1 0 Initial Version Preliminary 6 2 Copyright Statement Copyright O 2010 Terasic Technologies All rights reserved 35 Terasic DUAL User Manual www terasic com www
7. La fx uu Lx Hs C jo Co 51 N 101 159 3 3 19 MISO1 11 SCK1 SS 4 031 SFP TXR310 OPOUTLVL OPINLVL 4 2 PRTAD1 PRTAD01 PRTAD02 USER_LED_R3 USER_LED_R2 USER LED R1 USER LED RO 55338 CLKIN www terasic com AN DE RYA Table 3 1 shows the pin description of the HSMC connector Table 3 1 The pin mappings of the HSMC connector HSMC Schematic Net Connections Board Reference Signal Name IO Standard Function Pin J6 125 CONFIGO 1 CMOS Configuration mode channel 1 bit 0 Internally pulled down 127 CONFIGO 2 CMOS Configuration mode channel 2 bit 0 Internally pulled down 131 CONFIGI 1 CMOS Configuration mode channel 1 bit 1 Internally pulled down 133 CONFIGI 2 CMOS Configuration mode channel 2 bit 1 Internally pulled down 137 GPIOO 1 LVTTL Programmable general purpose I O 110 GPIOO 2 LVTTL Programmable general purpose I O 139 GPIO1 1 LVTTL Programmable general purpose I O 140 GPIOI 2 LVTTL Programmable general purpose I O 68 LASII CMOS Link Alarm Status Interrupt Channel 1 128 LASD CMOS Link Alarm Status Interrupt Channel 2 116 MDC2 CMOS Management Data Clock for single device default 114 MDIO2 CMOS Management Data Clock channel 2 for dual MDIO device 41 MISO1 LVTTL Master Input Slave Output Channel 1 101 MISO2 LVTTL Master Input S
8. SFI TX N2 SFI TX SFI TX P2 LVTTL LVTTL LVTTL CMOS CMOS CMOS CMOS CMOS CMOS Analog Analog Differential CML Differential CML Differential CML Differential CML Analog Analog LVTTL LVTTL LVTTL Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Terasic DUAL XAUI User Manual www teragic com differential clock PHY Reset Active low PMD Loss of Signal Channel 1 PMD Loss of Signal Channel 2 Channel 1 PHY Address LSB Channel 2 PHY Address LSB PHY Address bit 1 PHY Address bit 2 PHY Address bit 3 PHY Address bit 4 Not used Not used Analog Recovered Clock from CDR Channel 1 negative leg Analog Recovered Clock from CDR Channel 2 negative leg Analog Recovered Clock from CDR Channel 1 positive leg Analog Recovered Clock from CDR Channel 2 positive leg Receiver Common Mode Input channel 1 Receiver Common Mode Input channel 2 SPI ROM Clock for channel 1 SPI ROM Clock for channel 2 SPI ROM Boot Enable active high Receiver Serial Data channel 1 negative leg Receiver Serial Data channel 2 negative leg Receiver Serial Data channel 1 positive leg Receiver Serial Data channel 2 positive leg Transmitter Serial Data channel 1 negative leg Transmitter Serial Data channel 2 negative leg Transmitter Serial Data channel 1 positive leg Transmitter Serial Data chan
9. co XAUI Parallel Transmit Data Input Channel 2 lane C positive leg XAUI Parallel Transmit Data Input Channel 2 lane B positive leg XAUI Parallel Transmit Data Input Channel 2 lane A positive leg Clock Output Enable active low Enables the S15334C clock buffer HSMC Differential Clock output to the host board negative leg HSMC Differential Clock output to the host board positive leg HSMC Present active low Illuminates the HSMC Present LED on the host board when this card is plugged into the host JTAG TDO Looped back to TDI pin 38 JTAG TDI Looped back to TDO pin 37 No Connect for single MDIO device default Management Data Clock channel 1 for dual MDIO device No Connect for single MDIO device default Management Data I O channel 1 for dual MDIO device Rate Select 0 for SFP module receiver channel 1 pulled high via R59 This sets the input rate gt 4 25 GBd pull low for rates lt 4 25 GBd Rate Select 0 for SFP module receiver channel 2 pulled high via R3 This sets the input rate gt 4 25 GBd pull low for rates lt 4 25 GBd CLKIN to 515334 device GND pin on 515334 drive this pin low Optional clock pin when using 515338 EEPROM SCL for future use EEPROM SDA for future use User LED Green 0 User LED Green 1 User LED Green 2 User LED Green 3 User LED Green 4 User LED Green 5 www terasic com JAN DTE 146 144 91 89 85 83 151 149 145 143 www Ceragic com
10. lane D negative leg XAUI Parallel Transmit Data Input Channel 1 lane C negative leg XAUI Parallel Transmit Data Input Channel 1 lane B negative leg XAUI Parallel Transmit Data Input Channel 1 lane A negative leg XAUI Parallel Transmit Data Input Channel 1 lane D positive leg XAUI Parallel Transmit Data Input Channel 1 lane C positive leg XAUI Parallel Transmit Data Input Channel 1 lane B positive leg XAUI Parallel Transmit Data Input Channel 1 lane A positive leg XAUI Parallel Transmit Data Input Channel 2 lane D negative leg XAUI Parallel Transmit Data Input Channel 2 lane C negative leg XAUI Parallel Transmit Data Input Channel 2 lane B negative leg XAUI Parallel Transmit Data Input Channel 2 lane A negative leg XAUI Parallel Transmit Data Input Channel 2 lane D positive leg www terasic com JAN DTE RAN 80 158 156 160 37 38 56 54 55 115 95 155 34 33 92 90 86 84 152 150 XAUI TX 2 1 XAUI TX 2P2 XAUI TX 2P3 CLK OE HSM CLK N HSM CLK P HSM PSNTN JTAG TDO TDI JTAG TDO TDI MDCI MDIOI SFP TXRSIO SFP TXRS20 SI5338 CLKIN SI5338 SCL SMB SCL SMB SDA USER LED G0 USER LED Gl USER LED G2 USER LED G3 USER LED G4 USER LED G5 Differential CML Differential CML Differential CML LVCMOS CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Terasic DUAL XAUI User Manual www Ceragic
11. leg www terasic com JAN DTE RYAN 16 12 14 10 31 27 23 19 29 25 21 17 15 11 13 XAUI RX 2N0 XAUI RX 2NI XAUI RX 2N2 XAUI RX 2N3 XAUI RX 2P0 XAUI RX 2P1 XAUI RX 2P2 XAUI RX 2P3 XAUI TX INO XAUI TX INI XAUI TX IN2 XAUI TX IN3 XAUI TX 1 0 XAUI TX XAUI TX 1 2 XAUI TX 1P3 XAUI TX 2N0 XAUI TX 2NI XAUI TX 2N2 XAUI TX 2N3 XAUI TX 2 0 Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Terasic DUAL User Manual www C XAUI Parallel Receive Data Output Channel 2 lane D negative leg XAUI Parallel Receive Data Output Channel 2 lane C negative leg XAUI Parallel Receive Data Output Channel 2 lane B negative leg XAUI Parallel Receive Data Output Channel 2 lane A negative leg XAUI Parallel Receive Data Output Channel 2 lane D positive leg XAUI Parallel Receive Data Output Channel 2 lane C positive leg XAUI Parallel Receive Data Output Channel 2 lane B positive leg XAUI Parallel Receive Data Output Channel 2 lane A positive leg XAUI Parallel Transmit Data Input Channel 1
12. to Channel Loopback Test Design Procedure The same steps are followed for the Channel Loopback test above except to Step 20 1 Set USER DIPSW 7 0 00000100 Flip XAUI Lanes 2 Plug in the Dual XAUI to SFP HSMC into the HSMA port on the Stratix IV GX FPGA development 3 Plug in SFP modules into each SFP port on the Dual XAUI to SFP HSMC 4 Plug in two 10G Optical Loopback cables compatible with the SPF modules 5 Power on the Stratix IV GX FPGA development kit board 6 Program the Stratix IV GX FPGA development kit with the hsmc loopback sof On the Stratix IV GX FPGA development kit 30 Terasic DUAL XAUI User Manual www terasic com www Ceragic co m JAN DTE 7 Press and release cpu resetn S2 8 Press and release user pb 0 the rx is now ready to search for a prbs seed pattern 9 Press and release both cpu resetn user pb 1 and user pb 2 simultaneously Resets the 8727 device and SFP module s 10 Reset Module It should be OK to skip this one but include these steps if your board is failing A Set USER DIPSW 7 0 00000000 Program MDIO to reset module B Press and release user pb 1 C Press and release user pb 2 11 To Flip XAUI Lanes A Set USER DIPSW 7 0 00000100 Program MDIO to flip XAUI lanes B Press and release user pb 1 C Press and release user pb 2 12 Set pre emphasis for example if using an SFP 12 meter cable A USER DIPSW 7 0 11100110
13. B Press and release user pb 1 C Press and release user pb 2 13 Press and release cpu resetn 14 LEDs 15 8 will display the heartbeat pattern indicating the FPGA fabric is functional 15 LED 0 and 4 should be ON and LEDs 1 3 and 5 7 should be OFF 16 Press and release user pb 0 Start Test 17 LEDs 0 2 and 4 6 should all be ON and LEDs 3 and 7 should be OFF 18 Unplug the RX optical cable from the channel 1 SFP port 19 LED 3 should turn ON 20 Unplug the TX optical cable from the channel 1 SFP port 21 LED 7 should turn ON NOTE If the test doesn t pass for example with the 12 meter SFP cable it is ok to try different settings of USER DIPSW T7 3 in step 12 above to make the test pass To test the daughter card LEDs observe they follow LEDs 15 8 on the host board in step 8 above Pressing user pb 0 reverses the color of USER LEDS 0 3 on the daughtercard Pressing user pb 1 reverses the color of USER LEDS 4 7 on the daughtercard to SFP Module 10G Channel to Channel Electrical Loopback This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform The Stratix IV GX transmits 3 125G XAUI signals on the four lanes of channel 1 and the return signal is received on channel 2 Also the Stratix IV GX transmits 3 125G XAUI signals on the four lanes of channel 2 and the return signal is received on channel 1 The Stratix IV GX FPGA sends a 3 125G XAUI signal on four transmit lanes from
14. DC1 56 1 SFP TXR310 58 sz E PLO8B1 60 OPOUTLVL LA8I1 OPINLVL PLO8B1 PRTAD4 LABI1 es PRTAD3 69 PRTAD2 TXCNOFF1 PRTAD1 75 MOD 81 EE P PRTADO1 CLK OE 80 PRTADO2 82 81 USER LEO G3 USER LED R3 USER LED G2 86 USER LED R2 USER LEO G1 USERLED R1 USER LED GO USER LED RO 96 55338 Figure 3 2 Pin outs of Bank 2 on the HSMC connector 10 Terasic DUAL_XAUI User Manual www terasic com www teragic com INPUTS to the RSH connector FROM clock buffer OPRXLOB2 102 101 OPTXPLT2 SNB8PDSEL2 PCDRLK2 121 PLO8B2 125 LA812 127 NVMPROT 131 TXCNOFF2 MCD_AB82 GFIO1_2 USER_LED_G7 143 USER_LED_G6 146 145 USER LED G5 149 USER LED G4 151 HSM CLK 156 HSM CLK N 158 P8NTn 160 R117 HSM P8NTn Q8H 060 165 GND 2 1 166 GND 22 167 GND 2 3 168 GND 2 4 169 GND 3 1 lt I NC Figure 3 3 Pin outs of Bank 3 on the HSMC connector 161 GND 162 163 GND 164 GND 14 170 GND 32 171 GND 3 3 172 GND 34 1 Terasic DUAL XAUI User Manual www Cerasic com 105 3 3V 10 111 33V 11 117 3 3 12 123 3 13 129 3 3V 14 135 3 3V 15 141 33V 16 147 33V 17 153 3 3V 18 u Nm j
15. Loopback This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform The Stratix IV GX transmits 3 125G XAUI signals on the four lanes of channel 1 and the return signal is received on channel 2 Also the Stratix IV GX transmits 3 125G XAUI signals on the four lanes of channel 2 and the return signal is received on channel 1 The Stratix IV GX FPGA sends a 3 125G XAUI signal on four transmit lanes from channel 1 to the 8727 device which then outputs a 10G signal to the SFP module on channel 1 With an SFP module and optical cable installed as shown in Figure 5 2 the SFP sends an optical 10G signal from SFP channel 1 output to SFP channel 2 input The SFP module converts 10G optical signal into an electrical 106 signal and sends it to the BCM8727 PHY The PHY then converts the 10G signal into four 3 125G XAUI output signals and transmits them on channel 2 to the Stratix IV GX device through the HSMC connector The same process is followed for the channel 2 transmitter to channel 1 receiver 3 125G 10G 10G FIBER OUT SFP1 output to SFP2 input 22 xau 2220 FIBER IN 42 Optical Cables t 20 5 2 output to 4 SFP_TX2 gt XAUI_TX_CH2 FIBER OUT SFP1 input XAUI RX CH2 qth Re FIBER_IN Figure 5 2 XAUI to SFP Channel to Channel Loopback Test Setup XAUI to SFP Module 10G Channel
16. Stratix IV GX device through the HSMC connector 3 125G 10G 10G FIBER OUT 44 gt SEPIA SFP SFP1 Loopback 24 Rx FIBER_IN Optical Cables PHY 4 SFP TX2 FIBER OUT J b 2 SFP SFP2 Loopback 26 CH2 SL FIBER IN Figure 5 1 XAUI to SFP Channel Optical Loopback Test Setup XAUI to SFP Module 10G Channel Optical Loopback Test Design Procedure 1 Set USER DIPSW 7 0 00000100 Flip XAUI Lanes 2 Plug in the Dual XAUI to SFP HSMC into the HSMA port on the Stratix IV GX FPGA development 3 Plug in SFP modules into each SFP port on the Dual to SFP HSMC 4 Plug in two 10G Loopback cables compatible with the SPF modules 28 DUAL XAUI User Manual www terasic com www Cerasic co m N DTE RYAN 5 Power Stratix IV GX FPGA development kit board 6 Program the Stratix GX FPGA development kit with the hsmc loopback sof On the Stratix IV GX FPGA development kit 7 Press and release cpu resetn S2 8 Press and release user pb 0 the rx is now ready to search for a prbs seed pattern 9 Press and release both cpu resetn user pb 1 and user pb 2 simultaneously Resets the BCM8727C device and SFP module s 10 Reset Module It should be OK to skip this one but include these steps if your board is failing A Set USER DIPSW 7 0 00000000 Program MDIO to res
17. TTL LVTTL LVTTL LVTTL CMOS CMOS Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Terasic DUAL XAUI User Manual www teragic com PMD CMU Lock Detect Channel 1 PMD CMU Lock Detect Channel 2 PHY Reset Active low PMD Loss of Signal Channel 1 PMD Loss of Signal Channel 2 Channel 1 PHY Address LSB Channel 2 PHY Address LSB PHY Address bit 1 PHY Address bit 2 PHY Address bit 3 PHY Address bit 4 SPI ROM Clock for channel 1 SPI ROM Clock for channel 2 SPI ROM Boot Enable active high Optical Transmitter Enable channel 1 Optical Transmitter Enable channel 2 2 wire Speed Select channel 1 2 wire Speed Select channel 2 2 wire Write Enable SPI ROM Chip Select channel 1 SPI ROM Chip Select channel 2 Transmit Driver On or Off channel 1 Transmit Driver On or Off channel 2 XAUI Parallel Receive Data Output Channel 1 lane D negative leg XAUI Parallel Receive Data Output Channel 1 lane C negative leg XAUI Parallel Receive Data Output Channel 1 lane B negative leg XAUI Parallel Receive Data Output Channel 1 lane A negative leg XAUI Parallel Receive Data Output Channel 1 lane D positive leg XAUI Parallel Receive Data Output Channel 1 lane C positive leg XAUI Parallel Receive Data Output Channel 1 lane B positive leg XAUI Parallel Receive Data Output Channel 1 lane A positive
18. a Output Channel 1 lane B negative leg XAUI Parallel Receive Data Output Channel 1 lane A negative leg XAUI Parallel Receive Data Output Channel 1 lane D positive leg XAUI Parallel Receive Data Output Channel 1 lane C positive leg XAUI Parallel Receive Data Output Channel 1 lane B positive leg XAUI Parallel Receive Data Output Channel www terasic com JAN DTE RYAN D18 F18 H18 K18 D17 F17 H17 K17 K2 H2 F2 D2 F1 D1 B12 B14 B16 B18 A12 XAUI RX 2N0 XAUI RX 2NI XAUI RX 2N2 XAUI RX 2N3 XAUI RX 2P0 XAUI RX 2P1 XAUI RX 2P2 XAUI RX 2P3 XAUI TX INO XAUI TX INI XAUI TX IN2 XAUI TX IN3 XAUI TX 1 0 XAUI TX XAUI TX 1 2 XAUI TX 1P3 XAUI TX 2N0 XAUI TX 2NI XAUI TX 2N2 XAUI TX 2N3 XAUI TX 2 0 CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential Terasic DUAL XAUI User Manual WWW CeFBSIC COm 1 lane A positive leg Parallel Receive Data Output Channel 2 lane D negative leg XAUI Parallel Receive Data Output Channel 2 lane C negative leg XAUI Parallel Rec
19. asic com www teragic com AN DTE RAN 4 5 Power Power is supplied to the board from the 12V supply of the host board Figure 4 2 shows the power distribution 0144 3 3V 10 1 0V Linear 3 3V 1 1 DVDD a LT3080 um VCCT 1 DVDD 0 500 SFP_VCCR_1 U12 Pu Linear U13 LT3080 3 3V S00mV Switcher i 3 3V_SFP_2 LT3501 SPF_VCCT_2 07 VCCR 2 1 0 Linear 1V PVDDADC1 LT3080 ay PVDDADC1 500mV U5 1 0 Linear 1V_PVDDADC2 LT3080 PVDDADC2 500 98 U2 079080 33v DYDD 0 75A 0 2A S00mV 700 Figure 4 2 Power Tree of Dual XAUI to SFP HSMC Board 26 www Ceragic Terasic DUAL_XAUI User Manual www terasic com Chapter 5 Board Setup and Test Designs Two host platforms that this board has successfully been tested on are the Stratix IV GX production device development kit and the Arria II GX development kit The Arria II GX development kit only utilizes the HSMC port A so this kit can only use SFP port 1 The Arria GX development kit 6G edition allows the use of HSMC port A and port B so that it may be possible to use both SFP ports 1 and 2 However the 6G edition kit has not been tested in hardware 5 1 Board Setup Before powering on the host board on make sure to install a shunt on J13 and J14 Then plug the HSMC board into the host board This board was designed so that 515338 or the 515334 default may be
20. ata Input Channel CML 2 lane B positive leg A18 XAUI TX 2P3 Differential XAUI Parallel Transmit Data Input Channel CML 2 lane A positive leg 4 2 General User Input Output This board has eight dual color Green Red surface mount LEDs are provided for general purpose use A logic 0 is driven on the I O port to turn the LED ON logic 1 15 driven on the I O port to turn the LED OFF Table 4 2 lists the assignment for each users LED and describes board reference description signaling standard and schematic name for the USER LEDs located on the HSMC These are all 2 5V LVCMOS signals Each channel has a bi colored LED The 4 states of each bi color LED Off green red orange can be used to identify received or transmitted rate or any other state that the user would like The LEDs are driven from user logic located inside the host device on the host board Table 4 2 User LED Pinout Green Red Board Signal IO Standard Function Reference D5 USER LED RO 3 3V User defined USER LED GO 33 User defined D6 USER LED 3 3V User defined USER LED G1 33 User defined D7 USER LED R2 33 User defined USER LED G2 33V User defined D8 USER LED R3 33V User defined USER LED G3 3 3V User defined DI USER LED R4 3 3 User defined USER LED G4 33V User defined D2 USER LED R5 33V User defined USER LED G5 33V User defined D3 USER LED R6 33V User defined USER LED G6 33 User defined D4 USER LED R7 33 User defin
21. channel 1 to the 8727 device which then outputs 10G signal to the SFP module on channel 1 With an SFP module coax electrical cable installed such as the Amphenol part number SF SFPP2EPASS 002 or SFSFPP2EPASS 012 as shown in Figure 5 3 the SFP sends an electrical 10G signal from SFP channel 1 output to SFP 31 Terasic DUAL XAUI User Manual www terasic com www teragic com JAN DTE RYAN channel 2 input The SFP module receives the 10G electrical and sends it to the BCM8727 PHY The PHY then converts the 10G signal into four 3 125G XAUI output signals and transmits them on channel 2 to the Stratix IV GX device through the HSMC connector The same process is followed for the channel 2 transmitter to channel 1 receiver 3 125G 10G 10G 4 SFP_TX1 CABLE_IN 4 54 Passive Copper Cable 4 SFP_TX2 CABLE_IN S 4 4 gt TX 2 4 54 XAUI 2 4S Figure 5 3 XAUI to SFP Channel to Channel Electrical Loopback Test Setup to SFP Module 10G Channel to Channel Electrical Loopback Test Design Procedure The same steps are followed for the Channel Loopback test above except Step 20 from above is removed The reason this is that the electrical cable unplugs for transmit and receive at the same time 1 Set USER DIPSW 7 0 00000100 Flip XAUI Lanes 2 Plug in the Dual XAUI to SFP HSMC into t
22. e BCM8727 Two independent SFI interfaces from the 8727 to SFP cages MDIO interfaces 12 EEPROM for HSMC identification and user data 515334 clock generator 15625MBHz reference available on SMA connectors and through the HSMC connector 4 bi color LEDS for each channel 8 total bi color LEDs DUAL XAUI User Manual www terasic com www teragic com Figure 1 1 Picture of the Dual XAUI to SFP HSMC board 1 2 Getting Help Here are some places to get help if you encounter any problem Email to support terasic com e Taiwan amp China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 Terasic DUAL_XAUI User Manual www Ceragic com www terasic com Chapter 2 Architecture This chapter describes the architecture of the Dual XAUI to SFP HSMC board including block diagram and components User LEDs 10G SFP Interface 8727 06 05 08 91 32 HSMC J16 EEPROMs U10 U11 U14 U15 RCLKP N J3 J6 Clock PII U16 PWR SHDN J15 Switching Power Config Select CLK External Clock Out Supply U13 Settings J9 J12 Enable J14 J7 P J8 n SCL J13 Figure 2 1 The Dual XAUI to SFP HSMC PCB and component diagram A photograph of the Dual XAUI to SFP HSMC board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components DUAL XAUI User Manual www teras
23. ed USER LED G7 3 3V User defined 22 Terasic DUAL XAUI User Manual www terasic com www teragic com ANU S RYAN 4 3 Clocks Figure 4 1 shows to SFP HSMC board clock diagram PEXTCLK156 P PEXTCLK156 n 1 25MHz XTAL 1751 CLKO P 929 CLKO n 90 gt Control CLK0 P CLKO n Figure 4 1 XAUI to SFP HSMC Clocking Diagram 23 Terasic DUAL_XAUI User Manual www terasic com www AN DTE RYA All signal names and clock pin positions are located in Table 4 3 Table 4 3 XAUI to SFP HSMC Board Clock Distribution Signal Frequency Signal Originates Signal Propagates To From 156 25 HSM CLK P U16 13 J16 156 MHz HSM CLK N U16 14 J16 158 U6 T10 156 25 PEXTCLK156 P U16 17 U6 R10 MHz PEXTCLK156 016 18 156 25 CLKO P U16 21 J7 MHz CLK0 N U16 22 18 4 4 Memory Devices This section describes the board s memory interface support and their signal names types and connectivity relative to the interface they are connected to The board has the following memory interfaces 8K EEPROM connected to HSMC 2 x 256K SPI EEPROM connected to BCM8727 and HSMC 2 x 4K EEPROM connected to BCM8727 and SFP The 8K EEPROM intended use is to identify the board when it is plugged into the host board All signal names and memory pin positions are located in Table 4 4 Table 4 5 and Table 4 6 Table 4 4 8 Kbit Serial I2C EEPROM 24LC08B Pinout Board
24. eive Data Output Channel 2 lane B negative leg XAUI Parallel Receive Data Output Channel 2 lane A negative leg XAUI Parallel Receive Data Output Channel 2 lane D positive leg XAUI Parallel Receive Data Output Channel 2 lane C positive leg XAUI Parallel Receive Data Output Channel 2 lane B positive leg XAUI Parallel Receive Data Output Channel 2 lane A positive leg XAUI Parallel Transmit Data Input Channel 1 lane D negative leg XAUI Parallel Transmit Data Input Channel 1 lane C negative leg XAUI Parallel Transmit Data Input Channel 1 lane B negative leg XAUI Parallel Transmit Data Input Channel 1 lane A negative leg XAUI Parallel Transmit Data Input Channel 1 lane D positive leg XAUI Parallel Transmit Data Input Channel 1 lane C positive leg XAUI Parallel Transmit Data Input Channel 1 lane B positive leg XAUI Parallel Transmit Data Input Channel 1 lane A positive leg XAUI Parallel Transmit Data Input Channel 2 lane D negative leg XAUI Parallel Transmit Data Input Channel 2 lane C negative leg XAUI Parallel Transmit Data Input Channel 2 lane B negative leg XAUI Parallel Transmit Data Input Channel 2 lane A negative leg XAUI Parallel Transmit Data Input Channel www terasic com N DTE CML 2 lane D positive leg Al4 XAUI TX 2 1 Differential XAUI Parallel Transmit Data Input Channel CML 2 lane C positive leg A16 XAUI TX 2P2 Differential XAUI Parallel Transmit D
25. el 2 for dual MDIO device Master Input Slave Output Channel 1 Master Input Slave Channel 2 Module Absent Channel 1 Module Absent Channel 2 Master Output to Slave Input channel 1 Master Output to Slave Input channel 2 No Connect for single MDIO device default Management Data Clock channel 1 for dual MDIO device No Connect for single MDIO device default Management Data I O channel 1 for dual MDIO device Non volatile Memory Select Non volatile Memory Protect Optical Control Input Level Optical Control Output Level Optical Receiver Loss of Signal Channel 1 Optical Receiver Loss of Signal Channel 2 Optical Transmitter Fault Indicator Channel 1 Optical Transmitter Fault Indicator Channel 2 Optical Module Reset Channel 1 Optical Module Reset Channel 2 PMD CDR Lock Detect Channel 1 PMD CDR Lock Detect Channel 2 PMD CMU Lock Detect Channel 1 PMD CMU Lock Detect Channel 2 Reference Clock Channel negative leg of a differential clock Reference Clock Channel positive leg of a www terasic com JAN DTE RYAN E9 H5 H11 A10 A9 B9 C9 B10 C10 T14 R14 V1 V10 U1 V9 8 18 K5 MII H10 V7 16 V6 V15 V3 V12 V4 V13 PHYRESET PLOSBI PLOSB2 PRTADOI PRTADO2 PRTADI PRTAD2 PRTAD3 PRTAD4 RB CAL RB CAL VSS RCLKN 1 RCLKN 2 RCLKP 1 RCLKP 2 RDICM 1 RDICM 2 SCKI SCK2 SER BOOT SFI RX NI SFI RX N2 SFI RX Pl SFI P2 SFL TX NI
26. ernally pulled down CONFIGO 2 CMOS Configuration mode channel 2 bit 0 Internally pulled down J9 CONFIGI 1 CMOS Configuration mode channel 1 bit 1 Internally pulled down 0 CONFIGI 2 CMOS Configuration mode channel 2 bit 1 Internally pulled down L9 GPIO0 1 LVTTL Programmable general purpose I O G13 GPIOO 2 LVTTL Programmable general purpose I O M9 GPIOI 1 LVTTL Programmable general purpose I O H13 2 LVTTL Programmable general purpose I O Terasic DUAL XAUI User Manual www terasic com www teragic com E7 K10 08 E8 G5 G12 G10 N8 F5 F12 G7 G8 MI G9 10 D10 L4 L12 H8 J14 K4 K12 H 12 G6 111 R10 T10 Terasic DUAL_XAUI User Manual www teragic com LASII LASD MDC2 MDIO2 MISOI MISO2 MOD ABSI MOD ABS2 MOSI MOSI2 NC MDC 1 NC MDIO 1 NVMAISEL NVMPROT OPINLVL OPOUTLVL OPRXLOSI OPRXLOS2 OPTXFLTI OPTXFLT2 OPTXRSTI 1 OPTXRSTI 2 PCDRLKI PCDRLK2 PCMULKI PCMULK2 PEXTCLK156_N PEXTCLKI56 CMOS CMOS CMOS CMOS LVTTL LVTTL CMOS CMOS LVTTL LVTTL CMOS CMOS LVTTL CMOS LVTTL LVTTL CMOS CMOS CMOS CMOS LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Link Alarm Status Interrupt Channel 1 Link Alarm Status Interrupt Channel 2 Management Data Clock single device default Management Data Clock channel 2 for dual MDIO device Management Data I O for single MDIO device default Management Data I O chann
27. et module B Press and release user_pb 1 C Press and release user_pb 2 11 To Flip XAUI Lanes A Set USER DIPSW 7 0 00000100 Program MDIO to flip XAUI lanes B Press and release user pb 1 C Press and release user pb 2 12 Set pre emphasis for example if using an SFP 12 meter cable A USER DIPSW 7 0 11100110 B Press and release user pb 1 C Press and release user pb 2 13 Press and release cpu resetn 14 LEDs 15 8 will display the heartbeat pattern indicating the FPGA fabric is functional 15 LED 0 and 4 should be ON and LEDs 1 3 and 5 7 should be OFF 16 Press and release user pb 0 Start Test 17 LEDs 0 2 and 4 6 should all be ON and LEDs 3 and 7 should be OFF 18 Unplug the RX optical cable from the channel 1 SFP port 19 LED 3 should turn ON 20 Unplug the RX optical cable from the channel 2 SFP port 21 LED 7 should turn ON NOTE If the test doesn t pass for example with the 12 meter SFP cable it is ok to try different settings of USER DIPSW T7 3 in step 12 above to make the test pass To test the daughter card LEDs observe they follow LEDs 15 8 on the host board in step 8 above Pressing user pb 0 reverses the color of USER LEDS 0 3 on the daughtercard Pressing user pb 1 reverses the color of USER LEDS 4 7 on the daughtercard 29 DUAL XAUI User Manual www terasic com www teragic com S RYAN to SFP Module 10G Channel to Channel Optical
28. he HSMA port on the Stratix IV GX FPGA development 3 Plug in SFP modules into each SFP port on the Dual XAUI to SFP HSMC 4 Power on the Stratix IV GX FPGA development kit board 5 Program the Stratix IV GX FPGA development kit with the hsmc loopback sof On the Stratix IV GX FPGA development kit 7 Press and release cpu resetn S2 8 Press and release user pb 0 the rx is now ready to search for a prbs seed pattern 9 Press and release both cpu resetn user pb 1 and user pb 2 simultaneously Resets the 8727 device and SFP module s 10 Reset Module It should be OK to skip this one but include these steps if your board is failing A Set USER DIPSW 7 0 00000000 Program MDIO to reset module B Press and release user pb 1 32 DUAL XAUI User Manual www terasic com www Cerasic co m JA DTE RYAN C Press and release user_pb 2 11 To Flip XAUI Lanes A Set USER DIPSW 7 0 00000100 Program MDIO to flip XAUI lanes B Press and release user pb 1 C Press and release user pb 2 12 Set pre emphasis for example if using an SFP 12 meter cable A USER DIPSW 7 0 11100110 B Press and release user pb 1 C Press and release user pb 2 13 Press and release cpu resetn 14 LEDs 15 8 will display the heartbeat pattern indicating the FPGA fabric is functional 15 LED 0 and 4 should be ON and LEDs 1 3 and 5 7 should be OFF 16 Press and release user pb 0 Start Test
29. ic com www Ceragic ANU S RYAN 2 1 Block Diagram Figure 2 2 shows the block diagram of the Dual XAUI to SFP HSMC board TXO RXO 8727 1 1 RX1 1 CLKO p n k 12V Figure 2 2 Block diagram of the Dual XAUI to SFP HSMC board The XAUI interfaces will be attached to the HSMC side of the card and the SFI side of the interface will be attached to the SFP optical modules on the opposite side of the board The lower HSMC channels 0 thru 3 are utilized for the XAUI connection for channel 0 and upper HSMC channels 4 thru 7 are utilized for the XAUI connection for channel 1 of the 10GE channel links DUAL_XAUI User Manual www terasic com JAN DTE RYAN Two SFP connectors and cages combined with a SFP optical module not provided with the board form the 10GE optical interface The SFP modules communicate with the BCM8727 via the serial SFI protocol The SFP interface connector is 20 pins Most SFP optical modules will contain status and configuration registers accessible through an I2C port Other signals will include loss of signal OPRXLOS 2 1 and module absent MOD ABS 2 1 An oscillator capable of generating 156 25MHz is supplied on the HSMC to provide the host board with a clean low jitter reference clock The clock also
30. installed in position U16 Table 5 1 XAUI to SFP HSMC Board Setup Board Reference J13 515338 SCL 3 3V When using the S15334C default this pin is a ground pin It must be pulled to GND When using the Si5338 device this pin is SCL 714 CLK OE 3 3V When using the 515334 default this pin 18 output enable OEB active low When pulled low all programmed outputs are active When using the Si5338 device this pin is SDA Signal Name IO Standard Function 27 Terasic DUAL XAUI User Manual www terasic com www teragic com ANU S RYAN 5 2 Test Designs Using Stratix IV GX FPGA Development Kit Platform to SFP Module 10G Channel Optical Loopback This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform The Stratix IV GX transmits and receives 3 125G XAUI signals on four transceivers for each of the two channels utilized For each channel the Stratix IV GX FPGA sends a 3 125G XAUI signal on four transmit channels to the 8727 device which then outputs 10G signal to the SFP module With an SFP module and optical cable installed as shown in Figure 5 1 the SFP sends an optical 10G signal onto the optical fiber which is looped back into the SFP optical input The SFP module converts the 10G optical signal into an electrical 10G signal and sends it to the 8727 PHY PHY then converts the 10G signal into four 3 125G XAUI output signals and transmits them to the
31. lave Output Channel 2 78 MOD ABSI CMOS Module Absent Channel 1 138 MOD ABS2 CMOS Module Absent Channel 2 43 MOSII LVTTL Master Output to Slave Input channel 1 103 MOSD LVTTL Master Output to Slave Input channel 2 121 NVMAISEL LVTTL Non volatile Memory Select 132 NVMPROT CMOS Non volatile Memory Protect 61 OPINLVL LVTTL Optical Control Input Level 59 OPOUTLVL LVTTL Optical Control Output Level 42 OPRXLOSI CMOS Optical Receiver Loss of Signal Channel 1 102 OPRXLOS2 CMOS Optical Receiver Loss of Signal Channel 2 44 OPTXFLTI CMOS Optical Transmitter Fault Indicator Channel 1 104 OPTXFLT2 CMOS Optical Transmitter Fault Indicator Channel 2 62 PCDRLKI LVTTL PMD CDR Lock Detect Channel 1 122 PCDRLK2 LVTTL PMD CDR Lock Detect Channel 2 Terasic DUAL XAUI User Manual www terasic com www teragic com JAN DTE 60 120 12 66 126 77 79 73 71 67 65 47 107 50 53 113 48 108 119 49 109 74 134 32 28 24 20 30 26 22 18 PCMULKI PCMULK2 PHYRESET PLOSBI PLOSB2 PRTADOI PRTADO2 PRTADI PRTAD2 PRTAD3 PRTAD4 SCK1 SCK2 SER BOOT SFP TXDISI SFP TXDIS2 SMBSPDSELI SMBSPDSEL2 SMBWEN SS NI SS N2 TXONOFFI TXONOFF2 XAUI RX INO XAUI RX INI XAUI IN2 13 XAUL 1 0 XAUI RX IPI XAUI 1 2 1 3 LVTTL LVTTL LVTTL LVTTL LVTTL CMOS CMOS CMOS CMOS CMOS CMOS LVTTL LVTTL LVTTL LVTTL Open drain LVTTL Open drain LVTTL LV
32. nel 2 positive leg www terasic com JAN DTE RYAN J12 F9 F11 F8 F10 K8 J15 F7 L5 K13 F 12 1 5 7 Bl B3 B5 B7 SFP TXDISI SFP TXDIS2 SMBSCLI SMBSCL2 SMBSDAI SMBSDA2 SMBSPDSELI SMBSPDSEL2 SMBWEN SS NI SS N2 TRSTB TXONOFFI TXONOFF2 XAUI RX INO XAUI RX INI XAUI 1 2 XAUI 13 XAUI 1 0 1 1 1 2 1P3 LVTTL Open drain LVTTL Open drain LVTTL Open drain LVTTL Open drain LVTTL Open drain LVTTL Open drain LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL CMOS CMOS Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential CML Differential Terasic DUAL_XAUI User Manual www teragic com Optical Transmitter Enable channel 1 Optical Transmitter Enable channel 2 Serial Clock channel 1 Serial Clock channel 2 Serial Data channel 1 Serial Data channel 2 2 wire Speed Select channel 1 2 wire Speed Select channel 2 2 wire Write Enable SPI ROM Chip Select channel 1 SPI ROM Chip Select channel 2 JTAG Test Reset pin JTAG interface not used for this design Transmit Driver On or Off channel 1 Transmit Driver On or Off channel 2 XAUI Parallel Receive Data Output Channel 1 lane D negative leg XAUI Parallel Receive Data Output Channel 1 lane C negative leg XAUI Parallel Receive Dat
33. supplies the XAUI to SFI chip set for CMU reference use Power for the SFP modules and the chipset will be provided from the 12V and 3 3V power available on the HSMC connector DUAL XAUI User Manual www terasic com www Chapter 3 Pin Description This chapter describes the detailed information of the connector interfaces and the pin description on the Dual XAUI to SFP HSMC board 3 1 HSMC Expansion Connector The Dual XAUI to SFP HSMC board contains a HSMC connector Figure 3 1 Figure 3 2 and Figure 3 3 show the pin outs of the HSMC connector on the Dual XAUI to SFP HSMC board Terasic DUAL XAUI User Manual www terasic com www Ceragic com HSM_RX_P7 HSM_TX_P7 HSM RX N7 HSM TX N7 HSM RX P5 HSM TX P6 HSM RX N6 HSM TX N6 HSM RX P5 HSM TX P5 HSM RX N5 HSM TX N5 HSM RX P4 HSM TX P4 HSM RX 4 HSM TX N4 HSM RX P3 HSM TX P3 HSM RX N3 HSM TX N3 HSM RX P2 HSM TX P2 HSM RX N2 HSM TX N2 HSM RX P1 HSM TX P1 HSM RX N1 HSM TX N1 HSM RX PO HSM TX PO HSM RX NO HSM TX NO SMB SCL SMB BDA JTAG TDO TDI JTAG TDO TDI elk cutO elk inO Figure 3 1 Pin outs of Bank 1 on the HSMC connector Terasic DUAL XAUI User Manual www teras ic com www terasic com 12V N r4 BN OPRXLOS1 MISO1 3 3V OPRXFLT1 44 43 11 46 45 B SMB8PDSEL1 SCK1 SER BOOT 55 1 MDIO1 TXD031 M

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