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Preliminary, IBM Internal Use Only

1. 12 6 G5220297 00 p Power Preliminary Section 12 Electromechanical Table 12 1 MCM Primary Continued Net Topology 6 6036 memory J1 J32 9 5000 memory 4 J1 J33 7 5000 memory MCE5 J1 H33 4 7500 memory MCE6 J1 G32 7 5000 memory MCE7 J1 G33 64 7500 memory MREO J1 AL04 67 3536 memory MRE1 J1 AL06 65 1036 memory MRE2 J1 AL08 60 6036 memory MRE3 J1 AL10 57 0000 memory MRE4 J1 AL12 54 2500 memory MRE5 J1 AL14 52 1036 memory MRE6 J1 AL16 53 8536 memory MRE7 J1 AL18 13 8536 memory MWEO J1 M33 12 6036 memory MWE1 J1 N33 38 7950 funct TEA J1 N10 46 2857 funct DRTRY J1 AJ01 19 2500 funct ROM_OE J1 V31 17 5000 funct ROM WEZ J1 T31 39 4691 funct INT 60X J1 U16 40 7150 funct _60 J1 R16 81 0192 funct SRAM OE 1 22 10 2020 funct PLL CFGO J1 D25 16 6744 funct PLL CFG1 J1 B27 17 1617 funct PLL CFG2 J1 A27 15 3550 funct PLL_CFG3 J1 C28 53 8536 funct ROM LOAD J1 U20 32 4704 funct 60X AVDD J1 B02 27 2459 funct QACK_60X J1 D17 4 2367 funct QREQ_60X J1 018 4 2367 funct X_INT_60X J1 F31 4 2367 funct X_MCP_60X J1 H27 4 2367 funct X_SRAM_OE J1 G26 19 0000 funct INT_TO_664 J1 B31 8 5866 funct X PCLK 60X J1 D19 5 6036 funct X TAG BCLK J1 P29 21 9935 funct SRESE
2. G5220297 00 PowerPc Preliminary Section 8 Exceptions Section 8 Exceptions This section contains information on interrupts errors resets and test modes Some of the functionality of each area is implemented on the MCM and some of that functionality is lo cated on the planar To simplify the material both the MCM and the planar parts of each system are presented in this section 8 1 Interrupts 811 Planar Interrupt Handler Example planar interrupts are handled primarily by the interrupt controller in the ISA bridge the 660 the CPU and the firmware There are two 8259 type interrupt controllers located in the ISA bridge These controllers receive and prioritize example planar interrupts which can be asserted by motherboard logic PCI devices or ISA devices The interrupt controller then asserts an interrupt to the 660 The interrupt controller is programmed to handle both ISA and PCI interrupts using the cor rect protocols under software control Much of the operation of the interrupt controller is programmable See the SIO data book for more information 8 1 2 660 INT REQ and INT CPU Z The 660 features two interrupt inputs INT REQ and NMI REQ As shown in Figure 8 1 the 660 inverts INT REQ and passes it thru to the CPU as INT CPU While the 660 is in 601 error reporting mode it also use
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5. XX G5220297 00 PowerPc Preliminary Section 1 Introduction Section 1 Introduction This document provides a detailed technical description of the 100 MHz PPC 603e Multi Chip Module and is intended to be used by hardware software test and simulation engineers as a first source of information Software developers should read through the entire document because information relevant to their tasks may be located in hardware sections 1 1 The MCM The consists of the CPU L2 PCI Bridge Memory Controller and master clock ele ments of a PowerPC system The chips that provide this function are all packaged on a single ceramic substrate G5220297 00 1 1 p Section 1 Introduction Preliminary Power 1 2 100 MHz 603 Clock 60X CPU Driver 60X CPU BUS Control Address 32 Data 72 Control Tag Control SRAM System Control Cache and Status IBM27 82663 Buffer PCI_AD 31 0 Brid EPROM DEVICES EPROM Figure 1 1 MCM Block Diagram The see Figure 1 1 is compliant with the PowerPC Reference Platform Specifica tion Version 1 1 and the PCI Local Bus Specification revision 2 0 2 1 see Section 5 5 for host bridges The MCM uses
6. 12 14 G5220297 00 44 45 Pewer 12 3 3 MCM Solder Columns O Pad with VO iminary Solder PS Section 12 Electromechanical H eX C ee C eco eO OCOD 0 e OOOO Locator e e e Ox 09 0 O 0 9 0e a OJO 0000 e e e e 6 6 exe 6 6 e e V OOHOPDO 0 90 O OO HOOD 90 O O O _ 6 e 6 e 6 e 6 9 0000 e 6 e e e 0 9O OO HOOD O O9 Oe e amp e OS e 6 e 6 e e e e O90 D OO OO O OD O0 O Oe e _ 6 e e 6 6 e e 6 6 e e e e 05 90 9 QO OO OOOH 0 e e e 9 5
7. HEHEHEH d HEHHE gg Hao HEHHE d PowerPC 603 604 Reference Board Press C during memory test for configuration utilities Testing 8192K of memory 8192 KB OK Figure 10 6 System Initialization Screen While the logo screen is displayed pressing the C key on the console will enter the system configuration utility The configuration menu will also be entered if there is no bootable de vice present or if the configuration stored in the system non volatile RAM is not initialized or is corrupt G5220297 00 10 7 p Section 10 Firmware Preliminary Power 10 4 3 Main Menu Figure 10 7 shows the main menu for the system configuration utility Selections on the menu are highlighted by using the up and down arrow keys on the keyboard and are cho sen with the Enter key Each choice is detailed in the following sections PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Main Menu System Configuration Menu Run a Program Reprogram Flash Memory Save and exit Exit without saving Press Tl to select item Press Enter to perform action Figure 10 7 Configuration Utility Main Menu 10 8 G5220297 00 PowerPc Preliminary Section 10 Firmware 10 4 3 1 System Configuration Menu Figure 10 8 shows the System Configuration menu wh
8. N r e e e e e e e e e e 4 e e OO O9 OO O eX eo 9 00 7 6 Ov 2 6 6 e e e 0000000 00 6 6 6 e e 8 O9eO0e O6C0 O0 Ot Ov CO Oc 9 4 8 SSIS ESS A e A01 482 127 12 15 5220297 00 Section 12 Electromechanical Preliminary Power 12 3 4 Component Placement 0600005099900 5 222522 54550 5552 q 12 16 G5220297 00 PowerPc Preliminary Section 12 Electromechanical Part Number 91H5797 Sheet 1 of 5 G5220297 00 12 17 Power Preliminary Section 13 MCM Schematics Section 13 MCM Schematics This section contains the schematics of the Odyssey MCM For schematics of the planar see Appendix F The schematics are numbered separately from the rest of the MCM technical specification G5220297 00 13 1 a section 13 mom schematics Preliminary PowerPC 131 Component Placement 13 2 G5220297 00 Qc 20 T 13395 TA3SSAQOZAd LII NUWISU3 B66T 22 17 nuizagr JIdOH 1597 SNIMUHU g NOILIUHOdHOO 85661
9. 12 2 12 1 3 Package Delay Modeling 12 2 12 1 4 Net Electrical 12 3 12 2 MGM Thermal cee eet rp dU TE tess IU ERE EU a 12 11 12 2 1 Chip Thermal Requirements 12 11 12 2 2 Cooling Requirements 12 12 12 2 3 Cooling Recommendations 12 13 12 2 3 1 Thermal Resistance From Cap to Heat Sink 12 13 12 2 3 2 Thermal Resistance From Heat Sink to 12 13 12 3 Mechanical Drawings 12 14 12 3 1 MOM with Quee cute Grogs 12 14 12 3 2 MCM Without Cap pni E nae 12 14 12 3 3 MCM Solder Columns 32 eee Gos ER RR REPERTA SERE 12 15 12 3 4 Component Placement 12 16 Section 13 Schematics 13 1 13 1 Component 13 2 G5220297 00 xi Pewer Appendix A Example Planar Overview A 1 A 1 The Collateral Material ned eee nace A 1 A 2 Example Planar eed ence aaa ae ees ek A 2 System MOIIOLY eed eg ceci ea a a A 3 BUS x ma ESE its ase
10. t 8 Byte 4M 8B x 4M x 1 bank 32M Lm LM B 12x10 4 3 1 13 Memory Bank Enable BCR Program indexed BCR AOh memory bank enable to to enable all banks except 4 4 3 1 14 Memory Bank Addressing Mode As shown in Table 4 11 memory bank 0 connected to RASO contains an 8 byte x 1M SIMM 8M with one bank one RAS line It is addressed with 10 row and 10 column bits Program bits 3 1 of indexed BCR A4h with 010b mode 2 G5220297 00 4 21 Section 4 DRAM Preliminary PowerPc 8 Bytes DEPTH TOTAL RASO ORAS 8MB SIMM 1Mx8Byte 8MB 4 Bytes 4 Bytes 6 7 3eMB SIMM 4M x 4 Byte Not Populoted 4 Bytes 6 2 gt Tw RAS6 ORAS 128MB SIMM 16Mx8Byte 8 Bytes SSS RAS7 GRAS 32MB SIMM 4Mx8Byte Figure 4 3 Example Memory Bank Configuration 4 3 1 15 Starting and Ending Addresses As shown in Table 4 12 program indexed BCR 80h with 00h to configure address bits 27 20 of the bank 0 starting address Program indexed BCR 88h with 00h to configure ad dress bits 29 28 Also program indexed BCR 90h with 00h to configure address bits 27 20 ofthe bank 0 ending address and program indexed BCR 98h with 07h to configure address bits 29 28 The next two physical SIMM units are 4 byte x 4M x 2 bank 16M x 2 bank 32M SIMMs used side by side to achieve 8 byte width They form banks 1 and 2 each of which is 8 byte x 4M 32M Note that bank 7 is
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13. 9 e 9 6 e 6 E 090059 oO eO X eO 09 009 9 7 6 6 e e OO OL GOGH e e i Oe 00 00 O O O X9 e Xe O OO e v 4e e e e Oe O OD OO e 9 9 9 e 6 e e OX OED 0 9 e 00 e 9 OY e Oe ex OO 6 e R Ce 6 O eX OO X9 Oe D O OC e e P e e e O OO OO O e 6 e 6 6 6 e 1 e 09090 09 O OO ox eo 09 09 O99 0000 O0 O OV OO OO ex 9 9 9 9 e 4 e OO 0 OOOO O Xp eO O0 O Oe e L 4e 6 6 e 6 e e e e J OO e O e90 O0 O XO CX exXo9 O0 O0 D D O9 e e e e e e 6 6 e e 00 e e 9O Xo
14. 11 1 11 1 What the 6036 CPU Does e RR ga we ee ees wees ER 11 2 11 1 1 The 603e Address Munge 11 2 11 1 2 The 603e Data Shift SS nate X REIR ROS RA was ee 11 2 11 2 What the 660 Bridge Does 11 2 11 2 1 660 Bridge Address Unmunge 11 2 11 2 2 The 660 Bridge Data Swapper 11 2 11 3 Bit Ordering Within Bytes 11 4 11 4 Byte Swap Instructions 11 5 11 5 603e CPU Alignment Exceptions In LE Mode 11 5 11 6 Single Byte Transfers eoe eh ate rete dtes po wee ee 11 6 11 7 Two Byte Transfers 11 10 11 8 Transfers e Mc iata 11 12 11 9 Three byte Transfers OEE Re 11 14 11 10 Instruction Fetches and Endian Modes 11 15 11 11 Changing Mode REV EPI FPE VUE EPI 11 16 11 12 Summary of Bi Endian Operation and 11 18 Section 12 12 1 12 1 MOM be eie 12 1 12 1 1 AC Electrical 5 lt 12 1 12 1 2 SCM Package Delay Modeling
15. 8 16 8 2 8 4 Error Reporting With PCILPERR 8 16 8 2 9 Error Status Registers 8 16 8 2 10 Error Related Bridge Control Registers 8 16 8 2 11 Special Events Not Reported as Errors 8 17 cR EMI a a 8 18 8221 OPUBOSOLl ieee 8 18 8 3 2 660 Reset discesa tab IET MU E IA UMS S tuae sete 8 18 8 3 2 1 Reset State of 660 Pins 8 18 8 3 2 2 660 Configuration Strapping 8 20 8 3 2 3 660 Deterministic Operation Lockstep Applications 8 20 BA TestM deS eoe tes ubertate i ute Ud platte Elek Serbie est E 8 20 GAN GRU TESE 8 20 iets 8 20 82 11550 Ies MOOD ed OL 8 21 Section 9 Set Up and Registers 9 1 9 1 CPU Initialization uoa 256 Deut ere oat et epe ce Se Sou per ones 9 1 9 2 660 Bridge Initialization 9 1 9 3 PCI Configuration Scan semet mmt Ren metes sh 9 2 9 3 1 Multi Function Adaptors 24 esse tied ae Ese ie RES Pe RS DRE ES EE 9 2 9 3 2 PCI to PC BIGGS oo ae pers seo We 9 2 9 3 3 Indexed BCR Summary u
16. 5 14 5 5 2 3 Solution 2 Change the flag write procedure 5 14 5 5 2 4 Solution 3 Change the data set write procedure 5 14 5 6 Related Bridge Control Registers 5 15 Section 6 ROM Ray xay hor i Ra a 6 1 6 1 Direct Attach ROM Mode 225 edie yee 6 1 eee tee Bee eee 6 2 6 1 1 1 Read Sequence 2 6 2 6 1 1 2 Address Transfer Size and 6 4 6 1 1 3 Endian Mode Considerations 6 4 6 1 1 4 4 Byte PUER 6 4 6 12 ROM WIES odas ripe et CEU GUAE a Rn EORR dnd 6 4 6 1 2 1 ROM Write Sequence o oio Sos roS eR See e Seb Rs 6 5 6 1 2 2 Write Protection teas reca teu E gesti 6 5 6 1 2 3 Data Flow In Little Endian Mode 6 5 6 1 2 4 Data Flow Big Endian Mode 6 6 6 2 Remote ROM 6 7 6 2 1 Remote ROM Reads ies EG ede Env epe 6 8 6 211 Remote ROM Read Sequence 6 8 6 2 1 2 Address Transfer Size and Alignment 6 11 pads Burst Basses dai 6 11 6 2 1 4 Endian Mode Considerations 6 11 6 2
17. JINI OILY OO O 5121 O Z Z q WOW WOW NId WOW NOT ANOS 0 2 _ BO JNI NOISS 594 UDISA JeouIl NOIIdIHOS3U S LNALNOS OD Aq O 0i 2 3 gg NOMISU3 r NIME NOILUMOdHOO gt HENIN 561 34 4215 5661 1HOIHAdO KUHOUIG 0078 PN C c NOUNS 4 Ha 9 1 E T 5 9TXHZE 9T ST Y eo en lt O 2 gt 814 a 9 gt 0 e AlIMUd ONY ULE ABOLGH 2 U 6T LUND gas cPIPNeBOTOT ma48 Pies a AF gt ANON AW lt 2 ET Ma en SS3HOUU AYOWSW ST 4 lt O LIW Q 25384 4 Ch idd 1ND WIW 271 id NOUS TE PIE IR HIND 3H02 v99 WEY 991 BRE idd vledvaeddy Idd VTGTFOASI 071 WOW 4 1 dece 4 TIONLNOD e e lt 2 21 gt 8 SINANI 9190 Si1fidNI SSJudag gc ETO id cn
18. Preliminary Internal Use Only 100 MHz 608 Multi Chip Module User s Manual Release 0 1 This document provides a detailed technical description of the PPC 603e MCM It is in tended as a first source of information for both hardware and software designers Where appropriate other documents are referenced Document Number G5220297 00 February 1997 ghi EU 722 Pewer International Business Machines Corporation 1997 Printed in the United States of America 1997 All Rights reserved Note to US Government Users Documentation related to restricted rights Use duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp IBM Microelectronics PowerPC PowerPC 601 PowerPC 603 PowerPC 603e PowerPC 604 RISCWatch and AIX are trademarks of the IBM corporation IBM and the IBM logo are registered trademarks of the IBM corporation Other company names and product identifiers are trademarks of the respective companies This document contains information which is subject to change by IBM without notice IBM assumes no re sponsibility or liability for any use of the information contained herein Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties The products described in this document are not intended for
19. 2 1 Direct Access Registers Ras ISA Bus Register Suggestions Appendix D Planar Electromechanical DI T NE POCO OR D 1 1 Power Requirements D 1 2 Onboard 3 3V Regulator D 2 Physical Design lt 2 21 Construction csere Eae ae dE 0 2 2 General Wiring Guidelines D 83 CPU Bus Ming ae se iege ate es DA PGBS NIS a E a RR wa Ea RE VES CD wre M 9 5 Example Planar 0 5 1 Example Planar Connectors 0 5 2 Example Planar Connector Locations 0 5 3 Keyboard Connector J14 0 5 4 Alternate Keyboard Connector 14 0 5 5 Mouse Connector J15 D 5 6 Speaker OConnectord ep PES 0 5 7 Power Good LED KEYLOCK Connector J12 5 8 HDD LED Connector J11 1 x 2 Berg 0 5 9 Reset Switch Connector J10 1 x 2 Berg 0 5 10 Fan Connector J9 J35
20. 220 P21 NC DEPOP P VSS 79 79 U U U A A wi N Pa U N 24 U N TAG DTY U5 34 vss U1 144 U2 107 SS 1 R1 G01 R1 G02 U5 66 U5 67 U5 68 z vos p y P33 MD63 03 140 R01 PCI_AD1 U2 59 U3 237 0 PCI AD2 U2 46 U3 238 ms neee R04 ABUF20 U7 49 U8 49 U9 49 U10 49 U6B 36B _ TSIZ2 R1 K02 U1 195 U2 147 my R08 R1 A02 U1 28 U2 109 NO pg 0 N N N 07 U U 8 2 5220297 00 Preliminary 2 19 Section 2 Signals MCM Nodes NC _ R11 NC DEPOP 4 NO R1 Pe R14 U268 U3169 R1 R1 R17 R18 R1 NC DEPOP PCI OUT SEL VDD1 MCP_60X VDD1 LSSD_MODE VDD1 SS U2 68 U3 169 D 2 o R1 H02 U1 186 R1 E04 U1 205 2 2 R21 NC DEPOP R22 SRAM ADDR1 R23 NC DEPOP R24 A10 R25 NC DEPOP R26 A13 j U2 125 U7 52 U8 52 U9 52 U10 52 U1 170 U2 84 U5 57 8 B U1 12 U2 87 U6B 23B R27 NC DEPOP U6A 9A NC DEPOP MD61 U3 138 U3 139 U2 48 U3 236 J1 V03 U7 48 U8 48 U9 48 U10 48 U6B 35B 2 R1 A01 U1 36 GO oa mi 2 MD62 PCI ala py lt 40 o 03 DAISY18 04 VD
21. 4 27 4 4 1 8 to Memory Write in ECC Mode 4 27 4 4 1 9 PCI to Memory Read ECC Mode 4 27 4 4 1 10 PCI to Memory Write in ECC Mode 4 27 4 4 1 11 Check Bit Calculation 4 29 4 4 1 12 Syndrome Decode 4 30 45 DRAM Refresh RETE 4 30 4 5 1 Refresh Timer Divisor Register 4 31 4 6 Atomic Memory lt lt 4 32 4 6 1 Memory Locks and Reservations 4 32 4 6 2 CPU BeservaliOti v 52 oe eet 4 32 1403 ROI BOOK serae du Ex mU exc ER Rien 4 32 4 6 4 POLboOCKR8l685625 obese aS e 4 32 4 7 DRAM Module Loading Considerations 4 33 4 8 Related Bridge Control Registers 4 33 Section 5 PCI BUS E ROO ROI EUR eae 5 1 5 1 PCI Transaction Decoding pur kde tege mE ES 5 2 5 1 1 PCI Transaction Decoding Bus 5 2 5 1 2 PCI Memory Transaction Decoding By Address Range 5 2 5 1 3 PCI I O Transaction Decoding Re eee 5 3 5 1 4 ISA Master Considerations
22. 5 4 5 2 PCI Transaction Detalle leak eel ees tae diene x 5 5 5 2 1 Memory Access Range and Limitations 5 5 5 2 2 Bus Snooping on PCI to Memory Cycles 5 5 5 2 3 PCI to PCI Peer Transactions xau occuper ea dh ERE 5 5 5 2 4 PCI to System Memory Transactions 5 5 5 2 5 PCI to Memory Burst Transfer Completion 5 6 5 2 6 PCI to Memory Access Sequence 5 6 5220297 00 vii Pewer 5 2 7 PCI to Memory Writes 5 6 5 2 7 1 Detailed Write Burst Sequence Timing 5 6 5 2 6 PCI to Memory R adS 2 tesis Raa 5 8 5 2 8 1 Detailed Read Burst Sequence Timing 5 8 5 2 9 PCI BE to CAS Line Mapping eese ERR ERR En 5 9 5 3 Bus Arbitration 5 11 Jr E eto ecce nn ET 5 12 5 4 1 PCI B smaster Locks tasi 5 12 CPU BUS LOCKING oe taeda RE Extat 5 12 55 PCA Compliance x oem aub touts a een Bd te 5 13 5 5 4 PCI Target Initial Latency 5 13 5 5 2 Transaction Ordering RUles a aco Rie pio ce 5 13 5 5 2 1 Problem 5 13 5 5 2 2 Solution 1 Add a dummy CPU to PCI write
23. Global This signal is asserted during snoop operations to indicate that CPU busmasters must snoop the transaction 660 does not monitor GBL sampled at the negation of HRESET to set the DRTRY mode See the GBL 12 HRESET E32 CPU Hard RESET input Initiates hardware reset operations See 603e UM for more information G5220297 00 2 5 Section 2 Signals Preliminary P2werPc Table 2 4 CPU Bus Signals Continued L2 CLAIMst 660 CPU BUS CLAIMZ input This signal is asserted by an external CPU bus target to claim a CPU bus memory transaction It inhibits the 660 from driving AACK TEA and the CPU data bus lines L2 CLAIMZ connects only to 660 L2 is sampled by the 660 on the second CPU after TS is sampled active CPU bus targets can only map to system memory space 0 to 2G and only to memory space that is not cached by the 660 L2 The 660 L2 caches as much of the space from 0 to 2G as is populated by DRAM So if 8M is installed starting at 0 12 CLAIM Z can be asserted from 8M to 2G If the internal L2 is disabled then the entire 0 to 2G memory space can be claimed by L2 CLAIM _60 CPU MCP Machine Check Pin input The CPU enters either a machine check interrupt operation or a check stop state depending on the state of the machine X 60X4 660 Machine Check Pin output The 660 drives this pin to notify the CPU of a system error from a source which ma
24. mi n MWEO USER_PCICLK2 U4 21 PCI_AD4 U2 42 U3 10 ABUF22 U7 7 U8 7 U9 7 U10 7 U6B 38B R1 K01 U1 196 U2 146 R1 D01 U1 154 U2 137 U2 205 U3 170 U2 195 U3 144 R1 D05 U1 25 R1 E05 U1 204 U2 124 U7 2 U8 2 U9 2 U10 2 R1 G03 R1 G05 U5 23 U5 27 U5 28 U1 160 U2 99 U5 13 U6B 11B U5 51 z N NC DEPOP TSIZ1 2 2 07 NC DEPOP 0 NC DEPOP N10 N11 N12 N1 N14 N1 N1 N1 NC DEPOP DUAL CTRL REF NC DEPOP AD OE NC DEPOP DBWO 60 NC DEPOP L1 TST NC DEPOP BG MASTER N2 NC DEPOP N22 SRAM ADS ADDRO 2 2 5 ojo l N23 NC DEPOP N24 TA GATES NetName VSS m PWRONE Pom C C C Ios DUAL coe __ coe NC DEPOP _ coge NC DEPOP ___ N25 NC DEPOP N26 A22 N27 NC DEPOP N28 TAG_TA N29 NC DEPOP N30 TAG_BCLK NC DEPOP N32 MDP7 2 5220297 00 PowerPc Net Name MCM Nodes eoi g ws SS 0 Neo P05 ABUF21 U7 6 U8 6 U9 6 U10 6 U6B 37B 02 110 210 2 55 U U X ee y LLLI yess woo wo yess w P19 NC DEPOP
25. OL SINANI Y 591 IL Woes 8 5 OL SANTINd WHANAS O039N8H2 5301515345 5 40 LN3HWNDISSU3H ONY GND MON TEE ONY SNId 3UOH LIN 307991 U3ONOHO 090 Nid 21 89 SLIN NIUHO 619 3WUN GevOd 3503 Ol 59 5 NId SNOYAWNN dasyalay c NOTSHAN ST LON 19401 STO ONY PTD 5801108890 CANOWSY SNINDL 804 3 ION OLNO H204 ONY 440 5320 SNA X493 350373 2 2 NOISHaN STO TTS 580 40 1 1009 Woes OL NId 72004 3EGS ST4 64 811 STH xag aco 9713 2243 111 219 67 odi 3 809 211 STO 64 813 H Ell 802 814 0912 823 Ser tril 15134 ONIMOT O4 HO4 SNId 30 INJANDISSU3M OL 2TH GONG x29 NDISSUJH 2 200N 2 7007 SHOLlIOUdOD NI IANO 40 14349155934 350373 NOISHaN 1531 HOH4 3OUJH31NI ASN 071 d oW Aid 901 ONY Hed I2d 03009 S3ONUHO LNAWNDISSY NId amp H3MOd 071 OL x29 53HO ONY X9 2U0 OFSNYHD AONASNILNOD 803 071 LNO 33008 NO ONY 440 205 IOd 99 LHONONA 03593734 Q c NOISHAN 03 14 SHOLIOUdOO 30151534 135901559 SNId 03593734 _ 5 M3I 3H X04 Q31D8IHIGSIG T NOISH3 14940 96 amp 96 5741 5671 21 S6 E TT 6 92 07 56 27 91 56 81 62 56 62 84 56 52 98 56 22 80 56 62 80 56 02 80 5
26. C2P WRL OPEN AA14 U2 61 660 CPU to PCI Write Latch Open signal When asserted the CPU to PCI write latch accepts new data on each CPU When deasserted write latch holds its current contents CPU DATA OE J14 660 CPU Data Output Enable signal When asserted the 663 drives the G12 664 CPU Read Latch Open output When asserted the CPU read latch CPU DATA bus on the next CPU CLK CPU RDL OPEN accepts new data on each CPU CLK When deasserted the CPU read latch holds its current contents This signal is asserted when data is to be sampled from memory or the PCI When sampling data from memory this signal is also active on the fol lowing CPU CLK to allow ECC corrections to occur if necessary If no corrections occur the same data is provided by the MEM read ECC correction logic X CPU RDL _ G10 663 CPU Read Latch Open input See the 660 User s Manual for more OPEN information Add a 2009 nominal series resister to the CPU RDL OPEN net between the 664 and the 663 During a CPU to memory read if at the 663 CPU RDL OPEN goes low before MEM RD SMPL goes low then the 663 may provide incorrect data to the CPU The Table shows the minimum required interval between the falling edge of MEM RD SMPL and the falling edge of CPU OPEN Case 663 664 Requires Supplies 1 Worst Case Process Temperature amp Vpp 1 8ns 1 3ns 2 Best Case Process Worst Case Temp amp
27. 4 18 4 3 1 6 Memory Bank Addressing Mode 5 4 18 4 3 1 7 Memory Bank Starting Address 4 19 vi G5220297 00 Pewer Preliminary 4 3 1 8 Memory Bank Extended Starting Address BCRS 4 19 4 3 1 9 Memory Bank Ending Address BCRs 4 19 4 3 1 10 Memory Bank Extended Ending Address BCR 4 20 4 3 1 11 Memory Bank Enable 4 20 4 3 1 12 Memory Bank Configuration Example 4 20 4 3 1 13 Memory Bank Enable BCR 4 21 4 3 1 14 Memory Bank Addressing 4 21 4 3 1 15 Starting and Ending Addresses 4 22 4 4 Error Checking and 4 23 4 4 1 Memory Parity isse Celeste aa 4 23 4 4 1 1 ECC Overview las 4 24 4 4 1 2 ECC Dala FloWS chi ER OR dp Og 4 24 4 4 1 3 Memory Reads cuoio etu uere bise Cres c atento tue Beso 4 25 4 4 1 4 Eight Byte 4 25 4 4 1 5 Less Than Eight Byte 4 26 4 4 1 6 Memory Performance In ECC Mode 4 26 4 4 1 7 to Memory Read in ECC Mode
28. 708 Z908 802 1 1 eds 259 86 186 Tes 286 286 26 226 226 725 1 26 06 cae 206 706 506 296 296 126 226 226 726 526 106 ede Ede rae 506 299 Tee eue Eb6 T86 286 286 vas 586 196 ede 206 rae 506 dIH2S3H 6 27 d2 72 de 72 d02 72 d02 72 de 72 d02 72 do 72 d2 72 d02 72 d02 27 d3 72 dg aJ ua JO B82u8J8j48H 8S90J5 PUN zi 13366 651 TT At EE E dg 1 IJIUOW 1597 ONMO NOISI 3 NOI UHOdHOD S667 Wal gt ONIM A TVIPNOT LNA
29. following instructions look the same in either Endian mode 28 X38010138 2C X38010138 Enough of these instructions must be executed guarantee the above store has occurred before any memory or I O cycles are listed Xx X38010138 Figure 11 8 Instruction Stream to Switch Endian Modes G5220297 00 11 17 p Section 11 Endian Preliminary Power 11 12 Summary of Bi Endian Operation and Notes e When the 603e CPU is in BE mode the memory is in BE mode and data flowing on the PCI is in BE order so that it is recorded on the media in BE order Byte 0 is the most significant byte When the 603e CPU is in LE mode the memory is in LE mode and data flowing on the PCI is in LE order so that it is recorded on the media in LE order Byte 0 is the least significant byte The PCI bus is addressed in the same manner that memory is when the 603 CPU runs a cycle The unmunging in LE mode changes the effective low order address bits the byte enables and A D 2 On all but I O cycles the two low order A D lines are set to zero On PCI I O cycles A D 1 0 are also transformed by the unmunge operation No translations are made when accesses memory so that the byte with address 0 on the PCI flows to byte 0 in memory 1 to 1 2 to 2 and so on For example if BEO and 1 are active and A D 2 is a 0 then memory byte lanes 0 and 1 are addressed cas 0 and cas 1 active on writes Note that the LE devices whic
30. Eror Staus ooe A SmgeBrEmrOomer w 1 EvorTiggerLevel mes Bridge Options xa Aw mwEmbe TT mec Aw fEvorStaust Singer ECC Emr Address mecc ew geCnpSeOpn3 w NER 1 G5220297 00 4 33 Section 4 DRAM Preliminary PowerPc 4 34 G5220297 00 PowerPc Preliminary Section 5 PCI Bus Section 5 PCI Bus The includes 32 bit PCI bus interface that runs at frequencies up to 33MHz The PCI interface is a host PCI bridge that is compliant with the PCI Specification revi sions 2 0 and 2 1 see Section 5 5 for the 3 3v and 5v signalling environments The MCM PCI bus interface is designed to run at one half of the CPU bus frequency PCI bus activity initiated by the CPU is discussed in section 3 This section describes PCI bus transactions initiated by a non 660 bridge PCI busmaster PCI busmasters can initi ate arbitrary length read and write bursts to system memory Whenever a PCI busmaster accesses system memory the 660 broadcasts a snoop cycle onto the CPU bus See the 660 User s Manual CPU Bus section for details The support
31. G T9 AdOD Wd 1 121611 6 JHL 40 JNO 15291 SIHL 40 NOISH3 163191 NOA JH OSNd Ol SIHI GSNIVLNOD NOTLEWYHOANI ANY ONINYSDNOD N3 IO SI 331NUHU D YO ALNGYYEM ON edILHUd GHIHL HO WEI 40 SLHOTY AlHddOHd TWNLOSATISLNI JHL BION 3SN3OI dO SS3eHdx4 58 dliUHddO 7719 6 LNAEWND0d STHL NI 9NIHLION NIGHdH GANIVLNOD NOI LONHO ANI SHL 40 3SN ANY 504 1118911 30 ALI ISISNOdS3H ON SAWNSSY SONGHD OL 15 6 SI ANY NOTLYWYHOANI AUONIWNI 13d SNIGLNOD 1 SIH CWOW 3 NUON AS Dy NOD Qc 20 13395 p667 p 29 5 1 5 00 en 31 190 1597 37111 SNIMUHU NUONISU3 ONMO NOISI 3B lOIIQgHOdHOOo 5661 LHOTYAdOD NOIldI 2540 1 SNH 10D JO 38 SNId 557
32. tup ne 4 25 CPU 8 Byte Write Data Flow 4 25 PCI 8 Byte Write Data Flow 4 26 PCI or CPU Read Modify Write Data Flow 4 26 DRAM Refresh Timing Diagram 4 31 ROM Connections 6 2 ROM Read Timing Diagram 6 3 ROM Connections 2 Dba ceeds 6 5 ROM Data and Address Flow In Little Endian Mode 6 6 ROM Data and Address Flow In Big Endian Mode 6 7 Remote ROM Connections 6 8 Remote ROM Read Initial Transactions 6 9 Remote ROM Read Final Transactions 6 10 Remote ROM Write 6 13 MEM CIOGKS bad pened en hae 7 1 MGM CIOECKS BA SECO BIS REN 7 4 CPU_CLK to PCI_CLK 7 4 Conceptual Block Diagram of INT Logic 8 2 Interrupt Handling 3 925 9202 che eae 8 2 POI Interrupt Connections 8 4 Boot Record eim Sto sc et AL 10 2 Partition Table 10 2 Partition Table Entry Format for an Extended Partition 10 4 Partition Table Entry for PowerPC Reference Platform 10 4 PowerPC Refere
33. 4 Nj f oO e lt lt e o o lt Y1 lt oro N U1 48 U3 116 U10 46 Yi Yu v Y17 G5220297 00 Preliminary NC DEPOP VDD2 NC DEPOP 5 lt N Y Y Y Y A N V VDD2 V 8 N 21 22 24 27 14 Y U6B 22B Y2 VDD2 Y2 X SRAM BCLKO U7 51 SS SS 5 SS SS 3 x o MA11 02 177 VDD2 MD55 U3 121 5 218 0 0 PCI_STOP U2 203 A A PCI DEVSEL 2 U2 204 EE gt SRAM BCLK3 04 50 E NC DEPOP A gt gt gt 1 1 1 1 1 0 gt C P 0 A NC NC DEPOP ony Qj N 1 18 19 20 21 22 N NC DEPOP NC DEPOP NC DEPOP NC DEPOP AA AA2 ABS 3 gt 21 EE gt 27 2 21 Section 2 Signals MCM Nodes U1 5 U2 77 U5 40 U1 168 U2 89 U5 32 0 ABUF26 U7 24 U8 24 U9 24 U10 24 U6B 44B C2P WRL OPEN U2 61 U3 154 TA R1 C05 U1 155 U2 111 _60 R1 F03 U1 218 TAG U2 114 U5 73U5 74 SRAM_OE U7 50 U8 50 U9 50 U10 50 Section 2 Signals MCM Nodes 21 U1 17 U2 98 U5 14 U6B 12B
34. Oj oj of o N N orr w o A Q Q aJa Q bh oorr w HIN o ala Oy A Q A Ww ooon N o 0 Q Q A pp oOo spes et pep EEE During refresh e WE 1 0 are driven high e MEM DATA 63 0 tri stated MA 11 0 continue to be driven to their previous state 4 30 G5220297 00 PowerPc Preliminary Section 4 DRAM PCI CLK A E zd d To a CAS 7 0 EE M E E E E C DRE Figure 4 9 DRAM Refresh Timing Diagram Refresh requests are generated internally by dividing down the PCI CLK The divisor value is programmed the refresh timer divisor register This register is initialized to 504 a value that provides a refresh rate of 15 1us when PCI CLK rate is 33MHz For other PCI CLK frequencies the refresh rate register must be properly configured before accessing system memory Refresh continues to occur even if CPU CLK is stopped 4 5 1 Refresh Timer Divisor Register Index DO to D1 Read Write Reset to F8 DO and 01 D1 The refresh timer register is a 16 bit BCR that determines the memory refresh rate Typical refresh rates are 15 1 to 15 5 microseconds If all DRAM in the system supports extended slow refresh the refresh rate can be slower The refresh timer is clocked by the PCI clock input t
35. Ylva LPOLIO WIW LOG nd sna xe9 854 OUlU S 30 5 NO COMO 134 J 18 Wal n 3 957 0 GSW 9190 28801980 WAW Seu lgod H3 HG 2 AllHUd 81890 ASW 299 1807 WAW S 40 2 m SNE ANOWIW NO 223 HO GOO 857 ASW 9190 WIW ELLE B667T 92 75 28 7 41 031 41004 1597 20 13395 Ad3S5AGdOzdlLIl GC T 1 48 os ovoa evet H3BLDON 8661 l1HDIHAdO SH3j4JnH 901 reget o re LOO SUI ene oy ore ue Tep Tes e eM S Hate TED UI XI seg XI ew Parn N U uT NONNA namna Sui EERE E Tag X 59 eS qe FEST es 8 gt 991 lt 1 gt 581 lt 2 gt 991 lt 2 gt 081 55222 18 gt 591 lt 45581 lt 2 5581 lt 85581 EL lt TT DOL Tui o e 888 eee 11411 6 lt 8 gt 8 lt Tou Gu lt E gt U pou Gu a lt 2 gt 8 lt 8 gt 9 lt 1 lt lt 21 gt 8 77707 ET adds 58l Qu o 8 a
36. if the PCI bus is idle and the PCI to the Bridge is active 3 5 1 CPU to PCI Read If the CPU to PCI cycle is a read a PCI read cycle is run If the PCI read cycle completes the data is passed to the CPU and the CPU cycle is ended If the PCI cycle is retried the CPU cycle is retried If a PCI master access to system memory is detected before the PCI read cycle is run then the CPU cycle is retried and no PCI cycle is generated G5220297 00 3 7 LUE Section 3 CPU amp L2 Preliminary PowerPc 3 5 2 CPU to PCI Write If the CPU to PCI cycle is a write a PCI write cycle is run CPU to PCI I O writes are not posted as per the PCI Local Bus Specification version 2 1 If the PCI transaction is retried the Bridge retries the CPU CPU to PCI memory writes are posted so the CPU write cycle is ended as soon as the data is latched If the PCI cycle is retried the Bridge retries the cycle until it completes 3 5 2 1 Eight Byte Writes to the PCI Memory and I O The 660 supports 1 byte 2 byte 3 byte and 4 byte transfers to and from the PCI The 660 also supports 8 byte memory and I O writes writes only not reads to the PCI bus When an 8 byte write to the PCI is detected it is not posted initially Instead the CPU waits until the first 4 byte write occurs then the second 4 byte write is posted If the PCI retries on the first 4 byte transfer or a PCI master access to system memory is detected before the fir
37. 5 0000 TAG PWRDN J1 M31 U5 77 48 1036 MWS P2MRXS J1 C30 U2 66 40 9072 664 STOP J1 B29 R1 F04 CLK EN 30 7884 TT4 J1 A23 U1 180 24 5780 GBL J1 A12 U1 1 43 8399 SRAM_CS J1 AD29 U7 5 U9 5 U10 5 19 5000 TAG 51 J1 C33 U5 75 72 1036 OE 245 B J1 D29 U6A 25A U6A 48A U6B 25B U6B 48B 32 2071 DIR 245 A J1 G22 U6A 1A U6A 24A 43 6036 DIR 245 B J1 L22 U6B 1B U6B 24B 20 7500 TAG SFUNC J1 C32 U5 22 52 6036 CRS C2PWXS J1 A29 U2 65 03 151 39 1036 663 MIO TEST J1 A30 U3 156 49 2500 664 MIO TEST J1 K05 U2 154 13 7500 XTAL1 J1 U30 04 12 12 8 5220297 00 Y nd Power Preliminary Section 12 Electromechanical Table 12 1 MCM Primary Continued Net Topology 11 7071 XTAL2 J1 T29 32 5000 FRZ CLK J1 B11 18 6036 FRZ DATA J1 A22 8 5866 PCLK_60X J1 E18 66 3536 TAG_BCLK J1 N30 29 9142 CLK_EXT_FB J1 A17 27 0000 CLK_FB_SEL J1 A15 27 5000 CLK_PLL_EN J1 D33 67 5000 SRAM_BCLKO J1 W30 66 5000 SRAM BCLK1 J1 AE30 9 1624 SRAM BCLK2 J1 AG04 8 6624 SRAM BCLKS3 J1 AA04 22 6036 CLK COM FRZ J1 A18 29 6036 CLK REF SEL J1 B13 24 4571 CLK TTL CLK J1 A26 28 0000 CLK VCO SEL J1 A13 1 7500 663 CPU CLK J1 G04 63 6036 664 CPU CLK J1 G30 24 1036 CLK BCLK DIVO J1 C16 22 2500 CLK BCLK DIV1 J1 B17 26 3536 _ J1 F33 STROBE 14 8536 MPC601 J1 K27 CLKS 25 3536 CLK J1 A16 MR TRISTATE
38. Bol 80 eor eor eor Po eo For Pr PGLFRAME 6 Siga Type MISC FUNCTION MISC FUNCTION MISC FUNCTION MISC FUNCTION 2 2 2 2 2 Ej 2 A ALA E A E A E A Of O CIC ALA E A G5220297 00 PowerPc Hype foa 664 CPU CLK CLK BCLK DIVO 1 CLK FRZ STROBE CLK MPC601 CLKS CLK MR TRISTATE 2 1 1 Clock Subsystem Preliminary Section 2 Signals 664_PCI_CLK CLK POL DIVO USER PCICLKO 6 DAISEY DAISY01 20 PWR PWR Table 2 3 Clock Signals Signal Name Nodes Description See 970 data sheet for more information X 663 CPU CLK G04 663 CPU CLK F05 U4 38 MPC970 2x PCLK output U3 157 The CPU bus clock input of the 663 SRAM BCLKO 664 CPU CLK G30 0442 MPC970 BCLKO output PCLK 60X E18 0434 MPC970 PCLK EN output MPC970 BCLK1 output X SRAM BCLKO SRAM BCLK1 The CPU bus clock input of SRAM bank 0 MPC970 2 output 0 04 46 X SRAM BCLK1 29 08 51 SRAM BCLK2 U4 48 The CPU bus clock input of SRAM bank 1 MPC970 1 output X SRAM BCLK2 U9 51 W30 04 44 Y29 07 51 04 05 SRAM The CPU bus clock input of SRAM
39. D 5 11 3 3V Power Connector J5 2 2 eet ei e Et cd ee Rd D 5 12 Power Connector J4 D 5 13 AUX5 ON OFF Connector J6 0 5 14 PCI Connectors J19 J25 J26 and J27 0 5 15 ISA Connectors J29 J30 J31 J32 0 5 16 DRAM SIMM Connectors J21 J22 J23 and 24 D 5 17 Power Switch Connector J8 0 5 18 Power Up Configuration Connector J7 D 5 19 RISCWatch Connector J2 2 2 35 D 5 20 Battery Connector BT2 0 5 21 MCM Board Connector Footprint 1 0 5 22 MCM Board Connector Footprint 2 Appendix E Bill of Materials E 1 Planar Bill of Materials Appendix F Planar Schematics Component Appendix Data Sheets G5220297 00 xiii 99 99 O O1 D 10 Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure
40. Preliminary 2 20 PowerPc Net Name MCM Nodes or POL OBE uzs os e Vo U7 33 U8 33 U9 33 U10 33 U6B 32B v U7 25 U8 25 U9 25 U10 25 U6A 40A P e c lt lt N lt lt o Y D U1 50 U3 137 U10 20 S via S lt a o vis vis S VDD2 NC DEPOP S lt gt V V VDD2 9 NC DEPOP 1 1 1 1 1 21 2 2 NC DEPOP 2 VDD3 3 U1 37 U2 108 8 N V V V V V 7 U1 6 U2 81 U5 46 7 1 N S 1 V 2 VDD3 V27 tee U6A 11A U1 159 U2 101 U5 9 U6B 8B ws ea Uz or PoroEw U28 03 04 RSEN x U10 32 U6A 38A 05 06 ABUF15 Wo lt lt U7 31 U8 31 U9 31 U10 31 U6A 37A G5220297 00 PowerPc Net Name MCM Nodes W08 010 30 06 27 09 U1 46 U3 77 U9 46 U2 64 U3 165 C a a re CKSTP_IN R1 D02 U1 215 VDD2 N lt VDD2 AOS RR MMRS U2 69 U3 166 5 21 Neo 22 SRAM_WE U2 118 U7 3 U7 4 U8 3 U8 4 U9 3 U9 4 U10 3 U10 4 N 23 DEPOP U1 175 U2 80 U5 45 25 NC DEPOP 2 U1 21 U2 100 U5 12 U6B 9B U1 40 U3 219 U7 20 S 6 26 A15 U1 13 U2 90 U5 31 U6A 12A 2 9
41. eke ee eee ted 8 3 8 1 7 Scatter Gather Interrupts 8 4 9 2 BIIOIS CS uot te ectetuer prs eret m eco ee 8 5 8 2 1 CPU Bus Related Errors 8 5 8 212 Error 8 5 8 2 1 2 CPU Bus Error Handling Protocol 8 6 9 22 PCI Bus Related 5 8 6 9221 PGI Bus Error pee teu 8 6 8 2 2 2 PCI Bus Error Handling Protocol 8 6 8 2 2 3 PCI Bus Data Parity Errors 8 6 8 2 3 CPU Bus Transaction Errors 8 7 8 2 3 1 CPU Bus Transfer Type or Size Error 8 7 8 2 3 2 CPU Bus XATS Asserted 8 7 8 2 3 3 CPU to Memory 8 8 8 2 3 4 to Memory Reads 8 8 8 2 3 5 CPU Data Bus Parity Error Rb RECIEN ES 8 8 923 0 L2 Cache Parity e RE RR 8 9 8 2 3 7 Bus Write to Locked Flash 8 9 8 2 4 CPU to PCI Bus Transaction Errors 8 9 8 241 Bus Data Error While PCI Master 8 9 8 2 4 PCI Target Abort Received Whil
42. 0 13 0 13 SA 55 e betaine dace reae Pire E Y D 15 DRAM SIMM Connector D 16 1x2 Power Switch 18 1x2 Power Up Configuration Connector 0 18 2 8 RISCWatch Connector 0 19 XV Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Preliminary Pewer Tables Example Signal Table 2 1 User Supplied Signals i depo e E e vies eed ss 2 2 Glock Signals eer DU steep net pb Eee 2 3 CPU BUS a 2 4 e 2 7 DRAM Signals ce totes 2 8 E2 Sidhals CALLA CERES OD 2 9 System Interface Signals 2 10 InterChip Communication Signals 2 11 Test Si
43. 27 30 TT 50 2T 30 21 Toe Tf Qc 20 13395 8661 6 ES 20 4656 1111 NOMWISO3 f Aew 1 031 41004 1591 SNIMUHU ONMO NOISI 3M 3715 S66T LHOTY NOILlUMOdHOO WEI gt Ado2 Sd IdNOD NU 242 Wd 9 ssn 2 40 2 555 65 29 S5n 65 65 8S S6n ssn ne et NE Et 2Q1 edin 901 200 01 200 2005 EQ1 edin O1 edin TOT edin 86 200 26 200 96 200 200 76 200 26 200 6 200 200 68 200 98 200 2 98 200 58 200 200 8 200 8 200 52 290 82 240 22 290 92 200 52 200 v2 2000 52 20 22 20 12 20 Q2 Ed 59 200 89 200 29 200 99 200 9 200
44. 3898 Page Hi Write 6844 5944 388 Page Miss and Bank Miss Read Page Miss and Bank Hit Read Page Miss and Bank Miss Write Page Miss and Bank Hit Write 5 Refresh Rate set to 0208h RAS watchdog timer BCR set to 53h 2 The RAS of the new bank is high and has been high precharging for the minimum RAS high time The bridge places the address on the address lines and asserts RAS 3 The access is page miss but within the same bank so the RAS line must be sent high for at least the minimum RAS high precharge time The bridge also places the new address on the address lines and asserts RAS Page Miss and Bank Miss Read 8 4 4 4 7 4 4 4 7 3 3 3 Table 4 3 contains a summary of recommended general case aggressive EDO DRAM tim ing the required control register settings and the resulting performance of the memory controller G5220297 00 4 11 Section 4 DRAM Preliminary PowerPc Table 4 3 EDO DRAM Aggressive Timing Summary 1 Aggressive Aggressive Aggressive MemayTmmgRegseri 2 no Memory Timing Register 06 o f Bridge Chipset Options __ c nial Read Bust 10388 mia Write Burst 5493 5422 For a pipelined burst transfer immediately following a read Hit Read 9859 8593 5 Page Hit Wit 9959 38993 3222 _ Page Miss amp Bank Hit Read
45. DEPOP AE1 D34 AE1 NC DEPOP AE1 D40 AE1 NC DEPOP AE1 D46 AE1 NC DEPOP AE2 D52 ITI gt gt o o gt ITI o N 0 09 gt gt 5220297 00 Preliminary 2 22 D58 AE23 AE24 AE25 AE2 AE27 AE28 AE29 AES 1 m 2 AF01 m gt gt 0 04 gt AF07 0 gt gt 1 021 E AF1 AF1 AF1 AF1 AF16 AF1 AF1 2 AF2 AF2 gt gt gt gt T mj N N re ay A oj o aj 26 2 29 EE E 4 AF32 Section 2 Signals MCM Nodes NC DEPOP U1 56 U3 125 U10 12 NC DEPOP U1 179 U2 72 NC DEPOP NC NC DEPOP AP3 NC DEPOP SRAM BCLK1 NC DEPOP MDP5 MD48 664 PCI REQ VSS DAISY16 VDD2 X_SRAM_BCLK2 vss R1 B04 U1 226 U4 46 U3 234 U3 108 U2 58 J1 AD03 09 51 U1 94 U3 198 U7 9 VDD2 D15 VSS U1 87 U3 218 U7 19 U1 80 U3 229 U8 41 VDD2 D27 VSS D33 VDD2 D39 VDD2 D45 VSS D51 U1 72 U3 26 U8 13 01 141 03 55 09 35 01 131 03 70 U9 45 01 123 03 88 09 15 01 105 03 105 010 39 057 VSS D63 U1 55 U3 124 U10 9 U1 64 U3 136 U10 19 VDD2 NC VSS X SRAM VDD2 A8 VSS U8 51 02 180 Section 2 Signa
46. m x 4 NEN SEN 9 4 4d 2 o 2 4 82 4 4 9 49 do weis _ 6 8 7 4 p ow cx 0 452771 e qood 54 14 oss 5 nn SS ae ee e JOS 5 0 22 ee 23 4 5 4 8 08 7 5 6 6 67 5 NL 6 5 o 4 _ 8 PEE a p se 8 2 o sv 1 0 AR 11 4 G5220297 00 PowerPc Preliminary Section 11 Endian 11 4 Byte Swap Instructions The Power PC architecture defines both word and halfword load store instructions that have byte swapping capability Programmers will find these instructions valuable for deal ing with the BE nature of this architecture For example if a 32 bit configuration register of a typical LE PCI device is read in BE mode the bytes will appear out of order unless the load word with byte swap instruction is used The byte swap instructions are e Ihbrx load half word byte reverse indexed e lwbrx load word byte reverse indexed e sthbrx store half word byte reverse indexed e Stwbrx store word byte reverse indexed The byte reverse instructions shoul
47. det ae CR SS EG A 3 A23 last PN sesso tama A 3 ees ASSESSES ASAE SSeS AA A 3 A225 ovstem LO EPED RI A 3 A26 A BUS a A 3 A2 7 Power A 3 Ad OtherHelp 4 A 3 1 Example Firmware o3 s mex sre RES NIE EAT rM ERRNEMAERA TES 4 Adee Design EES diu gt 4 39 QUICKSIart Peripheral EIST x ste ds urbi oos TREES 4 Appendix B Planar I O Subsystems B 1 Bil JSAJGUDSVSIBIN REL Ane 1 Blob Ine ISABIIOdOS Ree eee eae 1 Address Ranges 2 Co xe E Aes dus 2 B 1 3 ISA Bus Concurrency 2 B 1 4 ISA Busmasters and _ _ 31 B 2 BAS OMA eae an Pee 3 B 1 5 1 Supported DMA Paths orbe B 3 125 47 hater Eb UE AIMO EC UAE SIMI Nar nS B 4 Scatter Gather curs etat cn dope tefie B 4 BSA CXGBUSG I ERE Vos bs Peete B 4 B 1 5 5 Control Signal Decodes B 4 B 1 5 6 Ke
48. gt 1n07 12 x28 gt Bd22 OBEZ 2523 eTASIUEG Bu6 eda 29 gt BOBT lt EMET lt gt 82 TH GU N3 IND Wes OBEZ TTASIEG 2 59 lt EDEz Ex 128 WHS 9uec 815190 ubisap 291 204 amp ec Ex 128 Weeds 9guec 28025 CUBIC 40 133 ONMO NOISI 3 NOILIUMHOdHOD WAT S667 982 9912 rome gaae 9861 saat 9081 egac 2181 2861 8081 SpeST1n vast 2081 S22T PEZ gt cast 9591 8899 2491 9057 571 JOST FIST 2471 JOEF SOET EDZ 8381 306 586 2021 ET vaer 22171 2027 2 eT 2 2571 Saar Saat 2021 lt 2511 Saar SEAT 208 908 508 202 EOL 532 S32 809 sas 2021 saz 1 9021 9821 saat 2021 saat gaat 20 902 Saar Saar 9881 28871 vast 226 896 MBIOOM p MBIOOM p p XION p 59172 IUNZ T pO Tene yd 9021 Sacr 511 Saar 9801 396
49. 1 4 S 9 2 8 6 1 19 19 19 19 19 19 19 19 19 eu ud 5Id8d Atl T4299 JOHINOD 5534999 2 30 T 3Eg92ad m 3g POST 9P ESAS Hen 04 031 3100471557 M 911 NOWisea PN gt HENIN 61 34 4215 5661 1HOIHAdO HOSS32OHd QOR OLNY MI att S N d a lt EDET 224 990 edz lt TD ora sng 89180 E des 8661 cS ES HL IIAITOH 1591 M 92 T NOMWISO3 f gt Nma 6 3 32156 566 LIHO9IMAdOD STQHLNOD ANY SOI NOD SHADO TO HOLgMOS IH 10 1s1 e1 Page X19 1S1 271 ML 5203 7 1s1 T131 C s ae agow ass7 Pare xao asst raz 2 8 JNO 15 x29 Dzrz XG OO OO 7ONASISJ1 XONASIG LI 101 M21 SAL ise E9407 ETE 20540
50. 710 2117 12 44 1x3 ino n5 7x g SxioI2d d3sn S rDISd u3sn ASN es 4360 436 9 dana xao 2109 2169 TIX 37815503 SU LYOHS SU ld34 ONY G40 13I1HS 38 LSNW SLIN JHL Tf If TE TL If TL TL Tr Tf If TL 2 QI iN 0000 SIS im 2 Yass N 5 GALON NOISS ISD ISAHd eo issue Og ES PeM C41 41005 1587 M gg NUNWISU3 gt NOTSIASY 85661 l1HDIHAdO SILON NOI NOD 54100 ID ZHW lulSAHO 99 OL 03 04808 HLIM TT 00 OL 14S ZHW AAT ZHN 09092 SNOISMHd GdLON NOI B66T ST ES 20 1 031 41004 1597 gg 9 13395 3 1111 NUNISO3 NOTSIASY 5661 1 5 SNId WOW AMY NONONG a eee oT AAAAAAAAAR Sanu SaASIUd TaASIUOU edi XOINX 28221 lt BATT ear eua Sg xo22dx MOHOLX EVIT gt 3837 LOC
51. 7812 CT 25429 9 0505430 11 ete TESS TE N38 EEE NEL omad Dae Xxag oMad IHS X72545 EZE KEES X xa9 reget za LOO 9 m 1 Dre Mel tes Orar 128 Peer e NI diS 0 NTT e Gare 6859 6939 zang 2059 2209 2259 6099 SENS Tango 2059 dl SHS LNO dLSHD MA AS aT 2099 Mr 2289 5 A MA UIUNDIS 93497134 HOLEMOSTY S3LIUDIGQNI SUUS Tu 2919 TES SUUS SUUS Tu SUUS 2089 B66T 8 5 20 Qc 20 T 13395 B 031 JIGOW 1597 No4isU3 NINE 5 34 3715 gt LHOTYAdOD NOTLYOd OHINOO TWYLNAS Ysa 1 1 888588 OU NN mm amp nImxIDnr one 1 NNT OOOOH 22225225222252252252222522522522522 5 le lebe lel lo lc le le lc lc le Lc lc le lo Lc
52. D 32 63 connect to CPU DL 0 31 D 0 63 also connect to the 660 SRAM l O CPU DATA 0 63 and to the SRAM DBB C08 R1 C04 CPU Data Bus Busy signal The CPU that validly asserts DBB is the U1 145 WO current CPU busmaster The 660 does not touch this signal DBDIS K21 1 04 CPU Data Bus DlSable input See 603e UM U1 153 1 DBG_60X G08 U1 26 CPU bus Data Bus Grant 660 asserts DBG while ARTRY is inactive 02 140 to signal that the requesting CPU may take ownership of the CPU data bus is input only on the CPU External agents must not drive this signal DBWO_60X N16 R1 D05 pu CPU Data Bus Write Only input Asserted to allow the CPU to run the data U1 25 tenure of a write out of order See 603e UM DP 0 7 U1 l O CPU Data Parity bus maps to D 0 7 DP1 maps to D 8 15 DP7 maps to U3 D 56 63 Odd parity is used an odd number of bits including the parity bit are SRAM driven high _60 18 CPU Data Error The CPU checks data parity and reports any data 1 beat with bad parity two CPU bus clocks after the for that data beat is output only on the CPU and input only on 660 660 samples to detect L2 parity errors DRTRY AJ01 pu CPU Data Retry input When asserted means that the CPU must invalidate the data from the previous read data beat DRTRY is also application section for details 1
53. Daisy04 E10 D11 Daisy05 E12 D13 Daisy06 E30 F29 Daisy07 E28 F27 Daisy08 E26 F25 Power amp Ground 60X_AVpp B02 U1 209 603e Analog VDD Bypass as recommended in the 603 documentation i f 12 yos E LLL ss GND 4 2 1 7 660 InterChip Communication These signals provide communication between the 663 and the 664 They are generally not intended for use by the system Note that RDL OPEN requires a resistor or other delay component between the 663 and the 664 For more information see Section 2 of the 660 User s Manual Table 2 9 InterChip Communication Signals Signal Name Nodes Description 663 CPU PAR G18 U2 192 660 CPU PAR ERR signal CPU Data Error When as ERR U3 174 BE this signal indicates a parity error on the CPU data bus during B write cycle AOS RR MMRS W20 02 69 660 All Ones Select ROM Remote Mask MEM RD SMPL signal This U3 166 signal is used to force the data bus to 64 one bits While ROM LOAD is asserted this signal is used to determine the location of the ROM When the PCI is burst reading memory MASK MEM RD SMPL is asserted after the first MEM RD SMPL and stays asserted until the PCI to MEM read latch is empty G5220297 00 2 11 Section 2 Signals Preliminary P2werPc Table 2 9 InterChip Communication Signals Continued SignalName MCM Nodes Description
54. ECC mode adds no additional clock cycles to 8 byte CPU to memory write transfers Note that all CPU bursts are composed of 8 byte beats CPU to memory writes of less than eight bytes are handled as RMW cycles which usually require four additional CPU clocks as compared to 8 byte writes 4 4 1 9 PCI to Memory Read in ECC Mode ECC mode adds no additional clock cycles to PCI to memory read transactions 4 4 1 10 PCI to Memory Write in ECC Mode ECC mode has a complex effect on PCI to memory writes During PCI to memory writes the bridge attempts to gather adjacent 4 byte data phases into 8 byte memory writes In response to conditions during a given data phase the bridge either gathers writes 8 bytes or read modify writes as shown in Table 4 13 Gather and 8 byte write operations incur no performance penalties but RMW cycles add from two to four usually three PCI clock cycles to the transaction time The consequences of ECC mode delays on PCI to memory write bursts are minor and are best understood from a few examples The following exam ples assume page hits and no snoop hits G5220297 00 4 27 Section 4 DRAM Preliminary PowerPc Table 4 13 Bridge Response to Various PCI Write Data Phases Bridge Conditions Description of Operation Operation This data phase is not the last data phase and The bridge latches the four bytes from this data This is a 4 byte transfer BE 3 0 0000 and phase into the low four bytes of a hold reg
55. Endian Preliminary Pewer Itis possible to fetch instructions with 4 byte aligned transfers when the cache is turned off In that case the 603e does not munge the address in LE mode The memory controller does not differentiate between instruction and data fetches but the is ineffective because the memory is always read 8 byte wide and data is presented on all 8 byte lanes If the unmunger were used the wrong instruction would be read The net result is illustrated in Figure 11 7 Example 4 byte instruction fetch I2 efgh at address xxxx xxx4 Big Endian Little Endian Swap Off Memory Swap Off Memory LSB LSB m Co O1 O S h f 7 6 5 4 3 2 1 0 xx XX DO gt RO O I X g X X e X X h X g X f X e MSB Unmunge Off Figure 11 7 Wrong Instruction Read When Unmunger is used 11 11 Changing BE LE Mode There are two BE LE mode controls One is inside the 603 CPU and the other is a register bit on the motherboard The 603e CPU interior mode is not visible to the motherboard hard ware The BE mode bit referred to in this document is the register bit on the motherboard It is a bit in space which is memory mapped just like other I O registers It defaults to BE mode The 603e CPU always powers up in the BE mode and begins fetching to fill its cache Con sequently at least the f
56. NC DEPOP NGDEPOP vss DAISY17 U7 29 U8 29 U9 29 U10 29 U6B 26B VDD2 01 113 03 178 07 38 ABUF13 U1 38 U3 196 U7 46 vss re DP5 U1 47 U3 95 U9 20 VDD2 NC DEPOP VSS NC DEPOP VDD2 NC DEPOP VDD2 NC DEPOP VSS NC DEPOP VDD2 gt AA28 AA gt gt gt S gt w gt S S gt Nj 01 gt UJ ABOS ABO E UJ gt gt gt gt gt gt gt gt 5 5 515 5 515 5 5 J Oj Oj A Q Dj O gt UJ e VSS 43 08 VDD2 A ABI A819 1 1 1 1 1 1 1 19 gt UJ 21 22 U1 3 U2 75 U5 37 A12 U1 169 U2 86 U5 63 VSS A20 U1 164 U2 97 U5 15 U6B 13B AB2 AB27 gt gt gt UJ W WwW NM N aj 5 gt 2 e O gt UJ 29 1 VDD2 MA10 S MD52 PCI FRAME 664 PCI TRDY NC DEPOP gt UJ 9 03 113 02 200 02 202 03 168 E E 00 N lt Preliminary 2 22 PowerPc Net Name MCM Nodes 4 A IN U6A 2A U6A 3A U6A 5A U6A 6A U6A 8A U6A 13A U6A 14A U6A 16A U6A 17A U6A 19A U6A 20A U6A 22A U6A 23A ACO5 NC DEPOP 06 ABUF25 U7 23 U8 23 U9 23 U10 23 U6B 43B 07 NC DEPOP 03 U1 110 U3 179 U7 39 09 NC DEPOP P NC DEPOP gt Q U2 51 U3 150 8 R1 F02 U1 2
57. Note that for each memory read operation eight bytes of memory are read and parity on eight bytes is checked regardless of the transfer size Therefore all of memory must be initialized at least up to the end of any cache line that be accessed For the same rea sons memory must be initialized while ECC memory data error checking is in use When the CPU reads from memory the data and accompanying parity information can come from either the L2 SRAM or from DRAM memory If the data is sourced from the L2 the parity information also comes from the L2 If the data is sourced by memory the parity information also comes from memory The L2 SRAM is updated when required using the data and parity from memory During CPU to memory reads the 660 samples the DPE output of the CPU to determine parity errors and reports them back to the CPU via MCP The particular memory read data beat will be terminated normally with 8 2 3 5 CPU Data Bus Parity Error This error is generated when parity error on the CPU data bus is detected during a transfer between the CPU and the 660 The full CPU data bus is always checked for parity regard less of which bytes lanes actually carry valid data The parity is odd which means that an odd number of bits including the parity bit are driven high The 660 directly checks the par ity during CPU write cycles The 660 detects CPU bus parity errors by sampling the signal from the CPU duri
58. VL IOVV SL JTO Figure 6 7 Remote ROM Read Initial Transactions At the completion of the eighth PCI read the 660 drives the assembled double word onto the CPU data bus The 660 then signals completion of the transfer to the CPU G5220297 00 PowerPc iminary Prel Section 6 ROM 9ADn2 Sodus I se uoos se A LL Mosse Od UL 9 ouoo WOY po ornuoo st sni eno SHEACTSLL WY 2 oq uo pauosseop SI ACUI UMOYS se pouosse skeme ST A C uonoesuer ou Suunp 4015 149 099 uo snq Od Idus 8 ACAL 77 OSO Idd ANV 15 8__ 3 gt rool lo clagvo s aqeug 4 PWD 3 eq Iod Idd 8 PPY gt 299 av Tod D LND D 40831 0d SL adv ndo Figure 6 8 Remote ROM Read Final Transactions Remote ROM reads are not pipelined The 660 does not assert to the CPU until the end of the remote ROM read sequence The 660 asserts PCI throughout the entire remote ROM read sequence G5220297 00 6 10 PowerPc Preliminary Section 6 ROM
59. is configured for DRTRY mode and should not be configured for no DRTRY mode In DRTRY mode data is assumed to have been speculatively presented to the CPU and so is held for one clock in the 603e BIU before being presented to the CPU core data consumers The MOM runs at 3 2 603e internal clock to bus clock ratio at 99MHz 66MHz CPU PLL CFG 0 3 is 1100 The 603e may be run at 1 1 core bus ratio and the frequency of the CPU bus clock can be varied See Section 7 Clocks for more information G5220297 00 3 1 A Section 3 CPU amp L2 Preliminary PowerPc 3 2 System Response by CPU Bus Transfer Type All access to the rest of the system is provided to the CPU by the 660 Table 3 1 shows the 660 decoding of CPU bus transfer types Based on TT 0 3 the 660 responds to CPU bus master cycles by generating a read transaction a write transaction or an address only re sponse The 660 ignores TT 4 when it evaluates the transfer type The bridge decodes the target of the transaction based on the address range of the transfer as shown in Table 3 2 The transfer type decoding shown in Table 3 1 combines with the target decoding to produce one of the following operations System memory reads and writes e PCI I O reads and writes PCI configuration reads and writes e PCI interrupt acknowledge reads PCI memory reads and writes System ROM reads and writes Various bridge control register rea
60. topics is beyond the scope of this document The total power entering the MCM cap from the chips is the sum of the power dissipation of each individual chip This power must be removed from the MCM while ensuring that the temperature of the center of the MCM cap does not exceed the value derived in Section 12 2 1 for various operating conditions Table 12 4 shows the required total thermal resis tance from the cap of the MCM to ambient at various ambient temperatures Table 12 4 Required Maximum Thermal Resistance Cap to Ambient Ambient Temperature At Typical Pd At Maximum Pd 12 12 G5220297 00 Power Preliminary Section 12 Electromechanical 12 2 3 Cooling Recommendations Table 12 5 shows the thermal resistance from the MCM cap to ambient at various airflows Table 12 5 Thermal Resistance From Cap to Ambient No Heat Sink Air Flow Linear Feet Per Minute Thermal Resistance to Ambient 15 45 CW 12 7 500 Comparison of Table 12 4 with Table 12 5 shows that a heat sink will be required to meet the MCM maximum cooling requirement 12 2 3 1 Thermal Resistance From Cap to Heat Sink Table 12 6 shows the thermal resistance from the MCM cap to a heat sink for two different cases Each case assumes a 45mm x 45mm heat sink the same size as the MCM cap with 10096 coverage of a thermally conductive adhesive between the cap and the heatsink Table 12 6
61. 02188 AG AL18 MRE7 U2457 ALTS AL 0 2 NC DEPOP c Dv gt gt o gt 2 J27 DEPOP E gt gt c Dv o z DEPOP APO R1 C02 U1 231 J3 NC DEPOP J3 MD42 AJ33 MD43 NC VSS SRAM_ADSP AKO VDD2 5 DAISY11 A VSS 7 DAISY11 8 VDD2 9 DAISY12 AK VSS AK1 DAISY12 AK1 VDD2 AK13 DAISY13 1 VSS AK15 DAISY13 1 VDD2 AK17 DAISY14 1 VDD2 AK19 DAISY14 VSS AK21 DAISY15 AK22 VDD2 AK23 DAISY15 VSS NC AK26 VDD2 AK2 NC VSS NC VDD2 02 184 55 041 ALO1 L2 ALO ALOS DEPOP ALO4 MREO ALO5 NC DEPOP gt gt e 03 91 03 92 gt gt Po A S gt A o U7 1 U8 1 U9 1 U10 1 N J1 AK07 A X A 02 190 J1 AK05 E 08 2 Api AL 27 CC L 3 2 woes EE as uae 02 55 Awa ws o 10 AM11 MDi2 03206 1 MD15 03 213 AMT 15 17 U8 22 17 MD20 03225 19 7 03233 20 MN J1 AK11 E J1 AK09 N J1 AK15 A125 27 J1 AK13 J1 AK19 A rir N J1 AK17 5 gt A o J1 AK23 J1 AK21 U3
62. 3 5 3 CPU to PCI Memory 3 8 3 5 4 CPU to PCI I O Transactions 5 cs suae x 3 8 3 5 5 CPU to PCI Configuration Transactions 3 8 3 5 6 CPU to PCI Interrupt Acknowledge Transaction 3 9 edo ae 3 9 3 6 CPU to BCR Transfers REFS 3 9 37 rbd Sa 3 10 3 7 1 Cache Response to CPU Bus 3 10 3 7 2 Cache Response to PCI Bus 3 11 Oat L2 Configuration prd aA a a 3 11 3 7 4 L2 Organization eeu Uu TR RUM CAE MANI E 3 11 3 7 5 Other L2 Related 3 11 Se A 3 13 MR M M 3 14 Section 4 DRAM OUR KE an Ace 4 1 4 1 Features and Supported Devices 4 1 4 1 1 SIMM Nomenclature 4 2 4 1 11 DRAM SUING ae ee 466 a De a i e ehe aoc ao 4 2 4 1 1 2 DRAM Error Checking RR CI RAT IIR EIS 4 2 4 2 DRAM 4 2 4 2 1 Memory Timing Parameters 4 2 4 2 1 1 Memory Timing Register 1 4 3 4 2 1 2 Me
63. 410 gt 571 eue 1531 799 SALT lt 77791907901 Bucy lt 182 390470557 lt 192 9 SpE 410 BOE lt 189 NI X10 dO15 p99 BOLT pu 255 55 12151 21 gt BdZT 202 gt 29 lt EDET O3H I2d p98 lt 189 1627991 29 WIHT Z1 ed2 OBOTT xag oaa pa 15 I9d p99 0782 59975 95 gt 182 2157151711 gt ru2 x 51080 gt ed2 1S317OIW p99 yal lt 787591 gt amp 1 199 7997 01711 1 ora82 EgEC T29 157nd p99 paz 1797291 22 XAS INI acasiud gt lt 232 1531 E99 28021 ru ET addy Sel gt BOST lt gt 99 TEA I2d NDI 5TASIUGd gt 0782 3S E98 OBUTT lt 222 OL 189 L3638H BTASIUGd OTHS 1631701 E99 lt 29 135346 lt lt gt lt gt pae 789 2145190 gt 0782 HH3 W34 99 SuEE lt 128 91907284 91 5190 BHE 92 HH3 HUd 299 gt 8272 gt 8202 BOS EHET gt Ja ZMCWOus 90Ez lt 29 244 STASICO 909 219 na E39 gt 851 BOWE 58267 lt gt 182 JOWS OBI oco Tas 31 253 ora 9352 3599 gt GBT Fu SOTWRES lt oguez cus
64. 61 8536 664 PCI CLK 1 30 20 6036 CLK PCI DIVO J1 B21 20 0607 CLK PCI DIV1 J1 C20 38 1036 USER PCICLK1 J1 AE01 29 5000 USER_PCICLK2 1 1 42 8536 USER J1 C01 31 1036 USER PCICLKA J1 A11 25 4571 USER PCICLK5 J1 A14 29 7500 USER PCICLK6 J1 E33 3 0000 DAISYO1 J1 D05 3 0000 DAISY01 J1 E04 2 5000 DAISY02 J1 D07 2 5000 DAISY02 J1 E06 2 5000 DAISY03 J1 D09 2 5000 DAISY03 J1 E08 2 5000 DAISY04 J1 D11 2 5000 DAISY04 J1 E10 2 5000 DAISY05 J1 D13 2 5000 DAISY05 J1 E12 2 5000 DAISY06 J1 E30 2 5000 DAISY06 J1 F29 G5220297 00 12 9 Y d Section 12 Electromechanical Preliminary Power Table 12 1 MCM Primary Continued Net Topology DAISY07 J1 E28 DAISY07 J1 F27 DAISY08 J1 E26 DAISY08 J1 F25 DAISY09 J1 E24 DAISYOS J1 F23 DAISY10 J1 E22 DAISY10 J1 F21 DAISY11 J1 AK05 DAISY11 J1 AK07 DAISY12 J1 AK09 DAISY12 J1 AK11 DAISY13 J1 AK13 DAISY13 J1 AK15 DAISY14 J1 AK17 DAISY14 J1 AK19 DAISY15 J1 AK21 DAISY15 J1 AK23 DAISY16 J1 AD03 DAISY16 J1 AF03 DAISY17 J1 Y03 DAISY17 J1 AB03 DAISY18 J1 T03 DAISY18 J1 V03 DAISY19 J1 M03 DAISY19 J1 P03 DAISY20 J1 H03 DAISY20 J1 K03 DAISY20 J1 K03 12 10 G5220297 00 Power Preliminary Section 12 Electromechanical 12 2 MCM Thermal Figure 12 2 contains a simplif
65. 8 200 0 55 200 85 200 25 290 95 240 55 2490 5 2005 5 200 zauan TS eo0n 5 19 6r eddn Sr eddn Sp E tn GONG xeg Cur lt 208 gg T 13395 8661 5 20 4656 LII NOMWISU3 f fie 1 031 41004 1591 SNIMUMG ONMO NOISI 3B 21215 NOILIUBHOdHOO 5661 LHOTYAdOD sna vliva HOSSdOOHd gt pae lt EDET lt rva IED 2199 are gt lt 2 OS opu lt Tool TUS TUI gt BULT OSUL orae OBET Ova yee VOL 82 DBA Sone Eero ED Eads or Gy feos 5259 aano 5296 Ta udo ool jon Ead N Taro wan
66. Page Miss 8 Bank Miss Write Page Miss 8 Bank Hit Write For a pipelined burst transfer immediately following a write Page Hit Read 3333 9333 7222 Page Hit Write 5888 388 4222 Page Miss amp Bark Miss Read Page Miss amp Bank Hit Read Page Miss amp Bank Miss Write Page Miss amp Bank Hit Write Notes See Table 4 2 for notes Page Miss amp Bank Miss Read 8 3 3 3 7 3 3 3 7 2 2 2 4 2 1 11 Conservative Timing Summary Table 4 4 contains a summary of recommended general case conservative page mode DRAM timing The table also shows the resulting performance of the memory controller These conservative timings may be too conservative for many applications These timings meet all of the worst case timing constraints for the systems described in the examples sec tions above 4 12 G5220297 00 PowerPc Preliminary Section 4 DRAM Table 4 4 Page Mode DRAM Conservative Timing Summary 1 consenatve conserve Conservative Conservative Conservative MemoyTmigRegseri 2 x o f Memo TmigRegsterz a Bridge Chipset Options Initial Read Burst 17555 444 __ 10444 Initial Write Burst 5455 544 5344 For a pipelined burst transfer immediately following a read Page Hit Read 5555 4 4444 Page Hit Write 358 33944 3344 Page Miss and Bank Miss Read Page Miss and Bark Hit Read Page Miss and Bank Miss Write
67. 3 1 1 1 3 1 1 1 5220297 00 pan PowerPc Preliminary Section 1 Introduction 1 3 Technology Overview The IBM Multi Chip Module MCM is shown in Figure 1 2 The MCM consists of a 45mm x 45mm cofired dark ceramic substrate upon which are mounted eleven unpackaged semi conductor dice chips capacitors and resistors The top of the substrate and the chips are completely covered by an aluminum cap which is non hermetically sealed to the substrate A thermally conductive grease fills the area between the cap and the chips The MCM is electrically connected to the circuit board planar by solder columns Thermal Grease Ceramic Substrate Solder Columns Figure 1 2 MCM C 1 3 1 Chip Attachment to All die on the MCM are attached to the ceramic substrate using IBM s C4 based flip chip attachment technology In this technology C4 solder balls provide an interconnection be tween the die and the substrate For those vendor die originally designed for wire bond base interconnection additional processing steps were applied to allow the C4 intercon nection Figure 1 3 shows a typical wire bond die In wire bond technology the wafer is sliced into individual dies each die is attached to a wire frame and for each chip pad one end of a wire is bonded to the chip pad and the other end is bonded to the package pin The uses the flip chip process An additional metalization laye
68. 4 28 Bridge Response to Various PCI Write Bursts 4 29 Check Bit Calculation 4 29 Syndrome Decode 4 30 Typical DRAM Module Maximum Input Capacitance 4 33 MCM Response to PCI C 3 0 Bus Commands 5 2 Mapping of PCI Memory Space Part 1 5 3 Mapping of PCI Memory Space Part 2 5 3 Mapping of PCI Master I O Transactions 5 4 PCI to Memory Write Burst Sequence Timing 5 7 xvi G5220297 00 Pewer Preliminary Table 5 6 PCI to Memory Read Burst Sequence Timing 5 9 Table 5 7 Active CAS Lines PCI to Memory Writes BE or LE Mode 5 10 Table 6 1 ROM Read Data and Address Flow 6 4 Table 6 2 ROM Write Data Flow in Little Endian Mode 6 6 Table 6 3 ROM Write Data Flow in Big Endian Mode 6 7 Table 6 4 Remote ROM Read Sequence CPU Address FFFX 6 11 Table 6 5 ROM Write BCR Contents 6 14 Table 7 1 Clock Net Calculations 7 2 Table 7 2 Clock Net Calculations reor toe hm RE REDE 7 3 Table 8 1 Mapping of PCI Memory Space Part 1 8 4 Table 8 2 Invalid CPU Bus Operations 8 7 Table 8 3 664 Pin Reset State sont 6c nant cs Sew na Oe ESSE 8 19 Table 8 4 663 Pin Reset
69. 6 EMMAN ca aa v9 00 ON NIGHD ASIUG Spp IUNDIS cedadn gt 14 19 8 5 19 S3 O HOI 41944 L IHO 4 LU 299 NO 500 2201 SNId 191014 3I1DHIHLISIGJdH NON H3HIId OL 111189 UXOUd LON 3HfiLE DNGHON 2 01 ONIGdHOOOU GQJHIM 110 ONY 4119 40 03593134 I S NOISY 8 5 NOISHd OL LIINE UILINI 30 WUHS ONY xA9 INI 3123448 SI3N O3IdJIGOW LNONId 035937134 075 NOISHAN ONIMHIM d voa 3593 Ol AINGOW 30 LNONId OL 5 HO UM 3593134 y 094538305 5356509 ALlIHUd 99 Wed 991 OL 580451534 TNA 15317 99 NU 1531 p99 3592134 NOISHAN HOI INI NO 03598 533 0310097 LNONId E99 4 2 NOISH3 3593 3H 27 NOISHaN COXID8 WOHS X dddgMS 642012 HUS SpEST 40 SNIHIM U dsod 3H J E NOISHAN 0 2 19 97 04 40151534 531435 GO 404 LIN N3dO UH fido SHON 77 OL dIHD 410151634 40 NOILDJS 0dONOHO NOILdO 9Sc 404 AINGOW 440 991 40 lt 1 gt 2991 071 AINGOW 01 S39NUHO HO UA c262d4 O262d4 Ol Q0dONOHO 3592134 4 NOISHaN OL TOGA Q3HD1IMS ZZW NId WOW NId
70. 89 X I ss LO UlIUd 750701007 730700 Idd 146 LNO Idd S 1x3 IJd SXUNEA SMW 5 Su N3dQ 10 129 N3d TEM azo Nad O7 TEM HA N3d 10u na TNS 08 H3 7357377223 Ad M12 238 WIW 158 cag 238 93M i 1531 OIW r99 1S3170IN eae KALI 0 CAL zu 1531 7989 153 OU JHdlNI e CO gS 9 l ION LNOD 20 13395 d BE ott OS gg S T 1593 f NIME gt H3BLDON NOTSIASY 85661 l1HDIHAdO SINIOd 1631 ONY 11336 Sha 154 799 599 dvd Cu ots NJAA 957 GSW 919078008 78 TESTO 18 cao 2097 12da 00 15 200 15 E09 12d vao 194 S9 I2d Had 857 U0 I2d LNI LEUNG T BEER eave 555555 6 EN x dHdS 4845 xddd ddd NUL QQOYS nU N LOLDI OY CU D NI ID DI CMS 858 x QS OC I OI 01007 04 MANHA I IIIA rini ee ee ee ee ee ee ee eee ee aeuo Idd ASW Idd 238 2 12d S 2938 3199 e134JO08 857 TE ASW yledvaddy E3H
71. Page Miss and Bank Hit Write For a pipelined burst transfer immediately following a write Page Hit Read 185588 44 444 Page Hit Write 9358 6344 5344 Page Miss and Bank Miss Read Page Miss and Bark Hit Read Page Miss and Bank Miss Write Page Miss and Bank Hit Write Notes See Table 4 2 for notes Table 4 5 contains a summary of recommended general case aggressive EDO DRAM tim ing the required control register settings and the resulting performance of the memory controller G5220297 00 4 13 Section 4 DRAM Preliminary PowerPc Table 4 5 EDO DRAM Conservative Timing Summary 1 Pee conservative conservative Conservative Conservative Conservative MemoryTimingRegister 2 MemoyTmigRegserz __ 6 Bridge Chipset Options 3 OC oC 0C intial Read Burst Initial Write Burst 5 4 4 4 5 4 3 3 5 3 3 3 e For a pipelined burst transfer immediately following a read Page Hit Read Page Hi Write 3844 3333 3333 Page Miss amp Bank Miss Read Page Miss amp Bank Hit Read Page Miss amp Bank Miss Write Page Miss 8 Bank Hit Write For a pipelined burst transfer immediately following a write Page Hit Read Page Write 6944 5938 938 Page Miss amp Bank Miss Read Page Miss amp Bank Hit Read Page Miss amp Bank Miss Write Page Miss 8 Bank Hit Write Notes See Table 4 2 for notes 4 2 1 12 Page Hit and Page
72. The characteristics of the memory lines are those stated in the 660 User s Manual The characteristics of the CPU bus lines are the sum of the characteristics of all of the at tached devices For the specifications in the individual documents to apply the must be operated with in the Recommended Operating Conditions of each of the individual devices 12 1 1 AC Electrical Characteristics The single chip module SCM data sheets for the die packaged in the MCM are contained in Appendix G As a first approximation it is accurate to use AC characteristics setup and hold specifications from the SCM data sheets when doing a system timing analysis of the MCM The MCM package contains both the semiconductiors and the wiring network inter connecting them Overall a system timing budget is much improved by the density of the wiring however when referenced from the package AC characteristics differ in theory from those listed in the SCM data sheets Actually such differences are less than 0 5 nanosec G5220297 00 12 1 Section 12 Electromechanical Preliminary Power onds due to the short net lengths in the MCM ceramic substrate and to the extremely small paracitic capacitances of flip chip packaging In order to adjust SCM AC characteristics to values appropriate to the MCM package sub tract out the SCM package delay component of a timing parameter then add back in the corresponding delay for the MCM Exa
73. Thermal Resistance From Cap to Heat Sink Reworkable Adhesive Non Reworkable 12 2 3 2 Thermal Resistance From Heat Sink to Ambient Table 12 7 showsthe required heat sink performance at various ambient temperatures us ing a value of 1 C W for the thermal resistance from the to the heat sink 100 coverage and 45mm x 45mm heat sink base Table 12 7 Required Maximum Thermal Resistance Cap to Ambient Ambient Temperature At Typical Pd At Maximum Pd High performance passive heatsinks with good forced air flow and typical fansinks are able to perform to these specifications G5220297 00 12 13 Section 12 Electromechanical 12 3 MCM Mechanical Drawings 12 3 1 MCM with Cap 47G9687 Thermal Paste Preliminary PowerPc 12 3 2 MCM Without Cap Capacitor Capacitor Chip Chip Chip Chip Cap NC mi SS 1 2 2 UL 7 AIS NS Fe FG NPN D 8 5 sig 88 275 as Sylgard C4 Encapsulant Module 55 lt lt lt lt lt lt Fillet Fillet Sub Assembly 2 8 32 Z Sig HE S aj g rug o C4 Encapsulant Fillet Capacitor Capacitor N Y M AX gt
74. US dabis c abu LA 2 7 ne tecto ed obruo NDERIT 2 8 TET UC IM 2 9 2 1 6 System Interface oo bene Sot eoo pont eene Br ede 2 10 2 1 7 660 InterChip Communication 2 lr rei eR ec REIS 2 11 TestSignalS i GF Es QE 2 13 2 2 NetNames Nodes 2 14 2 2 1 Complete Pin List for 2 14 Section CPU and Level Two Cache 3 1 Sol GPU oic OL aie ORE KOLAR 3 1 Sl OOS rr aed eiae bw Ruf BI e 3 1 3 2 System Response by CPU Bus Transfer Type 3 2 3 3 System Response by CPU Bus Address 3 4 3 3 1 Address Mapping for Non Contiguous I O 3 4 3 3 2 Address Mapping for Contiguous I O 3 6 3 3 3 PCI Final Address Formation 3 6 3 4 CPU to Memory Transfers 3 7 94 T LE ModE VERIS LG Nt Set Seated 3 7 35 GPU tOPOL Transactions tks En ew alles eme eel te ee e 3 7 3 5 1 CPU to PCI Read 2 5255 we Ses ek oe bb db pul pem been 3 7 35 2 GPU to POWE 3 8 3 5 2 4 Eight Byte Writes to the PCI Memory and I O 3 8 G5220297 00 Pewer
75. gt 826 8o8 gt EZ 729 53727 HTD OB2ET lt 7997211 OBI Zd 738 1007 I2d B26T 858 gt 95 104 380815 284 HTD lt gt OET lt gt 4 lt A e gt 11 OBgp OZZL N3dO O I2d OESHZ2T 208 gt T29 72578 47 72 OBET OET lt gt 522 lt 2 2151 gt 051 lt MDOT OEHZT y 8 gt T29 aa 1X3 X15 lt gt OPT ora SL lt gt E0S 29 AdHICIOd OEHZT 228 gt 159 ZI Wo H2 789 1551 EUS E28 p99 3t1 lt gt 2 y 8 6723 SE 159 TAIO ADE lt SWL OBST OZD T3571x3 12d 88 SoEE 909 uol x How lt 222 ONASIS IL oEas oe598 T4N 19d lt gt 2 lt 508 2794 lt 102T 110 1655 lt EDET OGATT lt TH BAL 80S7 29 NI HD OEST lt 58 91733 gt 21 222 NI d15 5 gt lt lt EIST gt 59 Q E 3872 OEUST lt 88 S723 gt 98 Euar xag I5 eget 101 OBgp 2222 30 G0 OEZ 28 123 8UrT OZ N3dO fM de eget lt 189 lt gt amp 51 OEA lt 0 U I2d OEZ yag 133 BOE E29 H31SU4 ud lt EUAT 1 OL gt 821 lt 182 H SpE 30 98ST 258 ero BOE ru yog ug gt lt gt BDET OET 1581 BUST 99 SUHBSUSI HOM INN lt gt 959 208 1123 oped PaT ua
76. lt gt U3 44 U3 45 U3 47 U3 48 U3 50 03 51 03 63 03 64 2 120 1 U2 150 U2 126 U2 136 B U1 200 B U1 199 B B B B B2 gt t N 2 14 5220297 00 PowerPc Preliminary Section 2 Signals Net Name MCM Nodes 011 DAisYo4 012 013 WT_60x WT_60X MCM Nodes 827 ura B28 VDD1 29 664 STOP R1 F04 02 151 UJ 31 INT TO 664 U2 55 UJ J1 E12 VDD1 BR 5 R1 E03 U1 235 S R1 H03 U1 236 V N N 0 USER U4 23 D D 02 PCI AD17 U2 29 U3 41 gg e 3 0 PCI AD19 U2 25 U3 43 a NC DEPOP z S o D 0 lt VDD1 08 R1 C04 U1 145 09 NC DEPOP D D D o 4 2 01 213 603E_CSEO 01 150 5 D D D m VDD1 PLL CFGO OE 245 B U6A 25A U6A 48A U6B 25B U6B 48B 1 1 1 1 1 21 22 2 27 D SHD 02 141 V D D 9 2 O ai 3 VDD1 3 SRESET 60 U1 189 S U 5 S S C 5 5 5 S S S S S N CLK_PLL_EN U4 7 PCI_AD14 U2 32 U3 20 oo N En E12 DAISYOS 1 013
77. m a m t gt A A A A le lc bo Le loe be loe be bo be bo bo bo CTCCTCTTTTTTTTTTTTTTTTTTTTTCTCTTTTTTTTCT CCC HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 555555555555555555555555555555555555 8505555 TEES 1 1 10 8 40 8 1Jn8 N fu t5 11 4bIn 30 2 JJng 289 c 19074 71907 Y o MY OOM CODI CU NF IEEE 3 8 1 ee AIBA ur ar ur ur ur AH EHHH OHHH bbb bobo bo bo bo bo bo bo bo bc bo bo bo bo HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt ONIN Ce Fe eu carr EEYLYA WAW VEUOLUUG WIW SEULUOC WAW WIW 3 3 0 Y 1 190 5 2 HS 0 GSW
78. restrictions That is bursts can start at any byte address and end on any byte address and can be of arbitrary length As per the PCI specification the byte enables are allowed to change on each data phase This has no practical effect on reads but is supported on writes The memory addresses linearly increment by 4 on each beat of the PCI burst All PCI devices must use only linear burst incrementing In ECC mode PCI to memory transactions that result in less than 8 byte writes cause the memory controller in the 660 to execute a read modify write operation during which 8 by G5220297 00 5 5 Section 5 PCI Bus Preliminary PowerPc tes of memory data are read the appropriate bytes are modified the ECC byte is modified and then the resulting 8 byte doubleword is written to memory 5 2 5 PCI to Memory Burst Transfer Completion PCI to memory burst transfers continue to normal completion unless one of the following occurs e The initiating PCI busmaster disconnects The 660 handles all master disconnects correctly e The 660 target disconnects on a 1 M boundary The 660 disconnects on all 1M boundaries e The 660 target disconnects because the PCI disconnect timer has timed out e The CPU retries the snoop cycle that the 660 broadcast on the CPU bus In this case the 660 target retries the PCI busmaster Note that L2 hits do not affect the PCI to memory transaction Read hits have no effect on the L2 and write hits cause the
79. signals that the data is valid For I O every CPU clock that TA is asserted a data beat completes For a single beat cycle TA is only one clock TBEN_60X 116 CPU Time Base Enable input See 60 UM Leave this input pulled high for normal operation 5 U10 Transfer burst indicates a burst transfer of four 64 bit double words on the 60X CPU bus The 664 does not assert TBST during PCI to memory snoop cycles TCO G28 CPU Transfer Code outputs See the 603e UM TC1 L30 N10 CPU bus Transfer Error Acknowledge Assertion of terminates the I O current data tenure and causes a machine check exception or checkstop in the CPU The 664 asserts TEA in the event of a catastrophic or unrecoverable system error TEA can be masked by setting the mask TEA bit in the bridge control registers If XATS is asserted the 660 asserts TEA regardless of the state of MASK_TEA 2 6 G5220297 00 PowerPc Preliminary Section 2 Signals Table 2 4 CPU Bus Signals Continued Signal Name MCM Nodes Nodes Description TLBISYNC R1 E02 Dolo TLBI sync input See 603e UM U1 233 CPU bus transfer start 5 is asserted low for one CPU bus clock to signal a valid address on the address bus to start a transaction TS is an input to the 664 when a CPU busmaster initiates a CPU bus transaction TS is an output of the 664 when it initiates a snoop c
80. these violations are of only theoretical interest since the conditions required to produce the violations are of such low probability The top section of Table 4 2 shows the settings of the memory controller BCRs The next section of the table shows access times from the memory controller idle state which it en ters when it is not servicing a read or write request The other two sections of the table show access times during back to back burst transfers The middle section of the table shows access times for the second of any pair of back to back transfers where the first transfer is a read The lowest section of the table shows access times for the second of any pair of back to back transfers where the first transfer is a write 4 10 G5220297 00 PowerPc Preliminary Section 4 DRAM Table 4 2 Page Mode DRAM Aggressive Timing Summary 1 mm p mem mx D Aggressive Aggressive Aggressive Memory iming Reose 2 no Memory Timing Register2 f BidgeChpsetOpionsa 08 o o f nial Read Bust 10444 0338 m aWrteBus 9444 5344 5433 For a pipelined burst transfer immediately following a read Page Hit Read da 4444 4393 Page Hit Write 93944 3344 sa Page Miss and Bark Hit Read Page Miss and Bank Miss Writ Page Miss and Bank Hit Write For a pipelined burst transfer immediately following a write Page Hit Read 020444
81. thru the 660 can not access this address range so do not map PCI de vices herein unless the CPU will not access them 2 In contiguous mode the CPU thru the 660 can create PCI I O addresses in the 64K to 8M range In non contiguous mode the CPU can only access PCI address es from 0 to 64K 5 1 4 ISA Master Considerations In systems that implement IGN PCI ADS31 and use an Intel SIO memory transactions pro duced on the PCI bus by the SIO on behalf of an ISA master are forwarded to system memory at the corresponding address 0 16M If ISA masters are utilized and the SIO is programmed to forward their cycles to the PCI bus then no other PCI device e g video is allowed to be mapped at the same addresses because contention would result The SIO contains registers to control which ranges of ISA addresses are forwarded to the PCI bus The 660 samples IGN PCI AD31 during PCI busmaster memory transactions from 0 to 2G If IGN PCI AD31 is negated the 660 ignores the transaction and if IGN PCI AD31 is asserted the 660 forwards the transaction to system memory In theory the IGN PCI ADS31 signal can be used by any PCI agent for this purpose but to ensure PR P compliance this signal should be asserted only while the ISA bridge is initiating a PCI to memory transaction on behalf of an ISA master One way to generate IGN PCI AD31 is to AND together the PCI signals of all of the PCI agents except the SIO and the 660 Th
82. 1 the byte swapper is placed be tween the CPU data bus and the memory and PCI data busses This allows the byte lanes to be swapped between the CPU bus and the PCI bus or between the CPU bus and memory but not between the PCI bus and memory Thus when a PCI busmaster accesses memory the MCM does not change either the address or the data location to adjust for en dian mode In either mode data is stored or fetched from memory at the address presented on the PCI bus 11 2 G5220297 00 PowerPc Preliminary Section 11 Endian The 660 cannot tell the endian mode of the CPU directly and so cannot automatically change endian mode to match the CPU There is a control bit located in ISA I O space port 0092 that the CPU can write to in order to set the endian mode of the motherboard Byte Swap Address and Unmunge 1 DO 0 PASS LE Mode Bit Port 92 Figure 11 1 Endian Mode Block Diagram PCI Bus In BE mode the 660 byte swapper is off and data passes through it with no changes In LE mode the byte swapper is on and the order of the byte lanes is rotated swapped about the center As shown in Table 11 3 the data on CPU byte lane 0 1 steered to memory byte lane 7 the data on CPU byte lane 1 is steered to memory byte lane 6 and so on During reads the data flows in the opposite direction over the same paths Table 11 3 660 Bridge Endian Mode Byte Lane Steering Note In this table PCI byte lanes 3 0 refer to the
83. 1 1 1 7 1 1 1 1 1 1 1 PCI to memory write at 66MHz CPU and 33MHz PCI 5 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 4 1 1 2 DRAM Error Checking The 660 supports either no parity or one bit per byte parity DRAM SIMMs in which one par ity bitis associated and accessed with each byte The 660 is BCR programmable to support either no parity even parity or ECC data error detection and correction ECC is implement ed using standard parity SIMMs All installed SIMMs must support the selected error check ing protocol Systems without error checking cost the least checking mode allows a standard lev el of error protection with no performance impact ECC mode allows detection and correc tion of all single bit errors and detection of all two bit errors ECC mode adds one CPU clock to the latency of CPU to memory reads and does not effect the timing of 8 byte and 32 byte writes 4 2 Performance 4 2 1 Memory Timing Parameters Most memory controller timing parameters can be adjusted to maximize the performance of the system with the available resources This adjustment is done by programming vari 4 2 G5220297 00 PowerPc Preliminary Section 4 DRAM ous memory controller BCRs Figure 4 1 shows the various programmable memory timing variables These variables control the number of CPU CLKs between various events The actual amount of time between the events shown will also be affected by va
84. 1 1 SIMM Topologies Table 4 6 shows the various memory module SIMM topologies that the 660 supports Each memory bank can be populated with any supported SIMM Table 4 6 Supported SIMM pelge Wer res x 8Meg 2 10x10 2 4M oes xT 2 We m 2 LTEM T6 Meg 2W bytes 8 bytes ae 12 x 10 __ 1 See BCR A4 to A7 in Section 4 3 1 6 The 660 supports the 168 pin 8 byte SIMMs shown in Table 4 6 which are each arranged as a single bank of 8 byte wide DRAM Each SIMM requires a single RAS line These SIMMs do not have to be installed in pairs The 660 also supports the 72 pin 4 byte SIMMs shown in Table 4 6 which are each ar ranged as two banks of 4 byte wide DRAM only one bank of which may be accessed at a given time Each bank requires RAS line and each bank is addressed by the same 4 16 G5220297 00 PowerPc Preliminary Section 4 DRAM address lines These SIMMs must be installed in pairs of identical devices since it is nec essary to use two 72 pin 4 byte SIMMs to construct an 8 byte wide memory array Since each 72 pin 4 byte SIMM consists of two banks this pair of SIMMs also requires two RAS lines The 660 addresses a given SIMM based on the value of the associated memory bank addressing mode BCR 4 3 1 2 Row and Column Address Generation
85. 1 5 4 Byte lt 6 12 6 2 2 Remote HOM Writes bee he e ES 6 12 6 2 2 1 Write 6 12 52 22 Write Protection ie tired memet s docuit A ally hr Era 6 12 6 2 2 3 Address Size Alignment and Endian Mode 6 12 6 3 Related Bridge Control Registers 6 13 6 3 1 ROM Write Bridge Control Register 6 13 6 3 2 Direct Attach ROM Lockout 6 14 6 3 3 Remote ROM Lockout Bit t RR E EE 6 14 viii G5220297 00 Pewer Preliminary 6 3 4 Other Related BCRS 6 15 Section 7 COCKS ea euo e 7 1 7 1 CPU Clock Physical Design Rules 7 2 fe Clock Freezing ce botte Beate tet ia e ana a este enw pd case 7 5 Section 8 Exceptions cce e 8 1 8 1 8 1 1 Planar Interrupt Handler 8 1 8 1 2 660 INT REQ and INT CPUs 8 1 8 1 3 Interrupt Acknowledge Transactions 8 2 SA NMI REQ ueste ot ted edo estes used ue pd oed de 8 2 8 1 5 Interrupt Handling OE NODE ae oie 8 2 8 1 6 Planar Interrupt Assignments
86. 10 Test Signal Descriptions CPU Test Signals LSSD MODE CPU LSSD test input Leave this input pulled high during normal operation L1 TST CPU LSSD test input Leave this input pulled high during normal operation L2 TST CPU LSSD test input Leave this input pulled high during normal operation 60X CLK OUT CPU system CLocK OUTput CLK OUT is a clock test output TDO CPU JTAG serial scan output TMS CPU JTAG TAP controller mode input Leave this input pulled high during normal operation TDI CPU JTAG serial scan input Leave this input pulled high during normal operation CPU JTAG scan clock input Leave this input pulled high during normal operation G5220297 00 2 13 Section 2 Signals Preliminary P2werPc Table 2 10 Test Signal Descriptions Continued TRST CPU JTAG TAP controller reset Most systems will assert this signal while either HRESET or TRST from the RISCWatch connector are asserted See the applications section 660 Test Signals 663 MIO TEST 0 Chip level test Deassert low for normal operation Do not casually assert 664 MIO TEST this signal 663_TEST Test mode Pull to logic high during normal operation Do not casually as 664_TEST 02 155 sert this signal 2 2 Net Names and MCM Nodes 2 2 1 Complete Pin List for MCM Table 2 11 matches version 5 0 of the schematic Note that while all nets on the MCM are brought to the on
87. 189 lt A NM oj A E E g gt A gt lt gt Al aA oj gt A 2 gt Al A oo 03 90 02 132 R1 F05 U1 187 TIC N 02 164 5220297 00 2 25 Section 2 Signals Pm NetName 7 AVES Notes 1 1077 pins are listed Preliminary Pewer MCM Nodes3 Net Name MGM Nodes ANZ 1 1 03 122 AN1 AN AN ANT ANI ANTS ANZO ANZ ANZ2 ANS AN2A ANZS ANZ ANS AN AN ANS A 2 The net name is the net name from the schematics see Section 13 Use it when referring to a net Many pin sites are not populated with a solder column These sites are indicated with DEPOP in the Net Name column NC in the Net Name column means that the MCM makes no connection to that site 3 The MCM Nodes indicate the pins of the devices that the MCM pin is connected to For example U2 24 repre sents pin 24 of device U2 2 26 G5220297 00 Power Preliminary Section 3 CPU amp L2 Section 3 CPU and Level Two Cache This section discusses topics that are directly related to the CPU CPU bus and Level Two L2 cache including how the 660 bridge decodes CPU initiated transfers as a function of the transfer type and address range For more information refer to the 660 User s Manual The 100 MHz PPC 603e MCM supports CPU bus speeds up to
88. 3 20001 cycle on the CPU bus which causes the L1 and L2 caches to invalidate that sector if there is an address match This insures that there will not be a cache hit during a CPU bus accesses to a memory block which is locked by a PCI agent 4 6 4 PCI Lock Release The bridge responds to the PCI lock release protocol in compliance with the PCI Specifica tion If an agent releases the lock that it owned the bridge releases the lock The bridge generates a normal snoop cycle on the CPU bus 4 32 G5220297 00 PowerPc Preliminary Section 4 DRAM 4 7 Module Loading Considerations The 660 directly drives up to eight 168 pin DRAM modules which typically exhibit an input capacitance of less than 20pf Table 4 19 shows some maximum input capacitance num bers that are typical of the various DRAM modules on the market System designers may wish to buffer MA 11 0 and perhaps WEZ if the system design requires the use of more than two banks of 72 pin SIMMs more than one pair of 2 sided 72 pin SIMMs Table 4 19 Typical DRAM Module Maximum Input Capacitance SIMM Type Maximum Input Capacitance Address 72 pin 4 50pf 50pf 9001 aspi 16 Meg 80pf 95pf 160 190 168 8M 16M 13pf 13pf 18pf 18 4 8 Related Bridge Control Registers Information on these registers is contained in the 660 Bridge Manual Bridge Control Regiser RW Memory
89. 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 7 1 Figure 7 2 Figure 7 3 Figure 8 1 Figure 8 2 Figure 8 3 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Preliminary Pewer Figures Block fsa retins Sd 1 2 EES dos SE 1 5 Chip Wire Bond and Flip Chip Connection 1 5 Flip Chips and Internal Wiring 1 6 Solder Columns 1 6 Non Contiguous PCI I O Address Transformation 3 5 Non Contiguous PCI Address Translation 3 6 Contiguous PCI Address Translation 3 6 L2 Mapping of System Memory 512K Configuration 3 12 SLC L2 Cache Directory 512K Configuration 3 13 Synchronous SRAM 512K 12 3 14 Synchronous TagRAM 512 12 3 14 CPU to Memory Transfer Timing Parameters 4 3 DRAM Logical Implementation 4 16 Example Memory Bank Configuration 4 22 CPU Redd Data ElOW nisa 4 25 PCI Read Data Flow
90. 512K SRAM and a 16K x 15 synchronous tagRAM Is unified write thru direct mapped look aside Caches system memory from 0 to 1G Maintains coherence for 32 byte blocks the PowerPC 60X coherence unit Supplies data to the CPU on burst read hits and snarfs the data on CPU burst read write misses The L2 is not updated during a PCI transaction Ignores CPU single beat reads and invalidates on CPU bus single beat write hits Snoops PCI to memory transactions invalidates on PCI write hits The L2 does not supply data to the PCI on read hits 1 2 3 System Memory Interface The MCM memory controller located in the 660 provides the system DRAM memory inter face as required by the PowerPC Architecture System memory can be accessed from both the CPU bus and the PCI bus The system memory interface Has a 72 bit wide data path 64 data bits and 8 bits of optional ECC or parity data Supports page mode and EDO hyper page mode DRAM Supplies 8 RAS outputs 8 CAS outputs and 2 WE outputs for up to 8 SIMM banks Supports 8 byte 168 pin and 4 byte 72 pin SIMMs for up to 1G of DRAM Allows mixed use of different size SIMMs including mixed 4 byte and 8 byte SIMMs Includes full refresh support including refresh counter and programmable timer Implements burst mode memory address generation for both CPU and PCI bursts Implements both little endian and big endian addressing and byte swapping modes Provides row and column address multiplexing
91. 6 6 7 7 7 1 1 NOT MUNGED NOT UNMUNGED 0 Note the CPU side G5220297 00 11 7 Li Section 11 Endian Preliminary PowerPc For single byte accesses to memory in LE mode Table 11 6 applies Table 11 6 Memory in LE Mode 663 603e 603e BYTE BYTE MEM BYTE CAS A31 30 29 add LANE LANE LANE ACTIVE o o o ejo 1 0 1 0 oj rj o a o o amp 5 o N alo wr 5 gt 5 ula m m Et Uu 2 Note At the CPU side For single byte accesses to PCI in BE mode Table 11 7 applies Table 11 7 PCI in BE Mode 603e 603e BYTE BYTE PCI BYTE A D 1 30 29 LANE LANE LANE 210 3210 LSB 111 0111 NOT UNMUNGED o mW NF MUNGED O Note AD 0 1 set to 00 for all PCI transactions except I O cycles 11 8 G5220297 00 PowerPc Preliminary Section 11 Endian For single byte accesses to PCI in LE mode Table 11 8 applies Table 11 8 PCI in LE Mode 663 603e 603e BYTE BYTE PCI BYTE A31 30 29 add LANE LANE LANE MSB 111 0111 110 1011 101 1101 100 1110 011 0111 010 1011 001 1101 1 LSB 000 1110 MUNGED SWAP UNMUNGED ON Notes At the CPU side AD 0 1 se
92. 8T id WSUS X E CT TT OT 6 idd 9190 An 4 EWS TLNO 5 Idd ANY Q2 6Od ONO LOW Sita 5009 553 0 55 SyceST los xX 9661 27 S T 6 gg 4 13395 5 31111 NOMISU3 NOILIUHOdHOO NOTSIASY 8661 l1HDIHAdO NOI LEWHO ANI a NOIS3U JEOISAH AINGSHSS OL ONICGHODDy G3HIM 38 LSNW SLIN Q3MOTI8 LON SLIN 4915 NIDH 9Ul X DOL X oH Wes x EM 10E 4986 ZX Tg WbOHS x CX 108 THIDE x TH 08 WHS BHIDE WUOHS x AH 128 945 x NI CXI2 Idd X07 Td p99 X2 ndo 73g XO fido p99 x 69 sn 62d SE rr QEN TS O1 SBA BS t1 TS en SA JU vau TS en 6220 624 vy QEM 610 yn 813 EET en yn as tn QED Tet en 2ST En 591 ESS vao To fido SLAIN 1 ONY HIONJ NI S3HONI 6270 OL 15 SLAIN 10 ONIMOT O4 3Hl 40
93. A A A A A A A A A A A A 5 6 19 20 21 22 23 24 25 26 27 28 Table 4 9 Row Addressing PCI Addressing Memory Bank Addressing Mode BCR MA Addressing Mode 7 12x10 11x10 010 AD JAD AD JAD AD JAD AD AD 10x10 11x11 24 23 22 21 20 19 18 17 16 15 14 13 12x12 12x11 011 AD JAD AD JAD AD JAD AD AD 24 23 22 21 20 19 18 17 16 15 14 13 Table 4 10 Column Addressing PCI Addressing Memory Bank Addressing Mode BCR MA Addressing Mode 7 12x10 11x10 010 AD AD AD AD JAD AD 10x10 11x11 26 24 12 11 10 9 8 7 6 5 4 3 12x12 12x11 011 AD AD AD AD JAD JAD AD 26 25 12 11 10 9 8 7 6 5 4 3 G5220297 00 4 17 Section 4 DRAM Preliminary PowerPc In the case of 10x10 addressing MA 9 0 are connected to the DRAM modules In the case of 11x10 or 11x11 connect MA 10 0 and in the case of 12x11 or 12x12 connect MA 11 0 to the DRAM modules 4 3 1 3 DRAM Pages The 660 uses an 8K page size for DRAM page mode determination 4 3 1 4 Supported Transfer Sizes and Alignments The 660 supports all CPU to memory transfer sizes and alignments that do not cross an 8 byte boundary 4 3 1 5 Unpopulated Memory Locations Physical memory does not occupy the entire address space assigned to system memory in the memory map While the Memory Select Error Enable bit 0 e Whenthe CPU
94. EDO DRAM Information aboutthe operation of the 660 with EDO DRAM is distributed throughout this section 4 3 System Memory Addressing 4 3 1 DRAM Logical Organization The DRAM system implemented by the 660 is logically arranged as shown in Figure 4 2 Each block shown in Figure 4 2 is a 9 bit DRAM composed of 8 data bits and 1 parity or check bit that is accessed whenever the 8 data bits are accessed The RAS aka MRE lines strobe in the row address The CAS aka lines strobe in the column address For a block to activate from idle for either a read or a write both the RAS and line to it must be activated in the proper sequence After the initial access the device can deliver data in fast page mode with only 5 strobes The CAS lines can be thought of as byte enables and the RAS lines as bank enables The WE signal goes to all each of the devices in the memory array The OE of each DRAM device is tied active This signal is not required to be deasserted at any time since the DRAMs only enable their output drivers when so instructed by the RAS CAS protocol G5220297 00 4 15 Section 4 DRAM Preliminary PowerPc CAS CAS CASS CAS CASH CAS CASH 0 1 2 3 4 5 6 7 Mem Mem Mem Mem Data Data Data Data Byte Byte Byte Byte 1 amp 2 amp 3 amp 4 amp 5 amp 6 amp 7 Parity Parity i Parity bit 1 bit 2 bit 4 bit 7 Figure 4 2 DRAM Logical Implementation 4 3
95. Each time a PCI or ISA busmaster accesses memory and once again for each time a PCI burst crosses a cache block boundary the 660 broadcasts a snoop operation on the CPU bus If the CPU signals L1 snoop hit by asserting ARTRY the 660 retries the PCI transaction The ISA bridge then removes the grant from the PCI agent who according to PCI protocol releases the bus for at least one cycle and then arbitrates again Mean while the 660 grants the CPU bus to the CPU allowing it to do a snoop push Then the PCI agent again initiates the original transaction During the transaction the 660 L2 cache is monitoring the memory addresses The L2 takes no action on L2 misses and read hits If there is an L2 write hit the L2 marks that block as invalid does not update the block in SRAM and does not affect the PCI transaction L2 operations have no effect on PCI to memory bursts 5 2 3 PCI to PCI Peer Transactions Peer to peer PCI transactions are supported consistent with the memory maps of Table 5 1 Table 5 2 Table 5 3 and Table 5 4 which together show the ranges of different bus com mand transactions that are supported If the ISA MASTER signal is used with the Intel SIO then the SIO is not allowed to perform peer to peer PCI memory transactions in the 0 to 2G range No other transaction types are affected 5 2 4 PCI to System Memory Transactions Single and burst transfers are supported Bursts are supported without special software
96. L2 to invalidate the block e The 660 will target disconnect the PCI busmaster if the refresh timer times out In this case the 660 will disconnect at the end of the current data phase for writes or at the end of the current cache block for reads 5 2 6 PCI to Memory Access Sequence When a PCI access is decoded as a system memory read or write the memory and CPU bus are requested and when granted a snoop cycle to the CPU bus and a memory cycle to system memory are generated If the processor indicates a snoop hit in the L1 cache ARTRY asserted then the memory cycle is abandoned and the PCI cycle is retried The CPU then does a snoop push The L2 cache does not need to do a snoop push because it is write through and therefore system memory always contains the result of all write cycles See Section 3 for more L2 information 5 2 7 PCI to Memory Writes During PCI to memory burst writes the 660 performs data gathering before initiating the cycle to the memory controller The data gathering involves combining two PCI write cycles into one memory write cycle if the address of the first write cycle is even Minimum initial write access time to 70 5 DRAM when the CPU bus is 66MHz and the PCI bus is 33MHz is 5 1 1 1 3 1 1 1 PCI clocks for 4 4 4 4 4 4 4 4 bytes of data 14 PCI clocks for 32 bytes of data Subsequent data phases of the same burst are generally serv iced at 3 1 1 1 3 1 1 1 12 PCI clocks for 32 bytes of data giving a
97. MA MA 11 0 valid out of 664 T 244 max Buffer delay T CAS CAS active out of 664 The second critical path is the data access time from MA plus the setup time into the 663 Make b Col setup CAS pulse width CPW gt T MA max MA 11 0 valid out of 664 1 CLK if EDO T 244 max Buffer delay min DRAM data valid from col addr valid MD setup max MEM DATA setup into 663 6 MTR2 1 0 RAS to 5 delay The minimum RAS to CAS delay provided by the 660 must exceed the timing of the critical path that determines the to CAS delay which is the data access time from RAS plus the setup time into the 663 Make RAS to CAS delay RCD CAS pulse width CPW gt T RAS fall max max 660 RAS fall time note 1 1 CLK if EDO Trac min DRAM data access from RAS MD setup max MEM_DATA setup into 663 7 MTR1 5 Row address hold time The row address hold time must be set to the RAS to CAS delay minus the Column address setup The timing for the row address hold time can also be calculated as follows Make 4 6 G5220297 00 PowerPc Preliminary Section 4 DRAM Row addr hold gt Trah min DRAM min row hold 244 Buffer delay T 11 0 valid out of 664 T RAS fall max max 660 RAS f
98. ROM control signals Local bus signals used for control functions by the planar Understanding all of these groups is vital to the use of the MCM Pay particular attention to those signals broken at the MCM level and which are reconnected at the planar Those nets are associated with pairs the names of which are prefaced by the letter X When applying the MCM to a system design it is recommended that the designer review the schematics for both the MCM see Section 13 and the example planar see Appendix F Although the example planar is a specific design implementation of the MCM most interface signals are used in a manner that would be common to any PowerPC sys tem design A review of the planar schematics and MCM and planar component data sheets see Appendix G will quickly answer most questions concerning how to interface with the I O Note that it is not intended for the user to interface with all of the I O Section 2 con tains I O listings that distinguish between signals intended for application use and those broken out only for manufacturing purposes G5220297 00 1 7 Section 1 Introduction Preliminary Power ii Co G5220297 00 PowerPc Preliminary S
99. State 8 19 Table 8 5 Configuration Strapping Options 8 20 Table 8 6 LSSD Test Mode Pin Definitions 8 21 Table 9 1 Configuration Address 9 2 Table 9 2 660 Bridge Indexed BCR Listing 9 2 Table 11 1 Mode Operations 11 1 Table 11 2 603e LE Mode Address Transform 11 2 Table 11 3 660 Bridge Endian Mode Byte Lane Steering 11 3 Table 11 4 660 Bit Transfer 11 4 Table 11 5 Memory Mode 11 7 Table 11 6 Memory LE Mode 11 8 Table 11 7 PCI in Mode 11 8 Table 11 8 PCIin LE Mode eeu 11 9 Table 11 9 Two Byte Transfer Information 11 11 Table 11 10 Rearranged Two Byte Transfer Information 11 11 Table 11 11 Four Byte Transfer Information 11 13 Table 11 12 Rearranged Four Byte Transfer Information 11 14 Table 12 1 MOM Primary I O 12 4 Table 12 2 Thermal Specifications for MCM Chips Typical Pd 12 12 Table 12 3 Thermal Specifications for Chips Maximum Pd 12 12 Table 12 4 Required Maximum Thermal Res
100. TRDY 1 This delay is controlled by the system arbiter 2 PCI Bus not parked on CPU If the PCI bus is parked on the CPU is asserted here 3 IRDY is always asserted as FRAME is deasserted IRDY is deasserted on the clock that TRDY is sampled active 4 This delay is paced by the remote ROM controller The PCI agent may assert TRDY as soon as it samples FRAME active STOP not asserted during the transaction Figure 6 9 Remote ROM Write 6 3 Related Bridge Control Registers The two BCRs most closely related to the ROM system are the ROM write BCR and the ROM lockout register Writes to the ROM are accomplished through the ROM write BCR Write protection is provided by means of the ROM lockout BCR 6 3 1 ROM Write Bridge Control Register Direct Access FFFF FFFOh Write Only Reset NA This 32 bit write only register is used to program the ROM in direct attach ROM systems see section 6 1 2 This register must be written by means of a 4 byte transfer Bits are shown with little endian labels G5220297 00 6 13 Section 6 ROM Preliminary PowerPc TEE ll IEEE pups EET EAT ERR PET or pes pa 53 p2 n po ese sp nasa Table 6 5 ROM Write BCR Contents BCR Byte Content in Little Endian System Content in Big Endian System ROM Data ROM Address low byte Table 6 5 Table 6 5 Table 6 5 ROM Address high byte ROM A
101. The 660 formats the row and column addresses presented to the DRAM based on the orga nization of the DRAM In memory bank addressing mode 2 the bridge is configured to ad dress devices that require 12x10 11x11 11x10 or 10x10 bit row x column addressing In memory bank addressing mode 3 the bridge is configured to address devices that re quire 12x12 or 12x11 bit row x column addressing no other addressing modes are cur rently available Table 4 7 and Table 4 8 show which CPU address bits are driven onto the memory address bus during CPU to memory transfers Table 4 9 and Table 4 10 show which PCI AD ad dress bits are driven onto the memory address bus during PCI to memory transfers These address line assignments are not affected by the endian mode of the system The addres sing mode is selected using the memory bank addressing mode BCRs see Section 4 3 1 6 The addressing mode of each bank of memory is individually configurable Table 4 7 Row Addressing CPU Addressing Memory Bank Addressing Mode BCR MA Addressing Mode 7 12x10 11x10 010 A A A A A A A A A A A A 10x10 11x11 Mode 2 7 8 9 10 11 12 13 14 15 16 17 18 12x12 12x11 011 A A A A A A A A A A A A Mode 3 7 8 9 10 11 12 13 14 15 16 17 18 Table 4 8 Column Addressing CPU Addressing Memory Bank Addressing Mode BCR MA Addressing Mode 7 12x10 11x10 010 A A A A A A A A A A A A 10x10 11x11 5 7 19 20 21 22 23 24 25 26 27 28 12x12 12x11 011
102. U3 152 When the memory write latch is sampling data this signal controls the memory write multiplexer Pull up with 10K nominal resistor to select during reset 603e in 3 2 core bus clock mode PCI AD OE N14 02 195 660 PCI Data Output Enable signal While asserted the 663 drives the U3 144 PCI AD bus Note This is an asynchronous input to the 663 PCI EXT SEL 014 U2 67 660 PCI Read Extension Select PCI Write Extension Select signal U3 153 When the PCI is reading from memory this signal controls the PCI read extension multiplexer PCI OL OPEN W14 02 64 660 PCI Other Latches Open signal This signal controls the latch en U3 165 ables for the PCI to MEM read latch the PCI read extension latch and the PCI write extension latch PCI OUT SEL R14 U2 68 660 PCI Output Select signal When asserted memory data is routed U3 169 to the PCI output bus else CPU data is routed to the PCI output bus This signal is asynchronous ROM LOAD U20 U2 70 660 ROM Load signal This signal is used to load data from a ROM one U3 160 byte at a time until eight bytes are received then pass the eight bytes to the CPU 663 5 G20 U2 193 660 SBE Single Bit Error signal When asserted indicates a correct 03 175 able single bit error has occurred on the memory data bus This signal is valid only on the CPU following the assertion of MEM RD SMPL If the memory is notin ECC mode this signal is unde fined 2 1 8 Test Signals Table 2
103. agreement including the contents of the 100 MHz PPC 603 and any components thereof is limited to twenty five thousand dollars 25 000 00 or its equivalent in your local currency and is without regard to the number of items in the MCM that caused the damage This limitation will apply except as otherwise stated in this Section regardless of the form ofthe action including negligence This limitation will not apply to claims by you for bodily injury or damages to real property or tangible personalproperty In no event will IBM be liable for any lost profits lost savings or any incidental damages or economic consequential dam ages even if IBM has been advised of the possibility of such damages or for any damages caused by your failure to perform your responsibi lities In addition IBM will not be liable for any damages claimed by you based on any third party claim Some jurisdictions do not allow these limitations or exclusions so they may not apply to you RISK OF LOSS You are responsible for all risk of loss or damage to the 100 MHz PPC 603 upon its delivery to you IBM TRADEMARKS AND TRADE NAMES This Agreement does not give you any rights to use any of IBM s trade names or trademarks You agree that should IBM determine that any of your advertising promotional or other materials are inaccurate or misleading with respect to IBM trademarks or trade names that you will upon written notice from IBM change or correct such ma
104. also 32M populated by an 8 byte x 8M 32M SIMM Using the same configuration banks 1 and 2 could also be implemented using two 8 byte x 4M 32M SIMMs Bank 3 is configured to the same size as bank 1 plus bank 2 and is imple mented using a single 8 byte x 8M 64M SIMM 4 22 G5220297 00 PowerPc Preliminary Section 4 DRAM Bank 4 is not populated so set memory bank enable BCR bit D4 to 0 The data in the start ing extended starting ending and extended ending address BCRs for bank 4 is ignored Note that empty memory banks are allowed but that gaps in the DRAM space are not al lowed For proper operation program the bridge to execute memory accesses at the speed of the slowest device If ECC or parity is selected all devices must support the capability And if the bridge is programmed to utilize hyper page mode all devices must support extended data out transfers Table 4 12 Example Memory Bank Starting and Ending Address Configuration Address BCR SIME Size 00000000 88 00800000 89 _32 om Address BCR Data Dats 96 00 Fo e1 os o27F FEF 00 0280 0000 sa 00 82 28 oa7FFFeF oa vo ss 48 se oo 0860 0000 so ss owrrrer so oo oneooooo st oo ee ae rer oE 99 27 z om 12 0 0000 sr or 8
105. bank 2 MPC970 BCLK4 output X SRAM The CPU bus clock input of SRAM bank 3 These 10 are the nominally 66MHz CPU bus clocks They are intended to be used in pairs where the CLOCK output is connected on the planar to the X CLOCK input The MPC970 drives the CLOCK outputs and the normal consumer of that clock is connected to the X CLOCK input A series termination resistor and or EMC components can be used as determined by the application MPC970 TAG BCLK MPC970 BCLK EN output X TAG BCLK The CLK input of the TAG 664 PCI CLK MPC970 PCI CLK1 output Normally connected to PCI CLK IN This clock is intended to be run at one half of the CPU bus frequency See the PCI Bus section 660 PCI CLK input Normally connected to 664 PCI CLK MPC970 PCI CLKO output These User PCI Clock outputs MPC970 PCI CLK output are intended for use as PCI clocks on the planar They MPC970 PCI CLKS3 output nominally one half the MPC970 PCI 4 output frequency of the CPU bus USER 5 MPC970 PCI CLK5 output clock See the PCI Bus USER PCICLK6 MPC970 PCI CLK6 output section Clock Control See 970 data sheet for more information Ker 0440 MPG970 input Tie to GND Tor normal operation OLK Divo 016 0451 MPOS7O input GND or normal operation B17 U amp z7 MPCS70 input Tie to GND for normal operation GOM_
106. control is saved in register and the CPU number is save in register C7h bit 5 If the error occurs while the PCI is accessing memory register C7h bit 4 is set to indicate the error occurred during a PCI cycle The PCI address is saved in register C8h The PCI control is saved in register C7h This error can be reset by writing a 1 to register C1h bit 2 Note that register locations listed above are used to indicate memory parity errors if the memory is being operated in parity mode This error cannot be controlled by means of the 650 compatible register set G5220297 00 8 13 a Section 8 Exceptions Preliminary PowerPc 8 2 6 4 System Memory Multi Bit ECC Error When memory is being operated in ECC mode this error is generated if a multi bit ECC error uncorrectable is detected during a read from system memory The multi bit ECC error can be controlled by the indexed register set The mask is at regis ter COh bit 3 If an error is detected the status bit at register C1h bit is set If the error occurs while the CPU is accessing memory then register C7h bit 4 is cleared to indicate the error occurred during a CPU cycle The CPU bus address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in bit 7 of register C7h If the error occurs while the PCI is accessing memory then register C7h bit 4 is set to indi cate the error occurred during a PCI cycle The PCI address is sav
107. correspond ing RAS decode For example RAS 4 corresponds to the BCRs at index 84h and 8Ch The eight least significant bits of the bank starting address are contained in the starting ad dress register and the most significant bits come from the corresponding extended starting address register The starting address of the bank is entered with the least significant 20 bits truncated These BCRs must be programmed in conjunction with the ending address and extended ending address registers Program the banks in ascending order such that for n 010 6 the starting address of bank n 1 is higher than the starting address of bank n Each bank must be located in the 0 to 1G address range See section 4 3 1 12 D7 o6 Ds o4 23 p2 pino A20 of start address A21 of start address 2MB A22 of start address 4MB A23 of start address SMB A24 of start address 16 A25 of start address 32 A26 of start address 64MB A27 of start address 128 4 3 1 8 Memory Bank Extended Starting Address BCRs Reset to 00h each BCR This array of eight BCRs along with the eight starting address registers contains the start ing address for each memory bank These BCRs contain the most significant address bits of the starting address of the corresponding bank bre os osos A28 of start address 256MB A29 of start address 512 Reserved 4 3 1 9 Memory Bank Ending Address BCRs Reset to 00h each B
108. critical path that determines the CAS precharge requirement is CAS rising to CAS falling The minimum CAS pre charge time supplied by the 660 must exceed the minimum precharge time re quired by the DRAM Make G5220297 00 4 5 Section 4 DRAM Preliminary PowerPc CAS precharge CP gt DRAM min CAS precharge 4 MTR2 3 2 CAS pulse width CPW The critical path that determines the CAS pulse width requirement is the data access time from CAS plus the setup time into the 663 Thus the minimum CAS pulse width provided by the 660 must exceed the minimum CAS pulse width required by the DRAM plus these fac tors Note that the 663 samples memory data on the clock that CAS is deasserted for standard DRAM and on the clock after CAS is deasserted for EDO DRAM Make CAS pulse width CPW gt T CAS fall max active out if 664 1 CLK if EDO DRAM data access from MD setup MEM DATA setup into 663 The factor 1 CLK if EDO is included in the equation only if EDO DRAM is used Note that CPW must be set to 3 or fewer clocks 5 MTR2 7 Column Address Setup ASC There are two critical paths that determine the Col addr setup requirement The minimum column address setup time supplied by the 660 must exceed both constraints The first is Tasc of the memory Make Col Setup gt Tasc min DRAM min col addr setup time
109. data bytes associated with PCI 3 01 when the third least significant bit of the target PCI address PCI AD 29 is 0 as coded in the instruction PCI byte lanes 7 4 refer to the data bytes associated with PCI C BE 3 0 when PCI AD 29 is a 1 G5220297 00 11 3 Li p Section 11 Endian Preliminary PowerPc 11 3 Bit Ordering Within Bytes The LE convention of numbering bits is followed for the memory and PCI busses and the CPU busses are labeled in BE nomenclature The various busses are connected to the 660 with their traditional native significance maintained BE for CPU and LE for PCI and memory so that MSb connects to MSb and so on The bit paths between the CPU and memory data busses are shown in Table 11 4 for both BE and LE mode operation Table 11 4 660 Bit Transfer hurt N A N A gt e 5 A AB 54 A AR A A gt N N A A gt 99 o AR N N N N m d
110. done before any DRAM accesses occur then no bus activity will have been affected by the unknown state of the counters before this point e When RESET is deasserted the DUAL REF signal begins toggling The phase of this toggling never effects any bus operations and therefore need not be known for deterministic operation of the 660 However if it is still desirable to control the phase of DUAL CTRL REF then the following timing requirements must be met for the deassertion of RESET Setup 4 4ns relative to a rising CPU clock edge Hold gt Ons relative to a rising CPU clock edge 8 4 Test Modes 8 4 4 CPU Test The three test pins of the 603e LLSD_MODE L1_TST_CLK amp 12 5 are only supported for use during internal factory testing They are not supported for customer use Refer to the RISCWatch documentation for use of the JTAG port for debugging and diag nostic purposes 8 4 2 660 Test Tiethe MIO TEST input of both the 663 and the 664 low during normal operation IBM does not support any use of MIO test mode by external customers 8 20 G5220297 00 PowerPc Preliminary Section 8 Exceptions MIO test mode is enabled on the 663 asynchronously by asserting MIO TEST to the 663 MIO test mode is enabled on the 664 asynchronously by asserting MIO TEST to the 664 IBM uses LSSD test mode to verify the switching levels of the inputs of the 663 and the 664 The TEST and MIO TEST pins
111. eg gt C22 N3dO lH nd x gt 88 lt gt 5 2 suse gt uar 35 gt lt 999 HD NaI r89 x gt lt lt gt 182 Geo oH lt gt 8222 288 SE23 8urT 542 S277 lt 909 HD NaI E99 x 2T9 xag o38o BITE 258 E23 2222 N3dO UH og ec gt 959 Cx lt 198 xag 590 lt 88 EED BOE E29 p99 INS lt 90 2 gt 959 101X BOET 99 13534 000974 Moa lt 288 cea lt BerT OZ na gt lt gt pae 549 eget lt 189 lt E gt Bote 858 gt 95 2 159 135 ON gt 199 0 lt 2961 lt 32 pua lt 29 g c gt 888 BEDI gt 92 lt E09 AO ULL HD lt egez SADa aan r84 EdEE XIT HTa o82gz gt 1357 4347 4713 2999 SN DIDA 35 25271 Oo 58 22 ge 8253 ose 9 X15 2909 p DIDA 436 gt E 0ST oe598 16 12 gt lt 808 2233 gt EZ T7259 IIA yal EBEC EN DI2d u3en EIST E09 tt 8261 lt 898 9293 gt 128 ANIC 15d 15 pa EBEC ex DIDA u3sn gt 261 598 OB8261 lt 898 Seo gt T29 31U1SIHLl HW HTD yal TH DIDA u3en Bos E49 lt
112. error to the CPU as a PCI bus data parity error while PCI master using MCP 8 2 4 2 PCI Target Abort Received While PCI Master This error is generated when a target abort is received on the PCI bus during a cycle which is mastered by the 660 for CPU access to the PCI bus The CPU cycle is terminated with a TEA the Error Address register is held and the Illegal Transfer Error register is set This error can be controlled by the indexed register set The mask is at register COh bit 7 If an error is detected the status bit at register O6h bit 12 is set Register C7h bit 4 is cleared to indicate an error on a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is save in register C7h bit 5 This error can be reset by writing a 1 to register O6h bit 12 This error cannot be controlled by means of the 650 compatible register set 8 2 4 3 PCI Master Abort Detected While PCI Master This error is generated when a master abort is detected on the PCI bus during a cycle which is mastered by the 660 for CPU access to the PCI bus Master aborts occur when no target claims a PCI memory or cycle PCI_DEVSEL is never asserted The 660 master aborts if no agent responds with DEVSEL within eight clocks after the start of a CPU to PCI cycle The cycle is ended with a response to the CPU all 1 s data is returned on reads the Transfer Error register is set and the Error Addr
113. first floppy disk drive If this fails the system will attempt to boot from the SCSI device programmed to SCSI ID 6 If this fails the system will attempt to boot from IDE drive zero master PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp 11 Rights Reserved Boot Device Selection Set Boot Device 1 Floppy 1 Set Boot Device 2 SCSI ID 6 Set Boot Device 3 IDE Drive 0 Set Boot Device 4 None Go to Previous Menu Press to select item Press to change item Figure 10 12 Boot Devices Screen If the system fails to find a valid boot image as discussed in Section 10 3 on any of the selected boot devices or if no boot device is selected the user will be prompted to enter the configuration menu to select a valid boot device Any changes made in boot device selection is saved when the Save and Exit option on the main menu is selected Exiting the system configuration utility in any other manner will cause boot device changes to be lost G5220297 00 10 13 p Section 10 Firmware Preliminary Power Set Date and Time The set date and time screen allows the date and time stored in the battery backed real time clock to be updated The screen is shown in Figure 10 13 To change the time the left and right arrow keys are used to select the digit to modify and the digit is then typed over with the number keys The date or time will be updated when Enter or eith
114. hor a vss EA EIUS VDD2 D49 U1 107 U3 99 U10 35 22 65 2 555 002 2222 25 06 2 VSS No p lt AH12 AH1 AH1 AH1 AH1 AH1 AH1 AH1 AH20 gt N mp a I NIO VDD2 AP1 1 01 01 230 ss MA7 U2 181 AH32 VDD2 H3 MD44 AJO1 DRTRY 0 CKSTP_OUT NC DEPOP AH28 AH gt w gt T 03 93 R1 H01 U1 156 R1 J01 U1 216 01 115 03 176 07 34 U1 99 U3 187 U7 44 NC DEPOP D12 U1 91 U3 208 U7 14 DEP D30 U1 67 U3 32 U8 18 NC DEPOP D36 U1 135 U3 67 U9 40 N DER D42 U1 126 U3 80 U9 12 N DERE D48 U1 117 U3 98 U10 34 NC DEPOP D54 U1 100 U3 114 U10 44 N U1 58 U3 127 U10 14 gt NC DEPOP gt d gt gt gt 9 LU NENNEN Lo 1 POs ell duos ___ D NIE 1 UI ANNI NDE pax EDE d gt gt gt gt gt gt gt gt gt cj a a a a a a 5 a a CO NiO Oy RY 2 gt N c EG c gt c G5220297 00 PowerPc Preliminary Section 2 Signals MCM Nodes Net Name ____ Nodes 06 maen GK Lo 08 MRE2 U2 162 at ______ AL14 02159
115. in big endian mode so the buffer does not swap the data bytes If the register data is 452301ABh then ABh is written to address 012345h of the ROM Only single beat four byte write transfers store word are supported Table 6 3 ROM Write Data Flow in Big Endian Mode CPU Register CPU DATA 0 63 PCI AD 31 0 ROM Signal ROM Address low byte ATO 815 ROM Address mid byte ALIS FP 0 0 0 16 23 ROM Address high byte 23 16 23 16 24 31 ROM Data 31 24 D 7 0 6 2 Remote ROM Mode In a system that uses the remote ROM mode the ROM device attaches to a PCI agent When a CPU busmaster reads from memory addresses mapped to ROM space the 660 arbitrates for the PCI bus and then masters a memory read transaction on the PCI bus The PCI agent claims the transaction and supplies the ROM device data CPU writes to the ROM ROM write protection operations are also forwarded to the PCI agent As shown in Figure 6 6 the ROM access flows from the CPU to the 660 over the CPU bus from the 660 to the PCI agent over the PCI bus and from the PCI agent to the ROM device The ROM device attaches to the PCI agent not to the PCI AD lines so a PCI bus load is saved by the remote ROM method G5220297 00 6 7 Section 6 ROM Preliminary PowerPc System ROM Address Control Data Figure 6 6 Remote ROM Connections 6 2 1 Remote ROM Reads For remote ROM reads the 660 arbitrates for the PCI bus initiates eight single byt
116. information e The NMI REQ input contains no edge detection logic The 660 has no memory of any previous state of NMI REQ e In general the assertion of NMI REQ has no effect on any other processes in the 660 e is generally asserted continuously while NMI REQ is sampled valid howev er f an error was detected before REQ was detected then the error handling logic will not sample the NMI REQ input and thus will not detect it until the previous error is cleared using the appropriate BCRs f the NMI REQ is deasserted before the previous error is cleared the NMI REQ will be lost e If REQ is still asserted when the previous error is cleared then the NMI REQ will be sampled asserted and MCP will begin to be asserted 8 14 G5220297 00 PowerPc Preliminary Section 8 Exceptions The 660 will not assert MCP while NMI REQ is active unless MCP assertion is en abled in BCR BA bit 0 As before if NMI REQ is active when assertion is en abled then MCP5 will be asserted Unlike with the bus related error sources when the 660 samples NMI REQ valid it does not disable further error detection Thus PCI and CPU bus related errors will still be detected and handled in the normal fashion However if the detected bus related error causes to be asserted for 2 CPU clocks then at the end of the second CPU clock MCP will be and remain deasserted until the current error is cleared us i
117. interrupt is pending A DEFAULT 7 vector is returned in this case This is the same vector that is returned on spurious interrupts Parity error in Flash ROM Parity is not stored in the Flash ROM Therefore the memory parity error signal and the DPE signal are ignored during ROM reads The Flash or ROM should include CRC with software checking to insure integrity Write to Flash with TSIZ other than 4 This will cause indeterminate data to be written into the Flash at an indeterminate ad dress Caching ROM space An L1 or CB L2 cast out will cause indeterminate results Running any cycle to the PCI configuration space with an undefined address Some of these could potentially cause damage See the warning under the PCI configu ration cycle section Accessing any ISA device with the wrong data size for that device Indeterminate results will occur 8 17 a Section 8 Exceptions Preliminary PowerPc 8 3 Resets The RESET pin of the 664 must be asserted to initialize the 660 before proper operation commences The 663 does not have a reset pin Since the operation of the 663 is controlled by the 664 the entire 660 bridge will be properly initialized by the proper assertion of 8 3 1 CPU Reset For information of CPU SRESET and HRESET see the 603e user manual 8 3 2 660 Reset The entire 660 is reset to the correct initial state by the proper assertion of the RESET input ofthe 664 POWER GOOD RESE
118. lt 222 XA9 N38L lt gt 789 828T 288 2123 gt 182 lt 1594708 8227 run 53199791 T89 r rT gost 5258 6853 gt p l lt 2 F93 98 89L7 lt 199 3091 T89 r rT lt gt 208 8853 rue gt BOLT NITALOTIM SL 2929 72 3A 206 2 lt org g PLT 1ML OBgp 0232 N3dO eM 0206 lt 288 2853 gt 292 T5eT 348 EGET 0782 3 951 OBgp 0232 TANS de AA 206 lt 298 2453 lt gt 902 Q E VOL q22T ain OBI 30 BIO WIN lt gt 206 lt 288 1223 Bgp TAL SW HH 509 ESET 07182 ale 991 702 Q E 387 W34 lt 202 dH 712 POL PLT 017901 2089 lt gt S89 lt A L gt 2 29 gt dee gt B461 lt 1027 5 lt 21 2 gt lt 189 INNIS DOL 209 209 a ES9 OW gt 282 lt 221 390 ru Gav BgAT ru N eMd Sol 2BDZT 22 xa dou gt 2 YZZ gt 01 EDET rH2 palT 0782 DOL 2989 lt 2772 394 OTUGT 02298 2 2 gt OPT lt gt 502 lt PIL POLT ALO SOL 989 r rT 7 OW lt 182
119. must equal 00 for the MCM to access the directory 3 7 5 Other L2 Related BCRs See Table 3 6 Table 3 6 Other L2 Related BCRs Brags Goni Rege oe Ems oe Paty erer Reader oes merem 122000 5220297 00 3 11 Section 3 CPU amp L2 Preliminary Power Memory Index Address A 14 26 0 31 2 13 8K 1 16 2 The L2 considers the 1G of cacheable system memory to be logically organized into 4K pages Every member of a given page has the same address tag which in this case is defined Tag 4K 1 as bits A 2 13 of the address 1G 256K Each page consists of 8K blocks of memory where each block consists of one 32 byte doubleword of memory A block 768 32 is referred to within the page by the index which is defined as bits A 14 26 of the address oe Thus each block of memory in the 0 to 1G range has a tag 768 32 A 2 13 which ranges from 0 to 4K 1 and an index 14 26 which ranges from 0 to 8K 1 All of the blocks that have the same index are said to be in the same congruence class or 512 32 set Each block in a given set has a unique tag Some map 512K ping examples 512K 32 256K432 256 Line Memory Address 0 256 32 32 768K 32 0 Figure 3 4 L2 Mapping of System Memory 512K Configurati
120. nor maintains the status of smaller units of memory Typical L2 read performance is 3 1 1 1 followed by 2 1 1 1 on pipelined reads For more information on the operation and capabilities of the L2 see the 660 User s Manual 3 7 1 Cache Response to CPU Bus The L2 supplies data to the CPU bus on burst read hits and snarfs the data updates the SRAM data while the memory controller is accessing the DRAM on CPU burst read write misses It snoops PCI to memory transactions and it invalidates on PCI write hits The L2 does not supply data to the PCI on read hits Table 3 4 L2 Cache Responses to CPU Bus Cycles TT 0 3 CPU Bus Cycle Cache Hit Action Action ee 9 Flush seotor eias Mer CR hie 0 Resend woe Resend j meme nee NE ze u m __ _______ ___ j me L2 ignores CPU bus single beat reads and invalidates on CPU bus single beat write hits Table 3 4 shows the actions taken by the L2 cache based on transfer type and single beat or burst mode The CPU cache inhibit signal is not used because cache inhibited bus operations always single beat The 660 does not use TT 4 Accesses to populated memory are snooped by L2 regardless of the state of GBL
121. not show the posted write buffers and other internal details Data 64 660 Bridge Data 64 Memory Check 8 E Correct _ TEAM or MCP Figure 4 4 CPU Read Data Flow Data 64 660 Bridge Data 32 emory Check 8 i Correct mH PCI_SERR Figure 4 5 PCI Read Data Flow 4 4 1 4 Eight Byte Writes Figure 4 6 shows the simplified data flow in a 660 system during 8 byte CPU to memory writes The data flows from the CPU into the bridge and out onto the memory data bus The bridge generates the check bits based on the eight bytes of data and stores them in memory with the data Memory 660 Bridge Generator Figure 4 6 CPU 8 Byte Write Data Flow Figure 4 7 shows the simplified data flow in a 660 based system during gathered PCI to memory 8 byte writes During the first of the two gathered data phases A the data flows from the PCI bus into a 4 byte hold latch in the bridge On the next data phase B the next 4 bytes of PCI data flows into the bridge where it is combined with the data from the pre vious data phase The 8 byte data then flows onto the memory data bus The bridge gener ates the check bits based on the 8 byte data and stores them in memory with the data G5220297 00 4 25 Section 4 DRAM Preliminary PowerPc 660 Bridge Data 32 660 Bridge Data 64 System Memory Figure 4 7 PCI 8 Byte Write Data Flow Note that if either or both of the two gathered PCI data phases is a w
122. odd parity generation and checking protocol generating parity on memory G5220297 00 4 23 Section 4 DRAM Preliminary PowerPc writes and checking parity on memory reads One parity bit is associated with each data byte and is accessed with it When a parity error is detected during CPU to memory reads the error is reported by means of or When parity error is detected during PCI to memory reads the error is reported by means of PCI SERRZ The 660 detects all single bit parity errors but may not detect multi bit parity errors Also an even number of parity errors will not be detected For example an event which causes a parity error in bytes O 1 2 3 4 and 5 will not be detected 4 4 1 1 ECC Overview While ECC is enabled the 660 uses the ECC logic to detect and correct errors in the trans mission and storage of system memory data The bridge implements the ECC protocol us ing the same connectivity and memory devices as parity checking While neither parity or ECC is enabled the bridge executes memory writes of less than eight bytes in response to busmaster requests to write less than eight bytes of data The bridge always whether parity ECC or neither is enabled reads data from memory in 8 byte groups even if the busmaster is requesting less than eight bytes While parity is enabled the bridge also executes memory writes of less than eight bytes in response to busmaster requests to write less than eight
123. of the 663 and 664 are intended for use by the IBM manufacturing process only The inclusion of the following information in this section is the total extent to which IBM supports the use of these pins by external customers 8 4 2 1 LSSD Test Mode Tie the TEST input of both the 663 and the 664 high during normal operation Do not allow these signals to be casually asserted Caution is advised in the use of LSSD test mode LSSD test mode is enabled on the 663 asynchronously by asserting TEST to the 663 In the same way LSSD test mode is enabled on the 664 asynchronously by asserting TEST to the 664 In LSSD test mode the 663 and 664 pins shown in Table 8 6 are rede fined to become LSSD test mode pins These pins have LSSD functions only while the 663 or 664 is in LSSD test mode Otherwise the pins perform normally IBM uses LSSD test mode to verify the logical operation of the 663 and the 664 Table 8 6 LSSD Test Mode Pin Definitions Test Pin Name 664 Pin 664 Pin Normal Name 663 Pin 663 Pin Normal Name TEST MEM ERR ECC LE SEL TEST XATS DUAL_CTRL_REF TEST_CCLK DPE MEM_BE 2 SCAN_IN CPU_PAR_ERR MEM_DATA_OE SCAN_OUT ROM_OE CPU_PAR_ERR RI NMI REQ MEM BE 0 STOP CLK MEM 1 In LSSD test mode never assert more than one of TEST ACLKzZ TEST TEST_CCLK and RESET at the same time as this may damage the device by provok ing excessive internal c
124. peak burst write rate of 32 bytes in 12 PCI clocks or about 85MBps with a 33MHz PCI clock This scenario holds while the RAS timer 10us typical does not time out the burst remains within the same 4K memory page and no refresh is requested 15us typ 5 2 7 1 Detailed Write Burst Sequence Timing The detailed write sequence is affected by several factors such as refresh requests memory arbitration delays page and or bank misses and cache boundary alignment Table 5 5 shows the details of the various sequences that a PCI to memory burst write will experience depending on the address relative to a cache block boundary of the first data phase of the transaction The starting address of the numbering sequence shown on the top row was arbitrarily chosen as 00 and could be any 32 byte aligned boundary times shown in Table 5 5 are in PCI clock cycles and do not include any cycles that the PCI 5 6 G5220297 00 PowerPc Preliminary Section 5 PCI Bus master spends acquiring the PCI bus from the PCI bus arbiter The initial data phase is timed from the assertion of FRAME to the PCI clock at which the PCI master samples TRDY active Subsequent data phase times are from the PCI clock at which the previous TRDY was sampled active to the PCI clock at which the current TRDY is sampled active All the numbers shown in Table 5 5 are for parity or none operation The numbers are also correct for ECC mode operation as long as all th
125. perform various operations in response to a detected error condition but it does not automatically perform further actions just because it asserts PCI SERR The 660 does not monitor PCI SERRZ as driven by other PCI agents PCI_SERR is not an input to the 660 8 2 8 4 Error Reporting With PCI PERR Z The 660 asserts PCI PERR5t for one PCI clock to report PCI bus data parity errors that occur while the 660 is receiving data during PCI to memory writes and CPU to PCI reads The 660 asserts PCI in conformance to the PCI specification 8 2 9 Error Status Registers Error status registers in the 660 may be read to determine the types of outstanding errors Errors are not accumulated while an error is outstanding however there will be one or MCP for each error that occurs For example if an illegal transfer error causes a TEA a memory parity error can occur while the CPU is processing the code that handles the The second error can occur before the error status registers are read If so then the second error status is not registered but the from the memory parity error is as serted 8 2 10 Error Related Bridge Control Registers Information on these registers is contained in the 660 Bridge Manual B dgeConroRegster RW System Control 81C 1 Memory Parity Error Status L2 Error Status L2 Parity Error Read and Clear Unsupported Transfer Type Error System Error Address PCI Command
126. precise external interrupt exception branching to either 500h or FFFO 0500h depend ing upon the Exception Prefix EP bit in the MSR The MSR EE bit is automatically set to O at this time 4 The code at the vector location requests single byte read of memory address BFFF FFFOh 5 Inresponse to the read the 660 arbitrates for the PCI bus and then generates an inter rupt acknowledge transaction on the PCI bus 6 The ISA bridge decodes and claims the PCI interrupt acknowledge transaction and returns the 8 bit vector which has been preprogrammed for the active interrupt and then negates the interrupt output 7 The 660 accepts the interrupt vector on the PCI bus returns it to the CPU and signals to terminate the CPU transfer normally Since the CPU does not require that the interrupt signal INT CPU be deactivated be tween interrupts another interrupt is allowed to occur as soon as software sets the MSR EE bit back to 1 For this reason software should enable interrupts as soon as pos sible after receiving the vector Note that the load instruction that fetches the interrupt vector is subject to out of order execution eieio as required After servicing the interrupt execute a return from interrupt RFI instruction to return to the program that was interrupted For more information on interrupts see the Exceptions section of the 603 User s Manual Note that other PCI busmasters can initiate interrupt acknowledge tran
127. reads an unpopulated location the bridge returns all ones and com pletes the transfer normally e When the CPU writes to an unpopulated location the bridge signals normal transfer completion to the CPU but does not write the data to memory The memory select error bit in the error status 1 register index C1h is set in both cases Gaps are not allowed in the DRAM memory space but empty size 0 memory banks are allowed While the Memory Select Error bit 21 a read or write to an unpopulated memory location is reported to the initiator as an error 4 3 1 6 Memory Bank Addressing Mode BCRs Index A4 to A7 Read Write Reset to 44h each BCR This array of four 8 bit read write BCRs defines the format of the row and column addres sing of each DRAM memory bank 07 pe ps p ps o Reserved Even Bank Addressing Mode 00x reserved 010 212x10 11x10 10x10 11x11 011 12 11 12x12 1xx reserved Reserved Odd Bank Addressing Mode 00 reserved Mode 2 010 12x10 11x10 10x10 11x11 Mode 3 011 12 11 12x12 1xx reserved Memory Bank Memory Bank 23 L 6 4 18 G5220297 00 PowerPc Preliminary Section 4 DRAM 4 3 1 7 Memory Bank Starting Address BCRs Index 80 to 87h Read Write Reset to 00h each BCR This array of eight BCRs along with the eight extended starting address registers contains the starting address for each memory bank Each pair of registers maps to the
128. shows the device and pin number in device pin format The right column shows whether the signal is an input or output of the device An I indicates that the signal is an input to the device An O indicates that the signal is an output from that device A pu indicates that the resistor to which the signal is connected is a 10k pullup resistor AACK connects to R1 pin A02 which is a 10k pullup resistor AACK also connects to U1 pin 28 and U2 pin 109 both of which are l Os 2 1 Pin Descriptions The following sections contain information about the connectivity and function of the MCM pins See the 660 User s Manual 660 UM the 603e User s Manual 603e UM and the SRAM Tag and buffer data sheets for more information Note that the I O pins make a connection to every net the This was only done to aid in the manufacturing test of the Of the 1089 I O pins that the pro vides only 296 signals are needed by the user to interface with the MCM These signals are listed in Table 2 2 G5220297 00 2 1 Section 2 Signals Preliminary PowerPc Table 2 2 User Supplied Signals Hye foa PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI p en Ro Per eG reso eor eor 2214 5
129. stored in little endian LE order when it is stored with the order of bytes reversed from that of BE order In other words the most significant byte is stored at the highest num bered address The endian ordering of data never extends past an 8 byte group of storage The 100 MHz PPC 603e normally operates with big endian BE byte significance which is the native mode of the PowerPC 603e CPU Internally the CPU always operates with big endian addresses data and instructions which is ideal for operating systems such as AIX which store data in memory and on media in big endian byte significance In BE mode neither the CPU nor the 660 Bridge perform address or data byte lane manipulations that are due to the endian mode Addresses and data pass straight through the CPU bus interface and the 660 The CPU also features a mode of operation designed to efficiently process code and oper ating systems such as WindowsNT which store data in memory and on media in LE byte significance The MCM also supports this mode of operation When the is in little endian mode data is stored in memory with LE ordering The 660 has hardware to select the proper bytes in the memory and on the PCI bus via address transforms and to steer the data to the correct CPU data lane via a data byte lane swap per Also see the 603e CPU and 660 Bridge User s Manuals Table 11 1 summarizes the operation of the MCM in the two different modes Ta
130. the PowerPC 603e RISC microprocessor The IBM27 82660 Bridge chip set 660 Bridge or 660 interfaces the CPU to the PCI bus and DRAM memory and provides L2 cache control The tagRAM and 512K SRAM components are also included on the The also includes a master clock generator For a list of the specific dice pack aged within the MCM see Table 1 1 Table 1 1 MCM Dice mT o Clock Driver MPC970 Motorola Tag RAM IDT1216 Integrated Device Technology SCBS143F Texas Instruments ill 5220297 00 PowerPc Preliminary Section 1 Introduction 1 21 CPU uses a PowerPC 603e PID6 603e at CPU bus speeds up to 66MHz See the PowerPC 603e Technical Summary Users Manual and Hardware Specifications for more information The MCM Runs at 3 2 CPU core CPU bus speed ratio up to 99 66 MHz Consult your IBM representative for available choices of CPU and operating frequency Supports one level of address bus pipelining Most data writes are posted Reports precise exceptions via TEA and reports imprecise exceptions via MCP Operates the 603e in 64 bit data bus mode Supports bi endian operation Supplies an ESP connector for RISCWatch debugging and monitor systems Runs in DRTRY mode 1 2 2 L2 Cache The contains a complete L2 The controller is located inside the 660 Bridge The L2 Uses
131. the address pins and transfer size TSIZ pins in either BE or LE mode In LE mode the CPU shifts the data from the byte lanes pointed to by the unmunged address over to the byte lanes pointed to by the munged ad dress This shift is linear in that it does not rotate or alter the order of the bytes which are now in the proper set of byte lanes Note that the individual bytes are still in BE order 11 2 What the 660 Bridge Does While the MCM is operating properly data is stored in system memory in the same endian mode as the mode in which the CPU operates That is the byte significance in memory is BE in BE mode and it is LE in LE mode Because of this hardware is included in the 660 that in LE mode will swap the data bytes to the correct byte lanes and that will transform or un munge the address coming from the 603e 11 2 1 The 660 Bridge Address Unmunge In LE mode the 660 unmunges address lines A 29 31 This unmunge merely applies the same XOR transformation to the three low order address lines as did the CPU This effec tively reverses the effect of the munge that occurs within the CPU For example if the CPU executes a one byte load coded to access byte 0 of memory in LE mode it will munge its internal address and emit address A 29 31 7h The 660 will then unmunge the 7 on A 29 31 back to 0 and use this address to access memory 11 2 2 The 660 Bridge Data Swapper The 660 contains a byte swapper As shown in Figure 11
132. the flag write completes e Ifthe flag write is a PCI IO write then the 660 will not post the flag write which forces the data set write s to complete on the PCI bus before the flag write is initiated on the PCI bus 5 5 2 4 Solution 3 Change the data set write procedure Design the device drivers such that the Consumer receives data set some way other than as a PCI memory target such as an as an I O target a PCI busmaster e While the Consumer is receiving the data set as a PCI IO target the 660 does not post the IO writes and so each write completes in order even if some are retried This technique forces the data set writes to complete before the flag write completes e f the Consumer is receiving the data set by initiating PCI to memory reads and is receiving the flag by initiating a PCI to memory read then as long as the CPU 5 14 G5220297 00 PowerPc Preliminary Section 5 PCI Bus initiates the data set writes to memory before the CPU initiates the flag write to memory then the ordering of the transactions will be preserved 5 6 Related Bridge Control Registers Information on these registers is contained in the 660 Bridge Manual Bridge Control Register mde PCI Type 0 Configuration Addresses 8080 08xx R W 4 IBM27 82650 Compatible thru 80 0 00xx 2 R Pocoma RW 2 PCI Device Status R W Revi
133. use in implantation or other direct life support ap plications where malfunction may result in physical harm or injury to persons INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION AS IS WITHOUT WARRANTIES OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRAN TIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE SOME STATES DO NOT ALLOW DISCLAIMERS OF EXPRESS OR IMPLIED WARRANTIES IN CERTAIN TRANSACTIONS THEREFORE THIS STATEMENT MAY NOT APPLY TO YOU Contacts IBM Microelectronics Division 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6531 Tel 800 PowerPC http www chips ibm com http www ibm com ftp ftp austin ibm com pub PPC_support Dale Elson Applications Engineer IBM PowerPC Embedded Processor Solutions elson austin ibm com ESD Warning The planar and MCM contain CMOS devices which are very susceptible to ElectroStatic Discharge ESD DO NOT remove them from the antistatic bags until you have connected yourself to an acceptable ESD grounding strap Work in a static free environment and be sure any person or equipment coming into contact with the cards do not have a static charge The cards are particularly susceptible until they are placed in a properly designed enclosure Bench work should be done by persons connected to ESD grounding straps G5220297 00 Pewer Preliminary IBM 100 MHz PPC 603e MCM AGREEMENT BEFORE READING THE REST OF THE D
134. 0 Firmware Preliminary Power 10 4 3 3 Reprogram Flash Memory The PowerPC 603 604 reference board stores its system firmware in a reprogrammable flash memory on the system board The reprogram flash memory option on the main menu allows the reprogramming of the flash device with a DOS formatted diskette This allows future revisions of the system firmware to be provided on diskette without the need for re moval of the device from the board If done improperly reprogramming the flash memory can cause the system to become un usable until external means are available to reprogram the device Use this option with care All boot devices specified in the Boot Devices Menu will be searched in order for FAT and CD ROM file systems and the first matching file on a boot device will be loaded The Reprogram the Flash Memory screen is shown in Figure 10 15 To reprogram the flash enter the file name in the Specify Image Filename field and select the Reprogram the Memory option PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp 11 Rights Reserved Reprogram Flash Memory Image Filename Reprogram the Memory Go to Previous Menu Press to select item Enter data at cursor Figure 10 15 Reprogram the Flash Memory Screen 10 16 G5220297 00 PowerPc Preliminary Section 10 Firmware 10 4 3 4 Exit Options The two exit options at the bottom of the main menu leave the system confi
135. 0 03 40 48 6036 PCI AD17 J1 C02 U2 29 03 41 44 2500 i PCI AD18 J1 B03 U2 28 U3 42 47 5000 i PCI AD19 J1 C04 U2 25 03 43 50 6036 i PCI AD20 J1 A03 U2 24 03 44 49 4571 PCI AD21 J1 A04 U2 23 U3 45 46 8536 i PCI AD22 J1 B05 U2 22 U3 46 51 0000 i PCI AD23 J1 A05 U2 21 U3 47 41 3536 i PCI AD24 J1 A06 U2 20 U3 48 44 2071 i PCI AD25 J1 B07 U2 19 U3 49 47 6036 i PCI AD26 J1 A07 U2 18 03 50 47 6036 PCI AD27 J1 A08 U2 15 03 51 46 4571 PCI AD28 J1 B09 U2 14 03 62 43 7500 i PCI AD29 J1 A09 U2 13 03 63 47 5000 PCI 0 J1 A10 U2 12 03 64 42 2071 i PCI AD31 J1 C10 U2 11 03 65 73 5000 i PCI IRDYs J1 AB01 U2 201 03 167 49 1036 i PCI J1 AE02 U2 53 72 6036 i PCI J1 U01 U2 10 52 8536 i PCI SERR J1 U02 U2 71 56 1036 i PCI 5 J1 AA01 U2 203 64 9571 i PCI J1 AC02 U2 202 44 3536 i PCI_AD_OE J1 N14 U2 195 46 1036 i PCI C BEO J1 V01 U2 6 53 6036 i PCI C BE1 2 J1 W02 U2 5 48 2071 i PCI 2 J1 W01 U2 4 49 2500 i PCI_C BE3 J1 Y01 U2 3 12 5000 i PCI CLK IN J1 K29 U2 123 i PCI DEVSEL 2 J1 AA02 U2 204 12 4 G5220297 00 Y nd Power Preliminary Section 12 Electromechanical Table 12 1 MCM Primary Continued 41 6036 pci PCI EXT SEL J1 U14 U2 67 U3 153 62 2071 pci PCI OL OPEN J1 W14 U2 64 U3 165 50 2071 pci PCI OUT SEL J1 R14 U2 68 U3 169
136. 0 usec has elapsed since starting the refresh timer so that sufficient refresh cycles have occurred to properly start the memory This will be hidden if G5220297 00 9 1 Section 9 Setup Preliminary PowerPc approximately 120 Flash accesses occur after the timer is started and before the memory initialization starts 5 Initialize all of memory so that all parity bits are properly set The CPU may cache unnecessary data hence all of memory must be initialized The 660 does not re quire reconfiguration when port 4Dh in the ISA bridge is utilized to reset the native I O and the ISA slots 6 Read the L2 cache presence detect bits and set register xx for 512K of synchro nous SRAM cache 9 3 PCI Configuration Scan The 660 bridge in the MCM enables the software to implement a scan to determine the complement of PCI devices present This is because the system returns all ones rather than an error when no PCI device responds to initialization cycles The software may read each possible PCI device ID to determine devices present Table 9 1 Configuration Address Assignments IDSEL Line 60X Address PCI Address ISA bus bridge SIO A D 11 8080 08XXh 080 08XX PCI Slot 1 A D 12 8080 10XXh 080 10XX PCI Slot 2 A D 13 8080 20XXh 080 20XX PCI Slot 3 A D 14 8080 40XXh 080 40XX Note This address is independent of contiguous mode Software must use only the addresses specified Using any addresses that causes more than one IDSEL to be
137. 0000 0 0101010101 21 Q1 OY AAA AAA AAA AAA Lb bc bo bo bo bo bo bo bc bo SSS EA EH EHE EA HH Qu M 88 mm 003000 0 NE SELDLLDIDIDLDLOLOLOLO ID OLO be b bo bo bo bo bo bc bo bc AMT NUS OT O O1 SI COO S lg T HHHHHHHHHHHHHHHH 5555555555555555 PD ee ee De ee ae ILI IER ELLE 522555555555555555555555555555555 ZEL Scored nd3 EEGIOU hnd3 5 9 9 E cUIUU WIW ZCULIUU CULO SEL WIW Seolod nd3 55555555555522252555555555555555555 HHHHGHHHHHHHHHHHHHHHHHHHHHHHHHHHHH Dom tu li bc lo Lo bc bc bo bc 1 fucum HO COO NON DOS 040 Im q gt NY OOM One IDIDUDUDULD LO br a foen tarha fan ar E g o
138. 01 1 4 E 1000 0111 0 E PPPP 010 6 E 110 2 5 E 1100 0011 0 E PPPP 011 7 E 111 3 6 E 1110 0001 1 E PPPP 100 0 000 4 7 1111 0000 1 0000 NNN 1 E NNN N N NNNN NNNN 1 E NNNN NNN 3 E NNN N N NNNN NNNN 1 E NNNN o 0 oO uo A WI dD Jj oj oO eB Ww DM Notes N not emitted by 60X because it crosses 8 bytes transformed into 2 bus cycles P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603e bus in LE mode G5220297 00 11 13 Li Li Section 11 Endian Preliminary PowerPc Table 11 12 contains the same information as found in Table 11 11 but it is arranged to show the CAS and PCI byte enables that activate as a function of the address presented at the pins of the 603e and as a function of BE LE mode Rearranging Table 11 12 for 4 byte transfers Table 11 12 Rearranged Four Byte Transfer Information 4 BYTE XFERS BE BE LE LE 60X ADDRESS PINS 5 0 7 PCI 5 0 7 0 7 2 3210 0 7 AD2 3210 0000 1111 0000 1111 0000 0000 1000 0111 0 E NNNN 1100 0011 PPPP E NNNN NNNN 0 E NNNN 1110 0001 PPPP E NNNN NNNN E NNNN o o o o eje Flo NNNN E 1000 0111 1 E PPPP NNNN E 1100 0011 1 E PPPP NNNN E 1110 0001 1 E PPPP 101 NNNN NNNN 110 NNNN NNNN 111 NNNN NNNN oy Or B Ww 0 0 0 100 1111 0000 1 0000 0000 1111 1 0000 1 1 1 Notes N not emitted by 60X because it crosses 8 b
139. 025 154pf 50pf 16ns CAS 13 3 5 025 154pf 50pf 16ns MA to buffer 13 6ns 025 30pf 50pf 13ns to memory 4 6ns 007 684pf 50pf 9ns 663 memory data input setup 6ns 664 Output timings are at 50pf For loads greater than 50pf 0 025ns pf are added Timing Requirements and register value calculations 1 4CLK 15ns gt 50ns 60ns gt SONS MTR1 1 0 10 2 5 CLK 15ns 70 5ns SONS gt PONS fors Ceo ics MTR1 4 2 100 G5220297 00 4 7 Section 4 DRAM Preliminary PowerPc 3 1CLK 15ns 10ns TONS TONS esa MTR2 6 5 00 4 15ns 16 5 20ns 6ns 45ns gt 42ns MTR2 3 2 10 5 1 CLK 15ns gt Ons 13ns 9ns 16ns 15ns gt 6ns b 1 3 CLK 15ns gt 13ns 9ns 35ns 6ns 60ns gt 63ns MTR2 7 0 see Note 2 6 3 3 CLK 15ns gt 16ns 70ns 6ns 90ns gt 92ns MTR2 1 0 10 see Note 2 7 2CLK 15ns 10 4ns 13ns 16ns SONS gt NS MTR1 5 1 Results Memory Timing Register 1 index Ath 32h Memory Timing Register 2 index A2h Note 2 The timing analysis above includes two timing violations path 56 is violated by 596 and path 6 is violated by 296 More conservate system designers may wish to use the values MTR1 32h MTR2 0Eh to ensure all timing requirements are met under all worst case conditions 8 Refresh rate 15 6us 30ns 520d 208h Refresh Timer Divisor in
140. 0K ohms to 20K ohms Pull down resistors should be 500 ohms to 2K ohms In Table 8 5 603 e refers to either a 603 or a 603e Table 8 5 Configuration Strapping Options Function Pull Up Down Location of ROM Up Remote ROM Down Direct Attach ROM CRS_C2PWXS 603 e in 1 1 or 3 2 Down 603 e not in 1 1 or 3 2 mode or 601 or 604 Up 603 e in 1 1 MWS P2MRXS CPU mode 3 2 CPU core bus mode 8 3 2 3 660 Deterministic Operation Lockstep Applications If fully deterministic operation of the chipset following RESET is required then the following items must be considered e When RESET is deasserted some outputs transition to a different but stable state This results in requirement 3 in Section 8 3 2 that neither CPU or PCI bus activity is allowed to begin during the first four CPU clocks after the deassertion of RESET e When is deasserted the refresh counter begins and continues to run counting the interval between refresh cycles to the memory There are two ways to start the refresh timer deterministically Meet the following timing requirements for RESET so that the clock cycle upon which RESET is deasserted is known Setup 4 2ns relative to a rising PCI clock edge Hold gt Ons relative to a rising PCI clock edge Write to the Refresh Timer Divisor Register index D1 DO and the Suspend Refresh Timer Register index D3 D2 to reset the refresh counters If this is
141. 0OUOOUOUOU IS QUO NC LOUP 0 Oana ZUOUOUOUU 3HIM G3HIMNO S 30 S 40 S 40 E 50 m 8 a Sayd 3HIM Sayd 3HIM B66T SE pS 20 41 031 41004 1597 4067 13395 57411 NUHNISO3 SNIMUHU H3BADN NOISI 3 S667 1HDIUAdOD SHOU gt pae 02581 lt ozatt lt S120 28248 2 oD wos _ Ju wanan ssn ssn 224 yu 158 21 ON 123130 3ONd3S3 Hd 1 eg 59 E S RE 2009 Wei S C21 310 3999 SS3HdA2 O4 LIM Q3AILL 4T35 ONY eva 3 540119201 1 Sand HLIM SLINDOSONDIW NO 2089 11420504214 UHIX3 Wed 211915 Aged SFI HLIM NoTSuan 3808 2019 608 118 87 x BONG org AHO 310 3898 119 X857 49846 Mad rTeTrangI 5199 1D m ng Zoo 55 5 4085 X3M HUHS cac TIdo
142. 1 PIRQ2 Figure 8 3 PCI Interrupt Connections EI __ 1 8 1 7 Scatter Gather Interrupts Where possible set up the scatter gather function to use the ISA bridge end of process EOP output indicator for the termination of ISA bus DMA in which scatter gather is employed The planar is initially configured to use this scheme The EOP signal from the ISA bridge is used as the terminal count ISA TO signal on the ISA bus 8 4 G5220297 00 PowerPc Preliminary Section 8 Exceptions 8 2 Errors Errors are handled primarily by the 660 the CPU and the firmware The errors are reported to the CPU or the PCI and status information is saved in the 660 register set so that error type determination can be done by the CPU There are two methods which the MCM 660 uses to report errors to the CPU the method and the method Errors related to a PCI bus transaction are reported to the PCI by means of the PCI or the PCI_SERR signals Errors that are detected while the CPU is running a cycle that can be terminated immediate ly are reported using Errors reported in this way are a direct result of the CPU transfer that is currently in progress For example when the 660 detects a transfer size error it ter minates the CPU transfer with TEA instead of with Errors that are detected while a CPU transfer is not in progress and errors that occur be cause of a CPU transfer but which are de
143. 154 A R1 B03 U2 129 E x K1 VSS NC VSS NC K20 VDD1 K21 DBDIS K VSS NC A a A ala OF wji Nj N N _________ _________ Pe _________ E CLK_MPC601_CLKS jU440 VDD1 PCI IN VS MATCH VDD1 2 PCI AD6 PCI AD7 NC DEPOP 24 04 40 02 123 42 A R1 A04 U1 153 U2 172 U2 40 U3 12 U2 39 U3 13 U7 22 U8 22 U9 22 U10 22 U6B 41B R1 K05 U1 197 U2 145 R1 B02 U1 149 U2 143 U2 142mU5 50 ojo NC DEPOP TSIZO r NC DEPOP NC DEPOP Section 2 Signals Net Name MCM Nodes L10 6 1 02 01 237 un L12 ECC LE SEL U2 2 U3 149 E L14 MEM DATA 02 196 03 145 E L16 TBEN 60 1 01 01 234 L7 L1 R1 F01 U1 203 E L20 un 122 DIR245B U6B 1B U6B 24B 23 L24 WT DTY IN R1 G04 U5 5 U5 6 Le TAG ADDR IS 0533 27 TAG VLD L 01 PCLADS U24103 1 DAYI 04 05 TT U10 21 U6B 40B VSS r 5 5 5 S Co Go Go 5 N N S 6 8 e 8 Wis 20 21 22 SERE Preliminary 2 18 PowerPc MCM Nodes N N N ony RY VDD3 M27 TAG_DATA_11 N 6 N N 2 30 VDD3 TAG PWRDN
144. 17 U2 133 E U2 115 U5 80 2 U2 116 U5 70 U1 178 U2 74 U5 35 U1 11 U2 85 U5 61 C27 U1 16 U2 96 U5 16 U6B 14B C29 C30 U1 151U2 105 U6B 2B 2 03 111 IGN PCI ADS 1 U2 57 02 3 DAISY16 004 U1 108 U3 186 U7 41 ADO7 U1 92 U3 207 U7 13 A VSS 009 U1 84 U3 221 U8 35 gt N N N gt gt gt io E 1 gt gt gt o gio EE 5220297 00 PowerPc MCM Nodes U1 76 U3 2 U8 45 AD1 VDD2 AD1 D23 AD1 VSS AD1 D29 AD1 VDD2 AD1 D35 AD1 VSS AD1 D41 AD1 VSS AD1 D47 AD20 VDD2 D53 01 68 03 31 08 15 01 139 03 57 09 39 01 129 03 79 09 9 01 118 03 94 09 19 01 101 03 107 010 41 01 57 03 126 010 13 01 2 02 73 07 5 08 5 09 5 010 5 02 179 03 109 04 16 U2 53 U1 109 U3 185 U7 40 U1 93 U3 199 U7 12 U1 85 U3 220 U8 34 U1 78 U3 1 U8 44 U1 71 U3 27 U8 14 U1 140 U3 56 U9 38 U1 130 U3 78 U9 8 U1 119 U3 89 U9 18 U1 102 U3 106 U10 40 2 23 VSS D59 AD2 AD2 AD24 VDD2 VSS NC VDD2 SRAM_CS AD2 AD2 AD29 A24 VSS 9 VDD2 MD49 USER PCICLK1 PCI LOCK amp NC DEPOP AD32 gt AE01 AE02 03 E gt ITI NC DEPOP D10 NC DEPOP D16 NC DEPOP D22 AE1 NC DEPOP AE1 D28 AE13
145. 2 12d 99 X TISAI Td 895 199 p lt gt 09 lod dO1S E09 CAdHI 12d TECH I2d NOI IDJ NOI TXDOT I2d X320 1 E28 XAGHI lod AUHl I2d O3H ILN OUHHUSI HOHJ IHN gon XrSS8 3HUHJ Idd TIWA 12d OSH INI X 15 I2d 555555555555555555555555555555555555555555555 940 ION LNOD B667 TE tS 28 741 031 41004 1597 50 13395 A36SAd0 31111 Sc 97 En NINE 857 Ayd Nd NOILUMOdHOO WEI 5 Breda nds 68 11 40I 5661 LHOTYAdOD rval nd NOISIO 3HGZIS T fauda na gt H344nH r99 Godd 165 2 9 TSOLGd hd2 lt O 25 UA gt 6561 259188 5 Ssored nd3 SoLo Nd 96 E9 04 25123H2 HH ESELGU ns3 TSOLUd fd2 QUIUO W3A4 59 9 5 9 COLIC H3 SroloOd ZvOlOU nd3 Srored nd3 SpalGd nd3 Nd 55 c m ELLELLLLLLLL LLLELLLLLLLLLLLLLLLLLI 05905660415 cre AAA A AAA nm mmm NON 00000000 9 0 09
146. 2K up to 4G Other size devices can also be implemented this way The CPU read address need not be aligned on an 8 byte boundary A CPU read from any ROM address of any length that does not cross 8 byte boundary returns all eight bytes of that double word from the ROM For example the operations shown in Table 6 1 could have been caused by a CPU memory read to FF80 0100h FF80 0101h or FF80 0105h 6 1 1 3 Endian Mode Considerations In little endian mode the address munging done by the CPU has no effect because PCI AD 2 0 are forced to 000 during the address phase by the 660 at the beginning of the transaction However in little endian mode the byte swapper is enabled so the bytes of ROM data returned to the CPU are swapped as shown in the last column of Table 6 1 6 1 1 4 4 Byte Reads The 660 handles 4 byte ROM reads and all ROM reads of less than 8 bytes as if they were 8 byte reads All 8 bytes are gathered by the 660 and all 8 bytes are driven onto the CPU data bus 6 1 2 ROM Writes The 660 decodes a CPU store word instruction to CPU address FFFF FFFOh as a ROM write cycle Note that the 660 treats any access from FFEO 0000h to FFFF FFFE with 6 4 G5220297 00 PowerPc Preliminary Section 6 ROM CPU 31 0 as an access to FFFO The three low order bytes of the CPU data word are driven onto the ROM address lines and the high order byte is driven onto the ROM data lines For example a store word instruc
147. 52 8536 pci 664 PCI REQ J1 AF01 U2 58 55 5000 pci PCI FRAME 664 J1 ACO1 U2 200 42 2500 memory MAO J1 AL20 U2 190 20 2500 memory MA1 J1 AL22 U2 189 36 3536 memory MA2 J1 AL24 U2 188 36 0000 memory MA3 J1 AL26 U2 187 32 7500 memory 4 J1 AL28 U2 186 32 3536 memory 5 J1 AL30 U2 185 31 1036 memory MA6 J1 AK31 U2 184 28 6036 memory MA7 J1 AH31 U2 181 29 8536 memory MA8 J1 AF31 U2 180 25 6036 memory MA9 J1 AD31 U2 179 39 8536 memory MDO J1 AN03 U3 180 36 5000 memory MD1 J1 AM03 U3 182 45 7500 memory MD2 J1 AN04 U3 183 50 0000 memory MD3 J1 AN05 U3 184 54 5000 memory MD4 1 5 03 189 53 3536 MD5 J1 AN06 U3 190 53 2500 memory MD6 J1 ANO7 03 193 45 1036 MD7 1 7 03 194 39 5000 MD8 1 09 U3 200 38 7500 memory MD9 J1 AMO9 U3 201 22 5000 memory MA10 J1 AB31 U2 178 20 2500 memory MA11 J1 Y31 U2 177 35 0000 memory MDPO J1 ANO8 U3 141 43 2500 memory MDP1 J1 AN14 U3 122 48 6036 memory MDP2 J1 AN20 03 103 52 0000 J1 AN26 U3 82 58 2500 memory 4 J1 AL32 U3 37 65 5000 memory MDP5 J1 AE32 U3 234 61 0000 memory MDP6 J1 W32 U3 214 53 8536 memory MDP7 J1 N32 03 195 54 1036 MD10 J1 AN10 U3 202 45 3536 memory MD11 J1 AN11 03 203 41 2500 MD12 J1 AM11 U3 206 42 7500 memory MD13 J1 AN12 U3 211 43 1036 memory MD14 J1 AN13 U3 212 44 3536 memory MD15 J1 AM13 U3 213 46 2500 memory MD16 J1 AN15 U3 215 65 8536 memory MD17 J1 AM15 U3 222 45 6036 memory
148. 558 lt 2182 poL lt 182 lt lt 19 lt gt 182 EGET lt gt 182 lt 13345 B66T 20 1 3 41004 1597 TA35SAUOZH 1111 NUNISO3 ONMO NOISI 3B NOILIUHOdHOO WEI S667 LHOIHAdOO 2 lt 2 ryan 3287 TED gp JHOY Wd Br BS TS 25 ES 5 1 85 ug TS 29 ES 2208 2998 POA cane 29559 2049 2189 2119 gine ging 8198 91 38 Sy 99 DI 310 3498 SSJHdAO 804 SNOI LODO 1 14420504214 UHLIXd SS3HdA 5 S408 ION OQ c pu tm aM Prise S 40 T JLIAM GOGWIL 4735 ANY YaLNNOD 15958 HLIM 2IIUIS SIIONOHHONAS 118 87 X 3898 800 yada Tod cou EOC vod Sou 90d 20d 800 Sade 614420504214 NO AM23HIU StI 15 3HOH 118 87 X vVTBTFOWHI lt 2602 Ta2 T 82 09 7799 lt 98 aaae ea lt EDET INS ANN 182 lt ever Bade
149. 57 0 TAS ODN recs COO EX DE WSHS E 8 7257 43H 7357 3438 19 e s NO EX DH WSHS r gt 8 7 190 TLL XID TLL HO X108 79 c LX 2 WE DOL XN3 1 T Ig1x TLX prn 2d x ND esg 133 NOI lIUHOdHOO WEI NOTSIAY 5661 1 5 E09 lt TA DE OEZ amp 58 9733 5190 BOLT lt 999 9U1 x 2129 E2EC AN DE Sec lt 298 2255100 Ga EBET 30 Weis x lt lt gt 182 JV Wes Sec lt 288 r23 9255100 gt lt 909 EN DE WUOHS X 28322 5 8567 lt 198 Heus lt gt 95 lt 88 Ep23 999 5190 lt 999 en DE 985 x lt gt 29 lt 598 1 999 y asivd 159 TAH DE 945 x gt 827E gt SET EUE lt gt 18 280097509 Wes lt gt 29 r 8 1 23 999 9 BUBT 729 ON TOH7 WAS x E29 IWS 296 28 Sea gt lt 9 9 xag NH Dad x gt 82 OHS 206 lt 999 5 28 2292 TT xao cau lt p28 ge23 gt 198 lt XAS INI xX TH9 lt EgET 34 Wot lt gt 8222 828 2 Tgae 1 2097 lt gt lt gt 2de a
150. 6 02 20 90151534 WOLSND Y SI 269dW 0579 0518 da3srn 03588 SI A3SSAU SI dIHO WOW OL 1 8 NI 3SN SI WHY 981 3lJHd5SIGd 510 1530 NOUS STxv9 v JO 9sSc qaaiooadd SI HID c NOILONN4 Sod Ted I2d NOD 3 lt 135 1 099 ONY 19 3 40 3H02 LIM 3 H2 I IN OdHdMOd SI AdSSAUO 3H OIld S3 NOIS3 Se SSON SSON M20 Wea WY SINIOd 1531 ANY joUJHdlNI ANY LL 9190 Wed 981 799 11246 SNE IO OYLNOD 243 331 7997E389 2 NOI LHYOAd OHLINOO Y MA INI OD 799 SHD0 19 Q 5 L 21 9 gt 5 O SOT 4 SS350d SN O SS350d Sn O SS490ud nggera 3 8 H3MO LS HHAAA
151. 60 does not set PCI locks but does honor them Also see Section 4 6 5 4 1 PCI Busmaster Locks The PCI signal is an input only to the 660 The 660 provides resource locking of one 32 byte cache sector block of system memory Once a PCI busmaster sets a lock on a 32 byte block of system memory the 660 saves the block address Subsequent accesses to that block from other PCI busmasters or from the CPU bus are retried until the lock is released The bridge generates a write with flush snoop cycle on the CPU bus when a PCI busmaster sets the PCI lock The write with flush snoop cycle causes the L1 and L2 caches to invali date the locked block which prevents cache hits on accesses to locked blocks If the L1 contains modified data as indicated by a CPU retry the PCI cycle is retried and the modi fied data is pushed out to memory 5 4 2 CPU Bus Locking The 660 does not set PCI locks when acting as the PCI busmaster The 60X processors do not have bus locking functions Instead they use the oad reserve and store conditional instructions Iwarx and stwcx to implement exclusive access by set ting a reservation on a memory block To work with the lwarx and stwcx instructions the 660 snoops all PCI accesses to system memory which allows the CPU that is holding the reservation to detect a violation of the reservation In addition the 660 generates a write with flush operation on the CPU bus in response to the PCI read that begins a PC
152. 60 waits until the CPU completes the current CPU access before allowing the PCI to memory read to proceed If the watchdog timer has timed out the memory controller will precharge the RAS lines and if the refresh timer has timed out the memory controller will do a refresh operation N min 5 This occurs when the memory controller is idle and no refresh or RAS timeout occurs and the access produces page hit typ 280r9 This occurs if the memory controller is in the middle beat 3 of 4 of serving a CPU burst transfer when the PCI burst starts and no refresh or RAS timeout occurs max 26 This occurs when CPU1 is just starting a burst transfer to memory followed by 2 starting a burst transfer to memory after which a refresh happens to be required M is a function of a 2 clock snoop delay and other delays caused by bridge overhead functions Whenever the memory access crosses a cache block boundary the Bridge broadcasts a snoop cycle on the CPU bus M typ 7 Unless a refresh or RAS timeout occurs typ 70 8 This occurs for a refresh or RAS timeout The memory controller running at its own speed requests up to 4 8 byte memory reads into 8 4 byte buffers in the 663 while the PCI target engine of the 660 is servicing the memory read transaction Under worst case conditions slow memory etc the memory controller just keeps up with the PCI bus and goes up Under better conditions the memo
153. 63 SBE amp U2 193 03 175 2 22 DIR245 UG6A 1A U6A 24A ves AE 01 10 0233 U3 16 pwsvm 04 U2 206 U3 161 VSS rp ojl CO lt Q Es ABICO N Q N SEEE N 8 L o I ves JE 5220297 00 PowerPc Net Name MCM Nodes 2 22 c gt E N I N gt I N H27 X_MCP_60X 02 138 X 664 CPU CLK U2 121 U2 37 U3 15 U2 208 U3 163 U2 49 U3 147 U2 197 U3 146 R1 E02 U1 233 U2 194 U3 171 5 128 c CO oO N Nj O 5 KR oO rm als _ G _ _ _ _ _ _ a a a Sa a a aS Say a ay oO c 29 J30 664_PCI_CLK U4 18 oo N G5220297 00 Preliminary 2 17 Section 2 Signals MCM Nodes U2 171 U2 170 U2 38 U3 14 NC DEPOP 3 33 4 0 PCI AD8 0 VDD1 DAISY20 S 0 664 MIO TEST 06 VDD1 5 VSS NC VDD1 NC VSS K1 NC K14 VDD1 Kis NC cic c J1 H03 lt ojo Oy RY 02
154. 660 WE 1 0 DRAM Write Enables WE 1 and WE 0 are the same MWE1 N33 U2 175 and are used to avoid the need for external buffers 2 1 5 L2 Table 2 7 L2 Signals Signal Name MCM Nodes ABUF 13 28 EN Buffered CPU A 13 28 for the SRAM SR DIR 245 A SRAM address buffer A Direction input Pull low for normal operation DIR 245 B SRAM address buffer B Direction input Pull low for normal operation 245 SRAM address buffer amp B Output Enable input Pull low for normal operation SRAM_ADS N22 U2 124 660 SRAM ADdress Strobe Enables latching of new address for the burst SRAM ADDRO SR 2 SRAM_ADSP _ AKOS_ SA 1 __ SRAMADSPY input Puran orromon _ SRAM_ALE U22 U2 119 660 SRAM Address Latch Enable This signal is always high when burst SRAMs are used This signal is not used on the MCM SRAM EN R22 U2 125 660 SRAM CouNT ENable Enables incrementing of burst address for the burst SR 52 SRAM SRAM CS 29 JW SRAM Chip Select to GND for normal operation SRAV_OEF 8850 Samou OOOO X SRAM OE U2 117 o 660 SRAM Output Enable output Connect to SRAM_OE for normal operation SRAM WE W22 02 114 660 SRAM Write Enable SR 3 4 TA GATES N24 U5 23 2 TAG TT1 TAH amp TAIN tied together and pulled high with 2 resistors Leave pulled 7 28 high for normal operation TAG ADDR 13 0553 1 TAG A13 Pull high for 256K
155. 66MHz and PCI bus speeds up to 33MHz The is initially configured with a CPU core CPU bus PCI bus frequency ratio of 99 66 33 MHz This accomplished by setting the configuration bits for the MPC970 clock driver via off pullups 3 1 CPU Busmasters The uses a single PowerPC 603e CPU and an internal L2 cache thus there are only two busmasters on the CPU bus the CPU and the 660 CPU bus arbitration is greatly sim plified and the multi processor capabilities of the 660 are not used The remaining arbitra tion on the CPU bus is between the CPU and the snoop broadcasting logic in the 660 Since the 660 parks the CPU bus on CPU1 the 603e whenever the bus is idle CPU latency is minimized One level of address bus pipelining is supported and most data writes are posted Precise exceptions are reported via TEA and imprecise exceptions are reported PIO or programmed transactions XATS type are not supported The is not currently specified for use with external CPU busmasters For more in formation on the CPU bus protocol see the 603e User s Manual For more information on the multiprocessor capabilities of the 660 see the 660 User s Manual For MCM applica tions involving external CPU bus agents please contact IBM PowerPC Embedded Proces sor Systems Application Engineering 3 1 1 603e CPU The MCM operates the 603e in 64 bit data bus mode The 660 will not operate 32 bit mode The
156. 7 8 T se Tox 97 47 4 4 Error Checking and Correction The 660 provides three levels of memory error checking no checking parity checking and error checking and correction ECC If no memory checking is enabled the system can be configured to use lower cost non parity DRAM While the system is configured for parity checking the 660 performs as follows e Uses odd parity checking e Detects all single bit errors e Allows full speed memory accesses While the system is configured for ECC the 660 performs as follows e Uses an H matrix and syndrome ECC protocol e Uses the same memory devices and connectivity as for parity checking e Detects and corrects all single bit errors Detects all two bit errors e The first beat of CPU to memory reads requires one additional CPU clock cycle e CPU to memory burst writes and 8 byte single beat writes are full speed e CPU memory single beat writes of less than eight bytes are implemented as read modify write RMW cycles e PCI to memory reads are full speed e PCI to memory writes are full speed while data can be gathered into 8 byte groups before being written to memory Single beat or ungatherable writes require a read modify write cycle XX 5 oy RR oO pm gt AINI O AU x 8M 32M 32M 64M 32 32 4 4 1 Memory Parity While the 660 memory controller is configured for memory parity checking the bridge im plements an
157. 82660 PowerPC to PCI Bridge User s Manual The terms 603e UM and 603e User s Manual refer to the BM PowerPC 603e RISC Microprocessor User s Manual Kilobytes megabytes and gigabytes are indicated by a single capital letter after the numeric value For exam ple 4K means 4 kilobytes 8M means 8 megabytes and 4G means 4 gigabytes The terms DIMM and SIMM are often used to mean DRAM module Hexadecimal values are identified where not clear from context with a lower case letter h at the end of the value Binary values are identified where not clear from context with a lower case letter b at the end of the value In identifying ranges of values from and to are used whenever possible The range statement from 0 to 2M means from and including zero up to but not including two megabytes The hexadecimal value for the range from 0 to 64K is 0000h to FFFFh The terms asserted and negated are used extensively The term asserted indicates that a signal is active logically true regardless of whether that level is represented by a high or low voltage The term negated means that a signal is not asserted The symbol at the end of a signal name indicates that the active state of the signal occurs with a low voltage level G5220297 00 xix Pewer
158. 99 es X L3S3H 0005 H3MOd GO oes zany HID ld x s Qc 20 13395 8661 80 75 20 1411 NOMWISO3 f Aew 1 031 41004 1591 SNIMUMG NOISIC3M NOILlUMOdHOO WEI gt 1H5IHAdOO OU JM dINI AHORA ONY dOHINOO 844408 799 222 ED Wd fido x eri LESS 99 7 4865 HUd 299 aaa usd fido IO T WON SHAH HH SOU Ul1UGd 74O bled HA 307007 Idd 735 LNO7 I2d 745 1X3 SxuiWcd SMW SxMdc2 Su 107 I2d 5 u Nao IBS G8 HSN 73573717223 37 38734 TEHA Z38 HIN E38 HIN _Ad 1 I2d A HI Idd 5 40 T e 1531 9 317 9 SE T0 TRON SHAH 54 509 SPIES ESET 222 222 222 6160 Ado X dO 3S 1DO 15 745 1 3 Sxeiwed SMH 5 582 Ge de dI 224 IO nd T lt 2E29 OEST uere 29 fido
159. AM BCLKs 0 DQ SRAM A 13 28 Address _ 9 ADSP SRAM_ADS 9 ADSC SRAM CNT ENZ 9 ADV _ 9 WE SRAM_OE 9 SRAM_CS 4 CS 7 Figure 3 6 Synchronous SRAM 512K L2 3 7 7 TagRAM The MCM uses an IDT71216 synchronous 16K x 15 cache tagRAM to implement the tags of the L2 Figure 3 7 shows the basic connectivity of the MCM SRAM The tagRAM is a synchronous device and so consumes one of the MPC970 clocks CPU address lines A 14 26 form the index of the directory entry Pull TAG ADDR 13 high for normal operation e CPU address lines A 2 13 form the tag of the directory entry Tie TAG DATA 11 to A13 for normal operation During tagRAM writes the valid bit associated with the index is set to match the TAG VALID input e During tagRAM reads the TAG MATCH outputis released to the active high open drain state only when A 2 13 matches the contents of tagRAM location A 14 26 and the Valid bit for that location is set to 1 If the the Valid bit is O invalid or the address stored in the tag does not match the current value of A 2 13 then the TAG MATCH output is driven low 16k x 15 X TAG BCLK TAG_CLEAR 9 TAG CLEAR TAG TAG WE A 14 26 A 12 0 2 13 TAG 11 0 TAG VALID VALID C
160. AM Calculations Ex 3 Same assumptions as above but with 50 5 DRAM 1 2CLK 15ns 30ns SONS gt 30 MTR1 1 0 200 2 4CLK 15ns 50 5ns BONS SONS acne wien MTR1 4 2 011 1CLK 15ns gt 10ns Toris gt TONS MTR2 6 5 00 4 2CLK 15ns 16ns 13ns 6ns 30ns gt 35NS MTR2 3 2 01 see note 4 5 1 CLK 15ns gt Ons 13ns 9ns 16ns 15ns gt 6ns b 1 2 CLK 15ns gt 13ns 9ns 25ns 6ns 45ns gt 58ns MTR2 7 0 see note 4 6 3 2 CLK 15ns gt 16ns 50ns 6ns 7905 gt 72 MTR2 1 0 10 7 2 15 5 gt 10ns 418 13ns 16ns SONS S eerte ss MTR1 5 1 Results Memory Timing Register 1 index Ath 2Ch Memory Timing Register 2 index A2h 06h Note 4 The timing analysis above includes two timing violations path 4 is violated by 14 and path 5b is violated by 15 More conservate system designers may wish to use the values MTR1 0Ch MTR2 09h to ensure all timing requirements are met under complete worst case conditions 8 Refresh rate 15 6us 30ns 520d 208h Refresh Timer Divisor index D1h DOh 0208h 9 RAS watchdog timer 10 000ns 15ns 8 83d 53h RAS watchdog timer register index B6h 53h default value 4 2 1 9 60ns EDO DRAM Calculations Ex 4 Same assumptions as above except using 60ns EDO DRAM 1 5220297 00 3CLK 15ns gt 40ns 45ns gt 40ns MTR1 1 0 201 Section 4 DRAM Prelimina
161. BET OVAT seach POLT OE2ET zv gt lt Elk lt TOPT ONT ar 0 EBE lt 5 55 lt BE 3159 gt gt gt lt EN WIDA lt 21 Tog gt gt gt 1 gt 1 gt 1 gt lt _ BOTI 295T NIS gurT Be 4148 o8urT lt BUT BT arre 21 __ 6209 lt BUT ST 8239 6239 v 8059 BorT lt gt EBT __ V BYT 2009 21 9039 OBUT 5 20 9 Saoo O 728 55 crs cere 12049 9239 cv were 2v __ 8139 przew cer arte 2 190 BANAAN gt B867 lt 1021 ET gt Sare sady Sen lt EDET OBIIT 8209 gt amp 8U T lt gt 921 PIAT
162. CLK_COM_FRZ J1 A18 29 6036 CLK_REF_SEL J1 B13 24 4571 CLK_TTL_CLK J1 A26 28 0000 CLK_VCO_SEL J1 A13 1 7500 663_CPU_CLK J1 G04 63 6036 664_CPU_CLK J1 G30 24 1036 CLK_BCLK_DIVO J1 C16 22 2500 CLK BCLK DIV1 J1 B17 26 3536 _ J1 F33 STROBE 14 8536 CLK_MPC601_ J1 K27 CLKS 25 3536 CLK_ J1 A16 MR TRISTATE 61 8536 664 PCI CLK J1 J30 20 6036 CLK_PCI_DIVO J1 B21 20 0607 CLK PCI DIV1 J1 C20 38 1036 USER PCICLK1 J1 AE01 29 5000 USER_PCICLK2 J1 NO1 42 8536 USER J1 C01 31 1036 USER PCICLKA J1 A11 25 4571 USER PCICLK5 J1 A14 29 7500 USER PCICLK6 J1 E33 Table 7 2 Clock Net Calculations Run Total Run Required Planar Run Tolerance Inch 3 5 nom 864 PCI CIKA In our experience a maximum clock trace length skew of two inches is acceptable It is the responsibility of the designer to determine the appropriate amount of allowed clock trace length variation for the individual application 5220297 00 7 3 Section 7 Clocks Preliminary PowerPc PCI Bus Clocks C PCI Clock MPC970 Consumer Solder Columns PCI Clock Consumer PCI Clock Consumer PCI Bus Clock CPU Clock Consumers PCI Clock Consumer X the total run including the trace length of the longest clock net Make all clock traces the same length Figure 7 2 MCM Clocks The allowed skew of the PC
163. CR This array of eight BCRs along with the eight extended starting address registers contains the ending address for each memory bank Each pair of registers maps to the correspond ing RAS decode For example RAS 4 corresponds to the BCRs at index 94h and 9Ch The eight least significant bits of the bank ending address are contained in the ending ad dress register and the most significant bits come from the corresponding extended ending address register The ending address of the bank is entered as the address of the next high G5220297 00 4 19 Section 4 DRAM Preliminary PowerPc est memory location minus 1 with the least significant 20 bits truncated Each bank must be located in the 0 to 1G address range These BCRs must be programmed in conjunction with the ending address and extended ending address registers See section 4 3 1 12 57 pe ps p 23 p2 n o A20 of end address 1MB A2 of end address 2MB A22 of end address 4MB A23 of end address 8 A24 of end address 16MB A25 of end address 32 A26 of end address 64 A27 of end address 128 4 3 1 10 Memory Bank Extended Ending Address BCR Reset to 00 each BCR This array of eight 8 bit read write registers along with the eight ending address registers contains the ending address for each memory bank These BCRs contain the most signifi cant address bits of the ending address of its bank Tos oo or A28
164. D1 05 ABUF19 alas lt 84 N 2 2 lt NC VDD1 NC DEPOP VSS NC DEPOP VDD1 NC DEPOP VDD1 NC DEPOP VSS T12 T13 T1 T1 T17 T1 T1 T20 Section 2 Signals MCM Nodes T21 NC DEPOP 23 26 U1 158 U2 103 U5 7 U6B 5B gt lt Of o U1 7 U2 83 U5 56 T26 VDD3 T27 18 U1 165 U2 93 U5 21 U6B 16B VSS XTAL2 VDD3 ROM_WE U4 13 w N oj U2 60 lt MD60 01 PCI PERR 02 PCI SERR NC DEPOP ABUF18 U3 133 U2 10 U2 71 E cic e 07 47 08 47 09 47 U10 47 U6B 33B e NC DEPOP ABUF28 c 07 26 08 26 09 26 U10 26 U6B 47B NC DEPOP 5 lt c NC DEPOP 10 5 E c R1 C03 U1 192 U2 144 c NC DEPOP c PCI EXT SEL VDD1 INT 60 VDD1 02 67 03 153 R1 D03 U1 188 C C N VDD1 ROM_LOAD NC DEPOP SRAM_ALE NC DEPOP ur U2 70 U3 160 02 119 BR G U1 174 U2 82 U5 55 NC DEPOP A17 U1 15 U2 92 U5 29 U6B 17B Uis U1 22 U2 102 U5 8 U6B 6B NC DEPOP XTAL1 4 12
165. D2 3210 0011 1111 0 1100 E 1001 1111 0 E 1001 1100 1111 0 0011 E 1110 0111 1 E PPPP 1111 0011 1 1100 E 1111 1001 1 E 1001 1111 1100 1 0011 E NNNN NNNN N E NNNN o nn o ejo o o o o T n 2 010 4 1 2 3 ui Ww N oj r N o A HG o o T 5 5 Notes N not emitted by 60X because it crosses 8 bytes transforms to 2 singles in BE machine CH in LE P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603e bus in LE mode Table 11 10 contains the same information as found in Table 11 9 but itis arranged to show the CAS and PCI byte enables that activate as a function of the address presented at the pins of the 603e and as a function of BE LE mode Table 11 10 Rearranged Two Byte Transfer Information 2 BYTE XFERS BE BE LE LE 60X ADDRESS PINS 5 0 7 PCI 5 0 7 2 3210 AD2 3210 1100 1111 1100 0011 1001 E NNNN 0011 1111 0011 PPPP 1111 1001 1100 1100 1111 1001 1110 0111 0011 0011 1111 NNNN 1001 1111E o o o o o 0011 1111 1001 1111 1100 1111 1110 0111 1111 0011 1111 1001 1111 1100 ojojo Ei 1100 N o Hn o 0011 u A olo jo Ei tg 1100 1001 m Fi Notes N not emitted by 60X
166. E13 E ETT Pak sox E E19 E E21 N N TRST R1 H04 U1 202 NC DEPOP S OIO N N AJ m m olo oj A m m gt Oo U2 66 U3 152 U2 30 U3 40 o ensam 02127 VSS or pwswz D08 N PCI_AD31 U2 11 U3 65 WO gio E o N e 5 5220297 00 2 15 Section 2 Signals MCM Nodes Eaz 25 Em paso 25 6 DAY E27 Em oas re E29 re R1 D04 U1 214 0 U2 33 U3 19 02 03 6 _______ 81 1 219 05 09157 U2 207 U3 162 BG 60 R1 B01 U1 27 VDD1 ITI mj mi mi mj m mi lo N EN nom m nj TI a 2 2 2 Oj NISJA wj N Unus Fa A ri ous 22 zs Ez Fa F25 TER F27 DAISY07 F28 F oase Sr onmo LAE 33 OLK ERZ STROBE 044 601 PCIAD11 U2 35 U3 17 G02 PCLADi2 U2 34 U3 18 TI Z TZ I oy BR T N J1 E28 m 2 16 PowerPc Net Name MCM Nodes 0 04 043 05 08 60 012602140 0 a olo oj l ABICO U2 192 U3 174 2 6
167. FRZ__ A18_ U46 7 MPO970 input Pul high or allow to fat for normal operation E PCI_CLK_IN USER_PCICLK1 USER_PCICLK2 USER_PCICLK3 USER_PCICLK4 otk SEL ms CLK FRZ STB CLK MR 3S A16 G5220297 00 Section 2 Signals Preliminary P2werPc Table 2 3 Clock Signals Continued Signal Name Nodes Description See 970 data sheet for more information CLK PCI DIVO MPC970 input Pull high or allow to float for normal operation CLK PCI DIV1 970 input Tie to GND for normal operation CLK PLL EN MPC970 input Pull high or allow to float for normal operation CLK REF SEL MPC970 input Pull high or allow to float for normal operation CLK TTL CLK MPC970 input Pull high or allow to float for normal operation CLK VCO SEL MPC970 input Tie to GND for normal operation FRZ CLK MPC970 input Can be connected to the ISA clock for use or pulled high FRZ DATA MPC970 input Pull down to GND for normal operation XTAL1 l O MPC970 crystal connection The following lists the names for the various nodes U1 603e 05 IDT Tag RAM U2 664 06 245 Buffer Chip 03 663 07 U10 SRAMs U4 MPC970 Clock Driver 2 1 2 CPU Bus Table 2 4 CPU Bus Signals A 0 31 VO 01 CPU address bus Represents the physical address of the current U2 transaction Is valid from the bus cycle in which TS is a
168. I CLK at any point in the system to the CPU CLK at the 660 Bridge is 2ns as shown in Figure 7 3 CPU CLK at 660 PCI CLK at 60X Figure 7 3 CPU CLK to PCI CLK Skew If the design rules laid out in Section 7 1 are followed the requirements are met G5220297 00 1 ii T PowerPc Preliminary Section 7 Clocks 7 2 Clock Freezing Some of the PCI clocks may not be required In this case the ability of the MPC970 to stop freeze the unused clocks is useful to reduce run time power consumption and EMI emis sions The MPC970 can freeze any set of output clocks in the low state while allowing the other clocks to continue running The freeze command is given to the MPC970 via a two wire synchronous serial interface that originates in the system EPLD See the clock freeze regis ter description in the System EPLD section for more information on activating this feature Firmware can read the presence detect bits of the PCI slots to determine which devices are present For PCI slots which are not populated firmware can disable the clocks for those slots This function can also be used by power management functions to further reduce power consumption of the motherboard by freezing the clocks of devices which have been placed in a power managed mode G5220297 00 7 5 Section 7 Clocks Preliminary PowerPc
169. I lock 5 12 G5220297 00 PowerPc Preliminary Section 5 PCI Bus 5 5 PCI 2 1 Compliance The contains a highly programmable system component the 660 bridge The 660 can be programmed to meet a wide range of application requirements Along with this flexi bility comes the ability to shoot oneself in the foot This section discusses ways to program the 660 to ensure compliance with the PCI 2 1 specification 5 5 1 PCI Target Initial Latency The 2 1 PCI specification allows host bridges a Target Initial Latency TIL of 32 PCI clocks under certain conditions When the 660 is in 2 1 CPU PCI clock mode and is used with one busmaster on the CPU bus the TIL is a maximum of 32 PCI clocks However when the 660 is used in 2 1 CPU PCI clock mode with two busmasters on the CPU bus itis possible to configure the 660 memory controller to operate the DRAM slowly enough that the TIL exceeds 32 PCI clocks Program the memory controller for the fastest settings that are consistent with good design practice 5 5 2 Transaction Ordering Rules Transaction ordering requirements were added to the PCI specification between revs 2 0 and 2 1 The PCI 2 1 specification states that writes from a given master must be visible by any other agent in the system as completing in the order in which they were initiated This requirement is intended to implement the Producer Consumer model contained in Appendix E of the PCI 2 1 specification 5 5 2 1 The P
170. L2 Connect to A13 for 512K L2 TAG A IN 04 SRAM buffer spare inputs Pull to GND Vdd for normal operation TAG CLR AC22 U2 116 660 Tag RAM clear When asserted all tags are forced to the invalid state See the 05 70 L2 Invalidate BCR TAG_CS1 TAG CS1 Pull this pin to GND for normal operation TAG CS2 5 TAG 52 Pull this pin high for normal operation TAG DATA 11 TAG 013 Connect to A13 for 256K L2 Pull high for 512K L2 TAG DTY TAG DTY S3 output Not used by MCM TAG_MATCH TAG match indication cache hit This signal is asserted for a cache hit It is an active high open drain output of the tag RAM Pullthis signal to 3 3v with a 200 ohm nominal resistor TAG PWRDN Power down mode control Pull this pin high for normal operation SFUNC TAG Status Bit Function Control input Pull to GND for normal operation TAG TAG output Not used by MCM TAG VALID AC20 U2 115 660 Tag valid bit The 660 asserts VALID to mark the current block valid in U5 80 the tag It is negated during tag writes in response to PCI write hits etc TAG VID 0554 TAGVIBIST output G5220297 00 2 9 Section 2 Signals Preliminary P2werPc Table 2 7 L2 Signals Continued Signal Name MEM Nodes Description TAG WE AA20 660 Tag RAM write enable Asserted to write to the Tag RAM TAG WT TAG WT S3 output Not used by MCM a
171. MD18 J1 AN16 U3 223 47 2500 memory MD19 J1 AN17 U3 224 45 7500 memory MD20 J1 AM17 U3 225 G5220297 00 12 5 Y d Section 12 Electromechanical Preliminary Power Table 12 1 MCM Primary Continued Net Topology 51 3536 memory J1 AN18 52 1036 memory J1 AN19 70 2500 memory J1 AM19 51 1036 memory J1 AN21 48 5000 memory J1 AM21 50 2500 memory J1 AN22 50 5000 memory J1 AN23 48 7500 memory J1 AM23 52 6036 memory J1 AN24 52 3536 memory J1 AN25 50 0000 memory J1 AM25 52 8536 memory J1 AN27 50 1036 memory J1 AM27 51 9571 memory J1 AN28 54 2500 memory J1 AN29 53 0000 memory J1 AM29 56 8536 memory J1 AN30 59 6036 memory J1 AN31 56 2500 memory J1 AM31 58 8536 memory J1 AL33 57 7500 memory J1 AK33 56 0000 memory J1 AJ32 56 3536 memory J1 AJ33 57 6036 memory J1 AH33 54 2500 memory J1 AG32 56 0000 memory J1 AG33 54 3536 memory J1 AF33 52 9571 memory J1 AE33 54 5000 memory J1 AD33 49 8536 memory J1 AC32 51 1036 memory J1 AC33 50 7500 memory J1 AB33 50 2500 memory J1 AA32 49 8536 memory J1 AA33 54 5000 memory J1 Y33 49 8536 memory J1 W33 49 8536 memory J1 V33 53 3536 memory J1 U32 60 7500 memory 1 033 45 5000 J1 T33 56 8536 memory J1 R32 48 6036 memory J1 R33 53 2500 memory J1 P33 10 2500 memory J1 L32 10 5000 memory J1 L33 13 3536 memory J1 K33
172. Miss PowerPC CPU bus memory transfers have the following characteristic behavior When a CPU issues a memory access followed immediately by another memory access the se cond access is typically from the same page of memory On the other hand if the second memory access does not immediately follow the first one so that the CPU bus goes idle then the second memory access is typically a page miss Thus the majority of memory ac cesses following a bus idle condition are page misses 660 memory performance is opti mized by assuming that a CPU to memory transfer from bus idle will be a page miss When neither the CPU or the PCI is accessing memory the memory controller goes to the idle state and all RAS lines are precharged deasserted Deasserting the RAS lines at idle begins to satisfy the minimum RAS precharge time requirement Assuming that the first access out of idle will be a page miss this technique allows the memory controller to reduce the time required for the initial beat of the burst DRAM read or write access by three CPU clocks If the initial access is a page hit this technique results in an increase in access time of two CPU clocks A net gain is realized whenever the system is experiencing more page misses from bus idle than page hits from bus idle For the first beat of pipelined transactions the memory controller checks the 11 0 memory address for a page hit If the address is within the same 8K memory page as the pr
173. O 60X Address 8000 0000 8000 0001 8000 0002 Contiguous 603 604 addresses No gaps 8000 FFFE 8000 FFFF Figure 3 3 Contiguous PCI I O Address Translation 3 3 3 Final Address Formation The 660 maps 60X CPU bus addresses from 2G to 4G as PCI transactions error address register reads or ROM reads and writes The 660 manipulates 60X bus addresses from 2G to 4G to generate PCI addresses as follows PCI 0 31 30 are set to zero PCI AD 2 0 are unmunged if little endian mode is selected e After unmunging PCI AD 1 0 are set to 00b except for PCI I O cycles 3 6 G5220297 00 Power Preliminary Section 3 CPU amp L2 3 4 CPU to Memory Transfers The system memory address space is from 0 to 2G Physical memory does not occupy the entire address space When the CPU reads an unpopulated location the 660 returns all ones and completes the transfer normally When the CPU writes to an unpopulated loca tion the Bridge signals normal transfer completion to the CPU but does not write the data to memory The memory select error bit in the error status 1 register bit 5 in index C1h is set in both cases All CPU to memory writes are posted and can be pipelined The 660 supports all CPU to memory bursts and all single beat transfer sizes and align ments that do not cross an 8 byte boundary which includes all memory transfers initiated by the 603 604 CPU 341 LE Mode The bridge supports all transfer si
174. OCUMENT YOU SHOULD CAREFULLY READ THE FOLLOWING TERMS AND CONDITIONS OPENING THE PACKAGE INDICATES YOUR ACCEPTANCE OF THESE TERMS AND CONDI TIONS IF YOU DO NOT AGREE WITH THEM YOU SHOULD PROMPTLY RETURN THE PACKAGE UNOPENED TO YOUR IBM SALES OFFICE International Business Machines Corporation IBM agrees to provide you an 100 MHz PPC 603e MOM in return for your promise to use reasonable efforts to develop a system based on the technology inthe The contains documentation and software listed below Documentation IBM27 82660 PowerPC to PCI Bridge and Memory Controller User s Manual PowerPC 603e RISC Microprocessor Hardware Specification PowerPC 603e RISC Microprocessor Technical Summary 64K x 18 Burst 041814 Data Sheet Texas Instruments 3 3V ABT 16 Bit Bus Transceivers with 3 State Output SN54LVTH16245A SN54LVTH16245A Data Sheet Integrated Device Technology BiCMOS StaticRAM 240K 16K x 15 Bit Cache Tag RAM for PowerPC and RISC Processors IDT71216 Data Sheet Motorola Low Voltage PLL Clock Driver MPC970 D Data Sheet LICENSE TO SOFTWARE The software is licensed not sold IBM or the applicable IBM country organization grants you a license for the software only in the country where you received the software Title to the physical software and documentation not the information contained in such documentation transfers to you upon your acceptance of these terms and conditions The term so
175. ON LOUD ONG Lassa LL Lo Lo Lo Lo Lo Lo Lo Lo 5 40 2 OY CON NWN O aT RT A Lob 5 40 c OI UON LOU O CT lc Lo Lolo bo Lo Lo Lo Lo 5 dO c E 5 S nmmxin 5 35 5 HEE ARR HOHHH OHH EA EH EA EA EA EAE ER ER EH 222525225252522525252525252522 c T lo bolo lo 4d m OO to Lh 5555 TTT 1 212 111 4 1 1 4 4 1111 1 1 HHHHHHHHHHHHHHHHHHHHHHHHH bc bo bc Le b bolo bo MOgIGO M 78100 55 9100 9100 8 le le le SIS HH HHHH 22222222522222222222225225 TTTTTTTTTTTTTTTTTTTTTTTTTT C 190014 m T 190714 eS 23 23 e SN OTcTZ LOI 8 o in E B gt 11 11111 1111 BRR SSS SSS 25525555555555555555555555 ANNU OOS 9000000001001 E Q 222222222 AXIM 222222222 UO NC IW wi Qnin ZO
176. PCI Device Status Single Bit Error Counter Single Bit Error Trigger Level Bridge Options 1 Error Enable 1 Error Status 1 CPU Bus Error Status Error Enable 2 Error Status 2 PCI Bus Error Status CPU PCI Error Address Single Bit ECC Error Address Bridge Chip Set Options 3 8 16 G5220297 00 PowerPc Preliminary Section 8 Exceptions 8 2 11 Special Events Not Reported as Errors G5220297 00 A PCI to memory cycle at any memory address above that programmed into the top of memory register The 660 ignores this cycle and the initiator master aborts No data is written into system memory on writes and the data returned on reads is indeterminate The busmaster must be programmed to respond to a target abort by alerting the host CPU to PCI configuration cycles to which no device responds with a DEVSEL sig nal within 8 clocks no device at this address The data returned on a read cycle is all 1 s and write data is discarded This allows soft ware to scan the PCI at all possible configuration addresses and it is also consistent with the PCI specification A CPU read of the IACK address having a transfer size other than 1 or having other than 4 byte alignment These conditions return indeterminate data The ISA bridge requires the byte enables CBE 3 0 to be 1110 in order to place the data on the correct byte lane 0 Accesses other than one byte at the address BFFF FFFOh are undefined A read of the IACK address when no
177. Power Consumption D 1 Specifications for 3 3V Regulator on the Motherboard D 2 Keyboard Connector Pin Assignments 0 9 Alternate Keyboard Connector Pin Assignments 0 9 Mouse Connector Pin Assignments 0 10 Speaker Connector Pin Assignments 0 10 Power Good LED Connector 0 11 HDD LED Connector 2 08 tiga 0 11 Reset Switch Connector 0 11 Fan Connector Pin Assignments 0 12 3 3V Power Connector J5 Pin Assignments 0 12 Power Connector J4 Pin Assignments D 12 AUX5 ON OFF Connector Pin Assignments D 13 PCI Connector Pin Assignments D 13 ISA Connector Pin Assignments D 15 DRAM SIMM Connector Pin Assignments D 16 Power Switch Connector Pin Assignments 0 18 Power Up Configuration Connector Pin Assignments 0 18 RISCWatch Connector Pin Assignments 0 19 Height Considerations D 22 Planar Bill of Materials E 1 xviii G5220297 00 Pewer Preliminary About This Book This document is designed for engineers and system designers who are interested in implementing PowerPC systems th
178. S MATCH TAG MATCH Figure 3 7 Synchronous TagRAM 512K L2 3 14 G5220297 00 PowerPc Preliminary Section 4 DRAM Section 4 DRAM The memory controller in the 660 bridge controls the system memory DRAM The system memory can be accessed from both the CPU bus and the PCI bus Much of the information in this section has been drawn from the 660 User s Manual 41 Features and Supported Devices e Supports memory operations for the PowerPC Architecture Data bus path 72 bits wide 64 data bits and eight bits of optional ECC or parity data Eight SIMM sockets supported Eight RAS outputs eight CAS outputs and two write enable outputs Supports industry standard 8 byte 168 pin SIMMs of 8M 16M 32M 64M and 128M that can be individually installed for a minimum of 8M and a maximum of 1G Supports industry standard 4 byte 72 pin SIMMs of 4M 8M 16M 32M 64M and 128M that must be installed in pairs for a minimum of 8M and a maximum of 1G Mixed use of different size SIMMs including mixed 4 byte and 8 byte SIMMs Full refresh support including refresh address counter and programmable DRAM refresh timer Burst mode memory address generation logic 32 byte CPU bursts to memory Variable length PCI burst to memory Little endian and big endian addressing and byte swapping modes Provides row and column address multiplexing for DRAM SIMMs requiring the fol lowing addressing 720
179. T 60 J1 D31 7 3536 funct TAG_ADDR_13 J1 L26 6 0000 funct TAG_DATA_11 J1 M27 52 1036 funct IGN_PCI_AD31 J1 AD01 4 6624 funct X_SRAM_BCLKO J1 Y29 5 1624 funct X SRAM BCLK1 J1 AF29 9 1624 funct X SRAM BCLK2 J1 AF05 8 6624 funct X SRAM J1 Y05 1 7500 funct X 663 CPU CLK J1 F05 G5220297 00 12 7 Y d Section 12 Electromechanical Preliminary Power Table 12 1 MCM Primary Continued Net Length Net Topology 10 1036 funct X 664 CPU CLK J1 H29 U2 121 8 6036 funct X CPU RDL J1 G10 U3 148 OPEN 22 2500 funct NMI FROM J1 A31 U2 56 ISABRDG 7 2071 funct POWER J1 A28 U2 156 GOOD RESET 7 2071 funct rw HRESET J1 E32 R1 D04 35 6584 J1 B25 R1 J04 41 2051 TDI J1 A25 R1 J05 14 6846 TDO J1 C26 U1 198 34 9543 TMS J1 A24 1 03 58 3719 CKSTP_OUT J1 AJ02 R1 J01 58 3719 TRST J1 C24 R1 H04 29 4987 TTO J1 A19 U1 191 27 6398 TT1 J1 B19 U1 190 15 3133 TT2 J1 A20 U1 185 28 0788 J1 A21 U1 184 5 3536 SHD J1 D27 U2 141 51 7310 5 J1 AL02 R1 F05 11 6036 TAG CS2 J1 H31 U5 76 21 5000 TT2 664 J1 C14 U2 153 35 9554 DBG_60X J1 G08 U1 26 70 1036 L2_CLAIM J1 AL01 U2 132 21 8536 663_TEST J1 G14 U3 155 49 6036 664_TEST J1 J04 U2 155 30 8536 MATCH J1 K31 U2 142 22 0000 BG J1 N20 U2 135 56 1497 SRAM_ADSP J1 AK03 U7 1
180. T68 pin 16 Meg 11x10 G5220297 00 4 1 Section 4 DRAM Preliminary PowerPc 4 1 1 SIMM Nomenclature The term SIMM is used extensively to mean DRAM memory module without implying the physical implementation of the module which can be a SIMM DIMM or other package 4 1 1 1 DRAM Timing The memory controller timing parameters are programmable to allow optimization of tim ings based on speed of DRAM clock frequency and layout topology Timing must be pro grammed based on the slowest DRAM installed e Support for fast page mode DRAMs e Support for extended data out EDO DRAM hyper page mode If 70ns DRAM is used in a system with the CPU bus at 66MHz the minimum access times for initial not pipelined CPU to memory transfers with page mode and EDO DRAM are as follows EDO DRAM Page Mode DRAM Noe Initial Read Burst 10 3 3 3 11 4 4 4 CPU clocks for 32 bytes Initial Write Burst 5 3 3 3 5 4 4 4 CPU clocks for 32 bytes e In the same system the times for a pipelined burst following a read are as follows EDO DRAM Page Mode DRAM Note Page Hit Read 5 3 3 3 5 4 4 4 CPU clocks for 32 bytes Page Hit Write 3 3 3 3 3 3 4 4 CPU clocks for 32 bytes e Inthe same system the times for a pipelined burst following a write are as follows EDODRAM Page Mode DRAM Note 2 5 3 5 3 5353 e Other minimum memory timings are as follows PCI to memory read at 66MHz CPU and 33MHz PCI 8 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 7 1 1 1 1
181. TRDY to indicate that the PCI target is ready Data transfer occurs when both PCI_TRDY and PCI IRDY are asserted 2 1 4 DRAM Table 2 6 DRAM Signals Sarai Name WOM esci 11 0 192 0 660 multiplexed Memory address MA 11 is the most significant bit MCE 7 0 660 CAS 7 0 Column address selects CAS 0 selects memory byte lane 0 660 DATA 63 0 Memory data bus MD 63 56 is always called memory byte lane 7 and is accessed using CAS 7 MEM DATA 7 15 63 are always the most significant bit in their memory byte lane In BE mode MEM DATA 63 56 is steered to from CPU_DATA 56 63 In LE mode MEM DATA 63 56 is steered to from CPU_DATA 0 7 Most Mem MEM Signif Byte Corresponding CPU Data in DATA Bit Lane CAS mode LE mode 63 56 63 7 56 63 0 7 55 48 6 48 55 8 15 47 40 5 40 47 16 23 39 32 4 32 39 24 31 31 24 3 24 31 32 39 23 16 2 16 23 40 47 15 8 15 1 8 15 48 55 7 0 7 0 0 7 56 63 660 CHECK 7 0 Memory ECC parity bus MDP 0 is always the memory check bit for memory byte lane 0 MD 7 0 ECC or even parity is generated and written on memory write cycles when enabled ECC or even parity across eight bytes is checked on memory read cycles when enabled 2 8 G5220297 00 PowerPc Preliminary Section 2 Signals Table 2 6 DRAM Signals Contnued MRE 7 0 amp u2 660 7 0 Row Address Selects MWEO M33 U2 176
182. TRL REF is high and indicates use of little endian or big endian mode when DUAL CTRL REF is low 660 Memory Byte Enables signal The eight BEs for read modify write memory cycles are multiplexed on BE 3 0 When not running a read mod write cycle MEM BE 3 0 should indicate MEM BE 3 0 all data lanes are enabled MEM RMW 7 0 all asserted low MEM DATA OE 2 114 U2 196 660 Memory Data Output Enable signal When asserted the 663 drives U3 145 the MEM DATA bus on the next CPU CLK ECC LE SEL L12 2 12 G5220297 00 PowerPc Preliminary Section 2 Signals Table 2 9 InterChip Communication Signals Continued Signal Name MEM Nodes Description MEM ERR 660 Memory Error signal When asserted indicates an uncorrectable 663 MEM ERR multi bit or parity error has occurred during a memory read This signal is only valid on the third after MEM RD SMPL is asserted MEM RD SMPL 660 Memory Read Sample signal This signal is used by the ECC logic to determine when to sample ECC results This signal is also used by the PCI read extension latch and the PCI to MEM read latch to load new data WRL OPEN 14 660 Memory Write Latch Open signal When asserted the MEM write latch accepts new data on each CPU CLK When deasserted the MEM write latch holds its current contents MWS P2MRXS C30 U2 66 660 Memory write select PCl to memory read crossover select signal
183. TZ The following rules must be followed to ensure cor rect operation 1 RESET must be asserted for at least eight CPU consecutive CPU clocks This is the minimum RESET pulse width 2 Both the CPU and PCI clocks must be running properly during the entire reset interval 3 Bus activity on the PCI bus must not begin until at least 4 CPU clocks after the deasser tion of RESET 4 Bus activity on the CPU bus also must not begin until at least 4 CPU clocks after the deassertion of RESET 5 Assertion and deassertion of RESET can be asynchronous for normal operation but if deterministic operation is required see section 8 3 2 3 All 660 outputs reach their reset state by the second CPU clock after RESET is first sampled active The rest of the minimum RESET pulse width is used by the 660 to initialize internal processes including setting internal registers and determining the CPU to PCI clock ratio Except as noted in section 8 3 2 1 all 660 outputs maintain their reset state until an external stimulus CPU bus activity forces them to change 8 3 2 1 Reset State of 660 Pins The following symbols are used in Table 8 3 and Table 8 4 means the signal is an input The signal does not have arequired state during reset means that the pin is tristate hi Z during reset means the state of the pin during reset is undefined means that the pin is driven to a logic 1 state hi means that the pin is driven to a logic 0 state l
184. Table 6 4 Remote ROM Read Sequence CPU Address FFFX PCI Big Endian Little Endian Byte Enables ROM ROM CPU DATA CPU DATA Address PCI AD 31 0 PCI C BE 3 0 EN 0 63 0 63 Me 98 E E 2 e oon om fee enon wm ajel Ms TT gt ow om Jeo s eom 7 ses 6 2 1 2 Address Transfer Size and Alignment The initial PCI address generated during the remote ROM read sequence is formed by co the high order 29 bits of the CPU address and forcing the three low order bits PCI AD 2 0 to 000b This generates base address that is aligned on an 8 byte boundary While reading the lower 4 bytes the 660 indicates which byte it is requesting using the PCI byte enables C BE 3 0 After the first four bytes of ROM data are read the 660 increments the address on the PCI AD lines by 4 before executing the second four PCI reads The CPU read address need not be aligned on an 8 byte boundary A CPU read from any address ROM space of any length that does not cross an 8 byte boundary within a double word returns all eight bytes of that double word data from the ROM For example the operations shown in Table 6 4 could have been caused by a CPU memory read to FFFO 0100h FFFO 0101h or FFFO 0105h Errors occurring during remote ROM reads are hand
185. Tea 26 eddy SOS Wess GINS IND Weeds CNIBEXEMET blado ON IH HBEHS X un 128 40 FRESHER Se NOHISU3 nuizq3r 41004 1597 ES INOISIC3M NOILIUHOdHOOD WAT S667 LHOIHAdOO JHOY E E d paz 02591 1 9T TEU lt 2 lt gt 5581 TED ST 27 Ec Sc 82 2189 SING 8159 Wd 850 eoo 900 200 saate 80d 2100 7100 945 310 3508 SS amp dHdA2 804 SNOI LODO 1 1LAHDOSOUIIN UHLIXd 5 SS3ddA2 405 59 TO aM Orre S 40 T SLIM CIWNIL 4735 INO HAINDOOD 15858 HIIM 211916 S IONOHHONAS 118 87 X 35898 S13 0GOHDIM NO AML23MIGI HLIM NOISH4d 3498 118 87 X vVTBTrOWSI THOGOAN INS NOUS TH Ia WOHS 8S2 lt 102 1 gaa gug gag gag OTELA poL lt g
186. The 660 only uses GBL as an output 3 10 G5220297 00 Power Preliminary Section 3 CPU amp L2 3 7 2 Cache Response to PCI Bus L2 maintains coherency during PCI to memory transactions as shown in Table 3 5 The L2 does not supply data to the PCI bus The L2 is not updated during a PCI transaction Table 3 5 L2 Operations for PCI to Memory Transactions 603 Mode PCI Bus CPU Bus Broadcast Snoop L2 Operation Memory Read Single Beat Read 01010 Memory Write Single Beat Write with Flush 00010 Invalidate Block Initiate Lock Read _ Single Beat Write with Flush 00010 Invalidate Block 3 7 3 L2 Configuration The L2 controller does not require any software configuration to set the size or organization of the tag and data SRAM The connection to the CPU address bus determines the size ofthe tag RAM and data SRAM Bridge Control Register D4 bit 3 should be setto 1 to select burst as the SRAM type 3 7 4 12 Organization The L2 directory contains 8K entries with one tag per entry The cache line block size is 32 bytes the PowerPC 60X coherence unit The L2 maintains coherence for the 32 byte block and neither operates on nor maintains the status of smaller units of memory All of the tags together are sometimes called the cache directory The L2 uses only A 2 31 to store and access L2 data A 0 1 are not used or saved in the cache directory because the MCM only caches the lowest 1G of the address space A 0 1
187. The beginning address of the partition in head sector cylinder notation Partition End The end address of the partition in cylinder head sector nota tion Beginning Sector The number of sectors preceding the partition on the disk That is the zero based relative block address of the first sector of the partition Number of Sectors The number of sectors allocated to the partition The subfields of a partition table entry are defined as follows Boot Ind Boot Indicator This byte indicates if the partition is active If the byte contains 0x00 then the partition is not active and will not be considered as bootable If the byte contains 0x80 then the partition is considered active Head An eight bit value zero based Sector A six bit value one based The low order six bits are the sector value The high order two bits are the high order bits of the 10 bit cylinder value Cylinder The low order eight bit component of the 10 bit cylin der value zero based The high order two bits of the cylinder value are found in the sector field Sys Ind System Indicator This byte defines the type of the partition There are numerous partition types defined For example the following list shows several 0x00 Available partition 0x01 DOS 12 bit FAT 0x04 DOS 16 bit FAT 0x05 DOS extended partition 0x41 PowerPC Reference Platform partition 10 3 1 2 Extended DOS Partition The extended DOS parti
188. Therefore this error is never generated during PCI to memory reads This error is not reported to the CPU 8 2 5 6 Errant Masters Both PCI and ISA masters can access certain planar and ISA bridge registers For exam ple various control registers such as the Map Type register the mode bit the Memory Control registers etc are accessible Faulty code in the PCI or ISA masters can defeat password security read the NVRAM and cause the system to crash without recov ery Take care when writing device drivers to prevent these events 8 2 6 Memory Transaction Errors 8 2 6 1 Memory Select Error This error is generated if a device addresses the system memory space CPU addresses from to 2G and PCI addresses from 2G to 4G when memory is not present at that ad dress The 660 only claims PCI accesses by asserting PCI DEVSELz when the access is to an address where memory is present The 660 disconnects PCI burst cycles at 1M boundaries This ensures that a PCI master cannot begin a transfer at an address where memory is present and then burst increment ing the address to an address where memory is not present therefore the memory select error is never generated on PCI accesses to system memory The memory select error can be controlled by the indexed register set The 15 at regis ter COh bit 5 If an error is detected the status bit at register 1 bit 5 is set Register C7h bit 4 is cleared to indicate an erro
189. ad System memory read e if no address conflict Multiple 1101 Dual Address 1110 Memory Read Line System memory read e if no address conflict Memory Write and Yes System memory write Yes if no address conflict Invalidate PCI busmasters are not able to access the boot ROM or the BCRs in the 660 PCI busmasters can not initiate transactions to the CPU bus CPU bus devices can howev er initiate transfers to the PCI bus Large amounts of data are typically moved between the PCI bus and memory by bursts initiated by a PCI busmaster See Section 8 1 3 and the PCI specification for information on PCI Interrupt Acknowledge transactions 5 1 2 PCI Memory Transaction Decoding By Address Range When a PCI busmaster transaction is decoded by bus command as a system memory read or write the 660 checks the address range Table 5 2 shows the address mapping of PCI busmaster memory accesses to system memory This is the mapping that the 660 uses when it decodes the bus command to indicate a system memory access 5 2 5220297 00 PowerPc Preliminary Section 5 PCI Bus Table 5 2 Mapping of PCI Memory Space Part 1 PCI Bus Address Other Conditions Target Cycle Decoded Target Address 0 to 2G IGN PCI 1 Not Decoded N A No Response Deasserted IGN PCI AD31 System Memory 0 to 2G Snooped by caches Asserted 2G to 4G el System Memory Snooped by caches Memory does not occupy this entire address space Acce
190. afoj co B66T 62 ES 20 41 031 41004 1597 Qc 20 8 13395 74355400 NUMNISO3 gt H3BLDON NOTSIAY 5661 1 071 31545 QUJMdINI WOW lt 827 ose GIOI r3 o26 osgosr Sed Berge 5854 o2u6 lt rauee L009 EDT OE 8ZT o 9e 543 26 Suec 0205 lt gt g09T S g Bed Ged 999 ara Sad 573 avez GOO 754 Sra BE ver Sg 20 EBZT AT 40 97 E SNId Tf 90 4 920 ST 4027 NE E ved SNId 54985 Tf BEH rca STE aaa STE reve LOTO d g xag zaa up erg Eza Bgg ea oO QE 3 per 40 ST 228 LTH SNId 27 sO 27 40 SNId SNId ozs LOO 57543 SLOOP E5 lt E TOON ce eo TOON
191. age mode to deassert the RAS lines 1 ii T 5220297 00 PowerPc Preliminary Section 4 DRAM In response to the RESET signal this register is reset to 53h This value results in a maxi mum RAS active time of just under 10us at 66MHz This is the value required by most 4 byte and 8 byte SIMMs The value of the BCR must be reprogrammed if the CPU bus frequency is not 66MHz or a different RAS pulse width is required 4 2 1 4 DRAM Timing Calculations The memory controller of the 660 features programmable DRAM access timing DRAM tim ing is programmed into Memory Timing Register 1 MTR1 and Memory Timing Register 2 MTR2 See section 4 2 1 for an explanation of the format of these BCRs All memory controller outputs are switched on the rising edge of the CPU clock with the exception of signal assertion during refresh operations which is timed from the PCI clock The RAS Watchdog Timer Register the Refresh Timer Divisor Register and the Bridge Chipset Op tions 3 BCO3 BCRs also have an effect on DRAM timing The values programmed into these registers are a function of the clock frequencies the timing requirements of the memory the amount of memory installed capacitive loading the mode of operation EDO vs standard the timing requirements of the 660 the type and arrangement of buffering for the MA memory address signals the clock skew between the 663 and the 664 and the net lengths of the signals to from t
192. all time note 1 Note 1 664 drivers that drive the RAS and CAS signals are slower falling than rising This causes active high pulse widths to grow by 0 to 5ns and active low pulse widths to shrink by 0 to 5ns 8 Refresh Timer Divisor The refresh timing divisor is clocked by the PCI clock The required value is calculated as follows Refresh rate period Tref clock 9 RAS watchdog timer The RAS watchdog timer must be set to limit the max RAS pulse width RAS watchdog timer Tras max period CPU clock 8 4 2 1 5 DRAM Timing Examples This section presents example DRAM timing calculations based on the equations found in Section 4 2 1 4 Except as noted in Section 4 2 1 4 the timing recommendations in this section apply to all 660 configurations In the equations below first the capactive loads are calculated based on the quantity and types of SIMMs and the buffers used Next the timing characteristics are calculated based on the capacitive loads Finally the timing requirements and register values are caculated 4 2 1 6 70ns DRAM Calculations Ex 1 Assume 70 standard DRAM memory four 72 pin DRAM SIMMs a CPU bus cycle time of 15ns 66 7Mhz and MA 11 0 buffered by an FCT244 four SIMMs per driver Capacitive loads RAS 2 62pf 30pf 154pf CAS 2 62pf 30pf 154pf MA to buffer 2 30 MA to memory 4 161pf 40pf 684pf Timing Characteristics RAS 13 2ns
193. and is composed of an odd number of data phases in which all data phases trans fer four bytes of data Here the total effect is to add three PCI clocks to the transaction time which is shown during the first data phase in Table 4 15 Table 4 15 Bridge Response to Case 2 PCI Write Burst Data Bridge Special Conditions Performance Impact Phase Operation ast High Wits Boy Wile Setup RW Add 3 POT clocks 4 28 G5220297 00 PowerPc Preliminary Section 4 DRAM Table 4 16 Bridge Response to Various PCI Write Bursts Data Bridge Special Conditions Performance Impact Phase Operation 7 aT SL s 10 Hes byte transfer aaas Poio a Game TEE Dye Wi 1 High Sore Wie 1 L Setup Gather None None first Table 4 16 shows the effect of several conditions on the transaction time Rows 1 through 6 show the effects of a less than 4 byte transfer at the high word location that occurs during a burst The term Nonein the column titled Performance Impactin row 6 indicates that there are no residual performance penalties due to the events of rows 1 through 5 Rows 7 through 9 show the effect of a less than 4 byte transfer at the low word location that occurs during a burst The term None in the column titled Performance Impact in row 9 indi cates that there are no residual performance penalt
194. asserted high can cause bus contention because multiple PCI agents will be selected In systems that contain the Intel SIO chip it must be configured prior to any other PCI bus agent The SIO PCI arbiter is automatically enabled upon power on reset During power on reset the SIO drives the A D 31 0 C BE 3 0 and PAR signals on the PCI bus 9 3 1 Multi Function Adaptors The 660 supports multi function adapters It passes unmodified the address of the load or store instruction that causes a PCI configuration cycle The only exception is that the three low order bits are unmunged in little endian mode and the two low order address bits are set to zero in either endian mode therefore addresses may be selected with non zero CPU address bits 21 23 corresponding to PCI bits 10 8 to configure multi function adaptors For example to configure device 3 in slot 1 use address 80 0 03XXh config ure device 7 in slot 2 use address 8084 07XXh 9 3 2 PCI to PCI Bridges The 660 supports both Type 0 and Type 1 configuration cycles 9 3 3 Indexed BCR Summary Table 9 2 contains a summary listing of the indexed BCRs in the 660 Access to these regis ters is described in the 660 Bridge User s Manual The values shown in the Set To column are for reference only and may not apply to a particular application Table 9 2 660 Bridge Indexed BCR Listing Bridge Control Register R W Bytes Set To 1 PCI Vendor ID In
195. at use the 100 MHz PPC 603e The material requires a detailed understanding of computer systems at the hardware and software level Power management is beyond the scope of this document This document was written by Dale Elson Reference Material Understanding of the relevant areas of the following documents is required for a good understanding of the 100 MHz PPC 603e MCM PowerPC 603e RISC Microprocessor User s Manual document MPR603EUM 01 PowerPC 603e Hardware Specification document MPR603EHS 01 PowerPC 603e Technical Summary IBM document MPR603TSU 04 BM27 82660 PowerPC to PCI Bridge User s Manual document number MPR660UMU 01 PCI Local Bus Specification Revision 2 1 available from the PCI SIG PowerPC Reference Platform Specification Version 1 1 document MPRPRPPKG The Power PC Architecture second edition Morgan Kaufmann Publishers 800 745 7323 document MPRPPCARC 02 Intel 82378ZB System I O SIO Data Book Intel order number 290473 004 The following documents are useful as sources of tutorial and supplementary information about the MCM PowerPC System Architecture Tom Shanley Mindshare Press 800 420 2677 IBM27 82650 PowerPC to PCI Bridge User s Manual document number 6500 0 01 Document Conventions The terms 660 and 660 bridge refer to the IBM27 82660 The terms 660 UM and 660 User s Manual refer to the current version of the BM27
196. ata The system is in little endian mode so the buffer swaps the data bytes If the register data is AB012345h then is written to address 012345h of the ROM Only single beat four byte write transfers store word are supported Table 6 2 ROM Write Data Flow in Little Endian Mode CPU Register CPU DATA 0 63 PCI AD 31 0 ROM Signal 32 39 ROM Data 31 24 D 7 0 40 47 ROM Address high byte 23 16 23 16 gt 9855 ROM Address mid byte 5 8 56 63 ROM Address low byte A 7 0 6 1 2 4 Data Flow In Big Endian Mode Figure 6 5 and Table 6 3 show the flow of CPU Data through the 660 to the ROM while the system is in big endian mode Note that the CPU Data bus is labeled in big endian order the PCI bus is labeled in little endian order and the 660 is labeled to match and the bit significance within the bytes is maintained 1 T O 5220297 00 PowerPc Preliminary Section 6 ROM 60X CPU MSB CPU Register Addr Addr Data LSB low med high 2 3 1 2 NO H aN ON o oco Ra Address not munged Data bytes not swapped CPU A 29 0 selects CPU data bytes 0 3 Figure 6 5 ROM Data and Address Flow In Big Endian Mode When the CPU executes a store word instruction to FFFF FFFOh the contents of the source register appear on CPU DATA 0 31 CPU ADDR 29 0 so the 660 selects CPU data byte lanes 0 through 3 as the source of the data The system is
197. attaches to the 660 by means of control lines and the PCI AD 31 0 lines When a CPU busmaster reads from the ROM the 660 masters a BCR transaction during which it reads the ROM and returns the data to the CPU CPU writes to the ROM and ROM write protection operations are also forwarded to the ROM device ROM accesses flow from the CPU bus to the 660 As shown in Figure 6 1 the data and address flow from the 660 to the ROM over the PCI AD lines ROM control flows from the 660 to the ROM over control lines that are not a part of the PCI bus G5220297 00 6 1 Section 6 ROM Preliminary PowerPc Although connected to the PCI AD lines the direct attach ROM is not a PCI agent The ROM and the PCI agents do not interfere with each other because the ROM is under 660 control and the 660 does not enable the ROM except during ROM cycles The 660 ac cesses the ROM by means of BCR transactions Other PCI devices cannot read or write the ROM because they cannot generate BCR transactions System ROM Control Figure 6 1 ROM Connections 611 ROM Reads When a CPU busmaster reads from memory addresses mapped to ROM space the 660 arbitrates for the PCI bus and then masters a BCR transaction on the PCI bus During this transaction the 660 reads the ROM eight times accumulates the data and returns the double word to the CPU The 660 then completes the PCI transaction and releases the PCI bus The 664 drives the address of the required byte ov
198. because it crosses 8 bytes transforms to 2 singles in BE machine CH in LE P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603e bus in LE mode G5220297 00 11 11 Li Li p Section 11 Endian Preliminary PowerPc 11 8 Four Byte Transfers Figure 11 5 gives an example of Word 4 BYTE Write of AT ADDRESS Xxx4 Big Endian Little Endian Swap Off Memory Swap On Memory Figure 11 5 Word 4 Byte Write of Oa0bOcOdh at Address xxxx xxx4 11 12 G5220297 00 PowerPc Preliminary Section 11 Endian Table 11 11 and Table 11 12 illustrate the cases that can occur The columns of Table 11 11 have these meanings e The first column indicates the target address e g the address of the byte coded into a store word instruction e The next two columns show the state of the address pins for BE mode e The next two columns show the state of the address pins for the same target data when the machine is in LE mode The remaining columns show the CASs and the PCI byte enables associated with the target data e The notes indicate which combinations either do not occur at the 603e pins because of internal exceptions or are not supported externally Table 11 11 Four Byte Transfer Information BE MODE LE MODE BE OR LE BE OR LE BE OR LE 603e BE x or w 100 Target CAS 0 7 PCI add 29 31 add a29 31 bytes 0 7 AD2 3210 000 4 100 0 3 0000 1111 0 0000 001 5 E 1
199. ble 11 1 Endian Mode Operations Mode Whatthe 603e Does What the 660 Does Big Endian BE No munge no shi Little Endian LE Address Munged amp Data Shifted Address Unmunged amp Data Swapped In BE mode the CPU emits the address unchanged and does not shift the data This is the native mode of the 603e CPU In BE mode the 660 passes the address and data through to the target without any changes that are due to endian mode In LE mode the CPU transforms munges the three least significant address bits and shifts the data on the byte lanes to match the munged address In LE mode the 660 un munges the address and swaps the data on the byte lanes 5220297 00 11 1 Li p Section 11 Endian Preliminary PowerPc 11 1 What the 603e CPU Does 11 1 1 The 603e Address Munge The 603e CPU assumes that the significance of memory is BE When it operates in LE mode it internally generates the same effective address as the LE code would generate Since it assumes that the memory is stored with BE significance it transforms munges the three low order addresses when it activates the address pins For example in the 1 byte transfer case address 7 is munged to 0 6 to 1 5 to 2 and so on Table 11 2 shows the address transform rules for the allowed LE mode transfer sizes Table 11 2 603e LE Mode Address Transform SPARE None 11 1 2 The 603e Data Shift The data transfer occurs on the byte lanes identified by
200. boot partition may contain an x86 type program When executed on an x86 machine this program displays a message indicating that this partition is not applicable to the current system environment The second relative block in the boot partition contains the entry point offset load image length flag field operating system ID field ASCII partition name field and the reserved1 area The 32 bit entry point offset little endian is the offset into the image of the entry point of the PowerPC Reference Platform boot program The entry point offset is used to allocate the Reserved1 space The reserved1 area from offset 554 to Entry Point 1 is re served for implementation specific data and future expansion G5220297 00 10 5 p Section 10 Firmware Preliminary Power The 32 bit load image length little endian is the length in bytes of the load image The load image length specifies the size of the data physically copied into the system RAM by the firmware The flag field is 8 bits wide The MSb in the field is allocated for the Open Firmware flag If this bit is set to 1 the loader requires Open Firmware services to continue loading the operating system The second MSb is the endian mode bit If the mode bit is 0 the code in the section is in big endian mode Otherwise the codes is in little endian mode The implication of the en dian mode bit is different depending on the Open Firmware flag If the Open Firmware flag is set t
201. bytes of data since writing a byte to memory also updates the associated parity bit During memory writes the bridge gener ates one parity bit for each byte of data and stores it with that byte of data This parity bit is a function only of the data byte with which it is associated During memory reads the in tegrity of the data is parity checked by comparing each data byte with its associated parity bit However when ECC is enabled the bridge reads from and writes to system memory only in 9 byte groups as a 72 bit entity even though the busmaster may be executing a less than 8 byte read or write There is one byte of ECC check byte information for eight bytes of data During memory writes the eight check bits are generated as a function of the 64 data bits as a whole and the check bits are stored with the data bits as a 72 bit entity During memory reads all 72 bits are read and the eight check bits are compared with the 64 data bits as a whole to determine the integrity of the entire 72 bit entity In ECC mode single bit errors are corrected When a multi bit error is detected during CPU to memory reads the error is reported by means of TEA MCP When a multi bit ECC error is detected during PCI to memory reads the error is reported by means of PCI SERRZ Note that the DRTRY function of the CPU is not used even when the 660 is in ECC mode the Bridge will not assert DRTRY Only the data returned to the CPU or PCI is correcte
202. c das a RR RR RE eR RR RR 9 3 Section 10 System Firmware 10 1 VIMOGUCHIONS urbano metis 10 1 10 2 Power On System Test perro tics meri 10 1 10 2 1 Hardware Requirements 10 1 10 3 Boot Record Format oec e EET RACE 10 1 10 3 1 Boot Record aset edente estere uote a Sea aS 10 2 10 3 11 PC Partition Table e ooh etit eR hr eR Res 10 2 10 3 1 2 Extended DOS Partition 10 3 10 3 1 3 PowerPC Reference Platform Partition Table Entry 10 4 10 3 2 Loading the Load Image 10 4 10 4 System Configuration c e ex RE eee 10 6 10 4 1 System Console 2 dd ete du ero uA ee Old oh we obstet 10 6 10 4 2 System Initialization BS hdres Be Okeke BE hee ae 10 7 10 235 Mall 10 8 G5220297 00 Hin ijji Pewer Preliminary 10 4 3 1 System Configuration Menu 10 9 10 4 3 2 Run a Program 10 5 10 4 3 3 Reprogram Flash 10 16 10 4 3 4 E XIECODIOTIS DL x ele 10 17 10 4 4 Default Configuration Values 10 17 Section 11 Endian Mode Considerations
203. ch a refresh happens to be required X is a function of snoop delays only Whenever the memory access crosses a cache block boundary the Bridge broadcasts a snoop cycle on the CPU bus Due to the posted write buffer structure delays incurred by crossing a page boundary here do not show up until later in the sequence X 3 Always The only benefit to disabling PCI snooping or enabling pre snooping is to reduce this delay to 1 Otherwise neither function increases performance Y is a function of memory latency This page and or bank miss delay can only be incurred at a page boundary but shows up here due to the posted write buffer structure The Bridge has a 4 x 4 posted PCI write buffer which allows it to accept data phases from the PCI bus while the memory controller is busy servicing page misses This minimizes the transfer delays caused by these memory overhead functions typ 1 This occurs for a page hit with no refresh This is also the minimum Y mid 2 This occurs for a page miss with no refresh Y max 4 This occurs for a refresh which also forces a page miss Z is a function of a subset of the W factors RAS timeouts and refresh operations This delay is only incurred due to a RAS timeout or refresh request that has occurred since the last W Y Z or G 2 typ 2103 This occurs for no refresh and no RAS timeout 2 max 3104 This occurs for either a timeout or a refresh operation G is the combination o
204. coded to three PCI clocks Bit 5 This bit controls the number of CPU clocks that the row address is held follow ing the assertion of RAS G5220297 00 4 3 es Section 4 DRAM Preliminary PowerPc Alh RAS precharge RP 00 2 CLK 01 3 CLK 10 4 CLK 5 CLK RAS pulse width min RPW 000 reserved 100 5 CLK 001 2 reserved 101 26 CLK 010 reserved 1102 7 CLK 011 4 CLK 11 8 CLK Row Address Hold Time 0 1CLK 1 2CLK RESERVED 4 2 1 2 Memory Timing Register 2 Index 2 Read Write Reset to AEh This BCR determines the timing of CAS signal assertion for memory cycles CAS timing must support the worst case timing for the slowest DRAM installed in the system See Sec tion 4 2 1 RAS to CAS Delay RCD 00 reserved 01 2 CLK 10 3 CLK 11 reserved CAS Pulse Width Reads Write CPW 00 1 CLK 01 2CLK 10 3 CLK 11 Reserved CAS Pulse Width Write CPWW reserved CAS Precharge CP 00 1 CLK 01 2 CLK 10 reserved 11 reserved Column Address Setup ASC 0 1CLK 1 2CLK 4 2 1 3 RAS Watchdog Timer BCR __ 6 This BCR limits the maximum RAS active pulse width The value of this BCR represents the maximum amount of time that any RAS can remain active in units of eight CPU bus clocks The timer down counter associated with this BCR is reloaded on the assertion of any line On expiration of the timer the 660 drops out of p
205. d be used in BE mode to access LE devices and in LE mode to access BE devices 11 5 603e CPU Alignment Exceptions In LE Mode The CPU does not support a number of instructions and data alignments in the LE mode that it supports in BE mode When it encounters an unsupportable situation it takes an in ternal alignment exception machine check and does not produce an external bus cycle See the latest 608e CPU documentation for details Examples include e L MW instruction e STMW instruction Move assist instructions LSWI LSWX STSWI STWX e Unaligned loads and stores G5220297 00 11 5 Li Li p Section 11 Endian Preliminary PowerPc 11 6 Single Byte Transfers Figure 11 2 is an example of byte write data at address xxxx Big Endian Little Endian Swap Off Memory Swap On Memory Unmunge On Figure 11 2 Example at Address xxxx 0 11 6 G5220297 00 PowerPc Preliminary Section 11 Endian Big Endian Little Endian Swap Off Memory Swap On Memory Figure 11 3 Example at Address xxxx xxx2 Figure 11 3 is an example of byte write data a at address xxxx xxx2 For single byte accesses to memory in BE mode Table 11 5 applies Table 11 5 Memory in BE Mode 603e 603e BYTE BYTE MEM BYTE A31 30 29 add LANE LANE LANE 0 1 gt gt o m njo o ejo 1 1 2 2 2 3 3 3 5 5 5 6
206. d for single bit errors The corrected data is not written into the DRAM location 4 4 1 2 ECC Data Flows While ECC is enabled the 660 always reads eight data bytes and one check byte from memory during CPU and PCI reads During busmaster 8 byte writes to memory the bridge writes eight data bytes and one check byte to memory When the busmaster writes less than eight data bytes to memory it is possible for each check bit to change due to a write to any one of the eight data bytes The Bridge then executes a read modify write RMW cycle reading all eight data bytes from memory modifying the appropriate bytes with the new data recalculating all of the check bits and writing the new data and check bits to memory 4 24 G5220297 00 PowerPc Preliminary Section 4 DRAM 4 4 1 3 Memory Reads Figure 4 4 shows a simplified data flow in a 660 system during CPU to memory read trans fers Figure 4 5 shows the simplified data flow during PCI to memory reads The data and check bits flow from system memory into the bridge where the checking logic combines the data with the check bits to generate the syndrome If there is a single bit error in the data the correction logic corrects the data and supplies it to the requesting agent If there is a multiple bit error in the data the bridge signals an error to the requesting agent Note that the structure of the bridge as shown in Figure 4 4 through Figure 4 8 is consider ably simplified and does
207. d in register C7h bit 5 This error can be reset by writing a 1 to register C5h bit 3 This error can also be controlled by means of a register in the 650 compatible register set The mask cannot be controlled by means of this register set If an error is detected the sta tus bits at 8000 0842h bit 0 and 8000 0843h bit 0 is cleared The address is not saved in a 650 compatible register register BFFF EFFOh is undefined This error can be reset by reading 8000 0843h 8 2 3 7 CPU Bus Write to Locked Flash This error is generated when the CPU attempts to write to flash memory when write to flash ROM has been disabled locked out If the flash ROM is directly attached to the 660 see configuration strapping CPU writes to FFFF FFFOh are detected as an error if writing has been locked out by means of 660 compatible register FFFF FFF1h see note in Sections 6 1 2 and 6 1 2 2 If the flash is remotely attached then CPU writes to the 4G 2M to 4G address space are detected as an error if writing has been locked out by means of register BBh bit 0 This error can be controlled by the indexed register set The mask is at register C4h bit O If an error is detected the status bit at register C5h bit 0 is set Register C7h bit 4 is cleared to indicate error on a CPU cycle The CPU address is saved in register C8h The CPU con trol is saved in register and the CPU number is saved in register C7h bit 5 This error can be reset by writing a 1 to r
208. ddress mid byte 1 ROM Address mid byte ROM Address high byte ROM Address low byte ROM Data 6 3 2 Direct Attach ROM Lockout BCR Direct Access FFFF FFF1h Write Only Reset NA After it has been written once this 8 bit write only register prevents direct attach ROM writes D7 ps 25 4 03 2 1 FFFF FFF ih Any Value Bits 7 0 Writing any value to the register prevents all future writes to a ROM that is connected directly to the 660 through the PCI AD lines 6 3 3 Remote ROM Lockout Bit The ROM write protect bit for remote ROM is in the Bridge Chipset Options 2 register index BBh While enabled writes to the remote ROM are forwarded to the PCI memory space While disabled writes to the remote ROM are treated as no ops and an error is signalled After the first time that the bit is set to 0 it cannot be set back to 1 Index BBh Read Write Reset to 4Fh ww 52 o2 o1 oo Flash Write enable 0 Disabled 1 Enabled Other Functions Bit 0 Flash write enable When the ROM is remotely attached this bit controls write access to the flash ROM address space 4G 2M to 4G When enabled writes to this space are forwarded to the PCI memory space at the same address When disabled writes to this space are treated as no ops and an error is signalled After the bit is set to O disabled it cannot be reset to 1 enabled 6 14 G5220297 00 P2werPc Preliminary Section 6 ROM 6 3 4 Oth
209. ddresses in the 4K page are mirrors into the the same 32 byte PCI space Each of the 32 contiguous port addresses in each 4K page has the same protection attributes in the CPU Forced to zero 6 0 X U A d d r e S S Discarded Hono LSB The three least significant address bits areunmunged during the transformation if little endian mode is selected Figure 3 1 Non Contiguous PCI I O Address Transformation For example in Figure 3 2 60X CPU addresses 8000 0000h to 8000 001Fh are converted to PCI port 0000h through 001 Fh PCI I O port 0020h starts in the next 4K page at 60X CPU address 8000 1000h G5220297 00 3 5 Section 3 CPU amp L2 Preliminary Pewer ISA I O 60X Address 8000 0000 8000 0001 8000 0002 60X Addresses 8000 0020 to 8000 OFFF Are Wrapped and Should Not Be Used Figure 3 2 Non Contiguous PCI I O Address Translation 3 3 2 Address Mapping for Contiguous I O In contiguous I O mode CPU addresses from 2G to 2G 8M generate a PCI I O cycle on the PCI bus with PCI AD 29 00 unchanged The low 64K of PCI I O addresses are for warded to the ISA bus unless claimed by a PCI agent Memory page protection attributes may only be assigned by 4K groups of ports rather than by 32 port groups as in the non contiguous mode This is the power on default mode Figure 3 3 gives an example of contiguous l O partitioning ISA I
210. dex 00 01 R 2 10148 PCI Device ID Index 02 03 R 2 00378 9 2 G5220297 00 PowerPc Table 9 2 660 Bridge Indexed BCR Listing Continued Preliminary Section 9 Setup Brage Control Register rw Sero POICommad POIDeviee Stats freo Rw Revision 1D f ji jm Standard Programming maras R ji o POISubdessCode fra R ji 9 POIGiass Code R ji jm POIGache tine Sze r jr POllamenyTme f 9 POIHeaderType r ji 9 PCI Built in Self Test BIST Control maxor n o Polmemuptlne mexe r 9 fPormiemuptPin mex j amnor e POISuordnaeBusNumbe ren j PCI Disconnect Coun re w FCI Special Address BOR ren 2 o G5220297 00 9 3 Section 9 Setup Preliminary PowerPc Table 9 2 660 Bridge Indexed BCR Listing Continued BidgeConwolRegster mo Rw Byles Memory Bank 2 amp 3 AdWessngMode moes awh _ Memory Bank 4 amp 5 Addressing Mode mexe Memory Bank 6 87 Addressing Mode mexar mceSau Cycle j Refresh Timer B5 Not used see Indexed 00 Index B5 t PCI Bus Timer Notus
211. dex D1h DOh 0208h 9 RAS watchdog timer 10 000ns 15ns 8 83d 53h RAS watchdog timer register index B6h 53h default value 4 2 1 7 60ns DRAM Calculations Ex 2 Same assumptions as above but with 60ns DRAM 1 15ns 40 5 Abns gt 40NS MTR1 1 0 201 2 bCLK 15ns 60 5ns 75n gt OONS eee aa MTR1 4 2 100 3 1CLK 15ns gt 10ns 15ns gt 10nS MTR2 6 5 00 4 3CLK 15 5 gt 16ns 15ns 6ns 45nS gt 37NS MTR2 3 2 10 5 1 CLK 15ns gt Ons 13ns 9ns 16ns 15ns gt 6ns b 1 3 CLK 15ns gt 13ns 9ns 30ns 6ns 60 5 gt 58ns MTR2 7 0 6 2 3 CLK 15ns gt 16ns 60ns 6ns 7515 gt 82ns MTR2 1 0 201 see Note 3 7 1 15 5 gt 10ns 415 13ns 1615 15 5 gt 1ins MTR1 5 0 Results Memory Timing Register 1 index A1h 11h Memory Timing Register 2 index A2h 09h 4 8 G5220297 00 PowerPc Preliminary Section 4 DRAM Note 3 The timing analysis above includes one timing violation path 6 is violated by 9 More conservate system designers may wish to use the values MTR1 31h MTR2 0Ah to ensure all timing requirements met under complete worst case conditions 8 Refresh rate 15 6us 30ns 520d 208h Refresh Timer Divisor index D1h DOh 0208h 9 RAS watchdog timer 10 000ns 15ns 8 83d 53h RAS watchdog timer register index B6h 53h default value 4 2 1 8 50ns DR
212. ds and writes 3 2 5220297 00 Power Preliminary Section 3 CPU amp L2 Table 3 1 TT 0 3 Transfer Type Decoding by 660 60X Bus 660 Operation For CPU to 660 Operation For CPU to PCI TT 0 3 60X Operation Transac Memory Transfers Transactions tion 0000 Clean block or lwarx Asserts No other response No PCI transaction only 0001 Write with flush SBW 1 Memory write operation PCI write transaction or burst 0010 Flush block or stwcx Asserts No other response No PCI transaction only 0011 Write with kill SBW or Memory write operation L2 PCI write transaction burst invalidates addressed block 0100 sync or tlbsync Asserts AACK No other response No PCI transaction only 0101 Read or read with SBR 1 Memory read operation PCI read transaction no intent to cache or burst 0110 Kill block or icbi Address Asserts L2 invalidates Asserts No other only addressed block response 0111 Read with intent to Memory read operation PCI read transaction modify 1000 Asserts AACK No other response No PCI transaction Write with flush Memory write operation PCI write transaction atomic Stwcx 1010 SBW Asserts and if the transaction is not claimed by another 60X bus device No PCI transaction No other response 1011 Reserved __ Asserts No other response No PCI transaction 1100 TLB invalidate Asserts No other re
213. e mexe Single Bit Eror Counter mexe o Single BitEror Trigger Lova o _ moSmui mexe 9 _ moSmawoni o o _ oP Bus Enor Saus mexe t jm _ moSmdwong o CPUPOlEmorMddess SmgeBiEOCEmorAdies meco jaw Notes 1 Inthis column along dash means that the initialization firmware does not write to this register The register is either not used not written to or the value of it depends on changing circumstances If the word Memory appears please refer to the System Memory section of the 660 User s Manual The initialization firmware sets the Memory registers depending on the information reported by the DRAM presence detect registers m 9 4 5220297 00 PowerPc Preliminary Section 10 Firmware Section 10 System Firmware 10 1 Introduction The firmware on the 100 MHz PPC 603e planar handles three major functions e Test the system in preparation for execution e Load and execute an executable image from a bootable device and e Allow user configuration of the system Section 10 2 briefly discusses the power on system test function Section 10 3 details a structure for boot records which can be loaded by the system firm ware Section 10 4 describes the system configuration utility This information is included for referenc
214. e 3 2 The acronym BCR means bridge control register Table 3 2 660 Address Mapping of CPU Bus Transactions Other CPU Bus Address Target Transaction Target Bus Address pees 0 to 2G 0000 0000h to 7FFF FFFFh 2G to 2G 8M 8000 0000h to 807F FFFFh 2G 8M to 2G 16M 8080 0000h to 80FF FFFFh 2G 16M to 3G 8M 8100 0000h to BF7F FFFFh 3G 8M to 3G BF80 0000h to BFFF FFFFh 3G to 4G 2M C000 0000h to FFDF FFFFh EM UT Contiguous Mode Non Contiguous Mode PCI I O Transaction PCI I O Transaction BCR Transaction or PCI Configuration Type 1 Transaction PCI Configuration Type 0 Transaction Transactions and PCI Interrupt Ack Transactions 0 to 2G 0000 0000h to 7FFF FFFFh 0 to 8M 0000 0000h to 007F FFFFh 0 to 64K 0000 0000h to 0000 FFFFh PCI Configuration Space 0080 0000h to OOFF FFFFh 16M to 1G 8M 0100 0000h to 3F7F FFFFh 1G 8M to 1G 3F80 0000h 3FFF FFFFh PCI Memory 0 to 1G 2M Transaction 0000 0000h to 3FDF FFFFh 4G 2M to 4G Direct Attach ROM BCR Transaction 0 to 2M FFEO 0000h to FFFF Read Write or 0000 0000h to 001F FFFFh Write FFFFh Lockout ROM Address Space Remote ROM PCI Memory Transaction to 1G 2M to 1G Bus Bridge 0000h to 3FFF FFFFh Notes System memory can be cached Addresses from 2G to 4G are not cacheable Memory does not occupy the entire address space Registers do not occupy the ent
215. e CPU again accesses a block of memory with this same low order address then this tagRAM location will again be ac cessed and the tag stored therein will be compared against 2 13 of the current access If they are the same then there is a cache hit 3 7 6 SRAM The uses four IBM041814 synchronous 64K x 18 SRAMs to implement the SRAM portion of the L2 Figure 3 6 shows the basic connectivity of the MCM SRAM These are synchronous devices and each SRAM consumes one of the MPC970 clocks In burst op eration the address of the data for the initial beat of the burst is latched into the SRAM the address of the data for the next beat of the burst is incremented internally under the control of the ADV input SRAM CNT ENZ Each SRAM is connected to two CPU bus data bytes and the associated two CPU bus parity lines ABUF 13 28 are a buffered copy of CPU A 13 28 The SRAMs are arranged in par allel so that an 8 byte doubleword is addressed during each access thus ABUF 28 is connected to of the SRAM The 660 asserts SRAM WEZ to write into the SRAM and asserts OEZ to read data out of the SRAM The 660 asserts SRAM_ADS to signal the initial beat of the burst G5220297 00 3 13 A Section 3 CPU amp L2 Preliminary PowerPc e Pull SRAM_CS low for normal operation Pull SRAM ADSP5 high for normal op eration 32k x 18 D 0 15 D 16 31 D 32 47 D 48 63 SRAMs DP 0 1 DP 2 3 DP 4 5 DP 6 7 SR
216. e PCI accesses releases the PCI bus and completes the CPU transfer The eight single bytes of ROM data are assembled into a double word in the 663 and passed to the CPU Figure 6 7 shows the beginning of the operation including the first two PCI transactions Figure 6 8 shows the last part of the operation including the last two PCI transactions During and following reset compliant PCI agents are logically disconnected from the PCI bus except for the ability to respond to configuration transactions These agents have not yet been configured with necessary operational parameters PCI agents capable of the re mote ROM access protocol reset with the ability to respond to remote ROM accesses be fore being fully configured The CPU begins reading instructions at FFFO 0100h before it can configure the PCI devices The ROM read discussion assumes that the system is in big endian mode 6 2 1 1 Remote ROM Read Sequence In response to a CPU bus read in the 4G 2M to 4G address range the 660 requests the PCI bus from the PCI arbiter When the PCI bus is granted or if the bus is already parked on the CPU the 660 initiates a series of PCI memory read transactions as shown in Table 6 4 for a CPU read from FFEO 0000h to FFFF FFFF Note that the last column in Table 6 4 shows the effect of little endian mode operation See Section 6 2 1 4 The address of the first transaction is the low order byte of the double word pointed to by the CPU address se
217. e PCI Master 8 10 8 2 4 3 PCI Master Abort Detected While PCI Master 8 10 8 2 5 PCI to Memory Transaction Errors 8 11 8 2 5 1 PCl to Memory Writes 8 11 82 52 8 11 8 2 5 3 Out of Bounds PCI Memory Accesses 8 11 8 2 5 4 PCI Address Bus Error While PCI 8 11 8 2 5 5 Bus Data Error While PCI Target 8 12 92 50677 ERE ep ER 8 12 8 2 6 Memory Transaction Errors 8 12 8 2 6 1 Memory Select 8 12 8 2 6 2 System 8 13 G5220297 00 ix Pewer 8 2 6 3 System Memory Single Bit ECC Error 8 13 8 2 6 4 System Memory Multi Bit ECC Error 8 14 8 2 7 SERR Channel Check and NMI Errors 8 14 8 2 7 1 Asserted Error 8 14 8 2 8 Error Reporting Protocol xr Ste 8 15 8 2 8 1 Error Reporting Willi 8 15 8 2 8 2 Error Reporting With TEA 8 15 8 2 8 3 Error Reporting With 1_5
218. e Section 4 6 3 4 6 2 CPU Reservation The CPU indicates a reservation request by executing a memory read atomic TT 0 3 1101 If there is no PCI lock on the addressed block of memory the bridge allows the transfer but takes no other action If there is a PCI lock on that block the bridge termi nates the CPU transfer with ARTRY does not access the memory location and takes no other action The CPU removes a reservation by executing a memory read with intent to modify atomic TT 0 3 21111 or a memory write with flush atomic TT 0 3 1001 The bridge treats these accesses as a normal memory transfers 4 6 3 PCI Lock The bridge responds to the PCI lock request protocol in compliance with the PCI specifica tion If an agent requests a lock and no PCI lock is in effect the lock is granted Once a PCI lock is granted no other PCI locks are granted until the current lock is released The 660 prevents CPU busmasters and other PCI busmasters from reading or writing with in a block of memory which is locked by a PCI busmaster CPU busmaster accesses to a locked block are retried with ARTRY PCI busmaster accesses to a locked block are re tried with the PCI bus retry protocol PCI and CPU busmaster accesses to other areas of system memory are unrestricted PCI to memory transactions cause the bridge to broadcast a snoop cycle to the CPU bus When a PCI agent is granted a memory block lock the bridge broadcasts a write with flush TT 0
219. e Section 6 2 1 2 The 660 expects the low order byte of ROM data in the 8 byte double word to be returned on PCI byte lane 0 PCI AD 7 0 As shown in The 660 then masters seven more PCI read transactions each time receiving back one byte of ROM data and driving it onto the CPU data bus as shown in Table 6 4 Note that the byte enables are incrementing within each 4 byte word pointed to by the PCI address G5220297 00 Iun In ve Co Section 6 ROM iminary Prel PowerPc uornoesue Jump 1 JOU 4015 AH S2 duues se uoos se 1125 Juose Og eur Now poved si amp epop stu st AAL JU 2012 uo 1 SI 4A CY UMous se poxiesse SI AANI C pousse AINV AA 40 uo poysed st Dd 99 149 099 uo pexred you snq Dd 0 5 st Kepp sni 1 sYT SITIO Od e e so qeug PWD 1 q PPY e PPV 142 099 parsed SARIS MOU snq WY soumssy S D SATO Tod o ACAL TAS AUC 799 4H 0 TH8g O Mod 12 799 Tod LND VIVG
220. e only Some of the information in this section con cerns the example planar rather than the MCM To obtain a copy of the commented source code of the firmware on diskette contact your IBM representative This material is available free of charge with a signed li cense agreement 10 2 Power On System Test The Power On System Test POST code tests those subsystems of the reference board which are required for configuration and boot to ensure minimum operability Tests also as sure validity of the firmware image and of the stored system configuration 10 2 1 Hardware Requirements In addition to the reference board the firmware requires the following peripherals to be installed as adapter cards e Serial Port 1 Address 0x3F8 1 Interrupt IRQ 4 e Serial Port 2 Address Ox2F8 COM2 Interrupt IRQ 3 Floppy Controller Address 0x3F0 Primary Floppy Mode PC AT or PS 2 e IDE Controller Address 0x1F0 Primary IDE 10 3 Boot Record Format The firmware will attempt to boot an executable image from devices specified by the user See Section 10 4 for details on specifying boot devices and order G5220297 00 10 1 Section 10 Firmware Preliminary Power The PowerPC Reference Platform Specification details a structure for boot records which can be loaded by the system firmware This specification is described in the following sec tions 10 3 4 Boot Record The format of the boot record is an extension of
221. e writes are gather store pairs Incurring a RMW operation costs 3 PCI CLKs Table 5 5 PCI to Memory Write Burst Sequence Timing S S 00 04 08 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 W 1 1 1 Y 1 2 1 1 2 1 2 1 2 1 X W 1 1 Y 1 2 1 1 2 1 2 1 2 1 1 1 1 1 1 2 1 2 1 2 1 W 1 1 Y 1 X 1 2 1 2 1 2 1 1 1 1 1 2 1 2 1 2 1 1 1 1 2 1 2 1 2 1 W 1 G 1 2 1 2 1 2 1 G 1 2 1 2 1 2 1 1 1 1 1 2 1 S indicates a cache block boundary at 0 mod 32 Snoops are broadcast to the CPU bus when a PCI burst crosses one of these boundaries W is a function of a 1 5 PCI clock snoop delay and memory arbitration delays If the CPU is accessing memory when the PCI agent begins the memory write burst the 660 waits until the CPU completes the current CPU access before allowing the PCI to memory write to proceed If the RAS watchdog timer has timed out the memory controller will precharge the RAS lines and if the refresh timer has timed out the memory controller will do a refresh operation W min 25 This occurs when the memory controller is idle and no refresh or RAS timeout occurs W typ 260r7 This occurs if the memory controller is the middle beat 3 of 4 of serving a CPU burst transfer when the PCI burst starts and no refresh or RAS timeout occurs max 23 This occurs when CPU1 is just starting a burst transfer to memory followed by 2 starting a burst transfer to memory after whi
222. ection 2 Signals Section 2 Signal Descriptions This section describes the connectivity of the 100 MHz PPC 603e Tables are used extensively for this purpose see Table 2 1 and the following paragraphs for an explana tion The terms asserted and active indicate that a signal is logically true regardless of the volt age level The terms negated inactive and deasserted mean that a signal is logically false The symbol at the end of a signal name indicates that the active or asserted state of the signal occurs with a low voltage level Otherwise the signal is active at a high voltage level Table 2 1 Example Signal Table Signal Name MCM Nodes Deseipion H08 PU bus address acknowledge The CPU bus target 660 or external CPU bus target asserts AACK to signal the end of the current address tenure 660 also asserts for one clock to signal the end of a broadcast snoop cycle AACK t is an input to the 664 when a CPU bus target claims the current transaction by means of L2 CLAIM is always an input to the CPU The Signal Name column contains the name of the signal In the Example Signal Table Table 2 1 the signal is shown The MCM column shows which pin s solder columns of the MCM connect to the signal The AACK net is connected to column R08 of the The Nodes columns show the internal MCM devices and pins to which the signal connects The left column
223. ection for direct attach ROM is provided through the ROM lockout BCR see Sec tion 6 3 2 ROM write lockout operations are compatible with the 650 bridge When a CPU busmaster writes any data to memory address FFFF FFF1h the 660 locks out all subsequent ROM writes until the 660 is reset In addition flash ROM devices can have the means to permanently lock out sectors by writing control sequences Flash ROM specifications contain details Note that the 660 treats any access from FFEO 0001 to FFFF with CPU A 31 1 as an access to FFFF FFF1 6 1 2 3 Data Flow In Little Endian Mode Figure 6 4 and Table 6 2 show the flow of CPU Data through the 660 to the ROM while the system is in little endian mode Note that the CPU Data bus is labeled in big endian order the PCI bus is labeled in little endian order and the 660 is labeled to match and the bit significance within the bytes is maintained G5220297 00 6 5 Section 6 ROM Preliminary PowerPc 60X CPU 660 Bridge Byte Lane N NW A 1 1 ON high med low MSB CPU Register Data bytes swapped CPU_A 29 1 selects Address munged CPU data bytes 4 7 Figure 6 4 ROM Data and Address Flow In Little Endian Mode When the CPU executes a store word instruction to FFFF FFFOh the contents of the source register appear on CPU DATA 32 63 CPU_ADDR 29 is 1 after the CPU munges the ad dress so the 660 selects CPU data byte lanes 4 through 7 as the source of the d
224. ed The system logic does not notify the CPU 8 2 5 4 PCI Address Bus Parity Error While PCI Target This error is generated when a parity error is detected during the address phase of a PCI access where the 660 is the PCI target of a access to system memory This error can be controlled by the indexed register set The mask is at register 04h bit 6 This error does not have an explicit status bit to indicate its occurrence However the fol lowing status bits are set e Register O6h bit 14 is set to indicate that PCI_SERR has been asserted This bit is cleared by writing a 1 to register O6h bit 14 BCRO4 b8 must be 1 to enable SERR assertion due to PCI bus address parity errors e Register bit 11 is set to indicate signalled target abort if the cycle was target aborted This bit is cleared by writing a 1 to register O6h bit 11 e Register O6h bit 15 is set to indicate a PCI bus parity error regardless of the state of the mask at register O4h bit 6 Note that this bit is set by all types of PCI bus parity errors This bit is cleared by writing a 1 to register O6h bit 15 Register C7h bit 4 is set to indicate an error on a PCI cycle The PCI address is saved in register C8h The PCI control is saved in register C7h This error cannot be controlled by means of the 650 compatible register set G5220297 00 8 11 a Section 8 Exceptions Preliminary PowerPc 8 2 5 5 PCI Bus Data Parity Error While PCI Target This err
225. ed in register C8h The PCI control is saved in register C7h This error can be reset by writing a 1 to register C1h bit 3 This error cannot be controlled by means of the 650 compatible register set 8 2 7 SERR I O Channel Check and NMI Errors The PCI bus defines a signal called SERR which any agent can pulse This signal is to report error events within the devices not bus parity errors The signal is wired to the ISA bus bridge on the planar The ISA bus signal IOCHCK is also wired to the ISA bridge If ei ther of these lines activate the ISA bridge asserts NMI to the 660 unless the condition is masked by a register within the ISA bridge The NMI signal causes the 660 to generate an interrupt to the CPU and to assert MCP to the CPU The ISA bridge contains status regis ters to identify the NMI source Software may interrogate the ISA bridge and other devices to determine the source of the error 8 2 7 1 Asserted Error This error is generated when the NMI input is sampled asserted by the 660 External logic can assert this signal for any type of catastrophic error it detects The external logic should also assert this signal if it detects PCI SERR asserted The 660 does not treat REQ as an interrupt but as an error indicator NMI is handled somewhat differently from the bus related error sources e There are no 660 BCRs associated with NMI REQ The external logic that asserted NMI to the 660 provides mask and status
226. ed until the lock is released The bridge generates a flush sector snoop cycle on the CPU bus when a PCI busmaster sets the PCI lock The flush sector snoop cycle causes the L1 and L2 caches to invalidate the locked block which prevents cache hits on accesses to locked blocks If the L1 contains modified data the PCI cycle is retried and the modified data is pushed out to memory Note The 60X processors do not have bus locking functions Instead they use the oad reserve and store conditionalinstructions Iwarx and stwcx to implement exclusive access To work with the lwarx and stwcx instructions the 660 generates a flush sector operation to the CPU in response to the PCI read that begins a PCI lock 3 6 CPU to BCR Transfers The 660 can be extensively programmed by means of the Bridge Control Registers BCR See the 660 User s Manual for a description of the operation and programming of the 660 BCRs G5220297 00 3 9 A Section 3 CPU amp L2 Preliminary PowerPc 3 7 L2 The contains an L2 cache controller located inside the 660 512K of synchronous SRAM and a 16K x 15 synchronous tagRAM This forms a unified write thru direct mapped look aside level 2 cache L2 that caches CPU memory space from 0 to 1G The L2 directory contains 8K entries with one tag per entry The cache line block size is 32 bytes the PowerPC 60X coherence unit The L2 maintains coherence for the 32 byte block and neither operates on
227. egister C5h bit This error cannot be controlled by means of the 650 compatible register set 8 2 4 CPU to PCI Bus Transaction Errors 8 2 4 1 PCI Bus Data Parity Error While PCI Master This error is generated when a PCI bus data parity error is detected during a CPU to PCI transaction The 660 checks parity during read cycles and samples PCI PERR5t during write cycles The bridge asserts PCI if a parity error is detected on a read cycle The PCI bus uses even parity which means that an even number of bits including the parity bit are driven high This error can be controlled by the indexed register set The mask is at register 04h bit 6 If an error is detected the status bit at register O6h bit 8 is set Register C7h bit 4 is cleared G5220297 00 8 9 a Section 8 Exceptions Preliminary PowerPc to indicate an error on a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 This error can be reset by writing a 1 to register O6h bit 8 When this error is detected the status bit at register 06h bit 15h is set regardless of the state of the mask at register 04h bit 6 The status bit at register O6h bit 15 is set by all types of PCI bus parity errors This bit is cleared by writing a 1 to register O6h bit 15 This error cannot be controlled by means of the 650 compatible register set Unless masked the 660 will report this
228. emory read request by pulling all posted writes through the bridge before completing the read In other words when the PCI agent initiates the read polls the flag the bridge is to retry or delay the read until the posted CPU to PCI memory write the data set transfer has completed This has the effect of pulling the writes through the bridge before the read is executed The 660 does not implement this function G5220297 00 5 13 Section 5 PCI Bus Preliminary PowerPc Note that PCI devices such as SCSI Ethernet and Token Ring adaptors that poll the flag in system memory typically also consume the data set by initiating PCI to system memory reads These devices are not affected Also PCI devices such as graphics adaptors and busmasters that receive the data set as a PCI memory target typically receive indication that the data is ready the flag as a PCI or PCI memory target they do not poll system memory for the flag These devices are also not affected 5 5 2 2 Solution 1 Add a dummy CPU to PCI write Design the device drivers to cause the CPU BIU to execute an access to the PCI bus of any type after the data set is written posted into the 660 by the CPU write to the PCI target and before the CPU BIU executes the write that sets the flag in system memory This solution forces the data set write to complete on the PCI bus before the flag write is initiated on the CPU bus Remember to insert eieio instr
229. er PCI AD 23 0 to the ROM address pins The ROM drives back the data on PCI AD 31 24 where it is received by the 663 This ROM read discussion assumes that the system is in big endian mode For the effects of little endian mode operation on ROM reads see Section 6 1 1 3 6 1 1 1 ROM Read Sequence Figure 6 2 is a timing diagram of a CPU to ROM read transaction This case assumes that the PCI bus is parked on the CPU so that the 660 has a valid PCI bus grant when the CPU starts the CPU bus transfer Initially the CPU drives the address and address attributes onto the CPU bus and asserts TS The 660 decodes the CPU transfer as a ROM read transaction It is possible for TS to be asserted across either a rising or falling edge of PCI CLK The 660 must only assert and negate PCI bus signals on the rising edge of PCI CLK so if TS is asserted across a rising edge of PCI CLK the 660 waits one CPU CLK to synchronize to the PCI bus The 660 initiates a BCR transaction by asserting PCI on the rising edge of PCI Note that the 660 is driving PCI AD 23 0 with the ROM address of byte 0 of the 8 byte aligned double word The 660 leaves PCI AD 31 24 tri stated and asserts ROM OEZ to enable the ROM to drive the data onto these bits On the next PCI CLK the 660 negates PCI FRAMEZ and asserts PCI_IRDY The ROM drives the requested data onto its data pins across PCI AD 31 24 and into the 660 Seven PCI CLKs after the 660 asse
230. er Related BCRs Information on these registers is contained in the 660 Bridge Manual Bridge Control Register f RW G5220297 00 6 15 Section 6 ROM Preliminary PowerPc 6 16 G5220297 00 PowerPc Preliminary Section 7 Clocks The 100 MHz PPC 603e provides a separate clock signal for each CPU bus and PCI bus agent in the system The clock signals are generated by a Motorola MPC970 The MPC970 inputs are brought off of the to allow maximum programming flexibility See the data sheet for more information on MPC970 programming capabilities and character istics See Figure 7 1 Control PCI Clock Inputs Consumers 16 5 MHz Crystal Clocks CPU Clock Consumers PCI Clock Consumer Figure 7 1 MCM Clocks The example planar configures the MPC970 to produce 8 CPU bus clocks all of which are consumed by the MCM components When required additional CPU bus clocks can be generated using a zero delay clock repeater such as the Motorola MPC930 PLL using one of the supplied CPU clocks as the seed clock The planar also configures the MPC970 to produce seven PCI bus clocks two of which are consumed by the MCM components The other PCI clocks are available for use on the p
231. er the up or down arrow is pressed Changing the date or time is immediate and is not affected by either the Save and Exit or Exit Without Saving options on the main menu PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Set Date and Time Set Date 03 01 94 Set Time 11 30 00 Go to Previous Menu Press to select item Enter data at cursor Figure 10 13 Set Date and Time Screen 10 14 G5220297 00 PowerPc Preliminary Section 10 Firmware 10 4 3 2 Run a Program The Run a Program option on the main menu loads and executes a program from a FAT DOS disk or from a CD ROM in 15 9660 format The program is loaded at location 0x00400000 4 MB and control is passed with a branch to the first address All boot devices specified in the Boot Devices Menu will be searched in order for FAT and CD ROM file systems and the first matching file on a boot device will be loaded The Run a Program screen is shown in Figure 10 14 To run a program enter the file name in the Specify Program Filename field and select the Run the Program option PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Run a Program Specify Program Filename Run the Program Go to Previous Menu Press to select item Enter data at cursor Figure 10 14 Run a Program Screen G5220297 00 10 15 p Section 1
232. error is detected perform the following steps 1 Set status bit indicating error type 2 Set status bit indicating error during PCI cycle 3 Save PCI address and control bus values 4 Report error to the PCI If the error is a PCI bus data parity error then report by means of PCI If the error is not a data parity error then report by means of PCI SERRit 5 If the PCI cycle is still active not the last data phase then target abort the cycle The 660 can be enabled to report PCI bus data parity errors with PCI SERR3 This method should only used if it is determined that PCI is not supported by some or all of the PCI masters in the system 8 2 2 3 PCI Bus Data Parity Errors While the 660 is the PCI busmaster during CPU to PCI transactions e During reads the 660 monitors the PCI AD and and PCI PAR lines to de tect data parity errors during the data phases If an error is detected the 660 asserts PCI Unless masked the 660 will report the error to the CPU bus using This error does not cause the 660 to alter the PCI transaction in any way e During writes the 660 monitors PCI PERR5Z to detect data parity errors that are de tected by the target Unless masked the 660 will report the error to the CPU bus using MCP This error does not cause the 660 to alter the PCI transaction in any way G5220297 00 Hin In PowerPc Preliminary Section 8 Except
233. ess register is held Note that some operating systems intentionally access unused addresses to determine what devices are located on the PCI bus These operating systems do not expect an error to be generated by these accesses When using such an operating system it is necessary to leave this error masked This error can be controlled by the indexed register set The mask is at register C4h bit 4 If an error is detected the status bit at register O6h bit 13 is set Register C7h bit 4 is cleared to indicate an error on a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 This error can be reset by writing a 1 to register O6h bit 13 This error cannot be controlled by means of the 650 compatible register set The 660 also checks for bus hung conditions If a CPU to PCI cycle does not terminate with in approximately 60 usec after the PCI is owned by the CPU the cycle is terminated with This is true for all CPU to PCI transaction types except configuration transactions This feature may be disabled via a 660 control register In the case of configuration cycles that do not receive DEVSEL no device present at that address the PCI cycle is master aborted and normal response is returned 8 10 G5220297 00 PowerPc Preliminary Section 8 Exceptions Write data is thrown away and all 1 s are returned on read cycles No error regi
234. evious memory access it is a page hit the row address currently latched into the DRAM is considered valid and the bridge accesses the DRAM using CAS cycles On page mis ses the bridge latches the new row address into the DRAMs before it accesses the DRAM using CAS cycles 4 14 G5220297 00 PowerPc Preliminary Section 4 DRAM On CPU to memory bursts only the address of the first beat of the burst is checked for page hits because the following three beats are always within the same memory page On PCI to memory bursts the address of each data phase of the burst is checked for page hits 4 2 1 13 CPU to Memory Access Pipelining CPU to memory accesses are pipelined with the result that during a series of back to back CPU to memory accesses all transfers following the initial transfer are faster The informa tion from the address tenure of the subsequent transfers is processed by the bridge while the data tenure of the preceding transfer is still active Considering a series of CPU to memory read transfers using 60ns EDO DRAM the initial burst requires 10 3 3 3 CPU clocks If this transfer is followed immediately back to back by another CPU to memory transfer the required cycle time is 5 3 3 3 As long as the transfers are back to back they are pipelined and can be retired at this pipelined rate 4 2 1 14 Extended Data Out EDO DRAM The 660 is designed to support hyper page mode DRAM sometimes called extended data out
235. f X and Y and is equal to the longer of X and Y G5220297 00 5 7 Section 5 PCI Bus Preliminary PowerPc 5 2 8 PCI to Memory Reads During PCI to memory burst reads the 660 performs memory pre fetching when it initiates cycles to the memory controller The pre fetching involves loading or pre loading 32 bytes from the memory for eight 4 byte PCI read cycles Pre fetching is only done within the same cache line Minimum initial read access time from 70ns DRAM when the CPU bus is 66MHz and the PCI bus is 33MHz is 8 1 1 1 1 1 1 1 PCI clocks for 4 4 4 4 4 4 4 4 bytes of data 15 PCI clocks for 32 bytes of data Subsequent data phases of the same burst are generally serv iced at 7 1 1 1 1 1 1 1 14 PCI clocks for 32 bytes of data giving a peak burst read rate of 32 bytes in 14 PCI clocks or about 73MBps with a 33MHz PCI clock This scenario holds while the RAS timer 10us typical does not time out and no refresh is requested 15 5 typ 5 2 8 1 Detailed Read Burst Sequence Timing The actual detailed read sequence is affected by several factors such as the speed of the DRAM refresh requests memory arbitration delays page and or bank misses and cache boundary alignment Table 5 6 shows the details of the various sequences that a PCI to memory burst read will experience depending on the address relative to a cache block boundary of the first data phase of the transaction The starting address of the numbering sequence shown o
236. f this Agreement Furthermore you accept sole responsibility for your decision to select and use the for attainment or non attainment of any schedule performance cost reliability maintainability quality manufacturability or the like requirements or goals self imposed by you or accepted by you from others concerning any product s or portion s of product s orfor any delays costs penalties charges damages expenses claims orthe like resulting from such non attain ment where use of all or any part of the MOM is involved GENERAL In the event there is a conflict between the terms of this Agreement and the terms printed or stamped on any item or any ambiguities with respectthereto including documentation contained in the 100 MHz PPC 603e MOM the terms ofthis Agreement controlto the extent IBM is afforded greater protection thereby IBM may terminate this Agreement if you fail to comply with the terms and conditions of this Agree ment Upon termination of this Agreement you must destroy all copies of the software and documentation You are responsible for payment ofany taxes including personal property taxes resulting from this Agreement Neither party may bring an action hereunder regardless of form more than one 1 year after the cause of the action arose If you acquired the in the United States this Agreement is governed bythe laws of the State of New York In the event of litigations trial shall be in New York wit
237. for 10x10 thru 12x12 DRAMs 1 24 The PCI Interface The allows CPU to PCI access and PCI busmaster to system memory access with snooping and handles all PCI related system memory and cache coherency issues The supplies 32 bit PCI host bridge interface that is Compliant with the PCI Specification revisions 2 0 and 2 1 see Section 5 5 3 3v and 5v signalling environment compliant G5220297 00 1 3 p Section 1 Introduction Preliminary Power Operates to at 1 2 of the CPU bus frequency e Supports a tertiary bus bridge including support for ISA masters Allows system memory block locking by PCI busmasters Supports type 0 and type 1 PCI configuration cycles 1 2 5 System Clocks The uses a Motorola MPC970 clock generator to provide the clocks required by the MCM components and six clocks for system use A 16 5 MHz quartz crystal seed clock provided by the user is used as an input to the clock generator It then produces the system and PCI clocks 1 2 6 Performance Minimum Cycle Times For Pipelined CPU to Memory Transfers at 66 MHz Page DRAM 70ns Pipelined 4 4 4 4 3 3 4 4 EDO DRAM 60ns Pipelined 5 3 3 3 3 3 3 3 Typical PCI to Memory Performance at 66 MHz CPU Clock and 33MHz PCI Clock 8 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 Write 5 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1 3 1 1 1
238. ftware means the original and all whole or partial copies of it including modified copies or portions merged into other programs IBM retains title to the software IBM owns or has licensed from the owner copyrights to the software provided under this agreement The terms of this Agreement apply to all of the hardware software and documentation provided to you as part of the 100 MHz PPC 603e MCM With regard to the software provided hereunder it is understood and agreed that you intend to use the software solely for the purpose of designing PowerPC compatible products testing your designs and making your own independent determination of whether you wish to eventually manufacture PowerPC compatible products commercially In accordance with this understanding IBM hereby grants you the rights to a use run and copy the software but only make such number of copies and run on such number of machines as are reasonably necessary for the purpose of designing PowerPC compatible products and testing such designs and b copy the software for the purpose of making one archival or backup copy With regard to any copy made in accordance with the foregoing license you must reproduce any copyright notice appearing thereon With regard to the software provided hereunder you may not a use copy modify or merge the software except as provided in this license b reverse assemble or reverse compile it or c sell sublicense rent lease assign or otherwise t
239. gnal Descriptions 2 13 Pin List With Net Names Nodes 2 14 TT 0 3 Transfer Type Decoding by 660 3 3 660 Address Mapping of CPU Bus Transactions 3 4 CPU to PCI Configuration Mapping 3 9 L2 Cache Responses to CPU Bus Cycles 3 10 L2 Operations for PCI to Memory Transactions 603 Mode 3 1 Other L2 Related 3 11 Memory Timing Parameters 4 3 Page Mode DRAM Aggressive Timing Summary 1 4 11 EDO DRAM Aggressive Timing Summary 1 4 12 Page Mode DRAM Conservative Timing Summary 1 4 13 EDO DRAM Conservative Timing Summary 1 4 14 Supported SIMM Topologies 4 16 Row Addressing CPU Addressing 4 17 Column Addressing CPU Addressing 4 17 Row Addressing PCI Addressing 4 17 Column Addressing PCI Addressing 4 17 Example Memory Bank Addressing Mode Configuration 4 21 Example Memory Bank Starting and Ending Address Configuration 4 23 Bridge Response to Various PCI Write Data Phases 4 28 Bridge Response to Best Case PCI Write Burst 4 28 Bridge Response to Case 2 PCI Write 51
240. gt 0 2ns 0 5ns 3 Best Case Process Temperature 8 Vpp gt 0 1ns 0 3ns The worst practical case occurs while the 664 is at Case 2 provides 5ns difference and the 663 is at Case 1 requires 1 8ns difference This re quires that a minimum delay of 1 3ns be added to the CPU RDL OPEN signal A delay of 2 4ns is recommended to allow a conservative margin of error Delay RC 200Q 12pf 2 4ns Note that this assumes the OPEN and MEM RD SMPL nets are both about three inches long and that the resister is close to the 664 A different resister value or an R C combination may be required if the length or capaci tance of the two nets are significantly different or if the resister placement differs significantly CRS C2PWXS A29 660 CPU Read Select CPU to PCI Write Crossover Select signal When the CPU read latch is sampling data this signal controls the CPU read multiplexer When the CPU to PCI write latch is sampling data this signal controls the CPU to PCI write crossover Pull down with a 1K nominal resistor to select during reset direct attach ROM DUAL CTRL REF 2 660 Control Signal Mux Select signal For 663 inputs that have two func tions this signal selects the function This signal is generated by dividing CPU CLK by two This is a useful first point to check when debugging a dead system U2 2 660 ECC Select Little Endian Select signal This signal indicates use of 03 149 ECC or byte when DUAL C
241. guration utility The two options are Save and Exit Exit without Saving Saves any changes made in the Configure Devices and Set Boot Devices screens and restarts the system Proceeds with the boot process as if the configuration utility had not been entered Any changes made in Configure De vices or Set Boot Devices are lost 10 4 4 Default Configuration Values When the PowerPC 603 604 reference board is shipped from the factory it has the follow ing default configuration Console Device Serial Port 1 Serial Port 2 Boot Devices S3 Video Keyboard 9600 Baud 9600 Baud Device 1 Floppy 1 Device 2 SCSI ID 6 Device 3 IDE Drive 0 These default values also take effect whenever the system configuration in system nonvol atile RAM becomes corrupted G5220297 00 10 17 Section 10 Firmware Preliminary Power 10 18 G5220297 00 PowerPc Preliminary Section 11 Endian Section 11 Endian Mode Considerations Data represented in memory or media storage is said to be in big endian BE order when the most significant byte is stored at the lowest numbered address and less significant by tes are at successively higher numbered addresses Data is
242. h by asserting MCP to the CPU bus for 2 CPU clocks The 660 does not itself take any other action All current and pipelined CPU and PCI bus transactions are unaffected The state of the memory controller is unaffected The asser tion of MCP does not cause any change in the behavior or state of the 660 8 2 8 2 Error Reporting With CPU bus related errors that are detected while the CPU is running a cycle that can be termi nated immediately are reported using Errors reported in this way are a direct result ofthe CPU transfer that is currently in progress For example when the 660 detects a trans fer size error it terminates the CPU transfer with instead of with The 660 reports an error with TEA by asserting TEA to the CPU in accordance with the PowerPC bus protocol The data beat on which TEA is asserted becomes the final data beat The 660 does not itself take any other action All other current and pipelined CPU and PCI bus transactions are unaffected The state of the memory controller is unaffected The assertion of does not cause any other change in the behavior or state of the 660 G5220297 00 8 15 Section 8 Exceptions Preliminary PowerPc 8 2 8 3 Error Reporting With PCI SERR Z The 660 asserts PCI_SERR for one PCI clock when a non data parity error system error is detected and the 660 is a PCI target As is the case with the other error reporting signals the 660 may
243. h interpret data structures in the memory require that their control data be arranged in LE order even in BE mode For example SCSI scripts in memory must always be arranged in LE order because that is what the device expects e Devices such as video may require the bytes to be swapped unless these devices have byte swap capability 11 18 G5220297 00 Power Preliminary Section 12 Electromechanical Section 12 Electromechanical 12 1 MCM Electrical The electrical characteristics of the MCM 10 are obtained by reference to the electrical characteristics of the individual devices to which a given 10 is connected The ratings of the 10 including the package effects are better than or equal to the ratings of the indi vidual devices Please refer to the appropriate sections in the following documents 27 82660 User s Manual PowerPC 603e PID6 603e Hardware Specifications TI 74LVT16245 Data Sheet 041814 SRAM Data Sheet IDT IDT71216 TagRAM Data Sheet Motorola MPC970 Data Sheet The conditions under which the MCM operates must not exceed the Absolute Maximum Ratings of any of the individual devices The AC and DC Electrical Specifications and Timing Specifications of each IO is affected by the combined characteristics of the devices that are attached to that net For example the characteristics of the PCI AD lines are the sum of the characteristics of the 663 and the 664
244. he ROM attaches directly to the 660 using the PCI AD lines This mode is required when using the Intel SIO ISA bridge as the example planar does be cause the SIO does not support mapping of the ROM to the ISA bus The direct attach mode also supports ROM device writes and write protect commands The example planar uses an AMD AM29F040 120 Flash ROM to contain the POST and boot code This is a 512K device located at 4G 2M It is recommended that Vital Product Data VPD such as the motherboard speed and native I O complement be programmed into in this device It is possible to program the Flash before or during the manufacturing process The other ROM access method remote ROM mode see section 6 2 attaches the ROM device to an external PCI agent which supports the PowerPC Reference Platform ROM space map and access protocol CPU busmaster transfers to ROM space are forwarded to the PCI bus and claimed by the PCI agent which supplies the ROM device data This PCI device is typically a PCI to ISA bridge The ROM device attaches to the ISA bridge through the ISA bus lines thereby saving a PCI bus load The 660 supplies write protect capability in this mode At power on the 603 604 CPU comes up in BE Mode with the L1 cache disabled and be gins fetching instructions using 8 byte single beat reads at address FFFO 0100 4G 1M 100h The example planar logic also resets to BE mode 6 1 Direct Attach ROM Mode The ROM device
245. he memory flight time The calculations below ignore the factors of clock skew and flight time This section discusses the timing calculations that are appropriate to 660 memory control ler design The timing recommendations in this section apply to all MCM configurations Because the MCM uses synchronous SRAM it is not affected by the 660 DRAM special case timing restrictions Each of the nine equations below lists a register or register bits that govern a memory timing parameter An equation is then provided for calculating the required value based on the timing requirements of the memory and the 660 MTR1 1 0 refers to Memory Timing Register 1 bits 1 0 See Figure 4 1 and Table 4 1 1 MTR1 1 0 RAS precharge RP The critical path that determines the RAS precharge requirement is RAS rising to RAS falling The minimum RAS pre charge time supplied by the 660 must exceed the minimum precharge time re quired by the DRAM Make RAS precharge RP gt DRAM min RAS precharge 2 MTR1 4 2 RAS pulse width RPW The critical path that determines the RAS pulse width requirement is RAS falling to RAS rising The minimum RAS pulse width supplied by the 660 must exceed the minimum RAS pulse width required by the DRAM plus 5ns Make RAS pulse width RPW gt Tras min DRAM min RAS pulse width PING SE pulse width shrinks note 1 MTR2 6 5 CAS precharge CP The
246. hich is generated by the 660 as itis comparing the 8 data bytes to the check byte This syndrome contains the results of the comparison as shown in Table 4 18 where ne means that no error has been detected cbx means that check bit x is inverted a single bit error dx means that data bit x is inverted a single bit error blank means that a multiple bit error has occurred Based on the information in the syndrome the 660 corrects all single bit errors and signals an error to the requesting agent on multiple bit errors Table 4 18 Syndrome Decode 0 1 0 1 0 0 0 1 1 0 0 5 Poo S7 S6 S5 54 o o b H Q A d43 Q jeep e ss fef lele pp oro A Q w w d36 ai E as a p 45 DRAM Refresh The memory controller provides DRAM refresh logic for system memory The memory con troller supports CAS before RAS refresh only which provides lower power consumption and lower noise generation than RAS only refresh In this refresh mode MA 11 0 are not required Refresh of the odd banks of memory is staggered from the refresh of the even banks of memory to further reduce noise see Figure 4 9
247. hout a jury If you acquired the MCM in Canada this Agreementis governed by the laws ofthe Province of Ontario otherwise this Agreementis governed by the laws ofthe country in which you acquired the obligations and duties which by their nature survive termination or expiration of this Agreement shall remain in effect beyond termination or expiration of this Agreement and shall bind IBM you and your successors and assigns If any section or paragraph ofthis Agreementis found by competent authority to be invalid illegal or unenforceable in any respectfor any reason the validity legality and enforceability of any such section or paragraph in every other respect and the remainder of this Agreement shall continue ineffectsolongasitstillexpressesthe intent ofthe parties Ifthe intent of the parties cannotbe preserved the parties will attemptto renegoti ate this Agreement and failing renegotiation this Agreement will then be terminated The headings in this Agreement shall not affect the meaning or interpretation of this Agreement in any way No failure by IBM in exercising any right power or remedy under this Agreement shall serve as a waiver of any such right power or remedy Neither this Agreement nor any activities hereunder will impair any right of IBM to develop manufacture use or market directly or indirectly alone or with others any products or services competitive with those offered or to be offered by you nor will this Agree
248. ich has choices to display and change the default state of the reference board on boot Each menu item is discussed in the following sections PowerPC 604 Reference Board System Firmware C Copyright 1994 IBM Corp 11 Rights Reserved System Configuration Menu System Information Configure I O Devices View SCSI Devices Set Boot Devices Set Date and Time Previous Menu Press Tl to select item Press Enter to perform action Figure 10 8 System Configuration Menu G5220297 00 10 9 Section 10 Firmware System Information The system configuration option shows the hardware configuration of the system at power up including processor installed options and firmware revision level A sample screen is shown in Figure 10 9 Preliminary P2werPc PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved System Configuration System Processor PowerPC 604 Installed Memory 8 MB Second Level Cache Not Installed Upgrade Processor Not Installed Boot Firmware Revision 1 0 Go to Previous Menu Press to select item Press Enter to perform action Figure 10 9 System Information Screen 10 10 G5220297 00 PowerPc Preliminary Section 10 Firmware Configure I O Devices The configure I O devices option allows the customization of system I O ports and the sys tem console The menu is shown in Figure 10 10 Options are highlighted by
249. ied drawing of the construction of the MCM The individual devices are mounted to the ceramic substrate which is mounted to the circuit board by sol der columns The cap covers the devices and the top of the substrate and is filled with thermal grease The cap is non hermetically sealed to the substrate As shown in Figure 12 3 the major heat flow path is from the devices to the thermal grease to the aluminum cap and to ambient A heat sink can be attached to the cap if required Thermal Grease Substrate VU UUUUUUUUUUUUUUU 00010 Solder Columns Figure 12 2 MCM Thermal Paths Heat Flow for Rj c Actual Heat Flow 14 Ceramic Substrate Figure 12 3 MCM Heat Flows 12 2 1 Chip Thermal Requirements Table 12 2 shows many of the thermal specifications of the chips in the MCM The values given for non IBM products are superceded by any values found in the manufacturers data sheets At a typical power dissipation the difference between the temperature of the center of the chip and the temperature of the center of the MCM cap was measured see Figure 12 3 The thermal resistance values from chip junction to MCM cap Rj c shown in Table 12 2 were derived from these measurements R j c T chip T cap Power chip and do not change significantly over the operating range of the Rj c describes the thermal resistance along the path from the center of the device to the cente
250. ies due to the events of rows 7 and 8 Rows 10 through 12 show the effect of a burst that ends at a low word location The total performance impact from this burst is to add 12 PCI clocks to the transaction time Note that the performance penalty for single data phase PCI writes is three additional PCI clocks whether the destination is the high word or the low word 4 4 1 11 Check Bit Calculation The 660 generates the check bits based on Table 4 17 which is shown using little endian bit numbering Table 4 17 Check Bit Calculation Data Bits CB x XOR of Data Bits 0 is LSb X 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 33 34 35 39 41 42 43 47 49 50 51 55 57 58 59 63 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 32 34 35 38 40 42 43 46 48 50 51 54 56 58 59 62 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 37 40 41 43 45 48 49 51 53 56 57 59 61 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 32 33 34 36 40 41 42 44 48 49 50 52 56 57 58 60 1 2 3 7 9 10 11 15 17 18 19 23 25 26 27 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 2 3 6 8 10 11 14 16 18 19 22 24 26 27 30 40 41 42 43 44 45 46 47 56 57 58 59 60 61 62 63 6 0 1 3 5 8 9 11 13 16 17 19 21 24 25 27 29 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 2 4 8 9 10 12 16 17 18 20 24 25 26 28 32 33 34 35 36 37 38 39 48 49 50 51 52 53 54 55 G5220297 00 4 29 Section 4 DRAM Preliminary PowerPc 4 4 1 12 Syndrome Decode The syndrome consists of an 8 bit quantity w
251. ilar to those generated by x86 to bridges The interrupt controller eg SIO then claims the transaction and supplies the single byte interrupt vector on PCI byte lane 0 The 660 then returns the vector to the CPU on the correct byte lane There is no physical interrupt vector BCR in the bridge Other PCI busmasters can initiate interrupt acknowledge transactions 8 1 4 NMI REQ The 660 considers the REQ input to be an error indicator Note that in Figure 8 1 there is no logical connection between NMI REQ and INT CPU except through the error handling logic See section 8 2 7 1 for more information on NMI REQ 8 1 5 Interrupt Handling INT_CPU ISA INT_REQ Interrupts PCI Interrupts CPU Bus PCI Bus Figure 8 2 Interrupt Handling As shown in Figure 8 2 the 100 MHz PPC 603e MOM interrupts are routed to the interrupt controller located inside the ISA bridge When a device signals an interrupt which is not masked in the interrupt controller then for error sources the interrupt controller is pro 8 2 5220297 00 PowerPc Preliminary Section 8 Exceptions grammed to assert NMI REQ If the input to the interrupt controller signals an interrupt then 1 The ISA bridge asserts INT REQ to the 660 2 The 660 asserts INT CPUZ to the CPU 3 The CPU recognizes the interrupt signal INT immediately as soon as the MSR EE interrupt enable bit in the CPU is set to 1 saves its state and then takes a
252. ingle beat CPU to memory read transfers and to the first beat of CPU to memory burst read transfers The other beats of the burst are unaffected During the extra CPU CLK the 663 holds the data while checking and if necessary correcting it The 660 does not use the DRTRY function even while in ECC mode In no DRTRY mode during memory reads the 604 uses the data bus data internally as soon as it samples active The 660 supports this mode by presenting correct ed data to the before driving valid The Bridge does not speculatively present data to the CPU using and then assert DRTRY if there is a data error By allowing the 604 to run no DRTRY node the 660 enables the 604 to use data from the L2 cache at the full speed of the L2 cache without requiring the 604 to insert an additional internal to the 604 one CPU clock delay on reads In DRTRY mode during memory reads the 604 holds the data internally for one CPU clock after sampling active This delay is inserted by the 604 to allow DRTRY to be sampled before the data is used Thus during CPU to memory reads in ECC mode while a 604 is in DRTRY mode the 660 inserts a one CPU clock delay to check correct the data and then the 604 adds a one CPU clock delay to check for DRTRY Thus two CPU clocks are added to single beat CPU to memory read transfers and to the first beat of CPU to memory burst read transfers 4 4 1 8 CPU to Memory Write in ECC Mode
253. ion G5220297 00 6 3 Section 6 ROM Preliminary PowerPc On a single beat transfer the CPU asserts and negates concurrently with For a burst transfer the 660 asserts for four CPU to return four identical double words to the CPU This is the only difference between single beat and burst ROM reads Also note that PCI DEVSEL Z PCI TRDY Z PCI 5 and ROM WEZ are negated throughout the transaction Table 6 1 ROM Read Data and Address Flow ROM ROMDataByte ROM Address ROM Data CPU DATA 0 63 CPU DATA 0 63 Access PCI AD 23 0 PCI AD 31 24 After Shift After Shift LE Mode xxxxxon edu gt m oxxom om _ 6 1 1 2 Address Transfer Size and Alignment During ROM reads system ROM is linear mapped to CPU memory space from 4G 2M to 4G FFEO 0000h to FFFF FFFFh This address range is translated onto PCI AD 23 0 as 0 to 2M 0000 0000h to 001F FFFFh Since the CPU begins fetching instructions at FFFO 0100h after a reset the most convenient way to use a 512K device as system ROM with the CPU is to use it from 4G 512K to 4G Connecting PCI AD 18 0 to ROM A 18 0 with no translation implements this With this connection the system ROM is aligned with 4G 2M but with alias addresses every 51
254. ions While the 660 is the PCI target during PCI to memory transactions e During reads the 660 does not monitor PCI and so will not detect a data parity error e During writes the 660 monitors the PCI AD and and PCI PAR lines to de tect data parity errors during the data phases If an error is detected the 660 asserts PCI PERR The 660 will not report the error to the CPU bus This error does not cause the 660 to alter the PCI transaction in any way 8 2 3 CPU Bus Transaction Errors 8 2 3 1 CPU Bus Transfer Type or Size Error This error is generated when the CPU generates a bus operation that is not supported by the 660 see Table 8 2 An error is not generated if the cycle is claimed by another CPU device CPU BUS CLAIMZ asserted Table 8 2 Invalid CPU Bus Operations Only the following transfer sizes are supported Other transfer sizes are not supported e 1 byte to 8 byte single beat reads or writes to memory within an 8 byte boundary e Burst reads or writes to memory 32 bytes aligned to double word e 1 byte to 4 byte single beat reads or writes to the PCI bus that do not cross a 4 byte boundary e 8 byte single beat writes to the PCI bus within an 8 byte boundary e All accesses not to memory or PCI with sizes of 1 to 4 bytes within a 4 byte boundary e ROM reads support the same sizes as memory Transfer type and size errors can be controlled by the indexed register set The mask is at registe
255. ire address space Each 4K page in the 8M CPU bus address range maps to 32 bytes in PCI space Registers and memory do not occupy the entire address space Accesses to unoccupied addresses result all one bits on reads and no ops on writes A memory read of BFFF FFFOh generates an interrupt acknowledge transaction on the PCI bus QV v cs 3 3 1 Address Mapping for Non Contiguous Figure 3 1 shows the address mapping that the 660 performs in non contiguous mode The map type register address 8000 0850h and the bridge chip set options 1 register in dex BAh control the selection of contiguous and non contiguous In non contiguous G5220297 00 3 4 Power Preliminary Section 3 CPU amp L2 mode the 8M address space of the 60X bus is compressed into 64K of PCI address space and the 60X CPU cannot create PCI addresses from 64K to 8M In non contiguous I O mode the 660 partitions the address space so that each 4K page is remapped into a 32 byte section of the 0 to 64K ISA port address space so that 60X CPU protection attributes can be assigned to any of the 4K pages This provides a flexible mech anism to lock the I O address space from change by user state code This partitioning spreads the ISA address locations over 8M of CPU address space In non contiguous mode the first 32 bytes of a 4K page are mapped to a 32 byte space in the PCI address space The remainder of the a
256. irst of the ROM code must be BE code It is beyond the scope of this documentto define how the system will know to switch to LE mode however great care must be made during the switch in order to synchronize the internal and external mode bits to flush all caches and to avoid executing extraneous code The following process switches the system from BE to LE mode when used in this system Disable L1 caching Disable L2 caching Flush all system caches Turn off interrupts immediately after a timer tick so no timer interrupts will occur dur ing the next set of cycles Mask all interrupts Bo mc 11 16 5220297 00 PowerPc Preliminary Section 11 Endian Set the CPU state and the motherboard to LE see Figure 11 8 Note that CPU is now in LE mode All instructions must be in LE order Put interrupt handlers and CPU data structures in LE format Enable caches Enable Interrupts 0 Start the LE operating system initialization cS OU Figure 11 8 shows the instruction stream to switch endian modes X mfspr R2 1008 Load the HDO register Instructions to set the Little Endian bit in R2 0 sync Sync Sync mtspr 1008 R2 Moves to HIDO register sync sync sync sync Store to external Endian control port X8000 0092 The above instruction must be on a double word boundary So the following instruction is executed first due to pipeline 24 eieio To this point all instructions are in Big Endian format
257. is will assert IGN PCI AD31 during a PCI transaction only while either the 660 or the SIO is the initiator and the 660 knows when it is the initiator The required connectivity of IGN PCI AD31 prevents the SIO from initiating peer to peer PCI memory transactions in the O to 2G range ISA masters cannot access any PCI memory The SIO is allowed to initiate PCI memory transactions from 2G to 4G and other PCI transaction types I O amp etc 5 4 G5220297 00 PowerPc Preliminary Section 5 PCI Bus 5 2 PCI Transaction Details Further details of the MCM implementation of various PCI transactions are found in the 660 User s Manual 5 2 1 Memory Access Range and Limitations PCI memory reads and writes by PCI busmasters are decoded by the 660 to determine if they access system memory PCI memory reads and writes to addresses from 2G to 4G on the PCI bus are mapped by the 660 as system memory reads and writes from OG to 2G These PCI to memory transactions are checked against the top of memory variable to de termine if a given access is to a populated bank The logic of the 660 does not recognize unpopulated holes in the memory banks PCI accesses to unpopulated locations below the top of memory are undefined PCI accesses to system memory are not limited to 32 bytes PCI burst mode accesses are limited only by the size of memory PCI bus latency restrictions and the PCI disconnect counter 5 2 2 Bus Snooping on PCI to Memory Cycles
258. istance Cap to Ambient 12 12 Table 12 5 Thermal Resistance From Cap to Ambient No Heat Sink 12 13 Table 12 6 Thermal Resistance From Cap to Heat Sink 12 13 Table 12 7 Required Maximum Thermal Resistance Cap to Ambient 12 13 Table A 1 Quickstart Peripheral List 4 Table 1 DMA Assignments B 3 Table B 2 DRAM Module Presence Detect Bit Encoding B 5 Table B 3 Planar ID Encoding B 6 Table B 4 DRAM Module Presence Detect Bit Encoding B 7 Table B 5 External Register Support B 8 Table B 6 Signal Descriptions soon Segue sa Sted a sees eases B 10 Table C 1 Summary of SIO Register Setup Configuration Address 8080 08 C 2 G5220297 00 xvii Table C 2 Table C 3 Table C 4 Table D 1 Table D 2 Table D 3 Table D 4 Table D 5 Table D 6 Table D 7 Table D 8 Table D 9 Table D 10 Table D 11 Table D 12 Table D 13 Table D 14 Table D 15 Table D 16 Table D 17 Table D 18 Table D 19 Table D 20 Table D 21 Table E 1 Preliminary Pewer Summary of SIO Configuration Registers C 4 Combined Register Listing C 6 Compatible ISA Ports Not on Reference Board C 11 Power Supply Specification 0 1 Approximate
259. ister This data phase is to the lower 4 byte word Eight Byte The previous data phase caused a gather and The bridge combines the high four bytes from This is a 4 byte transfer and this data phase with the low four bytes from the This data phase is to the upper 4 byte word previous data phase and writes all eight bytes to memory This is a single phase transaction or The bridge Reads eight bytes from memory mo This is the first data phase and difies the data by replacing the appropriate four is to the upper 4 byte word or bytes with the data from this data phase and then This is the last data phase and writes all eight bytes to memory is to the lower 4 byte word or This is a less than 4 byte transfer Best case see Table 4 14 is a burst starting on a low word memory address is 0 mod 8 composed of an even number of data phases in which all data phases transfer four bytes of data Notice that the first data phase is gathered and the second data phase causes an 8 byte memory write The following pairs of data beats follow the same pattern No page misses snoop hits or data beats of less than 4 bytes are encountered This case adds no PCI clock cycles to the best case transaction time Table 4 14 Bridge Response to Best Case PCI Write Burst Data Bridge Special Conditions Performance Impact Phase Operation ees er Table 4 15 shows a case where the first data phase is to a high word memory address is 4 mod 8
260. k after TS is sampled active 660 will only assert ARTRY on the clock after it asserts AACK during a PCI retry See the 603e User s Manual for more information BG 6644 F11 U2 134 660 CPU_GNT1 660 asserts to grant the address bus to CPU the CPU 2 4 5220297 00 PowerPc Preliminary Section 2 Signals Table 2 4 CPU Bus Signals Continued BG 60 F09 CPU BG CPU address bus grant input Normally connected to BG 6644 BG MASTER N20 5 660 CPU_GNT2 660 asserts to grant the bus to a second CPU busmaster BR 60X4 CPU BR The CPU asserts this output to request the CPU address bus Normally connected to BR 66445 BR 6644 660 CPU REQ14 660 CPU bus request input for CPU1 the CPU BR_MASTER 660 CPU REQ 2 660 CPU bus request input for CPU2 a second CPU busmaster 60 CPU Cache Inhibit output Asserted to indicate that a single beat transaction should not be cached See 603e UM CKSTP_IN 2 CPU ChecKSToP INput When this signal is asserted the CPU will enter checkstop CKSTP OUT CPU ChecKSToP OUTput The CPU asserts this open drain output to indicate that it has detected a checkstop condition and has entered the checkstop state CSEO o CPU Cache Set Element 0 output See 603e UM CSE1 o CPU Cache Set Element 1 output See 603e UM D 0 63 Ut The 64 bit CPU data bus DO is the MSbit D 0 31 connect to CPU DH 0 31 03
261. la nar The MPC 970 is configured to interface with a 16 5 MHz crystal An oscillator internal to the component then produces the root frequency used to create all clock outputs G5220297 00 7 1 Section 7 Clocks Preliminary PowerPc 71 CPU Clock Physical Design Rules The and the example planar were physically designed with careful attention to the fact that at PowerPC operating frequencies the circuit board itself becomes a component that materially affects circuit behavior Clock nets are the most critical wiring on the board Their wiring requirements should be given priority over the requirements of other groups of signals The following design rules are helpful in designing low noise and low skew clock nets 1 Clock nets are to have a minimum number of vias 2 No clock wires may be routed closer than one inch to the edge of the board Consider adding EMC caps to the far end of the clock trace 3 Clock nets should not have more than two nodes Daisy chains stubs and star fanouts are not allowed 4 Clock nets are to be routed as much as possible on internal signal planes 5 Route a ground trace as a shield in the adjacent wiring channel on both sides of the clock trace It is a good practice to periodically every inch or so connect these shield traces to the ground plane Completely surround the clock trace with shield traces Avoid im pedance bumps 6 Series source termination resistors are required Cho
262. led as usual for the error type No spe cial rules are in effect 6 2 1 3 Burst Reads The 660 supports burst reads in remote ROM mode The 660 supports a pseudo burst mode which supplies the same eight bytes of data from the ROM to the CPU on each beat of a 4 beat CPU burst A burst ROM read begins with the 660 executing a single beat ROM read operation which assembles eight bytes of ROM data into a double word on the CPU data bus For a burst ROM read the 660 asserts TA for four CLK cycles with asserted on the fourth cycle The same data remains asserted on the CPU data bus for all four of the data cycles For a single beat read the 660 asserts and for one CPU CLK cycle and the CPU completes the transfer 6 2 1 4 Endian Mode Considerations In little endian mode the address munging done by the CPU has no effect because PCI AD 2 0 are forced to 000 during the address phase by the 660 at the beginning of the transaction However in little endian mode the byte swapper is enabled so the bytes of ROM data returned to the CPU are swapped as shown in the last column of Table 6 4 G5220297 00 6 11 Section 6 ROM Preliminary PowerPc 6 2 1 5 4 Byte Reads The 660 handles 4 byte ROM reads and all ROM reads of less than 8 bytes as if they were 8 byte reads All 8 bytes are gathered by the 660 and all 8 bytes are driven onto the CPU data bus 6 2 2 Remote ROM Writes While the 660 is config
263. lock in duration and is coincident with the clock in which PCI is first asserted After the first clock the PCI AD pins carry data The PCI AD lines are driven by the initiator dur ing the address phase and by the originator of the data initiator or target during the data phases PCI C BE 3 0 660 C bus command and BE byte enable multiplexed lines During a PCI address phase C 3 0 the bus command During a PCI data phase PCI C BE 3 0 are active low byte enables BEO enables AD 7 0 BE1 enables AD 8 15 BE2 enables AD 16 23 and en ables AD24 31 The initiator drives C BE 3 0 If no bus transaction is in progress then the current PCI busmaster must drive the PCI C BE 3 0 pins PCI DEVSEL Z 660 PCI device select PCI DEVSEL4 is driven by a PCI target that is claiming the current transaction The 660 claims PCI memory transactions from 0 to 2G within the installed DRAM space PCI 660 PCI Frame The current PCI busmaster drives PCI FRAMEZ PCI FRAMEZ signals the beginning of the address tenure on the PCI bus and the duration of the data tenure PCI FRAMEZ is deasserted to signal the final data phase of the transaction G5220297 00 2 7 Section 2 Signals Preliminary Pewer Table 2 5 PCI Bus Signals Continued Signal Name MCM Nodes Description PCI_IRDY 660 PCI initiator ready PCI_IRDY is driven by the current PCI busmas
264. ls U4 48 F3 MD47 0 BR MASTER 202 CPU 664 NC DEPOP SRAM BCLK2 NC DEPOP Q P gt gt S gt 218 aS 9 gt a U1 97 U3 197 U7 8 U1 89 U3 210 U7 18 U1 81 U3 228 U8 40 U1 73 U3 25 U8 12 01 143 03 54 09 34 01 133 03 69 09 44 01 124 03 87 09 14 01 106 03 104 010 38 01 52 03 117 010 8 U1 63 U3 135 U10 18 gt gt o 0 08 0 NC DEPOP gt 5 DEPOP NC DEPOP NC DEPOP gt gt gt gt gt gt gt gt gt gt 8 Fo Fo Fo Fo Fo Fo S 6 oj lt j o gt Nj Of O gt 2 NC DEPOP 2 NC DEPOP AG22 D56 23 NC DEPOP G24 062 gt gt E E gt C N a NC DEPOP E Q 2 gt gt N DEPOP C N gt R1 B05 U1 227 U3 100 D46 U3 101 POL vss U7 35 VDD2 D 7 U1 98 U3 188 U7 45 vss 2268 31 NC DEPOP gt I gt gt gt w 01 2 gt I e 2 04 I e 6 gt Z 2 E E I 5 9 2 24 PowerPc MCM Nodes vss D25 U1 74 U3 24 U8 9 VDD2 D31 U1 66 U3 33 U8 19 vss
265. ly subset is intended for customer use see Table 2 2 The rest of the signals can be left floating Table 2 11 Pin List With Net Names and MCM Nodes Pin NetName MCM Nodes A30 S AD24 B02 PCLAD26 0 U PCI AD20 AD 1 RIO gt E UJ UJ 027 yss f Hoe 00 O PCI AD29 0 PCI AD22 U2 22 U3 46 ojo UJ 506 24 23 21 20 18 15 13 12 4 0 19 184 180 4 03 4 05 gt UJ 07 PCI AD25 U2 19 U3 49 N GBL 09 PCI_AD28 U2 14 U3 62 3 8 UJ gt oy hy AL A nm USER us B11 FB SEL lus C Iss eT CLK REF SEL 04 4 CLK MR U4 2 TRISTATE ao us wes 87 uz gt c e IS ws SY 22 FRZ 24 ss 27 cro ua POWER GOOD RE CRS C2PWXS U2 65 U3 151 gt co e N E oor ww yes gt 2 2 2 2 2 2 2 2 1 1 1 1 R1 R1 2 2 gt gt 1 2 4 gt 3 2
266. ly represent contiguous addresses This table shows what would happen for all cases 5 10 G5220297 00 PowerPc Preliminary Section 5 PCI Bus 5 3 Bus Arbitration Logic The requires an external PCI arbiter such as may be supplied in the ISA bridge The 660 sends a CPU 660 bus request to the PCI bus arbiter to request ownership of the PCI The 660 receives a PCI bus grant from the PCI bus arbiter The 660 follows the PCI specifi cation for host bridges The PCI arbiter typically parks the PCI bus on the 660 The 100 MHz PPC 603e MCM example planar uses the Intel SIO as the PCI bus arbiter The PCI arbiter sees the 660 as one of several PCI agents The order of priority for PCI arbitration is programmable and is initially set to be 1 660 the SIO normally parks the bus on the 660 2 PCI slot 1 3 PCI slot 2 4 PCI slot For more information on arbitration see Section 9 on planar initialization and see the PCI Arbitration Controller section of the SIO data book See the example planar schematics for the connection of the various PCI requests and grants There may be concurrency of cycles on the ISA bus caused by DMA or ISA masters with PCI or CPU transactions as long as the ISA bus operations are not forwarded to the PCI bus Forwarding of ISA bus operations must wait for the ISA bridge to grant the PCI bus to its ISA interface G5220297 00 5 11 Section 5 PCI Bus Preliminary PowerPc 5 4 PCI Lock The MCM 6
267. ment or any activities hereunder require IBM to disclose any business planning information to you You agreeto comply with all applicable governmentlaws and regulations Any changes to this Agreement mustbe in writing and signed by the parties iv G5220297 00 Pewer Preliminary Table of Contents Section 1 Introduction 1 1 The MEMES rt Eats E P ETE SER 1 1 1 2 100 MHz PPC 603e MOM t hers wear eds 1 2 CRU sls esd PEPPER 1 3 12250 sa Nas uda ER DA he tx bai uses palo pe 1 3 1 2 3 System Memory Interface 1 3 12 4 The POL Interface re 1 3 125 SYSICMASIOCKS Es Aue Sia Dre pa lon dre 1 4 1 2 6 MOM Performance 1 4 1 3 Technology Overview 1 5 1 3 1 Chip Attachment to MON oitis Rie 1 5 1 3 2 Substrate Attachment to the Planar 1 6 1 4 Incorporating the into a System Design 1 7 Section 2 Signal Descriptions 2 1 2 1 Pin Descriptions a e 2 1 2 1 1 Clock Subsystem 2 3 2 aS PU BIS oa a eu aa tra re e 2 4
268. mory Timing Register 2 4 4 4 2 1 3 RAS Watchdog Timer BCR 4 4 4 2 1 4 DRAM Timing Calculations 4 5 4 2 1 5 DRAM Timing Examples 4 7 4 2 1 6 70 5 DRAM Calculations 4 7 4 2 1 7 60 lt DRAM Calculations 4 8 4 2 1 8 50ns DRAM Calculations 4 9 4 2 1 9 60ns EDO DRAM Calculations 4 9 4 2 1 10 Aggressive Timing Summary 4 10 4 2 1 11 Conservative Timing 4 12 4 2 1 12 Hit and Page 4 14 4 2 1 13 CPU to Memory Access 0 4 15 4 2 1 14 Extended Data Out EDO DRAM 4 15 4 3 System Memory 0 4 15 4 3 1 DRAM Logical Organization 4 15 4 3 1 1 SIMM Topologies E ACOO 4 16 4 3 1 2 Row and Column Address Generation 4 17 43 1 3 DRAM Pages Gee RR DR PE 4 18 4 3 1 4 Supported Transfer Sizes and Alignments 4 18 4 3 1 5 Unpopulated Memory Locations
269. mp 1 076671 S 1M NI AIG 1M YL ov 0 5 LNO cG ALG ui din ou1 sa3a INO TS U ih OT TON DL SPIRA NEAT gt COO IIE 79 x3ogi 53195 91 lt o X758 9Ul X ce HOYO Ol ET 82 gt gt lt oSd2 Src9T vo B66T E E pS 20 41 031 JIGOW 1597 9 081 1335 57411 NUHWISO3 SNIMUHU gt HENIN 61 34 4215 5661 gt IUNOI LlON LJ NON C ONY SUI UIS CUI N LDLD CO UT SJ Lassa Ll bo Lo lo Lo Lo Sy2 S9NILIOO 4 79100 Spo SNILIUO 4 78100 Spo SNIIUO 4 78100 Spo SNILIUO 4 gt 5 40 2 eee eee HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 555555555555555555555555555555555555 OI U
270. mple Package modeling information that allows such an analysis is found in Section 12 1 2 Note that the dynamic interfaces between the MCM and a system planar consist of the PCI port and the system memory port Both interfaces are contained within the 660 bridge compo nents For this reason only a paper model of the 660 SCM package is included here for use in package delay comparison 12 1 2 SCM Package Delay Modeling Figure 12 1 is a paper electrical model of the quad flatpack package that houses the 660 bridge die Typical delays attributed to this package are nanoseconds Figure 12 1 QFP Package 12 1 3 MCM Package Delay Modeling To provide information needed to correctly model the MCM package a paper model of the package has been included in Figure 12 1 In this model a transmission line is used to model the effects of a net trace in ceramic The length of this transmission line is different for each signal that is considered Refer to Table 12 1 for a listing of the net lengths for all signals to which the user is expected to interface 12 2 G5220297 00 Y d Power Preliminary Section 12 Electromechanical 12 1 4 Net Electrical Model Figure 12 1 shows a typical electrical model of the major nets on the MCM This model ap plies to the PCI DRAM and clock net groups The segment labeled C shows the effects of the chip IO pad The Redistribution segment shows the effects of the redistributi
271. multi bit ECC error during CPU to memory transfer L2 cache parity error PCI bus data parity error 660 is PCI busmaster during CPU to PCI transaction PCI target abort received 660 is PCI busmaster during CPU to PCI transaction PCI master abort generated 660 is PCI busmaster during CPU to PCI transaction G5220297 00 8 5 TES a Section 8 Exceptions Preliminary Power 8 2 1 2 CPU Bus Error Handling Protocol If the error is masked do not detect the error If the error is detected perform the following steps 1 Set status bit indicating error type 2 Set status bit indicating error during CPU cycle 3 Save CPU address and control bus values 4 Report error to the CPU Reported by means of if the CPU cycle is still active or by means of if the CPU cycle has ended PCI bus data parity errors also cause PCI PERR to be asserted There is a status bit PCI Status Register bit 15 that is set whenever any type of PCI bus parity error is detected The setting of this status bit is not maskable 8 2 2 PCI Bus Related Errors 8 2 2 1 PCI Bus Error Types During a PCI to memory transaction in which the 660 is the PCI target e PCI bus address parity error e PCI bus data parity error PCI memory select error Memory parity error Memory single bit ECC error trigger exceeded Memory multi bit ECC error 8 2 2 2 PCI Bus Error Handling Protocol If the error is masked the 660 does not detect the error If the
272. n the top row was arbitrarily chosen as 00 and could be any 32 aligned boundary The times shown in Table 5 6 are in PCI clock cycles and do not include any cycles that the PCI master spends acquiring the PCI bus from the PCI bus arbiter The initial data phase is timed from the assertion of FRAME to the PCI clock at which the PCI master samples TRDY active Subsequent data phase times are from the PCI clock at which the previous TRDY was sampled active to the PCI clock at which the current TRDY is sampled active All the numbers shown in Table 5 6 are for ECC parity or no error checking operation G5220297 00 In T Co PowerPc Preliminary Section 5 PCI Bus Table 5 6 PCI to Memory Read Burst Sequence Timing S S 00 04 08 oc 10 14 18 20 24 28 2C 30 34 38 3C 40 N 1 1 1 1 1 1 1 M 1 1 1 1 1 1 1 M N 1 1 1 1 1 1 M 1 1 1 1 1 1 1 M N 1 1 1 1 1 M 1 1 1 1 1 1 1 M N 1 1 1 1 M 1 1 1 1 1 1 1 M N 1 1 1 M 1 1 1 1 1 1 1 M N 1 1 M 1 1 1 1 1 1 1 M N 1 M 1 1 1 1 1 1 1 M N M 1 1 1 1 1 1 1 M N 1 1 1 1 1 1 1 M S indicates a cache block boundary at 0 mod 32 Snoops are broadcast to the CPU bus when a PCI burst crosses one of these boundaries N is the number of PCI clocks required from the assertion of FRAME until the master samples the first TRDY from the 660 active and is a function of snoop and memory arbitration delays If the CPU is accessing memory when the PCI agent begins the memory read burst the 6
273. nce Platform Partition 10 5 xiv G5220297 00 Pewer Preliminary Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 10 Figure 10 11 Figure 10 12 Figure 10 13 Figure 10 14 Figure 10 15 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 12 1 Figure 12 2 Figure 12 3 Figure A 1 Figure B 1 Figure D 1 Figure D 2 Figure D 3 Figure D 5 Figure D 6 Figure D 7 Figure D 8 Figure D 9 Figure D 10 Figure D 11 Figure D 12 Figure D 13 Figure D 14 Figure D 15 Figure D 16 Figure D 17 Figure D 18 Figure D 19 Figure D 20 Figure D 21 G5220297 00 System Initialization Screen 10 7 Configuration Utility Main Menu 10 8 System Configuration Menu 10 9 System Information Screen 10 10 Device Configuration Screen 10 11 SCSI Devices Screen 10 12 Boot Devices Screen 10 13 Set Date and Time Screen 10 14 Run a Program Screen 10 15 Reprogram the Flash Memory Screen 10 16 Endian Mode Block Diagram 11 3 Example at Address 0 11 6 Example at Addres
274. ng CPU read cycles This error is also generated when an L2 cache data parity error see section 8 2 3 6 is de tected CPU DPAR 0 indicates the parity for CPU DATA 0 7 DPAR 1 indicates the parity for DATA 8 15 and so on G5220297 00 Hin In Co PowerPc Preliminary Section 8 Exceptions This error can be controlled by the indexed register set The mask is at register C4h bit 2 If an error is detected the status bit at register 5 bit 2 is set Register C7h bit 4 is cleared to indicate an error on a CPU cycle The CPU address is saved in register C8h the CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 This error can be reset by writing a 1 to register 5 bit 2 This error cannot be controlled by means of the 650 compatible register set 8 2 3 6 L2 Cache Parity Error This error is generated when a parity error is detected during a CPU read from the L2 cache The parity is checked by the CPU which drives DPE to the 660 When this error is de tected the 660 indicates both this error and a CPU bus data parity error This error can be controlled by the indexed register set The mask is at register C4h bit 3 If an error is detected the status bit at register 5 bit 3 is set Register C7h bit 4 is cleared to indicate error on a CPU cycle The CPU address is saved in register C8h The CPU con trol is saved in register and the CPU number is save
275. ng the appropriate BCRs even if NMI REQ is still asserted 8 2 8 Error Reporting Protocol In general when the 660 recognizes an error condition it sets various status BCRs saves address and control information for bus related errors disables further error recognition until the current error is cleared and reports the error to either the CPU or PCI bus Unless otherwise noted the 660 takes no further error handling action but relies on the CPU software or PCI agent to take the next step in the error handling procedure The 660 continues to react appropriately to CPU and PCI bus traffic the state of the memory control ler is unchanged current and pipelined CPU and PCI transactions are unaffected and the behavior and state of the 660 is unaffected For example if a memory parity error is reported to the CPU using MCP and the CPU does not respond to the MCP then the 660 will in all ways continue to behave as if the MCP had not been asserted However various BCRs will contain the error status and ad dress information and further error recognition will be disabled until the CPU resets the error in the 660 BCRs 8 2 8 1 Error Reporting With MCP The following errors are reported to the CPU using e NMI errors e Errors that occur because of a CPU transfer but which are detected too late to be reported using and e Errors that are not a direct result of the current CPU transfer The 660 reports an error wit
276. non cacheable The Segment Register T bit bit 0 defaults to 0 which is the normal storage access mode It must be left in this state for the hardware to function Direct store PIO segments are not supported Set the bit that controls ARTRY negation HIDO 7 to 0 to enable the precharge of ARTRY It may be necessary set HIDO 7 to 1 to disable the precharge of ARTRY for 100 MHz PPC 603e MCM configurations having a CPU bus agent such as an added L2 that drives the ARTRY line Software must set this bit before allowing any CPU bus traffic to which the CPU agent might respond Note that PCI to memory transactions cause the 660 bridge to broadcast snoop operations on the CPU bus HIDO bit 0 Master Checkstop Enable defaults to 1 which is the enabled state Leave it in this state so that checkstops can occur MCM errors are reported through the 660 by way of the TEA and MCP pins Because of this the bus error checking in the CPU must be disabled by setting HIDO bits 2 and 3 to zero 9 2 660 Bridge Initialization Before DRAM memory operations can begin the software must 1 Read the SIMM presence detect and SIMM type registers 2 Setup and check the memory related registers in the 660 see the 660 Bridge User s Manual 3 Program the timer in the ISA bridge register which controls ISA refresh timing In SIO compatible bridges it should be programmed to operate in Mode 2 with an interval of approximately 15 usec 4 Make sure 20
277. ns to this ad dress range so do not map devices to this PCI memory address range 2 The CPU thru the 660 can not access the 1G 2M to 2G address range so do not map PCI devices herein unless the CPU will not access them 3 Transactions initiated on the PCI bus by the ISA bridge on behalf of an ISA bus master only PCI AD31 asserted for SIO are forwarded to system memory and broadcast snooped to the CPU bus from 0 to 16M If this is not an ISA busmaster transaction then the 660 ignores it Note that the 660 will also forward PCI transactions from 16M to 2G if IGN PCI ADS 1 is asserted during an ISA bridge mastered transaction and that this capability is not normally used 5 1 3 PCI I O Transaction Decoding The 660 initiates PCI I O transactions on behalf of the CPU Other PCI busmasters are also allowed to initiate PCI transactions Table 5 4 shows the mapping of PCI transactions 660 ignores PCI transactions G5220297 00 5 3 Section 5 PCI Bus Preliminary PowerPc PCI ISA is mapped to PCI space from 0 to 64K The ISA bridge subtractively de codes these transactions and also PCI memory transactions from 0 to 16M Other devices may actively decode and claim these transactions without contention PCI I O is assigned from 16M to 1G 8M Table 5 4 Mapping of PCI Master Transactions The 660 ignores I O transactions initiated by PCI busmasters Note 1 The CPU
278. o 1 the mode bit indicates the endian mode of the code section pointed to by the load image offset and the firmware has to establish the hardware endian mode according to this bit Otherwise this bit is just an informative field for firmware The OS ID field and partition name field are used to identify the operating system located inthe partition The OS ID field has the numeric identification value of the operating system located in the partition The 32 byes of partition name field must have the ASCII notation of the partition name The name and OS D can be used to provide to a user the identifica tion of the boot partition during the manual boot process Once the boot partition is identified by the PowerPC Reference Platform boot partition table entry the firmware e Reads into memory the second 512 byte block of the boot partition e Determines the load image length for reading in the boot image up to but not includ ing the reserved2 space e Allocates a buffer in system RAM for the load image transfer no fixed location e Transfers the load image into system RAM from the boot device the reserved2 space is not loaded The load image must be fully relocatable as it may be placed anywhere in memory by the system firmware Once loaded the load image may relocate itself anywhere within system RAM 10 4 System Configuration This section describes the utilities in the system firmware which allow the system to be cus tomized The
279. o the 664 Controller The reset value of 01F8h provides a refresh rate of 15 1 micro seconds while the PCI clock is 33MHz 01F8h equals 504 times 30ns equals 15 12us Bits 3 11 of the timer allow timer values from 8 to 4096 Don 57 16 os 24 22 2 01 po ELS Hardcoded to 0 Refresh Timer Value LSBs Bits 7 3 Refresh timer 7 3 These are the five least significant bits of the refresh tim er value Dih pisppiaprapi2priipio D ps Refresh Timer Value MSBs Hardcoded to 0 Bits 11 8 Refresh timer 11 8 These are the four most significant bits of the refresh timer value G5220297 00 4 31 Section 4 DRAM Preliminary PowerPc 4 6 Atomic Memory Transfers The 660 supports atomic memory transfers by supporting the CPU reservation protocol and the PCI lock protocol 4 6 1 Memory Locks and Reservations The 660 supports the Ilwarx and stwcx atomic memory update protocol by broadcasting snoop cycles to the CPU bus during PCI to memory transactions The bridge does not otherwise take any action nor does it enforce an external locking protocol for CPU busmas ters See Section 4 6 2 PCI busmasters can lock and unlock a 32 byte block of system memory in compliance with the PCI specification This block can be located anywhere within the populated system memory space aligned on a 32 byte boundary Only a single lock may be in existence at any given time The bridge does not implement complete bus locking Se
280. of end address 256 A29 of end address 512 Reserved 4 3 1 11 Memory Bank Enable BCR Index Read Write Reset to 00h This BCR contains a control enable for each bank of memory Each bank of memory must be enabled for proper refreshing For each bit a 0 disables that bank of memory and a 1 enables it This register must be programmed in conjunction with the starting address and ending ad dress registers If a bank is disabled by this register the corresponding starting and ending address register entries become don t cares 4 3 1 12 Memory Bank Configuration Example In the example memory bank configuration shown in Figure 4 3 the eight memory banks are populated by different size and organization devices For convenience this example shows the bridge configured to address each memory bank in order with no gaps in the populated address range but this is not required Any bank can be placed in any 1MB aligned non populated address range from 0 to 1G 4 20 G5220297 00 PowerPc Preliminary Section 4 DRAM o 6 25 D4 3 22 21 oo Enable Bank 0 Enable Bank 1 Enable Bank 2 Enable Bank 3 Enable Bank 4 Enable Bank 5 Enable Bank 6 Enable Bank 7 Table 4 11 Example Memory Bank Addressing Mode Configuration SIMM SIMMs SIMM Bank Row x BCR Bits Type Per Topology Col Bank ja C EE sar Te eee _ sr nem e ___ EE E Tm
281. on Figure 3 5 shows how the MCM maps the SRAM to main memory using the index and tag fields of the address Notice that there are 8k tags and 8k 32 byte blocks in the SRAM and that the main memory is divided up into 4k pages each one of which is composed of 8k blocks When an address is presented to the cache directory for snooping the MCM uses the index to select which directory location to access by presenting A 14 26 to the tagRAM address inputs The tagRAM then compares the tag in that location the A 2 13 of the previous cacheable access to that location to the tag A 2 13 of the current transaction If there is a match and the tag is marked valid then there is a cache hit signalled by MATCH 3 12 G5220297 00 Power Preliminary Section 3 CPU amp L2 Figure 3 5 SLC L2 Cache Directory 512K Configuration Suppose the CPU requests a burst store to location 512K 8 0000h which is initially invalid either stale or never accessed The index is A 14 26 which is Oh so the accessed ta gRAM location is Oh The tag currently on the address bus is A 2 13 which equals 2 So the stores 2h into tagRAM location Oh The valid bit is set for that location While the CPU is accessing other blocks of memory with different low order addresses oth er locations in the tagRAM are being accessed however if th
282. on meta lization that is added to the chips to produce flip chips The Ceramic Vias segments show the effects of vias in the MCM ceramic substrate The Routed Signal segment shows the effects of trace lengths in the ceramic The Solder Column segment shows the effects of the solder columns For net lengths see Table 12 1 HR Redistribution Chip IO Driver Ceramic Vias Routed Signal Lvia1 Rvia1 0 5nH 50 uQ 2 Zo 45Q 0 2 To 117ps cm L typ 5 cm Ice Ceramic Vias 22 13 Solder Lvia2 Rvia2 Linter Rinter 0 5nH 50 uQ F 79pH G Cinter1 Cinter2 23 23 Figure 12 1 Net Electrical Model G5220297 00 12 3 Section 12 Electromechanical Preliminary Power Table 12 1 Primary 63 0000 i PCI ADO J1 TO1 U2 48 03 236 44 2500 i PCI AD1 J1 R01 U2 59 03 237 50 6036 i PCI AD2 J1 R02 U2 46 03 238 47 5000 i PCI AD3 J1 P01 U2 43 03 239 42 1036 i PCI AD4 J1 N02 U2 42 03 10 41 0000 PCI AD5 J1 M01 U2 41 03 11 42 3536 PCI AD6 J1 L01 U2 40 U3 12 39 9571 i PCI AD7 J1 L02 U2 39 03 13 40 1036 i PCI AD8 J1 K01 U2 38 03 14 49 7500 i PCI AD9 J1 J01 U2 37 03 15 58 8536 i PCI PAR J1 AH01 U2 7 40 1036 i PCI AD10 J1 H01 U2 36 03 16 46 9571 i PCI AD11 J1 G01 U2 35 03 17 36 1036 i PCI AD12 J1 G02 U2 34 03 18 55 0000 i PCI AD13 J1 F01 U2 33 03 19 39 8536 i PCI AD14 J1 E01 U2 32 U3 20 46 9571 i PCI AD15 J1 E02 U2 31 03 21 47 9571 i PCI AD16 41 001 02 3
283. ons to 4G 2M to 4G The 660 does not allow CPU masters to access the rest of the PCI memory space from 2G to 4G In remote ROM mode PCI busmaster memory write transactions from 4G 2M to 4G are ignored by the 660 However the PCI agent that controls the ROM responds to these trans actions In contrast in direct attach ROM mode the 660 forwards PCI busmaster memory transactions from 2G to 4G to populated memory locations to system memory from 0 to 26 Remote ROM writes must be one byte single beat transfers The endian mode of the system has no net effect on a ROM write because the transfer size is one byte The address is munged by the CPU and unmunged by the 660 The data comes out of the CPU on the byte lane associated with the munged address and then is swapped by the 660 to the byte lane associated with the unmunged address Thus a ROM write in little endian mode puts the data byte in the same ROM location as does the same ROM write in big endian mode 6 12 G5220297 00 PowerPc Preliminary Section 6 ROM CPU CLK CPU ADDR 5 CPU DATA PCI CLK j PCI REQ amp n PCI CLKS 1 PCI 5 PCI AD 664 Add PCI AD 663 i Daa 3 0 l Cmd Byte Enables DEVSEL FRAME IRDY 3 n PCI CLKs O
284. or is generated when a PCI bus data parity error is detected during a PCI to memory write transaction The PCI bus uses even parity which means that an even number of bits including the parity bit are driven high This error can be controlled by means of the registers in the indexed register set The mask is at register O4h bit 6 This error does not have an explicit status bit to indicate its occur rence However the following status bits are set e Register bit 11 is set to indicate signalled target abort if the cycle was target aborted This bit is cleared by writing a 1 to register O6h bit 11 e Register O6h bit 15 is set to indicate a PCI bus parity error regardless of the state of the mask at register O4h bit 6 Note that this bit is set by all types of PCI bus parity errors This bit is cleared by writing a 1 to register O6h bit 15 e Register 06h bit 14 which indicates PCI SERRA is set if the mask at register COh bit 6 is disabled cleared Note that the mask at register COh bit 6 allows the 660 to signal PCI SERR in addition to PCI PERR5 for this error This bit is cleared by writing a 1 to register O6h bit 14 Register C7h bit 4 is set to indicate an error on a PCI cycle The PCI address is saved in register C8h The PCI control is saved in register C7h This error cannot be controlled by means of the 650 compatible register set During PCI to memory reads the 660 does not monitor PCI PERREZ to detect data parity errors
285. ose them according to the MPC970 data sheet recommendations and place them as close as possible to the clock source pin of the MCM 7 To minimize clock skew on the planar design the circuit board such that the combined length MCM plus planar of each of the clocks is the same In other words determine the required total length of the longest clock trace and then make all of the other traces the same total length see Figure 7 2 Inside the MCM the PCI clock traces run about 1 inch and the CPU clock traces run about 3 5 inches Thus the planar runs of the clocks should be adjusted accordingly Suppose in Figure 7 2 one of the PCI clocks planar runs is initially the longest at 8 5 inches Added to the about 1 inch of MCM run the total length is about 9 5 inches Cor rect design will then stretch all of the other PCI clock lines to 8 5 inches The required planar run length of the CPU lines is then 9 5 3 5 6 inches See Table 7 1 and Table 7 2 Table 7 1 Clock Net Lengths Net Topology 13 7500 XTAL1 11 7071 XTAL2 32 5000 FRZ CLK 18 6036 FRZ DATA 8 5866 PCLK 60X 66 3536 TAG BCLK 29 9142 CLK EXT FB 27 0000 CLK FB SEL 27 5000 CLK PLL EN 67 5000 SRAM BCLKO G5220297 00 1 ii PowerPc Preliminary Sion UR Table 7 1 Clock Net Lengths Continued Net Length Net Topology 66 5000 SRAM BCLK1 J1 AE30 9 1624 SRAM_BCLK2 J1 AG04 8 6624 SRAM_BCLK3 J1 AA04 22 6036
286. ow O CINI 8 18 G5220297 00 PowerPc Section 8 Exceptions Table 8 3 664 Pin Reset State 664 Signal State 664 Signal State 664 Signal State MEM BE 3 0 RESET AOS_RR_MMRS MEM_DATA_OE ROM_LOAD ARTRY MEM_ERR ROM_OE C2P_WRL_OPEN MEM_RD_SMPL ROM_WE CAS 7 0 MEM_WRL_OPEN SBE CPU ADDR 0 31 MIO TEST SHD CPU_BUS_CLAIM CPU_CLK CPU_DATA_OE CPU_GNT1 CPU_GNT2 CPU_PAR_ERR CPU_RDL_OPEN CPU_REQ1 CPU_REQ2 CRS_C2PWXS DBG DPE DUAL_CTRL_REF ECC LE SEL GBL IGN_PCI_AD31 INT_CPU INT_REQ 11 0 MWS P2MRXS SRAM ADS REQ SRAM ALE PCI AD 81 0 SRAM CNT EN PCI AD SRAM OE PCI 0 SRAM WE PCI CLK STOP CLK EN PCI DEVSEL PCI EXT SEL TAG PCI FRAME TAG MATCH PCI GNT TAG VALID PCI 1 TAG WE PCI LOCK TBST PCI OL OPEN PCI OUT SEL TEST PCI PAR TS PCI TSIZE 0 2 PCI REQ TT 0 4 PCI SERR WE 1 0 INI NIN 5 PCI STOP PCI TRDY RAS 7 0 XATS Notes During reset INT CPUXZ i
287. r COh bit O If an error is detected status bits at register C1h bits 1 0 are set to 10 Register C7h bit 4 is cleared to indicate an error on a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 Transfer type and size errors are reset by writing a 1 to register C1h bit 0 or register C1h bit 1 The indexed register set uses the same mask and error reset bits for XATS that it uses for unsupported transfer types Transfer type and size errors can also be controlled by the 650 compatible register set The mask cannot be controlled by means of this register set If an error is detected the status bit at 8000 0844h bit O is cleared The address is saved at BFFF EFFOh This error can be reset by reading BFFF EFFOh Note that the 650 compatible register set does not differenti ate between XATS errors and unsupported transfer type errors 8 2 3 2 CPU Bus 5 Asserted Error This error is generated when the CPU asserts the 5 signal The XATS error can be controlled by the indexed register set The mask is at register COh bit O If an error is detected the status bits at register C1h bits 1 0 are set to 01 Register C7h bit 4 is cleared to indicate an error on a CPU cycle The CPU address is saved regis ter C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 This error can be reset by writing 1 to regi
288. r is added to the the chip is flipped over and C4 balls are used to connect the chip pads to the MCM sub strate pads Unpackaged die have a much smaller footprint than packaged die This reduces the overall size of the circuitry and allows the a much smaller footprint than would be re quired by the same circuitry implemented on a planar in discrete packages Wire Bond 10 Pad Connection Flip Chip IO Pad Connection Redistribution Layer Solder Balls Passivation Layer Packaging Figure 1 3 Chip Wire Bond and Flip Chip Connection G5220297 00 1 5 p Section 1 Introduction Preliminary Power Figure 1 4 shows chips mounted to the MCM substrate Figure 1 4 also illustrates the inter nal structure of the MCM substrate The acts as the circuit board between the various chips Structures analogous to printed circuit board traces and vias form the electrical inter connections between the various MCM chips The trace lengths on the MCM are much shorter than are achievable on a planar This means that signal propagation flight times between the devices are minimized which can allow faster operating frequencies than can be achieved on a planar The impedance of the various nets can be more precisely con trolled which contributes to high signal quality and low noise Figure 1 4 MCM Flip Chips and Internal Wiring 1 3 2 Substrate Attachment to the Planar Figure 1 5 shows how solder columns are u
289. r of the MCM cap This specification can be used with the MCM to simplify thermal calculations Table 12 3 shows the same data as Table 12 2 but for the expected maximum power dis sipation of the MCM All references to the MCM cap in Table 12 2 and Table 12 3 refer to the center of the MCM cap G5220297 00 12 11 p Section 12 Electromechanical Preliminary Power Table 12 2 Thermal Specifications for MCM Chips Typical Pd Parameter Maximum Junction Temperature Thermal Resistance Junction to MCM Cap C W Power Dissipation Typical W Junction Temp Rise Above Cap C Maximum Allowed Cap Temperature at Typical Pd C Typical MCM Total Pd 9 W Parameter Maximum Junction Temperature Thermal Resistance Junction to MCM Cap C W Power Dissipation Maximum W Junction Temp Rise Above Cap Maximum Allowed Cap Temperature at Max Pd C Maximum Total Pd 12 W 12 2 2 Cooling Requirements Table 12 2 and Table 12 3 show the typical and maximum total power dissipation of the Additionally the tables show that the MCM cap must be maintained below 67 at typical Pd and 66 at maximum Pd to ensure that all of the chips are adequately cooled There are other factors such as heat spreading and alternate heat conduction pathways that tend to reduce the cooling requirements Treatment of these complex
290. r on a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 This error can be reset by writing a 1 to register Cth bit 5 8 12 G5220297 00 PowerPc Preliminary Section 8 Exceptions This error cannot be controlled by means of the 650 compatible register set 8 2 6 2 System Memory Parity Error When memory is being operated in parity mode this error is generated if a parity error is detected during a read from system memory Memory parity is odd which means that an odd number of bits including the parity bit are driven high MEM CHECK 0 indicates the parity for MEM DATA 7 0 MEM CHECK 1 indicates the parity for MEM DATA 15 8 and so on The system memory parity error can be controlled by the indexed register set The mask is at register COh bit 2 If an error is detected the status bit at register C1h bit 2 is set If the parity error occurred while the CPU was accessing memory then register C7h bit 4 is cleared to indicate the error occurred during a CPU cycle The CPU address is saved in register C8h The CPU control is saved in register C3h and the CPU number is saved in register C7h bit 5 If the parity error occurred while the PCI was accessing memory then register C7h bit 4 is set to indicate the error occurred during a PCI cycle The PCI address is saved in register C8h The PCI control is saved in register C7h This error can be
291. ransfer it In the event that you no longer wish to use the software you will return it to IBM LICENSE TO DESIGN DOCUMENTATION With regard to the design documentation provided hereunder itis understood that you intend to use such documentation solely for the pur pose of designing yourown PowerPC compatible products testing yourdesigns and making yourownindependentdetermination of wheth er you wish to eventually manufacture PowerPC compatible products commercially In accordance with this understanding IBM hereby grants you the right to a use the design documentation for the purpose of designing PowerPC compatible products and testing such de signs b make derivative works of the design documentation for the purpose of designing PowerPC compatible products and testing such designs andc make copies of the design documentation and any such derivative works but only such numbers as are reasonably neces sary for designing PowerPC compatible products and testing such designs With regard to any copy made in accordance with the forgoing license you must reproduce any copyright notice appearing thereon With regardtothe design documentation provided hereunder you may not a use copy modify or merge the design documentation as provided in this license or b sell sublicense rent lease assign or otherwise transfer it In the event you no longer wish to use the design documentation or any derivative versions thereof you must return them
292. reset by writing 1 to register C1h bit 2 Note that register locations listed above are used to indicate single bit ECC errors if the memory is being operated in ECC mode This error can also be controlled by means of the register in the 650 compatible register set The mask cannot be controlled by means of this register set If an error is detected the status bit at 8000 0840h bit 0 is cleared The address is saved at BFFF EFFOh This error can be reset by reading BFFF EFFOh 8 2 6 3 System Memory Single Bit ECC Error When memory is being operated in ECC mode single bit errors are detected and cor rected Since single bit errors are corrected generally no error reporting is necessary But when a single bit error is detected the single bit error counter register register B8h is in cremented and the system memory address is saved in the single bit ECC error address register register If the count in the single bit error counter register exceeds the value in the single bit error trigger level register B9h the 660 generates a single bit ECC trigger exceeded error The trigger exceeded error can be controlled by the indexed register set The mask is at register COh bit 2 If an error is detected the status bit at register C1h bit 2 is set If the error occurs while the CPU is accessing memory register C7h bit 4 is cleared to indi cate the error occurred during a CPU cycle The CPU address is saved in register C8h The CPU
293. rious other fac tors such as clock to output delays The CPU signal shown is not meant be contigu ous as the number of clocks between various events is programmable CPU CLK MA 11 0 1 1 Column Column 1 21 Column RPW o 20080000 fo ROD a CPW Ce CPW CH Figure 4 1 CPU to Memory Transfer Timing Parameters Table 4 1 shows the function location and section references for the variables shown in Figure 4 1 Table 4 1 Memory Timing Parameters Function BCR Section ASC Column Address Setup min Memory Timing Register 2 e RAS Precharge Memory Timing Register1 4211 Note that ASC and RCD are minimums if ASC does not equal RCD then the larger value will be used such that e If RCD lt RAH ASC then the actual RCD will be stretched to equal RAH ASC e If RCD gt RAH ASC then the actual RAH will be stretched to equal RCD ASC 4 2 1 1 Memory Timing Register 1 Index 1 Read Write Reset to 3Fh This BCR determines the timing of RAS signal assertion for memory cycles RAS timing must support the worst case timing for the slowest DRAM installed in the system See Sec tion 4 2 1 Bits 1 0 These bits control the number of CPU clocks for RAS precharge Bits 4 2 These bits control the minimum allowed RAS pulse width except on refresh For refresh the RAS pulse width is hard
294. rite of less than 4 bytes the two data phases will still be gathered and then the bridge will execute a RMW cycle filling in the unwritten bytes in the group of 8 bytes with data from those locations in memory The same write case while ECC is disabled does not cause a RMW cycle the bridge merely writes only the indicated bytes leaving the write enables of the unaccessed bytes deasserted Generator 660 Bridge Data 64 Chee System Memory Figure 4 8 PCI or CPU Read Modify Write Data Flow 4 4 1 5 Less Than Eight Byte Writes Figure 4 8 shows the simplified data flow during a CPU or PCI busmaster to memory write of less than eight bytes during which the bridge executes a RMW cycle In Figure 4 8 A the bridge reads in the data and check bits from the addressed memory locations and places this data corrected as necessary in a register In Figure 4 8 B this data is modi fied by the bridge which replaces the appropriate memory data bytes with write data from the busmaster The bridge then recomputes all of the check bits and writes the new data and check bits to memory 4 4 1 6 Memory Performance In ECC Mode Enabling ECC mode on the 660 affects memory performance in various ways depending on the transaction type The effect is the same for both EDO and page mode DRAMs 4 26 G5220297 00 PowerPc Preliminary Section 4 DRAM 4 4 1 7 CPU to Memory Read in ECC Mode ECC mode adds one CPU CLK to s
295. roblem There is a theoretical case in which the 660 does not comply with the PCI Producer Consumer model Appendix E Summary of PCI Ordering Rules Item 5b Note that to date 6 20 96 there have been no know actual occurrances of this case with the 660 It was recently discovered during a comprehensive review of the PCI 2 1 specification is not aware of any existing hardware software combination that produces a situation where this case can be observed For the following discussion please refer to the PCI 2 1 specification sections 3 2 5 and Appendix E Assume that the CPU is the Producer and that it is producing the final 4 bytes of a data set by initiating a PCI memory write via the 660 to a particular PCI agent the Consumer Assume that the 660 posts the write and that before the posted write completes on the PCI bus for instance if it is retried the CPU writes the flag to system memory Meanwhile the PCI agent is polling the flag by periodically reading the system memory location Assume that the PCI agent reads the flag as set meaning that the data set transfer is complete At this point the possibility exists that the agent has not allowed the CPU to PCI data set write to complete If so then the two CPU transactions have completed out of order and the flag will indicate that the data transfer has completed when in fact it has not To prevent this the PCI 2 1 spec requires the bridge to react to the PCI to m
296. rrespond to the IDSEL inputs of the PCI devices The generation of PCI configuration cycles is via the 660 indexed Bridge Control Registers BCR This configuration method is described in section 4 of the 660 User s Manual The IDSEL assignments and their respective PCI AD lines are shown in Table 3 3 The ad dresses used for configuration are assigned as shown in Table 3 3 3 8 G5220297 00 Y d Power Preliminary Section 3 CPU amp L2 Table 3 3 CPU to PCI Configuration Mapping PCI to ISA Bridge POI slot 1 PCI 5012 PCI siot Notes 1 This address is independent of contiguous mode 3 5 6 CPU to PCI Interrupt Acknowledge Transaction Reading the interrupt acknowledge address BFFF FFFOh causes the bridge to arbitrate for the PCI bus and then to execute a standard PCI interrupt acknowledge transaction The system interrupt controller in the ISA bridge claims the transaction and supplies the 1 byte interrupt vector There is no physical interrupt vector BCR in the bridge Other PCI busmas ters can initiate interrupt acknowledge transactions but this may have unpredictable ef fects 3 5 7 PCI Lock The 660 does not set PCI locks when acting as the PCI master The PCI LOCK signal in the 660 supports resource locking of one 32 byte cache sector block of system memory Once a PCI lock is established the block address is saved Subsequent accesses to that block from other PCI busmasters or from the CPU bus are retri
297. rts PCI FRAMEZ it sends ROM LOAD low On the next clock the 660 latches the ROM data on PCI AD 31 24 sends ROM LOAD high and increments the ROM address on PCI AD 23 0 The byte from the ROM is latched into a byte shift register which accumulates the bytes in an 8 byte double word The contents of the shift register move through the 660 and onto the CPU data bus 6 2 G5220297 00 PowerPc Preliminary Section 6 ROM I Each Cycle o ica Typ byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 47 PCI Clocks 81 24 23 0 664 ROM OE Q a 5 lt oO D O n O PCI_AD PCI_AD Figure 6 2 ROM Read Timing Diagram The ROM then drives the next data byte onto PCI_AD 31 24 Seven PCI CLKs after it ne gated ROM LOAD for the previous byte the 660 again negates ROM LOAD and also shifts the previous byte of ROM data to the next position On the next PCI CLK the 660 sends ROM LOAD high and increments the ROM address on PCI AD 23 0 This pattern is repeated until all eight bytes have been loaded into the shift register After the last byte has been latched into the 660 by the falling edge of ROM LOAD the 660 completes the PCI transaction by deasserting PCI It also negates ROM OEZ to clear the PCI bus After the last byte of data has had time to propagate through onto the CPU data bus the 660 signals TA to the CPU Table 6 1 shows the data and address flow during the transact
298. ry PowerPc 2 5 15 gt 60 5ns JONS gt 65NS MTR1 4 2 100 1CLK 15ns 10ns TONS gt TONS zs ce MTR2 6 5 00 4 2 1 CLK 15ns gt 16ns 15ns 6ns 45ns gt SZNS MTR2 3 2 01 5 CLK 15ns gt Ons 13ns 9ns 16ns 15ns gt 6ns b 1 2 1 CLK 15ns gt 13ns 9ns 30ns 6ns 60 5 gt 58ns MTR2 7 0 6 2 2 1 CLK 15ns gt 16ns 60 5 6ns FONG gt 82NS MTR2 1 0 201 see Note 5 7 1 15ns 10 5 4ns 13ns 16ns TONS JS esce emm oe MTR1 5 20 Results Memory Timing Register 1 index A1h 2 11h Memory Timing Register 2 index A2h 05h Note 5 The timing analysis above includes one timing violation path 6 is violated by 9 More conservate system designers may wish to use the values MTR1 31h MTR2 06h to ensure all timing requirements met under complete worst case conditions 8 Refresh rate 15 6us 30ns 520d 208h Refresh Timer Divisor index D1h DOh 0208h 9 RAS watchdog timer 10 000ns 15ns 8 83d 53h RAS watchdog timer register index B6h 53h default value 4 2 1 10 Aggressive Timing Summary Table 4 2 contains a summary of recommended general case aggressive page mode DRAM timing the required control register settings and the resulting performance of the memory controller Aggressive timings may generate slight violations of certain worst case timing constraints In many cases
299. ry controller gets ahead of the PCI read process and N decreases 5 2 9 PCI BE to CAS Line Mapping Table 5 7 shows which lines are activated when a PCI master writes memory Note that CAS 0 refers to byte addresses 0 mod 8 CAS 1 refers to byte addresses 1 mod 8 etc For read cycles eight bytes of memory data are read on each access but the master receives only the desired 4 bytes The bytes are read or written to memory independently of BE or LE mode the endian mode byte swappers are situated between the CPU and the rest of the system not between the PCI and the rest of the system G5220297 00 5 9 Section 5 PCI Bus Preliminary PowerPc Table 5 7 Active CAS Lines PCI to Memory Writes BE or LE Mode Byte Enables BE Column Address Selects CAS 2 1 2 3 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X x O O OF OF HY AY O O Oo a oclo HI AH O O Oj Oo AH Notes X active Blank inactive Byte enables would normal
300. s 11 7 Double Byte Write Data ab at Address xxxx xxxO 11 10 Word 4 Byte Write of Oa0bOcOdh at Address xxxx xxx4 11 12 Instruction Alignment Example 11 15 Wrong Instruction Read When Unmunger is used 11 16 Instruction Stream to Switch Endian Modes 11 17 Net Electrical Model 12 2 MCM Thermal Paths de Rae 12 3 MGM Heat FIOWS 12 3 Example Planar Block Diagram 2 Typical External Register Ep 7 Signal and Power Layers D 3 Typical Wiring Channel Top View D 3 PowerPC 603 604 Board Fabrication D 4 The Keyboard Connector D 9 The Alternate Keyboard Connector D 9 The Mouse Connector 0 10 1 4 Speaker Connector D 10 1x5 Power Good LED Connector 0 11 1x2 HDD LED Connector 0 11 1x2 Reset Switch Connector 0 11 1 2 Fan Connector D 12 1x6 3 3V Power Connector J5 D 12 1X12 Power Gonnecltor oid ed aei 0 12 AUXS ON OFF Connector
301. s WT 1 5 TAG DTY S2 input tied to WT S3 input and pulled high Leave pulled high for normal operation TRES 23 TAOE OE_STAT and OE_TAG signals wired together amp pulled up Leave pulled up for normal operation 2 1 6 System Interface Table 2 8 System Interface Signals IGN PCI ADS1 ADO1 02 57 660 Ignore PCI AD 31 input This signal is required when the Intel SIO is the PCI master because it does not latch ISA MASTER on posted ISA writes to O to 16M IGN PCI AD31 is used to allow ISA busmasters to access system memory when the SIO is used as the ISA bridge The 664 expects the memory address to appear in the range of 0 to 16M it actually works over the entire 0 2G range during the address phase when IGN PCI AD31 is asserted and then maps the access to system memory at 0 to 16M Itis usually generated by ANDing all of the active PCI bus grants see note 1 IGN PCI AD31 must be valid on the PCI clock before FRAME is sampled active GNT 0 IGN PCI AD31 GNT n 664 STOP CLK B29 R1 F04 660 input Prepares the 660 for stopping the CPU during power EN U2 151 management This feature is not supported Leave this pin pulled high for normal operation Exceptions INT_TO_664 B31 U2 55 660 INT REQ Interrupt request input The 660 synchronizes this signal from the interrupt controller to the CPU bus clock and passes it through to the CPU as an interrupt INT 60 CPU INT In
302. s INT to report certain error conditions but this function is not used by the MCM The only reason that the 660 connects to INT_CPU is to be able to use it in reporting errors to the 601 CPU When the bridge is not in 601 error reporting mode the path though the 660 from INT REQto INT_CPU is functionally an inverting latch The CPU does not need the interrupt to be synchronized to the CPU clock and typical interrupt controllers feature programmable output polarity so if the target system is not using a 601 then the interrupt can be wired around the 660 without being connected to the 660 In this case tie the INT REQ input inactive This could have been done on the example planar the current connectivity illustrates the use of the 660 pins G5220297 00 8 1 nt a Section 8 Exceptions Preliminary PowerPc Not used on MCM Error Reporting 12601 Type 0 Other Error INT REQ INT CPU CLK Figure 8 1 Conceptual Block Diagram of INT Logic 8 1 3 Interrupt Acknowledge Transactions To perform an interrupt acknowledge operation the CPU initiates a single byte read to ad dress BFFF FFFO This causes the 660 to arbitrate for the PCI bus and then to initiate a single byte PCI Interrupt Acknowledge transaction with PCI C BE O amp active is active regardless of the endian mode of the 660 The PCI Interrupt Acknowledge transaction that the 660 generates is sim
303. s ISA Master operations to system memory G5220297 00 5 1 Section 5 PCI Bus Preliminary PowerPc 51 PCI Transaction Decoding When a PCI busmaster initiates a transaction on the PCI bus the transaction either misses all of the targets and is master aborted or it is claimed by a PCI target The target can be either MCM system memory via the 660 or another PCI target 511 PCI Transaction Decoding By Bus Command Table 5 1 shows the response of the 660 and other agents to various PCI bus transactions initiated by a PCI busmaster other than the 660 The 660 ignores No response all PCI bus transactions except PCI memory read and write transactions which it decodes as possible system memory accesses Table 5 1 MCM Response to PCI C 3 0 Bus Commands Command Initiate this Transaction Transaction Claim the Transaction Acknowledge to initiate intended to be the target o Special Cycle ves m on owe oe e 7 100 Resewed ____ a 0101 Reseved ____ noe jma Memory Read System memory read Yes itno address conflict om Memory write ves System memory write Yes if no address confict 1000 Reseved ____ None o 1001 Resewed ____ noe ma 1010 Configuration Read No Only 660 1011 Configuration Write No Only 660 pa Memory Re
304. s driven to the inverse of INT REQ Drive TEST continuously high and MIO TEST continuously low for correct operation AOS RR MMRS Table 8 4 663 Pin Reset State MEM 1 PCI AD 81 0 C2P WRL OPEN MEM BE 2 3 PCI AD OEs CPU CLK MEM 0 7 PCI EXT SEL CPU DATA 00 63 MEM DATA 63 0 PCI IRDY CPU DATA MEM DATA OE PCI OL OPEN CPU DPAR O 7 MEM ERR PCI OUT SEL CPU PAR ERR MEM RD SMPL PCI TRDY CPU RDL OPEN MEM WRL OPEN ROM LOAD CRS C2PWXS MIO TEST SBE DUAL_CTRL_REF ECC_LE SEL MWS_P2MRXS TEST Note For correct operation TEST must always be driven high and MIO_TEST must always be driven low G5220297 00 8 19 a Section 8 Exceptions Preliminary Power 8 3 2 2 660 Configuration Strapping There are two strapping options for 660 system configuration information which is required before the processor can execute and which therefore cannot be programmed into the 660 Configuration strapping is accomplished by attaching a pullup or pulldown resister to the specified 664 output pin During reset the 664 tri states these outputs allowing them to assume the level to which they are strapped When RESET is deasserted the 664 reads in the value from these pins Table 8 5 shows the strapping options and their associated pins Pullup resistors should be 1
305. sactions but this may have unpredictable effects 8 1 6 Planar Interrupt Assignments In general program ISA interrupts as edge sensitive Program PCI interrupts as level sensi tive Interrupts are assigned to priority levels per ISA conventions Table 8 1 shows the in terrupt assignments of the planar IRQ 0 7 connect to the master controller and IRQ 8 15 connect to the cascaded controller Figure 8 3 shows the connection of the PCI interrupts G5220297 00 8 3 Section 8 Exceptions Preliminary PowerPc Table 8 1 Mapping of PCI Memory Space Part 1 f npn 3 WwerrOwwerb WemaioSIO _2 Keyboards TT s AMOS DEL NE 9 2M 1 2 1 11 12 13 14 15 3 4 5 7 1 PROS 4 Form gt BARO 15 Br me 3 Denam Parcs 4 TT w samono 5 aay 1 I M ooo 8 Pulledup amos 39 Par Pone sefom S man See Paw PCLINTAR seors PCI Slot 1 J26 PIRQ
306. se utilities allow viewing of the system configuration as well as the ability to change device configurations console selection boot devices and the date and time These functions are described in the following sections 10 4 1 System Console The system console can be either a screen oriented video display or a line oriented serial terminal The example screens shown in this section show the S3 video keyboard inter face When using a serial terminal the configuration utilities will prompt for numeric input for each prompt instead of using the arrow keys All choices and options are the same as for the screen oriented menus The configuration of the reference board as shipped is set for S3 video Keyboard console In the case that either the video adapter or the keyboard fails the power on test the system 10 6 G5220297 00 PowerPc Preliminary Section 10 Firmware console will default to serial port 1 The baud rate for the serial console is specified in the configuration menus The value as shipped is 9600 baud 10 4 2 System Initialization The logo screen shown in Figure 10 6 is displayed at power on The logo screen is active while the system initializes and tests memory and performs a scan of the SCSI bus to deter mine what SCSI devices are installed PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved THEE RN HEHEHEHE HHH HERES
307. sed to connect the to the planar Each column is attached to the MCM by an eutectic solder joint The solder at this point melts at a higher temperature than the solder used for the column itself The is then sol dered to the planar again using an eutectic solder The solder column process is robust and offers a lower impedance It is also one of the higher density interconnection methods Figure 1 5 MCM Solder Columns For more information on solder columns assembly and rework see Ceramic Ball and Col umn Grid Array Surface Mount Assembly Rework document number APD SBSC 101 0 G5220297 00 O PowerPc Preliminary Section 1 Introduction 1 4 Incorporating the MCM into a System Design The captures in one ceramic package all key components of a PowerPC system design that resides on a CPU s local bus The MCM s primary ports of interface to the rest of a system are the PCI bus and the system memory DRAM port Other signals that con nect the MCM to a system fall into the following groups Processor PLL configuration 970 configuration Signal nets broken at the level for test purposes and need to be reconnected on the planar RISCWatch interface 60X bus signals requiring pullup pulldown connections at the planar L2 cache configuration and presence detect Clock nets broken at the level to allow net length matching with planar resident clock nets
308. sion ID PCI Standard Programming Interface PCI Subclass Code PCI Class Code PCI Cache Line Size PCI Latency Timer PCI Header Type POI Bultin BIS Coni __ mex FT Polmemptline mexe Fj PolmemuptPn mexe FT POIMIN ONT Fj __ mes __ __ PPorBusNumber me RFT POSubadmaeBusNumer mxn R lT BOI Discomect Comer _ me jaw PCI Special Cycle Address BOR R 7 __ jaw jT jaw jT CAE mecs jaw PoBsEmrSaus jaw MININ jajaja ano aj aja G5220297 00 5 15 Section 5 PCI Bus Preliminary PowerPc 5 16 G5220297 00 PowerPc Preliminary Section 6 ROM Section 6 ROM implements a 2M ROM space from 4G 2M to 4G on the CPU bus by means ofthe 660 bridge The 660 provides two boot ROM device access methods which minimize pin and package count while still allowing a byte wide Flash ROM device to source 8 byte wide data The ROM 15 indicated to the 660 on the strapping pin configuration bits during power on reset POR See section 8 3 2 2 The ROM access method used by the example planar is referred to as the direct attach ROM mode t
309. sponse No PCI transaction only 1101 Read atomic Memory read operation PCI read transaction burst 1110 External control Address 660 asserts all ones on the CPU data bus Asserts and eciwx only if the transaction is not claimed by another 60X bus device No PCI transaction No other response 1111 Read with intent to Burst Memory read operation PCI read transaction modify atomic stwcx Note 1 SBR means Single Beat Read SBW means Single Beat Write Transfer types in Table 3 1 that have the same response are handled identically by the bridge For example if the address is the same the bridge generates the same memory read transaction for transfer types 0101 0111 1101 and 1111 The 660 does not generate PCI or system memory transactions in response to address only transfers The bridge does drive all ones onto the CPU bus and signals TA during an eciwx if no other CPU bus agent claims the transfer G5220297 00 3 3 PowerPc References in the remainder of this document to a CPU read assume one of the transfer types in Table 3 1 that produce the read response from the 660 Likewise references to a CPU write refer to those transfer type that produce the write response Section 3 CPU amp L2 3 3 System Response by CPU Bus Address Range The 660 determines the target of a CPU busmaster transaction based on the CPU bus ad dress range as shown in Tabl
310. sserted through U5 the bus clock in which is asserted U6 The CPU drives A 0 31 during transactions mastered by the CPU The 660 drives A 0 31 while broadcasting CPU address bus snoop cycles in response to a PCI to memory transaction R30 CPU bus agents pu CPU bus address acknowledge The CPU bus target 660 or external l O CPU bus target asserts AACK to signal the end of the current address tenure 660 also asserts AACK for one clock to signal the end of a broadcast snoop cycle is an input to the 664 when a CPU bus target claims the current transaction by means of L2 CLAIM is always an input to the CPU CPU bus Address Bus Busy While asserted the address bus is busy The 660 does not touch this signal CPU bus Address Parity One bit of odd see DP 0 7 parity per byte APO maps to A 0 7 AP1 maps to A 8 15 AP2 maps to A 16 23 and AP3 maps to A 24 31 The 660 does not check address parity The CPU and 660 snoop A 0 31 during transactions initiated by other CPU Address Parity Error output The CPU signals address parity errors using this open drain output The 660 does not touch this signal CPU bus Address Retry ARTRY is asserted by a CPU bus device either the target or a snooping master to signal that the current address tenure needs to be rerun at a later time The 660 samples ARTRY during broadcast snoops and transactions by CPU busmasters on the second cloc
311. sses to unoccupied space are not decoded Unless the IGN PCI AD31 signal is asserted PCI memory accesses in the 0 to 2G ad dress range are ignored by the 660 There is no system memory access no snoop cycle and the 660 does not claim the transaction When the IGN PCI AD31 signal is asserted the 660 maps PCI memory accesses from 0 to 2G directly to system memory at 0 to 2G PCI memory accesses from 2G to 4G are mapped to system memory from 0 to 2G PCI memory accesses that are mapped to system memory cause the 660 to claim the transaction access system memory and arbitrate for the CPU bus and broadcast a snoop operation on the CPU bus A detailed description of the snoop process is presented in the 660 User s Manual Table 5 3 gives a more detailed breakdown of the MCM response to PCI memory transac tions in the 0 to 2G range Note that the preferred mapping of PCI memory so that it can be accessed both by the CPU and by PCI busmasters is from 16M to 1G 2M Table 5 3 Mapping of PCI Memory Space Part 2 PCI Bus Address Target Resource System Memory Address Snoop Address 2G to 4G System memory 1 0 to 2G 0 to 2G 1G 2M to 2G Reserved 2 No system memory access No snoop 16M to 1G 2M PCI Memory The 660 ignores PCI memory transactions in this range 0 to 16M PCI ISA Memory 3 Notes 1 The 660 maps PCI busmaster memory transactions in the 2G to 4G range to sys tem memory and the CPU is unable to initiate PCI memory transactio
312. st 4 byte transfer then the CPU is retried If the PCI retries on the second 4 byte transfer then the 660 retries the PCI write 3 5 3 CPU to PCI Memory Transactions CPU transfers from 3G to 4G 2M are mapped to the PCI bus as memory transactions 3 5 4 CPU to PCI I O Transactions CPU transfers from 2G 16M to 3G 8M are mapped to the PCI bus as I O transactions In compliance with the PCI specification the 660 master aborts all I O transactions that are not claimed by a PCI agent 3 5 5 CPU to PCI Configuration Transactions The MOM allows the CPU to generate type 0 and type 1 PCI configuration cycles The CPU initiates a transfer to the appropriate address The 660 decodes the cycle and generates a request to the PCI arbiter in the SIO When the PCI bus is acquired the 660 enables its PCI AD drivers and drives the address onto the PCI AD lines for one PCI clock before it asserts PCI Predriving the PCI AD lines for one clock before asserting PCI FRAMEXZ allows the IDSELs to be resistively connected to the PCI AD 31 0 bus at the system level The transfer size must match the capabilities of the target PCI device for configuration cycles The MCM supports 1 2 3 and 4 byte transfers that do not cross a 4 byte bound ary Address unmunging and data byte swapping follow the same rules as those for system memory with respect to BE and LE modes of operation Address unmunging has no effect on the CPU address lines which co
313. ster C1h bit or register C1h bit 1 G5220297 00 8 7 TES a Section 8 Exceptions Preliminary PowerPc The indexed register set uses the same mask and error reset bits for XATS and for unsup ported transfer types This error can also be controlled by the 650 compatible register set The mask cannot be controlled by means of this register set If an error is detected the status bit at 8000 0844h bit O is cleared The address is saved at BFFF EFFOh This error can be reset by reading BFFF EFFOh The 650 compatible register set does not differentiate between XATS er rors and unsupported transfer type errors 8 2 3 3 CPU to Memory Writes During CPU to memory writes the CPU drives data parity information onto the CPU data bus Correct parity is then generated in the 660 and written to DRAM memory along with the data The L2 SRAM is updated when required with the data and the parity information that the CPU drove onto the CPU data bus During CPU to memory writes the 660 checks the data parity sourced by the CPU and normally reports any detected parity errors via TEA 8 2 3 4 CPU to Memory Reads The is initially configured to check memory data using parity However the 660 can be programmed to execute an error checking and correction ECC algorithm on the memory data by generating ECC check bits during memory writes and checking correct ing the data during memory reads ECC can be implemented using normal parity DRAM
314. ster is set and no address is captured in the error address register 8 2 5 PCI to Memory Transaction Errors 8 2 5 1 PCI to Memory Writes During PCI to memory writes the 660 generates the data parity that is written into DRAM memory The bridge also checks the parity of the data and asserts PCI if it detects a data parity error 8 2 5 2 PCI to Memory Reads During PCI to memory reads the 660 checks the parity of the memory data and then gen erates the data parity that is driven onto the PCI bus If there is a parity error in the data par ity returned to the 660 from the DRAM the bridge drives PCI PAR incorrectly to propagate the parity error and also reports the error to the CPU via MCP The data beat with the bad parity is nottarget aborted because doing so would slow all data beats for one PCI clock TRDY is generated before the data is known good However if the agent is bursting and there is another transfer in the burst the next cycle is stopped with target abort protocol During PCI to memory reads the 660 also samples the PCI PERRZ signal which other agents can be programmed to activate when they detect a PCI parity error 8 2 5 3 Out of Bounds PCI Memory Accesses If a PCI busmaster runs a cycle to a system memory address above the top of physical memory no one will respond and the initiator master aborts the cycle The initiating bus master must be programmed to notify the system of master aborts as need
315. t 182 EBET ToS lt gt 162 EUET TH2 lt lt 129 i334 B66T SS ESG 20 1 3 41004 1597 TA385SAUOZH 1111 NUNISO3 NOTSIASY NOILIUHOdHOOD WAT S667 LHOIHAdOO JHOY V c cE Wd SE SE 2E BE 5E Sy pa 2208 2998 POA cane 29559 2049 2189 2119 gine 9179 8198 913g SSJHdAO 504 SNOI LODO 1 14420504214 UHLIX4d SS3HdA 5 S408 aM Prise Sy 99 OQ c pu tm S 40 T JLIAM GOGWIL 4735 ANY YaLNNOD 15958 HLIM 2IIUIS SIIONOHHONAS 118 87 X 3898 800 cou EOC Sou 90d 20d 800 Sade yoda Cf 613420504214 NO A ML23HIU StI NOISHd 3HOH 118 87 X vVTBTFOWHI eu 5 Qyddy7Sdy W ONT WINS IND Wes SS C DH HONS lt 2602 lt 1021 228 888 88
316. t shown fields must contain PC compatible values i e acceptable to DOS to avoid con fusing PC software The CV fields however are ignored by the firmware Boot Ind Head Sys Ind Head 32 bit start RBA zero based LE 32 bit RBA count one based LE Partition Begin Sector Cyl Partition End Sector Cyl Beginning Sector Number of Sectors RBA Relative Block Address in units of 512 bytes LE Little Endian Figure 10 4 Partition Table Entry for PowerPC Reference Platform The 32 bit start RBA is zero based The 32 bit count RBA is one based and indicates the number of 512 byte blocks The count is always specified in 512 byte blocks even if the physical sectoring of the target devices is not in 512 byte sectors 10 3 2 Loading the Load Image This section describes the layout of the PowerPC 0x41 type partition and the process of loading the load image 10 4 G5220297 00 PowerPc Preliminary Section 10 Firmware qe 0 PC Compatibility Block 512 Entry Point Offset LE 516 Load Image Length LE Load Image Flag Field 520 OS ID 521 522 Partition 554 Reserved1 1024 OS Specific Field Optional Code Section of the Load Image Reserved2 RBA Count 512 Figure 10 5 PowerPC Reference Platform Partition The layout for the Ox41 type partition is shown in Figure 10 5 The PC compatibility block in the
317. t to 00 for all PCI transactions except I O cycles ojejo 0 0 1 1 0 0 1 1 AL wi wi H G5220297 00 11 9 Li Li p Section 11 Endian Preliminary PowerPc 11 7 Two Byte Transfers Figure 11 4 gives an example of double byte write data ab at address Big Endian Little Endian Swap Off Memory Swap On Memory Figure 11 4 Double Byte Write Data ab at Address xxxx 0 Table 11 9 and Table 11 10 illustrate all cases that can occur The columns of Table 11 9 have these meanings e The first column indicates target address e g the address of the byte coded into a store half word instruction e The next two columns show the state of the address pins for BE mode e The next two columns show the state of the address pins for the same target data when the machine is in LE mode e The remaining columns show the CASs and the PCI byte enables associated with the target data e The notes indicate which combinations either do not occur at the pins because of internal exceptions or are not supported externally 11 10 G5220297 00 PowerPc Preliminary Section 11 Endian For 2 byte transfers Table 11 9 holds Table 11 9 Two Byte Transfer Information PROG BE MODE LE MODE BE OR LE BE OR LE BE OR LE TARG 603e BE x or w 110 Target CAS 0 7 PCI ADDR add a29 31 Add a29 31 bytes 0 7 A
318. tected too late to be reported using TEA and errors that are not a direct result of the current CPU transfer are reported using MCP For example memory parity errors occurring while a PCI busmaster is accessing memory are reported using There are three separate data error checking systems in the 660 CPU bus memory and PCI bus The 660 does not generate or check CPU address bus parity Each error that can be detected has an associated mask If the error is masked then the detection of that error condition is disabled There are also assertion masks for the MCP TEA and PCI signals that prevent reporting of any error by means of that signal these masks do not affect the detection of the error Once an error is detected and the appropriate status address and control information is saved the detection of all subsequent error detection is disabled until the current error is reset For more information on error handing see the 660 User s Manual 8 2 1 CPU Bus Related Errors 8 2 1 1 CPU Bus Error Types e Errors Reported With TEA cycle still active CPU bus unsupported transfer type CPU bus unsupported transfer size CPU bus XATS asserted e Errors Reported With MCP cycle has ended CPU data bus parity error CPU bus write to locked flash CPU bus memory select error Memory parity error during CPU to memory transfer Memory single bit ECC error trigger exceeded during CPU to memory transfer Memory
319. ter Assertion of PCI IRDY3t indicates that the PCI initiator is ready to complete this data phase PCI LOCK 660 PCI lock This signal is used to allow PCI masters to establish re source lock of one cache line of system memory The 660 never asserts LOCK as a master but it honors PCI busmaster locks of system memory PCI PAR 660 PCI parity Even parity across AD 31 0 and the C BE 3 0 lines PCI PARis valid one PCI bus clock after either an address or data tenure The PCI device that drove the PCI AD lines is responsible for driving PCI PAR The 660 checks and drives PCI parity PCI 5 660 PCI parity error PCI is asserted by PCI device receiving the data PCI is sampled on the second PCI clock after the PCI AD lines are sampled PCI SERR Z 5 660 PCI system error PCI is asserted for one PCI clock when catastrophic failure is detected while the 660 is a PCI target PCI SERRZ is not monitored by the 660 The 660 asserts PCI_SERR for certain PCI bus errors PCI STOP 01 U2 203 O 660 PCI stop The target of the current PCI transaction can assert PCI to indicate that the PCI target wants to end the current trans action Data transfer can still take place if the target also asserts PCI TRDYAZ but that is the final data tenure PCI TRDYs 02 02 02 660 PCI target ready The target of the current PCI transaction drives U3 168 PCI
320. terials at your expense NO IMPLIED LICENSE TO IBM INTELLECTUAL PROPERTY Notwithstanding the fact that IBM is hereby providing design information for your convenience you expressly understand and agree that except for the rights granted under sections 1 and 2 above no right or license of any type is granted expressly or impliedly under any pat ents copyrights trade secrets trademarks or other intellectual property rights of IBM Moreover you understand and agree that in the eventyou wish to be granted any license beyondthe scope ofthe expressly stated herein you will contact IBM s Intellectual Property Licens ing and Services Office currently located at 500 Columbus Avenue Thornwood N Y or such other IBM offices responsible for the licens ing of IBM intellectual property when you seek the license YOUR ASSUMPTION OF RISK You shall be solely responsible for your success in designing developing manufacturing distributing and marketing any product s or portion s where use of all or any part of the 100 MHz PPC 603e is involved You are solely responsible for any claims warranties representations indemnities and liabilities you undertake with your customers distributors resellers or others concerning any product s or portion s of product s where use of all or any part ofthe MCM is involved You assume the riskthat IBM may introduce other Reference Design that are somehow better than the which is the subject o
321. terrupt input The CPU initiates an interrupt if MSR EE is set 603e else it ignores the input Active low level sensitive unlatched X INT 60 660 INT CPUst CPU interrupt output The 660 asserts INT_CPU to signal the CPU to run an interrupt cycle The software is expected to eventually run PCI interrupt acknowledge transaction to get the interrupt vector 660 can assert INT CPU response to an INT REQ input Normally connected to INT 60X3 NMI FROM 660 REQ input Non maskable interrupt request When detected ISABRDG active normally from the ISA bridge an error is reported to the CPU POWER GOOD 660 While this pin is low all latches in the 664 enter a pre defined state Clocking mode is re sampled and ROM write lockout is cleared ROM ROM OE 660 ROM output enable ROM_OE enables direct attached ROM This signal is always high during remote ROM operation ROM WEZ 660 ROM write enable Write enable for flash ROM for direct attach ROM This signal is always high during remote ROM operation 2 10 G5220297 00 PowerPc Preliminary Section 2 Signals Table 2 8 System Interface Signals Continued Daisy Chain Daisy01 E04 D05 The DAISYxx columns are arranged in pairs which are connected to Daisy02 E06 D07 each other For example Daisy01 consists of columns E04 and 005 which are connected to each other Daisy03 E08 D09
322. the PC environment The boot record is composed of a PC compatibility block and a partition table To support media interchange the PC compatibility block may contain an x86 type program The entries in the partition table identify the PowerPC Reference Platform boot partition and its location in the media The layout of the boot record must be designed as shown in Figure 10 1 The first 446 bytes of the boot record contain a PC compatibility block the next four 16 byte entries make up a partition table totalling 64 bytes and the last 2 bytes contain a signature 0 0 PC Compatibility Block 0x1BE 446 Partition Entry 1 0x1CE 462 Partition Entry 2 0x1DE 478 Partition Entry 3 OxQ1lEE 494 Partition Entry 4 Ox1FE 510 0x55 OxAA Figure 10 1 Boot Record 10 3 1 1 PC Partition Table Entry To support media interchange with the PC the PowerPC Reference Platform defines the format of the partition table entry based on that for the PC This section describes the format of the PC partition table entry which is shown in Figure 10 2 0 Partition Begin 4 Boot Ind Head Sector Cyl Partition End Sys Ind Head Sector Cyl Beginning Sector 12 Low Word LE High Word LE Number of Sectors Low Word LE High Word LE LE Little Endian Figure 10 2 Partition Table Entry 10 2 G5220297 00 Power Preliminary Section 10 Firmware Partition Begin
323. the speed of each serial port Baud rates for the two serial ports are independent If a serial port is used as the system console setthis value to match the baud rate of the terminal View SCSI Devices The SCSI devices screen shows the devices found on the SCSI bus during power on initial ization The string shown is the SCSI device s response to the SCSI inquiry command Ac cording to the SCSI specification this data comprises the manufacturer s ID device model number and device revision level A sample screen is shown in Figure 10 11 PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved SCSI SCSI SCSI SCSI SCSI SCSI SCSI Device Device Device Device Device Device Device 0 1 2 3 4 5 6 Previous Menu SCSI Devices None None None None None None IBM MXT 540SL H Press to select item Press Enter to perform action Figure 10 11 SCSI Devices Screen 10 12 G5220297 00 PowerPc Preliminary Section 10 Firmware Set Boot Devices The boot devices menu allows the user to select which devices are queried for boot images and in what order they are selected for boot Allowable selections are one of the two floppy disk drives any of six SCSI drive ID numbers either of two IDE disk drives or no device selected The default configuration is shown in Figure 10 12 In this configuration the sys tem will attempt to find a boot image on the
324. tion is used to allow more than four partitions in a device The boot record in the extended DOS partition has a partition table with two entries but does not con tain the code section The first entry describes the location size and type of the partition The second entry points to the next partition in the chained list of partitions The last parti tion in the list is indicated with a system indicator value of zero in the second entry of its partition table Because of the DOS format limitations for a device partition a partition which starts at a location beyond the first 1 gigabyte is located by using an enhanced format shown in Figure 10 3 G5220297 00 10 3 Section 10 Firmware Preliminary PowerPc 0 Partition Begin Boot Ind 1 1 1 Partition End Sys Ind 1 1 1 Beginning Sector 32 bit start RBA zero based LE Number of Sectors x 32 bit RBA count one based LE LE Little Endi 1 All ones in the field Relative Block Address in units of 512 bytes Figure 10 3 Partition Table Entry Format for an Extended Partition 10 3 1 3 PowerPC Reference Platform Partition Table Entry The Power PC Reference Platform partition table entry see Figure 10 4 is identified by the 0x41 value in the system indicator field other fields are ignored by the firmware ex cept for the Beginning Sector and Number of Sectors fields The CV Compatible Value no
325. tion with data 0012 3456h writes 56h to ROM location 00 1234h Only single beat four byte write transfers store word are sup ported A ROM write is considered to be a BCR operation The ROM write BCR is detailed in Section 6 3 1 The ROM write discussion assumes that the system is in big endian mode For the effects of little endian mode operation on ROM reads see Section 6 1 2 3 In direct attach mode the ROM is attached to the 660 as shown in Figure 6 3 System ROM Address Data Control Figure 6 3 ROM Connections 6 1 2 1 ROM Write Sequence This case assumes that the PCI bus is parked on the CPU Initially the CPU drives the ad dress and address attributes onto the CPU bus and asserts TS The 660 decodes the CPU transfer as a ROM write transaction which is a BCR transaction The 660 initiates a BCR transaction by asserting PCI on the rising edge of PCI CLK Note that the 660 is driving PCI AD 23 0 with the ROM address and PCI AD 31 24 with the ROM data On the next PCI the 660 negates PCI FRAME and asserts IRDY Four PCI CLKs after the 660 asserts PCI FRAMEZ it asserts ROM WEZ for two PCI CLKs The 660 completes the PCI transaction by deasserting PCI IRDY The 660 signals and AACK to the CPU to signal transfer completion to the CPU Also note that PCI DEV SEL PCI TRDY PCI 5 and ROM _ are negated throughout the transaction 6 1 2 2 Write Protection Write prot
326. to IBM DISCLAIMER OF WARRANTY IBM does not represent or warrant that the 100 MHz PPC 603e MCM which may contain prototype items a meets any particular require ments b operates uninterrupted c is error free or d is non infringing of any patent copyright or other intellectual property right of any third party IBM makes no representation or warranty regarding the performance or compatibility that may be obtained from the use of the MCM or that the is adequate for any use The may contain errors and may not provide the level of completeness functionality support performance reliability or ease of use available with other products whether or not similar to the MCM IBM does not represent or warrant that errors or other defects will be identified or corrected THE 100 MHz PPC 603e MCM IS PROVIDED AS IS WITH ALL FAULTS WITHOUT WARRANTY OF ANY KIND EX PRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE MCM IS WITH YOU Some jurisdictions do not allow exclusion of implied warranties so the above exclusions may not apply to you G5220297 00 iii Pewer LIMITATION OF REMEDIES IBM s entire cumulative liability and your exclusive remedy for damages for all causes claims or actions wherever and whenever asserted relating in any way to the subject matter of this
327. uctions before and after the dummy write This produces the following sequence 1 The CPU initiates a CPU to PCI write to produce the final part of the data set The CPU address tenure completes and the PCI write is posted 2 Some time later the 660 initiates this transaction on the PCI bus The transaction takes an unknown amount of time to complete If the transaction is retried on the PCI bus the 660 will continue to reinnitiate the transaction until it completes 3 After 1 and before 4 the CPU initiates a dummy CPU to PCI write to flush the posted write buffer The 660 does not allow this second CPU to PCI write to complete on the CPU bus by being written into the 660 posted write buffer until the first CPU to PCI transaction the data set write actually completes on the PCI bus This prevents the following transaction the flag write from completing before the data set write completes 4 The CPU initiates the CPU to memory flag write 5 5 2 3 Solution 2 Change the flag write procedure Design the device drivers such that the Consumer receives the flag in some way that ensures that the data set write completes before the flag write completes One way to do this is to cause the CPU to write the flag to the agent using a PCI IO or memory write instead of a CPU to memory write e If the flag write is PCI memory write then as in item in option 1 this flag write forces the preceeding data set write to complete before
328. ured for remote ROM operation the 660 forwards all CPU to ROM write transfers to the PCI bus as memory writes The PCI agent that is controlling the re mote ROM acts as the PCI target during CPU to ROM write transfers executes the write cycle to the ROM and may provide ROM write protection 6 2 2 1 Write Sequence A CPU busmaster begins a remote ROM write transaction by initiating a one byte single beat memory write transfer to CPU bus address range 4G 2M to 4G FF80 0000h to FFFF FFFFh The 660 decodes the CPU transfer arbitrates for the PCI bus and initiates a memory write PCI transaction to the same address in the 4G 2M to 4G address range The PCI agent that is controlling the remote ROM such as the PCI to ISA Bridge claims the transaction manages the write cycle to the ROM device and signals TRDY The 660 then completes the PCI transaction and signals and to the CPU Note that remote ROM writes are neither posted or pipelined 6 2 2 2 Write Protection Write protection can be provided by the PCI agent that controls the ROM In addition some flash ROM devices can have the means to permanently lock out sectors by writing control sequences The 660 also has a write lockout in the Bridge Chipset Options 2 register bit 0 of index BBh 6 2 2 3 Address Size Alignment and Endian Mode In remote ROM mode CPU memory writes from 4G 2M to 4G cause the 660 to generate PCI bus memory write transacti
329. urrent flows In LSSD test mode the pin controls the drivers of the 663 and the 664 Assertion of the DI pin asynchronously causes all of the 663 664 output drivers push pull tri state open driver or bi directional to be tristated In LSSD test mode the pin controls the receivers of the 663 and the 664 Assertion of causes all of the 663 or 664 inputs to report a certain pattern to the internal logic This has no effect on the external operation of the device that can be used by an external customer The 660 must be reset properly after leaving LSSD test mode in order to assure correct normal mode operation No further information on the use of the 660 test pins is expected to be released G5220297 00 8 21 Section 8 Exceptions Preliminary Power 8 22 5220297 00 PowerPc Preliminary E Section 9 Set Up and Registers The following subsections represent activities carried out early in the boot firmware On the MOM all initialization registers are contained in the 603e nd the 660 bridge controller chips 9 1 CPU Initialization The 603 CPU exits the reset state with the L1 cache disabled and bus error checking dis abled All memory pages 2G to 4G must be marked as
330. using the up and down arrow keys on the keyboard and are changed with the left and right arrow keys Options on the menu are discussed below PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Device Configuration Select Console Device S3 Video Keyboard Set Serial Port 1 Speed 9600 Baud Set Serial Port 2 Speed 9600 Baud Go to Previous Menu Press to select item Press lt gt to change item Figure 10 10 Device Configuration Screen Any changes made device configuration are saved when the Save and Exit option on the main menu is selected Exiting the system configuration utility in any other manner will cause device configuration changes to be lost Select Console Device The console selection box allows the selection of an option for the system console Serial Port 1 or 2 Console input and output will be transmitted and received through a serial port on an adapter card Console input and out put will be transmitted and received at the baud rate selected with Serial Port Speed S3 Video Keyboard Console output will be displayed on a video monitor connected to an S3 PCI video adapter console input will be received from a keyboard connected to the keyboard connector on the refer ence board G5220297 00 10 11 Section 10 Firmware Set Serial Port 1 or 2 Speed Preliminary PowerPc The serial port speed selection box sets
331. y not be affiliated with the current transaction The 660 asserts in the event of a catastrophic or unrecoverable system error The 660 asserts for two CPU bus cycles PLL CFGO CPU Phase Lock Loop Configuration Inputs See the 603e UM for more PLL CFG1 information Normally set to PLL_CFG 0 3 1100 for 99MHz CPU core PLL CFG2 and 66MHz CPU bus operation PLL_CFG3 QACK_60X 017 R1 E03 CPU Quiesce Acknowledge input Indicates that the other CPU bus U1 235 agents have ceased any bus activity that the CPU has to snoop is sampled at the negation of HRESET to select 32 bit mode Drive QACK low during HRESET with an open collector gate to select 64 bit mode See the applications section for details QREQ 60X4 C U1 31 CPU QREQ Quiescence Request output The CPU is requesting a low power mode See the 603 UM RSRV_60X U1 232 Represents the state of the Reservation bit See 603e UM SHD 02 141 660 Shared output The function of this pin is to restore the SHD netto a high state after it has been asserted This pin is not used and should be weakly pulled up 18 D27 SMI ALO2 R1 F05 CPU System Management Interrupt The CPU initiates an interrupt if 01 187 MSR EE is set 6036 else it ignores the input Active low level sensitive unlatched 031 SRESET CPU Soft RESET input Async falling edge sensitive Initiates reset exception See 603e UM for more information TA AA16 CPU bus Transfer Acknowledge
332. yboard Mouse B 4 B 1 5 7 Real Time Glock RTC ales B 4 B 1 5 8 PCI Adapter Card Presence Detect Register B 5 B 1 5 9 L2 SRAM Identification Register 5 B 1 5 10 Planar ID Detection Register B 5 B 1 5 11 DRAM Presence Detection B 6 1 5 12 DRAM SIMM 1 2 Memory ID B 6 B 1 5 13 DRAM SIMM 3 4 Memory ID Register B 6 B 1 6 Miscellanbolis B 7 B 1 6 1 Speaker Support EE RUE B 7 System iis aE E E E SES B 7 B 2 1 System Register Support B 7 B 2 1 1 External Register Support B 7 B 2 1 2 Internal deis eL EXER Xu AEN a B 8 B 2 2 Signal Descriptions obire EET pb eet te e B 10 B 2 3 EPLD Design 1 B 12 B23 ISI Wet Cx 12 sess PREX ROC ECCO sw dere ony RR OE B 14 Xii G5220297 00 PowerPc Appendix C Planar Set Up and Registers C 1 ISA Bridge SIO 1 1 Summary of SIO Configuration Registers C 2 Example Planar Combined Register Listing
333. ycle on behalf of a PCI busmaster accessing system memory CPU bus Transfer Size in number of bytes The TSIZ lines are valid with the CPU address lines CPU bus TT 0 4 Transfer Type Indicates the type of transaction currently in progress The TT lines are valid with the CPU address lines TT2 connects only to the CPU Normally connect TT2 to TT2 664 660 TT2 Connect to TT2 WT 60 D15 R1 HO3 CPU Write Through output Asserted to indicate that a single beat U1 236 O transaction is write through XATS 7 R1 B03 pu CPU bus eXtended Address Transfer Start for PIO operations which are 02 129 not supported by the 660 If XATS is asserted the 660 generates a TEA error to the CPU regardless of the setting of MASK_TEA The 603e CPU does not have an XATS output This pin is not normally connected 2 1 3 PCI Bus Table 2 5 PCI Bus Signals Signal MCM Nodes Description 664 PCI REQ2 01 U2 58 660 PCI REQX PCI bus request The 660 asserts PCI REQX to the PCI bus arbiter to request the PCI bus CPU 6644 02 02 54 660 PCI GNT4 PCI bus grant input PCI GNT4 is driven by the PCI bus arbiter in response to the 660 asserting PCI to request the PCI bus PCI AD 31 0 660 PCI multiplexed Address Data bus A PCI bus transaction consists of an address phase followed by one or more data phases The address tenure is defined as one PCI bus c
334. ytes transformed into 2 bus cycles P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603e bus in LE mode not supported in memory controller crosses 4 byte boundary 11 9 Three byte Transfers There are no explicit Load Store three byte instructions however three byte transfers oc cur as a result of unaligned four byte loads and stores as well as a result of move multiple and string instructions The TSIZ 3 transfers with address pins 0 1 2 3 4 or 5 may occur in BE All of the other TSIZ and address combinations produced by move multiple and string operations are the same as those produced by aligned or unaligned word and half word loads and stores Since move multiples strings and unaligned transfers cause machine checks in LE mode they are not of concern in the BE design 11 14 G5220297 00 PowerPc Preliminary Section 11 Endian 11 10 Instruction Fetches and Endian Modes Most instruction fetching is with cache on Therefore memory is fetched eight bytes wide Figure 11 6 shows the instruction alignment Example 8 byte instruction fetch 1 l2 efgh at address xxxx xxx0 Big Endian Little Endian Swap Off Memory Swap On Memory LSB S h f 7 6 5 4 3 2 1 0 m C A gt 9 b a Figure 11 6 Instruction Alignment Example G5220297 00 11 15 Li p Section 11
335. zes and alignments that the CPU can create in LE mode however all loads or stores must be at natural alignments in LE mode or the CPU will take an alignment exception Also load store multiple word and load store string word instruc tions are not supported in the CPU in LE mode 3 5 CPUto PCI Transactions Since all CPU to PCI transactions are CPU memory mapped software must in general uti lize the EIEIO instruction which enforces in order execution particularly on PCI and configuration transactions Some PCI memory operations can be sensitive to order of ac cess also See the 660 User s Manual All addresses from 2G to 4G including ROM space must be marked non cacheable See the PowerPC Reference Platform Specification The MCM supports all PCI bus protocols during CPU to PCI transactions The supports all CPU to PCI transfer sizes that do not cross 4 byte boundary and it supports 8 byte CPU to PCI writes that are aligned on an 8 byte boundary The bridge does not support CPU bursts to the PCI bus When the 660 decodes a CPU access as targeted for the PCI the 660 requests the PCI bus Once the SIO grants the PCI bus to the 660 the bridge initiates the PCI cycle and re leases the bus CPU to PCI transactions that the PCI target retries cause the 660 to deassert its PCI REQX the Bridge follows the PCI retry protocol The Bridge stays off of the PCI bus for two PCI clocks before reasserting PCI or

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