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Secured opto-electronic system for product

1. Key Fig 6 10 Implementation of cryptoprocessor with 32 bit datapath 6 3 Interconnection of cryptoprocessor with ARM7 After the whole cryptoprocessor is completed it has to be connected to the main data bus of the system This interconnection is illustrated in the Fig 6 13 The cryptoprocessor should behave as a black box which would read data from 32 bit input FIFO carry out its task and write results to 32 bit output FIFO The status should indicate accomplishment of the task and APB access controller could read this status and send it to ARM7 62 FEI DEMC EDET EZ Fig 6 11 Conversion of 4 successive 32 bit words into 128 bit word S1 b 93 x S2 Fig 6 12 Conversion of 128 bit word into 4 successive 32 bit words ARM CLOCK DOMAIN DATA DATA IN OUT CRYPTOPROCESSOR CLOCK DOMAIN L Fig 6 13 Interconnection of cryptoprocessor with ARM7 Since cryptoprocessor is separated from the rest of the system special protocol has to be created and applied on the data First 32 bits of data should contain header In this header the whole necessary configuration should by present Cryptoprocessor should access this header compare it with masks stored in special registers and decide which 63 FEI DEMC action to perform Afterwards data could be read from 32 bit input FIFO and processed
2. 16 interframe blanking lines 0x10 0x80 1280 PCLKs 553 lines 480 lines ACTIVE VIDEO Line blanking 640 by 480 pixels 0x10 0x80 37 interframe bianking lines 0x10 0x80 Fig 2 11 VGA 30fps output frame Each pixel is represented by 2 bytes 5 It depends on the chosen format how these 2 bytes will be used format can be chosen by adjusting register 0x0416 Possible choices are YUV 4 2 2 RGB 565 RGB 444 and Bayer 10 bit 5 I have chosen YUV 4 2 2 format because only grayscale image was required To obtain grayscale image only 19 FEI DEMC luminance component Y component has to be read from YUV stream I have also decided to use the resolution 320x240 half resolution According to the requirements for further image processing this resolution was suitable The design can be easily adapted to a different resolution in the future This resolution is adjusted in the camera register 0x0400 and in the output stream every second pixel is skipped and every second line is skipped too 5 This ensures the resolution 320x240 Therefore one Y component is sent per every 4 clock periods as illustrated in the Fig 2 12 to Fig 2 15 Also camera was set to transmit the Y component first and the C component chrominance as the second Fig 2 12 to Fig 2 15 illustrates the output format Signals HSYNC and VSYNC provide line and frame synchronization and PCLK pro vides pixel synchronization 5 You
3. 63 7 1 Communication model between ARM7 andaPC 66 7 2 Main window of the PC interface llle ens 67 7 3 Application in the Debug mode 68 7 4 About window in the PC interface llle 69 List of Tables Levenshtein distance of different prints and corresponding scans Basic estimation of required ARM7 cycles as well as required logic re sources for implementation of particular operations within the algorithm Architecture and implementation comparison of open source processors Comparison of code properties of open source processors Selected open source processors to be reused in cryptoprocessor 40 42 55 56 57 List of Symbols and Abbreviations 2D ABC AES AHB ALU AMBA ASB ASIC AT AT BT BCB BT Two dimensional APB Bus Controller Advanced Encryption Standard Advanced High performance Bus Arithmetic Logic Unit Advanced Microcontroller Bus Architecture Advanced Micro Devices Architectures Mat rielles pour le Traitement et la S curisation des Donn es Agence Nationale pour la Recherche France national agency for research Advanced Peripheral Bus Advanced RISC Machine IP owned by ARM Ltd Advanced System Bus Application Specific Integrated Circuit Affine Transfomation Combined Affine Transformation and Basis Transformation Borland C Builder Basis Transformation general purpose computer programming langua
4. sources are placed network of interconnections between resources has to be built up This stage is called Routing There are several options available to further optimize the Placement and Routing The last stage is to create the configuration file Back annotation can also be generated for use in Timing analysis Placement Routing configuration file generation and back annotation generation operations are carried out by Actel Designer tool Layout button The Designer tool 22 is illustrated in the Fig 3 2 We Designer 580X GEN adb ir File View Tools Options Help osale ARISE gt sl EL Design Flow MultiView Navigator Matiview Navigator 1 qa odere 5 S 170 Attribute aints PinEditor ChipPlanner Editor Editor Jl I an Errors A Warnings A Info Ready FAM Fusion DIE M7AFS600 PKG 484 FBGA A Fig 3 2 Actel Designer tool The last stage of the design is the Configuration of the FPGA with FlashPro tool 23 This tool communicates with the FlashPro3 device which transfers the configuration from the PC to the FPGA via the JTAG interface FlashPro tool allows the user to config ure separately the flash array and the internal flash memory After the configuration is finished FlashPro performs configuration check Before the design is configured to the FPGA several simulations on the PC are avail able All simulations are performed by ModelSim 18 When starting simulation
5. i a Fig 6 5 LFSRs for generation of multiplicative inversed pairs Unfortunately GF 28 generated by LFSRs is expressed by non AES primitive poly nomial 6 2 Since GF 25 suitable for AES is expressed by AES irreducible polynomial 6 1 all elements of the generated GF 25 have to be transformed into AES GF 25 by the basis transformation m x 23x x x x 1 6 1 il X amp ux a e tv 41 6 2 Let assume d is the element in the GF 25 expressed by primitive polynomial m x 6 2 Its polynomial representation 34 is d x dix dex dsx dax dax Td dix do 6 3 49 FEI DEMC Let assume c is the element in the GF 25 expressed by the AES irreducible polyno mial m y 6 1 Its polynomial representation is c y ey ce csy cay czy py c1y co 6 4 If A is the root of the polynomial m y and B is the root of the polynomial m x 34 than it holds that m A A FA cA cA 4 120 6 5 m A B B BP B 41 0 6 6 Therefore the basis of both polynomials 6 1 and 6 2 can be expressed as 3 A7 ASA AT A AA AT 6 7 B B9 B B4 B B BB 6 8 The smallest root of the m x polynomial 6 1 is A 0x02 34 The smallest root of the m x polynomial 6 2 is B 2 0x03 34 Therefore we can find the relationship between A and B as B AG1I 6
6. prof Ing Liberios Vokorokos PhD ved ci zad vaj ceho A dekan vedecko pedagogick ho pracoviska gt V Ko iciach d a 20 2 2009 Thesis assignment Study Specialization Electronics and Telecommunication Engineering Thesis title Secured opto electronic system for product traceability Extent of Thesis Recommended number of pages 40 and more Date of Assignment 20 2 2009 Date of Submission 7 5 2009 Head of the Department Prof Ing Du an Levick CSc Dean of the Faculty Prof Ing Liberios Vokorokos PhD Outline of Thesis 1 Design the architecture of opto electronic digital system for secured traceability of products based on the FPGA and verify the functionality of its particular parts Future automated system has to capture a digital image of the selected region on the cover of the product compute an optical signature of the product according to a simple algorithm encrypt the signature and transfer it via the USB to the connected PC 2 Design and verify functionality of the image acquisition from the camera to FPGA and the transfer of the images to a PC via the USB interface 3 Analyze the possibility of the realization of selected mathematical operations for the optical signature calculation by the embedded ARM processor in the FPGA 4 Design a simple cryptoprocessor with limited instruction set and verify the possibility of its realization inside the FPGA 5 Design the method for interconne
7. 1 can be described as AT c After substitution c BT d AT BT d 7 6 5 4 3 2 1 80 co co o oc o co o c c7 c6 C5 ca c3 c2 CI co d ds ds da ds dy di do 6 15 6 16 51 FEI DEMC where x operation represents matrix multiplication After matrix multiplication AT BT d 7 6 85 84 83 82 81 80 0 10 1 1 10 11 1 10 1 1 10 1 1 1 F amp F OF nua 0 0 1 1 0 0 0 1 1 C A 0 0 0 1 1 1 1 1 d 0 ds 1 ds 1 dy 0 d 0 d 0 di 1 do 1 where operation represents logic negation d d6 Bd di d d Ed Bd d amp dg amp d d ds 6 d4 d3 d d diy d dg ds do d Bd do d 6 dg dy d amp ds d4 d d3 B do do ded 6 17 Complete S box generator is shown in the Fig 6 6 Detailed implementation of the S box is shown in the Fig 6 7 3 S box generator FG Basis Affine transformation Basis transformation S box DEO S LLL BER C A TEE uM NM LI ML Teda i CI Fig 6 6 S box generator with basis transformation 6 1 3 Implementation of AES enc
8. ARM7 VHDL cycles tiles Computation of global image threshold 1 200 000 N A Binarization of the image 1 152 000 N A Application of 2D median filter N A 120 Localization of circular and rectangular objects N A N A Computation of rotation angle N A N A Rotation of the image N A N A Trimming of the image relocation to the center N A N A Computation of the Freeman code 60000 N A Computation of the Levenshtein distance 8 000 000 N A Total N A N A 42 FEI DEMC 6 Analysis of the cryptoprocessor core Every data before being transferred out the FPGA have to be encrypted Strong encryption will assure perfect protection of confidential data against attacks from outside When data enters the FPGA from outside they have to be authenticated too As long as big amounts of data are processed in 128 bit blocks a block cipher mode have to be used According to NIST specifications the following block cipher modes are recommended e Confidentiality modes ECB CBC CFB OFB CTR 28 e Authentication mode CMAC 29 e Authenticated encryption mode CCM 30 e High throughput authenticated encryption mode GCM 31 One of the most flexible ways to implement these block modes is to build a cryptopro cessor 4 The main part of the cryptoprocessor is the encryptor decryptor block Other operations required by a block mode can be performed in special ALU and intermediate results can be temporarily stored in in
9. RCON and Inv RCON are generated by the RCON generator illustrated in the Fig 6 3 6 1 2 Implementation of S boxes One of the most important parts of the AES cipher are S boxes S box represents complex non linear byte transformation 1 therefore it 1s difficult to implement it Byte substitu tion according to FIPS 197 1 composes of the following operations 1 Computation of the multiplicative inverse in GF 25 2 Affine transformation 1 46 FEI DEMC decrypt Cp 32 bit XOR s a m Iu mux sel a yq original key 127 96 x e m wO in gt Wo w4 1 32 mux_sel NW nreset M p 0 n wi in a o E 7 eis w5 l NV key i n J mux_sel A N94 decrypt 128bi BE An NO nreset 12850 EN MS w2 in w2 out Y n A gt We P w6 32 W6 a1 mux_sel 4 decrypt nreset NU TE w3 in W w3 out a w7 d e W pe ch ES key o ut 128bit 32 32 32 32 Fig 6 2 Key expansion block for forward and backward expansion 0x36 0x01 Ox8E E 0x02 b Inv RCON RCON nreset T 8 isst Inv RCON RCON Fig 6 3 RCON and Inv RCON constants generator Most usual implementations are 3 e Decomposition of GF 25 and mapping into two GF 2 implemented in combi natorial logic e Look Up Table LUT
10. gt mei Sadra nA i Header Sem Se fosa Data sent 19200 words 75KB M xem Sending packet data Data received i 4 amp n v Y Time Time Fig 7 1 Communication model between ARM and a PC 7 3 PC software implementation PC software was programmed in the Borland C Builder 6 0 20 Its purpose is to visualize the results of the capturing process on the PC Even if embedded system was able to capture frames at the speed of 30 fps USB interface slowed down the process to approximately 4 fps As long as PC serves for visualization purposes only 3 4 fps is considered as sufficient This visualization is used just to prove that captured frame inside the memory was captured correctly 66 FEI DEMC 7 3 1 PC interface from user s point of view PC interface is very easy to be used It has a lot of comments displayed at the hint line and the small glyphs for the user to intuitively understand the meaning of the buttons The interface contains two windows e Main window e About window 7 3 1 1 The Main window Main window is shown in the Fig 7 2 Camera Stream Yiewer Ioj xl Play Stop streaming TIME Camera initialization Show the About window 17 8 31 J51 Frames Per Second display Clear the console Start Stop System Time reference Capture Fig 7 2 Main window of the PC interface 67
11. 40 5 KRABI Mut 4 T ITITI e 34 2 E m 1 i 0 ha HH nmm y m uie RO i mia ET Gi 4 Fig 2 1 Actel System Management Board 2 2 Actel Fusion FPGA architecture 2 2 1 Actel Fusion Actel Fusion was designed as mixed signal Programmable System Chip PSC It com bines advantages of flash FPGA core flash memory blocks and configurable analog blocks 2 Flash based non volatile memory retains configuration even if power is turned off so in spite of other producer s products Actel Fusion can be used as a single chip so lution Fusion devices have a 128 bit flash based lock and industry leading AES decryp FEI DEMC tion used to secure programmed intellectual property IP and configuration data Actel Fusion is produced using 130 nm process technology Highest supported clock frequency is 350 MHz but I O pads allow at most 250 MHz Chip s source voltage is 3 3 V however the core is powered by 1 5 V voltage regulated by on chip 1 5 V regulator 2 The Fusion family consists of AFS250 AFS600 and AFS1500 devices 2 Most pow erful AFS1500 has up to 1 5 M system gates AFS600 and AFS1500 support CoreMP7 processor derived from ARM7TDMI and are denoted as M7 AFS600 and M7AFS1500 The particular design was targeted for M7 AFS600 device so it will be described in greater details 2 2 2 2 M7 AFS600 device M7AFS600 contains 600 000 system gates which form 13 824 VersaTile
12. 9 where repesents logic operation exclusive or XOR In order to find the relationship between elements c and d variables x and y in polynomials 6 3 and 6 4 have to be substituted by the roots of the irreducible polynomials c A c7A cgA csA c4A c3A c5A c14 co 6 10 d B d7B dB d5B d4B d4B d5B d B do 6 11 After substitution according to equation 6 9 d A di A 81 de AG1 6 ds A 1 da A 1 d3 A 91 d AB1 4 di A 6 1 4 do 6 12 50 FEI DEMC After simplification d A If c A 2 d A than the relationship between coefficients can be described as c7 C6 c5 C4 c BT d c3 c2 ci co 0 0 Cy UC CC ue eo o Qo oc cc oc d ds ds d4 d3 d d do P de Ods Bd da Bd Pd Ddo d d d d 6 dg ds d d dg d 6 ds deg ds d d de d3 ds d3 da d3 d4 dz d d A d1 de A d d5 A dz de ds d4 A4 d d B d3 A d dg d3 d gt A d ds Bd P di A bed ed 6 13 6 14 where c BT d describes the basis transformation and 8x8 matrix is the basis transfor mation matrix In some cases it is beneficial to combine basis transformation with affine transformation forming compact combined transformation Affine transformation
13. ACTEL FlashPro User s Guide v8 5 2008 available online http www actel com documents flashpro_ug pdf 24 AcTEL SmartTime v8 5 User s Guide 2008 available online http www actel com documents smarttime ug pdf 25 ACTEL SmartPower v8 5 Users Guide 2008 available online http www actel com documents smartpower ug pdf 73 FEI DEMC 26 ACTEL SoftConsole Quick Start Guide 2006 available online http www actel com documents SoftConsole OS UG pdf 27 ACTEL CoreConsole vl4 User s Guide 2007 available online http www actel com documents CoreConsole ug pdf 28 NIST Special Publication 800 38A Recommendation for Block Cipher Modes of Operation 2001 available online http csrc nist gov publications nistpubs 800 38a sp800 38a pdf 29 NIST Special Publication 800 38B Recommendation for Block Cipher Modes of Operation The CMAC Mode for Authentication 2005 available online http csrc nist gov publications nistpubs 800 38B SP_800 38B pdf 30 NIST Special Publication 800 38C Recommendation for Block Cipher Modes of Operation The CCM Mode for Authentication and Confidentiality 2004 available online http csrc nist gov publications nistpubs 800 38C SP800 38C updated July20 2007 pdf 31 NIST Special Publication 800 38D Recommendation for Block Cipher Modes of Operation Galois Counter Mode GCM and GMAC 2007 available online http csrc nist gov publications nistp
14. FEI DEMC Control panel is located in the bottom part of the window To initialize camera the user has to click to the Camera initialization button After the initialization Start Capture button displays After clicking on the Start Capture button the Screen starts to display the captured picture FPS will be dynamically measured and displayed in their FPS display area Time display area displays actual system time After performing any user action it will be displayed in the console panel The console can be cleared with the button located in the lower right corner of the window The last button in the lower right corner shows the About window If there was a need to display the frame errors the interface can be switched to the debug mode by pressing the Ctrl Shift F12 key combination When in debug mode small red D letter will be added in the left part of the hint line If there was an error during capturing process it would be displayed in the console with the time when the error occurred Fig 7 3 shows interface in debug mode Z Camera Stream Viewer zl xl D About Camera Stream Viewer FPS 3 TIME S 5 84 14s x 9 Fig 7 3 Application in the Debug mode 68 FEI DEMC 7 3 1 2 The About window About window displays the basic information about the application Fig 7 4 shows the About window About Camera Stream Viewer Fig 7 4 About window in the PC interface 69 FEI DE
15. P Parent fu Pare void TFormi DravFrame2 TImage Image char Buf Pane t Panel int 1 37 B Pare Byte ptr 7 Seae2 TI Pee Bitmap component creation s E Pee Graphics TBirmap bicmap am 3 Bitmap settings U T k OJ T birmaprnew Grephics TBicmap bitmap FixelFormatepf24bit suu 7 bitmap WidtheWidrh Sca me bitmap HeighteBeight Properties Everts Drav Frame to bitmap prm ELO 1 lt Height i Aw ne Ancho ahhh ak Too ptr Byte bitmap gt Scantine 1 for 140 3 lt Width 3 2 t WlConssrts TSceConssa 1f ByteChain Curr Desa t Don tohe ptr 3 540 Byte Buf 1 Nideh 341 Enabied me ptr 3 3 1 Byte Buf i Width 341 Pa vat prr j42 Byte Baf i Midrh 341 fot Fonit Giph T6 sap prr 3 52 3 Byte Buf i Width j ReY Grouplndex 1 ptr j 344 Byrte Bof i Width 3 G Y Hen 2 ptr 3 345 Byte Buf i Width 3 BeY MekCones 0 Heil eymg dde Meplype HCoriwt He Play Sp she ICT al 482 24 Insert Man cpp Mainh Diag Fig 3 5 PC software development environment Borland C Builder When a new project is created an empty window is displayed The user has to in sert all the objects like buttons images labels combo boxes etc 20 To create more attractive application object properties have to be tunned After the visual part of the application is created functionality has to be programmed using C cod
16. Thesis Ko ice Technical University of Ko ice Faculty of Electrical Engineering and Informatics 2009 76 pages N vrh opto elektronick ho syst mu s kryptografick m zabezpe en m pre kontrolu originality v robkov Architekt ra n vrh a t dia uskuto nite nosti vystopovate nos vlo ene digit lne syst my hardwarov zabezpe e nie dajov aplikovan kryptografia rekonfigurovate n obvody FPGA kryptoprocesory ARM Abstract in English The goal of this thesis is an architecture design feasibility study of the secured opto electronic system for product traceability and prototype realization of selected blocks The thesis demonstrates the implementation of the embedded system based on Actel Fu sion FPGA Field programmable Gate Array interconnected with the external small cam era from ST Microelectronics The system communicates with the PC via Cypress USB interface The core of the system represents the SoC System On Chip in FPGA based on the ARM7TDMI processor The system was implemented in the Actel System Man agement board based on Fusion FPGA The thesis also contains a discussion about the implementation of the image processing algorithms with products authentication as well as analysis of the possible implementations of the cryptoprocessor for confidentiality and authenticity of transferred data One part of the thesis deals with the problems related to the implementation of the AES cipher Advanced Encry
17. This study is the first step and further work is necessary to design exact protocol for data and control packets transfer and processing 64 FEI DEMC 7 Software implementation 7 1 ARM firmware design Firmware was written in c code in Keil u Vision3 development environment 19 using external GNU compiler Its complexity lies in close to hardware low level program ming At the first step simple functions had to be created These functions were directly accessing registers in peripherals in the ARM7 s address space peripherals connected to APB bus Functions were grouped in libraries according to peripheral they were writ ten for Finally Main function with an infinite loop was written This function uses all low level functions to access ARM7 s peripherals ARM core 12 13 has its firmware stored in the non volatile flash memory in side FPGA 2 This memory is accessed by CoreAhbNvm component flash controller which translates communication between the processor and the flash memory Because the processor executes instructions from the beginning of the memory space CoreAhb Nvm s address space range 0x00000000 OxOFFFFFFFE is in the beginning of the ARM 77 s address space Firmware is divided into these parts e Main function including infinite loop e I C library containing functions for I C bus control e CamDMA library containing functions for image acquisition and external memory sharing e
18. all mentioned 1s sues it could be advantageous to design cryptoprocessor capable of working with 128 bit words but using only 32 bit datapath 6 2 2 2 Architecture with 32 bit datapath Implementation of the 128 bit cryptoprocessor operating with 32 bit datapath is shown in the Fig 6 10 Despite the shift to 32 bit datapath each operation has to be carried out over 128 bit words Therefore each operation has to be performed in 4 steps where in 60 FEI DEMC each step a sub operation is carried out over 32 bit sub words However computational performance is 4 times lower When comparing number of used FPGA resources number of tiles necessary for mul tiplexers decreases rapidly In 32 bit datapath only about 360 tiles are needed to imple ment multiplexers when compared to about 1400 tiles needed in 128 bit datapath AII other parts of datapath are smaller For XOR operation only 32 tiles are needed Adder benefits from less resource count but the most important is the reduction of a delay in the critical path because of a shorter carry chain within the Adder The most important are savings in the number of used memory modules In contrast to 128 bit data registers using 16 RAM modules 32 bit data registers require only 4 RAM modules The session key register requires only 2 RAM modules when compared to 8 RAM modules needed in 128 bit datapath This saving allows implementing cryptopro cessor in Actel Fusion FPGA 2 used in
19. dec core in FPGA AES core has been implemented and tested in Actel Fusion AFS600 Actel Igloo AGL600 and Altera Cyclone III C5E144 FPGAs 3 Both S boxes in logic and in memory were tested When implemented in Actel Fusion device it turned out that AES with S boxes in memory utilized 2987 tiles and highest achieved frequency was 58 5 MHz and AES with S boxes in logic utilized 5499 tiles and highest achieved frequency was 28 7 MHz 3 In case of Altera Cyclone III only AES with S boxes in memory was measured It utilized 1705 logic elements one logic element can implement one combinatorial gate with register in series therefore it can be compared with 2 tiles and the highest achieved 52 FEI DEMC S box generator RAM4K9 dir do a eae inv_do inv_data gt Wb 0 m gt addra 7 0 o mco addrb 7 0 rda sboxa_out mM 1 E gt ma sel gt mb 9 m gt blka sboxa n r 1 sel 9 blkb rdb sboxb out abo ih 0 gt addra 8 decrypta M 1 addrb 8 Ik decryptb 0 0 eS nreset clk SS nreset 1 0 pi Fig 6 7 Detailed implementation of the S box in TDPRAM frequency was 111 4 MHz 3 AES with S boxes in memory was the only tested in Actel Igloo device Highest achieved frequency was 24 5 MHz 3 It is important to notice that Actel Igloo device is tar
20. en m pre kontrolu originality v robkov Design of an opto electronic system for cryptography based product traceability Pokyny na vypracovanie 1 Navrhn architekt ru opto elektronick ho digit lneho syst mu pre kontrolu originality v robkov na b ze hradlov ch pol FPGA a overi funk nos jeho jednotliv ch ast Bud ci automatizovan syst m m nasn ma digit lny obraz vybranej oblasti na obale v robku vypo ta optick podpis v robku pod a jednoduch ho algoritmu za ifrova ho a posla prostredn ctvom USB zbernice do pripojen ho PC 2 Navrhn a overi funk nos sn mania obrazov z kamery do FPGA a ich prenos do PC cez rozhranie USB 3 Analyzova mo nos realiz cie vybran ch matematick ch oper ci pre v po et optick ho podpisu procesorom ARM vlo en m v FPGA 4 Navrhn jednoduch kryptoprocesor s obmedzenou in truk nou sadou a overi mo nos jeho realiz cie vo vn tri hradlov ho po a 5 Navrhn mo nos prepojenia kryptoprocesora s procesorom ARM 6 Vypracova dokument ciu pod a pokynov ved ceho pr ce napr hlavn as 40 str n a viac pr lohy pod a charakteru pr ce elektronick forma hlavnej asti a pr loh Ved ci diplomovej pr ce doc Ing Milo Drutarovsk CSc Konzultant diplomovej pr ce Prof Viktor Fischer D tum odovzdania diplomovej pr ce 8 5 2009 NO NOE A on AN ES EE VO RV prof Ing Du an Levi k CSc fy
21. implemented in embedded dual port RAM 4T FEI DEMC The decomposition method 33 is preferably used in ASIC circuits where implementa tion of RAM memory is more expensive 3 In contrary LUT implementation is used mainly in FPGAs where RAM memories are available and logic resources can be utilized for the rest of the AES core 3 For this reason LUT implementation was chosen for the particular project 3 6 1 2 1 LUT based S box implementation Before the LUT based S box can be used LUT has to be created inside the embedded RAM In case of volatile FPGAs Altera Xilinx LUT is created during initial configu ration of the FPGA In case of non volatile FPGAs the configuration stage during initial ization is omitted However LUT has to be created inside the memory For this purpose S box generator has to be implemented in logic thus memory can be initialized imme diately after power up 3 However Actel Fusion FPGA contains true dual port RAMs TDPRAM 2 With TDPRAM both S box and S box can be generated and saved in TDPRAM simultaneously And what is more TDPRAM can be used as two S boxes op erating simultaneously 3 Combination of S box generator and TDPRAM is illustrated in the Fig 6 4 One idea of generating addresses and corresponding S box values is to S box S box A S box generator True dual port RAM S box B R Fig 6 4 S box and S box generation and connection
22. logic T80 8 Harvard NA In RAM 2x T400 4 Harvard 3 In logic 55 FEI DEMC Tab 6 2 Comparison of code properties of open source processors Name of CPU synthesizability code length readability modifiability Lightweight 8080 2007 1120 good many comments very good 68HC08 5517 2430 very poor poor comments poor LEON3 9674 N A very good perfect doc poor too complex Ax8 1315 1900 good many comments good HPC 16 2894 3759 good good document good McAdam s Marca N A N A very good good doc very good MiniMIPS 16171 N A medium good doc good PAVR 7876 7900 good medium doc medium Plasma MIPS 4180 2000 medium medium comments medium Ppx16 1172 970 medium poor comments good RISC5x 2983 1700 good good comments medium Tiny64 3529 530 good good comments good System68 2802 3962 medium medium comm poor System11 3529 4792 medium medium comm poor T48 1547 5500 good medium comments medium T65 1603 1700 medium poor comments good T80 3229 3100 good poor comments good T400 1216 3550 medium medium comm medium 56 FEI DEMC Tab 6 3 Selected open source processors to be reused in cryptoprocessor Not very suitable for FPGA More suitable for FPGA Lightweight 8080 Ax8 HPC 16 McAdam s Marca Tiny64 Ppx16 T48 RISC 5x T65 T80 6 2 2 Design of n
23. the promising solutions is the miniaturization of the optical markers for recognition of originals However a new issue shows up This miniature markers have to be localized scanned and the originality of the product has to be confirmed Therefore it is essential to design secured opto electronic system for product traceability Several years ago the Hubert Curien Laboratory in Saint Etienne France together with the SignOptic private company have proposed an image processing algorithm en abling cheap and reliable product recognition and authentication The system is already validated in industrial applications working in product area factory However industrial needs have shown that it would be very useful to build a simple and portable device that should be able to authenticate products as well as to authenticate the factory in a hos tile environment The design of a secured embedded system suitable for such kind of applications has become the aim of a research and development project of the AMTeS Architectures Mat rielles pour le Traitement et la S curisation des Donn es research team from the laboratory that is in charge of Professor Viktor Fischer Professor Fischer and his team have invited me two times in order to work on the project The objective of the first stay during the summer 2008 was to implement an image acquisition embedded system connected to a PC via USB interface The aim of the second stay was the work on the overall syste
24. the setting of contrast reg 0x039A to OxAO and switching the camera mode to RUN by writing 0x2 to the register 0x0180 In this application the image size was configured to QVGA by writing 0x2 to the register 0x0380 synchronization codes were turned off 0x00 to the reg 0x2104 HSYNC synchronizes active lines only 0x0F to the reg 0x2106 and clock is free running 0x85 18 FEI DEMC to the reg 0x210A Table and detailed description of all registers in the V 6524 camera can be found in its user manual 5 2 6 2 Output data format and synchronization When initialization of the camera chip is finished captured video data are sent to the output pins of the camera chip 5 There are 8 data output pins available Synchronization is carried out by monitoring HSYNC VSYNC signals and synchronizing PLL to PCLK signal producing camera synchronized clock domain inside the FPGA All output data are synchronized to PCLK Data are sent to output on falling edge of PCLK Also control signals HSYNC and VSYNC are changed on the falling edge of PCLK Video stream consists of frames sent one after another There are interframe blanking data between each two frames 5 Also between every two lines of frame there are interline blanking data By default blanking data contains 0x1080 values These values can be changed in registers 0x2110 and 0x2112 Fig 2 11 illustrates output frame 1460 PCLKs
25. this project However cipher module operates with 128 bit words For this reason word length conversion blocks have to be added The convertor block from 32 bit to 128 bit is shown in the Fig 6 11 One may notice three sets of 32 bit registers implemented in logic These registers are controlled by the enable signals EO E1 and E2 and provide temporary storage of successive 32 bit sub words Last 32 bit sub word is not registered and 1s transferred directly to 128 bit output bus This solution helps to save one clock cycle which would have been needed in case of registration of the last 32 bit sub word The whole conversion requires 4 clock cycles Inversed convertor is shown in the Fig 6 12 One may notice that no registration is necessary and all 32 bit sub words are successively multiplexed into 32 bit bus The only necessity is the correct control of select signals S1 S2 and S3 The whole conversion requires 4 clock cycles 61 FEI DEMC din Input Output dout register register v 1 carry m Bv Data register dual port Dus RAM 4 modules 1 x bs ud 0 1 flow rate h 1 D cmp A B Session Key RAM 128 2 Kl 32 32 Cipher 7 125 RNG 128 Ko 32 128 Main Key ROM Inv Main Key
26. to TOPRAM implement one combinatorial S box and source it with counter 3 Counter value can be considered as the memory address and output of the combinatorial S box as the value to be written to memory 3 After 256 cycles whole LUT is created in the memory 3 However implementation of combinatorial S box utilizes about 200 tiles 3 However more convenient solution based on LFSRs exists and will be described in the next section 48 FEI DEMC 6 1 2 1 1 S box generator based on LFSRs One of the design constraints was the size of the S box generator Number of used re sources of the generator is very important when implementing in smaller FPGAs There fore S box generator based on two LFSRs was designed 3 Before the S box pairs address and value could be created multiplicative inversed elements have to be generated simultaneously in LFSRs 3 Implementation of both LFSRs 3 is shown in the Fig 6 5 Due to the limited number of pages of this thesis the mathematical description of the LFSRs will not be discussed and only main results will be presented Mathematical description is explained in article which was submitted to FPL 09 conference 3 and CryptArchi workshop 3 p i 1 2 3 4 5 es DTTUM 6 5 4 3 2 1 0 Y o o b Y be N w i d Y A 4 Y a o 4 4 Y
27. Cyp usb library containing functions for USB communication Firmware for ARM7 is responsible for image acquisition memory sharing camera initialization and USB communication This firmware is just the first version In future it has to be expanded to include optical signature extraction and cryptoprocessor control 65 FEI DEMC 7 2 USB transport protocol To transport data via USB protocol had to be created The idea was to divide data into packets with headers The transport protocol postulated asymmetric data rates in different directions Packets transferred from ARM7 to PC had bigger header and were capable to contain more data Packets transferred from PC to ARM7 had smaller header and smaller data space This asymmetry was due to requirements of the system ARM7 had to send big amount of image data while PC had to send only command with little data to specify request The communication model is illustrated in the Fig 7 1 Communication is carried out by sending a pair of physical packets First packet represents the logical header and the other packets the logical data PC ARM side USB side I I Command to Waiting f Header aiting for start capturing 0 sent data len gp a en OB gt Nojdata part cmd CA o AP FRAME ee ze Capture starts Capturing frame Waiting Tor the header m gt null Ale 4 Header sent data len 19200 words 75KB cmd not used
28. Development Environment Intellectual Property Joint Test Action Group Key In Key Out Liquid Crystal Display Light Emitting Diode LFSR LHC LSB LUT MAC MK N A NIST NLFSR OFB PCI PLL PSC PTRi QVGA RAM RC REG RGB RISC Linear Feedback Shift Register Laboratoire Hubert Curien Saint Etienne France Least Significant bit Look Up Table Message Authentication Code Main Key Not Available National Institute for Standards and Technology Non Linear Feedback Shift Register Output FeedBack confidentiality block cipher mode Peripheral Component Interconnect widely used computer peripheral bus Phase Locked Loop Programmable System on Chip Plain Text Register input Quarter VGA display standard with resolution 320x240 Random Access Memory Resistor Capacitor based oscillator Register Red Green Blue color model Reduced Instruction Set Computer RNG ROM RS232 S box SCL SDA SDF Random Number Generator Read Only Memory Recommended Standard 232 is a standard for serial binary data transfer Substitution box Serial Clock signal of an I C bus Serial Data signal of an PC bus Standard Delay Format SecReSoC Secured Reconfigurable System on Chip SK SM SoC SRAM Session Key State Machine System on Chip Static RAM TDPRAM True Dual Port RAM USB VGA VHDL VHSIC VSYNC XOR YUV Universal Serial Bus Video
29. Graphic Array VHSIC Hardware Description Language Very High Speed Integrated Circuit Vertical Synchronization signal Exclusive OR logic operation color model YUV containing Luminance component and two Chrominance components FEI DEMC Introduction Humankind crossed the borders of the 2151 century with new fascinating technologies and rapid technical advance These technologies are however the outcome of the previ ous progress and innovations change and replace each other to form a chain of our de velopment But as nothing is so simple and onefold there are many shades of utilization of the technical progress The only desired utilization of this progress is to help people whether in everyday life or beyond the visible innovations for common people with a special emphasis on these improvements legality and correspondence with particular in ternational conventions and norms Therefore the creation of new and original products is just as important for progress as the protection of seals of originality authorship and copyrights To keep it simple it can be said that it is important to search for all the ways of preventing fake products to get a chance to enter the market and thus violate the rights of both authors and consumers Throughout the previous centuries there have been numerous attempts to create and introduce new procedures for distinguishing between fake and original products Begin ning with the old valuable paintings p
30. IC s design to form powerful low cost and flexible SoC 12 ARM7 has found its application in Game Boy Advance Nintendo DS or iPod 14 Many producers include this soft IP in their microcontrollers because of its unique features e g Atmel AT91SAM7 12 ARM is 32 bit RISC processor which also support 16 bit instructions via Thumb instruction set Registers are orthogonal It has Von Neumann architecture with a 32 bit data bus carrying both instructions and data ARM7 uses 3 staged pipeline The address bus provides 4 GB of linear addressing space Fig 2 5 shows block diagram of ARM7 13 12 Processor 12 FEI DEMC is connected via the bridge to the AMBA bus 15 13 12 This bus is a standard and it includes AHB ASB and APB buses AHB bus is a high performance system bus widely used to interconnect ARM core with memory interface PCI interface and other interfaces which require short access time and high throughput It is a multi master bus so more ARM cores can share it ASB was formerly a high performance system bus but it was replaced by AHB APB is a peripheral bus It is optimized for minimal power consumption and reduced interface complexity It is low performance and is not pipelined Main advantage is its simplicity 15 Only one bus master is permitted the peripherals are connected to the APB as its slave devices 15 13 12 2 3 2 The Actel CoreMP processor architecture Actel s CoreMP7 is the o
31. Libero 26 FEI DEMC IDE generates batch file do and executes it in the ModelSim The following simulations are available e Pre synthesis e Post synthesis e Post layout Pre synthesis simulation can be carried out before the VHDL code is synthesized This simulation is only functional Post synthesis simulation is carried out on the synthesized VHDL code Although the simulation is still functional it can be useful when comparing the impact of the synthesis with the original design Post layout simulation represents the timing simulation of the design and can be performed after the back annotation was created 17 22 18 This type of simulation is very critical when estimating the limits of the design maximal frequency delays glitches and other unusual behavior Maximum frequency and delays between gates can be also estimated by SmartTime tool part of the Designer tool 24 22 Power consumption can be estimated by the SmartPower tool part of the Designer tool 25 22 3 0 ModelSim One of the most important issues during the design period is when the design doesn t behave properly after being configured into the FPGA The method for correction of the issue is called debugging However localization of the issue can be very difficult and time consuming The best way to localize difficulties is to run a simulation There are two common types of the simulation e functional simulation e timing simulation Func
32. MC 8 Conclusion As it has been stated in the introduction one of the biggest problems of the modern world is faking of original products and thus enabling to gain profit illegally from items being in a declarable ownership of their sole authors This research has been carried out to establish hardware platform to install the procedures of distinguishing original and fake products from each other with the highest possible accuracy From the technical point of view this project dealt with the realization of the first steps important for this new technology particularly with the image acquisition encryp tion analysis of cryptoprocessor and feasibility study about implementation of optical signature extraction algorithm to hardware Image acquisition subsystem together with ARM 7 subsystem have been successfully implemented in hardwate and tested Prototype has been created AES cipher decipher subsystem have been implemented in FPGA and basic parameters have been measured It hasn t been tested yet since block cipher modes are required for testing in hardware and cryptoprocessor for performing these block cipher modes hasn t been implemented yet Architecture of cryptoprocessor has been proposed in structural level Future development lies in the implementation and testing of the cryp toprocessor Product authentication algorithm has been designed and tested in Matlab Analysis of the complexity of this algorithm has been carried out Other algo
33. Technical University of Ko ice Faculty of Electrical Engineering and Informatics Department of Electronics and Multimedia Communications Secured opto electronic system for product traceability Architecture design and feasibility study Master s Thesis ubo Ga par Supervisor Assoc Prof Milo Drutarovsk PhD Consultant Prof Viktor Fischer Ko ice 2009 Metadata Sheet Author Thesis title Subtitle Language Type of Thesis Number of Pages Degree University Faculty Department Study Specialization Town Supervisor Consultant s Date of Submission Date of Defence Keywords Category Conspectus Thesis Citation Title SK Subtitle SK Keywords SK ubo Ga par Secured opto electronic system for product traceability Architecture design and feasibility study english Master s Thesis 76 Master degree Technical University of Ko ice Faculty of Electrical Engineering and Informatics FEI Department of Electronics and Multimedia Communica tions DEMC Electronics and Telecommunication Engineering Ko ice Assoc Prof Milo Drutarovsk PhD Prof Viktor Fischer 7 5 2009 27 5 2009 traceability Embedded digital systems data securization applied cryptography reconfigurable circuits FPGA cryptoprocessors ARM Technika technol gia in inierstvo Elektronika ubo Ga par Secured opto electronic system for product traceabil ity Master s
34. VersaTile a n u g a n n a n g a SRAM Block 5 4 608 Bit Dual Port SRAM g or FIFO Block B 8 FFEF EFE 5 Quad Quad Quad Quad Quad d x ccc M nnonanacanaoncccosccnononcocOGOSODODODODOOSOOD h af Bank 3 Legend Via hard connection een flash connection Ground Fig 2 3 Structure of VersaTile ultra fast local lines system Clock and reset signals can be connected to VersaNet global networks which are connected to six CCCs clock conditioning circuits The core is organized into quadrants Three CCCs are connected to west global resources in west 11 FEI DEMC quadrants and three CCCs are connected to east global resources in east quadrant For more detailed description of Actel Fusion s inner structure please refer to Actel Fusion s documentation 2 Long Lines Ultra Fast Local Lines 7 connects a VersaTile to the adjacent VersaTile I O buffer or memory block Fig 2 4 Ultra Fast Local Lines connected to the eight nearest neighbors Analog blocks were not used in this project so these parts will not be described in this documentation For further information about analog blocks please refer to Actel Fusion s documentation 2 2 3 IP processor based on ARM7TDMI 2 3 1 The ARM7TDMI S processor architecture ARM7TDML S further just ARM7 13 12 is world wide spread soft IP processor 12 This processor was designed by ARM Ltd company to be a part of AS
35. ata part 16 5 Each communication register access starts with start command both SDA and SCL signals are pulled LOW following by 8 bit device address 16 5 LSB bit of the device address distinguishes if the next operation will be writing to the slave 0 or reading from slave 1 in this case device address is 0x21 Therefore write flag 1s sent to the bus 0 Subsequently slave device confirms successful transfer by sending acknowledge bit After acknowledge a short pause follows after which high 8 bits of register address are sent to the slave This pause is required by camera so changes inside the chip have enough time to take effect Slave confirms transfer by sending acknowledge to the master device After acknowledge a short pause follows after which low 8 bits of register address are sent to the slave Slave confirms transfer by sending acknowledge to the master device afterwards a short pause follows The next action will be different when writing to the slave than when reading from the slave WRITING TO THE SLAVE After pause 8 bits of data are sent to the slave device Slave confirms successful transfer by sending acknowledge 16 5 Short pause follows After pause master sends stop command by pulling both SDA and SCL signals to HIGH READING FROM THE SLAVE After a pause stop command is passed to the bus by 21 FEI DEMC pulling both signals to HIGH 16 5 A longer pause period follows so the slave devic
36. bility of the VHDL code e size of circuit in tiles and number of used RAM modules e reusability of a control part of the processor e number of stages in pipeline preferred not more than 3 Observed results are summarized in Tab 6 1 and Tab 6 2 According to the results of the analysis the following 10 processors see Tab 6 3 have been chosen to be reusable Only 5 processors were optimized for FPGA registers in RAM Harvard architecture For more appropriate decision every chosen processor has to be reviewed more carefully and tested on simulations Most reusable part 1s the control logic Datapaths have to be usually modified completely 54 FEI DEMC Tab 6 1 Architecture and implementation comparison of open source processors Name of CPU num of bits architecture pipeline registers in Lightweight 8080 8 Von Neumann 2 16x in logic 68HC08 8 Von Neumann 3 In logic LEON3 32 Harvard 7 In RAM Ax8 8 Harvard NA In RAM 2x HPC 16 16 Von Neumann N A In logic McAdam s Marca 16 Von Neumann 4 16x in RAM MiniMIPS 32 Von Neumann 5 In logic PAVR 32 Von Neumann 6 In RAM 10x Plasma MIPS 32 Von Neumann 3 In RAM Ppx16 8 Harvard N A In RAM except acc RISC5x 8 Harvard 1 In RAM Tiny64 32 Von Neumann 3 8x in logic System68 8 Von Neumann N A In logic System11 8 Von Neumann N A In logic T48 8 Harvard N A _ In logic T65 8 Von Neumann N A _ In
37. can A Scan B Scan A Scan B Original Scan A 0 140 222 231 print ScanB 140 0 220 222 Fake ScanA 222 220 0 134 print ScanB 231 222 134 0 recognize the original from fake one Recognition can be a questionable issue when light conditions are worse and the difference between the original and fake ones are smaller 5 2 Hardware implementation of image processing signature extrac tion and comparison algorithms One of the system s constraints was the acquisition speed of at least 4 frames per second Therefore system has to be able to capture the image carry out the image processing extract a Freeman code compute the Levenshtein distance and decide whether the product is original or fake before the next image is captured This gives the system approximately 250 ms to perform all the mentioned steps As explained in the previous section algorithm is very robust There are three possible solutions for computation of algorithm e in ARM7 processor e in coprocessor connected to ARM7 e part in the coprocessor and part in the ARM7 However algorithm has a serial structure thus parallelization can become an issue This 40 FEI DEMC limits the advantage of the FPGA which is its parallelism And what is more some operations are carried out on every pixel of the image or small blocks of the image These operations are very time consuming The whole algorithm has been
38. celles 6 1 5 Cryptoprocessor development stage ooo llle 6 1 6 Development and analysis of potential implementation of image pro cessing and product authentication stage 6 2 1 Actel System Management Board e 9 2 2 Structure of Actel Fusion 4008 be hae o 30k X Puy a 11 2 3 Structure of Versa Tle so owe a ua BE Bo RA oem dne 11 2 4 Ultra Fast Local Lines connected to the eight nearest neighbors 12 2 5 ARM7TDMI S architecture lens 14 2 6 Micronic USB CYPRESS module frontside 15 2 7 Micronic USB CYPRESS module back side 15 2 8 X24 camera integration kit leen 16 2 9 Camera chip VS6524 in scale 7 1 llle 17 2 10 Simplified block diagram of ST VS6524 camera chip 18 2 11 VGA 30fps output frame llle 19 2 12 n B pixel in video stream sse e Re RR 20 2 13 Beginning of the frame o s ton Get b Ae ee S 20 214 Eudol the first lines i v esie ER ERE REAL 20 2 5 Bnd Or the frame s ae odg en xU A OX ACE XM X 2l 2 16 Write operation with the internal register OXCOO3 sn 22 2 17 Read operation with the internal register OxCO03 23 ISk PabetodbE 2 RR teg em xem eoe A og etg 25 3 2 Actel Designer tool a 26 3 3 Waveform view in ModelSim llle 28 3 4 Keil uVision 3 development tool llle 29 3 5 PC software development environment Borland C Builder 30 4 1 Interconnection of dev
39. cessing unit data security encryption and authentication block and communication block The proposed architecture is determined by the requirement of the use of Actel FPGAs security reasons and embedded soft core processor ARM7 Most of the hardware should be placed in one chip FPGA The only modules that could be implemented outside FPGA are the communication USB interface and program data memory Since the required system is relatively complex it cannot be designed and imple mented in one thesis Instead the aim of this work is the design of a global architecture and a feasibility study of its selected blocks e g image processing block However some functional blocks have been designed and simulated in VHDL e g AES cipher op timized for non volatile FPGAs some were designed simulated and tested in hardware e g acquisition block and communication block using USB interface The architecture of the crypto processor has been proposed on a structural level without description in VHDL and simulation Chapter 1 describes the overal secured embedded system for product authentication and the roles of its modules Chapter 2 describes available hardware platform including ARM processor and embedded camera module Chapter 3 concerns all develpment tools that have been used during the work Chapter 4 introduces implementation of image ac quisition within the ARM7 subsystem Chapter 5 analyses the used image processing signature extracti
40. complex product as the product authentication device for secured trace ability of original products later just scanner requires certain subsequent steps in the product s design As long as the product has to represent stand alone system the em bedded system later just ES has to be developed in the first step Subsequently CMOS camera chip has to be connected to the embedded system 5 ES has to contain these elements e SoC design inside the FPGA based on the ARM processor e Static RAM memory e USB interface The hardware platform is the most important part of the design because 1t directly in fluences device s costs performance power consumption and reliability The following hardware platform was obtained for the prototype e ST Microelectronics X24 development board 6 with 1 3 Mpix embedded camera chip VS6524 5 e Actel System Management Board 7 with embedded Actel Fusion M7AFS600 FBGA484 FPGA 2 with ARM support Santa Cruz interface Two SRAM modules GSI GS88018BT 200 2 MB in total 8 Two FLASH modules ST M29W800DT 2 MB in total 9 e USB board 10 with Cypress USB module CY7C68013A 100A XC 11 Santa Cruz compliant e PC AMD Athlon XP 2600 1 GB DDR ram USB 2 0 support FEI DEMC The selection of VS6524 camera chip was a very good choice for its rich image pro cessing settings In order to omit initial configuration of the FPGA Actel FPGA was selected as the only producer
41. cribed as one of eight possible directions 38 FEI DEMC from the previous pixel in the edge Algorithm is finished when all of the pixels in the edge are described by the Freeman code As soon as the optical signature is extracted it has to be compared with the signature of the original product acquired from the encrypted data area on the surface i e encrypted data in barcode The best way to compare two Freeman codes with different lengths is to compute the Levenshtein distance Big advantage of the Levenshtein distance is the resistance to different lengths of the compared Freeman codes Fig 5 4 Original print scan A and scan B Fig 5 5 Fake print scan A and scan B Example is illustrated in the Fig 5 4 and Fig 5 5 Two scanns of the original image are shown in the Fig 5 4 Two scanns of the fake image are shown in the Fig 5 5 Levenshtein distances of the different prints and their scans are summarized in the Tab 5 1 As shown in the table Levenshtein distances between scans of original prints and scans of fake prints are all over 200 In contrary Levenshtein distances between two scans of the same print are less than 150 It is important to note that images were scanned in laboratory conditions therefore Levenshtein distances are very different and it is easy to 39 FEI DEMC Tab 5 1 Levenshtein distance of different prints and corresponding scans Original print Fake print S
42. cting the cryptoprocessor with the ARM processor 6 Write the documentation according to the instructions given by the supervisor of the thesis i e main part of 40 pages or more appendices according to the type of the thesis provide the main part and appendices in the electronic form Declaration I hereby declare that this thesis is my own work and effort Where other sources of information have been used they have been acknowledged Ko ice 7 5 20090 1 1 1 11 l l 444 44 n Signature Acknowledgement I would like to thank to my family for their unconditional love and support I would like to express my sincere thanks to my supervisor Assoc Prof Milo Drutarovsk for his valuable recommendations and carefull review of the thesis Special mention and thank should go to Prof Viktor Fischer for his constant and constructive guidance throughout the thesis support and patience during long phone calls and discussions To all other who gave a hand I say thank you very much Preface Counterfeiting of the products represents a very serious threat nowadays The trend of counterfeiting is as old as the humankind itself However the development of more ad vanced techniques of production goes hand in hand with enhancements in counterfeiting techniques In order to be able to distinguish the original products from the fake ones production techniques have to develop faster than enhancements in counterfeiting tech niques One of
43. d generation of maximum length sequences was studied too To sum it up the first steps required for developing the above described technologies has been carried out with success Further development and the final realization lies on the subsequent research and on the final technical realization It can be concluded that this project has been finished successfully and it has fulfilled all the expectations connected with its practical realization 71 FEI DEMC Bibliography 1 2 3 4 5 6 7 8 9 10 11 12 NIST FIPS 197 Advanced Encryption Standard 2001 available online http csrc nist gov publications fips fips 197 fips 197 pdf ACTEL Fusion Handbook 2009 available online http www actel com documents Fusion_HB pdf L GASPAR M DRUTAROVSKY V FISCHER AND N BOCHARD Efficient AES S boxes implementation in non volatile FPGAs submitted for FPL 2009 confer ence Prague Aug 31 Sep 2 2009 ANR SecReSoC project France 2009 ST MICROELECTRONICS VS6524 VGA single chip camera module datasheet 2006 available online http www stdistributiondemandcreation com steval datasheets vs6524 pdf ST MICROELECTRONICS X24 Camera integration kit User manual 2007 ACTEL Actel System Management Board User s Guide 2006 GSI TECHNOLOGY GS88018 32 36BT xxxV 9Mb Sync Burst SRAMs datasheet 2007 available online http www gigasemi com 880xxB V
44. developed in Matlab The goal of this work is to es timate the number of ARM7 cycles required to carry out all operations of the algorithm and to estimate the resource count in case of hardware implementation As long as used functions in Matlab haven t been written in the c code yet cycle accurate estimation in Keil u Vision 3 couldn t have been performed Estimation issue was even greater when an operation of the algorithm used several robust Matlab functions Due to these issues and lack of time in some cases I wasn t able to estimate required number of cycles These estimations have to be carried out in greater detail in the future Tab 5 2 summarizes the estimations for the particular operations of the algorithm Size of the image is 320x240 pixels Operations that couldn t have been estimated are denoted as N A Not Available However the provided estimations can be used to predict the complexity of calculations However only three estimated operations require about 10 000 000 clock cycles If the processor operated in the frequency of 40 MHz and the algorithm consisted only from these three estimated operations processing of the image would take 250 ms These estimations have to be proved by simulations in the future 41 FEI DEMC Tab 5 2 Basic estimation of required ARM cycles as well as required logic resources for implementation of particular operations within the algorithm
45. e Every ob ject in the application is represented by a class in the hierarchy of classes The class at the bottom of a hierarchy inherits all attributes and properties of the above classes in the hierarchy 30 FEI DEMC Before the application is compiled the compiler has to be set to retail mode In this mode exe file will be created without linking debug libraries 20 And what 1s more special settings have to be specified so resulting application will not depend on Borland C Builder libraries but only on standard windows libraries 31 FEI DEMC 4 Structure of the image acquisition subsystem 4 1 Interconnection of the development boards This chapter describes the structure of the image acquisition subsystem During the de velopment phase the system was composed of several development boards The structure of the system with its interconnected subparts 1s illustrated in the Fig 4 1 EMBEDDED SYSTEM Fig 4 1 Interconnection of development boards forming the system The system is composed of the embedded system ES and the camera 5 placed in the X24 camera evaluation board During the acquisition images are transferred from the camera to the ES where image processing has to take place The control of the operation by a PC as well as data exchange is provided via USB interface USB communication is established via the Cypress USB module 10 placed in the Santa Cruz interface located o
46. e has enough time to prepare data to be sent to the master It can be 00xSCLperiod long After this period start command is sent to the bus The device address follows with the read flag 1 Slave confirms transfer by sending acknowledge and a short pause follows Subsequently the slave starts to send data to the master It sends 8 bits of data After transfer is completed master sends negative not acknowledge to the slave Immediately after acknowledge master sends stop command to force slave not to send more data 16 5 If access to the other register 1s required the whole process has to be repeated again after a longer pause 5 After configuring all the required registers the camera should operate according to the expectations To prevent incorrect configuration of the camera chip always check the configuration by reading the content of the register after it has been modified Fig 2 16 and Fig 2 17 illustrate write and read operation with the register of address 0xC003 Bibi REGISTERADDRESS P 1 101 10 stant DEVICEADDRESS 3 2 HIGH BITS pE ea ef Le SCO 0 20 s gt LI 1 REGISTER ADDRESS i iab 1 LOW BITS 19 DATATOBEWRITEN 9 srop 0x03 Ie ia 0x06 EGRE i Fig 2 16 Write operation with the internal register 0xC003 22 FEI DEMC 51 71 REGISTER ADDRESS Z START DEVICE ADDRESS IM 1 HIGH BITS Er i L1 a 1 ei SCL 1 1 1 3 0X20
47. e doubled to assure safe transfer of the key from one block to another In the 57 FEI DEMC Fig 6 8 critical key bus is illustrated in red color 4 Despite the security of the AES cipher there is a possibility to extract a key from big amount of encrypted data For this reason it is recommended to change key every 64 kB of data 4 This issue has been solved by using two sets of registers for keys Main key register for permanent key and Session key register for temporary key 4 At the beginning session key is generated by the RNG After being stored in session registry it is encrypted by the main key and sent out to receiver Afterwards receiver decrypts the encrypted session key with the same main key Subsequently the sender can encrypt data with generated session key and send them to the receiver The receiver decrypts the data with the previously received and decrypted session key For each 64 kB of data new session key is generated 4 Input and output registers Data are open Input and output registers Data are encrypted Program Data memory registers 128 bits Data bus Control unit TT i Key for encryption authentication Main key entrance uasauauac Session key encryption gt MKencrypt Main key encryption Session key authent gt SKauth MKauth Main key authent Key registers 128 bits Legend A E Programmable or reconfigurable modules F
48. e successfully performed acquisition ARMT s task is to monitor these signals 35 FEI DEMC poinjdeou4 ONY O FrCaptured 0 LEGEND State of the State Machine Command execution L SOU nCS 0 AND FrCaptured 0 sou QNV 0 L gt BEIJNASA E FrameReady 1 FrameReady 0 o o o o k SOU FrCaptured nCS 0 2 4 AND D zx VSYNCreg 0 AND YSYNCreg 1 PEoHSLIEJJ nCS 0 nCS 0 AND AND VSYNCreg 1 VSYNCreg 0 0 Fig 4 4 State diagram of the main image acquisition state machine 36 FEI DEMC 5 Optical signature extraction algorithm One of the most important steps during secured traceability of the product is the com parison of the optical signature of the product with the optical signature of the original product It is very important to evaluate optical signatures of two scanned images as dif ferent when these images were printed in two different printers If images were printed with the same printer optical signatures of the scans have to be evaluated as matching Algorithm for the optical signature extraction and subsequent comparison with the optical signature of the original product is described in next section 5 1 Description of the image processing signature extraction and comparison algorithm Before the algorithm can be applied s
49. elopment boards forming the system 32 4 2 System on Chip based on ARM7 processor 33 4 3 Illustration of the DMA controller with two clock domains 35 4 4 State diagram of the main image acquisition state machine 36 5 1 Special uncopyable marker for optical signature extraction 37 5 2 A Scan of original print B Binarized and filtered C Angle estimation 38 5 3 A Rotated B Dot localized C Centered and trimmed 38 5 4 Original print scan A and scan B llle 39 5 5 Fake print scan A and scan B llle 39 6 1 Shares AES Encryption Decryption core a 45 6 2 Key expansion block for forward and backward expansion 47 6 3 RCON and Inv RCON constants generator len 47 6 4 S box and S box generation and connection to TOPRAM 48 6 5 LEFSRs for generation of multiplicative inversed pairs 49 6 6 S box generator with basis transformation 52 6 7 Detailed implementation of the S boxin TDPRAM 53 6 8 Block diagram of the cryptoprocessor 00 58 6 9 Implementation of cryptoprocessor with 128 bit datapath 59 6 10 Implementation of cryptoprocessor with 32 bit datapath 62 6 11 Conversion of 4 successive 32 bit words into 128 bit word 63 6 12 Conversion of 128 bit word into 4 successive 32 bit words 63 6 13 Interconnection of cryptoprocessor with ARM7
50. ew cryptoprocessor architecture The other way to develop the cryptoprocessor is to create a new design However there are many issues that need to be considered Control logic has to be very stable because it directly influences the performance of the datapath Number of used logic resources also has to be considered In this case datapath is the most expensive one Thus it is very important to decide to base the architecture on either 128 bit datapath or 32 bit datapath Block diagram of the cryptoprocessor is shown in the Fig 6 8 4 As shown in the Fig 6 8 data and key registers are physically separated in different RAM modules This precaution helps to preserve security of the key inside the FPGA 4 Even if it doesn t seem critical at first sight it can turn to catastrophe if an unencrypted key is transferred out of the cryptoprocessor via the data bus 4 How is this possible If an attacker intentionally applies very strong magnetic field to the critical parts of the FPGA ie select signal of the multiplexer key can be redirected to output data bus However it is not sufficient to physically separate data and key registers The whole architecture buses multiplexers has to be designed carefully otherwise the security is reduced For these reasons parts of the architecture that operate with keys need to be specially treated In this case resource optimization is not as important as the security of keys Some key paths can b
51. f hardware platform 21 Actel system management board ls 2 2 Actel Fusion FPGA architecture llle 225 etel Fusion 2 2242 Sct S xor XXE K R XE RU d 2 252 NTA SOOO deyi CC os us uos Een Pet E Rev Bel v Rote A ee 2 2 3 JPUSIODRHGOI c 59 G Sank a o Deck RR hh rats s 2 3 IP processor based on ARM7TDMI lens 2 3 1 The ARM7TDML S processor architecture 2 3 2 The Actel CoreMP7 processor architecture 2 4 Micronic development module with Cypress USB 2 5 X24 camera integration kit ouo SR A K pw 2 0 SLM VS GILA CIMETA iiieasg Becr roe Fon bug br ao argu an 2 6 1 Initialization of the camera aoao a 2 6 2 Output data format and synchronization 2 6 3 PC communication description les 3 Description of the software development tools Oak Labero IDE atere rect ecu Gas A SA Be d S SD Model Sim uu ao S e Xe ME YE v ME CY ok BS Ao UEGIIDVISIOB S RNA AO VE VINE AO SPORE 3 4 C design environment Borland C Builder 4 Structure of the image acquisition subsystem 4 1 Interconnection of the development boards 4 2 System on chip based on the ARM processor 10 10 12 12 13 13 15 16 18 19 21 24 24 27 29 30 4 3 Image 3C St HOT o uctor RR ed e Se exe Oed Re Red Beleg BN e eS Optical signature extraction algorithm 5 1 5 2 Description of the image process
52. ge developed in 1972 by Dennis Ritchie at the Bell Telephone Laboratories C CBC CCC CCM CE CFB CMAC CMOS cmp CTR CTRo DDR DFF DI DIP DMA DO general purpose computer object programming language developed from C programming language Cipher Block chaining confidentiality block cipher mode Clock Conditioning Circuit Counter with CBC MAC is a confidentiality and authenticity block cipher mode Chip Enable signal Cipher FeedBack confidentiality block cipher mode Cipher MAC authenticity block cipher mode Complementary Metal Oxide Semiconductor Comparison Counter mode confidentiality block cipher mode Cipher Text Register output Double Data Rate D flip flop circuit Data In Dual In line Package of switches Direct Memory Access Data Out DPRAM Dual Port RAM ECB Electronic CodeBook confidentiality block cipher mode ES FBGA FIFO FIPS FLASH FPGA fps GCM GF HSYNC PC I O IDE IP JTAG KI KO LCD LED Embedded System Fine Ball Grid Array First In First Out Federal Information Processing Standard Flash memory is a non volatile memory that can be electrically erased and re programmed Field programmable Gate Array frames per second Galois Counter mode high throughput block cipher mode for confidentiality and authenticity Galois Field Horizontal Synchronization signal Inter Integrated Circuit Input Output Integrated
53. geted for low power applications and therefore its performance was reduced 3 When measuring power consumption Actel Igloo outperformed both Actel Fusion and Altera Cyclone III devices 3 6 2 Analysis of cryptoprocessor core There are two possible ways to design cryptoprocessor 4 First way is to make analysis of all regular available open source processors if they are modifiable to cryptoproces sor Other way is to start building the cryptoprocessor from scratch During the design time designer can inspire in or even utilize control parts from open source processors and design new datapath Nevertheless the cryptoprocessor topic is completely new and no research has been carried out in this field before 4 The cryptoprocessor hasn t been 53 FEI DEMC implemented yet and is just in the design stage 6 2 1 Modifiability analysis of available open source processors All processors except the Leon 3 35 were acquired from opencores org 36 Main criteria for selecting the best processor to be reused were the following e suitable for implementing in FPGA e easily modifiable to cryptoprocessor e VHDL code should be readable and well commented documented e size of implementation has to be reasonable According to these criteria most considered properties of processors were e synthesizability e type of architecture Harvard vs von Neumann e implementation of registers in logic vs in RAM e readability and good modifia
54. ig 6 8 Block diagram of the cryptoprocessor 58 FEI DEMC 6 2 2 1 Architecture with 128 bit datapath Implementation of the 128 bit datapath of the cryptoprocessor is shown in the Fig 6 9 Arithmetic logic unit is broken into separate parts XOR increment compare and flow through operations For most of the block cipher modes XOR operation is required Increment can be used in the CTR block mode counter mode and comparison is usually used during authentication In the center of the architecture is the cipher block Archi din Input 128 Output dout register register 1 0 1 0 vA By Data register dual port GE RAM 16 modules REG 128 A B 000 001 T inc 000 000 flow through cmp A B s i 0751 9 128 vv Adder NC 128 0 1 0 128 A 07 Session Key RAM DI RNG DO cipher lt Inv Main 128 KO Ey 9 ON Main s SO iey a ROM y Fig 6 9 Implementation of cryptoprocessor with 128 bit datapath 59 FEI DEMC tecture allows implementing any type of symmetric cipher with 128 bit data length and 128 bit key length For the particular project AES was chosen as the one recommended by NIST 1 One may notice red colored buses in Fig 6 9 These buses represent paths where keys are transferred and require specia
55. ing signature extraction and comparison alzorithnis 2 39 OE ERA E Z ato wh ae ave Hardware implementation of image processing signature extraction and comparison algorithms 45 7242 24 7439 8 o RE RE Y RO Analysis of the cryptoprocessor core 6 1 6 2 6 3 AES Encryption Decryption module len 6 1 1 Implementation of the shared AES encryptor decryptor core 6 1 2 Implementation of S boxes 200 6 1 3 Implementation of AES enc dec core in FPGA Analysis of cryptoprocessor core 6 2 1 Modifiability analysis of available open source processors 6 2 2 Design of new cryptoprocessor architecture Interconnection of cryptoprocessor with ARM7 Software implementation 7 1 1 2 7 3 ARM firmware design aoaaa aaa k a ka 4 4 USB transport protocol sy owns HOLD HAS KB REED Yd D IU PE software implementation s 208 ee ae RR x EO ER OY 7 3 1 PC interface from user spointof view Conclusion Bibliography Appendices 37 37 40 43 43 44 46 32 93 54 57 62 65 65 66 66 67 70 72 76 List of Figures 1 1 Block diagram of the secured opto electornic system for product trace ADIY oap td 5S atu Som tu Sae tae Sco e See o Sn cr to SU e TD ecc Ne oe TE dto aet 3 1 2 Image acquisition development stage len 5 1 3 S box development stage amp uos sco K A CE EE 5 1 4 AES development stage o oo
56. iplier CLK CLKEN CFGBIGEND nIRQ nFIQ nRESET ABORT Instruction LOCK decoder and WRITE contral logic SIZE 1 0 PROT 1 0 TRANS 1 0 ALU bus A bus Barrel shifter 32 bit ALU B bus DBG outputs DBG inputs CP control CP handshake Instruction pipeline W rite data register Read data register Thumb instruction decoder WDATA 31 0 RDATA 31 0 Fig 2 5 ARM7TDML S architecture design period this memory wasn t available Cypress chip supports USB 2 0 and com municates with Santa Cruz interface by 16 bit wide tri state bus For more details about the module programmer s model and firmware please refer to Cypress CY7C68013A 100AXC manual 11 or Micronic documentation 10 The module is illustrated in Fig 2 6 and Fig 2 7 14 FEI DEMC Fig 2 7 Micronic USB CYPRESS module back side 2 5 X24 camera integration kit X24 kit 6 is a product of ST Microelectronics It was created to demonstrate camera chip features to simplify design for developers and to improve time to market X24 board is shown in the Fig 2 8 Camera chip VS6524 5 is soldered in a small connector board which is placed in the X24 board s socket 6 Logically X24 evaluation board is divided into 3 parts see Fig 2 8 The left part contains Cypress USB controller Altera FPGA and USB connector This part was used in the first stages of project design It helps the developer to find the appropria
57. ision 3 development tool rived from ARM7 external GNU Sourcery G compiler had to be used GNU debugger hasn t been adapted for u Vision 3 yet however Actel SoftConsole application 26 can be used for debugging instead After the firmware is written Intel Hex file is generated This file is subsequently imported into the Flash memory system builder in Actel Libero IDE 17 23 After wards the firmware 1s transferred into the internal flash memory of the FPGA during the configuration stage 29 FEI DEMC 3 4 C design environment Borland C Builder After the system is developed a communication link has to be established with the PC via the USB To control the transfer over the USB line computer application has to be pro grammed This application should be user friendly and needs to be able to communicate with the USB driver One of the easiest ways to program application containing GUI is by using Borland C Builder 20 This development tool is illustrated in the Fig 3 5 File Edit Search View Project Run Component Database Tools Window Help None s D U JF gig Sede Add wei Sviten Data Access Data Conso Eves DatsSnao BOE ADO Intedise WebServices internet cross lriemet WebSnao Fastet Decuien 352 gt ag ERA H VN Eg Ez Object TreeView A Maincpp CIN m I tale WITZ USE Classes MP 7 Terminate true R Camera Stream Viewer Come le
58. l data traffic before being transmitted out of the FPGA has to be encrypted For this purpose cryptoprocessor has to be included in the design in the future 4 3 Image acquisition Once the image acquisition is initiated image data are sent from the external camera into the FPGA Inside the ES DMA controller redirects the traffic outside the FPGA into the external SRAM memory Before a 32 bit word can be transferred into the external SRAM memory it has to be concatenated from a four 8 bit words each pixel is encoded in one byte This concatenation is performed in 8 32 bit converter concatenator block Since incoming data and control signals from the camera have to be synchronized the design contains another PLL which is synchronized to the external clock signal from the camera Afterwards all control signals are registered within this clock domain Before the data can be transferred into the external SRAM memory an address has to be generated For this purpose Address Generator is included in the project This generator is initialized by the controller which communicates with the ARM processor via the APB bus Since ARM7 is the master of the DMA controller acquisition of the image is initiated by ARM7 by switching multiplexers in the DMA controller towards the acquisition part If the acquisition is not performed multiplexers are switched towards the memory controller thus ARM7 is capable of accessing external SRAM memory The DMA con
59. l treatment All these paths could be doubled to secure the integrity of transferred keys Furthermore all the red buses are designed in the way that no key can be multiplexed to the data bus without being encrypted first In case of decryption generated session key for encryption has to be expanded first the last expanded key has to be stored in session key register and only then it can be used for decryption In case of decryption with the main key the last expanded key has to be stored in inverse main key register As shown in the Fig 6 9 128 bit architecture is very convenient but is very ex pensive in terms of FPGA resources If one decides to implement cryptoprocessor with 128 bit datapath 16 memory modules for data registers have to be included as well as 8 memory modules for session key registers AES cipher itself uses 10 memories for stor ing S boxes In this case all 24 memory modules available in Fusion FPGA 2 wouldn t be enough This allows the implementation of the system in bigger FPGA families only The second disadvantage of this robust 128 bit architecture lies in number of used logic resources Each 128 bit multiplexer utilizes 128 tiles In this case all multiplexers utilize about 1400 tiles Further it is important to mention the critical path The architecture was designed to be as symmetric as possible in terms of critical paths delays However the biggest delay is introduced in the right path because of the Adder For
60. m design Although the system should be small and handy its architec ture will be certainly very complex and its detailed structure is not known yet For this reason the objective of my work was to propose an architecture that would be 1 evolutive in order to permit to upgrade the system 2 embeddable in digital devices in order to be small in size 3 featuring sufficient hardware and software means in order to implement easily se rial algorithms and parallel hardware structures 4 secured containing cryptographic means as random number generator and crypto processor 5 easily connectable to internet For the above mentioned reasons AMTeS team has selected the reconfigurable logic de vices FPGAs as the hardware platform The work on the project needed a large spectrum of knowledge and abilities starting from programming and description languages like VHDL Very High Speed Integrated Circuit Hardware Description Language C and C communication protocols like IC Inter Integrated Circuit and USB microprocessor architectures image processing ap plied cryptography and cryptographic protocols It was not easy to acquire all the nec essary knowledge in a relatively short time But the fact that I have the possibility to participate on the development of a product dedicated to very important industrial appli cations has motivated me very much Contents Introduction 1 Overview of the project 2 Description o
61. may have noticed that every line has only 319 pixels not 320 This issue was corrected in hardware part by copying the last pixel Pixel n Blanking pixel n Pixel n 1 DI PK Vf Vf Lf Lf V4 V Fig 2 12 n pixel in video stream Pixel 1 Blanking pixel 1 Pixel 2 pur INTERFRAME BLANKING DATA X Vli X Cli X BLANC DATA X YR X c P K AL AF 4 346 A4 NE XXE Y 4 X x4 X 4 XA x HSYNC yrs de MN a NM o NU MN UG VSYNC f Fig 2 13 Beginning of the frame Pixel 318 Blanking pixel 318 Pixel 319 D 0 X BI c 318 X BLANC DATA X YRI X C 319 X INTERLINE BLANKING DATA POLK V4 V 4 V4 V4 V4 Vf Vi V4 Li HSYNC VSYNC Fig 2 14 End of the first line 20 FEI DEMC Pixel 318 Blanking pixel 318 Pixel 319 D 7 0 Y 318 C 318 X BLANC DATA Y 319 C 319 INTERFRAME BLANKING DATA PK f X ST OK X o Se Le o4 A 4 HSYNO a VSYNC 1 Fig 2 15 End of the frame 2 6 53 DC communication description The camera chip is controlled through IC interface 16 where it acts as IC slave periph eral with its device address 0x20 5 In our case ARM7 processor acts as master device and has full control of the I C bus According to unique states of SDA and SCL data exchange can be established Basic parts of data exchange are start stop acknowledge not acknowledge commands device address containing read write flag register address high and low byte and d
62. n the Actel System Management board 7 Essential part of the ES is the System on Chip SoC based on the ARM7TDMI processor 12 13 32 FEI DEMC 4 2 System on chip based on the ARM processor The SoC is instantiated inside the Actel Fusion FPGA as shown in the Fig 4 2 U ra z lt tc ip lt z ac m X Li Fig 4 2 System on Chip based on ARM processor The main part of the SoC is the ARM processor 12 13 The processor represents the main control unit of the SoC AHB and APB buses represent convenient solution for interconnecting peripherals with the ARM7 Bandwidth critical peripherals i e SRAM block have to be connected to the AHB bus In contrast peripherals with lower band width demands can benefit from the simplicity of the APB protocol The program for ARM7 processor is stored in an embedded flash memory The em bedded SRAM is used for storing temporary results of the calculation For interfacing with an external SRAM memory a memory controller block is necessary Operation of the camera is controlled via the IC interface If more than one device requires access to the external memory DMA controller has to be used In this case external memory is shared by the image acquisition system part of the DMA controller and the ARM7 s memory controller Cypress USB controller block enables ARM7 to communicate with 33 FEI DEMC the PC via Cypress USB module 10 Al
63. nly soft IP ARM core that is used in FPGAs 12 It is fully compatible with ARM7TDMI S core Actel has minimized the size of ARM7 core and maximized speed so it could run in Actel s ProASIC3 and Fusion flash based FPGAs 12 2 It is provided with or without the on chip debug circuitry The debug circuitry is about half the size of ARM core so being able to remove it after the debug may allow design to be implemented in a smaller device Instructions for CoreMP7 are stored in the internal flash memory so there is no need to connect external memory Internal SRAM blocks are also used Using Actel s CoreConsole software CoreMP7 can be implemented with other IP cores to form more complex design 12 2 4 Micronic development module with Cypress USB To establish communication and control between PC and FPGA design Cypress USB module is needed Company Micronic designed USB CYPRESS module 10 which con tains Cypress CY7C68013A 100AXC chip 11 This module complies with Santa Cruz specification therefore it fits to Actel System Management Board After power up while there is no non volatile memory on the module firmware for Cypress chip has to be al ways programmed inside Socket for ROM memory is also on the board but during the 13 FEI DEMC ADDR 31 0 Address register Incrementer bus Address Scan debug incrementer control Register bank 31 x 32 bit registers 6 status registers I 32x 8 E mult
64. o fake the marker The optical signature of the product is encrypted and printed on the product package too We will call this encrypted signature of the original product a reference signature In the authenticity evaluation phase a portable device containing camera scanner will read the area containing marker and calculate its optical signature Then it will read the reference signature decrypt it with the same key that was used in the factory Finally the FEI DEMC reference signature is compared with the acquired and calculated signature If both are equal the product is original In order to authenticate the authentication device itself and to exchange encryption keys some protected channel e g via Internet must exist at least for some short time intervals For some practical reasons modularity the authentication device has to be composed of a secured authentication module connected to an embedded PC via USB interface The PC itself is connected to the authentication authority via Internet Regarding Fig 1 1 the aim of this work is the design of the secured authentication module including USB interface without embedded PC and ethernet connection For practical reasons the architecture have been decomposed to several independent func tional blocks that do not correspond exactly to those given in Fig 1 1 but that were more easy to design together First the data acquisition block including camera initializati
65. of non volatile FPGAs on the market 2 Cypress USB module complies the Santa Cruz interface specifications 10 so it is suitable for the Actel System Management Board Flash memory modules were not used in this project but are available for being used in the future 2 1 Actel system management board Actel System Management Board is a development kit 7 It includes Actel Fusion M7AFS600 FPGA 2 ARM processor is also available for instantiation inside the FPGA 2 12 The board is suitable for creating systems with enhanced power man agement thermal management serial and ethernet communication ARM microproces sor subsystem with external memories PCI ports and Santa Cruz extension connectors Board also includes simple user interface small keyboard DIP switches red and green LEDs and LCD display Configuration as well as debugging is carried out through JTAG circuitry Additionally second A3P250 FPGA is present M7AFS600 FG484 couldn t provide enough free pins therefore A3P250 was included 7 Fig 2 1 illustrates Actel System Management Board 7 The following resources from all available are used e M7AFS600 FPGA 2 e two SRAM memory chips 8 e Santa Cruz interface e Legacy interface e Reset circuitry e JTAG circuitry for FPGA programming only e RS232 port used during development instead of USB FEI DEMC d i ABY E TA Hm i T Wi 3 s amp s we 2332 ti _ o 21 K da ko DO gappi r
66. oftware source codes for Borland C Builder 76
67. on ARM controller and USB interface have been designed simulated and tested In order to validate the function ality acquired image data have been saved in external RAM outside FPGA but inside the module and then transferred to the PC via USB bus in order to be visualized on the screen This part of the work has permitted to connect external devices to the module camera external memory PC via USB bus In the second phase of the project it was necessary to design the core of the cryp tographic module the AES cipher including key expansion procedure The cipher de cipher had to be adapted to the required non volatile FPGA family Namely S boxes implemented in a volatile embedded memory had to be generated inside the device The cipher decipher block has been designed and simulated in VHDL and mapped to the se lected FPGA device The third phase of the project consisted in the feasibility study of the image processing algorithm proposed by the laboratory Together with A Idrissa which has implemented the algorithm in software I had to analyze each function if possible from the point of view of its implementation in hardware FEI DEMC In the fourth and the last phase of the project I had to work on the architecture of the crypto processor This work has started with a study of existing crypto processors and the possibilities of the use of existing open source microprocessor designs as a basis to the future crypto processor a
68. on and final product s authentication algorithms and its feasibility in the selected hardware The analysis of the possible cryptoprocessor implementations im plementation of the AES cipher as well as implementation and mathematical description of S box generation in the logic are described in Chapter 6 Firmware for ARM7 and software in PC development and its first version is introduced in Chapter 7 FEI DEMC 1 Overview of the project The architecture of the whole system is depicted in Fig 1 1 It is composed of the secured authentication device and external authentication authority including product database this authority usually is situated in the factory The product authentication procedure is composed of the preparation and evaluation phase Encrypted product code Secret key Surface of a product Caption Decryption of product of product code code Image Extraction acquisition E C i USB ontroller interface Image part containing marke Embedded PC Ethernet USB interface interface Temporary internet Authentication connection authority Fig 1 1 Block diagram of the secured opto electornic system for product traceability In the preparation stage in the factory the system prints an uncopyable characteristic marker e g a small point on the product scans this printed marker and calculates its optical signature unclonable function The method must guarantee that it is impossible to copy t
69. on of the FPGA with the Actel FlashPro tool 23 24 FEI DEMC 8 Project File Est View Toot Window Heip Bea og tk t DE D Erato Dese Block creation Curert aope vew nps EE aed x t Ready WOL FAM Fuuon DIE MIAFSIO PRG 4M FBGA Fig 3 1 Libero IDE At the beginning VHDL structure has to be created User can choose whether to write his own entities or to take an advantage of generating the entities When writing the code user can insert some specific code structures from templates For including ARM7 processor 12 with its peripherals to the design CoreConsole tool 27 has to be used CoreConsole represents powerful tool for ARM7 inclusion in the design together with its buses peripherals and other AMBA compliant 15 IP peripheral blocks If ARM is not suitable for the application other processor can be used ARM Cortex 8051 ABC etc After the VHDL design is created it has to be synthesized with respect to FPGA resources Synthesis is carried out by Synplify tool 21 During synthesis combinatorial and sequential logic minimization is carried out At the end user is provided with the summary of the synthesis Another synthesis with compatibility check is performed in the Designer tool button Compile Before configuring the FPGA all FPGA resources used in the design have to be as signed to a special location of the FPGA This stage is called Placement When all re 25 FEI DEMC
70. pdf ST MICROELECTRONICS M29WS00DT SMbit 3V Sup ply Flash Memory datasheet 2004 available online http www btdesigner com pdfs M29W 800D pdf MICRONIC USB board datasheet 2006 CYPRESS CY7C68013A EZ USB FX2LP USB Microcontroller datasheet 2008 available online http www cypress com docID 5485 ACTEL CoreMP7 datasheet 2007 available online http www actel com documents CoreMP7_DS pdf 72 FEI DEMC 13 ARM LTD ARM7TDMI S Technical Reference Manual 2001 available online http infocenter arm com help topic com arm doc ddi0234b DDI0234 pdf 14 WIKIPEDIA ARM7TDMI 2009 available online http en wikipedia org wiki ARM7TDMI 15 ARM LTD AMBA Specification 2001 16 NXP The P C Bus Specification 2000 avallable online http www nxp com acrobat_download literature 9398 3934001 1 pdf 17 ACTEL Libero IDE Quick Start Guide for Software v8 4 2008 available online http www actel com documents gettingstarted_ug pdf 18 MENTOR GRAPHICS ModelSim User s Manual software version 6 3g 2008 available online http www actel com documents modelsim_ug pdf 19 KEIL Lu Vision User s Guide 2009 available online http www keil com support man docs uv3 20 BORLAND Borland C Builder reference guide 2002 21 SYNPLICITY Synplify FPGA Synthesis 2008 available online http www actel com documents synplify_ref_ug pdf 22 ACTEL Designer v8 4 User s Guide 2008 23
71. pecial uncopyable marker has to be recognized in one of the acquired images Afterwards image has to be processed to be suitable for extraction of the signature Example of the marker is shown in the Fig 5 1 Fig 5 1 Special uncopyable marker for optical signature extraction After the marker is found in the image image processing operations are performed as follows 1 Computation of optimal global image threshold using Otsu s method 2 Binarization of the image 3 Application of 2D median filter 37 FEI DEMC 4 Localization of the circle and rectangle objects in the image 5 Compututation of the angle between horizontal plain and rectangle s longer edge 6 Rotation of the image 7 Trimming of the image to contain only circle object 8 Move of the circle object to the center of the image A Uc B Fig 5 2 A Scan of original print B Binarized and filtered C Angle estimation emer A B C Fig 5 3 A Rotated B Dot localized C Centered and trimmed Examples of image processing steps applied on the scan of original print are shown in the Fig 5 2 and Fig 5 3 After the image is processed optical signature can be extracted For this purpose computation of the Freeman code is favorable Freeman code describes an outline of the object At the beginning the first pixel of the object is located Subsequently the next pixels in the edge are located Each pixel is des
72. ption Standard in non volatile FPGAs Abstract in Slovak Cie om pr ce je n vrh architekt ry t dia uskuto nite nosti zabezpe en ho optoelek tronick ho syst mu pre vystopovanie produktov a realiz cia prototypu z vybran ch blokov Pr ca demon truje implement ciu vlo en ho embedded syst mu zalo en ho na Actel Fusion FPGA Field programmable Gate Array prepojen ho s miniat rnou externou kamerou od spolo nosti ST Microelectronics Syst m komunikuje s PC pomocou Cy press USB rozhrania Jadro syst mu je tvoren SoC System On Chip zalo en m na ARMT7TDMI procesore Tento SoC bol implementovan vo Fusion FPGA ktor je s as ou Actel System Management board Pr ca tie zah a diskusiu o implement cii algoritmov pre spracovanie obrazu spolu s autentifik ciou produktov a taktie anal zu mo n ch implement ci kryptoprocesora pre utajenie a autenticitu pren an ch d t as pr ce je venovan problematike implement cie AES Advanced Encryption Standard ifr tora v nevolatiln ch z ang non volatile obvodoch FPGA TECHNICK UNIVERZITA V KOSICIACH Fakulta elektrotechniky a informatiky Katedra elektroniky a multimedi lnych telekomunik ci DIPLOMOV PR CA Student ubo GA PAR tudijn odbor Elektronika a telekomunika n technika Akademick rok 2008 2009 N zov pr ce v slovenskom a anglickom jazyku N vrh opto elektronick ho syst mu s kryptografick m zabezpe
73. put of MixCols with round key o Round 10 not used Add round key B used instead reason key has to be added before MixCols operation e Decryption o Round 0 XORing input data with original 017 round key o Rounds 1 to 10 not used 2 S boxes implemented as LUTs in embedded dual port memories Each S box is switchable between being direct or inverse Each embedded memory block can operate as two direct S boxes or two indirect S boxes 3 S boxes will be discussed in section 6 1 2 in more detail 45 FEI DEMC 3 Add round key B Operation of XORing data with round key It is implemented after Shift rows multiplexer e Encryption o Round 0 to 9 not used o Round 10 XORing data from shift rows multiplexer with last round key before registration and output e Decryption o Round 0 not used Add round key A used instead o Round 1 to 10 XORring data from shift rows multiplexer with all round keys except original key 4 InvMixColumn MixColumn block is shared by both encryption and decryption InvMixColumn was implemented according to V Fischer amp M Drutarovsky pro posed serial decomposition of InvMixCols 32 5 Data in reg Data out Key in reg Key out registers are shared In the Fig 6 2 implementation of the key expansion block is shown In key ex pansion block many resources are shared between forward used during encryption and backward used during decryption expansion of the key
74. r later denoted as direct cipher and decipher later denoted as inverse cipher are reversed to one another implementation of encryptor and decryptor consumes many logic resources If some modifications are made some operations in inverse cipher are swapped resource sharing between encryptor and decryptor is possible 1 6 1 1 Implementation of the shared AES encryptor decryptor core Implementation of shared AES Encryptor Decryptor core is shown in the Fig 6 1 User has a possibility to select Encryptor Decryptor or shared Encryptor Decryptor core Red components in the Fig 6 1 are Encryptor core specific and green components are De cryptor core specific Black components are used in all cores As shown in the Fig 6 1 44 FEI DEMC InvMixCols MixCols not round 0 decrypt AND Y decrypt 1 Roundkey d x Inverse decrypt shift rows Shift rows x A li 1 DATA OUT data out d 128 SBOX 16x ec ad TE ata in DATAIN 178 REG 9 i nreset nreset nreset round 0 Roundkey Fig 6 1 Shares AES Encryption Decryption core the following logic parts are shared 1 Add round key A Operation of XORing data with round key It is implemented after round zero multiplexer e Encryption o Round 0 XORing input data with original 017 round key o Rounds 1 to 9 XORing out
75. rchitecture Following this study I have proposed two architectures of the crypto processor having 128 bit and 32 bit datapath respectively Course of development is illustrated in Fig 1 2 to Fig 1 6 in detail respectively All stages carried out by the AMTeS team are visualized by green color My own work or in collaboration with the AMTeS team are illustrated by blue color Acquired first version of AES cipher without decipher key expansion and S box generation is shown by red color Expected development in the future is visualized by brown color ENBEL LIRNNNNET raio eooo l Entre F E r be E E E Fig 1 2 Image acquisition development stage Image acquisition EEREN 4Q 2008 SEED 2009 2009 mented orial logic exl m a8 x So o DS ion matrices tive polynomial Fig 1 3 S box development stage FEI DEMC January 2009 February 2009 March 2009 Fig 1 4 AES development stage 09 LLI od d and ation F 10 2009 April 2009 LEE Crypto processor sryptoprocessor acks Fig 1 5 Cryptoprocessor development stage 0 192009 SE LE Futwe from image t implementation C o 5 2 Z m ea 15 wW On Fig 1 6 Development and analysis of potential implementation of image processing and product authen tication stage FEI DEMC 2 Description of hardware platform Designing of such
76. rithms are developed too and finally the best algorithm will be chosen The work has dealt with several questions and difficulties concerning the particular project whereas the most significant obstacles for the research were the stability of cam era operation with easy configuration optimized VHDL design inside the Actel FPGA and setup of the USB interface During the design of AES cipher module mathematic basics in the field of Galois fields had to be studied and applied in the design AII these difficulties have been overcome with success and the project has met all the requirements needed for its realization The most discussed and researched parts were the VHDL optimization with frame corruption issues optimized generation of S boxes inside the FPGA and study of third 70 FEI DEMC party processors VHDL codes Embedded system was able to capture frames with the frame rate of 30 fps The only part that slowed down the frame rate was the USB part Because of the USB module and the USB driver obstacles PC frame rate was rapidly decreased to 3 4 fps Because visualization served for frame check only speed of frames per second in the PC is not important as long as embedded system is capable of real time capturing A lot of mathematic calculations and simplifications were necessary to derive transformation matrices These matrices were successfully implemented in transforma tion blocks Basic theory in the field of LFSRs NLFSRs an
77. roceeding throughout various works of arts and coming to the modern brands of fashion no original product could have been saved from the threat of being copied Smugglers have always tried to gain profit by using realizations of ideas of other people However with the expansion of supplies and demands beyond the borders of individual countries and with the existence of the free market the problem with fake products starts to be more important nowadays than ever before And it is the task of new technologies to develop new systems and procedures to detect the originality of products As a result this thesis deals with one of the possible technologies that could be used for solving this problem The product authentication method proposed by the Hubert Curien Laboratory later just LHC together with the SignOptic company permits to recognize and to authenticate products using image processing The image processing method algorithm proposed by this consortium is relatively simple so that it could be embedded in a small and portable FEI DEMC hardware unit Since the authentication device can be used in potentially hostile environ ment the authentication data and other confidential information has to be protected by secured cryptographic algorithms The aim of this thesis is to propose an architecture of secured embedded system mod ule composed of several functional parts simple camera with integrated optics and digi tal output image pro
78. s also called tiles 2 Chip includes two PLLs six CCCs as well as internal RC oscillator 100 MHz and Crystal oscillator 50 MHz external crystal oscillator was used instead 2 Accuracy of RC oscillator is 1 The device includes 4 Mb of flash memory which is divided into two separate 2 Mb blocks Flash ROM of capacity 1 kb is also included Total amount of SRAM is 108 kb divided into 24 SRAM blocks Each block can store 4608 bits and allows these configurations 4608x1 2304x2 1152x4 512x9 Dual Port and 256x18 Single Port M7AFS600 is packed in FG484 FBGA from which 172 pins form digital I Os and 40 pins form analog I Os Fig 2 2 shows structure of M7AFS600 2 2 2 3 Fusion core The Fusion core consists of logic cells called VersaTiles which support 3 input LUTS Latches with clear or set and D flip flops with clear or set and enable 2 LUTs are very important when used to create combinatorial logic Latches and D flip flops are essential structures for sequential logic Structure of VersaTile 2 is shown in Fig 2 3 Every VersaTile is connected to its 8 neighbors by ultra fast local lines 2 For con necting longer distances long line and very long line resources are used Fig 2 4 shows 10 FEI DEMC Bank 0 Bank 1 TiocooonaaaGa0000000000870000000000000000000000 2 ccc a n SRAM Block g 4 608 Bit Dual Port SRAM a or FIFO Block a Osc E a a I Os o CCC PLL EI n a a
79. s fe REGISTER ADDRESS TIME LOW BITS iS 1 STOP SIETI LI EJ LI LI EEA CO i 0x03 MER CN Fig 2 17 Read operation with the internal register OxC003 23 FEI DEMC 3 Description of the software development tools The quality of special design environments with development tools is essential during the design stage The absence of debugging capabilities syntax highlighting or possibility to change unpractical eye tiring background color can slow down the creative process and lead to user s exhaustion Therefore a good development environment becomes essential During the design of the particular project the following development environments were used e Libero IDE from Actel Corporation version 8 4 17 with SP1 e ModelSim from Mentor Graphics Corporation version 6 3g 18 e Li Vision3 from Keil Corporation version 3 62c 19 e Borland C Builder version 6 0 20 3 1 Libero IDE Libero IDE represents a special development environment created by Actel Corporation 17 The user deals with this environment during all stages of VHDL design Libero IDE is illustrated in the Fig 3 1 Design flow with the Libero IDE consists of the following steps e Creation the VHDL code or generation by wizards e Synthesis of the VHDL code by Synplify tool from Synplicity Inc e Placement and Routing by Actel Designer tool 22 e Generation of the configuration file and back annotation for timing analysis e Configurati
80. sleep state play pause stop control etc 5 Microprocessor monitors and controls all camera operations 5 It is the main control 16 FEI DEMC Fig 2 9 Camera chip VS6524 in scale 7 1 element inside the camera chip It performs the following tasks handles IC communica tion video pipe configuration automatic exposure control flicker cancellation automatic white balance dark calibration and active noise management According to the selected output video format video timing and video pipe are ad justed 5 VS6524 has very rich image processing features All image processing features are processed in video pipe sharpening gamma correction YUV conversion output for mat adjustment cropping contrast adjustment saturation adjustment etc There are two equal video pipes in VS6524 pipe 0 and pipe 1 Each pipe can have its own im age processing settings Only one pipe can output at a time Pipes can be used to alter between two sets of settings very quickly There is also possibility to alter pipes every second frame In this project only pipe 0 was used Fig 2 10 illustrates simplified structure of camera chip 5 After power up initialization has to take place During the initialization internal camera registers are being accessed and the camera is being configured After the ini tialization has taken place it is possible to start the capturing process and data are sent to the output interface These are
81. te configuration for camera chip easily This part was later disconnected by jumpers in middle part The middle part contains interface select jumpers 12 MHz crystal oscillator and camera socket Camera mini board is placed in this socket Camera chip is soldered to this mini board in its center The Right part contains voltage translation chip and connectors for external interface The camera operates with 2 5 V 5 but Actel FPGA board supports 3 3 V 2 This is the reason why 15 FEI DEMC Fig 2 8 X24 camera integration kit voltage translation chip is used in X24 board X24 board has to be connected to Actel FPGA System Management Board 7 2 6 STM VS6524 camera Camera chip V 6524 from ST Microelectronics is a configurable system on chip 5 Cam era chip has 3 MPixel CMOS array 5 Fig 2 9 shows this camera chip in scale 7 1 5 System consists of a microprocessor clock generation circuit video timing circuit VGA pixel array video pipe and PC interface 5 Inside the camera clock generator is driven with the external clock signal 5 In this project 12 MHz external clock source was used All the external control of the camera is carried out by modifying internal camera reg isters through C interface signals SDA and SCL 5 By modifying register s content user is able to adjust many camera features like contrast saturation white balance out put format fps blanking data HSYNC and VSYNC signals
82. ternal registers To sustain security of the system it is preferable to implement two sets of registers Data registers and key registers Key registers are special registers where main key as well as session keys are stored These key registers have to be inaccessible from outside of the cryptoprocessor 4 6 1 AES Encryption Decryption module Main part of the cryptoprocessor is the AES module for encryption and decryption AES is a new encryption standard approved by NIST as FIPS 197 1 Robustness of the algorithm assures sufficient security of the confidential data after being encrypted AES 1s symmetric cipher Size of the plaintext is limited to 128 bits and size of the key can be 128 192 or 256 bits While sufficient security can be assured with 128 bit key AES module used in this project works only with 128 bit If needed the project can be expanded in the future 43 FEI DEMC AES algorithm 1s divided into 10 rounds while the following operations can be found in individual rounds 1 e Substitute bytes e Shift rows e Mix columns e Add round key When decryption is performed inverse operations are carried out 1 e Inverse shift rows e Inverse substitute bytes e Add round key e Inverse mix columns While the key length is only 128 bits key has to be expanded 1 After expansion ten new 128 bit round keys are generated For more detailed description refer to AES standard FIPS 197 1 While steps of the ciphe
83. the most important signals PCLK HSYNC VSYNC and D7 DO A detailed description of initialization will be discussed later For further camera s operation control description refer to the camera reference manual 5 17 FEI DEMC Clock FC interface SDA CLK generator FC SCL CE Pe Microprocessor vi VREG p VDD GND Video timing Statistics generator Gathering FSO AVDD VSYNC HSYNC VGA Video pipe PCLK Pixel array D 0 7 Hy Fig 2 10 Simplified block diagram of ST VS6524 camera chip GND 2 6 1 Initialization of the camera As mentioned before the camera initialization is carried out by configuring appropriate internal registers 5 First of all the camera chip has to be connected to 2 8 V voltage source external clock source 6 5 to 26 MHz and CE pin set HIGH 5 Subsequently internal camera registers can be accessed through C interface pins SDA and SCL 5 PC 8 bit device address of the camera is permanently set to 0x20 while LSB bit is shared with the read write flag will be described later Before any commands can be sent to the camera internal microprocessor must be enabled 5 By writing value 0x06 to the register 0xC003 internal microprocessor is en abled Subsequently digital O pins has to be enabled by writing 0x01 to the register 0xC034 After these two registers have been configured rest of registers can be config ured The next step could be
84. tional simulation is used to observe waveforms of the signals without respect to placement routing and behavior of the FPGA Timing simulation respects placement and 27 FEI DEMC routing and all characteristics of the targeted FPGA To perform timing simulation sdf file 22 has to be imported into the ModelSim 18 One of the most commonly used tools for VHDL simulation is ModelSim 18 Before the simulation can be performed VHDL testbench has to be created Afterwards design with testbench is imported to the ModelSim All used libraries have to be imported too Once imported design has to be compiled After the compilation is performed simulation can be executed The designer has to specify the duration of the simulation If the design is very complex computation of the simulation take very long Results of the simulation are displayed in the Waveform window see Fig 3 3 18 According to the complexity of the project it is advantageous to read input values from the text file and store the results of the simulation Special warning messages or error messages can be conditionally displayed in the transcript window gui ove detour 7 7 As ee SHO ae s eic fa file Edit View _Add Format Tools Window m eS BOO gt aE CETT 4 EF 100 ps S EL EE L sy j A jee ere Res e Ba BK amp A A Ho Data Ho Dats Ho Data Ho Dats No Data Ho Data No Data To Data Ho Da
85. troller is illustrated in the Fig 4 3 Zones enclosed within the red line belong to the ARM7 s clock domain and zones enclosed within the green line belong to the camera synchronized clock domain I have chosen this solution as the only feasible one If the data were acquired by the ARM processor and subsequently transferred into the memory it could consume all processor time and no other control and processing would be possible State diagram of the main image acquisition state machine is illustrated in the Fig 4 4 After the acquisition is initiated by ARM7 state machine abandons IDLE state and 34 FEI DEMC MEMORY CONTROLLER ADDRESS BUS 0055 52 00 ADDRESS E APB BUS EXT SRAM CONTROL MEMORY CONTROLLER DATA BUS JI 4 ee ees TROU A J O I H EXT SRAM DATA 32bit DATA 01 1 Fig 4 3 Illustration of the DMA controller with two clock domains waits until vertical image synchronization signal VS YNC is LOW In the next state state machine waits until vertical image synchronization signal changes to HIGH If it happens it signalizes the beginning of the image State machine immediately enters capture state where an acquisition is performed After the image is acquired VSYNC signal changes to LOW and state machine enters IDLE state Status signals indicat
86. ts Cursor 1 20000137 ps J ds 5187970 ps to 5941 ns i Now 20 us Delta 4 Fig 3 3 Waveform view in ModelSim Furthermore the whole simulation process can be automated by creating do batch file 18 File can be executed inside the Modelsim command line by the command do filename do 28 FEI DEMC 3 3 Keil uVision 3 After the processor is put into the design the source code has to be created One of the best firmware development tools is Keil u Vision 3 19 This professional development tool allows users to write program in c code or assembler code simulate the code gener ate programming Intel Hex file and debug the code directly in hardware if the hardware is compatible with u Vision 3 Keil ui Vision 3 main window is illustrated in the Fig 3 4 Since the original Keil u Vision 3 compiler is not compatible with Actel CoreMP7 de Mie se GAK ono 0 E File Edit View Project Debug Flash Peripherals Tools SVCS Window Help asugi aBn acr Esa a6aaQj nmeeerm SHHe z mgr ccce 09 x while 1 char aaa 0 char key sent 0 Clear key sent flag char key 0 char a b c d e f clear key int i key 1 key sent Main c 11 warning 177 D variable aaa was declared but never referenced Main c 13 warning 550 D variable key was set but never Main c i4 warning 177 D variable f was declared but never referenced Simulation Fig 3 4 Keil uV
87. ubs 800 38D SP 800 38D pdf 32 V FISCHER M DRUTAROVSKY P CHODOWIEC AND F GRAMAIN nvMix Column Decomposition and Multilevel Resource Sharing in AES Implementations Very Large Scale Integration VLSI Systems IEEE Transactions on Volume 13 Issue 8 Aug 2005 pp 989 992 ISSN 10638210 33 A SATOH S MORIOKA K TAKANO AND S MUNETOH A compact Rijndael hardware architecture with S Box optimization Proc Theory and Application of Cryptology and Information Security ASIACRYPT 01 ser LNCS vol 2248 Gold Coast Australia Springer Verlag Dec 9 13 2001 pp 239 254 TA FEI DEMC 34 D CANRIGHT A very compact s box for AES Proc International Workshop on Cryptographic Hardware and Embedded Systems CHES 05 ser LNCS vol 3659 Edinburgh Springer Verlag Aug 29 31 2005 pp 441 455 35 JIRI GAISLER SANDI HABINC AND EDVIN CATOVIC GRLIB IP Library User s Manual LEON3 quick start guide Quick Start Guide 2009 available online http www gaisler com products grlib grlib pdf 36 OPENCORES OpenCores database Processors 2009 available online http www opencores org 75 FEI DEMC Appendices CD containing the following Appendix A electronic version of this document Appendix B VHDL source codes of e ARM7 subsystem e mage acquisition subsystem e S box with generator e AES cipher decipher core Appendix C ARM7 s firmware souce codes for Keil Li Vision 3 Appendix D PC s

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