Multiport VNA Measurements - PORTO
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1. 1 1 I 1 1 1 i 1 1 1 i Microwave 1 1 E Sources Switches pn I 4 EA a RR i i a amt Dmi Am3 Dmg an a i gt a ag a ae Sy oti aoe 1 b b i l am2 m2 am4 m4 1 id i l gt da a4 lt i Baa by by D a m m e e e e o ee ee me ee o oa ee ee ee o ee o m oae mo e e oe mo o oae a o a a oa a oas a a mme me meee me mee m me ee m m_e mm ee m m m m me m es en e_m m m m m_m e mn m_m me m m n ee m e e me e_m e Microwave Sources Switches Figure 16 a Complete reflectometer multiport architecture and b an example of a partial reflectometer architecture assumption that each port has two possible states as shown in Figure 17 state A Figure 17 a where a complete reflectometer is connected and state B Figure 17 b where only the reflected wave test cou pler is available The new calibration approach introduces e simple compact and easily scalable math use ful for both complete and partial reflectometer architecture e flexible standard sequence e reduced number of standards and connections The new error model generalizes the ten terms of the well known two port error model to a multiport error model and allows the combination of measurements at different ports of different standards in a single linear system with 6 n 1 error terms The generalized equa tion for error coefficient computation or de2. Politecnico di Torino Porto Institutional Repository Article Multiport VNA Measurements Original Citation T G Ruttan B Grossman A Ferrero Teppati V J Martens 2008 Multiport VNA Measurements In IEEE MICROWAVE MAGAZINE vol 9 n 3 pp 56 69 ISSN 1527 3342 Availability This version is available at http porto polito it 1680209 since July 2008 Published version DOI 10 1109 MMM 2008 919919 Terms of use This article is made available under terms and conditions applicable to Open Access Policy Article Public All rights reserved as described at http porto polito it terms_and_conditions html Porto the institutional repository of the Politecnico di Torino is provided by the University Library and the IT Services The aim is to enable open access to all the world Please share with us how this access benefits you Your story matters Article begins on next page 96 IEEE microwave magazine Thomas G Ruttan Brett Grossman Andrea Ferrero Valeria Teppati and Jon Martens t would have been difficult to predict even 15 20 years ago that microwave design and the personal computer PC would be as closely linked as they are today In those days PC manu facturers were excitedly claiming clock speeds of 16 33 MHz while the microwave designer was routinely applying well known design skills to problems into mil limeter wave frequencies The proliferation of PC appli cations and I
3. 66th ARFTG Conf Dec 2005 Session 4 Paper 4 7 J C Tippet and R A Speciale A rigorous technique for measur ing the scattering matrix of a multiport device with a 2 port net work analyzer IEEE Trans Microwave Theory Tech vol MTT 30 pp 661 666 May 1982 8 J C Rautio Techniques for correcting scattering parameter data of an imperfectly terminated multiport when measured with a two port network analyzer IEEE Trans Microwave Theory Tech vol MTT 31 pp 407 412 May 1983 9 B Young Wideband 2N port S parameter extraction from N port data IEEE Trans Microwave Theory Tech vol MTT 46 pp 1324 1327 Sept 1998 10 I Rolfes and B Schiek Multiport method for the measurement of the scattering parameters of N ports IEEE Trans Microwave Theory Tech vol 53 pp 1990 1995 June 2005 11 H C Lu and T H Chu Multiport scattering matrix measure ment using a reduced port network analyzer IEEE Trans Microwave Theory Tech vol 51 pp 1525 1533 May 2003 12 A Ferrero U Pisani and K J Kerwin A new implementation of a multi port automatic network analyzer IEEE Trans Microwave Theory Tech vol MTT 40 no 11 pp 2078 2085 Nov 1992 13 A Ferrero F Sampietro and U Pisani Multi port vector network analyzer calibration A general formulation IEEE Trans Microwave Theory Tech vol MTT 42 no 12 pp 2455 2461 Dec 1994 14 J Martens D Jud
4. ITRS data on package pin count 1 Figure 4 Typical 3 D digital interconnect configuration IEEE microwave magazine q Aivnces TGA f Hin PCL g EXPRESS 6 3 unbalanced lines To first order this is due to the vir tual ground between the pair of lines in a differential transmission line which reduces the requirement for a solid reference ground plane for acceptable high fre quency performance 3 Challenges of Measuring Digital Interconnections in the Analog World Since most of the digital interconnect structures are a com bination of many parallel data lines and or differential serial bus designs the challenge of performing high fre quency measurements is quite different from the typical micro wave device where there are only a few I O lines to worry about Additionally PCBs are the circuit media of choice and will include both planar and o three dimensional 3 D struc Rapid O tures as found in backplane server chassis and memory modules illustrated in Figure 4 So the measurement prob lem is compounded by the need to connect many data 2005 2010 lines possibly in more than one plane while making good high frequency connec tions from the PCB structures to the VNA instrumentation which typically has coaxial test ports To provide a reliable test interface between the VNA and PCB test structures the two choices are to either use coaxial to PCB launchers or probe directly to the PC
5. S Ii SRS 41 44 43 44 T4 T Figure 10 Each of the six two port measurements produces a 2 x 2 submatrix of the final 4 x 4 matrix which is a function of the terminations applied T14 Recall that it has been required that all of the ter minations are known Given this it is possible to use the generalized scattering matrix renormalization to mathematically transform each m port from the nor malized port impedance of the measurement system to the normalized port impedance of the termina tions 7 Further study on this topic is captured in 8 11 and while each represents a slightly different approach to this problem the required use of some quantity of known terminations still exists Practical Limitations A practical limitation exists in many measurements when attempting to apply the techniques described above and this occurs most notably when the interface to the DUT fixture is made using microprobes rather than coaxial connectors With microprobe measurements it is often the case that the terminations are either patterned or assembled onto the fixture In these cases it is then necessary to design multiple copies of the fixturing to accommodate all the various port termination configurations that must be measured Figure 11 To be successful with this approach it is first neces sary to assume that the behavior of the multiple DUTs and fixturing is sufficiently repeatable If this assump tion is valid then the
6. and connector losses are also very high due to the frequencies involved It is particularly important to minimize losses after the test couplers as this will affect raw directivity and hence measurement sta bility Stability is even more important as the port count increases since simplified calibrations will be desirable and tend to be more sensitive to stability 3 Switch loss per unit isolation gets worse at higher frequencies Thus one should carefully consider iso lation needs and minimize complexity of the switch fabric This means that while all N S parameters must be measurable it may not be necessary that every port be drivable by every source 4 At higher frequencies single pole double throw SPDT switches perform much better in terms of loss per unit isolation than single pole triple throw SP3T or single pole quadruple throw SP4T switch es Consider this in setting up the switch fabric 5 Certain details of the measurement system may come into play For example if the measurement system is source locking i e using a coupled ref erence signal to lock the source it may be desir able to keep a tighter control on how reference couplers are placed June 2008 6 For calibration simplicity it would help if the load match consistent The load match is determined by the match presented by a port is independent of the dri drive side SPDT off state impedance in almost all cases ving port With a general archit
7. architectures as illustrated in the four port example in Figure 16 b some extensions of the ten term error model have been proposed in the past 15 In most cases off the shelf calibration techniques for multiport systems suffer from the following drawbacks e The implementation is complex and in many cases the formulation is not port scalable e A rigid standard sequence must be followed e Asignificant number of standards and a very large number of connections are required Recently a new calibration methodology for multi port VNAs with partial reflectometer architectures was introduced by the authors in 16 It is based on the LOG MAG 10 000 dB DIU a ae ee SWEEP SETUP gt START 0 040000000 GHz STOP 65 000000000 GHz ee ek cannes SET CENTER SPAN 401 DATA POINT S Slit 0 162400000 GHz aT STEPSIZE GHz 65 000000000 LOG MAG C W MODE OFF 10 000 dB DIU MARKER SWEEP DISCRETE FILL E e a HOLD BUTTON FUNCTION ee ee ee ee ee ee O R OA TEST SIGNALS aa eet ofa dane a rer ee or ee ee a a PRESS lt ENTER gt Find TO SELECT OR TURN ON OFF GHz 65 000000000 Figure 15 The measurement of a coaxial delay line 42 h after calibration There was some insertion loss drift due to cables and temperature changes IEEE microwave magazine June 2008 E i 1 1 1 i 1 1 i 1 1 i 1 I 1 i 1 1 I i 1 I i 1 1 1 1 1 1 i 1 i I 1 1 1
8. ist ress the lt lt Insert Button od je g Inserting THRU between two ports means a through connection is possible g Inserting TRL between two ports means perform a TRL cal between the two arts er completing the matrix press Compute equence Figure 20 Dynamic calibration connection matrix and standard sequence IEEE microwave magazine and types cause some problems Indeed a thru con nection is possible only between Ports 1 and 2 All other ports can be connected only through the use of adapters These issues typically require time consum ing adapter removal techniques losing measurement accuracy and introducing more standards connections The new software instead allows for building a cali bration Figures 19 and 20 which fits the types of con nectors and restrictions imposed by the DUT To deter mine the standard sequence the software splits the ports into different groups according to the user speci fication see Figure 19 Then it merges the groups as much as possible into fully known two port devices or unknown two port devices in this case one unknown thru and computes the final sequence as shown in Figure 20 In this way no adapter removals are needed and a high level of accuracy is achieved Examples of Interconnect Device Measurements The previous sections described the VNA hardware and calibrations required to support multiport measure ments But there are additional capabil
9. of con nections jumps to 58 Figure 21 June 2008 Taking maximum advantage of the calibration methods described previously would reduce this 12 port SOLT calibration to 25 port connections 6 However even making 25 port connections repeatable presents challenges Figure 22 illustrates a 12 port microstrip PCB struc ture where contact is made through replaceable 2 4 mm coaxial connectors This structure was measured after the completion of a reduced 12 port thru reflect line TRL calibration which had required 28 port connec tions with the results shown in Figure 23 As seen from the measurements in Figure 23 five of the six microstrip structures demonstrated the expected behavior However the microstrip structure placed between Ports 2 and 8 was clearly different Upon fur ther investigation it was determined that the connector on Port 2 did not have the proper torque applied dur ing the calibration Correcting the connector torque during a complete recalibration would again require 28 connections to be made However if the only standards that contacted Port 2 could be remeasured and the SOL SOL a Figure 21 Ball diagrams for SOLT calibrations a Two port requiring eight port connections and b 12 port requiring 58 connections Figure 22 12 port coax microstrip structure June 2008 error coefficients recalculated this would reduce the number of connections that need to be made to f
10. pins used for both signal and power delivery an estimate that 20 30 of these pins are dedicated to signal lines is not unreasonable But in order to keep system physical dimensions from increasing at a similar rate it is necessary that these signals be placed more closely together More signals placed closer together leads to increasing density ITRS 2006 Update Performance On Chip 2009 2011 2013 2015 2017 2019 multiport VNA measurement Figure 1 Abstracted International Technology Roadmap for Semiconductors ITRS data system details calibration and for on chip performance 1 June 2008 IEEE microwave magazine ar 58 Finally the trend to differential lines for the signal path is also driven by the need for speed Since the ground planes for typical board level interconnect structures in computer systems have many routing clearance holes and plane discontinuities it is diffi cult to create a well defined reference ground plane for transmission lines Differential balanced lines are used in many high speed digital systems for board level transmission lines The reason for this is that differential lines will have improved high fre quency performance compared to single ended 100 10 o 1 4 D 5 0 1 r j g a p asma 1980 1985 1990 1995 2000 Figure 2 Projected interface data rate trends 2 ITRS 2006 Update Package Pin Count Package Pins 0 2005 2010 2015 Figure 3 Abstracted
11. resulting six measurements are shown in Figure 12 As in the example of Figure 9 the off diagonal ele ments of the 4 x 4 S parameter matrix are each mea sured once while the on diagonal elements are mea sured multiple times However note there is not one unique termination for each port but three different terminations on each port depending on the fixture Figure 12 If the terminations are integrated with the DUT i e as thin film resistors it is difficult to know their behavior independent of the DUT If the terminations are assembled i e as surface mount technology SMT components the same characteri zation difficulty exists as the assembly process con June 2008 tributes to the terminations behavior Therefore for this approach to be successful an additional assump tion that the terminations are sufficiently repeatable is often necessary Benefits of Using n Port Instruments for n Port Devices The previous section explained that while it is possible to measure n port devices with lt n port instruments some assumptions must be made Regardless of the device multiple measurements must be made post processed and combined to produce the desired result In the worst case repeatable behavior across manufac turing and assembly variances must be assumed For devices up to 12 ports n 12 Table 1 quantifies how these assumptions scale versus the number of available instrument ports I I I I Measur
12. wafer and coaxial ports gender connectivity problems or mechanical dimension problems where ports are separated too far to be easily connected Dynamic cali bration allowing the user to decide where to connect thrus or unknown thrus is crucial in these cases Moreover as the number of ports increases a reduced standard sequence means there is less probability for mistakes due to loose connectors or bad probe contacts Reduced calibration time is another important benefit both in R amp D and production test applications A software program 17 has been developed that incorporates these measurement and calibration methodologies providing the capability to compute an optimized standard sequence which reduces the number of connections and the corresponding mea surement complexity Dmi Figure 17 a State A and b state B configurations IEEE microwave magazine 65 66 For example let us consider a directional coupler with two APC7 and two female SMA ports see Figure 18 This is a typical case where the connector gender Figure 18 An example of a DUT a directional coupler with two SMA and two APC7 ports Figure 19 An example of dynamic calibration for a four port system _MMSNT_V2 3_ 07 _06_07 TSet tst ee a a M Calibration Properties et your connectivity properties in the grid bove elect the grid cell between the two ports in uestion elect a property from the available properties
13. 5 TT Port 6 Aggressor Port 7 Port 8 Two Coupled Differential Interfaces crosstalk between one aggres sor structure and one victim structure now would be treated as an eight port measurement as shown in Figure 8 b When measuring with a two port VNA the condition of m lt n exists with even the minimum differential structure 2 lt 4 Currently four port VNAs m 4 to microwave frequencies are commonly available and this provides for Figure 8 Example of port numbering for a one differential interface and b two coupled differential interfaces rD p D 4 port DUT DP r vm gt GL Port 1 Port 2 i Measurement 1 i l I MME pP h I OO amp Pe gt Ee Bb gt Ee P D gt E EE fie be Oe een r a aa a ea a ee I re Ga G Measurement 6 i i I I I gt Ee P Figure 9 Example of two port measurements needed to characterize a four port device This illustrates the consistent application of terminations T1 4 to each port IEEE microwave magazine the condition m n 4 4 for 0 the minimum differential structure However it is clear that when considering cross talk between two or three cou pled differential pairs n 8 and n 12 respectively the condition of m lt n exists In principal this isn t a new challenge In 7 Tippet and Speciale describe a procedure for measuring n port devices with m port instruments where m lt n T
14. B surface with microwave probes Coaxial launchers are best suited to nonplanar 3 D structures as shown in Figure 4 where probing on surfaces with more than one plane is difficult though not impossible with proper probe station fixturing Coaxial launches have the added advan tage that the test ports for high I O count devices can be physically spread out to ease the mechanical design of the test fixture at the expense of test board size These coaxial launches need to be well designed and repeatable to provide a low reflection high frequency transition if accurate 2020 calibration and measurement results are expected The use of microwave probes for the PCB test inter face presents both an opportunity and a challenge The opportunity lies in the fact that the probe launch inter face will typically have an improved high frequency transition to the board compared with coaxial launch es Thus with a more electrically transparent test port transition as well as a more repeatable connection probing will generally provide improved calibration June 2008 and measurement accuracy The challenge is that for multiport devices it is nearly impossible to fixture a probe station to mechanically place all the probes required if the traditional single port probes are used One solution is to use multi port probes on the same probe head as shown in Figure 5 This method allows multiple ports to be tested simultane ously if the probe
15. Brett Grossman are with Intel Corp Andrea Ferrero and Valeria Teppati are with Politecnico Di Torino Jon Martens is with Anritsu Corp Digital Object Identifier 10 1109 MMM 2008 919919 1527 3342 08 25 00 2008 IEEE June 2008 BARRAEETDOLUGOLUG SAARARAESIEEOOUTE LLLLLLLLLLLLLLI COLLLLLLLLLLLLLLI AMTETETTTTTTTLLLI l rt DHREERREERROREEE TTT Tih i tk el i a a G G ed dt ALLLLLELLLLLLLLI TEITEI ALLLLLLLLLLI EOORCUCUCCCUCCOUU TTT LLL MITTIN TT JOHN FOX amp DIGITAL VISION this the digital engineer again reaches into the microwave engineer s toolbox and this time pulls out the vector net work analyzer VNA Though the typical microwave engineer s VNA with only two ports doesn t lend itself to easily characterizing the groups of parallel signal chan nels the digital engineer faces it can do so by making it a multi 40 000 port instrument 35 000 This article presents some of 30 000 the most recent multiport VNA 25 000 measurement methodologies N used to characterize these high 20 000 speed digital networks for sig 15 000 nal integrity There will be a 10 000 discussion of the trends and 5 000 measurement challenges of high speed digital systems fol 2005 2007 lowed by a presentation of the measurement techniques as well as some examples of interconnect device measurements The intent here is to present some general concepts a
16. al socket mounting site is shown at the lower right section of the board with the test line de embedding structures placed in the upper center region All of the various calibration and verification structures are placed in the upper left and upper right regions The measurement port assignment and config uration is shown in Figure 26 Figure 27 displays the postprocessed differential S parameter data of the socket It should be noted that this data has all the board and package test lines de embedded so that this is only the response of the sock et plus the solder balls pads and 1 mm microstrip line length on the bottom of the socket as well as the pack age LGA pad a short 0 79mm package via and 1 mm microstrip line length at the top of the socket This illus trates the differential response for this socket including differential insertion and return loss near end crosstalk NEXT and far end crosstalk FEXT for three contact pairs in the grid array Within this three pair configura tion one of the pairs is the victim quiet signal channel where the unwanted noise is imposed by neighboring signal channels and the two remaining contact pairs aggressor channels placed adjacent to the victim channel impart the unwanted or crosstalk noise If we look at this data from the perspective of a microwave designer it might be surprising that this response looks relatively clean that is free from many resonances and discontinuit
17. e TRL calibration elements test line de embedding structures and an SMT mounted socket to be characterized Using the 12 port VNA the differential response of the socket can be obtained through the single ended measurements and postpro cessing of the data using the integrated capabilities in the test software This will give the differential response of one victim line and the crosstalk from two adjacent ageressor lines from this 12 port measurement The layout of the test board in Figure 25 shows the land erid array LGA socket soldered to the board in the lower left side with a test package and retention clamping Figure 25 CPU socket multiport test board with socket and test package dB dB AI lg A AUT E ta ea WMT Pe a a E L E Cl ttt tt 4 8 12 16 20 Frequency GHz c dB Figure 26 Port assignment for 12 port measurements of the CPU socket Dsi Ee Ds22 IN I DS33 AAN ik 0 4 8 12 16 20 b aks d aea E am Ary hy a E TT i Ye la 0 4 8 12 Frequency GHz d a lorz annnm y CEEREEEAA Figure 27 Typical socket differential de embedded multiport data a Differential insertion loss b differential return loss c differential NEXT and d differential FEXT IEEE microwave magazine June 2008 structure to compress the package into the socket to pro vide the LGA socket contacts and the test package pads An addition
18. ecture selected one may then On the highest level having one source and receiver consider some of the implementation details Many ade per port is probably impractical at these higher fre quate couplers exist for this application and so what quencies per the configuration in Figure 13 a The per about the switches Mechanical switches were ruled out formance level of a switch matrix in front of a two port or M port M N VNA will likely be unac ceptable for stability reasons This tends to argue for a coupler or coupler set per port as in the con figuration of Figure 13 c as a more practical approach Much could be said about hav ing a test and reference coupler per port versus having only a test cou pler per port in which case the reference coupler back in the two port VNA would be used From the point of view of calibration simplicity the former is preferable As discussed later in this article however approaches have been found to allow all known calibra tion methods and combinations thereof to be used when there is limited reference coupler cover age In this particular measure ment scenario it was desired to source lock the receiver and have a tighter control of reference signal levels Since the calibrations would not be hampered system sweep control would be simpli fied and costs could be reduced this led to a decision to use only one test coupler per port The above analysis leads to a struc
19. embedding is the following SGB FB SLB KB SHAm MAm 0 1 where S is the DUT or standard scattering matrix H K L M F G are diagonal n x n matrices containing error coefficients and m Bin By are matrices contain ing the measured incident and reflected waves see 16 for details Now we will briefly revisit the dynamic calibration concept originally introduced only for a complete reflectometer VNA and recent ly extended to partial reflec More information can be found in 13 and 17 The dynamic cal ibration technique was origi nally developed on a graph theory based algorithm which computes the standard sequence with the following assumptions e Only a set of available one and two port stan tometer architectures Source or dynamically Termination June 2008 a dards is required and thus no multiport standards are needed to accomplish the calibration e The user can define the connectivity properties among the different VNA ports i e the user spec ifies which ports can be connected with fully defined two port standards as thrus or partially defined standards e g reciprocal devices e The user may also integrate one or more two port traditional calibrations on specific port pairs to increase the accuracy The dynamic calibration is particularly useful for measurements in the digital world In this scope it is common to have mixed environments such as on
20. ement 1 I I I I I I I I I I I Measurement 2 I I I I I I l l l l l l l l Measurement 3 i i i l l l l l l Figure 11 Example of three of the two port measurements necessary to fully characterize the four port illustrating the application of a unique termination T1 6 to each unmea sured port and the need for a unique DUT and fixturing for each measurement IEEE microwave magazine 61 S44 Shon 1 Measurement 1 921 922 Measurement 2 aa E T riaa Measurement 4 1an a Measurement 5 raa 1 S421 S44 eis Measurement 6 1a S43 S44 Io F0 r 1 l 2 Figure 12 Each of the six two port measurements produces a 2 x 2 submatrix of the final 4 x 4 matrix which is a function of the terminations applied T112 Table 1 is a worst case illustration for the cases where m lt n and assumes no device symmetry However what should also be clear from Table 1 is that in the cases where m n the assumptions of symmetry and repeatability are no longer necessary Significant benefits in terms of measurement time postprocessing time and fixture design complexity also result from requiring only a single measurement per DUT Though there are multiple ways to implement these multiport VNAs some choices create opportunities for additional efficiencies Several of these choices will be discussed in the following sections in the context of developing and utilizing a 12 port 65 GHz VNA M
21. ge and J Bigelow Multi port vector network analyzer measurements IEEE Microwave Mag vol 6 no 4 pp 72 81 Dec 2005 15 H Heuermann GSOLT The calibration procedure for all multi port vector network analyzers in 2003 IEEE MTT S Int Microwave Symp Dig vol 3 June 2003 pp 1815 1818 16 A Ferrero V Teppati M Garelli and A Neri A novel calibra tion algorithm for a special class of multi port vector network analyzers in IEEE Trans Microwave Theory Tech vol MTT 56 no 3 pp 693 699 Mar 2007 17 MMS NT help and user manual Online Available www pafmicro com AR IEEE microwave magazine 69
22. heir procedure requires first having unique known termina tions T1 n for each port Next multiple m port mea surements are made until all combinations of n ports taken m at a time have been completed An example of this procedure where m 2 and n 4 is shown in Figure 9 and described in the following For the case where m 2 and n 4 n n 1 2 6 measurements are required to characterize the n port device Each of these six measurements produces a 2 x 2 S parameter matrix which is a function of the ter minations applied to the unmeasured ports Once com pleted all of these measurements must then be com bined to produce the 4 x 4 S parameter matrix of the DUT Su Sp S13 S14 S21 522 S23 S24 DUT 531 532 533 534 S41 S42 543 Sag S parameter matrix of a four port DUT The submatrix collected from each measurement is illustrated in Figure 10 From Figure 10 it is clear that the six measure ments allow each of the off diagonal S parameters to be measured precisely one time However in achiev ing this the on diagonal S parameters are each mea sured three times If the terminations I are not identical then the repeated measurements of the on diagonal S parameters will not be identical June 2008 Measurement 1 Measurement 4 I S11 I S43 I Soa t a seesuemens lt ieee 1 S32 S33 1 S341 S33 4 I ot ler Fj E 8 8 ot ee i S44 i S14 I I Measurement 6 ee Su Smo
23. ies through 8 10 GHz Given the physical structure of these sockets with many densely packed contacts in a grid array and the contact design driven more by the mechanical requirements rather than an optimized electrical impedance transition the expectation might be that we would not see useable performance anywhere in the microwave frequency range Additionally this data points out that due to these measurement capabilities it is possible to design and model digital interface connections for optimized high frequency performance and validate these designs and models with accurate real world measurements Conclusions We have seen that characterizing digital interconnect devices and structures in the high speed microwave arena presents a variety of difficult challenges The large number of signal lines with high density placed on a less than ideal circuit board media requires care ful thought and design of the test structures measure ment and calibration methodology and test equip ment in order to accurately measure these interconnect devices and systems The physical configuration of these board level structures running the range from planar to 3 D drives the test interface to more complex forms to insure proper testability Application of a well known microwave tool the VNA to these test ing challenges leads us to expanding the VNA to mul June 2008 tiple ports and rethinking the approach to calibration and testing so that
24. it becomes practical to extract the single ended and differential S parameter perfor mance data from these structures This article has shown that a 12 port VNA designed with these mea surement challenges in mind coupled with test soft ware that incorporates new methodologies to enable multiple signal line devices to be tested accurately and efficiently and a test interface that is tailored to the spe cific configuration of the digital interconnect device will result in useful accurate measurement data to val idate designs and models of digital interconnects References 1 ITRS International technology roadmap for semiconductors reports 2006 update 2006 Online Available http www itrs net Links 2006Update 2006UpdateFinal htm 2 M Resso Building bridges between digital and microwave tech nologies in 70th ARFTG Signal Integrity Workshop Dig Dec 2007 pp 1 22 3 H Johnson and M Graham High Speed Digital Design Englewood Cliffs NJ Prentice Hall 1993 pp 319 321 4 B Grossman T Ruttan and E Fledell Architectural considera tions for multiport vector network analyzers in Proc IEC DesignCon 2007 Feb 2007 Track 13 Paper 13 WA2 5 B Grossman and T Ruttan Why multi port VNA s in 70th ARFTG Conf Signal Integrity Workshop Dig Dec 2007 pp 120 139 6 B Grossman T Ruttan and E Fledell Comparison of multiport VNA architectures Measured results in Proc
25. ities that a multi port VNA must support in order to make these types of multiport measurements feasible on a regular basis During the VNA calibration process it is possible for several deterministic variances to occur which can affect the quality of the calibration Several well known examples of these are cable movement temper ature drift and probe or connector repeatability Typically if something does occur that causes a cali bration to be unacceptable an attempt is made to iden tify and address the problem and then the entire cali bration is repeated In a one or two port calibration the penalty in terms of time for repeating the entire calibration may be acceptable However as was illus trated in 6 the penalty with increasing port counts can grow dramatically up to 2 5 h for a 12 port calibration depending on the a calibration approach chosen Furthermore simply repeating the calibration doesn t ensure that new errors are not introduced Again in a one or two port calibration it can be a challenge to ensure repeatable con ditions for the standard measure ments on each port whether probed or coaxial standards As the number of ports increases so too does the number of standard connections Consider that for a typical two port short open load thru SOLT calibra tion the number of repeatable port connections required is eight whereas for a reasonably equivalent 12 port SOLT calibration this number
26. ity and isolation IEEE microwave magazine 63 primarily for repeatability match stability and speed While a variety of solid state solutions are possible some current diodes comprised of a P layer an insulat ing layer and an N layer PIN offered relatively good insertion loss per unit isolation The PIN diode based SPDT switches used here have a maximum insertion loss of about 7 dB to 65 GHz with an isolation of at least 110 dB to 65 GHz This performance and the layer struc ture opens up the use of SP3T switches with modest insertion loss 3 dB at 65 GHz and gt 50 dB of isolation on the upper level A 12 port system uses a layer of four SP3T switches two for source side and two for receive side to form this remaining switch fabric section This resulting system had reasonable raw directivi ties 10 dB or better to 65 GHz when configured in a wafer probing environment and stability as indicated by the line measurement in Figure 15 taken 42 h after calibration The insertion loss drift observed is believed to be due to the cabling and temperature changes Calibration and Measurement Options for Multiport Measurements We will now describe a general calibration approach for multiport systems which has been applied and proved 12 TRANS gt 0 000 dB LOG MAG 0 200 dB DIU S11 REFL gt 0 000 dB Cee ee deena pence eee genera acane rece lacaregacaas ee ee ee Ce Bol nanrasaanrnahaaaanaa
27. nd trends for multiport VNA measurements as applied to computer system board level interconnect structures and not to promote any particular brand or product Key Trends in High Speed Digital Systems In order to meet the challenges of the marketplace outlined above the drivers for digital systems include achieving higher speeds increasing the den sity of the signal channels and moving to differential lines for the data bus All three of these are primarily fulfilling the same objective to increase the total sys tem data bandwidth Figure 1 shows the industry s projected trends for maximum on chip CPU operating frequency It is very likely that all of the potential opportunity represented by this increasing chip performance will not be realized unless the system interconnect speeds also increase Figure 2 illustrates how industry associations are proposing this will be implemented To meet this trend and support transmission data rates into the tens of Gb s per channel will require min imal loss reflection and crosstalk well into the microwave frequency range of 5 20 GHz Signal density is increasing because of two factors more signals and closer placement In order to achieve the desired overall system bandwidths while keeping some control over the frequency of the signals the number of signals in the typical system is growing Figure 3 illustrates this with the trend to higher pack age pin count While this metric includes
28. nrasdaaanrnaaaaadannaafaannnNanruan ternan saaaahnanadaannalaaaartanaadaaarriaasaaanaaadaannnfaaaan A LE N VA A E E A E EE EALER EAN BIAS TN IE I E AECA TA AE SOOO A a E E a A ONC 0 040000000 GHz 65 000000000 S21 TRANS LOG MAG S22 REFL 0 000 dB 0 200 dB DIU 0 000 dB ee vee ce acer p acca ee renege case ana ae ee ee ee ee ee ee S ea ek Se eT Be Ae eRe er Sa eee aye tac hy Aer abe i ee Oe ee ee i oe ee ee ee ee ee ee i i a n Safar a fe S E a A Th oie ene ec ale hie gs ae ai 0 040000000 GHz cee m ape cease ene f asc eahecwenesenatesanrenssccosensgenens su rw ata een aw aceuas nada Rbdqcomnadadh aon Anodaotoonnrnooer Doaa ono Ge sade nonono nonn daca sbocnadeacsekassospocese wee eee eb e wanes svonemoosuRuccooF ee Perec Hry Rr at hehe Tat vy MC Ct ee eanaenanee Poemene effective for the 12 port system just presented In the following discussion we will call the combination of the test and reference coupler a reflectometer or complete reflectometer If the reference coupler is not present the reflectometer will be called a partial reflectometer In the past multiport VNA calibrations have been mainly developed for the complete reflectometer archi tecture see an example for four ports in Figure 16 a 12 14 The well established calibration techniques involve the use of either fixed standard sequences or automated electronic calibration devices For the partial reflectometer
29. nternet use in our everyday lives along with complementary metal oxide semiconductor CMOS technology keeping pace with Moore s law have resulted in today s PC system having clock fre quencies well into the GHz range and channel data rates measured in Gb s Keeping pace with these frequencies in the typical digital system presents significant design challenges Preserving the signal integrity of a single broadband signal through the packages sockets connectors and PC board PCB traces typically found in today s com puter systems the system designer now borrows many Multiport VNA Mee AM note tools from the microwave designer However to achieve the overall bandwidth required the system architecture consists of tens to hundreds of parallel channels operat ing at these high data rates This is not the typical chal lenge of the microwave designer Power integrity where the dc power is delivered cleanly to the CPU and other semiconductor devices is also an important topic for the digital designer Power integrity can have a significant impact on signal integrity due to ground bounce bias ringing and other effects but we will save that discussion for another time A key element in the design process of these systems whether it is to validate simulation models or to verify performance is the ability to measure the performance of these systems at the operating frequency of interest For Thomas G Ruttan and
30. our in this example Figure 24 illustrates the result of per forming only these four measurements and updating the existing calibration This type of capability may be a convenience with one or two port measurements But it is essential for measurements with increasing port quantities and it is just one example of a needed capability beyond the fun damental VNA hardware and calibration algorithms Now that we have seen an example of a calibration process and its data we will discuss an example of the multiport characterization of a digital interconnect device placed on a test structure shown in Figure 25 This is a characterization test board for a CPU socket using on board calibration elements and de embedding structures with 12 port microwave probes for the test interface with the 12 port VNA CPU sockets are used in many computers to provide a removable connection between the CPU package and the system mother board so this is a good example of a digital 0 Insertion Loss E 2 eel red 4 ee i 8 eal a A a a Z Lie ES ia iS a i a ee 10 LUER E a ee E 0 4 8 12 16 20 Frequency GHz Figure 23 Microstrip measurement after initial TRL cali bration Frequency GHz Figure 24 Microstrip measurement after updated TRL calibration IEEE microwave magazine 68 interconnect device that requires multiport high frequency characterization The test board contains on board 12 port multilin
31. test patterns on the board are designed to match the probe head pattern as shown in Figure 6 The issue of VNA calibra tion for testing these board test structures must be carefully considered While it is possi ble for both the coaxial launch and probing cases to perform a calibration at the VNA test ports and 1 include the test interface launch per Conceptually it is useful to consider the structure of Figure 7 b as a single four port device n 4 If it were necessary to utilize a two port VNA to characterize this device m 2 the condition of m lt n is realized If two a b formance as part of the device Figure 5 Multiport ground signal ground GSG probe tips on the same probe head under test DUT or 2 perform a separate de embedding of the launches it has been determined in previous work 4 6 that performing an on board calibration places the reference plane on board and thus provides accurate results Applying Microwave Measurement Techniques to the Problem Multiport VNAs VNAs having two ports are readily available in many microwave labs and more recently 4 8 and even 12 port VNAs have become commercially available These instruments with increased port quantities are utilized to characterize the many parallel channels of interconnect in digital systems but why not simply utilize traditional two port instruments The topic considered first is the condition of mea suring n port de
32. ture like that in Figure 13 c Due to the need to be close to the DUT in a wafer probing environ ment compartmentalizing the test couplers makes some sense so they can be positioned around the prob ing platform The first layer of switches nearest the DUT is where the bulk of the isolation is needed since that is where neigh bor to neighbor potential coupling is unavoidable From the perfor mance advantages of SPDT switch es it then follows that the ports may want to be separated into pairs This leads to the architecture shown in Figure 14 which also has the advantage of having the load June 2008 To VNA Port 1 To VNA Port 2 Switch Fabric Port 1 Port N a b To VNA Port 1 To VNA Port 2 To VNA Receivers y Source Switch Fabric Receiver 4 Switch Fabric Port 1 Port N c Figure 13 Some possible extremes of architectures for a multiport VNA system using a a source and receiver per port b only a two port VNA as a base and relying entirely on a switch fabric to connect to N ports or c a combination using indepen dent test couplers but a base two port VNA plus switch fabric to provide test signals To VNA Ports and Receivers Remaining Switch Fabric One 2 Port Module SPDT im SPDT Figure 14 A somewhat more optimal N port architecture for wafer and board probing applications at high frequencies is shown here Test ports are compartmentalized into pairs to improve stabil
33. ultiport VNA Architectural Choices In considering the architecture of an n port VNA we will focus on the macro questions of how the sources receivers and couplers should be configured Somehow associated with every port must be a path to a source to a reference and test coupler and to a reference and test Table 1 DUT variations and terminations versus instrument ports No of DUT No of Instrument No of DUT Total No of Ports Ports Variations Terminations 2 2 1 O 4 2 6 12 8 2 28 168 Z 2 66 660 4 4 1 O 4 6 24 12 4 15 120 8 8 1 O 12 8 5 12 l2 12 1 O Shaded rows highlight cases where the number of DUT ports and instrument ports are equal m n IEEE microwave magazine receiver The basic questions that must be answered from this viewpoint include e How many sources If less than one per port how are they switched to the ports e How many couplers and where should they be e How many receivers If less than two per port how are they switched to the couplers Several possible configurations are shown in Figure 13 In some cases additions are made to a two port VNA Figure 13 b and c while in another the construction is integral Figure 13 a To more clearly delineate why certain choices may be made it might help to look more carefully at the constraints 1 Because of the frequencies involved extra sources and receivers will be very expensive Extra couplers will be much less so 2 Cable
34. vices with m port instruments when m lt n Frequently in high speed digital inter connects this condition has presented itself when it is has been necessary to characterize coupling crosstalk in adjacent structures Considering the crosstalk between two single ended structures is an illus trative example In a single ended interface each interconnect structure is generally treated as a two port device Figure 7 a As such characterizing the crosstalk between one aggressor struc ture and one victim structure involves measurements e Figure 6 Multiport probing pattern on a test board Poti Port 2 Single Ended Interface a Port A Port 2 Port 3 Port 4 Two Single Ended Interfaces b Single Ended Interface tween two two port devices as Figure 7 Example of port numbering for a one single ended interface and shown in Figure 7 b b two coupled single ended interfaces June 2008 IEEE microwave magazine 59 60 ageressors and a single victim i e three coupled struc tures were of interest it then follows that the number of device ports n 6 is still gt m 2 and so on If this discussion were expanded to include differen tial interfaces then the simplest interface becomes a four port structure Figure 8 a Similarly measuring Differential Interface Port 1 S Port 2 Port 3 S Port 4 Single Differential Interface a Port 1 x Port 2 Victim Port 3 Port 4 Port
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