NAI 64RS3 VME 18 Channel serial communications
Contents
1. o o o Jo JOJO JO Jo MANCHESTER DATA ENCODING North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3_A001_Rev_3 1 Page 12 of 29 North Atlantic Industries Excellence in ALL we do Baud Rate Baud Rate High Low Address 092 090h 096 094h 09A 098h 09E 09Ch 0A2 0A0h 0A6 0A4h Chan 1 6 Type 24 bit unsigned integer Range 300 to 4Mbps Baud Rate High amp Low Registers combined Read Write R W Initialized Value 9600 Baud Both the Baud Rate High Register and Baud Rate Low Register combined together determine the communications baud rate Enter desired baud rate directly as 24 bit unsigned integer Use external clock to transmit data as low as necessary ex 2 2 BAUD RATE HIGH REGISTER BAUD RATE LOW R2. FLOW CONTROL XON XOFF CHAR AS DATA ol lolololololololololololololo 0 STRIPPED 4 KEPT 1lololo olololololololojolololo 1 TIME OUT DETECTION North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 9 of 29 North Atlantic Industries Excellence in ALL we do Tx Rx Configuration High Address 056h 05Ah 062h 066h 06Ah Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value 0 This register is used to configure CRC function and OPEN and IDLE flags In HDLC mode error protection is done by CRC generation and checking The frame sequence at the end of each frame consisted of two or four bytes of CRC checksum 32 bit or CCITT algorithms can be selected REGISTER 015 014 013 012 11 10 D9 07 06 D5 D4 D3 D2 D1 FUNCTION CRC RESET VALUE HDLC ONLY Tx Rx CONFIG HI 0 0 0 1 1 0000 00000000 0 CRC SELECT HDLC 1 32BIT CRC 0 16B
3. XOFF Character Address 108h 10Ah 10Ch 10Eh 110h 112h Chan 1 6 Type unsigned character usually a member of the ASCII data set Range not applicable Read Write R W Initialized Value 13h Modes Affected Async This register bit field specifies the XOFF character for in band flow control in Async mode REGISTER D15 D14 D13 D12 D11 D10 D7 05 D4 D3 D2 FUNCTION XOFF CHAR D DATA BIT FIFO Status Address 114h 116h 118h 11Ah 11Ch 11Eh Chan 1 6 Type binary word Range not applicable Read Write R Initialized Value not applicable This register describes current FIFO Status See Rx Almost Full Tx Almost Empty Rx High Watermark and Rx Low Watermark specific registers for function description and programming REGISTER D15 D14 D13 D12 D11 D10 09 08 07 06 05 D4 D3 D2 D1 DO FUNCTION FIFO STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 04 1 RxFIFO ALMOST FULL TxFIFO ALMOST EMPTY 010 1010 0 10 10 0 0 010 10 0111 010 HIGH WATERMARK REACHED LOW WATERMARK REACHED Rx EMPTY 0 0 0 0
4. J1 AMP 748483 5 Mate AMP 748368 1 Pin Pin Pin Pin Pin Pin Pin 1 Chassis 1318 0 03 25 DCD 06 37 RTS 01 49 04 61 06 73 CLK 02 2 CTS 06 14 CTS 02 26 TXD 05 38 TXD 01 50 03 62 TXD 06 74 Ground 3 RXD 06 15 RTS 02 27 RTS 04 39 RXD 01 51 5 03 63 CLK 05 75 RXD 02 4 5 05 16 DCD 02 28 TXD 04 40 Chassis 52 03 64 DCD 06 76 DCD 01 5 05 17 TXD 02 29 RXD 04 41 RTS 06 53 TXD 03 65 RXD 05 77 5 01 6 DCD 05 18 5 01 30 Ground 42 CLK 06 54 02 66 DCD 04 78 01 T TXD 05 19 TXD 01 31 CTS 03 43 TXD 06 55 02 67 CTS 04 8 RTS 04 20 RXD 01 32 RXD 03 44 CLK 05 56 RXD 02 68 04 9ITXD 04 21 5 06 33 CTS 02 45 DCD 05 57 DCD 01 69 Ground 10 RXD 04 22 RXD 06 34 RTS 02 46 RXD 05 58 CTS 01 70 RTS 03 11 DCD 03 23 CTS 05 35 Ground 47 DCD 04 59 01 71 03 12 5 03 24 5 05 36 TXD 02 48 CTS 04 60 RTS 06 72 TXD 03 J2 AMP 748483 5 Mate AMP 748368 1 Pin Pin Pin Pin Pin Pin Pin 1 Chassis 13 09 25 12 37 RTS 07 49 CLK 10 61 12 73 08 2 CTS 12 14 5 08 26 TXD 11 38 TXD 07 50 09 62 TXD 12 74 Ground 3IRXD 12 15 RTS 08 27 RTS 10 39 07 51 RTS 09 63 11 75 RXD 08 4 CTS 11 16 DCD 08 28 TXD 10 40 Chassis 52 CLK 09 64 DCD 12 76 DCD 07 5 RTS 11 17 TXD 08 29 RXD 10 41 RT
5. The memory map of the 6 channel Serial Communications module is described hereafter North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 4 of 29 North Atlantic Industries Excellence in ALL we do MODULE MEMORY MAP 6 CHANNEL SERIAL COMMUNICATIONS P3 000 Tx Buffer Chan 1 W 07C Channel Control Low Chan 5 R W OFO Termination Character Chan 1 R W 002 Tx Buffer Chan 2 W 7 Channel Control High Chan 5 R W OF2 Termination Character Chan 2 R W 004 Tx Buffer Chan 3 W 080 Channel Control Low Chan 6 R W OF4 Termination Character Chan 3 R W 006 Tx Buffer Chan 4 W 082 Channel Control High Chan 6 R W OF6 Termination Character Chan 4 R W 008 Tx Buffer Chan 5 W 084 Data Configuration Chan 1 R W OF8 Termination Character Chan 5 R W 00A Tx Buffer Chan 6 W 086 Data Configuration Chan 2 R W OFA Termination Character Chan 6 R W 00C Rx Buffer Chan 1 R 088 Data Configuration Chan 3 R W OFC XON Character Chan 1 R W 00 Rx Buffer Chan 2 R 08A Data Configuration Chan 4 R W OFE XON Character Chan 2 R W 010 Rx Buffer Chan 3 R 08C Data Configuration
6. _ Model 646853 Eighteen 18 Synchronous Asynchronous Excellence in ALL we do RS 232C RS 422 RS 485 Channels VMEbus CONTROL SERIAL COMMUNICATION CARD EIGHTEEN INDEPENDENT amp PROGRAMMABLE RS 232C RS 422 RS 485 SYNCHRONOUS or ASYNCHRONOUS For Commercial or Military Applications FEATURES e Independent full duplex synchronous or asynchronous channels e High Data Rate 4 Mbps synchronous 800 Kbps asynchronous Programmable for RS 232C RS 422 RS 485 Hardware data transfers minimize data latency Power on loop back self test Watchdog timer and soft reset via front panel P2 or both Part Number S N Date Code amp Revision in non volatile memory Conforms to ANSI VITA 1 1 1997 VME64 extension e Conforms to VITA 1 1994 Typical Configuration e VxWorks Library and Driver Available Typical Configuration DESCRIPTION This sophisticated high speed DSP based card incorporates eighteen 18 intelligent full duplex communications channels that can be individually software programmable for protocol and data configurations Interface level selection RS 232C RS 422 or RS 485 is programmable in banks of three The architecture avoids latency problems because all data transfer is done in hardware and not in software DSP runs at 160 MHz and only handles background tasks such as interrupt generation Any incoming data no matter how many channels are active in whatever
7. 4 a Jg e N FUNCTION CONTROL LO RTS GPIO 11 CTS GPIO 21 NOT APPLICABLE NOT APPLICABLE DCD GPIO 51 Tx INITIATE2 Tx ALWAYS ASYNC ONLY RESERVED TRISTATE TRANSMIT LINE ENABLE RECEIVER SET RELEASE BREAK ENTER HUNT MODE TIMEOUT ENABLE RESET CHANNEL FIFOs amp UART2 O O O O O JO o o O O O JO O JO JO o O O JO JOJO O JO o O O O O O O O o CLEAR Rx FIFO2 O O O O o o o 1 0 O O O 2 O O O o o o O O O O O o o O O O O 2 JO o o O O O O O O 2 O O JO o o o O O O O O o 2 o o O O O O O O o 2 o o o 0 0 O O O O O O o o 2 o o o o O O O O O O o o o o 2 o o O O O O o o o o o o O O O O O o o o o 2 o O O O O O o o o o CLEAR Tx FIFO2 Notes 1 Disable DO through D4 to enter GPIO control RTS CTS as GPIO when RTS CTS Flow
8. O O O O o o o 2 o o O O O O O o o o o o o O O O O O o o o o o o O O O O O O o o o o o 2 N A North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3_A001_Rev_3 1 Page 17 of 29 North Atlantic Industries Excellence in ALL we do Interrupt Vector Address 198h 19Ah 19Ch 19Eh 1A2h Chan 1 6 Type unsigned character Range not applicable Read Write R W Initialized Value not applicable This register contains the interrupt vector or address to the interrupt service routine REGISTER 015 014 013 012 011 010 09 07 D6 05 D3 D2 D1 FUNCTION INTERRUPT VECTOR D DATA BIT Channel Status Address 1A4h 1A6h 1A8h 1Aah 1Ach 1Aeh Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value not applicable This register describes the status of 13 different events These events are NOT latched They are dynamic Use this register to read current or real time status See specific registers for function description and programming REGISTER 15 014 013 012 11 0
9. 04 12d CLK 05 19d CLK 07 234 5 09 304 11 1a lRXD 01 25z CLK 02 27a RTS 04 6c RXD 06 18c DCD 07 22c CTS 09 3d RTS 11 2a RXD 01 27z CLK 02 28a RTS 04 06 18d DCD 07 22d CTS 09 4d RTS 11 5 01 1d DCD 02 5c CLK 04 9c RTS 06 15c TXD 08 25c CLK 09 9z CTS 11 4a RTS 01 2d DCD 02 5 04 9d RTS 06 15d TXD 08 25d CLK 09 11z CTS 11 21z CLK 01 15a RXD 03 3c DCD 04 8c CTS 06 16c RXD 08 31c TXD 10 1z RXD 12 23z CLK 01 03 4c DCD 04 8d CTS 06 16d RXD 08 31z TXD 10 3zIRXD 12 11a DCD 01 21 5 03 2 05 11c CLK 06 21c RTS 08 28c RXD 10 132 5 12 12a DCD 01 22 5 03 30a TXD 05 11d CLK 06 21d RTS 08 28d RXD 10 15z RTS 12 5a TXD 02 17 5 03 1c RXD 05 17c TXD 07 24c CTS 08 272 15 10 5z CTS 12 6a TXD 02 18a CTS 03 2c RXD 05 17d TXD 07 24d CTS 08 27d RTS 10 Tz CTS 12 9a RXD 02 23a CLK 03 Tc RTS 05 14c RXD 07 26c CLK 08 32c DCD 10 17z CLK 12 10a RXD_ 02 24 03 05 14d RXD 07 264 08 29z DCD 10 19z CLK 12 13a RTS 02 31a TXD 04 10c CTS 05 13c RTS 07 20c RXD 09 29c TXD 11 14 5 02 2 04 10d CTS 05 13d RTS 07 20d RXD 09 29d TXD 11 Connector CTS 01 15a DCD 08 13 5 CTS 14 11c RXD 16 10b CTS 17 10e CTS 01 16a DCD 08 7 RXD 13 6 CTS 14 12c RXD 16 11b CTS 17 11e TXD 03 19e TXD 09 8d RTS 13 18b CLK 14
10. Receiver Enable Disable A Receiver Enable Disable function allows the user to turn selected receivers ON OFF When receiver is disabled no data will be placed in the buffer Card is shipped with all receivers enabled CRC code generation and detection is also available for message integrity when used in Synchronous HDLC and Asynchronous PPP modes This serial card can operate in an Interrupt Driven Environment to provide notification of all events to the system It supports hardware flow control CTS RTS as well as software flow control XON XOFF When a flow control mode is selected the serial card does the operation automatically with minimal system intervention North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 1 of 29 North Atlantic ustries Excellence in ALL we do A Parity Error Interrupt is provided for each single byte throughout the communications data stream Multi Drop Link Mode The transmitter and receivers of up to 32 cards can be tied together in either Half or Full Duplex mode While in Multi Drop Link Mode The transmit line for each channel will automatically change from tri state to enable to transmit any data as soon as it is placed in the transmit buffer Once transmission is completed the transmit line is automatically changed back to tri state mode For redundant appl
11. 02 01 FUNCTION Tx Rx CONFIG LO 879 5 FLOW CONTROL 1 FLOW CONTROL 1 AUTO TRANSMIT MODE 0 0 1 0 ENABLED RTS FUNCTION 0 WATERMARK 41 AVAIL CARRIER DETECT FLOW CARRIER DETECT PIN POLARITY 4 ACTIVE LOW 0 ACTIVE HIGH 1 ADDRESS RECOGNITION 1 ADDRESS LENGTH HDLC ONLY l 16 0 8 BITS 1 HIGH BYTE RECOGNITION ADDRESS AS DATA HDLC ONLY 1 0 STRIPPED 1 KEPT SYNC CHAR LENGTH 0 6 12 Bi Sync 4 8 16 Bi Sync SYNC CHAR AS DATA 0 STRIPPED 4 KEPT 1 TERMINATION CHAR 1 1
12. 10 D9 D7 06 D5 D4 D3 D2 D1 DO FUNCTION TEST ENABLE D DATA BIT Module Test Status Address 7E4h 7E6h 7E8h Type binary word Range 0000h to FFFFh Read Write R Initialized Value not applicable This register reports the DO Loopback Test Status for each module channel DO reports status for channel 1 D1 for channel 2 etc Channel Status Data bit Chn where n is 1 2 3 4 5 or 6 is fail high true and indicates channel is not operating spec compliant Status is latched Status is unlatched when read REGISTER 15 014 013 012 011 010 07 06 05 D3 D2 01 DO FUNCTION MODULE TEST STATUS X X X XIX X X X X Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 MODULE CHANNEL STATUS BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 21 of 29 North Atlantic Industries Excellence in ALL we do Watchdog Timer Address 7Eah Type binary word Range not applicable Read Write R Initialized Value Oh This register implements a Watchdog timer When it detects that a value or word has been written to it that word will be inv
13. Front Panel I O and P2 amp PO I O 1 PO Connector installed S Front Panel I O and P2 I O No PO 2 PO Connector not installed P P2 amp I O only G P2 I O only W P With Wedgelocks A VME64 with Blank Front Panel and P2 amp I O only B VME64 Front Panel unshielded with Front Panel P2 amp POI O T VME64 Front Panel unshielded with Front Panel amp P2 I O No D VME64 with Blank Front Panel Low profile extractors and P2 amp POI O only NOTE Unshielded to accommodate for mating 78 pin connector North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 28 of 29 North Atlantic Industries Excellence in ALL we do Revision Page Revision Description of Change Engineer Date 1 Initial Release FH 04 18 02 1 1 Added Modular Memory Map GS 04 23 02 1 2 Added JX amp PX Pin Outs GS 04 29 02 1 3 Added edited Mechanical options A B amp D GS 05 02 02 1 4 Hide Memory Map Map is TBD Used Select Font HIDE Text GS 06 12 02 1 5 Storage from 40 to 55 C FH 07 14 02 Adds new memory map and related descriptions derived from RS2 rev 1 1 Removed all DCD DTR references Updates to 6 not 4 channels per module Rx Tx Buffer 16 is 32k not 64k Interface Levels registe
14. 0 0 0 0j 0 j0 1 0 0 0 0 0 Tx FULL Time Out Value Address 120h 122h 124h 126h 128h 12Ah Chan 1 6 Type unsigned integer Range 0 to 65535 Read Write R W Initialized Value 9C40h 1 second Modes Affected Async This register bit field determines the time out period If there is no receive line activity for the configured period of time a time out is indicated in the Interrupt Status Register bitD10 Lsb is 35us REGISTER 015 014 013 012 011 010 D9 08 07 06 05 D4 D3 D2 D1 DO FUNCTION TIME OUT VALUE D D D D D D D DATA BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 16 of 29 Interrupt Enable North Atlantic Industries Excellence in ALL we do Address 180h 182h 184h 186h 188h 18Ah Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value not applicable This register provides for Interrupt Enabling Set bit high True to enable interrupts Status will still be reported in status registers See specific registers for function description and programmin REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7
15. 03 08 3 1 Modified P3 memory map SB 4 9 09 2009 North Atlantic Industries All rights reserved This document is furnished for the customers of North Atlantic Industries Other uses are unauthorized without written permission of North Atlantic industries Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues The information provided in this Operation Manual is believed to be accurate No responsibility is assumed by North Atlantic Industries for its use and no license or rights are granted by implication or otherwise in connection therewith North Atlantic Industries acknowledges the trademarks of other organizations for their respective products or services mentioned in this document North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 29 of 29
16. 111 1111 1111 xxxx xxxx or 57FFxx h xx is CSR register offset Write to address 57FF63 h the A31 A24 base address bits for example 01h Write to address 57FF67 h the A23 A16 base address bits for example 02h Write to address 57FF6B h the A15 A8 base address bits for example 04h Write to address 57FF6F h the address modifier you wish to respond to shifted up 2 bits ex 28h 0A 2 then write to address 57FFFBh 10h to enable the card The card will now respond to the base address 010204 in the example and address modifier OA in example programmed The base address and address modifier can be changed at any time PRODUCT CONFIGURATION AND MEMORY MAP This card is populated with 3 modules of 6 Serial Communication Channels As such the card can be configured as an 18 channel card The memory map of each module counts from or is superimposed over its respective module offset 1 through 3 Address Base Module Offset Register Offset For example Address Base Module 2 offset 200 MRS2 register 00 20C hex MEMORY MAP 000 Module 1 Register 200 Module 2 Register 400 Module 3 Register 002 202 402 004 204 404 006 206 406 x Module 1 Module 2 Module Offset 000 Offset 200 Offset 400 Channels 1 6 3FC Channels 7 12 Channels 13 18 3FE
17. 13 71 15 12 CTS 15 24 RTS 17 36 TXD 14 48 CTS 16 60 RTS 18 72 TXD 15 North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3 A001 Rev 3 1 Page 26 of 29 North Atlantic Industries Excellence in ALL we do Rear Panel Connectors 2 amp 160 pin DIN connector P2 Connector NOTE DCD Channels 11 12 14 15 17 amp 18 are NOT available on rear connectors PO amp P2 The board contains three green LED s LED1 LED2 4 LED3 that are for factory use only LED2 4 LED3 will be ON during normal operation Miniature test connector JP1 is used to download programming data and JP4 is a ground Do not interface to these two connectors unless factory instructed to be used for field modification North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 Pin Pin Pin Pin Pin Pin Pin Ta TXD 01 19a CTS 02 25a RXD 04 12c CLK 05 19c CLK 07 23c RTS 09 30c RXD 11 8a TXD 01 20 5 02 2
18. 4 R W 18E Interrupt Status Chan 2 R W 054 Tx Rx Configuration Low Chan 1 R W 0C8 Rx Buffer Almost Full Chan 5 R W 190 Interrupt Status Chan 3 R W 056 Tx Rx Configuration High Chan 1 Rx Buffer Almost Full Chan 6 R W 192 Interrupt Status Chan 4 R W 058 Tx Rx Configuration Low Chan 2 R W Rx Buffer High Watermark Chan 1 194 Interrupt Status Chan 5 R W 05A Tx Rx Configuration High Chan 2 R W Rx Buffer High Watermark Chan 2 196 Interrupt Status Chan 6 R W 05 Tx Rx Configuration Low Chan 3 R W ODO Rx Buffer High Watermark Chan 3 198 Interrupt Vector Chan 1 R W Tx Rx Configuration High Chan 3 R W 002 Rx Buffer High Watermark Chan 4 19A Interrupt Vector Chan 2 R W 060 Tx Rx Configuration Low Chan 4 R W 004 Rx Buffer High Watermark Chan 5 R W 19C Interrupt Vector Chan 3 R W 062 Tx Rx Configuration High Chan 4 006 Rx Buffer High Watermark Chan 6 R W 19E Interrupt Vector Chan 4 R W 064 Tx Rx Configuration Low Chan 5 R W 008 Rx Buffer Low Watermark Chan 1 R W 1 0 Interrupt Vector Chan 5 R W 066 Tx Rx Configuration High Chan 5 R W Rx Buffer Low Watermark Chan 2 R W 1A2 Interrupt Vector Chan 6 R W 068 Tx Rx Configuration Low Chan 6 R W ODC Rx Buffer Low Watermark Chan 3 R W 1A4 Channel Status 1 R 06A Tx Rx Configuration High Chan 6 R W ODE Rx Buffer Low Watermark Chan 4 R W 1A6
19. Chan 5 R W 100 XON Character Chan 3 R W 012 Rx Buffer Chan 4 R 08E Data Configuration Chan 6 R W 102 XON Character Chan 4 R W 014 Rx Buffer Chan 5 R 090 Baud Rate Low Chan 1 R W 104 XON Character Chan 5 R W 016 Rx Buffer Chan 6 R 092 Baud Rate High Chan 1 R W 106 XON Character Chan 6 R W 018 Number Of Words Tx Buffer Chan 1 R 094 Baud Rate Low Chan 2 R W 108 XOFF Character Chan 1 R W 01A Number Of Words Tx Buffer Chan 2 R 096 Baud Rate High Chan 2 R W 10A XOFF Character Chan 2 R W 01C Number Of Words Tx Buffer Chan 3 R 098 Baud Rate Low Chan 3 R W 10C XOFF Character Chan 3 R W 01E Number Of Words Tx Buffer Chan 4 R 09A Baud Rate High Chan 3 R W 10E XOFF Character Chan 4 R W 020 Number Of Words Tx Buffer Chan 5 09 Baud Rate Low Chan 4 R W 110 XOFF Character Chan 5 R W 022 Number Of Words Tx Buffer Chan 6 R 09 Baud Rate High Chan 4 R W 112 XOFF Character Chan 6 R W 024 Number Of Words Rx Buffer Chan 1 R 0A0 Baud Rate Low Chan 5 R W 114 FIFO Status Chan 1 R 026 Number Of Words Rx Buffer Chan 2 R 0A2 Baud Rate High Chan 5 R W 116 FIFO Status Chan 2 R 028 Number Of Words Rx Buffer Chan 3 R 0A4 Baud Rate Low Chan 6 R W 118 FIFO Status Chan 3 R 02A Number Of Words Rx Buffer Chan 4 R 0A6 Baud Rate High Chan 6 R W 11A FIFO Status Chan 4 R 02C Number Of Words Rx Buffer Chan 5 R 0A8 Preamble Chan 1 R W 11C FIFO Status Chan
20. Channel Status 2 R 06C Channel Control Low Chan 1 R W 0 0 Rx Buffer Low Watermark Chan 5 R W 1 8 Channel Status R Channel Control High Chan 1 022 Rx Buffer Low Watermark Chan 6 R W 1AA Channel Status 4 R 070 Channel Control Low Chan 2 R W OE4 HDLC Address Sync Char Chan 1 1AC Channel Status 5 R 072 Channel Control High Chan 2 R W OE6 HDLC Address Sync Char Chan 2 1AE Channel Status 6 R 074 Channel Control Low Chan 3 R W 0 8 HDLC Address Sync Char Chan 1F8 Module ID R 076 Channel Control High Chan 3 R W HDLC Address Sync Char Chan 4 1FC FPGA Version R 078 Channel Control Low Chan 4 R W OEC HDLC Address Sync Char Chan 5 R W DSP Version R 07A Channel Control High Chan 4 R W OEE HDLC Address Sync Char Chan 6 R W Serial Communications Module register programming and its associated Bit Map is as follows North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3_A001_Rev_3 1 Page 5 of 29 North Atlantic Industries Excellence in ALL we do MODULE REGISTER DEFINITIONS Transmit Buffer Address 000h 002h 004h 006h 008h 00Ah Chan 1 6 Type unsigned character word Range 00h or FFh low byte Read Write W Initialized Value Not Applicable This register is the trans
21. Control disabled 2 Firmware will clear bit when done North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3 A001 Rev 3 1 Page 11 of 29 Type binary word Range not applicable Read Write R W North Atlantic Industries Excellence in ALL we do Data Configuration Address 084h 086h 088h 08Ah 08Ch Chan 1 6 Initialized Value 0000 0000 0101 0011 binary 53h This register is used for channel data configuration REGISTER D15 D14 D13 D12 D11 D10 D9 A g o a Jg R e N FUNCTION DATA CONFIG 8 DATA BITS 7 DATA BITS 6 DATA BITS 5 DATA BITS NO PARITY SPACE PARITY ODD PARITY EVEN PARITY MARK PARITY 1 STOP BIT 2 STOP BITS NRZ DATA ENCODING NRZI DATA ENCODING DATA ENCODING FM1 DATA ENCODING
22. Rx Buffer Address 024h 026h 028h 02Ah 02CH 02Eh Chan 1 6 Type unsigned integer word Range 0 to 32767 Read Write R Initialized Value 0 This register contains the number of words to be received REGISTER 015 014 013 012 11 09 05 D4 03 D2 DO FUNCTION NUMWORDSRXBUFFER D D DATA BIT Protocol Address 030h 032h 034h 036h 038h Chan 1 6 Type unsigned integer word Range 0 to 5 Read Write W Initialized Value 0 Asynchronous This register is used to configure the associated channel for either asynchronous mono synchronous bi synchronous or HDLC PPP asynchronous Extended Transparent communications mode REGISTER 0151014013 012 011 01009 07 06 05 D4 D3 02 D1 DO FUNCTION PROTOCOL 0 0 ASYNC 5 BI SYNC 0 41 1 HDLC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 PPP ASYNC EXTENDED TRANSPARENT Clock Mode Address
23. mode can be immediately extracted A BREAK sequence capability is also incorporated Bus Data is transferred within 300 ns A layer of software isolates the user from UART idiosyncrasies thus simplifying programming and usage An Internal Loop Back Self Test is performed when power is applied and results are stored in registers During Loop Back test the outputs are disconnected Each channel can be programmed into a Loop Back mode that internally wraps the transmitter around the receiver without the need of external wiring Output short circuit capability is continuous and bullet proof If the card is not powered neither the inputs nor outputs will load down the lines Inputs and outputs can withstand 15 volts under any condition All serial lines are transient protected to IEC1000 4 2 4 4 amp 4 5 Serial Data Transmit Enhancement An additional asynchronous mode to support Immediate Transmit operation has been incorporated This mode immediately transmits serial data anytime the transmit buffer is not empty There is no requirement to set the TX Initiate bit after each byte There is no requirement to set the TX Initiate bit after each byte where VME traffic and overhead can be simplified since only the actual data byte being transmitted needs be sent to the transmit buffer Each channel has its own 64kbyte Transmit and Receive buffer While in Asynchronous mode the upper byte of each received word provides status information for that word
24. time If CTS RTS is disabled CTS amp RTS can be used as ports DCD Data Carrier Detect DCD DTR If enabled operation is automatic Both CTS RTS amp DSR DTR can be enabled at the same time DSR Data Set Ready DTR Data Terminal Ready RS232 is output is not used North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 631 567 1100 631 567 1823 fax 4 9 2009 RS422 is non inverted is inverted and internally terminated with 120c RS485 is non inverted is inverted No internal termination Generally used for multi drop Party lines and terminated at far end Full duplex 4 wire Use RXD amp TXD Half duplex 2 wire Use RXD tied to TXD and RXD tied to TXD RTS Request to Send RXD Receive Data TXD Transmit Data The transmit word is 8 bits Cage Code 0VGU1 64RS3 A001 Rev 3 1 Page 24 of 29 North Atlantic Industries Excellence in ALL we do SERIAL COMMUNICATIONS SPECIFICATIONS Serial Communications Specifications RS232 RS422 RS485 Mode of Operation Single Ended Differential Differential Total Number of Drivers 1 Driver 1 Driver 1 Driver Receivers on One Line 1 Receiver 1 Receiver 32 Receiver Maximum Data Rate 120 kb s 10Mb s 10Mb s Driver Output Signal Level Min Loaded 5V 3kO load 2 0V 1000 load 1 5V 540 load Driver Load Impedance Ohms 3k mi
25. 03Ch 040h 042h 044h 046h Chan 1 6 Type unsigned integer word Range 0 to 3 Read Write W Initialized Value 0 This register configures for internal or external transmit receive clocks User can set D15 to enable internal clock signal on output connector pin annotated CLK xx Applies to internal clock mode only REGISTER 15 014 013 012 011 01009 08 07 06 05 D4 D3 D2 D1 DO FUNCTION CLOCK MODE TX INTERNAL RX INTERNAL TX INTERNAL 4 TX CLKA RX CLKA North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 7 of 29 North Atlantic Industries Excellence in ALL we do Interface Levels Address 048h 04Ah Chan 1 3 Chan 4 6 Type unsigned integer word Range 0 to 4 Read Write W Initialized Value 5 This register is used to configure the interface level RS232 RS422 RS485 Loop Back or Tri State for three associated channels Loop Back selection connects the channel s transmit and receive line internally To implement user must send data and look at Receive FIF
26. 10 D9 D7 D6 05 D3 D2 D1 FUNCTION CHANNEL STATUS PARITY ERROR Rx BUFFER ALMOST FULL CRC ERROR sync amp hdlc only Rx COMPLETE ETX RECEIVED Rx DATA AVAILABLE Rx OVERRUN HIGH WATERMARK REACHED LOW WATERMARK REACHED Tx BUFFER ALMOST EMPTY Tx COMPLETE TIME OUT OCCURRED BREAK ABORT SYNC CHAR DETECTED N A N A N A gt jojo O JO O O O O o o JOJO O O o JO o o o o O O O O O JO o o o O O 2 O O O O JOJO o o o O O O O JO o o o o O O O O JOJO JO JO o o o o O O O O O O JO o o o o O O O O JO 2 JO O o o O O O O O 2 O O JO O o o o O O O O 2 O o o o o O O O O O O 2 o o o O O O JO O JOJO o 2 o o o o O O O O O o o 2 o o O O O O O o o o o o 2 o o O O O O O O o o o o o o O O O O O O o o o o o o Module ID Address 1F8h Type ASCII character in each upper and lower byte Range 0 to 65535 Read Write R Initialized Value 5033h Read register to determi
27. 13c RTS 16 CLK 17 12 TXD 03 1d TXD 09 9 RTS 13 19b CLK 14 14c RTS 16 4a CLK 17 1e DCD 03 17a DCD 09 5a CTS 13 7a TXD 15 9a CTS 16 11a TXD 18 2e DCD 03 18 DCD 09 6a CTS 13 8a TXD 15 10a CTS 16 12a TXD 18 13e CTS 04 2d CTS 10 16b CLK 13 1 15 1 CLK 16 6b RXD 18 14 CTS 04 CTS 10 176 CLK 13 2c RXD 15 2 CLK 16 Tb RXD 18 DCD 05 5e CLK 10 16d DCD 13 7c RTS 15 2b DCD 16 12b RTS 18 4e DCD 05 10 17d DCD 13 8c RTS 15 3b DCD 16 13b RTS 18 15e TXD 06 Te 11 104 TXD 14 3c CTS 15 15 TXD 17 8b CTS 18 1 TXD 06 CLK 11 11d TXD 14 4c CTS 15 16c TXD 17 9b CTS 18 13a DCD 06 4d TXD 12 14d 14 9c CLK 15 19c RXD 17 14b CLK 18 14a DCD 06 TXD 12 15d RXD 14 10c CLK 15 1b RXD 17 15b CLK 18 17e CTS 07 12d TXD 13 18d RTS 14 17 TXD 16 4 RTS 17 18e CTS 07 13d TXD 13 19d RTS 14 18c TXD 16 5b RTS 17 64RS3_A001_Rev_3 1 Page 27 of 29 North Atlantic ustries Excellence in ALL we do PART NUMBER DESIGNATION 64RS3 XX X X X X XX Number of Channels 18 18 channels SPECIAL OPTION CODE OR LEAVE BLANK ENVIRONMENTAL 0 C to 70 C OPTIONS E 40 C to 85 C 0 H E With Removable Conformal Coating 9 custom see separate spec With Removable Conformal Coating MECHANICAL PO CONNECTOR F
28. 4 D3 D2 D1 FUNCTION PLATFORM D D D D D D D Dj D D DATA BIT ASCII 6 ASCII 4 Model Address 7Dah Type ASCII character in each upper and lower byte Range not applicable Read Write R Initialized Value 5253h This register holds product model code RS in ASCII ASCII R is in upper byte and ASCII S is in lower byte REGISTER D15 D14 D13 D12 D11 D10 07 06 05 D4 D3 D2 D1 DO FUNCTION MODEL D DATA BIT ASCII R ASCII S Generation Address 7DCh Type ASCII character in each upper and lower byte Range not applicable Read Write R Initialized Value 2033h This register holds product generation code 3 in ASCII ASCII space is in upper byte and ASCII 3 is in lower byte REGISTER 15 014 013 012 011 010 D7 06 05 D4 D3 D2 D1 DO FUNCTION GENERATION D DATA BIT ASCII ASCII 3 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 20 of 29 North Atlantic Industries Excellence in ALL we do Special Spec Address 7Deh Type ASCII character in each upper and lower byte Range not applicable Read Write R Initialized Va
29. 5 R 02E Number Of Words Rx Buffer Chan 6 R Preamble Chan 2 R W 11E FIFO Status Chan 6 R 030 Protocol Chan 1 Preamble Chan R W 120 Time Out Value Chan 1 R W 032 Protocol Chan 2 W Preamble Chan 4 R W 122 Time Out Value Chan 2 R W 034 Protocol Chan 3 W Preamble Chan 5 R W 124 Time Out Value Chan 3 R W 036 Protocol Chan 4 W 082 Preamble Chan 6 R W 126 Time Out Value Chan 4 R W 038 Protocol Chan 5 W 084 Tx Buffer Almost Empty Chan 1 R W 128 Time Out Value Chan 5 R W Protocol Chan 6 W 086 Tx Buffer Almost Empty Chan 2 R W 12A Time Out Value Chan 6 R W 03 Clock Mode Chan 1 W 088 Tx Buffer Almost Empty Chan 3 R W 180 Interrupt Enable Chan 1 R W Clock Mode Chan 2 W Tx Buffer Almost Empty Chan 4 R W 182 Interrupt Enable Chan 2 R W 040 Clock Mode Chan 3 W Tx Buffer Almost Empty 5 R W 184 Interrupt Enable Chan R W 042 Clock Mode Chan 4 W OBE Tx Buffer Almost Empty 6 R W 186 Interrupt Enable Chan 4 R W 044 Clock Mode Chan 5 W 0CO Rx Buffer Almost Full Chan 1 R W 188 Interrupt Enable Chan 5 R W 046 Clock Mode Chan 6 W 0C2 Rx Buffer Almost Full Chan 2 R W 18A Interrupt Enable Chan 6 R W 048 Interface Levels Chan 1 3 W 0C4 Rx Buffer Almost Full Chan R W 18C Interrupt Status Chan 1 R W 04A Interface Levels Chan 4 6 W 0C6 Rx Buffer Almost Full Chan
30. CII data set Range not applicable Read Write R W Initialized Value 3h Modes Affected Async and Bi Sync This register contains the termination character used for termination detection When using the Asynchronous or Bi Synchronous modes the receive data stream is monitored for the occurrence of the termination character When this character is detected an interrupt unless masked is generated REGISTER 0151014 013 012011 010 09 08 07 06 D5 D4 03 02 D1 FUNCTION TERMINATION CHAR D DATA BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 15 of 29 North Atlantic Industries Excellence in ALL we do XON Character Address OFCh OFeh 100h 102h 104h 106h Chan 1 6 Type unsigned character usually a member of the ASCII data set Range not applicable Read Write R W Initialized Value 11h Modes Affected Async This register bit field specifies the XON character for in band flow control in Async mode REGISTER 015 014 013 012 011 010 07 D6 05 03 02 01 DO FUNCTION XON CHAR D DATA BIT
31. D6 05 D4 D3 D2 g o FUNCTION INTERRUPT ENABLE PARITY ERROR Rx BUFFER ALMOST FULL CRC ERROR sync amp hdlc only Rx COMPLETE ETX RECEIVED Rx DATA AVAILABLE Rx OVERRUN HIGH WATERMARK REACHED LOW WATERMARK REACHED Tx BUFFER ALMOST EMPTY Tx COMPLETE TIME OUT OCCURRED BREAK ABORT SYNC CHAR DETECTED N A N A FB jojo O O JOJO O O O o o o o O O o o o o O O O O O o o o o O O O O O O O o o o o O O O O JO O O O o o o o O O O O O O o o o o O O O O O O O O O o o o o o O O O JOJO O JO O JO o o o o O O O O JOJO O 2 O O o o o o O O O O o o O JO o o o o O O O O O JO 2 o o o O O O o o o o 2 o o o o O O O O o o o o o o 2 o o O O O O o o o o o o o 2 N A Interrupt Status Address 18Ch 18Eh 190h 192h 194h 196h Chan 1 6 Type binary word Range not applic
32. EGISTER D15D14D13 D12 D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 DO D15 D14 D13 D12 D11 D10 D9 D7 06 05 D4 D3 D2 D1 DO XIXI IX X X X X X DIDIDIDIDID 300 Baud 00 012C hex 0 0 4 0 7 1 1 010 9600 Baud 00 2580 hex 0 0 0 1 1 1 1 0 0 0 0 0 0 0 4000000 Baud 0900 hex 0101111 1 1 0 1 0 0 1 1 0 0 0 Bit rate generation is based on a primary clock divided by an integer value Programmed bit versus actual bit rate will have greater resolution at lower bit rates 115 KHz When specifying internal clock the card generates and transmits the actual bit rate as close rounding off to the programmed bit rate based on the following formula Actual bit rates available 25 2 synchronous 1 5625 MHz N asynchronous N 7 integer Asynchronous examples Programmed Bit Rate b s Integer Divisor Actual Bit Rate 381 minimum 4096 381 5 600 2604 600 2400 651 2400 9600 163 9586 57600 27 57870 115200 14 111607 300000 5 312500 600000 3 520883 800000 maximum 2 781250 Note Bit generation formulas may differ between product models Preamble A
33. IT CRC CCITT SYNC 1 16BIT CRC CCITT 0 16BIT CRC 1 1 APPEND CRC RxCRC AS DATA HDLC ONLY 0 STRIPPED 1 KEPT 1 SHARED FLAGS TRANSMISSION HDLC ONLY 1 IDLE FLAGS TRANSMISSION DATA INVERSION 1 0 0 NORMAL 1 INVERTED Channel Control High Address 06Eh 072h 076 07Ah 07Eh 082h Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value 0 This register is reserved for future use REGISTER 15 014 13 012 011 010 09 D7 06 D5 D4 D3 D2 D1 DO FUNCTION CONTROL HI XIX XIXIEXIXIXI XIXIXIXIXIXIXI XI X North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 10 of 29 North Atlantic Industries Excellence in ALL we do Channel Control Low Address 06Ch 070h 074h 078h 07Ch 080h Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value 0 This register is used to for channel control configuration REGISTER D15 D14 D13 D12 D11 D10 D9
34. Low Watermark Reached bit in the ISR Interrupt Status Register When the Low Watermark Reached an interrupt request will be generated REGISTER 15 014 013 012 011 010 07 06 D5 03 02 01 FUNCTION LO WATERMARK 0 D DATA BIT HDLC Address Sync Character Address OE4h OE6h OE8h OEah OEch OEeh Chan 1 6 Type unsigned character word Range not applicable Read Write R W Initialized Value 5 Modes Affected HDLC and Synchronous This register is mode dependant If using HDLC mode this value is compared to the address is received message and if it s equal the message is stored in the receive buffer If using Mono Bi Synchronous mode this value is considered the Sync Character and is used for communication synchronization The receiver searches incoming data for the Sync Character once found communication is synchronized and additional data is valid REGISTER 015014 013 012 11 10 09 07 D6 D5 D4 D3 D2 D1 DO FUNCTION HDLC SYNC CHAR D DATA BIT Termination Character Address OFOh OF2h OF4h OF6h OF8h OF ah Chan 1 6 Type unsigned character usually a member of the AS
35. O to verify that the sent data Loop Back is usually used for test REGISTER D15 D14 D13 D12 D11 D10 09 08 07 06 05 D4 D3 D2 D1 DO FUNCTION INTERFACE LEVELS 65232 RESERVED 7110 65422 4 RS485 11010 MANUAL LOOP BACK 4 TRI STATE North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 8 of 29 North Atlantic Industries Excellence in ALL we do Tx Rx Configuration Low Address 054h 058h 05Ch 060h 064h 068h Chan 1 6 Type binary word Range not applicable Read Write R W Initialized Value 0 This register is used to set the transmit receive configuration for the associated channel programmed protocol see Protocol Register Functions depend upon REGISTER p15 p14 p13 p12 p11 p10 05
36. ON DSP VERSION D DATA BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 19 of 29 North Atlantic Industries Excellence in ALL we do GENERAL USE MEMORY MAP 7D8 Platform R 7EA Watchdog Timer R W 7DA Model R 7EC Soft Reset 7DC Generation R 7EE Part Number R 7DE Special Spec Serial Number R 7E0 Interrupt Level R W 722 Date Code R 7E2 Test Enable R W 7F4 Rev Level PCB R 7E4 Module 1 Test Status R 7F6 Rev Level Master FPGA R 7E6 Module 2 Test Status R 7F8 Rev Level Master DSP R 7E8 Module 3 Test Status R 7FA Board Ready R GENERAL USE REGISTER DEFINITIONS Platform Address 7D8h Type ASCII character in each upper and lower byte Range not applicable Read Write R Initialized Value 3624h The register holds the VME platform code 64 in ASCII ASCII 6 is in upper byte and ASCII 4 is in lower byte REGISTER 15 014 013 012 011 010 D9 07 06 05 D
37. Page 3 of 29 North Atlantic Industries Excellence in ALL we do CONFIGURATION The VME bus interface will respond to A32 D16 A24 D16 and A16 D16 DTB cycles A32 mode Unit responds to address modifiers OA OD OE and 09 Base address can be set anywhere in the 4 Gigabyte address space on 512 byte boundaries A24 mode Responds to address modifiers 3A 3D 3E and 39 Base address can be set anywhere in the 16 Megabyte address space on 512 byte boundaries A16 mode Responds to address modifiers 2A 2D 2E and 29 Base address can be set anywhere in the 64 K byte address space on 512 byte boundaries Note Address switch A8 A9 amp A10 must be set to ON for 2048 byte boundaries SW1 1 SW1 2 amp SW1 3 Enable Geographical Addressing by removing jumper from JP2 Disable by adding jumper to JP2 GEOGRAPHICAL ADDRESSING Geographical Addressing is implemented This card will respond to address modifier 2Fh for A24 Address mode where the 5 Msb s of the A24 address are the 5 bits defined by the slot in VME back plane The Card can optionally be interrogated at 2Fh to determine resource requirements and available functionally Using the address modifier 2Fh the following need to be written to the card 1 The base address the card should respond to 2 The address modifier A16 A24 A32 3 Then enable the card For example If the card is in slot 10 the 5 Msb s are 01010 so the address of the CSR registers 01010
38. S 12 53 TXD 09 65 RXD 11 77 CTS 07 6 DCD 11 18 5 07 30 Ground 42 CLK 12 54 CLK 08 66 DCD 10 78 CLK 07 7T TXD 11 19 TXD 07 31 CTS 09 43 TXD 12 55 DCD 08 67 CTS 10 8 RTS 10 20 RXD 07 32 RXD 09 44 CLK 11 56 RXD 08 68 CLK 10 9 TXD 10 21 CTS 12 33 CTS 08 45 DCD 11 57 DCD 07 69 Ground 10 RXD 10 22RXD 12 34 RTS 08 46 RXD 11 58 5 07 70 RTS 09 11 DCD 09 23 CTS 11 35 Ground 47 DCD 10 59 07 71 09 12 CTS 09 24 5 11 36 TXD 08 48 CTS 10 60 RTS 12 72 TXD 09 J3 AMP 748483 5 Mate AMP 748368 1 Pin Pin Pin Pin Pin Pin Pin 1 Chassis 13 15 25 DCD 18 37 RTS 13 49 CLK 16 61 18 73 14 2 5 18 14 5 14 26 TXD 17 38 TXD 13 50 15 62 TXD 18 74 Ground 3 RXD_18 15 14 27 RTS 16 39 13 51 RTS 15 63 CLK 17 75 RXD 14 41 5 17 16 DCD 14 28 TXD 16 40 Chassis 52 CLK 15 64 DCD 18 76 DCD 13 5 17 17 TXD 14 29 RXD 16 41 RTS 18 53 TXD 15 65 RXD 17 77 CTS 13 g DCD 17 18 5 13 30 Ground 42 18 54 CLK 14 66 DCD 16 78 CLK 13 7 17 19 TXD 13 31 CTS 15 43 TXD 18 55 14 67 CTS 16 5 16 20 13 32 RXD 15 44 CLK 17 56 RXD 14 68 CLK 16 9 16 21 5 18 33 CTS 14 45 DCD 17 57 DCD 13 69 Ground 10 RXD 16 22RXD 18 34 RTS 14 46 RXD 17 58 13 70 RTS 15 11 DCD 15 23 CTS 17 35 Ground 47 DCD 16 59
39. TA BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 14 of 29 North Atlantic Industries Excellence in ALL we do Rx Buffer Low Watermark Address 0D8h ODah ODCh ODeh OEOh OE2h Chan 1 6 Type binary word Range 0 Low Watermark High Watermark 32767 Read Write R W Initialized Value 1000 decimal 3E8h This register defines the Receive Buffer Low Watermark value When the Rx Buffer size is less than the Low Watermark value FIFO Status bit D3 is flagged and If XON XOFF is enabled XON is sent and or If RTS CTS isenabled RTS goes active The Watermark registers are used for XON XOFF and or RTS CTS flow control The Receive Buffer Low Watermark register value controls when the XON character is sent when using software flow control and controls when the RTS signal would be asserted when using hardware flow control For software flow control operation the XON character would be sent once when the number of bytes in the Rx FIFO equals the value in the Receive Buffer Low Watermark register AND an XOFF character has be sent prior to this XON character The valid state transition to sending the XON character can only be from the state of a previous XOFF character that has been sent There is a Low Watermark Reached interrupt enable disable bit in the Interrupt Enable Register and a
40. able Read Write R W Initialized Value not applicable This register describes the status of 13 different events These events are latched and not cleared until read by the host See specific registers for function description and programmin g REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Jg R N FUNCTION INTERRUPT STATUS PARITY ERROR Rx BUFFER ALMOST FULL CRC ERROR sync amp hdlc only Rx COMPLETE ETX RECEIVED Rx DATA AVAILABLE Rx OVERRUN HIGH WATERMARK REACHED LOW WATERMARK REACHED Tx BUFFER ALMOST EMPTY Tx COMPLETE TIME OUT OCCURRED BREAK ABORT SYNC CHAR DETECTED N A N A gt lO O JO JOJO O JO o o 2 JO o o o o O 2 O O O JO o o o o O O 2 O O O JO o o o o O O O JO o o o o O O O O JOJO JO o o o o O O O O JOJO O JO o o O O O JO o o o o O O O O O 2 O O JO sO o o o O O O O O 2 JO o o o O O O O O JOJO 2 o o o O O O O O JOJO o 2 o o o o O
41. d Value 31767 decimal 7C17h This register defines the Receive Buffer High Watermark value When Rx Buffer size equals the High Watermark value FIFO Status bit D3 is flagged and If XON XOFF is enabled XOFF is sent and or If RTS CTS enabled RTS goes inactive The Watermark registers are used for XON XOFF and or RTS CTS flow control The Receive Buffer High Watermark register value controls when the XOFF character is sent when using software flow control and controls when the RTS signal would be negated when using hardware flow control For software flow control operation the XOFF character would be sent once when the number of bytes in the RX FIFO equals the value in the Receive Buffer High Watermark register Once the XOFF has been sent it cannot be sent again until the XON character has been sent The valid state transitions to sending the XOFF character can be either no previous XON XOFF character sent or a previous XON character sent There is also a High Watermark Reached interrupt enable disable bit in the Interrupt Enable Register and a High Watermark Reached bit in the ISR Interrupt Status Register When the High Watermark Reached and interrupt request will be generated REGISTER 15 014 013 012 011 010 09 08 07 06 05 D4 D3 D2 D1 DO FUNCTION WATERMARK VALUE 0 DID D DA
42. d with all channels running simultaneously Asynchronous and synchronous internal clock Bit Rate Generation limitation s Bit rate generation is based on a primary clock divided by an integer value Programmed bit versus actual bit rate will have greater resolution at lower bit rates 115 KHz When specifying internal clock the card generates and transmits the actual bit rate as close rounding off to the programmed bit rate based on the following formula Actual bit rates available 25 MHz N synchronous 1 5625 MHz N asynchronous N 7 integer Asynchronous examples Programmed Bit Rate b s Integer Divisor Actual Bit Rate 381 minimum 4096 381 5 600 2604 600 2400 651 2400 9600 163 9586 57600 27 57870 115200 14 111607 300000 5 312500 600000 3 520883 800000 maximum 2 781250 Note Bit generation formulas may differ between product models Data transfers within 300 ns 32 Kbytes for each Receive and Transmit buffer Accessed in 16 bit mode only 1 vector per channel 5 VDC 1 per module Mode dependant RS232 has lower power 15 RS422 more C 0 C to 70 C E 40 C to 85 C See part number 40 C to 105 C Geographical addressing can be implemented Otherwise board dip switches are activated for setting base address 9 2 H 4HP 0 8 W 233 4 x 20 3 x 160 mm deep 22 OZ 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 www naii com e mail sales naii com Cage Code 0VGU1
43. ddress 0A8h OAAh OAch OAeh OBOh 0B2h Chan 1 6 Type binary word Range High word 80h AOh COh or EOh Low word 00h to FFh Read Write R W Initialized Value 0 Modes Affected HDLC Bi Sync This register determines both the number of preambles and the preamble pattern sent out during preamble transmission The high byte decodes 1 2 4 or 8 preambles The low byte describes the preamble pattern Preamble transmission applies to both the HDLC and Sync modes In HDLC mode zero bit insertion is disabled during preamble transmission REGISTER 0151014 013 012011 010 D9 08 07 06 05 D4 D3 D2 D1 DO FUNCTION PREAMBLE 1 1 PREAMBLE VALUE 1 0 1 2 PREAMBLES VALUE OxNN 1 1 4 PREAMBLES VALUE OxNN 1 1 1 8 PREAMBLES VALUE OxNN North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 13 of 29 North Atlantic Industries Excellence in ALL we do Tx Buffer Almost Empty Address 0B4h OB6h OB8h OBah OBCh Chan 1 6 Type unsigned integer Range 0 to 32767 Read Write R W Init
44. erted within 70 The inverted word remains until replaced by a new word User after 70 uSec looks for the inverted word to confirm that the processor is operating Soft Reset Address 7Ech Type unsigned integer Range 0 to 1 Read Write R Initialized Value 0 Level sensitive Writing 1 initiates and holds software in reset state Then writing 0 initiates reboot depending upon configuration takes up to 10 seconds This function is equivalent to a power on reset Part Number Address 7Eeh Type unsigned integer word Range 0000h to FFFFh Read Write R Initialized Value not applicable This register contains the product part number A unique 16 bit code is assigned to each part number Serial Number Address 7 Type unsigned integer word Range 0000h to FFFFh Read Write R Initialized Value not applicable This register contains the board serial number Date Code Address 7F2h Type unsigned integer word Range 0000h to FFFFh Read Write R Initialized Value not applicable This register contains the date of manufacture It is read as a four digit decimal number where four digits represent YYWW Year Year Week Week For example 0126 converts to the 26 week of 2001 Revision Level PCB Address 7F4h Type unsigned integer word Range not applicable Read Write R Initialized Value not applicable This register contains the PCB revision level North Atlantic Indu
45. ialized Value 100 decimal 64h This register specifies the minimum size in bytes of the transmit buffer before the TxFIFO Almost Empty Status bit D1 the FIFO Status register is flagged High True If the interrupt is enabled see Interrupt Enable register VME interrupt will be generated REGISTER 015 014 013 012 011 010 D9 07 D6 05 D3 D2 D1 FUNCTION Tx BUFFER AE VALUE D DATA BIT Rx Buffer Almost Full Address 0COh 0C2h 0C4h OC8h OCah Chan 1 6 Type unsigned integer Range 0 to 32767 Read Write R W Initialized Value 32667 0x7F9B This register specifies the maximum size in bytes of the receive buffer before the RxFIFO Almost Full Status bit DO in the FIFO Status register is flagged High True If the interrupt is enabled see Interrupt Enable register a VME interrupt will be generated REGISTER D15 D14 D13 D12 D11 D10 09 07 06 D5 D4 D3 D2 D1 DO FUNCTION Rx BUFFER AF VALUE D DATA BIT Rx Buffer High Watermark Address 0D2h 0D4h OD6h Chan 1 6 Type binary word Range Low Watermark lt High Watermark lt 32767 Read Write R W Initialize
46. ications this card can be paralleled with another card to offer redundancy User provided software control is required to drive one output ON at time during data transmission No two or more cards in parallel should transmit simultaneously Output levels are in tri state while transmission is inactive Geographical addressing can be implemented A watchdog timer is provided to monitor processor activity To simplify logistics Part number Serial number Date code and Rev level are stored in non volatile memory locations A VxWorks Software Communications Driver amp Library is available from our WEB site http www naii com A current updated soft copy of this manual is also available at our web site North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 2 of 29 North Atlantic Industries Excellence in ALL we do SPECIFICATIONS Number of channels Data rate VME Data transfer Receive Transmit buffers Interrupts Power Temperature operating Storage temperature Base address Size Weight North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 Eighteen 18 fully programmable 4 Mbits s per channel in Synchronous HDLC mode 800kbits s per channel in Asynchronous mode RS 422 amp RS 485 Data can be read 4us after receipt in UART These data rates are verifie
47. lue 2020h This register holds product special code in ASCII ASCII spaces are used for none where ASCII space is in upper byte and ASCII space is in lower byte REGISTER 015 014 013 012 011 010 09 08 07 06 05 D4 03 D2 D1 DO FUNCTION SPECIAL SPEC D DATA BIT ASCII ASCII Interrupt Level Address 7EOh Type unsigned integer Range 0 to 7 Read Write R Initialized Value Oh This register is used to define the Interrupt Priority Level Enter O to disable interrupts Enter in priority level O through 7 otherwise REGISTER D15 D14 D13 D12 D11D10 06 05 D4 D3 D2 D1 FUNCTION FPGA VERSION D DATA BIT Test Enable Address 7E2h Type binary word Range not applicable Read Write R Initialized Value Oh This register is used to enable the Loopback Test DO The 00 test transmits 65580 characters from each channel FIFO buffer which is looped it back to the receive FIFO buffer where it is checked for validity Test checks and verifies internal hardware for proper operation Card implements DO as Power On Self Test or POST POST cannot be disabled REGISTER 015 014 013 012 11
48. mit data buffer Data intended to be transmitted must be placed here prior to transmission Data words are 8 bit and occupy the register s lowest significant bits Isbs or low byte See bit map below REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO FUNCTION TRANSMIT BUFFER X X X X X X X X D D D D D D D D X DON T CARE D DATA BIT Receive Buffer Address 00Ch 00 010h 012h 014h 016h Chan 1 6 Type unsigned integer word Range 00h or FFh for low byte and for high byte Read Write R Initialized Value Not Applicable This register is the receive data buffer Data is received in the low byte as unsigned integer The high byte is used for status REGISTER 15 014 013 012 011 01009 08 07 D6 05 D4 D3 D2 D1 DO FUNCTION RECEIVE BUFFER 5 5 5 5 5 5 5 5 S STATUS BIT D DATA BIT Asynchronous PE FE X X X X EOF only if Termination Char is used Bi Mono Synchronous xX X X HDLC Mode xX X X X X X EOF X VFRRDOCRCRAB X X C R X Last Word is Status Word PE Error FE Framing Error EOF End Of Frame Parit
49. n 100 54 Max Driver Current in High Z State Power On N A N A 1000 Max Driver Current in High 2 State Power Off 6mMA 2V 100 1000 Receiver Input Voltage Range 15V 10V to 10V 7V to 12V Receiver Input Sensitivity 3V i200mV i200mV Receiver Input Resistance Ohms 3k to 7k 120 10k 2 EIA232 standard uses negative bipolar logic in which a negative voltage signal represents logic 1 and positive voltage represents logic 0 FACTORY DEFAULTS Address recognition Off Baud rate 9600 CTS RTS Disabled Clock select Internal DCD DTR Disabled HDLC SDLC address sync char 0x00A5 Interrupt level 0 Interrupt vector 0x00 Lower limit 100 Mode Tri State asynchronous Number of data bits 8 Parity Disabled Receivers Enabled RX buffer almost full 32667 Stop bits 1 TX buffer almost empty 100 Upper limit 31767 XON 0x11 XOFF 0x13 XON XOFF Disabled Note See function descriptions for specific default values North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 25 of 29 CONNECTORS North Atlantic Industries Excellence in ALL we do Front panel Connectors J1 J2 amp J3
50. ne Module ID P1 ASCII Find ASCII in upper byte and ASCII 3 in lower byte together 5033h REGISTER 015 014 013 012 011 010 D9 07 D6 05 03 02 01 DO FUNCTION MODULE ID D DATA BIT ASCII ASCII 3 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 18 of 29 FPGA Version Address 1FCh North Atlantic Industries Excellence in ALL we do Type unsigned integer word Range 0 to 65535 Read Write R Initialized Value not applicable This register contains the FPGA version number REGISTER 15 014 013 012 011 010 D9 07 06 05 D4 D3 02 D1 DO FUNCTION FPGA VERSION D DATA BIT DSP Version Address 1Feh Type unsigned integer word Range 0 to 65535 Read Write R Initialized Value not applicable This register contains the DSP firmware version number REGISTER D15 D14 D13 D12 D11 D10 09 07 06 05 D4 D3 D2 D1 DO FUNCTI
51. rs are 2 groups of 3 not 1 per channels Clock cs 11 19 02 Mode has 3 options Tx Rx Configuration Low losses DTR DSR option Channel Control Low loses both DTR and DSR options Time out value LSB is 35 us not 25 Watchdog Timer is 70 not 50 us 1 7 Added Special Option code to Part Number GS 12 12 2 1 8 Pin 14 CTS is HIGH and Pin 33 CTS is LOW on front panel connectors GS 1 16 03 1 9 Revealed hidden pin numbers in J3 Connector pin out table GS 1 20 3 2 0 Enter baud rate directly into Baud Rate Register GS 02 11 03 21 Added TIME OUT ENABLE to Channel Control Lo Register Moved AUTO TRANSMIT 71113 MODE ENABLE from Channel Control Low to Tx Rx Configuration Low register Card is configurable for 18 channels only not 6 or 12 The board contains three green LED s 2 2 LED1 LED2 amp LED3 that are for factory use only LED2 amp LED3 will be ON during normal GS 10 29 3 operation 23 Use RXD tied to TXD and RXD tied to TXD GS 11 5 3 24 Edits Baud Rate Hi Lo register programming GS 1 23 4 25 Correct address to Baud Rate Low FOR COMMERCIAL AND MILITARY APPLICATIONS GS 3414 26 Interface levels are programmable in groups of three GS 5 26 4 2 7 RS422 is terminated with 120s not 10k GS 11 5 4 28 Timeout Value defaults to 1 second 9C40h GS 7 8 5 2 49 New Address KL 04 24 07 Added clarification to internal clock bit rate generation and available bit rates Clarified TxRx 3 0 Config Low High register bit actions Corrected minor typos AS 01
52. stries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3 A001 Rev 3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 22 of 29 North Atlantic Industries Excellence in ALL we do Revision Level Master FPGA Address 7F6h Type unsigned integer word Range not applicable Read Write R Initialized Value not applicable This register contains the Master FPGA firmware revision level Revision Level Master DSP Address 7F8h Type unsigned integer word Range not applicable Read Write R Initialized Value not applicable This register contains the Master DSP firmware revision level Board Ready Address 7Fah Type binary word Range not applicable Read Write R Initialized Value not applicable This register can be polled to determine if the card is ready for configuration or any register read or write access When board initialization is completed after as much as 10 seconds the board is ready for access and the Board Ready register is set to AA55h North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com 4 9 2009 Cage Code 0VGU1 64RS3_A001_Rev_3 1 Page 23 of 29 North Atlantic Industries Excellence in ALL we do GLOSSARY CTS Clear to Send CTS RTS If enabled the operation of these bits is automatic Both CTS RTS amp DTR DSR can be enabled at the same
53. y Bit VFR Valid Frame RDO Receive Data Overflow CRC CRC RAB Receive msg Aborted C R Command Response 1 Calculated parity does not match the received parity bit 1 A character framing error was detected 1 Indicates End of Frame Useful to identify multiple frames in large buffer This bit carries the parity bit of the last received character 0 Received fame is invalid 0 No data overflow has occurred 0 Fail Received frame contains errors 0 No abort condition detected Only significant for 2 byte address mode Number of Words Tx Buffer Address 018h 01Ah 01 01Eh 020h 022h Chan 1 6 Type unsigned integer word Range 0 to 32767 Read Write R Initialized Value 0 This register contains the number of words to be transmitted 1 Overflow 1 Pass CRC errors in received frame 4 Receive frame was aborted REGISTER 15 014 013 012 011 010 09 08 D7 06 05 D4 D3 D2 D1 DO FUNCTION NUM WORDS TX BUFFER D DATA BIT North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 9 2009 64RS3_A001_Rev_3 1 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code 0VGU1 Page 6 of 29 North Atlantic Industries Excellence in ALL we do Number of Words
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