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CMV34M Hardware Manual - RTD Embedded Technologies, Inc.

1. IDAN Pin Signal Function CPU Pin 1 Red Red Analog Output 4 2 Green Green Analog Output 6 3 Blue Blue Analog Output 8 4 Reserved Reserved 5 GND Ground 9 6 GND Ground 9 7 GND Ground 9 8 GND Ground 10 9 45V 5 Volts 7 10 GND Ground 10 11 Reserved Reserved 12 DDC Data Monitor data 5 13 HSYNC Horizontal Sync 2 14 VSYNC Vertical Sync 1 15 DDC CLK Monitor Clock 3 BDM 610000077 Rev A BDM 610000077 Rev A Table 63 USB 9 Pin D Connector male IDAN Pin Signal Function Mode 1 VCCI 45 V to USB1 Output 2 Data USB1 USB1 Data input output 3 Data USB1 USB1 Data input output 4 GND Ground 5 GND Ground 6 45 V to USB2 Output 7 Data USB2 USB2 Data input output 8 Data USB2 0582 Data input output 9 GND Ground Table 64 Ethernet 9 Pin D Connector female IDAN Pin RJ 45 Pin Signal CPU Pin 1 3 B RX 1 2 4 C 3 3 1 A TX 5 4 7 D 7 5 Ground 9 6 6 B RX 2 7 5 4 8 2 A TX 6 9 8 D 8 Appendix C IDAN Dimensions and Pinout 81 82 CMV34M cpuModule BDM 610000077 Rev A Appendix D Additional Information Application Notes RTD offers many application notes that provide assistance with the unigue feature set of the CMV34M cpuModule For the latest application notes refer to the RTD website Drivers and Example Programs To obtain the latest versions of drivers and example programs for this cpuModule
2. Onboard PCI PCle Devices Physical Dimensions Board Spacing Appendix B Troubleshooting Common Problems and Solutions Troubleshooting a PC 104 System How to Obtain Technical Support AppendixC IDAN Dimensions and Pinout IDAN Dimensions and Connectors External I O Connections Appendix D Additional Information Application Notes BDM 610000077 Rev A Table of Contents Drivers and Example Programs HH Hs s hne 83 Interrupt Programming p RO ss NEC o 83 Serial Port Programming RIS ELE RD DUK E LENA Redes 83 PC 104Specifications olio Dr REDIMERE RN ERR DECUS 83 AppendixE Limited Warranty viii CMV34M cpuModule BDM 610000077 Rev A Chapter 1 Introduction This manual provides comprehensive hardware and software information for users developing with the CMV34M PCle 104 cpuModule Note Read the specifications beginning on page 9 prior to designing with the cpuModule A This manual is orga
3. Power Management drove rop e ri E RETE RO EUER Enabling Enhanced Intel SpeedStep Technology Core 2 Duo Advanced Configuration and Power Interface ACPI Power Button MOdes tae Low Power Wake Options a AT vs ATX Power Supplies ATX Power Supply Signal sika e kon nak rena Reducing Power Consumption Multi Color LED Reset Status Features and Settings That Can Affect Boot Quick BOO enn Add On Cards With BIOS Extensions VGA Controller ee Hard Drive kko dek Monitor TYPE ERR ENS NVRAM Updates iii ekehnbbebr le ru RR eet e NR V RE Boot Device Order 2 eee be ebdaaw ba dele System Recovery ioter e We aa tur eR erae pa bee n Reset Button Recovery enn Load Default BIOS Settings Serial Power On Self Test POST Code Output BIOS Boot Block Recovery Appendix A Hardware Reference Jumper Settings and Locations
4. e ee 29 Serial Port 1 CN7 and Serial Port 2 CN8 30 Serial Port UART cos ie etes eres SES S RN 30 RS 232 Serial Port Default uuo Re Roper EE rr ON ee 30 RS 422 or RS 485 Serial Port T 31 RS 422 and RS 485 Mode Pinout ne 32 Dual Serial Port ARA RE E 33 Advanced Digital I O aDIO Port CN6 35 USB 2 0 Connector CN17 LL eee hes e re ees 36 Ethernet 10 100 1000Base T and TX Connector 20 37 PCle 104 Type 2 Bus 1 Top and CN2 Bottom 38 PCle 104 Type 2 Compatibility ke RR ____ _ RE 40 41 PCle Link Configuration ERR ve 41 PCle Peei TO Peet ius ooo te ER 41 Optional RTC Battery Input 3 ee 42 Fan Power Switched CN15 LLL ee n ens 42 Chapter 4 Using the cpuModule The RTD Enhanced AMIBIOS e e he hee he rea ean 44 Configuring the RTD Enhanced AMIBIOS LL I Ie eese 44 Entering the BIOSSet p ea E SERE ERO QUOD 44 Field Select Mm 44 Main Menu Setup Fields em Ee aE rr A ea TEO a ee kje pala 45 Mem
5. Note Future BIOS versions may have slightly different setup menus and options BDM 610000077 Rev A Chapter 4 Using the cpuModule 45 Memory Map Table 33 shows how memory in the first megabyte is allocated in the system Table 33 First Megabyte Memory Map Address hex Description C0000 FFFFFh ROM 256 KB BIOS in Flash EPROM shadowed into DRAM during runtime C0000 EFFFFh Run time user memory space Usually memory between C0000h and CFFFFh is used for the BIOS of add on VGA video cards A0000 BFFFFh Normally used for video RAM as follows EGA VGA 0A0000 0AFFFFh Monochrome 0B0000 0B7FFFh CGA 0B8000 0BFFFFh 00502 9FFFFh DOS reserved memory area 00400 00501h BIOS data area 00000 003FFh Interrupt vector area Memory beyond the first megabyte can be accessed in real mode by using EMS or a similar memory manager See your OS or programming language references for information on memory managers 46 cpuModule BDM 610000077 Rev A Address As with all standard PC 104 boards the I O total I O space is 64k in size However because early processors only addressed 10 address lines SA0 SA9 the first 1k is used for legacy I O devices Any ISA add on modules you install must therefore use I O addresses in the range of 0 1023 decimal or 000 3FF hex The upper I O addresses are used for PCI I O devices and are automatically assigned by the BIOS or operating system at boot time Note If yo
6. The bus connectors of the cpuModule are simply plugged onto a PC 104 stack to connect to other devices Follow the procedure below to ensure that stacking of the modules does not damage connectors or electronics WARNING Do not force the module onto the stack Wiggling the module or applying too much pressure may damage it If the module does not readily press into place remove it check for bent pins or out of place keying pins and try again For mechanical dimensions including board to board spacing see Physical Dimensions on page 68 1 Turn off power to the PC 104 system or stack Always work at an ESD protected workstation and wear a grounded wrist strap Select and install stand offs to properly position the cpuModule on the stack Remove the cpuModule from its anti static bag Check that pins of the bus connector are properly positioned nu Check the stacking order make sure all ofthe busses used by the peripheral cards connected to the cpuModule 7 Hold the cpuModule by its edges and orient it so the bus connector pins line up with the matching connector on the stack 8 Gently and evenly press the cpuModule onto the PC 104 stack 18 CMV34M cpuModule BDM 610000077 Rev A Connecting the Utility Cable The multi function connector CN5 implements the following interfaces e compatible keyboard e PS 2 mouse port e Speaker port 0 1W output e Hardware Reset input e Battery input
7. PCMCIA trying to use the same memory address check for two software devices e g EMM386 PCMCIA drivers etc trying to use the same memory addresses check for hardware and software devices trying to use the same memory address check for an address range shadowed see Advanced Setup screen while in use by another hardware or software device I O address conflict check for another module trying to use I O addresses reserved for the cpuModule between 010h and 01Fh check for two modules e g dataModules PCMCIA cards Ethernet trying to use the same I O addresses 72 CMV34M cpuModule BDM 610000077 Rev A Problem keyboard does not work Table57 Troubleshooting cont d Cause keyboard interface damaged by misconnection wrong keyboard type Solution check if keyboard LEDs light verify keyboard is an AT type or switch to AT mode floppy drive light always on two hard drives will not work but one does cable misconnected both drives configured for master check for floppy drive cable connected backwards set one drive for master and the other for slave operation consult drive documentation floppy does not work data error due to drive upside down orient drive properly upright or on side will not boot when video card is removed illegal calls to video controller look for software trying to access nonexistent video controller for video sound or beep commands
8. During the time of this manual s publication 32GB was the largest available SATA Disk Chip capacity BDM 610000077 Rev A Chapter 1 Introduction 7 Block Diagram The next figure shows a simplified block diagram of the CMV34M cpuModule CPU ER 1GB or 2GB Surface Mount DDR2 800 Dual Channel Memory 2 High Speed North Bridge RTD Custom USB 2 0 Ports PCle Switch ASIC GMCH m Gigabit COM1 Ethernet Port COM3 1 0 Hub Super 1 0 South Bridge SATA Disk E Chi si COMA USB 3 0 Enhanced PS 2 Mouse Controller 8105 and Keyboard 2 2 Figure 2 CMV34M cpuModule Simplified Block Diagram A 2 7 PCle 104 Bus Type 2 You can easily customize the cpuModule by stacking PCI 104 Express or PCle 104 modules such as video controllers Digital Signal Processors drive carriers LAN controllers or analog and digital data acquisition modules Stacking modules onto the cpuModule avoids expensive installations of backplanes and card cages and preserves the module s compactness The cpuModule uses the RTD Enhanced AMI BIOS Drivers in the BIOS allow booting from hard disk Disk Chip or boot block flash thus enabling the system to be used with traditional disk drives or nonmechanical drives Boot from USB devices and network are also supported The cpuModule and BIOS are also compatible with any real time operating systems for PC compatible comp
9. abnormal video flat panel is enabled disable the flat panel in the BIOS can only use 640 x 480 resolution in Windows flat panel is enabled disable the flat panel in the BIOS video drivers not installed install the video drivers will not boot from PCMCIA hard drive booting from PCMCIA is not supported boot from SSD use autoexec bat to load PCMCIA drivers run application from PCMCIA card COM port will not work in RS 422 or RS 485 modes not configured for RS 422 485 correctly configure serial port in Setup program COM port will not transmit in RS 422 or RS 485 mode not enabling transmitters control RTS bit of Modem Control Register to enable transmitters see Serial Port descriptions date and time not saved when power is off no backup battery connect a backup battery to the multi function connector Troubleshooting a PC 104 System Ifyou have reviewed the preceding table and still cannot isolate the problem with your CMV34M cpuModule please try the following troubleshooting steps Even if the resulting information does not help you find the problem it will be very helpful ifyou need to contact technical support 1 Simplify the system Remove items one at a time and see if one particular item seems to cause the problem 2 Swap components Try replacing items in the system one at a time with similar items BDM 610000077 Rev A Appendix Troubleshooting 73 How to O
10. 1 P0 0 2 P0 1 3 P0 2 4 P0 3 5 0 4 6 0 5 7 0 6 8 0 7 9 strobe 0 10 strobe 1 11 P1 0 12 P1 1 13 1 2 14 1 3 15 GND 16 5 V 1 Available during standby BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 35 USB 2 0 Connector CN17 Two USB 2 0 compliant connectors are available on connector 17 Table 24 provides the pinout of the USB connector Note For proper operation at USB 2 0 speeds be sure to use a cable that is rated for USB 2 0 such as the cable kit supplied by RTD Table 24 USB Connector CN17 Pin Signal Function In Out 1 VCC1 Supply 5 V to 0581 out 2 VCC2 Supply 5 V to USB2 out 3 DATA1 Bidirectional data line for USB1 in out 4 DATA2 Bidirectional data line for USB2 in out 5 DATA1 Bidirectional data line for USB1 in out 6 DATA2 Bidirectional data line for USB2 in out 7 GND Ground out 8 GND Ground out 9 GND Ground out 10 GND Ground out Facing the connector pins the pinout of CN17 is 36 CMV34M cpuModule 9 7 KONCE we 10 8 5 3 1 6 4 2 BDM 610000077 Rev A Ethernet 10 100 1000Base T and TX Connector CN20 This connector provides a 10 100 1000Base T Ethernet connection Table 25 provides the pinout of the Ethernet connector For 1000Base T all four pairs are used for transmit and receive To use the onboard 10 100 1000 Ethernet controller Ethernet must be enabled in the BIOS When enabled the multi color LED will blink
11. 1 VSYNC Vertical Sync out 2 HSYNC Horizontal Sync out 3 DDCSCL Monitor Communications Clock out 4 RED Red Analog Output out 5 DDCSDA Monitor Communications Data bidirectional 6 GREEN Green Analog Output out 7 PWR 45 V out 8 BLUE Blue Analog Output out 9 GND Ground out 10 GND Ground out Facing the connector pins of the SVGA Video connector CN18 the pinout is PWR DDCSDA DDCSCL VSYNC 28 CMV34M cpuModule BDM 610000077 Rev A SATA Disk Chip Socket 06 The SATA Disk Chip socket is an 18 pin socket in a 32 pin format that supports miniature SATA flash disk chips The socket allows a true SATA device to be attached to the board with either a socketed or soldered connection Such devices are supported by all major operating systems and do not reguire special drivers Table 12 SATA Disk Chip Socket 06 Pin Signal Pin Signal 1 GND 32 Vec 3 3V 2 RX 31 GND 3 RX 30 4 GND 29 n c 5 TX 28 n c 6 TX 27 n c 7 GND 26 Reserved 8 no pin 25 no pin 9 no pin 24 no pin 10 no pin 23 no pin 11 no pin 22 no pin 12 no pin 21 no pin 13 no pin 20 no pin 14 no pin 19 no pin 15 Reserved 18 Reserved 16 n c 17 GND 1 TX and RX are the transmit and receive respectively of the Disk Chip Installing and Configuring the SATA Disk Chip To ensure proper installation of the SATA Disk Chip follow the following configuration steps 1 2 3 Always work at an ESD protected workstati
12. A Receive Data in 2 4 TXD1 COM Transmit Data out 7 5 TXD1 COM A Transmit Data out 3 6 RXD1 COM Receive Data in 8 7 TXD2 COM B Transmit Data out 4 8 Ring Indicate in 9 9 10 GND Signal Ground 5 Table 22 RS 422 485 and COM RS 422 485 Pin Signal Function In Out DB 9 1 RXD24 COM B Receive Data in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 TXD1 COM Transmit Data out 7 5 TXD1 COM Transmit Data out 3 6 RXD1 COM A Receive Data in 8 7 TXD2 Transmit Data out 4 8 TXD2 COM B Transmit Data out 9 9 10 GND Signal Ground 5 BDM 610000077 Rev A Advanced Digital I O aDIO Port CN6 CN6 is configured as an aDIO port aDIO is 12 digital bits configured as 8 bit programmable and 4 bit port programmable I O providing any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit programmable digital inputs match a pattern or on any value change event Bit masking allows selecting any subgroup of 8 bits The strobe input latches data into the bit programmable port and generates an interrupt Refer to Advanced Digital Ports aDIO page 50 for information on programming the aDIO Table 23 aDIO Pinout CN6 Pin Function CN6 Pin Function
13. GND 28 29 PEx1 2Rp PEx1 3Rp 30 31 PEx1 2Rn 1 3Rn 32 33 GND GND 34 35 PEx1 1Clkp PEx1 36 37 PEx1 1Clkn PEx1_0Clkn 38 39 5V_Always 5V_Always 40 41 PEx1_2Clkp PEx1 3Clkp 42 43 PEx1 2Clkn PEx1 3Clkn 44 45 CPU DIR PWRGOOD 46 47 SMB DATA Reserved 48 49 SMB CLK Reserved 50 51 n c PSON 52 BDM 610000077 Rev A BDM 610000077 Rev A Table 26 PCle 104 Type 2 Bus Signal Assignments Top View Pin Signal Signal Pin 53 STKO STK1 54 55 GND GND 56 57 PEx4 1T 0 p PEx4 OT 0 p 58 59 PEx4 1T 0 n PEx4 OT 0 n 60 61 GND GND 62 63 PEx4 1T 1 p PEx4 OT 1 p 64 65 PEx4 1T 1 n PEx4 OT 1 n 66 67 GND GND 68 69 PEx4 1T 2 p PEx4 OT 2 p 70 7i PEx4 1T 2 n PEx4 OT 2 n 72 73 GND GND 74 75 PEx4 1T 3 p PEx4 OT 3 p 76 77 PEx4 1T 3 n PEx4 OT 3 n 78 79 GND GND 80 81 SATA 1Tp SATA 0Tp 82 CN1 only 83 SATA 1Tn SATA 84 CN1 only 85 GND GND 86 87 SSTX1p SSTXOp 88 89 SSTX1n SSTXOn 90 91 GND GND 92 93 Reserved Reserved 94 95 Reserved Reserved 96 97 GND GND 98 99 Reserved Reserved 100 101 Reserved Reserved 102 103 GND GND 104 Chapter 3 Connecting the cpuModule 39 Table 26 PCle 104 Type 2 Bus Signal Assignments View Pin Signal Signal Pin 105 STK2 Reserved 106 107 GND GND 108 109 PEx4 1R 0 p PEx4 OR 0 p 110 111 PEx4 1R 0 n PEx4 OR 0 n 112 113 GND GND 114 115 PEx4 1R 1 p PEx4 OR 1 p 116 117
14. IDAN enclosure Ethernet CN20 COM2 amp 4 SVGA CNS Video CN18 z Hr ta NNE Dp zl COM183 USB 2 0 CN17 Switched Fan CN15 aDIO CN6 Apacer Multi Function CN5 M d SATA Auxiliary Power PCle Bus Battery Disk Chip CN3 CN1 amp CN2 CN13 U6 Figure 1 CMV34M cpuModule top view 2 CMV34M cpuModule BDM 610000077 Rev A Enhanced Intel SpeedStep Core 2 Duo only Enhanced Intel SpeedStep Technology has revolutionized thermal and power management by giving operating systems greater control over the processor s operating freguency and input voltage Systems can easily manage power consumption dynamically Today s embedded systems are demanding greater performance at eguivalent levels of power consumption Legacy hardware support for backplanes board sizes and thermal solutions have forced design teams to place greater emphasis on power and thermal budgets Intel has extended architectural innovation for saving power by implementing new features such as Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the processor performance and power consumption levels to be modified while a system is functioning This is accomplished via operating system or application software which changes the processor speed and the processor core voltage while the system is operating A variety of inputs such as system power source processor thermal state or operating system policy are used to
15. PEx4 1R 1 n PEx4 OR 1 n 118 119 GND GND 120 121 PEx4 1R 2 p PEx4 OR 2 p 122 123 PEx4 1R 2 n PEx4 OR 2 n 124 125 GND GND 126 127 PEx4 1R 3 p PEx4 OR 3 p 128 129 PEx4 1R 3 n PEx4 OR 3 n 130 131 GND 5 132 133 SATA 1Rp A SATA_ORp 134 CN1 only 135 SATA_1Rn SATA ORn 136 only 137 GND GND 138 139 SSRX1p SSRXOp 140 141 SSRX1n SSRXOn 142 143 GND GND 144 145 Reserved Reserved 146 147 Reserved Reserved 148 149 GND GND 150 151 Reserved Reserved 152 153 Reserved Reserved 154 155 GND GND 156 1 Signals marked with are active low PCle 104 Type 2 Compatibility The PCle 104 2 connector is compatible with any PCI 104 Express or PCle 104 peripheral module that does not use the x16 Link This includes any card that uses the PCle x1 links USB or a power supply In addition this connector can be used to add SATA devices to the system If a card is installed that is not compatible with the Type 2 connector the CPU will keep the system in soft off and the LED will be Cyan to indicate that there is a Bus Stacking Error If this feature is not desired JP6 can be installed to disable the Bus Stacking Error feature 40 cpuModule BDM 610000077 Rev A USB 3 0 This module supports USB 3 0 or SuperSpeed USB on the CN1 and CN2 bus connectors There two USB 3 0 links available on the top bus connector CN1 and two links available on the bottom bus connector CN2 The links are provided by a T
16. RE ENA RUNG Va G ERU CE XR 12 Chapter 2 Getting Started Connector Locations 14 Selecting the Stack Order for the CMV34M 16 Stack Example e a ae a odide 17 Connecting to the Stack o ecce repu a ke ex a zadka ERR grep 18 Connecting the Utility Cable orte b par be RPG PR Role sl Ve 19 Connecting a Keyboard o union pin PARET RA ert ves iu net avete unes 19 Booting the CMV34M cpuModule for the First Time 19 Chapter 3 Connecting the cpuModule Proper Grounding Technigues 22 Connector Locations 22 Auxiliary Power heme een an 24 Utility Port Connector 5 III m e e e ens 25 Speaker Uds ifa De NIN IN ba on 25 Mri c HUUu 26 26 System RESET cpm 26 tois dB 26 PP 27 SVGA Video Connector CN18 28 BDM 610000077 Rev A Table of Contents v SATA Disk Chip Socket U6 Le 29 Installing and Configuring the SATA Disk Chip
17. Reset Pin 3 of the multi function connector allows connection of an external push button to manually reset the system The push button should be normally open and connect to ground when pushed The type of reset generated by this button can be set in the BIOS configuration utility Soft Power Button Pin 4 of the multi function connector allows connection of an external push button to send a soft power signal to the system The push button should be normally open and connect to ground when pushed For more information on the modes of the Soft Power Button refer to the Power Management section in Chapter 4 Using the cpuModule 26 CMV34M cpuModule BDM 610000077 Rev A Battery Pin 9 of the multi function connector is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only reguired to maintain time when power is completely removed from the cpuModule A battery is not reguired for board operation WARNING The optional RTC battery input connector CN13 should be left unconnected if the multi function connector 5 has a battery connected to pin 9 BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 27 SVGA Video Connector CN18 Table 11 provides the pinout of the video connector Table 11 SVGA Video Connector CN18 Pin Signal Function In Out
18. These I O lines are grouped into two ports Port 0 and Port 1 Port 0 is bit programmable Port 1 is byte programmable Port 0 supports RTD s Advanced Digital Interrupt modes The three modes are strobe match and event Strobe mode generates an interrupt and latches Port 0 when the strobe input transitions from low to high Match mode generates an interrupt when an 8 bit pattern is received in parallel that matches the match mask register Event mode generates an interrupt when a change occurs on any bit In any mode masking can be used to monitor selected lines When the CPU boots all digital lines are programmed as inputs meaning that the digital I O line s initial state is undetermined If the digital I O lines must power up to a known state an external 10 resistor must be added to pull the line high or low The 8 bit control read write registers for the digital I O lines are located from I O address 9COh to 9C4h These registers are written to zero upon power up From 9COh to 9C4h the name of these registers are Port 0 data Port 1 data Multi Function DIO Control and Wake Control register EN Note RTD provides drivers that support the aDIO interface on popular operating systems RTD recommends using these drivers instead of accessing the registers directly Digital I O Register Set Table 37 Port 0 Data I O Address 9C0h D7 D6 D5 D4 D3 D2 D1 DO P0 7 P0 6 P0 5 P0 4 P0 3 0 2 P0 0 Port 0 Data register is a re
19. bit direction programmable and 4 bit port direction programmable I O plus 2 strobe inputs giving you any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit direction programmable digital inputs match a pattern or on any value change event Bit masking allows selecting any subgroup of eight bits The strobe input latches data into the bit programmable port and generates an interrupt Any of the interrupt modes can be used to generate a wake event from any standby powerdown mode BDM 610000077 Rev A Chapter 1 Introduction 3 Ordering Information The CMV34M cpuModule is available with a selection of processors and memory sizes The cpuModule can also be purchased as part of an Intelligent Data Acquisition Node IDAN building block which consists of the cpuModule and a milled aluminum IDAN frame The IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged PC 104 stack Refer to Appendix C IDAN Dimensions and Pinout for more information The CMV34M cpuModule can also be purchased as part of custom built or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD for more information on its high reliability PC 104 systems CMV34M Model Options The basic cpuModule model options are shown below Refer to the RTD
20. connector on the top is specially designed to accommodate the 22mm board spacing when mated with a standard connector When attaching a board below the CMV34M the standard 0 600 board spacing is used BDM 610000077 Rev A Appendix A Hardware Reference 69 70 cpuModule BDM 610000077 Rev A Appendix B Troubleshooting Many problems you may encounter with operation of your CMV34M cpuModule are due to common errors This appendix includes the following sections to help you get your system operating properly Common Problems and Solutions page 72 Troubleshooting a PC 104 System page 73 How to Obtain Technical Support page 74 BDM 610000077 Rev Appendix B Troubleshooting 71 Common Problems and Solutions Table 57 lists some of the common problems you may encounter while using your CMV34M cpuModule and suggests possible solutions If you are having problems with your cpuModule review this table before contacting Technical Support Problem cpuModule will not boot Table 57 Troubleshooting Cause no power or wrong polarity Solution check for correct power on the PC 104 Plus PCI bus connector incorrect Setup reboot and press Delete to run Setup defective or misconnected device on bus check for misaligned bus connectors remove other cards from stack incorrect PCle 104 cards installed LED is Cyan See PCle 104 Type 2 Compatibility on page 40 cable con
21. cpuModule BDM 610000077 Rev A Stack Example The figure below shows an example of a complete system stack Most systems will be a subset of this example This example stack may be further expanded with PCle to PCle bridges or a PCle to PCI bridge PCle 1 Peripheral PCle PCle x1 Peripheral PCle Unconnected amp Unused PCle x1 Peripheral PCI Bus Segment PCle I PCle x1 Peripheral PCle and SATA within PCle six boards of CPU 2 USB 3 0 Peripheral with pass through PCI USB 3 0 within four PCI PCle boards of CPU USB 3 0 Peripheral with pass through PCI PCI PCle SATA Hard Drive Carrier PCle Spacer to improve Spacer li PCle cooling 4 CPU PCle PCle x4Peripheral PCle PCle x1 Peripheral PCle No more than eight PCle x1 Peripheral PCI Pass Through PCle Connectors PCle x1 Peripheral PCle PCle x1 to PCI Bridge S Power Supply PCle and SATA within PCI PCle six boards of CPU no USB 2 0 Peripheral with pass through PCI more than six boards PCI PCle between CPU and USB 2 0 Peripheral with pass through PCI power supply PCI PCle PCI Peripheral PCI All four PCI PCI Peripheral with pass through ISA Peripherals PCI ISA together PCI Peripheral with pass through ISA PCI PCI Peripheral with pass through ISA PCI ISA Unconnected amp Unused ISA Bus Segment Figure 4 System Stacking Example BDM 610000077 Rev A Chapter 2 Getting Started 17 Connecting to the Stack
22. determine the proper operating state The software model behind Enhanced Intel SpeedStep Technology has ultimate control over the frequency and voltage transitions This software model is a major step forward over previous implementations of Intel SpeedStep technology Legacy versions of Intel SpeedStep technology required hardware support through the chipset Enhanced Intel SpeedStep Technology has removed the chipset hardware requirement and only requires the support of the voltage regulator processor and operating system Centralization of the control mechanism and software interface to the processor and reduced hardware overhead has reduced processor core unavailability time to 10 us from the previous generation unavailability of 250 ps Thermal Monitor The Intel Thermal Monitor is a feature on the CMV34M that automatically throttles the CPU when the CPU exceeds its thermal limit This allows the processor to operate for short durations at a higher frequency than the thermal solution or ambient temperature would otherwise allow The thermal limit and duty cycle of the Thermal Monitor cannot be modified A second thermal monitor is used to throttle the memory interface when the memory controller or the memory approaches it s thermal limit This ensures proper operation even under the harshest conditions The thermal monitors operate independently of each other aDIO with Wake on aDIO RTDS exclusive aDIO is 12 digital bits configured as 8
23. for Real Time Clock Soft Power Button input To use these interfaces you must connect to the utility port connector CN5 The utility harness from the RTD cable kit provides a small speaker two connectors for the keyboard and mouse a push button for resetting the system a soft power button and a lithium battery to provide backup power for the real time clock Refer to Utility Port Connector CN5 on page 25 to connect devices to the utility port connector Connecting a Keyboard You may plug a PC AT compatible keyboard directly into the PS 2 connector of the utility harness in the cable kit You may also use a USB keyboard plugged into any of the USB connectors Note Many keyboards are switchable between PC XT and AT operating modes with the mode usually EN selected by a switch on the back or bottom of the keyboard For correct operation with this cpuModule you must select AT mode Booting the CMV34M cpuModule for the First Time You can now apply power to the cpuModule You will see e greeting message from the VGA BIOS if the VGA BIOS has a sign on message e The cpuModule BIOS version information e Amessage requesting you press Delete to enter the Setup program e message to press F11 to choose the boot device If you don t press Delete the cpuModule will try to boot from the current settings If you press Delete the cpuModule will enter Setup Once you have configured the cpuModule using Setup save your changes and
24. match mode 1 output 10 mask register 11 compare register Table 41 DIO Control I O Address 9C3h Write Access D7 D6 05 04 03 02 01 00 Reserved Digital IRQ Mode Multi Function 00 Disabled Register Select 01 strobe Mode Port 1 Direction 00 clear mode _ 10 event mode 0 input 01 porto direction 11 match mode 1 output 10 mask register 11 register Table 42 Multi Function at Address 9C2h read write 00 clear X X X X X X X X Oin 1 out 01PortOdirection O 1 0 1 0 1 0 1 0 1 0 1 0 0 no mask 1 mask 10 DIO mask M7 M6 M5 M4 M3 M2 M1 read write 11 compare 7 C6 C5 C4 C3 C2 Ci co 1 Contents based on bits DO and D1 of DIO Control Clear Register A read to this register Clears the IROs and a write to this register sets the DIO Compare DIO Mask DIO Control Port 1 and Port 0 to zeros A write to this register is used to clear the board Port 0 Direction Register Writing a zero to a bit in this register makes the corresponding pin of the aDIO connector an input Writing a one to a bit in this register makes the corresponding pin of the aDIO connector an output Mask Register Writing a zero to a bit in this register will not mask off the corresponding bit in the DIO Compare register Writing a one to a bit in this register masks off the corresponding bit in the DIO Compare register When all bits are masked off the aDIOs comparator is disabled This condition means Event
25. out Facing the connector pins the pinout is Speaker 10 9 7 5 3 1 8 6 4 PWR A speaker output is available on pins 1 and 2 of the multi function connector These outputs are controlled by a transistor to supply 0 1 W of power to an external speaker The external speaker should have 8 Q impedance and be connected between pins 1 and 2 BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 25 Keyboard A PS 2 compatible keyboard can be connected to the multi function connector Usually PC keyboards come with a cable ending with a 5 pin male PS 2 connector Table 9 lists the relationship between the multi function connector pins and a standard PS 2 keyboard connector Table 9 Keyboard Connector Pins CN5 Pin Signal Function PS 2 5 KBD Keyboard Data 1 6 KBC Keyboard Clock 5 7 GND Ground 3 2 PWR Keyboard Power 45 V 4 To ensure correct operation check that the keyboard is either an AT compatible keyboard or a switchable XT AT keyboard set to AT mode Switchable keyboards are usually set by a switch on the back or bottom of the keyboard Mouse A PS 2 compatible mouse can be connected to the multi function connector Table 10 lists the relationship between the multi function connector pins and a standard PS 2 mouse connector Table 10 Mouse Connector Pins CN5 Pin Signal Function PS 2 10 MSD Mouse Data 1 8 MSC Mouse Clock 5 7 GND Ground 3 2 PWR Keyboard Power 5 V 4 System
26. refer to the RTD website Interrupt Programming For more information about interrupts and writing interrupt service routines refer to the following book Interrupt Driven PC System Design by Joseph McGivern ISBN 0929392507 Serial Port Programming For more information about programming serial port UARTS consult the following book Serial Communications Developer s Guide by Mark Nielson ISBN 0764545701 PC 104Specifications A copy of the latest PC 104specifications can be found on the webpage for the PC 104 Embedded Consortium http www pc104 org BDM 610000077 Rev Appendix D Additional Information 83 84 CMV34M cpuModule BDM 610000077 Rev A Appendix E Limited Warranty Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are reguired to contact the factory for a Return Materi
27. running guickly by following the simple steps described in this chapter which are 1 Before connecting the cpuModule the user must be properly grounded to prevent electrostatic discharge ESD For more information refer to Proper Grounding Techniques on page 22 Connect power Connect the utility harness Connect a keyboard Default BIOS configuration Fail Safe Boot ROM Mo CU Connect VGA monitor to the SVGA connector Refer to the remainder of this chapter for details on each of these steps BDM 610000077 Rev A Chapter 2 Getting Started 13 Connector Locations Figure 3 shows the connectors and the SATA Disk Chip socket of the CMV34M cpuModule Ethernet CN20 COM284 SVGA Video CN8 CN18 COM183 CN7 USB 2 0 kra 3i si CN17 Meli MITI ori 3 Switched ONES z ra i ZW CN15 aDIO CN6 Apacer Multi Function CN5 m d SATA Auxiliary Power PCle Bus Battery Disk Chip CN3 amp CN2 CN13 U6 Figure 3 CMV34M Connector Locations EN Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board W square solder pad on the bottom side of the board 14 CMV34M cpuModule BDM 610000077 Rev Table5 CMV34M Basic Connectors Connector Function Size and Pitch Mating Connector PCle 104 Type 2 Bus 156 pin 0 635mm Samtec ASP 129646 03 CN2 PCle 104 T
28. when the main supply is turned off power down modes 53 55 It is not reguired for board operation 3 With supplied heat sink solution Depending on the CPU usage performance may degrade as the ambient temperature approaches the maximum Contact RTD Tech Support for more information BDM 610000077 Rev A Chapter 1 Introduction 9 Electrical Characteristics The table below lists the Electrical Characteristics of the CMV34M Operating outside of these parameters may cause permanent damage to the cpuModule Symbol loc Vu lApiovec Table4 Electrical Characteristics Parameter Overcurrent Limit Output Voltage High HSYNC VSYNC Output Voltage Low HSYNC VSYNC Output Voltage High DDC Output Voltage Low DDC Input Voltage High DDC Input Voltage Low DDC Supply Current for DDC Electronics Test Condition USB Ports Each port SVGA Port 78 0 mA lo 8 0 lou 4 0 lo 8 0 mA Serial Ports RS 232 Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low R 3k R 3k Serial Ports RS 422 485 Differential Output Differential Output Common Mode Output Differential Input Threshold Absolute Max Input Voltage Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Supply current R 50 Ohm R lt 27 Ohm R lt 27 or 50 Ohm 7V lt Vem lt 7V aDIO lou 4 0 lo 8 0 Mi
29. 7 Valid Time Date always reads 1 e Bit 6 Reserved e Bits 5 0 RTC Alarm Day of the Month Altering the contents of any unlisted RTC register may interfere with the operation of your cpuModule The specific uses of the unlisted RTC registers will depend on the BIOS version loaded on the cpuModule Contact RTD s technical support for more information Note registers that are not listed above are used by the BIOS and should be considered Reserved BDM 610000077 Rev A Chapter 4 Using the cpuModule 55 Watchdog Timer Control The cpuModule includes a Watchdog Timer which provides protection against programs hanging or getting stuck in an execution loop where they cannot respond correctly The watchdog timer consists of a counter a reset generator and an interrupt generator When the counter reaches the interrupt time out it can generate an interrupt When the counter reaches the reset time out the system is reset The counter is refreshed or set back to zero by reading from a specific register The watchdog can also be put into an inactive state in which no resets or interrupts are generated The ability to generate an interrupt allows the application to gracefully recover from a bad state For example consider a system that has a reset time out of 2 seconds interrupt time out of 1 second and the watchdog timer is refreshed every 0 5 seconds If something goes wrong an interrupt is generated The Interrupt service r
30. 984h Value 0 00 0 08 0 09 0x0A 0x0B 0x0C 0x0D 0x0F 60 cpuModule Table 50 Manual LED Colors Color Automatic see Table 48 Off will reduce system power consumption Blue Green Cyan Green Blue Red Magenta Red Blue Yellow Red Green White Red Green Blue BDM 610000077 Rev A Reset Status Register The cpuModule has several different signals on board which can cause a system reset If a reset occurs the reset status register can be used to see which reset or resets have been asserted on the cpuModule The user has the ability to see which resets have been asserted Resets can also be cleared e Examine Resets Reading from I O port 0x987 will indicate if a reset has been asserted If a 1 is read the corresponding reset has been asserted If a 0 is read from the bit the reset has not been asserted e Clear Reset Each reset can be cleared by writing a 1 the selected bit of I O port 0x987 Table 51 Reset Status I O Address 987h Read Access D7 D6 D5 D4 D3 D2 D1 Utility Reset System Power Good Main 5V Input Memory Power 1 reset asserted 1 reset asserted 1 reset asserted 1 reset asserted 0 lt no reset 0 no reset 0 reset 0 no reset CPU Core Power SIO Power Good Management Power Standby Power 1 z reset asserted 1 z reset asserted 1 z reset asserted 1 reset asserted 0 no reset 0 reset 0 reset 0 reset Table 52 Reset Stat
31. C is prevented from updating e Bit6 Periodic Interrupt Enable When high the RTC IRQ will be asserted by the periodic interrupt e Bit 5 Alarm Interrupt Enable When high the RTC IRQ will be asserted when the current time matches the alarm time e 4 Update Ended Interrupt Enable When high the RTC IRQ will be asserted every time the RTC updates once per second e Bit 3 Square Wave Enable Not used e Bit 2 Data Mode Sets the data format of the RTC clock calendar registers 0 1 binary This is typically set to BCD mode e Bit 1 Hours Byte Format Sets the hour byte to 12 or 24 hour time 0 12 hour 1 24 hour This is typically set to 24 hour mode e Bit 0 Daylight Savings Enable When high the RTC will automatically update itself for Daylight Savings Time It is recommended to leave this bit low and let the operating system manage time zones and DST OCh 12 RTC Status Register C Read Only e Bit 7 IRQ Indicates that the Real Time Clock IRQ is asserted Goes high whenever one of the enabled interrupt conditions in Register B occurs e Bit6 Periodic Flag e Bit 5 Alarm Flag e Bit 4 Update Ended Flag e Bit 3 0 Reserved Reading this register will also clear any of set flag IRQ Periodic Alarm Update Ended Note that even if the interrupt source is not enabled in Register B the flags in Register C bits 4 5 and 6 may still be set 0Dh 13 RTC Status Register D e Bit
32. CMV34M cpuModules f HALO 1 EN TE pos rn User s Manual BDM 610000077 Revision A www rtd com 1509001 and AS9100 Certified CMV34M cpuModules User s Manual Document Number BDM 610000077 Revision A Copyright 2009 2012 Embedded Technologies Inc All rights reserved Trademarks Advanced Analog I O Advanced Digital I O aAlO a2DIO Autonomous SmartCal Catch the Express cpuModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of International Business Maachines Inc PCI PCI Express and PCle are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this docaument are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without
33. D3cold Only wake from S1 is supported Table 27 and Table 28 below shows the configuration of the PCle x1 links on CN1 and CN2 Table27 CN1 Link Configuration Link BIOS Name Location Connection S3 Wakesupport PCle Peer To Peer 0 Link 0 Closest to CPU Direct Yes No 1 PCle Switch Shared No To other Shared 2 PCle Switch Shared No To other Shared 3 PCle Switch Farthest from CPU Shared No To other Shared Table 28 2 Link Configuration Link BIOS Location Connection 53 Wake support PCle Peer To Peer 3 Link 3 Closest to CPU Direct Yes No 2 Link2 Direct Yes No 1 Link1 Direct Yes No 0 PCle Switch Farthest from CPU Shared No To other Shared PCle Peer To Peer Peer to Peer transactions are transactions directly between two PCle peripheral cards An example of this is writing data directly from a data acquisition card to a DSP card without first writing to the host CPU s memory The PCIe links that are directly connected to the chipset do not support Peer to Peer transactions The shared PCle links support peer to peer transactions to other shared links This is reflected in Table 27 above Peer to peer transactions may also be performed between peripheral cards attached to the x4 links However you cannot do a peer to peer transaction between a peripheral on a x4 link and a peripheral on a x1 link BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 41 Optional RTC Battery Input CN13 The op
34. Disk Chip Socket 18 pin 0 1 na Chapter 3 Connecting the cpuModule 23 Auxiliary Power CN3 The Auxiliary Power connector CN3 can be used to supply power to devices that are attached to the cpuModule These devices include hard drive front end boards for data acquisition systems and other devices Power can also be conveyed to the module through the Auxiliary Power connector CN3 The cpuModule only requires 5 VDC and ground for operation A Standby 5V may also be supplied to allow the system to support Standby power states Note Although it is possible to power the cpuModule through the Auxiliary Power connector the preferred method is to power it through the bus connector from a power supply in the stack The cpuModule can have large current transients during operation which make powering it through wires difficult Powering through the bus eliminates such problems as voltage drop and lead inductance If using the Auxiliary Power connector to power the system care must be taken to ensure good power connections The power and ground leads must be twisted together or as close together as possible to reduce lead inductance A separate lead must be used for each of the power pins All 5V pins and all ground pins must be connected Do not use wire smaller than 20 gauge and the length of the wire must not exceed 2 ft The power supply solution must be verified by measuring voltage at the Auxiliary Power Connector and verif
35. Ethernet Can be disabled in the BIOS e Serial Ports Can be disabled in the BIOS Fan Mode Set the fan to auto mode so it is used only when the processor reaches high temperatures This option will only effect the fan if it is connected to the switched fan power connector CN15 e Multi Color LED Can be disabled in the BIOS BDM 610000077 Rev A Chapter 4 Using the cpuModule 59 Multi Color LED The CMV34M has a Multi Color LED which can be enabled or disabled in the BIOS setup screen The color ofthe LED indicates the status of the board as shown in Table 48 Color Green Blue Red Yellow Red Green White R G B Cyan Blue Green Magenta Blue Red Blink Table 48 LED Colors Description Normal Operation SATA Activity cpuModule is reset cpuModule is in Standby cpuModule is approaching thermal limit Ethernet Link at 100 Mbps or Bus Stacking Error Ethernet Link at 1000 Mbps Ethernet Activity 1 Ifpower isapplied to the cpuModule while jumper JP5 is installed the LED will be red This does not indicate that the board is in reset 2 TheLED will remain White until the system is shut down The LED can also be controlled manually by writing to I O Port 984h as shown in Table 49 and Table 50 Table 49 Multi Color LED I O Address 984h D7 D6 D5 Reserved Reserved Reserved D4 D3 D2 D1 Do Reserved Reserved Multi Color LED The following table lists the color displayed and the value written I O Port
36. I TUSB7340 controller Drivers are available for Windows XP and Windows 7 Linux support is available in Kernel version 2 6 37 or later Early Linux support for USB 3 0 has been shown to have issues with USB 3 0 Hubs therefore we recommend using Kernel version 3 1 0 or later Each USB 3 0 link consists of a high speed TX and RX differential pair for SuperSpeed and a bi directional differential pair for HighSpeed FullSpeed and LowSpeed Typically a USB 3 0 Hub will use both sets of signals and USB Devices will use one set or the other In order for USB 3 0 to function correctly the SuperSpeed and HighSpeed signals for a specific link must go to the same endpoint Therefore if both USB 3 0 and USB 2 0 boards are used in the same system the USB 3 0 boards must be closer to the CPU than the USB 2 0 boards Otherwise the USB 2 0 boards will shift the HighSpeed signals without shifting the SuperSpeed signals and the link association will be broken Boot to USB and other Legacy USB features are currently not supported on the USB 3 0 links PCle Link Configuration This cpuModule supports a total of eight PCle x1 links The chipset however only provides five PCle x1 links Four of the links on CN1 and CN2 are connected directly to the chipset The other four are connected through PCle packet switch and share the bandwidth of a single x1 link back to the chipset The links that are connected to the PCle switch do not support wake from S3
37. T IRO OUT Figure 6 aDIO Match Mode Strobe Mode Another interrupt mode supported by aDIO is Strobe mode This allows the strobe pin of the DIO connector to trigger an interrupt A low to high transition on the strobe pin will cause an interrupt reguest The reguest will remain high until the Clear Register is read from Additionally the Compare Register latched in the value at Port 0 when the Strobe pin made a low to high transition No further strobes will be available until a read of the Compare Register is made You must read the Compare Register and then clear interrupts so that the latched value in the compare register is not lost To enter Strobe mode set bits 4 3 of the DIO Control register to 01 Wake on aDIO The aDIO Strobe Match and Event interrupt can be used to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 Wake from aDIO will work as long at 5V Standby power is applied to the board To use the aDIO to wake the system Wake from aDIO must first be enabled in the BIOS setup utility Then the aDIO is configured in the appropriate interrupt mode The Wake Enable bit is then set in the Wake Control Register at 0x9C4 The CPU can then be placed in a standby mode and the aDIO interrupt will wake the system During system standby a 32kHz clock is used for the aDIO instead of an 8 33 MHz clock Therefore transitions must be at least 30 us in order to trigger a wake even
38. Watchdog 0 Watchdog Select Interrupt Select Reset time timer is interrupt is time for for WDT disabled disabled WDT 00 2 00s 1 Watchdog is 1 Watchdog 00 0 25s 01 0 505 armed and interrupt is 01 lt 0 50s 10 lt 0 75s can generate enabled 10 0 755 11 1 005 resets and 11 1 005 interrupts Reading the Runtime Register also refreshed the watchdog timer 56 CMV34M cpuModule BDM 610000077 Rev A Thermal Management The cpuModule has several thermal features which can be used to monitor and control the board s temperature when extreme operating conditions are prevalent Thermal Monitor The Intel Thermal Monitor is a feature on the CMV34M that automatically throttles the CPU when the CPU exceeds its thermal limit The maximum temperature of the processor is defined as the temperature that the Thermal Monitor is activated The thermal limit and duty cycle of the Thermal Monitor cannot be modified EN Note The CPU and PCB temperatures displayed in the BIOS are approximate and should not be used to validate a cooling solution Fan Mode The CPU fan can be controlled by the CPU when connected to the switched fan power connector CN15 Three fan modes are supported which can be toggled in the BIOS setup When the fan is not always on the CPU s power consumption is reduced and the life of the fan is increased Always On When in this mode the fan is always powered by the CPU e On At 70C This mode allows the s
39. ad write bit direction programmable register A particular bit can be set to input or output A read of an input bit returns the value of port 0 A read of an output bit returns the last value written to Port 0 A write to an output bit sends that value to port 0 Table 38 Port 1 Data l O Address 9C1h D7 D6 D5 D4 D3 D2 D1 Do Reserved Reserved Reserved Reserved 1 3 1 2 1 1 P1 0 Port 1 Data register is a read write byte direction programmable register A read on this register when it is programmed to input will read the value at the aDIO connector write on this register when it is programmed as output will write the value to the aDIO connector A read on this register when it is set to output will read the last value sent to the aDIO connector Table 39 Multi Function I O Address 9C2h D7 D6 D5 D4 D3 D2 D1 00 The multi function register is read write register whose contents are set by the DIO Control register See the DIO Control register description for a description of this register 50 CMV34M cpuModule BDM 610000077 Rev A Table 40 DIO Control I O Address 9C3h Read Access D7 D6 D5 04 03 02 D1 00 Strobe 0 Status Strobe 1 Status 0 no strobe 0 strobe 1 strobe 1 strobe Digital IRQ Mode Multi Function 00 Disabled Register Select Digital IRO Status 01 strobe Mode Port 1 Direction 00 clear mode 0 no digital interrupt 10 event mode 0 input 01 port 0 direction 1 digital interrupt 11
40. al Authorization number This limited warranty does not extend to any products which have been damaged as a result ofaccident misuse abuse such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of god or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do
41. amount of time shown in Table 54 for the desired recovery mode 5 Release the reset button allowing the system to boot Table 54 Reset Button Recovery Modes Hold Time Mode 0 4 seconds No recovery mode System will stay in reset while button is pressed 4 8 seconds Load Default BIOS Settings 8 12 seconds Serial POST Code Output 12 seconds BIOS Boot Block Recovery Load Default BIOS Settings Loading BIOS defaults allows recovery from an incorrectly configured display device incorrect boot options and many other incorrect settings It is also a good starting point when making BIOS changes After restoring defaults the BIOS settings should be reviewed and modified as needed The default BIOS can be restored either by using Reset Button Recovery or the Load Defaults option in the BIOS Serial Power On Self Test POST Code Output The POST Codes represents a series of events that take place in a system during the Power On Self Test If the POST fails the system will not boot as expected Knowing which POST code the failure occurred may help system debug This recovery mode configures serial port connector CN7 as dual RS 232 and sends the POST codes on the second port i e pin 7 is the transmit pin The port settings are 115kbps 8 bits no parity one stop bit When using this recovery mode the POST codes can be logged on another computer running terminal software Contact RTD technical support for more details BIOS Boot B
42. and Match mode will not generate an interrupt This register is used by Event and Match modes Compare Register A Read Write register used for Match Mode Bit values in this register that are not masked off are compared against the value on Port 0 A Match or Event causes bit 6 of DIO Control to be set and if the aDIO is in Advanced interrupt mode the Match or Event causes an interrupt BDM 610000077 Rev Chapter 4 Using the cpuModule 51 Table 43 Wake Control I O Address 9C4h 07 06 05 04 03 02 D1 DO Reserved Int Mask Wake Enable 1 Interrupt is masked 1 Interrupt triggers a Wake Event O Interrupt is enabled O Interrupt does not trigger a wake event Port 1 Data register is a read write byte direction Interrupts In order to use an interrupt with aDIO the interrupt must first be selected in the BIOS setup utility under Advanced I O Devices aDIO Configuration aDIO Interrupt The Digital I O can use interrupts 3 5 6 7 10 11 and 12 The interrupt must also be reserved so that is it not assigned to PCI devices To reserve the interrupt enter the BIOS under PCIPnP and change the interrupt you wish to use to Reserved Then select the appropriate interrupt mode in the DIO Control register Also verify that the Int Mask bit is cleared in the Wake Control register Advanced Digital Interrupts There are three Advanced Digital Interrupt modes available These three modes are Event Match and Strobe The use of these thre
43. are especially slow This does not affect the actual boot time of the CPU However the CPU may boot before the monitor powers on NVRAM Updates System configuration data is stored in the onboard NVRAM When the system configuration changes this information must be updated If an update is necessary it will happen at the end of POST the BIOS will display an Updating NVRAM message The NVRAM update takes a few seconds and increases the boot time Once the NVRAM is updated boot times will return to normal NVRAM updates only happen when the system configuration changes They do not happen spuriously They are usually triggered by adding or removing a PCI device from a stack Updates can also be triggered by altering the Plug n Play configuration of the BIOS Boot Device Order The BIOS contains a list of devices to try booting from If you wish to boot to a particular device for example hard drive make sure that it is first in the boot order This will speed up boot times BDM 610000077 Rev A Chapter 4 Using the cpuModule 63 System Recovery Reset Button Recovery The CMV34M provides several methods for recovering from an incorrectly configured system In order to enter the recovery mode follow the steps below 1 Remove power from the system including standby power 2 Press and hold the reset button attached to the Utility Connector 3 Apply power to the system while continuing to hold the reset button 4 Wait the
44. btain Technical Support If after following the above steps you still cannot resolve a problem with your CMV34M cpuModule please gather the following information e cpuModule model BIOS version and serial number e List of all boards in system e List of settings from cpuModule Setup program e of autoexec bat and config sys files if applicable e Description of problem e Circumstances under which problem occurs Then contact RTD Technical Support Phone 814 234 8087 Fax 814 234 5218 E mail techsupportGrtd com 74 CMV34M cpuModule BDM 610000077 Rev A AppendixC IDAN Dimensions and Pinout cpuModules like all other PC PCI 104 modules can be packaged in Intelligent Data Acquisition Node IDAN frames which are milled aluminum frames with integrated heat sinks and heat pipes for fanless operation RTD modules installed in IDAN frames are called building blocks IDAN building blocks maintain the simple but rugged stacking concept of PC 104 and PC 104 Plus Each RTD module is mounted in its own IDAN frame and all connections are brought to the walls of each frame using standard PC connectors No connections are made from module to module internal to the system other than through the PC 104 bus enabling quick interchangeability and system expansion without hours of rewiring and board redesign The CMV34M cpuModule can also be purchased as part of a custom built HiDAN or HiDANplus High Reliabilit
45. bus Typically ifa peripheral module has both PCle and PCI bus connectors only the PCle is active and the PCI is pass through The following is a list of rules to use to determine the stack order 1 wo By The PCle connectors above and below the CPU have completely separate signals Therefore it is possible to attach boards to the PCle connector above and below the CPU Any board that uses a PCle or SATA link must be within six boards of the CPU Any board that uses a USB 3 0 link must be within four boards of the CPU Any board that uses a USB 3 0 link must be closer to the CPU than any board that uses a USB 2 0 link To preserve power integrity it is recommended that there be no more than six boards between the CPU and the power supply In order to maintain maximum performance over the full temperature range it is recommended that a PCle spacer be used between the CPU and any board immediately above it A maximum of four PCI boards may be attached to any PCI bus The PCle to PCI bridge must be at one end of the PCI bus segment and all of the peripheral cards at the other end There may be up to eight PCI pass through connectors between the PCle to PCI bridge and the peripheral cards There must be no more than two boards between the first PCI peripheral and the last PCI peripheral If there are four PCI peripheral cards in a PCI bus segment there may not be any PCI pass through connections between them 16
46. cally This feature can be enabled or disabled in the BIOS When enabled the feature can be set to several different modes which are described below Disabled The processor speed is set to its maximum operating frequency e Enabled The processor speed is controlled by the operating system Advanced Configuration and Power Interface ACPI The cpuModule supports several different ACPI low power modes including the S1 S3 S4 and SS sleeping states The BIOS setup utility provides an option to select between S1 and S3 as the Standby state Sleep modes S4 and 55 are setup by the operating system The cpuModule s ACPI suspend modes are described below 51 Power on Suspend The 51 low power state consumes the most power of all supported ACPI sleep modes In this mode the CPU stops executing instructions but power to the CPU and RAM is maintained e 53 Suspend to RAM Everything in the system is powered off except for the system memory When the system wakes from this mode operating systems allow applications to resume where they left off as the state of the application is preserved in memory 54 Hibernate When the system enters this state the operating system will save the current state of applications and relevant data to disk thus allowing the system RAM to be powered down e S5 Soft Off The system is in a soft off state and must rebooted when it wakes Power Button Modes The soft power button input
47. ced Intel SpeedStep Technology and dynamic FSB freguency switching Core 2 Duo only Enhanced Intel Dynamic Acceleration Technology and Enhanced Multi Threaded Thermal Management Core 2 Duo only Supports enhanced Intel Virtualization Technology Core 2 Duo only 45 nm process e 1 GB or 2GBytes BGA DDR2 SDRAM Dual channel memory interface Up to 800MHz Data Rate per channel Surface Mounted for maximum reliability e Stackable 156 PCle 104 Type 2 bus on top Four PCI Express x1 Lanes Two PCI Express x4 Lanes Two SATA 2 0 Two USB 2 0 Two USB 3 0 High Speed shared with USB 2 0 links SMBus e Stackable 156 pin PCle 104 Type 2 bus on bottom Four PCI Express x1 Lanes Two PCI Express x4 Lanes One SATA 2 0 Two USB 2 0 Two USB 3 0 High Speed shared with USB 2 0 links SMBus Advanced Thermal Management Thermal Monitor throttles processor and memory to prevent thermal runaway Auto Fan Control only runs fan when needed SMBus Temperature Monitor for CPU and board temperature Mini Fan Heatsink with Auto Fan control Passive Structural Heatsink amp Heatpipes in IDAN and HiDAN System Configurations e Advanced Programmable Interrupt Controller APIC 24 interrupt channels with APIC enabled 15 in legacy PIC mode High Precision Event Timer e Advanced Configuration and Power Interface ACPI BDM 610000077 Rev A Chapter 1 Introduction 5 ACPI 3 0 Compliant Supported power down modes 51 Powe
48. e Core 2 Duo processor or a single core Celeron M processor The Core 2 Duo processor features Enhanced Intel SpeedStep technology which enables real time dynamic switching between multiple voltage and freguency points This results in optimal performance without compromising low power A dual channel DDR2 memory interface operating at up to 800 MHz ensures adeguate memory bandwidth to keep up with both processors All memory chips soldered directly onto the board The video interface is provided by an Analog SVGA output The two outputs are independent and can display separate images and display timings Maximum resolution is 2048 x 1536 High speed peripheral connections include USB 2 0 with up to 480 Mb sec data throughput A Serial ATA SATA controller provides a fast 3 0 Gbps connection to the hard drives Network connectivity is provided by an integrated 10 100 1000 Mbps Ethernet controller Other features include two RS 232 422 485 COM ports and Advanced Digital I O aDIO RTD has gone the extra mile to include additional advanced features for maximum flexibility These include a SATA Disk Chip socket that allows flash drive with a standard SATA interface to be attached to the board either socketed or soldered An Advanced Watchdog Timer is provided that can generate an interrupt or reset when the timer expires SDRAM is soldered directly to the board for high vibration resistance The CMV34M is also available in a rugged fanless
49. e a standby power to wake the system will not be fully supported ATX power supplies do provide a standby power thus allowing the system to utilize all low power modes supported by the hardware When an ATX supply is used to power the cpuModule lower power modes can be achieved During these low power modes the standby power from the ATX power supply provides power to a small circuit on the CPU which is used to watch for a system wake event ATX Power Supply Signals The auxiliary power connector CN3 provides two ATX style signals 5V Standby and PSON The 5V Standby rail is used to power certain parts of the cpuModule when the main power supply is turned i e during Suspend to RAM 53 Hibernate 54 or Soft Off 55 power modes The PSON signal is an active low open drain output that signals the power supply to turn on Use of these signals allows the power consumption to drop to below 1W during standby modes and still enable any of the wake events Reducing Power Consumption In addition to the CPU s low power modes power consumption can further be reduced by making some modifications to the BIOS setup When the following features are modified the CPU s power consumption will decreases e Speed Setting the processor to its minimum speed in the BIOS will reduce power consumption e Memory Speed Changing the DDR DRAM clock frequency will reduce power consumption however memory performance will also be reduced e
50. e modes is to monitor state changes at the aDIO connector Interrupts are enabled by writing to the Digital IRQ Mode field in the DIO Control register Event Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the event is guaranteed to register Pulses as small as 60 ns can register as an event but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Event mode set bits 4 3 of the DIO Control register to 10 Match Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the match is guaranteed to register Pulses as small as 60 ns can register as a match but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Match mode set bits 4 3 of the DIO Control register to 11 Note Make sure bits 4 3 are set BEFORE writing the DIO Compare register If you do not set them first the contents of the DIO Compare register could be lost because the Event mode latches in Port 0 into the DIO Compare register 52 CMV34M cpuModule BDM 610000077 Rev A CLOCK DIGITAL INPU
51. ections Port 1 Port 2 RXD TXD TXD RXD RXD TXD TXD RXD When using half duplex in RS 485 mode connect the ports as shown in Table 16 Table 16 Half Duplex RS 485 Mode From To Port 1 Port 1 RXD Port 1 TXD Port 1 RXD Port 1 Port 2 RXD Port 1 RXD Port 2 TXD BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 31 RS 422 and RS 485 Mode Pinout Table 17 provides the serial port connector pinout when RS 422 or RS 485 modes are enabled Table 17 Serial Port in RS 422 485 Mode Pin Signal Function In Out DB 9 1 Reserved 1 2 Reserved 6 3 RXD Receive Data in 2 4 TXD Transmit Data out 7 5 TXD Transmit Data out 3 6 RXD Receive Data in 8 7 Reseved 4 8 Reseved 9 9 10 GND Signal Ground out 5 Facing the serial port connector the pinout is 9 7 5 3 1 software control The transmitters are enabled by manipulating the Request Send RTS signal the Note When using the serial port in RS 485 mode the serial transmitters are enabled and disabled under serial port controller This signal is controlled by writing bit 1 of the Modem Control Register MCR as follows e f MCR bit 1 then RTS 0 and serial transmitters are disabled e f MCR bit 0 then RTS 1 and serial transmitters are enabled Note For more information on the serial port registers i
52. es or other peripherals to the system you must ensure they do not use interrupts needed by the cpuModule or malfunctions will occur The CMV34M cpuModule supports the standard PC interrupts listed in Table 35 Interrupts not in use by hardware on the cpuModule itself are listed as available Similarly if the operating system is using APIC more IRGs will be available Table35 Hardware Interrupts Used on the CMV34M cpuModule Interrupt Normal Use 0 Timer 0 1 Keyboard 2 Cascade of IRQ 8 15 3 COM2 4 COM1 5 Available 6 Available 7 Available 8 Real Time Clock 9 Available routed to IRO 2 10 Available 11 Available 12 Mouse 14 SATA hard disk 15 SATA Disk Chip socket 1 IRQs 14 and 15 may be available if the SATA controller is not configured in Compatability Mode Will claim an IRQ line that is required by a legacy device To reserve an IRQ for a legacy device refer to the Note The cpuModule has onboard PCI devices that will claim IRQ lines In some instances a PCI device PnP PCI Configuration Setup fields in the BIOS Note A devices hardware interrupt will be available for use if the given device is not present in the system and the device is disabled in Setup 48 cpuModule BDM 610000077 Rev A Non Standard Serial Port Modes It is possible to change the input clock rate for the UARTs of the cpuModule by selecting the Serial Port Baud Rates option in the Serial Port C
53. f a system is dependent upon numerous system settings as well as devices attached to a system This section addresses some devices and settings that can increase or decrease a system boot time Ouick Boot The BIOS contains a Ouick Boot option that minimizes the boot time of the system Ouick Boot eliminates the exhaustive tests that are performed during Power On Self Test POST while maintaining the functionality of the board By enabling the Ouick Boot feature your system can achieve 5 second boot times Add On Cards With BIOS Extensions Some add on cards have an integrated BIOS extension The most common examples are SCSI controllers and network cards with boot ROMs During POST the BIOS executes the card s extension code This extension code is third party code which is beyond RTD s control The BIOS extension will most likely increase the boot time Exactly how much it increases boot time will depend on the particular card and firmware version VGA Controller VGA controllers have a VGA BIOS that must be initialized during POST It can take some time to initialize the VGA BIOS Exactly how long will depend on the particular VGA controller and BIOS version Hard Drive Type During Hard Drive initialization each device must be probed Some devices take longer to probe 2 5 inch hard drives tend to take longer than 3 5 inch ones because they spin at a lower RPM Monitor Type Some monitors take a while to power on Desktop flat panels
54. ical configuration and the actual devices may change based on BIOS settings Table 56 Onboard PCI Devices BDM 610000077 Rev A Device ID Vendor ID Description 2A40 8086 Host Bridge 2A41 8086 PCI to PCI Bridge PCle x16 2A42 8086 Primary Display Controller 2A43 8086 Secondary Display Controller 10F5 8086 Ethernet Controller CN20 2937 8086 USB UHCI 4 2938 8086 USB UHCI 5 2939 8086 USB UHCI 6 293C 8086 USB EHCI 2 2940 8086 PCI to PCI Bridge PCle 104 x1 41 2942 8086 PCI to PCI Bridge PCle 104 x1 2 2944 8086 PCI to PCI Bridge PCle 104 x1 43 2946 8086 PCI to PCI Bridge PCle 104 x1 4 2948 8086 PCI to PCI Bridge to Shared Links 2934 8086 USB UHCI 1 2935 8086 USB UHCI 2 2936 8086 USB UHCI 3 293A 8086 USB EHCI 1 2917 8086 LPC Bridge 2928 8086 SATA Controller 2930 8086 SMBus Controller 292D 8086 SATA Controller 8509 10B5 PCI to PCI Bridge Shared Link x1s 8624 10B5 PCI to PCI Bridge x4s 8241 104C USB 3 0 xHCI Controller Appendix A Hardware Reference 67 Physical Dimensions Figure 8 shows the mechanical dimensions of the CMV34M cpuModule o 0551 0000 0 0920 ES 28 s ums m Figure 8 CMV34M Physical Dimensions 0 005 inches 68 CMV34M cpuModule BDM 610000077 Rev A Board Spacing In order to facilitate larger heatsink solutions the CMV34M is designed to use a 22mm standoff between it and the board above it The PCle 104
55. is mode enabled the serial port connectors must be connected to RS 232 compatible devices Table 14 provides the serial port connector pinout and shows how to connect to an external DB 25 or DB 9 compatible serial connector Table 14 Serial Port in RS 232 Mode Pin Signal Function In Out DB 25 DB 9 1 DCD Data Carrier Detect in 8 1 2 DSR Data Set Ready in 6 6 3 RXD Receive Data in 3 2 4 RTS Reguest To Send out 4 7 5 TXD Transmit Data out 2 3 6 CTS Clear To Send in 5 8 7 DTR Data Terminal Ready out 20 4 8 RI Ring Indicate in 22 9 9 10 GND Signal Ground 7 5 30 cpuModule BDM 610000077 Rev A Facing the serial port s connector pins the pinout is RS 422 or RS 485 Serial Port You may use Setup to configure the serial ports as RS 422 or RS 485 In this case you must connect the serial port to an RS 422 or RS 485 compatible device When using RS 422 or RS 485 mode you can use the serial ports in either half duplex two wire or full duplex four wire configurations For half duplex 2 wire operation you must connect RXD to TXD and connect RXD to TXD EN Note The cpuModule has a 120 2 termination resistor Termination is usually necessary on all RS 422 receivers and at the ends of the RS 485 bus Termination resistors can be enabled in the BIOS setup utility When using full duplex typically in RS 422 mode connect the ports as shown in Table 15 Table 15 Full Duplex Conn
56. lock Recovery This recovery mode allows you to re load a BIOS that has been corrupted The BIOS can be loaded from a file on a USB key or other removable drive In order for this to work the boot block of the BIOS must still be intact Contact RTD tech support for more details 64 CMV34M cpuModule 610000077 Rev A Appendix A Hardware Reference This appendix provides information on CMV34M cpuModule hardware including Jumper Settings and Locations page 66 Onboard PCI PCle Devices page 67 Physical Dimensions page 68 BDM 610000077 Rev A Appendix A Hardware Reference 65 Jumper Settings and Locations Many cpuModule options are configured by positioning jumpers Jumpers are labeled on the board as JP followed by a number Figure 7 shows the jumper locations that are used to configure the cpuModule Table 55 lists the jumpers and their settings JP5 Apacer Figure 7 CMV34M Jumper Locations top side Table 55 CMV34M Jumpers Jumper Pins Function Default JP5 2 Reserved open JP6 2 Used to disable the Bus Stacking Error detection See PCle 104 Type 2 Compatibility open on page 40 pins 1 2 Disable Bus Stacking Error detection open Enable Bus Stacking Error detection normal operation 66 CMV34M cpuModule BDM 610000077 Rev A Onboard PCI PCle Devices The CMV34M cpuModule has several onboard PCI PCle devices all of which are listed in the table below This table shows a typ
57. n 0 5 2 4 V 0 0 V 2 4 V 0 0 V 2 0 V 0 3 V 5 0 V 10 0 V 2 4 V 25 V 2 0 V 1 5 V 0 0 V 0 3 V 25 V 2 4 V 0 0 V 2 0 V 0 5 V Max 5 0A 3 3 V 0 5 V 3 3 V 0 4 V 5 5 V 0 8 V 500 mA 10 0 V 5 0 V 25 V 0 8 V 6 0 V 6 0 V 3 0 V 0 3 V 25 V 3 3 V 0 4 V 5 5 V 0 8 V 500 mA 10 CMV34M cpuModule BDM 610000077 Rev A BDM 610000077 Rev A Table4 Electrical Characteristics Symbol Parameter Test Condition Min Max Utility Port Connector CN5 Verc Input RTC Voltage 2 0V 3 6 V Utility Supply 500 mA Current 1 Maximum DC undershoot below ground must be limited to either 0 5V or 10mA During transitions the device pins may undershoot to 2 0V or overshoot to 7 0V provided it is less than 10ns with the forcing current limited to 200 mA 2 Only required to maintain date and time when power is completely removed from the system Not required for board operation Chapter 1 Introduction 11 Contact Information RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Phone 1 814 234 8087 Fax 1 814 234 5218 E mail sales rtd com techsupport rtd com Internet http www rtd com 12 CMV34M cpuModule BDM 610000077 Rev A Chapter 2 Getting Started For many users the factory configuration of the CMV34M cpuModule can be used to get a PC 104 system operational You can get your system up and
58. ncluding the MCR refer to the Serial Port Programming reference in Appendix D 32 CMV34M cpuModule BDM 610000077 Rev A Dual Serial Port Modes The serial port connectors can be configured as dual serial ports in the BIOS The mapping between the connectors and COM port numbers is shown in Table 18 The supported combinations of serial port modes are listed in Table 19 which also includes a reference to the corresponding connector pinout Table 18 Dual Serial Port Connections Connector COMA COMB CN7 COM 1 COM 3 CN8 COM 2 COM 4 Table 19 Dual Serial Port Modes COMA COM B Pinout Reference RS 232 RS 232 Table 20 RS 422 RS 232 Table 21 RS 422 RS 422 Table 22 RS 485 RS 232 Table 21 RS 485 RS 485 Table 22 Table 20 COMA RS 232 and COM B RS 232 Pin Signal Function In Out DB 9 1 DCD1 COM A Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 RTS1 COM A Request To Send out 7 5 TXD1 COM A Transmit Data out 3 6 CTS1 COM A Clear To Send in 8 7 TXD2 COM B Transmit Data out 4 8 Ring Indicate in 9 9 10 GND Signal Ground 5 BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 33 34 cpuModule Table21 RS 422 485 and RS 232 Pin Signal Function In Out DB 9 1 DCD1 COM A Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM
59. nected backwards verify all cables are connected correctly cpuModule keeps rebooting problem with power supply reset switch is on watchdog timer is not being serviced guickly enough check for correct power on the PC 104 Plus PCI bus connector check that the reset button is not pushed in verify that the watchdog timer is being refreshed before it times out cpuModule will not boot from particular drive or device erratic operation device not bootable use sys command on drive or reformat the device using the s switch device not formatted power not connected to boot drive excessive bus loading format drive using s switch connect power cable to floppy or hard drive reduce number of modules in stack remove termination components from bus signals remove any power supply bus terminations power supply noise power supply limiting examine power supply output with oscilloscope glitches below 4 75 VDC will trigger a reset add bypass caps examine power supply output with oscilloscope check for voltage drop below 4 75 VDC when hard drive or floppy drive starts add bypass caps insufficient cabling through power connector increase wire gauge to connector power through bus connectors temperature too high add fan processor heatsink or other cooling device s See Thermal Management on page 57 memory address conflict check for two hardware devices e g Ethernet SSD Arcnet
60. nized as follows Chapter 1 Introduction introduces main features and specifications Chapter 2 Getting Started provides abbreviated instructions to get started guickly Chapter 3 Connecting the cpuModule provides information on connecting the cpuModule to peripherals Chapter 4 Using the cpuModule provides information to develop applications for the cpuModule including general cpuModule information detailed information on storing both applications and system functions and using utility programs Appendix A Hardware Reference lists jumper locations and settings physical dimensions and processor thermal management Appendix B Troubleshooting offers advice on debugging problems with your system Appendix IDAN Dimensions and Pinout provides connector pinouts for the cpuModule installed in an RTD Intelligent Data Acguisition Node IDAN frame AppendixD Additional Information lists sources and websites to support the cpuModule installation and configuration Appendix E Limited Warranty BDM 610000077 Rev A Chapter 1 Introduction 1 CMV34M cpuModules RTD s CMV34M cpuModule represents the latest in high performance energy efficient embedded computing solutions Based on the Intel Montevina platform it features a 64 bit Penryn processor coupled with a GS45 chipset It includes a source synchronous Front Side Bus FSB operating up to 1066 MHz and up to 6 MB of L2 cache This cpuModule is available either with a dual cor
61. not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Website www rtd com BDM 610000077 Rev Appendix E Limited Warranty 85 86 CMV34M cpuModule BDM 610000077 Rev A
62. of the utility port connector CN5 can be configured by the operating system as a suspend button transition to S1 or S3 or as soft power button transition to S5 Consult your operating system documentation for information on how to configure it The power button will always cause a transition to S5 if pressed for 4 seconds or longer without interaction from the operating system Low Power Wake Options The cpuModule supports several methods of waking from a low power state Several of these wake options are BIOS configurable and can be accessed directly from the Power menu in the BIOS setup e Resume onaDIO This option allows the system to use an aDIO Strobe Match or Event interrupt to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 For more information refer to the section titled Wake on aDIO on page 53 e Resume on PME When enabled the system can wake when a signal is applied to the PME signal on the PCI bus or the WAKE signal on the PCle bus This includes wake up on onboard LAN controller 58 CMV34M cpuModule BDM 610000077 Rev A e Resume on RTC Alarm The RTC Alarm allows the system to turn on at a certain time every day AT vs ATX Power Supplies Both AT and ATX power supplies may be used with the CMV34M cpuModule however AT power supplies do not provide any standby power to the cpuModule When an AT power supply is used to power the system low power modes that reguir
63. on and wear a grounded wrist strap Remove power from the system Insert the Disk Chip in the SATA Disk Chip Socket U6 aligning pin 1 with the square solder pad on the board Apply power to the system Re enter the BIOS and set the boot order of the system accordingly BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 29 Serial Port 1 CN7 and Serial Port 2 CN8 Serial Port 1 COM1 is implemented on connector 7 and Serial Port 2 is implemented on connector CN8 The serial ports are normally configured as PC compatible full duplex RS 232 ports but you may use the BIOS Setup program to reconfigure these ports as half duplex RS 422 or full duplex RS 422 or RS 485 If you reconfigure the ports you must also select the address and corresponding interrupt using Setup Table 13 provides the standard I O addresses and corresponding interrupts Table 13 Serial Port Settings 1 O Address hex IRQ 03F8 IRQ4 02F8 IRQ3 03E8 IRQ4 02E8 IRQ3 Serial Port UART The serial ports are implemented with a 16550 compatible UART Universal Asynchronous Receiver Transmitter This UART is capable of baud rates up to 115 2 kbaud in 16450 and 16550A compatible mode and includes a 16 byte FIFO Refer to any standard PC AT hardware reference for the register map of the UART For more information about programming UARTs refer to Appendix D RS 232 Serial Port Default The default serial port mode is full duplex RS 232 With th
64. onfiguration menu of the BIOS Setup Changing the option from Normal to Non Standard will allow the serial port to operate at higher speeds This transforms bits 7 5 of the Divisor Latch High Byte of the UART into selections for alternate clock rates The following table describes the bit operations and the resulting divide by one baud rate Table36 Divisor Latch High and Low Bytes Divisor Latch High Byte Divisor Baud Rate Error Latch Low Bit7 Bit 6 Bit 5 Bits 4 0 Byte 0 0 0 0x00 0x01 115 200 0 16 1 0 0 0x00 0x01 460 800 0 16 1 1 0 0x00 0x01 921 600 0 16 0 0 1 0x00 0x01 1 500 000 0 16 To achieve non standard baud rates divide the baud rate you require by one of the non standard divisors 460 800 921 600 and 1 500 000 If the result is a whole number substitute that value for the Divisor Latch Low Byte For example to achieve a baud rate of 750 000 select the Divisor Latch High Byte for 1 500 000 and set the Divisor Latch Low Byte to 2 Note The signaling mode of the output will limit the highest baud rate achievable For RS 232 mode EN the maximum suggested baud rate is 230 400 For 422 485 modes the maximum is 1 500 000 Note When using the non standard high speed serial port modes it is highly recommended to use hardware flow control whenever possible BDM 610000077 Rev A Chapter 4 Using the cpuModule 49 Advanced Digital I O Ports aDIO This board supports 12 bits of TTL CMOS compatible digital TTL signaling
65. ory Mapo si te borne tal 46 I O Address Map eere ned ee ced nea niente LE DERE RERUM RU NEQNE ka UE 47 Hardware Interr pts ob pb Pinte nji DES 48 Non Standard Serial Port Modes 49 Advanced Digital I O Ports aDIO 50 Digital I O Register Sesanje E OEE EE E EAS Cope od TER RR DT 50 Port 1 Data register is a read write byte direction 52 chins 52 Advanced Digital Interrupts ai ne 52 Event Ho P b dune da O lead 52 Mateh aides ne Me ib O bih ite 52 Strobe MOE M T 53 MELIA 53 Real Time Clock Control tans ET ARA RET 54 OVERVIEW Festes ed eoe E tope pa da RR 54 Accessing the Eee ka p E ORE 54 Watchdog Timer Control HH meme eme 56 Thermal Manageiient noni ia bobi 57 Thermal SOSA ILE 57 CMV34M cpuModule BDM 610000077 Rev A PUE Further Temperature Reduction
66. outine then attempts to restart the application software If it is successful the application is restarted in much less time than a full reboot would require If it is not successful the system is rebooted Due to system latency it is recommended that the Watchdog be refreshed at about half of the reset time out period or half of the interrupt time out period whichever is applicable Register Description The Advanced Watchdog Timer has a Setup Register and a Runtime Register The Setup Register is set by the BIOS and can be adjusted by entering the BIOS Setup Utility and going to Advanced Miscellaneous RTD Features The Setup Register may also be read by the driver to determine if the Watchdog is enabled and the interrupt and base address that it is using EN Note Enabling the watchdog timer in the BIOS does not actually arm it The watchdog timer can be armed by accessing l O address 985h as explained below Table 46 Advanced Watchdog Setup Register 98Bh 07 06 05 04 03 02 D1 00 Reserved WDT IRO Reg Enable Select Interrupt for WDT O lt Watchdog timer is disabled and 000 Disabled Runtime Register will not appear 001 IRO5 in I O map 010 lt IRO7 1 Watchdog Timer is enabled 011 IRQ10 Runtime Register will appear in 100 IRQ11 map 101 IRQ12 110 Reserved 111 Reserved Table 47 Advanced Watchdog Runtime Register 985h D7 D6 05 04 03 02 D1 DO WDT_Active WDT_IRQ_Ena Reserved WDT IRO Time WDT RST Time 0
67. p You can run Setup by rebooting the cpuModule and repeatedly pressing the Delete key When you are finished with Setup save your changes and exit The system will automatically reboot Field Selection To move between fields in Setup use the keys listed below Table31 Setup Keys Key Function Move between fields PgUp PgDn Selects next previous values in fields Enter Go to the submenu for the field Esc To previous menu then to exit menu 44 CMV34M cpuModule BDM 610000077 Rev A Main Menu Setup Fields The following is a list of Main Menu Setup fields Table 32 Main Menu Setup Fields Field Active Keys Selections Main Press Enter to select Access system information such as BIOS version EPLD version and CMOS time and date settings Advanced Press Enter to select Setup advanced cpuModule features PCIPnP Press Enter to select Set PnP and PCI options and control system resources Boot Press Enter to select Set the system boot sequence Security Press Enter to select Setup the supervisor and user access passwords or enable boot sector virus protection Power Press Enter to select Control power management settings including power supply type and system wake functions Thermal Press Enter to select Monitor the cpuModule temperature or activate thermal or fan modes Exit Press Enter to select Save or discard changes and exit the BIOS or load the default BIOS settings
68. page 50 Real Time Clock Control page 54 Watchdog Timer Control page 56 Thermal Management page 57 Power Management page 58 Multi Color LED page 60 Reset Status Register page 61 Features and Settings That Can Affect Boot Time page 63 System Recovery page 64 BDM 610000077 Rev Chapter 4 Using the cpuModule 43 The RTD Enhanced AMI BIOS The RTD Enhanced AMI BIOS is software that interfaces hardware specific features of the cpuModule to an operating system OS Physically the BIOS software is stored in a Flash EPROM on the cpuModule Functions of the BIOS are divided into two parts The first part of the BIOS is known as POST power on self test software and it is active from the time power is applied until an OS boots begins execution POST software performs a series of hardware tests sets up the machine as defined in Setup and begins the boot of the OS The second part of the BIOS is known as the CORE BIOS It is the normal interface between cpuModule hardware and the OS which is in control It is active from the time the OS boots until the cpuModule is turned off The CORE BIOS provides the system with a series of software interrupts to control various hardware devices Configuring the RTD Enhanced AMI BIOS The cpuModule Setup program allows you to customize the cpuModule s configuration Selections made in Setup are stored on the board and are read by the BIOS at power on Entering the BIOS Setu
69. port programmable as input or output Event Mode Interrupt generates an interrupt when any input bit changes 6 CMV34M cpuModule BDM 610000077 Rev Match Mode Interrupt generates an interrupt when input bits match a preset value External Strobe Mode latches 8 data inputs and generates and interrupt Two Strobes can be configured as readable inputs Two USB 2 0 Universal Serial Bus Ports Supports 480 Mb s high speed 12Mb s full speed and 1 5Mbs low speed peripherals 500 mA 5 provided per port USB Boot capability Serial ATA SATA with RAID support Transfer rate up to 3Gb sec Integrated AHCI controller RAID 0 and 1 supported through Intel Matrix Storage Technology Compatability mode supports legacy operating systems SATA Disk Chip Socket Miniature SATA Flash Disk Chip Capacities up to 32GB Natively supported by all major operating systems Utility port PC AT compatible keyboard port PS 2 Mouse Port Speaker port 0 1W output Hardware Reset input Soft Power Button input Battery input for Real Time Clock Power I O ATX Power signals RTD Enhanced AMI BIOS User configurable using built in Setup program Nonvolatile storage of CMOS settings without battery Boot Devices Standard Devices floppy disk hard disk etc SATA Disk Chip USB Device Network FailSafe Boot ROM e Surface mount Flash chip that holds ROM DOS Quick Boot mode 1
70. r On Suspend S3 Suspend to S4 Hibernate and S5 Soft Off CPU Clock Throttling and Clock Stop for to Support Wake events include aDIO Interrupt e Wake on LAN e Real Time Clock e COM port Ring e Power Switch e etc e Network Boot supported by Intel PXE e Y2K compliant Real Time Clock external battery required e Nonvolatile storage of CMOS settings without battery Advanced Watchdog timer e Complete PC compatible Single Board Computer e SVGA controller Onboard with 3D Acceleration Intel Graphics Media Accelerator 4500MHD Generation 5 0 graphics engine with 10 cores Dynamic Video Memory up to 256MB DirectX 10 Support Supports Windows Vista Aero Glass Effects Analog SVGA Output e Gigabit Ethernet Intel 82567LM PHY ICH9M Controller PRO1000 Series 10 100 1000 Auto negotiation Jumbo Frame Support 9kB PXE network Boot Smart Speed operation for automatic speed reduction on faulty cable plants Automatic MDI MDI X crossover capable Software configurable RS 232 422 485 serial ports 16550 compatible UARTs for high speed 120 Ohm Termination resistors for RS 422 485 through BIOS Configuration Eachserial port connector can be configured as two limited serial ports for a total of four serial ports Fully jumperless configuration e Advanced Digital I O aDIO One 8 bit bit programmable I O with Advanced Digital Interrupt Modes 4 bit
71. reboot Note You may miss the initial sign on messages if your monitor takes a while to power on Note By default cpuModules are shipped with Fail Safe Boot ROM enabled When Fail Safe Boot ROM is enabled the system will boot to it exclusively BDM 610000077 Rev A Chapter 2 Getting Started 19 20 cpuModule BDM 610000077 Rev A Chapter 3 Connecting the cpuModule This chapter provides information on all CMV34M cpuModule connectors Proper Grounding Technigues page 22 Connector Locations page 22 Auxiliary Power CN3 page 24 Utility Port Connector CN5 page 25 SVGA Video Connector CN18 page 28 SATA Disk Chip Socket U6 page 29 Serial Port 1 CN7 and Serial Port 2 CN8 page 30 Advanced Digital aDIO Port CN6 page 35 USB 2 0 Connector CN17 page 36 Ethernet 10 100 1000Base T and TX Connector CN20 page 37 PCle 104 Type 2 Bus CN1 Top and CN2 Bottom page 38 Optional RTC Battery Input CN13 page 42 Fan Power Switched CN15 page 42 BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 21 Proper Grounding Technigues Before removing the CMV34M from its static bag proper grounding technigues must be used to prevent electrostatic discharge ESD damage to the cpuModule Common grounding procedures include an anti static mat on a workbench which may connect to an anti static wrist strap also known as an ESD wrist strap on the wrist of the
72. t If the aDIO is to be used for a wake event only and not an interrupt the Int Mask bit can be set in the Wake Control Register This will block the interrupt but still allow a wake event to occur The various settings for Wake Enable and Int Mask are shown in Table 44 below Table 44 Interrupt and Wake Event Generation WakeEnable Int Mask Function 0 0 Interrupt Only 0 1 Interrupt Wake event is generated 1 0 Interrupt and Wake Event 1 1 Wake Event Only BDM 610000077 Rev A Chapter 4 Using the cpuModule 53 Real Time Clock Control Overview The cpuModule is eguipped with a Real Time Clock RTC which provides system date and time functions When the cpuModule is turned off a battery must be attached to the utility connector to provide power to the RTC Without power the RTC will lose the date time information when the system is turned off The RTC also provides an alarm function This may be used to generate an interrupt at a particular time and day This feature is commonly used to wake up the system from Sleep Standby to run a scheduled task defragment the hard drive back up files etc In addition to the date time alarm functions the RTC contains several bytes of battery backed RAM commonly called CMOS memory In typical desktop PC the CMOS memory is used by the BIOS to store user settings This RTD cpuModule uses onboard flash to store user BIOS settings To preserve compatibility with tradi
73. technician or engineer Connector Locations Figure 5 shows the connectors and the SATA Disk Chip socket of the CMV34M cpuModule Ethernet CN20 COM2 amp 4 SVGA Video CN8 CN18 COM1 amp 3 CN7 USB 2 0 CN17 Switched Fan CN15 aDIO CNG H Apacer 5 Multi menm ii Function CN5 d SATA Auxiliary Power PCle Bus Battery Disk Chip CN3 CN1 amp CN2 CN13 U6 Figure 5 CMV34M Connector Locations Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board EN and a square solder pad on the bottom side of the board Pin 1 of the bus connectors match when stacking PC 104 modules 22 CMV34M cpuModule BDM 610000077 Rev A Table 6 CMV34M Basic Connectors BDM 610000077 Rev A Connector Function Size and Pitch Mating Connector CN1 PCle 104 Type 2 Bus Top 156 pin 0 635mm Samtec 5 129646 03 CN2 PCle 104 Type 2 Bus Bottom 156 0 635mm Samtec ASP 129637 03 CN3 Auxiliary Power 1x10 0 1 FCI 65039 027LF CN5 Utility Port 2x5 0 1 3M 89110 0001 CN6 aDIO 2x8 0 1 3M 89116 0001 CN7 Serial Port 1 COM1 amp 3 2x5 0 1 3M 89110 0001 CN8 Serial Port 2 COM2 amp 4 2x5 0 1 3M 89110 0001 CN13 RTC Battery Input optional 1x2 2mm FCI 69305 002LF CN15 Fan Power switched 1x3 2mm FCI 69305 003LF CN17 USB 2 0 2x5 0 1 3M 89110 0001 CN18 Video SVGA 2x5 0 1 3M 89110 0001 CN20 Ethernet 2x5 0 1 3M 89110 0001 U6 SATA
74. ting bolt lengths 76 CMV34M cpuModule BDM 610000077 Rev A External I O Connections BDM 610000077 Rev A Table 58 PS 2 Mouse 6 Pin mini DIN Connector female IDAN Pin Signal Function 1 MDAT Mouse Data 2 Reserved 3 GND Ground 4 5V 45 Volts 5 MCLK Mouse Clock 6 Reserved Table 59 Keyboard 6 Pin mini DIN Connector female IDAN Pin Signal Function 1 KDAT Keyboard Data 2 Reserved 3 GND Ground 4 5 V 5 V 5 KCLK Keyboard Clock 6 Reserved Appendix C Dimensions and Pinout 77 78 CMV34M cpuModule Table 60 COM1 COM2 RS 232 9 Pin D Connector male IDAN Pin Signal Function Mode 1 DCD Data Carrier Detect Input 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 DTR Data Terminal Ready Output 5 GND Ground 6 DSR Data Set Ready Input 7 RTS Reguest To Send Output 8 CTS Clear To Send Input 9 RI Ring Indicator Input Table 61 1 2 RS 422 485 9 D Connector male IDAN Pin Signal Function Mode 1 Reserved 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 Reserved 5 GND Ground 6 Reserved 7 TXD Transmit Data Output 8 RXD Receive Data Input 9 Reserved BDM 610000077 Rev A BDM 610000077 Rev A Appendix C Dimensions and Pinout 79 80 cpuModule Table 62 SVGA 15 Pin High Density D Connector female
75. tional PCs the RTD Enhanced BIOS also mirrors the user settings from flash in CMOS Therefore the contents of CMOS may be overwritten at boot time and should be treated as read only Accessing the RTC Registers You may access the RTC date time and CMOS memory using the Index and Data Registers located at l O addresses 70h and 71h e Address 70h is the Index register It must be written with the number of the register to read or write Valid values are 00h to 7Fh Address 71h is the Data register It contains the contents of the register pointed to by the Index To read write an RTC register you must first set the Index register with the register number and then read write the Data register A list of key RTC registers is shown in Table 45 below Table45 Real Time Clock Registers Registers Registers Function hex decimal 00h 0 RTC Seconds 02h 2 RTC Minutes 04h 4 RTC Hours 06h 6 RTC Day of Week 07h 7 RTC Day of Month 08 8 RTC Month 09h 9 RTC Year 0Ah 10 RTC Status Register A e Bit 7 RTC Update In Progress Read Only RTC registers should not be accessed when this bit is high e Bits 6 4 Divider for 32 768 KHz input should always 010 e Bits 3 0 Rate select for periodic interrupt 54 CMV34M cpuModule BDM 610000077 Rev A Table 45 Real Time Clock Registers Registers Registers Function hex decimal OBh 11 RTC Status Register B e Bit 7 Inhibit Update When high the RT
76. tional RTC battery input is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only reguired to maintain time when power is completely removed from the cpuModule A battery is not reguired for board operation Table 29 Optional Battery Input CN13 Pin Signal Function 1 BAT RTC Battery Input 2 GND Ground WARNING This optional RTC battery connector CN13 should be left unconnected if the utility port connector 5 has a battery connected Fan Power Switched CN15 The switched fan power connector CN15 is an optional fan connector which allows the system to power the fan when the processor temperature reaches high temperatures To utilize this connector refer to the Thermal Management section on page 57 Table 30 Fan Power Switched CN15 Pin Signal Function 1 CPU FAN PWM 5 Volts DC switched 2 GND Ground 3 FAN TACH Fan Tachometer Input 42 CMV34M cpuModule BDM 610000077 Rev A Chapter 4 Using the cpuModule This chapter provides information for users who wish to develop their own applications programs for the CMV34M cpuModule This chapter includes information on the following topics The RTD Enhanced AMI BIOS page 44 Memory Map page 46 1 0 Address Map page 47 Hardware Interrupts page 48 Advanced Digital I O Ports aDIO
77. to indicate an Ethernet connection For more information refer to the Multi Color LED section on page 60 Table 25 Ethernet Connector CN20 RJ 45 Pin 10 Signal Function 3 1 B RX Receive 10 100 6 2 B RX Receive 10 100 4 3 C 5 4 1 5 Transmit 10 100 2 6 Transmit 10 100 7 7 Dt 8 8 D 9 AGND Ethernet Ground 10 AGND Ethernet Ground 9 5 3 1 BDM 610000077 Rev A Chapter 3 Connecting the cpuModule 37 PCle 104 Type 2 Bus CN1 Top and CN2 Bottom Connector CN1 and CN2 carries the signals of the PCle 104 PCle bus These signals match definitions found in the PCI 104 Express amp PCle 104 Specification Version 2 01 from the PC 104 Embedded Consortium Table 26 lists the pinouts of the PC 104 Express bus connector WARNING Not all PCle cards are compatible with the PCle 104 Type 2 connector Be sure that all of the boards attached to this bus are compatible before powering the system 38 CMV34M cpuModule Table 26 PCle 104 2 Bus Signal Assignments View Pin Signal Signal Pin 1 USB PE RSTA 2 3 3 3V 3 3V 4 5 USB_1p USB_Op 6 7 USB_1n USB_On 8 9 GND GND 10 11 PEx1_1Tp PEx1 0Tp 12 13 PEx1 1Tn PEx1 OTn 14 15 GND GND 16 17 PEx1 2Tp PEx1 3Tp 18 19 PEx1 2Tn PEx1 3Tn 20 21 GND GND 22 23 PEx1 1Rp PEx1 ORp 24 25 PEx1 1Rn 2 PEx1_ORn 26 27 GND 2
78. u add any PC 104 modules or other peripherals to the system you must ensure they do not use EN reserved addresses listed below or malfunctions will occur The exception to this is if the resource has been released by the user Table 34 lists I O addresses reserved for the CMV34M cpuModule Table 34 1 0 Addresses Reserved for the CMV34M cpuModule Address Range hex Bytes Device 000 00Fh 16 DMA Controller 010 01Fh 16 Reserved for CPU 020 021h 2 Interrupt Controller 1 022 02Fh 13 Reserved 040 043h 4 Timer 060 064h Keyboard Interface 070 071h 2 Real Time Clock Port 080 08Fh 16 DMA Page Register 0A0 0A1h 2 Interrupt Controller 2 0C0 0DFh 32 DMA Controller 2 0F0 0FFh 16 Math Coprocessor 100 101h 2 Video lnitialization 1F0 1FFh 16 Hard Disk 200 201h 2 Reserved 238 23Bh 4 Bus Mouse 2E8 2EFh 8 Serial Port 2F8 2FFh 8 Serial Por 3E8 3EFh 8 Serial Port 3F8 3FFh 8 Serial Port 980 9BFh 64 Reserved 9C0 9C4h 5 aDIO 9C5 9DFh 27 Reserved 1 Ifa floppy or IDE controller is not connected to the system the I O addresses listed will not be occupied 2 Ifa PS 2 mouse is not connected to the system the I O addresses listed will not be occupied 3 The l O addresses for the serial port are selected in the BIOS Setup utility 4 IfaDIO is disabled the addresses listed will not be occupied BDM 610000077 Rev A Chapter 4 Using the cpuModule 47 Hardware Interrupts EN Note lf you add any expansion modul
79. us I O Address 987h Write Access D7 D6 D5 D4 D3 D2 D1 DO Utility Reset System Power Good Main 5V Input Memory Power 1 clear reset 1 clear reset 1 clear reset 1 clear reset CPU Core Power SIO Power Good Management Power Standby Power 1 z clear reset 1 z clear reset 1 z clear reset 1 z clear reset BDM 610000077 Rev A Chapter 4 Using the cpuModule 61 I O Address t 457h D7 D6 D5 D4 D3 D2 D1 00 Table 53 Reset Status Description and Priorities Reset Reset Signal Priority Utility Reset gt CPU Core Power 5 System Power 4 SIO Power 3 Main Power 45V 2 Management Power 2 Memory Power 2 Standby Power 1 Description Utility connector push button reset CPU core powers supply Power supplies that are not for standby power Power monitored by the Super I O Main input power cpuModule 45V Power used in management mode Power to onboard memory banks Standby power supplies When a reset is asserted all resets with a higher reset priority will also be asserted For example if the standby power reset is asserted all other resets will also be asserted 2 The BIOS allows the user to change the function of the utility connector s push button reset Even if the push button is not configured as a reset this bit will always read a 1 asserted when the reset button has been 62 CMV34M cpuModule pushed BDM 610000077 Rev A Features and Settings That Can Affect Boot Time The boot time o
80. uters although these may require creation of custom drivers to use the aDIO and watchdog timer 8 CMV34M cpuModule BDM 610000077 Rev A Specifications Physical Characteristics e Dimensions 116mm x 99mm x 24mm 4 6 L x 3 9 W x 0 95 H e Weight Approximately 0 20 Kg 0 44 Ib with Heatsink Power Consumption Exact power consumption depends on the actual application Table 2 lists power consumption for typical configurations and clock speeds Table 2 cpuModule Power Consumption Module Speed RAM Power Typ Heavy CPU Heavy CPU Load amp Gfx Load CMV34MVD1860 1 86 GHz 1024 MB 21 0 W 31 5 W 33 0 W CMV34MVD1200 1 20 GHz 1024 MB 15 8 W 21 0 W 23 0 W CMV34MCS1200 1 20 GHz 1024 MB 13 3 W 16 0 W 19 5 W Operating Conditions Table 3 Operating Conditions Symbol Parameter Test Condition Min Max Vecs 5V Supply Voltage 4 75V 5 25V Vccs 3 3V Supply Voltage n a n a Vcci2 12V Supply Voltage n a n a 5V Standby Voltage 4 75V 5 25V 5V Standby Current 500mA Ta Ambient Operating MVD1860 40 70 Temperature Ta Ambient Operating MVD1200 40 85 Temperature MCS1200 Ts Storage Temperature 25 85 Rh Humidity Non Condensing 0 90 Mean Time Before 23C 275 000 Failure hours 1 The 12Vand external 3 3V rails are not used by the cpuModule Any requirements on these signals are driven by other components in the system such as a PCI device 2 5V Standby is used to power the board
81. warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Revision History Revision Date Reason for Change A 5 31 2012 Initial release li CMV34M cpuModule BDM 610000077 Rev A CMV34M cpuModules www rtd com 1509001 and AS9100 Certified Accessing the Analog World iv CMV34M cpuModule BDM 610000077 Rev A Table of Contents Chapter 1 Introduction CMV34M 2 Enhanced Intel SpeedStep Core 2 Duo only ee 3 nomiue 3 aDIO with 1 e he hme ese he me e he he heme hens 3 Ordering Information eel eere ida 4 CMV34M Model Optiofis ve etel hop dose teneo es rr rv OPES 4 Cable Kits amd Accessories seansa 4 Board Features oo espe panes 5 6 do TUTUP 7 Block Did P C 8 Specifications od a oe E ka basata UHR NDA dek aaa 9 Physical Characteristics arier En EU K NE ea _______ _ a 9 Power Consumptie zavesa AA wus 5 lol mons 9 Operating Conditions yaa PT e QUUM REY kaka 9 Electrical Characteristics 10 Contact Information sii ss er peer Re RR ZA o
82. website www rtd com for more detailed ordering information and any new variations that may be available Cable Kits and Accessories Table 1 Part Number CMV34MVD1860HR 2048 CMV34MVD1860HR 1024 CMV34MVD1200HR 2048 CMV34MVD1200HR 1024 CMV34MCS1200HR 2048 CMV34MCS1200HR 1024 CMV34M cpuModule Model Options Description Core 2 Duo Dual Core 1 86 GHz 2GB DDR2 SDRAM Core 2 Duo Dual Core 1 86 GHz 1GB DDR2 SDRAM Core 2 Duo Dual Core 1 20 GHz 2GB DDR2 SDRAM Core 2 Duo Dual Core 1 20 GHz 1GB DDR2 SDRAM Celeron Single Core 1 20 GHz 2GB DDR2 SDRAM Celeron Single Core 1 20 GHz 1GB DDR2 SDRAM For maximum flexibility RTD does not provide cables with the cpuModule You may wish to purchase the CMV34M cpuModule cable kit P N which contains Multi function utility harness keyboard socket battery reset speaker Two serial port cables DIL 10 to DSUB 9 VGA monitor cable DIL 10 to high density 15 pin DSUB aDIO cable DIL 16 to DSUB 25 Two USB cables 5 pin SIL to USB A PCle 104 Type 2 break out board to connect SATA and USB Ethernet cable DIL 10 to RJ 45 For additional accessories refer to the RTD website 4 CMV34M cpuModule BDM 610000077 Rev A Board Features e Penryn Processor Part Number Speed Cores L2 Cache FSB Speed CMV34MVD1860 1 86GHZ Two 6 MB 1066 MHz CMV34MVD1200 1 20 GHz Two 3 MB 800 MHz CMV34MCS1200 1 20 GHz One 1 MB 800 MHz Intel 64 architecture for 64 bit processing Enhan
83. y Intelligent Data Acquisition Node This appendix provides the dimensions and pinouts of the CMV34M installed in an IDAN frame Contact RTD for more information on high reliability IDAN HiDAN and HiDANplus PC PCI 104 systems IDAN Adhering to the PC 104 stacking concept IDAN allows you to build a customized system with any combination of RTD modules IDAN Heat Pipes Advanced heat pipe technology maximizes heat transfer to heat sink fins HiDANplus Integrating the modularity of IDAN with the ruggedization of HiDAN HiDANplus enables connectors on all system frames with signals running between frames through a dedicated stack through raceway BDM 610000077 Rev A Appendix C Dimensions and Pinout 75 IDAN Dimensions and Connectors 6 pin mini DIN female module P N Adam Tech MDE006W mating P N Adam Tech MDP006 9 pin D male module P N Adam Tech DEO9PD mating P N Adam Tech DEO9SD 25 pin D female module P N Adam Tech DB25SD mating P N Adam Tech DB25PD KEYBOARD 1 176 415 m 00 fe ts Oo 00 00 co N 00 m N N 15 pin high density D female 9 pin D male module P N Adam Tech HDT15SD module P N Adam Tech DEO9PD mating P N Adam Tech HDT15PD mating P N Adam Tech DEO9SD Figure 9 IDAN CMV34M Connectors 1 Heatsink fins not shown in Figure 9 extend 0 75 inches from the sides of the IDAN frame 2 Use40mm for this frame when calcula
84. ying that it does not drop below 4 75 V The voltage at the connector should be checked with an oscilloscope while the system is operational WARNING f you connect power incorrectly the module will almost certainly be destroyed Please verify power connections to the module before applying power Table7 Auxiliary Power Connector CN3 Pin Signal Function 1 GND Ground 2 45 V 45 Volts DC 3 GND Ground 4 5 V 45 Volts DC 5 GND Ground 6 GND Ground 7 45 V 45 Volts DC 8 5V_STDBY 5V Standby ATX 9 5V 5 Volts DC 10 PSON Power Supply On ATX 1 For more information on the style signals 5V Standby and PSON refer to the Power Management section in Chapter 4 Using the cpuModule 24 CMV34M cpuModule BDM 610000077 Rev A Utility Port Connector CN5 The utility port connector implements the following functions PC AT compatible keyboard port PS 2 mouse port Speaker port 0 1W output Hardware Reset input Soft Power Button input Battery input for Real Time Clock Table 8 provides the pinout of the multi function connector Table 8 Utility Port Connector CN5 Pin Signal Function In Out 1 SPKR Speaker Output open collector out 2 PWR 5V out 3 RESET Manual Push Button Reset in 4 PWRSW Soft Power Button in 5 KBD Keyboard Data in out 6 KBC Keyboard Clock out 7 GND Ground 8 MSC Mouse Clock out 9 BAT RTC Battery Input in 10 MSD Mouse Data in
85. ype 2 Bus Bottom 156 0 635mm Samtec 5 129637 03 CN3 Auxiliary Power 1x10 0 1 FCI 65039 027LF CN5 Utility Port 2x5 0 1 3M 89110 0001 CN6 aDIO 2x8 0 1 3M 89116 0001 CN7 Serial Port 1 COM183 2x5 0 1 3M 89110 0001 CN8 Serial Port 2 COM2 amp 4 2x5 0 1 3M 89110 0001 CN13 RTC Battery Input optional 1x2 2mm FCI 69305 002LF CN15 Fan Power switched 1x3 2mm FCI 69305 003LF CN17 USB 2 0 2x5 0 1 3M 89110 0001 CN18 Video SVGA 2x5 0 1 3M 89110 0001 CN20 Ethernet 2x5 0 1 3M 89110 0001 U6 SATA Disk Chip Socket 18 pin 0 1 na WARNING connect power incorrectly the module will almost certainly be damaged or destroyed Such damage is not covered by the RTD warranty Please verify connections to the module before applying power Power is normally supplied to the cpuModule through the PCle bus connectors CN1 or CN2 Ifyou are placing the cpuModule onto a PC 104 stack that has a power supply you do not need to make additional connections to supply power If you are using the cpuModule without a PC 104 stack or with stack that does not include a power supply refer to Auxiliary Power CN3 on page 24 for more details BDM 610000077 Rev A Chapter 2 Getting Started 15 Selecting the Stack Order for the CMV34M There are several things to consider when selecting the order of boards in the stack Before selecting the order be sure to determine which bus connector on each board is the Active
86. ystem to keep the fan turned off until the CPU reaches 70C In this mode the fan will slowly transition between on and off to prevent oscillations This is the best mode for applications that will spend most of the time below OC e Variable The fan will spin slowly until the CPU reaches 60C and then will increase speed Maximum speed is reached when the CPU reaches 75C Further Temperature Reduction The cpuModule temperature is directly related to power consumption Reducing the power consumption of the CPU will have an effect on the CPU s temperature Suggested methods for reducing the CPU s power consumption can be found in the Power Management section on page 58 BDM 610000077 Rev A Chapter 4 Using the cpuModule 57 Power Management The CMV34M cpuModule supports various powering mechanisms which allow the cpuModule to monitor power consumption and temperature and achieve minimal power consumption states These unigue features include Enhanced Intel SpeedStep Technology Core 2 Duo only thermal monitoring and thermal throttling as well as low power modes including ACPI configurations Various wake options are also available to resume normal system power Enabling Enhanced Intel SpeedStep Technology Core 2 Duo When enabled Enhanced Intel SpeedStep Technology can give application software greater control over the processor s operating freguency and input voltage This allows the system to easily manage power consumption dynami

CMV34M Hardware Manual - RTD Embedded Technologies, Inc.

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