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MPC5200B - Data Sheet

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1. r Output Driver Input Pull up Name Alias Type Power Supply Type Type down l2c 3 SDA y o VDD 10 DRV4 Schmitt PSC PSCI 0 TxD Sdata out UO VDD_IO DRV4 TTL MOSI TX PSC1_1 RxD Sdata_in UO VDD_IO DRV4 TTL MISO TX PSC1 2 Mcik Sync RTS UO VDD IO DRV4 TTL PSC1_3 BitClk SCK CTS y o VDD IO DRV4 Schmitt PSC1_4 Frame SS CD UO VDD_IO DRV4 TTL PSC2 0 TxD Sdata out UO VDD 10 DRV4 TTL MOSI TX PSC2 1 RxD Sdata in y o VDD IO DRV4 TTL MISO TX PSC2 2 Mcik Sync RTS UO VDD_IO DRV4 TTL PSC2_3 BitClk SCK CTS y o VDD IO DRV4 Schmitt PSC2 4 Frame SS CD UO VDD_IO DRV4 TTL PSC3_0 USB_OE TxDS 1 0 VDD_IO DRV4 TTL TX PSC3_1 USB_TXN RxD UO VDD_IO DRV4 TTL RX PSC3_2 USB TXP BitClk UO VDD 10 DRVA Schmitt RTS PSC3 3 USB RXD Frame VO VDD 10 DRV4 TTL SS CTS PSC3_4 USB_RXP CD y o VDD IO DRV4 TTL PSC3_5 USB_RXN UO VDD_IO DRV4 TTL PSC3_6 USB_PRTPWR 1 0 VDD 10 DRV4 TTL Mcik MOSI PSC3 7 USB SPEED 1 0 VDD_IO DRV4 TTL MISO PSC3_8 USB_SUPEND UO VDD_IO DRV4 TTL SS PSC3_9 USB_OVRCNT UO VDD_IO DRV4 TTL SCK GPIO TIMER GPIO_WKUP_6 MEM CS1 y o VDD MEM IO DRV16 MEM TTL PULLUP MEM GPIO WKUP 7 UO VDD_IO DRV8 TTL TIMER 0 1 0 VDD_IO DRV4 TTL MPC5200B Data Sheet Rev 4 62 Freescale Semiconductor Table 52 MPC5200B Pinout Listing continued
2. 1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency CPU core frequency and PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies This represents total input jitter short term and long term combined and is guaranteed by design Two different types of jitter can exist on the input to CORE_SYSCLK systemic and true random jitter True random jitter is rejected Systemic jitter is passed into and through the PLL to the internal clock circuitry Relock time is guaranteed by design and characterization PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep modes 1 2 4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage controlled core PLL MPC5200B Data Sheet Rev 4 Freescale Semiconductor Table 11 e300 PLL Specifications Characteristic Sym Notes Min Typical Max Unit SpeciD e300 frequency bus 1 50 550 MHz 04 1 e300 cycle time bs 1 2 85 40 0 ns O4 2 e300 VCO frequency fVCOcore 1 400 1200 MHz 04 3 e300 input clock frequency XLB_CLK 25 367 MHz O4 4 e30
3. Core Power Supply VDD_CORE SYS_XTAL XLB PCI IPB CORE MHz SpeciD Mode 331661331331264 33 132 66 132 396 Unit Notes Typ Typ Operational 727 5 1080 mw M6 D5 1 Doze 600 mW 1 8 D5 2 Nap 225 mW 01 4 D5 3 Sleep 225 mW 1 65 D5 4 Deep Sleep 52 5 52 5 mW 1 6 D5 5 PLL Power Supplies SYS_PLL_AVDD CORE_PLL_AVDD Mode Typ Unit Notes Typical 2 mw 7 D5 6 Unloaded UO Power Supplies VDD 10 VDD MEM 108 Mode Typ Unit Notes Typical 33 mW 3 D5 7 Typical core power is measured at VDD CORE 1 5 V Tj 25 C Operational power is measured while running an entirely cache resident program with floating point multiplication instructions in parallel with a continuous PCI transaction via BestComm Doze power is measured with the e300 core in Doze mode the system oscillator System PLL and Core PLL are active all other system modules are inactive Nap power is measured with the e300 core in Nap mode the system oscillator System PLL and Core PLL are active all other system modules are inactive Sleep power is measured with the e300 core in Sleep mode the system oscillator System PLL and Core PLL are active all other system modules are inactive Deep Sleep power is measured with the e300 core in Sleep mode the system oscillator System PLL Core PLL and all other system modules are inactive Typical PLL power is measured at SYS PLL AVDD CORE PLL AVDD 1 5 V Tj 2 25 C IO power figures given
4. Name Alias Type Power Supply SE mee eg TIMER_1 1 0 VDD 10 DRV4 TTL TIMER_2 MOSI 1 0 VDD 10 DRV4 TTL TIMER_3 MISO 1 0 VDD_IO DRV4 TTL TIMER_4 SS 1 0 VDD 10 DRV4 TTL TIMER_5 SCK UO VDD_IO DRV4 TTL TIMER_6 1 0 VDD 10 DRV4 TTL TIMER_7 1 0 VDD IO DRV4 TTL Clock SYS_XTAL_IN Input VDD IO SYS XTAL OUT Output VDD IO RTC XTAL IN Input VDD 10 RTC XTAL OUT Output VDD IO Misc PORRESET Input VDD 10 DRV4 Schmitt HRESET UO VDD 10 DRV8_OD Schmitt SRESET y o VDD 10 DRV8 OD Schmitt IRQO 1 0 VDD 10 DRV4 TTL IRQ1 y o VDD 10 DRV4 TTL IRQ2 UO VDD 10 DRV4 TTL IRQ3 y o VDD IO DRV4 TTL Test Configuration SYS_PLL_TPA 1 0 VDD 10 DRV4 TTL TEST MODE 0 Input VDD 10 DRV4 TTL TEST MODE 1 Input VDD 10 DRV4 TTL TEST SEL 0 1 0 VDD_IO DRV4 TTL PULLUP TEST_SEL_1 1 0 VDD_IO DRV8 TTL JTAG_TCK TCK Input VDD IO DRV4 Schmitt PULLUP JTAG_TDI TDI Input VDD_IO DRV4 TTL PULLUP JTAG_TDO TDO UO VDD_IO DRV8 TTL JTAG_TMS TMS Input VDD 10 DRV4 TTL PULLUP JTAG_TRST TRST Input VDD_IO DRV4 TTL PULLUP Power and Ground VDD IO MPC5200B Data Sheet Rev 4 Freescale Semiconductor Table 52 MPC5200B Pinout Listing continued Output Driver Input Pull up Name Alias Type Power Supply Type Type down VDD MEM IO VDD_CORE VSS IO CORE SYS PLL AVDD CORE_PLL_AVDD 1 AI open drain outputs of the MPC5200B are actually regular three state output drivers with the output data tied low and the output enable controlled T
5. ns A15 47 3 Slave select clock delay programable in the PSC CCS register 30 0 ns A15 48 4 Output data valid 8 9 ns A15 49 5 Input Data setup time 6 0 ns A15 50 6 Input Data hold time 1 0 ns A15 51 7 Slave disable lag time 8 9 ns A15 52 8 Sequential Transfer delay programable in the PSC CTUR CTLR 15 0 ns A15 53 register 9 Clock falling time 7 9 ns A15 54 10 Clock rising time 7 9 ns A15 55 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 Freescale Semiconductor SCK CLKPOL 0 Output SCK CLKPOL 1 Output SS Output MOSI Output MISO Input A X 6 S Figure 43 Timing Diagram SPI Master Mode Format 1 CPHA 1 Table 49 Timing Specifications SPI Slave Mode Format 1 CPHA 1 Sym Description Min Max Units SpeciD 1 SCK cycle time programable in the PSC CCS register 30 0 ns A15 56 2 SCK pulse width 50 SCK duty cycle 15 0 ns A15 57 3 Slave select clock delay 0 0 ns A15 58 4 Output data valid 14 0 ns A15 59 5 Input Data setup time 2 0 ns A15 60 6 Input Data hold time 1 0 ns A15 61 7 Slave disable lag time 0 0 ns A15 62 8 Minimum Sequential Transfer delay 2 x IP Bus clock cycle time 30 0 m ns A15 63 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4
6. All injection current is transferred to VDD IO VDD IO MEM An external load is required to dissipate this current to maintain the power supply within the specified voltage range Total injection current for all digital input only and all digital input output pins must not exceed 10 mA Exceeding this limit can cause disruption of normal operation Table 4 Drive Capability of MPC5200B Output Pins Driver Type Supply Voltage lon lot Unit SpeciD DRV4 VDD_IO 3 3 V 4 4 mA D3 25 DRV8 VDD_IO 3 3 V 8 8 mA D3 26 DRV8_OD VDD lO 2 3 3 V 8 mA D3 27 DRV16 MEM VDD IO MEM 3 3 V 16 16 mA D3 28 DRV16 MEM VDD IO MEM 2 5 V 16 16 mA D3 29 PCI VDD lO 3 3 V 16 16 mA D3 30 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 1 1 4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high static voltage or electrical fields However it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level GND or Vcc Table 7 gives package thermal characteristics for this device Table 5 ESD and Latch Up Protection Characteristics Sym Rating Min Max Unit SpecID Vuem Human Body Model HBM JEDEC JESD22 A114 B 2000 V D4 1 Vum Machine Model MM JEDEC JESD22 A115 2
7. Freescale Semiconductor SCK CLKPOL 0 Input SCK CLKPOL 1 Input SS Input MOSI Input MISO Output A Figure 44 Timing Diagram SPI Slave Mode Format 1 CPHA 1 1 3 17 GPIOs and Timers 1 3 17 1 General and Asynchronous Signals The MPC5200B contains several sets if I Os that do not require special setup hold or valid requirements Most of these are asynchronous to the system clock The following numbers are provided for test and validation purposes only and they assume a 133 MHz internal bus frequency Figure 45 shows the GPIO Timing Diagram Table 50 gives the timing specifications Table 50 Asynchronous Signals Sym Description Min Max Units SpeciD tok Clock Period 7 52 ns A16 1 tis Input Setup 12 ns A16 2 Du Input Hold 1 ns A16 3 tpv Output Valid 15 33 ns A16 4 ton Output Hold 1 ns A16 5 MPC5200B Data Sheet Rev 4 54 Freescale Semiconductor Output A vali A H e 4 Us e Figure 45 Timing Diagram Asynchronous Signals MPC5200B Data Sheet Rev 4 Freescale Semiconductor 55 1 3 18 IEEE 1149 1 JTAG AC Specifications Table 51 JTAG Timing Specification Sym Characteristic Min Max Unit SpeciD TCK frequency of operation 0 25 MHz A17 1 1 TCK cycle time 40 ns A1
8. Freescale Semiconductor 25 Table 25 Burst Mode Timing continued Sym Description Min Max Units Notes SpeciD tg DATA hold after rising edge of PCI 0 ns A7 32 clock tio DATA hold after CS negation 0 DC 1 x tpcicx ns 4 A7 33 Di ACK assertion after CS assertion WS 1 x tpolck ns A7 34 t2 ACK negation before CS negation 7 0 ns 3 A7 35 tia ACK pulse width 4 8 x 2 x 32 DS x tporox 4 9 x 2 x 32 DS x teoria ns 2 9 A7 36 tja CS assertion after TS assertion 2 5 ns A7 37 De TS pulse width tPCIck PCIck ns A7 38 NOTES 1 Wait States WS can be programmed in the Chip Select X Register Bit field WaitP and WaitX It can be specified from 0 65535 Example Long Burst is used this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst on the internal XLB is executed gt LB 1 Data bus width is 8 bit gt DS 2 8 gt 4 x 2 x 3218 32 gt ACK is asserted for 32 PCI cycles to transfer one cache line Wait State is set to 10 gt WS 10 1 10 32 43 gt CS is asserted for 43 PCI cycles ACK is output and indicates the burst Deadcycles are only used if no arbitration to an other module ATA or PCI of the shared local bus happens If arbitration happen
9. Sym Description Min Max Units SpeciD tmem_clk MEM_CLK period 7 5 ns A5 1 lvalid Control Signals Address and MBA Valid after lmem cik x 0 5 0 4 ns A5 2 rising edge of MEM_CLK thold Control Signals Address and MBA Hold after tmem cik x 0 5 ns A5 3 rising edge of MEM_CLK DMyalia DQM valid after rising edge of MEM_CLK tmem cik x 0 25 0 4 ns A5 4 DMhold DQM hold after rising edge of MEM_CLK tmem cik x 0 25 0 7 ns A5 5 datasetup MDQ setup to rising edge of MEM_CLK 0 3 ns A5 6 datanoig MDQ hold after rising edge of MEM_CLK 0 2 ns A5 7 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 17 MEM_CLK T T T E pi lvalid E Control Signals Active T DMvalid oou oaa waso TITIA A AA A A uoc tue TT ee h valid wien ZPC VOIN TTT gt tvalid thold MBA Bank Solcts A TIO WUA A II NOTE Control Signals are composed of RAS CAS MEM_WE MEM_CS MEM_CS1 and CLK_EN Figure 5 Timing Diagram Standard SDRAM Memory Read Timing 1 3 6 2 Memory Interface Timing Standard SDRAM Write Command In Standard SDRAM all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK clock at the memory device Table 19 Standard SDRAM Write Timing Sym Description Min Max Units S
10. A13 16 Programming IFDR with the maximum frequency IFDR 0x20 results in the minimum output timings listed The 12C interface is designed to scale the data transition time moving it to the middle of the SCL low period The actual position is affected by the prescale and division values programmed in IFDR Because SCL and SDA are open drain type outputs which the processor can only actively drive low the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull up resistor values 3 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM NOTE Output timing is specified at a nominal 50 pF load A Ae Ae M Cu I I I KiE v Po lo 3 i 4 9 a Figure 36 Timing Diagram I C Input Output 1 3 15 J1850 See the MPC5200B User s Manual MPC5200BUM MPC5200B Data Sheet Rev 4 46 Freescale Semiconductor 1 3 16 PSC 1 3 16 1 Codec Mode 8 16 24 and 32 bit I7S Mode Table 42 Timing Specifications 8 16 24 and 32 bit CODEC 12S Master Mode Sym Description Min Typ Max Units SpeciD 1 Bit Clock cycle time programmed in CCS register 40 0 ns A15 1 2 Clock duty cycle 50 9 A15 2 3 Bit Clock fall time 7 9 ns A15 3 4 Bit Clock rise time 7 9 ns A15 4 5 FrameSync valid after clock edge 8 4 ns A15 5 6 FrameSync invalid after clock edge 8 4 ns A15 6
11. Jj MEET BETTE ETE TETTE TT Sample position A data are sampled on the expected edge of MEM CLK the MDQS signal indicate the valid data Sample position B data are sampled on a later edge of MEM CLK SDRAM controller is waiting for the valid MDQS signal NOTE Control Signals signals are composed of RAS CAS MEM WE MEM CS MEM CS1 and CLK EN Figure 7 Timing Diagram DDR SDRAM Memory Read Timing MPC5200B Data Sheet Rev 4 Freescale Semiconductor 1 3 6 4 Memory Interface Timing DDR SDRAM Write Command Table 21 DDR SDRAM Memory Write Timing Sym Description Min Max Units SpecID tmem cik MEM CLK period 7 5 ns A5 20 tposs Delay from write command to first tmem cik 0 4 ns A5 21 rising edge of MDQS datavalid MDQ valid before rising edge of 1 0 ns A5 22 MDQS datahold MDQ valid after rising edge of 1 0 ns A5 23 MDQS I I I I I MEM Ok 4 MEM GLK A A A A A A A A Control Signals write XI LIN RE VILLA Write MILITO Wills KULLA datavalid datahold MDQS Data Strobe E ee mba Data JI XXX X X L XXX XXX AK NOTE Control Signals signals are composed of RAS CAS MEM WE MEM CS MEM CS1 and CLK EN Figure 8 DDR SDRAM Memory Write Timing
12. ns Comment SpeciD Min Max Min Max Min Max tcvc 114 75 55 Cycle time allowing for asymmetry and clock A8 26 variations from STROBE edge to STROBE edge tocyc 235 156 117 Two cycle time allowing for clock variations from A8 27 rising edge to next rising edge or from falling edge to next falling edge of STROBE tps 15 10 7 Data setup time at recipient A8 28 tDH 5 5 5 Seng Data hold time at recipient A8 29 tovs 70 48 34 Data valid setup time at sender to STROBE edge A8 30 tovH 6 6 m 6 Data valid hold time at sender from STROBE edge A8 31 trs 0 230 0 200 0 170 First STROBE time for drive to first negate DSTROBE A8 32 from STOP during a data in burst ty 0 150 0 150 0 150 Limited Interlock time A8 33 tMLI 20 20 20 x Interlock time with minimum A8 34 tul 0 0 0 Unlimited interlock time A8 35 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 81 Table 29 Ultra DMA Timing Specification continued MODE 0 MODE 1 MODE 2 Sym ns ns ns Comment SpeciD Min Max Min Max Min Max taz 10 10 10 Maximum time allowed for output drivers to release A8 36 from being asserted or negated tzAH 20 20 20 Minimum delay time required for output drivers to A8 37 ls 0 Sep 0 Se 0 assert or negate from released state 28 38 tenv 20 70 20 70 20 70 Envel
13. 1 JTAG_TDO tdo I output is really an input to the core w N A From the board under test power sense for chip power HALTED is not available from e300 core Input to the e300 core to enable disable soft stop condition during breakpoints MPC5200B With respect to the emulator tool s perspective Input is really an output from the embedded e300 core and internally ties CORE QACK to GND in its normal functional mode always asserted For a board with a COP common on chip processor connector which accesses the JTAG interface and which needs to reset the JTAG module simply wiring JTAG_TRST and PORRESET is not recommended MPC5200B Data Sheet Rev 4 Freescale Semiconductor 67 To reset the MPC5200B via the COP connector the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200B The circuitry shown in Figure 54 allows the COP to assert HRESET or JTAG_TRST separately while any other board sources can drive PORRESET PORRESET PORRESET COP Header HRESET MPC5200B ORESET 10Kohm HRESET VDD SRESET VDD m 10Kohm SRESET mile 10Kohm COP Connector VDD Physical Pinout 1 JTAG TRST 3 10Kohm VDD 5 JTAG_TMS 7 10Kohm VDD 9 JTAG_TCK H 10Kohm VDD 13 Key JTAG TDI 15 CKSTP OUT TEST SEL 0 TDO JTAG_TDO NC NC NC NC Figure 54 COP Connector Diagram 3 4 2 2 Bo
14. 16 24 and 32 bit CODEC I S Slave Mode MPC5200B Data Sheet Rev 4 48 Freescale Semiconductor 1 3 16 2 AC97 Mode Table 44 Timing Specifications AC97 Mode Sym Description Min Typ Max Units SpeciD 1 Bit Clock cycle time 81 4 ns A15 15 2 Clock pulse high time 40 7 ns A15 16 3 Clock pulse low time 40 7 ns A15 17 4 FrameSync valid after rising clock edge 13 0 ns A15 18 5 Output Data valid after rising clock edge 14 0 ns A15 19 6 Input Data setup time 1 0 ns A15 20 7 Input Data hold time 1 0 ns A15 21 NOTE Output timing is specified at a nominal 50 pF load 1 gt i o CLKPOL 0 3 2 Input Sack Aas Hm ue FrameSync SyncPol 1 E Output 5 gt La Sdata_out XI 1 X X Output 6 7 iat M Sdata in X X X X Input Figure 39 Timing Diagram AC97 Mode 1 3 16 3 IrDA Mode Table 45 Timing Specifications IrDA Transmit Line Sym Description Min Max Units SpeciD 1 Pulse high time defined in the IrDA protocol definition 0 125 10000 us A15 22 2 Pulse low time defined in the IrDA protocol definition 0 125 10000 us A15 23 3 Transmitter rising time 7 9 ns A15 24 4 Transmitter falling time I 7 9 ns A15 25 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 Freescale Semiconductor
15. 49 Ze e IrDA TX ER 3 Cho J amp Y SIR FIR MIR 4 Las n I Ei LI Figure 40 Timing Diagram IrDA Transmit Line 1 3 16 4 SPI Mode Table 46 Timing Specifications SPI Master Mode Format 0 CPHA 0 Sym Description Min Max Units SpeciD 1 SCK cycle time programable in the PSC CCS register 30 0 ns A15 26 2 SCK pulse width 50 SCK duty cycle 15 0 ns A15 27 3 Slave select clock delay programable in the PSC CCS register 30 0 ns A15 28 4 Output Data valid after Slave Select SS 8 9 ns A15 29 5 Output Data valid after SCK 8 9 ns A15 30 6 Input Data setup time 6 0 ns A15 31 7 Input Data hold time 1 0 ns A15 32 8 Slave disable lag time 8 9 ns A15 33 9 Sequential Transfer delay programable in the PSC CTUR CTLR 15 0 ns A15 34 register 10 Clock falling time 7 9 ns A15 35 11 Clock rising time 79 ns A15 36 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 50 Freescale Semiconductor q SCK N a i N CLKPOL 0 l 2 2 Output Sen p 10 Tem SCK qa CLKPOL 1 a EEN dr 2 Output F 8 SH lt ra Output X g e I I 4 5 e qu T MOSI i Output X A I 6 Bst be pi a MISO X j Input 1 7 i 7 al p gt 8 Pe Figure 41 Timing Diagram SPI Master Mode
16. 69 5 Document Revision History s cues ste STEE pre 70 MPC5200B Data Sheet Rev 4 Freescale Semiconductor JOojonpuooluJeg e eoseoJ4 t ed PS ejeg goozsodlN Figure 1 shows a simplified MPC5200B block diagram SDRAM DDR Systems Interface Unit SIU Real Time Clock E SDRAM DDR E Memory Controller System Functions 603 Interrupt Controller Le e300 Core GPIO Timers E Local Plus Controller JTAG COP a nx Interface SRAM Bestom PCI Bus Controller Reset Clock 16KB SES pt rh Generation ATA Host Controller pem lt _ A CommBus bee DE 43 PSC Ethernet 12C SPI USB J1850 MSCAN 6x 2x 2x 2x EE AME ENS MEM yoy oY Figure 1 Simplified Block Diagram MPC5200B Local Bus 1 Electrical and Thermal Characteristics 1 1 DC Electrical Characteristics 1 1 1 Absolute Maximum Ratings The tables in this section describe the MPC5200B DC Electrical characteristics Table 1 gives the absolute maximum ratings Table 1 Absolute Maximum Ratings Characteristic Sym Min Max Unit SpecID Supply voltage e300 core and peripheral logic VDD CORE 0 3 1 8 V D1 1 Supply voltage l O buffers VDD 10 0 3 3 6 V D1 2 VDD MEM IO S
17. Cycle A11 2 3 Slave select to clock delay 15 0 ns A11 3 4 Output Data valid after Slave Select SS 20 0 ns A11 4 5 Output Data valid after SCK 20 0 ns A11 5 6 Input Data setup time 20 0 ns A11 6 7 Input Data hold time 20 0 ns A11 7 8 Slave disable lag time 15 0 ns A11 8 9 Sequential transfer delay 1 IP Bus Cycle A11 9 10 Clock falling time 7 9 ns A11 10 11 Clock rising time 7 9 ns A11 11 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 Freescale Semiconductor 41 10 lag T SCK CLKPOL 0 T Output 2 2 gt e Je eg SCK 4 qi CLKPOL 1 N Y 7 DA Output ja 8 9 n n M e i Output CAE R 4 5 Nd ngj et MOSI y Output 6 Bad Due Z lt I MISO Input A 7 7 gt lt gt Figure 32 Timing Diagram SPI Master Mode Format 0 CPHA 0 Table 37 Timing Specifications SPI Slave Mode Format 0 CPHA 0 Sym Description Min Max Units SpeciD 1 Cycle time 4 1024 IP Bus Cycle A11 12 2 Clock high or low time 2 512 IP Bus Cycle A11 13 3 Slave select to clock delay 15 0 ns A11 14 4 Output Data valid after Slave Select SS 50 0 ns A11 15 5 Output Data valid after SCK 50 0 ns A11 16 6 Input Data
18. DSTROBE device DD 0 15 device 2X OX XOOK XKKKK KKK Figure 18 Timing Diagram Host Pausing an Ultra DMA Data In Burst DMARQ q device DMACK host tu tu wu wx Ei eme STOP i i host A i Woo tu tack I I I HDMARDY i I host A As y MEC gt I lioRDvz DSTROBE l device X pa i ZAH tovs Inc ot om DD 0 15 EE CRC SS OSOS gt 1 t I DAO DA1 DA2 ACK XXX CS 0 1 Figure 19 Timing Diagram Drive Terminating Ultra DMA Data In Burst MPC5200B Data Sheet Rev 4 34 Freescale Semiconductor DMARQ device ES I tu i tuu i re me DMACK t host trp Gan tack I I I I I l 1 STOP I l host A t peg U aem a N HDMARDY I i host N l l i I y 4 i t I H i ia ei a E ma r tlorpyz I I I DSTROBE EEN device xX Es tovs 1 DVH lt pos XXX KOOOOOOO OE 086 OOOO tack DAO DA1 DA2 xx CS 0 1 Figure 20 Timing Diagram Host Terminating Ultra DMA Data In Burst DMARQ device tul l DMACK host E tenv i tack I l STOP T I host Fi t i tu u ZIORDY K 4 re I I I L DDMARDY l A I host e tack S l I I HSTROBE i device Fd l l DD 0 15
19. Format 0 CPHA 0 Table 47 Timing Specifications SPI Slave Mode Format 0 CPHA 0 Sym Description Min Max Units SpeciD 1 SCK cycle time programable in the PSC CCS register 30 0 ns A15 37 2 SCK pulse width 50 SCK duty cycle 15 0 ns A15 38 3 Slave select clock delay 1 0 ns A15 39 4 Input Data setup time 1 0 ns A15 40 5 Input Data hold time 1 0 ns A15 41 6 Output data valid after SS 14 0 ns A15 42 7 Output data valid after SCK 14 0 ns A15 43 8 Slave disable lag time 0 0 ns A15 44 9 Minimum Sequential Transfer delay 2 x IP Bus clock cycle time 30 0 A15 45 NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 Freescale Semiconductor 51 8 SCK F H X CLKPOL 0 Input 2 2 SCK CLKPOL 1 N Input S SS ln We lt gt 9 Input X g Se 4 9 isa gp S m MOSI X j Input i X 6 7 AER lt gt pase X w Figure 42 Timing Diagram SPI Slave Mode Format 0 CPHA 0 Table 48 Timing Specifications SPI Master Mode Format 1 CPHA 1 Sym Description Min Max Units SpeciD 1 SCK cycle time programable in the PSC CCS register 30 0 ns A15 46 2 SCK pulse width 50 SCK duty cycle 15 0
20. Operating Frequency Data 13 1 3 3 Clock AC Specifications 13 kad Besche isn4ddck ve e Ah 14 1 8 5 External Interrupts mana nan pat SEN EEN 15 136 SDRAM EECHER 17 dr E e EE 21 138 Local Plus ES coco d 4 23 D non eed ameter eed heniomaies 28 19 10 Etemel ir devia eee tek kod do SER 38 LS RE LEE A0 He le EECH 41 LATS MSCGAN corran rr aaron 45 E TEE 45 ee MICO A E AET AENA ans Peas quib aba ae 46 AP trace EE 47 13 17 GPIOS and TIMES uoces he IRR IURE ERG 54 1 3 18 IEEE 1149 1 JTAG AC Specifications 56 2 Package Description s secre o ERE RARO RE X ER 57 21 Package ParaMBlerS i cue cm Ae Re ALE web ae 57 2 2 Mechanical DIMENSIONS sos eer RR E 58 2 0 PIAQUELISINOS Age SE eh dree tech LOTO 59 3 System Design Information i aaa ee eee 64 3 1 Power Up Down Sequencing 64 3 1 1 Power Up Sequence 65 3 1 2 Power Down Sequence 65 3 2 System and CPU Core AVDD Power Supply Filtering 65 3 3 Pull up Pull down Resistor Requirements 65 3 3 1 Pull down Resistor Requirements for TEST pins65 3 3 2 Pull up Requirements for the PCI Control Lines 66 3 3 3 Pull up Pull down Requirements for MEM MDQS Pins SDRAM e battre 66 3 3 4 Pull up Pull down Requirements for MEM MDQS Pins DDR 16 bit Mode 66 md JTAG saciar deen be a 66 A 66 3 4 2 e300 COP BDM Interface 67 4 Ordering mormalloni EE
21. Vin 0 VDD IO V D2 7 Input voltage memory I O buffers SDR Vinspn 0 VDD MEM lOspn V D2 8 Input voltage memory I O buffers DDR Vinppn 0 VDD MEM lOppn V D2 9 Ambient operating temperature range Ta 40 85 26 D2 10 Die junction operating temperature range Tj 40 115 C D2 12 1 These are recommended and tested operating conditions Proper device operation outside these conditions is not guaranteed 2 Maximum e300 core operating frequency is 400 MHz 1 1 3 DC Electrical Specifications Table 3 gives the DC Electrical characteristics for the MPC5200B at recommended operating conditions see Table 2 Table 3 DC Electrical Specifications Characteristic Condition Sym Min Max Unit SpecID Input high voltage Input type TTL Vu 2 0 Ss V D3 1 VDD IO VDD MEM lOspn Input high voltage Input type TTL Vin 1 7 V D3 2 VDD MEM lOppn Input high voltage Input type PCI Viu 2 0 V D3 3 VDD IO Input high voltage Input type SCHMITT Vin 2 0 V D3 4 VDD IO Input high voltage SYS XTAL IN CVin 2 0 D3 5 Input high voltage RTC_XTAL_IN Cu 2 0 D3 6 Input low voltage Input type TTL Vu 0 8 D3 7 VDD IO VDD MEM lOspn Input low voltage Input type TTL ViL 0 7 V D3 8 VDD MEM lOppn Input low voltage Input type PCI Vu 0 8 V D3 9 VDD IO Input low voltage Input type SCHMITT ViL 0 8 V D3 10 VDD IO Input low voltage SYS XTAL IN CVI 0 8 D3 11 Input low
22. as RX and TX pins at normal IO pads 2C1 GPTimer or PSC2 There is no filter for the WakeUp dominant pulse Any High to Low edge can cause WakeUp if configured 1314 Pc Table 40 I C Input Timing Specifications SCL and SDA Sym Description Min Max Units SpeciD 1 Start condition hold time 2 JiP Bus Cycle A13 1 2 Clock low time 8 IP Bus Cycle A13 2 4 Data hold time 0 0 ns A13 3 6 Clock high time 4 P Bus Cycle A13 4 7 Data setup time 0 0 ns A13 5 8 Start condition setup time for repeated start condition 2 IP Bus Cycle A13 6 only 9 Stop condition setup time 2 IP Bus Cycle A13 7 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM MPC5200B Data Sheet Rev 4 Freescale Semiconductor 45 Table 41 12C Output Timing Specifications SCL and SDA Sym Description Min Max Units SpeciD 11 Start condition hold time 6 P Bus Cycle A13 8 201 Clock low time 10 P Bus Cycle A13 9 32 SCL SDA rise time 7 9 ns A13 10 40 Data hold time 7 IP Bus Cycle A13 11 50 SCL SDA fall time 7 9 ns A13 12 e Clock high time 10 IP Bus Cycle A13 13 70 Data setup time a IP Bus Cycle A13 14 8 Start condition setup time for repeated start condition 20 JIP Bus Cycle A13 15 only EW Stop condition setup time 10 JIP Bus Cycle9
23. for a computational fluid dynamics CFD thermal model To determine the junction temperature of the device in the application after prototypes are available the Thermal Characterization Parameter Y y can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation Ty Tr P jp x Pp Eqn 5 where Ty thermocouple temperature on top of package C Y yr thermal characterization parameter C W Pp power dissipation in package W The thermal characterization parameter is measured per JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire 1 2 Oscillator and PLL Electrical Characteristics The MPC5200B System requires a system level clock input SYS_XTAL This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator There is a separate oscillator for the independent Real Time Clock RTC system The MPC5200B clock generation uses two phase locked loop PLL blocks e The s
24. voltage RTC_XTAL_IN Cu 0 8 D3 12 Input leakage current Vin 0 or lin 2 LA D3 13 VDD IO VDD IO MEMspn depending on input type Input leakage current SYS XTAL IN lin 10 LA D3 14 Vin 0 or VDD IO MPC5200B Data Sheet Rev 4 Freescale Semiconductor Table 3 DC Electrical Specifications continued Characteristic Condition Sym Min Max Unit SpecID Input leakage current RTC_XTAL_IN lin 10 uA D3 15 Vin 0 or VDD_IO Input current pullup resistor PULLUP liNpu 40 109 uA D3 16 VDD 10 Vin 0 Input current pullup resistor PULLUP_MEM liNpu 41 111 uA D3 17 memory I O buffers VDD_IO_MEMspr Vin 0 Input current pulldown PULLDOWN IINpd 36 106 LA D3 18 resistor VDD IO Vin VDD 10 Output high voltage IOH is driver dependent VoH 2 4 V D3 19 VDD 10 VDD IO MEMspn Output high voltage IOH is driver dependent VOHDDR 17 V D3 20 VDD IO MEMppn Output low voltage IOL is driver dependent VoL 0 4 V D3 21 VDD 10 VDD_IO_MEMgpa Output low voltage IOL is driver dependent VoLDDR 0 4 V D3 22 VDD IO MEMppn DC Injection Current Per les 1 0 1 0 mA D3 23 Pin Capacitance Vin 0 V f 1 MHz Cin 15 pF D3 24 Leakage current is measured with output drivers disabled and pull up pull downs inactive See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 52
25. 0 input clock cycle time lxiB CLK x 2 73 Gem 50 0 ns 04 5 e300 input clock jitter litter 2 E 150 ps 04 6 e300 PLL relock time tiock 3 100 us 04 7 1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies CPU core frequency and e300 PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies in Table 12 This represents total input jitter short term and long term combined and is guaranteed by design Two different types of jitter can exist on the input to CORE_SYSCLK systemic and true random jitter True random jitter is rejected Systemic jitter is passed into and through the PLL to the internal clock circuitry Relock time is guaranteed by design and characterization PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep modes 1 3 AC Electrical Characteristics Hyperlinks to the indicated timing specification sections are provided below 1 3 1 Unless otherwise noted all test conditions are as follows AC Operating Frequency Data Clock AC Specifications Resets External Interrupts SDRAM PCI Local Plus Bus ATA Ethernet AC Test Timing Conditions TA 40to 85 C e Tj 40to 115 C
26. 00 V D4 2 Venom Charge Device Model CDM JEDEC JESD22 C101 500 V D4 3 lar Latch up Current at TA 85 C D4 4 positive 100 mA negative 100 lar Latch up Current at TA 27 C D4 5 positive 200 mA negative 200 1 1 5 Power Dissipation Power dissipation of the MPC5200B is caused by 3 different components the dissipation of the internal or core digital logic supplied by VDD_CORE the dissipation of the analog circuitry supplied by SYS_PLL_AVDD and CORE PLL AVDD and the dissipation of the IO logic supplied by VDD_IO_MEM and VDD_IO Table 6 details typical measured core and analog power dissipation figures for a range of operating modes However the dissipation due to the switching of the IO pins can not be given in general but must be calculated by the user for each application case using the following formula 2 Pio Proint ZN CxVDD IO xf Eqn 1 M where N is the number of output pins switching in a group M C is the capacitance per pin VDD IO is the IO voltage swing f is the switching frequency and PIOint is the power consumed by the unloaded IO stage The total power consumption of the MPC5200B processor must not exceed the value which would cause the maximum junction temperature to be exceeded P Prone t P total core analog t Pro Eqn 2 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 7 Table 6 Power Dissipation
27. 00 ns A9 15 MDC is generated by MPC5200B with a duty cycle of 50 except when MII SPEED in the FEC MII SPEED control register is changed during operation See the MPC5200B User s Manual MPC5200BUM The MDC period must be set to a value of less than or equal to 2 5 MHz to be compliant with the IEEE MII characteristic by programming the FEC MI SPEED control register See the MPC5200B User s Manual MPC5200BUM a tia pi tia MDC Output l ts l tio gt l EE E SE E I I Di D Figure 30 Ethernet Timing Diagram MIl Serial Management 1 3 11 USB Table 35 Timing Specifications USB Output Line Sym Description Min Max Units SpeciD 1 USB Bit width 83 3 667 ns A10 1 2 Transceiver enable time 83 3 667 ns A10 2 3 Signal falling time 7 9 ns A10 3 4 Signal rising time 7 9 ns A10 4 Defined in the USB config register 12 Mbit s or 1 5 Mbit s mode NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 40 Freescale Semiconductor USB_TXN A XA N Y q 1 1 44 lt a 4 3 4 pi Le e 9 pi la Figure 31 Timing Diagram USB Output Line 1 3 12 SPI Table 36 Timing Specifications SPI Master Mode Format 0 CPHA 0 Sym Description Min Max Units SpeciD 1 Cycle time 4 1024 IP Bus Cycle A11 1 2 Clock high or low time 2 512 IP Bus
28. 00BUM 2 SYS_XTAL_IN duty cycle is measured at Vu MPC5200B Data Sheet Rev 4 Freescale Semiconductor 13 1 3 4 Resets The MPC5200B has three reset pins e PORRESET Power on Reset e HRESET Hard Reset e SRESET Software Reset These signals are asynchronous I O signals and can be asserted at any time The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200B inputs as specified in the DC Electrical Specifications section Table 14 specifies the pulse widths of the Reset inputs Table 14 Reset Pulse Width Name Description Min Pulse Width E Reference Clock SpeciD PORRESET Power On Reset typp stable lup osc Hoch SYS XTAL IN A3 1 HRESET Hardware Reset 4 clock cycles SYS_XTAL_IN A3 2 SRESET Software Reset 4 clock cycles SYS XTAL IN A3 3 For PORRESET the value of the minimum pulse width reflects the power on sequence If PORRESET is asserted afterwards its minimum pulse width equals the minimum given for HRESET related to the same reference clock The typp stable describes the time which is needed to get all power supplies stable For tjock refer to the Oscillator PLL section of this specification for further details For tup_osc refer to the Oscillator PLL section of this specification for further details Following the deassertion of PORRESET HRESET and SRESET remain low for 4096 reference clock cycles The deassertion of H
29. 1 3 7 PCI The PCI interface on the MPC5200B is designed to PCI Version 2 2 and supports 33 MHz and 66 MHz PCI operations See the PCILocal Bus Specification the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board without any external buffers or other glue logic Parameters apply at the package pins not at expansion board edge connectors The MPC5200B is always the source of the PCI CLK The clock waveform must be delivered to each 33 MHz or 66 MHz PCI component in the system Figure 9 shows the clock waveform and required measurement points for 3 3 V signaling environments Table 22 summarizes the clock specifications MPC5200B Data Sheet Rev 4 Freescale Semiconductor 21 PCICIK 0 4Vcc 4 0 4 Vcc p to p rpm minimum Figure 9 PCI CLK Waveform Table 22 PCI CLK Specifications 66 MHz 33 MHz Sym Description Units Notes SpeciD Min Max Min Max lej PCI CLK Cycle Time 15 30 30 ns 1 8 A6 1 thigh PCI CLK High Time 6 11 ns A6 2 tlow PCI CLK Low Time 6 11 ns A6 3 PCI CLK Slew Rate 1 5 4 1 4 Vins 2 A6 4 PCI Clock Jitter 200 200 ps peak to peak NOTES 1 In general all 66 MHz PCI components must work with any clock frequency up to 66 MHz CLK requirements vary depending u
30. 51 8 Board temperature is measured on the top surface of the board near the package D Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51 2 When Greek letters are not available the thermal characterization parameter is written as Psi JT 1 1 6 1 Heat Dissipation An estimation of the chip junction temperature Ty can be obtained from the following equation Ty Ta Roya x Pp Eqn 3 where TA ambient temperature for the package C Roja junction to ambient thermal resistance C W Pp power dissipation in package W The junction to ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance Unfortunately there are two values in common usage the value determined on a single layer board and the value obtained on a board with two planes For packages such as the PBGA these values can be different by a factor of two Which value is correct depends on the power dissipated by other components on the board The value obtained on a single layer board is appropriate for the tightly packed printed circuit board The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well sep
31. 7 2 2 TCK clock pulse width measured at 1 5V 1 08 ns A17 3 3 TCK rise and fall times 0 3 ns A17 4 4 TRST setup time to tck falling edge 10 ns A17 5 5 TRST assert time 5 ns A17 6 6 Input data setup time 5 ns A17 7 7 Input data hold time 15 ns A17 8 8 TCK to output data validO 0 30 ns A17 9 9 TCK to output high impedance 0 30 ns A17 10 10 TMS TDI data setup time 5 ns A17 11 11 TMS TDI data hold time 1 ns A17 12 12 TCK to TDO data valid 0 15 ns A17 13 13 TCK to TDO high impedance 0 15 ns A17 14 1 TRST is an asynchronous signal The setup time is for test purposes only 2 Non test other than TDI and TMS signal input timing with respect to TCK 3 Non test other than TDO signal output timing with respect to TCK m U gt 2 gt a 2 gt TCK VM ad Y ZS puc VM Midpoint Voltage Numbers shown reference Table 51 Figure 46 Timing Diagram JTAG Clock Input TCK TRST Numbers shown reference Table 51 Figure 47 Timing Diagram JTAG TRST MPC5200B Data Sheet Rev 4 56 Freescale Semiconductor TCK DATA INPUTS 8 E gt DATA OUTPUTS X OUTPUT DATA VALID 9 a gt DATA OUTPUTS Numbers shown reference Table 51 Figure 48 Timing Diagram JTAG Boundary Scan TCK TDI TMS 12 t TDO X OUTPUT DATA VALID 13 E gt TDO Numbers shown reference Table 51 Figure 49 Timing Diagram Test Access Port 2 Package Description 2 1 Package Para
32. 7 Output Data valid after clock edge 9 3 ns A15 7 8 Input Data setup time 6 0 ns A15 8 1 Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load gt A A A CLKPOL 0 3 Es Output 2 2 4 lt ra 4 BitClk CLKPOL 1 sk a oe 5 47x op Output 7 La 3 Bae iae gt lt a FrameSync L SyncPol 1 Output V FrameSync SyncPol 0 Output 7 Ar iby X X X Output I 8 d lt b RxD Input A A A I Figure 37 Timing Diagram 8 16 24 and 32 bit CODEC IS Master Mode MPC5200B Data Sheet Rev 4 Freescale Semiconductor 47 Table 43 Timing Specifications 8 16 24 and 32 bit CODEC 12S Slave Mode Sym Description Min Typ Max Units SpeciD 1 Bit Clock cycle time 40 0 ns A15 9 2 Clock duty cycle 50 90 A15 10 3 FrameSync setup time 1 0 ns A15 11 4 Output Data valid after clock edge 14 0 ns A15 12 5 Input Data setup time 1 0 ns A15 13 6 Input Data hold time 1 0 ns A15 14 1 BitClk CLKPOL 0 Input BitClk CLKPOL 1 Input FrameSync SyncPol 1 Input FrameSync SyncPol 0 Input TxD Output RxD Input Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load X Figure 38 Timing Diagram 8
33. Freescale Semiconductor Data Sheet Technical Data MPC5200B Data Sheet Key features are shown below Freescale reserves the right to change the detail specifications as may be required to permit MPC603e series e300 core Superscalar architecture 760 MIPS at 400 MHz 40 C to 85 C 16 KB Instruction cache 16 KB Data cache Double precision FPU Instruction and Data MMU Standard and Critical interrupt capability SDRAM DDR Memory Interface Up to 133 MHz operation SDRAM and DDR SDRAM support 256 MB addressing range per CS two CS available 32 bit data bus Built in initialization and refresh Flexible multi function External Bus Interface Supports interfacing to ROM Flash SRAM memories or other memory mapped devices 8 programmable Chip Selects Non multiplexed data access using 8 16 32 bit databus with up to 26 bit address Short or Long Burst capable Multiplexed data access using 8 16 32 bit databus with up to 25 bit address Peripheral Component Interconnect PCI Controller Version 2 2 PCI compatibility PCI initiator and target operation 32 bit PCI Address Data bus 33 and 66 MHz operation PCI arbitration function ATA Controller Version 4 ATA compatible external interface IDE Disk Drive connectivity BestComm DMA subsystem Intelligent virtual DMA Controller Dedicated DMA channels to control peripheral recepti
34. K 0000 D 0000 C B IDE VIEW 0000000000 A B 123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 272X b A S 0 3 JAJBJC BOTTOM VIEW 1 G0 15 JA CASE 1135A 01 ISSUE B Figure 50 Mechanical Dimensions and Pinout Assignments for the MPC5200B 272 TE PBGA MPC5200B Data Sheet Rev 4 58 Freescale Semiconductor 2 3 Pinout Listings See details in the MPC5200B User s Manual MPC5200BUM Table 52 MPC5200B Pinout Listing Name Alias Type Power Supply e e Oe jen SDRAM MEM CAS CAS UO VDD MEM IO DRV16 MEM TTL MEM CLK EN CLK EN VO VDD MEM IO DRV16 MEM TTL MEM CS VO VDD MEM IO DRV16 MEM TTL MEM DQN 3 0 DQM O VDD MEM IO DRV16_MEM TTL MEM_MA 12 0 MA O VDD MEM IO DRV16_MEM TTL MEM_MBA 1 0 MBA O VDD MEM IO DRV16 MEM TTL MEM MDGS 3 0 MDQS O VDD MEM IO DRV16 MEM TTL MEM MDQD 31 0 MDQ O VDD MEM IO DRV16 MEM TTL MEM CLK O VDD MEM IO DRV16 MEM TTL MEM CLK O VDD MEM IO DRV16 MEM TTL MEM RAS RAS UO VDD MEM 10 DRV16_MEM TTL MEM_WE VO VDD MEM IO DRV16_MEM TTL PCI EXT AD 31 0 VO VDD IO PCI PCI PCI CBE 0 VO VDD IO PCI PCI PCI_CBE_1 VO VDD IO PCI PCI PCI CBE 2 VO VDD IO PCI PCI PCI CBE 3 VO VDD IO PCI PCI PCI_CLOCK VO VDD IO PCI PCI PCI_DEVSEL VO VDD IO PCI PCI PCI_FRAME VO VDD IO PCI PCI PCI_GNT VO VDD IO DRV8 TTL PCI IDSEL VO VDD IO DRV8 TTL PCI IRD
35. MII Tx Signal Timing Sym Description Min Max Unit SpeciD t5 TX CLK rising edge to TXD 3 0 TX EN TX ER 5 ns A9 5 invalid tg TX CLK rising edge to TXD 3 0 TX EN TX ER valid 25 ns A9 6 t TX CLK pulse width high 35 65 TX_CLK Period A9 7 ta TX_CLK pulse width low 35 65 TX CLK Period A9 8 1 TheTX CLK frequency shall be 25 of the nominal transmit frequency e g a PHY operating at 100 Mb s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb s must provide a TX GLK frequency of 2 5 MHz See the IEEE 802 3 Specification t7 TX_CLK Input N l t5 tg TXD 3 0 Outputs l TX_EN TX_ER t L6 owl Figure 28 Ethernet Timing Diagram MII Tx Signal Table 33 MII Async Signal Timing Sym Description Min Max Unit SpeciD tg CRS COL minimum pulse width 1 5 TX_CLK Period A9 9 I CRS COL UA M l t Figure 29 Ethernet Timing Diagram MIl Async MPC5200B Data Sheet Rev 4 Freescale Semiconductor 39 Table 34 MII Serial Management Channel Signal Timing Sym Description Min Max Unit SpeciD tio MDC falling edge to MDIO output delay 0 25 ns A9 10 t41 MDIO input to MDC rising edge setup 10 ns A9 11 tjo MDIO input to MDC rising edge hold 10 ns A9 12 tia MDC pulse width high 160 ns A9 13 tja MDC pulse width low 160 ns A9 14 tis MDC period 4
36. QS 1 0 signals are not used in DDR 16 bit mode and require pull down resistors 3 4 JTAG The MPC5200B provides the user an IEEE 1149 1 JTAG interface to facilitate board system testing It also provides a Common On Chip Processor COP Interface which shares the IEEE 1149 1 JTAG port The COP Interface provides access to the MPC5200B s embedded Freescale formerly Motorola MPC603e e300 processor This interface provides a means for executing test routines and for performing software development and debug functions 3 4 1 JTAG_TRST Boundary scan testing is enabled through the JTAG interface signals The JTAG_TRST signal is optional in the IEEE 1149 1 specification but is provided on all processors that implement the PowerPC architecture To obtain a reliable power on reset performance the JTAG_TRST signal must be asserted during power on reset 3 4 1 1 JTAG_TRST and PORRESET The JTAG interface can control the direction of the MPC5200B I O pads via the boundary scan chain The JTAG module must be reset before the MPC5200B comes out of power on reset do this by asserting JTAG_TRST before PORRESET is released For more details refer to the Reset and JTAG Timing Specification PORRESET Required assertion of JTAG TRST Optional assertion of JTAG TRST JTAG TRST Figure 53 PORRESET vs JTAG TRST 3 4 1 2 Connecting JTAG TRST The wiring of the JTAG_TRST depends on the existence of a board related debug interface see bel
37. RAM Memory Controller uses a 1 4 period delayed MDQS strobe to capture the MDQ data The 1 4 period delay value is calculated automatically by hardware Table 20 DDR SDRAM Memory Read Timing Sym Description Min Max Units SpeciD tmem cik MEM CLK period 7 5 ns A5 15 lvalid Control Signals Address and MBA tmem cik x 0 5 0 4 ns A5 16 valid after rising edge of MEM_CLK thold Control Signals Address and MBA tmem cik x 0 5 m ns A5 17 hold after rising edge of MEM CLK datasetup Setup time relative to MDQS 0 4 ns A5 18 datanoig Hold time relative to MDQS 2 6 ns A5 19 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 19 I MEM Ok 4 4 KT EI EI E MEM_CLK A jA d A 4 4 4 i ty lid hola Control Signals Active Y NOP Y READ Y NOP Y NOP J NOP V NOP ji NOP MDGS Data Strobe N PON d OO taata valid m ata valid max MDQ Data HOH CU Sample NIT ldata sample min Ze Head Data Sample Window ata sample max MDGS Data Strobe cf NU NU Las vulpis Yr voaa TTT TMT 0 5 xt x lMEM CLK position A max X X Sample position E B Read Data WO HOME Tea Sample Window z tvalid MA Address lvalid MBA Bank Selects 7 Row Column J JI TTTTTTTI FTT HUHI 7
38. RESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles NOTE As long as VDD is not stable the HRESET output is not stable Table 15 Reset Rise Fall Timing Description Min Max Unit SpeciD PORRESET fall time 1 ms A3 4 PORRESET rise time 1 ms A3 5 HRESET fall time 1 ms A3 6 HRESET rise time 1 ms A3 7 SRESET fall time 1 ms A3 8 SRESET rise time 1 ms A3 9 NOTE Make sure that the PORRESET does not carry any glitches The MPC5200B has no filter to prevent them from getting into the chip HRESET and SRESET must have a monotonous rise time The assertion of HRESET becomes active at Povver on Reset vvithout any SYS XTAL clock MPC5200B Data Sheet Rev 4 14 Freescale Semiconductor For additional information see the MPC5200B User s Manual MPC5200BUM 1 3 4 1 Reset Configuration Word During reset HRESET and PORRESET the Reset Configuration Word is latched in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal If both resets HRESET and PORRESET are inactive high the contents of this register are locked immediately with the SYS_XTAL clock see Figure 3 PUES 3 SYS_XTAL l PORRESET H gt HRESET RST_CFG_WRD X sample sa
39. VDD CORE 1 42 to 1 58 V VDD 10 3 0 to 3 6 V USB SPI MSCAN PE J1850 PSC GPIOs and Timers IEEE 1149 1 JTAG AC Specifications MPC5200B Data Sheet Rev 4 Freescale Semiconductor e Input conditions All Inputs tr tf lt 1 ns e Output Loading All Outputs 50 pF 1 3 2 AC Operating Frequency Data Table 12 provides the operating frequency information for the MPC5200B Table 12 Clock Frequencies Min Max Units SpeciD 1 e300 Processor Core 400 MHz A1 1 2 SDRAM Clock 133 MHz A1 2 3 XL Bus Clock 133 MHz A1 3 4 IP Bus Clock 133 MHz A1 4 5 PCI Local Plus Bus Clock 66 MHz A1 5 6 PLL Input Range 15 6 35 MHz A1 6 1 3 3 Clock AC Specifications SYSCLK Figure 2 Timing Diagram SYS XTAL IN Table 13 SYS XTAL IN Timing Sym Description Min Max Units SpeciD tcycLe SYS_XTAL_IN cycle time 28 6 64 1 ns A2 1 tnisE SYS XTAL IN rise time 5 0 ns A2 2 Bean SYS_XTAL_IN fall time 5 0 ns A2 3 tDUTY SYS XTAL IN duty cycle measured at Vull 40 0 60 0 A2 4 CVin SYS_XTAL_IN input voltage high 2 0 V A2 5 Cu SYS_XTAL_IN input voltage low 0 8 V A2 6 1 CAUTION The SYS XTAL IN frequency and system PLL_CFG 0 6 settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies See the MPC5200B User s Manual MPC52
40. W hold after CS negation tIPBIck ns A7 9 tg DATA output valid before CS assertion tjpBlck ns A7 10 to DATA output hold after CS negation tjpBlok ns m A7 11 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 23 Table 24 Non MUXed Mode Timing continued Sym Description Min Max Units Notes SpeciD tjo DATA input setup before CS negation 8 5 ns A7 12 ti DATA input hold after CS negation 0 DC 1 x tpcig ns 9 A7 13 tio ACK assertion after CS assertion tPCIck ns 3 A7 14 tis ACK negation after CS negation tPCIck ns 3 A715 tja TS assertion before CS assertion 6 9 ns 4 A716 tis TS pulse width tPCIck tPCIck ns DI A7 17 tio TSIZ valid before CS assertion tiPBlck ns 9 A718 uz TSIZ hold after CS negation iPBIck ns 9 A719 tig ACK change before PCI clock 2 0 ns CU A7 20 tig ACK change after PCI clock 4 4 ns 0 A7 21 NOTES 1 ona P Co ACK can shorten the CS pulse width Wait States WS can be programmed in the Chip Select X Register Bit field WaitP and WaitX It can be specified from 0 65535 In Large Flash and MOST Graphics mode the shared PCI ATA pins used as address lines are released at the same moment as the CS This can cause the address to change before CS is deasserted ACK is input and can be used to shorten the CS pulse width Only available in L
41. Y VO VDD IO PCI PCI PCI_PAR VO VDD IO PCI PCI PCI_PERR VO VDD IO PCI PCI PCI_REQ 1 0 VDD IO DRV8 TTL PCI_RESET VO VDD IO PCI PCI PCI_SERR VO VDD IO PCI PCI PCI_STOP VO VDD IO PCI PCI MPC5200B Data Sheet Rev 4 Freescale Semiconductor 59 Table 52 MPC5200B Pinout Listing continued Name Alias Type Power Supply SS Tie Greg PCI_TRDY UO VDD IO PCI PCI Local Plus LP ACK UO VDD 10 DRV8 TTL PULLUP LP_ALE 1 0 VDD 10 DRV8 TTL LP_OE 1 0 VDD 10 DRV8 TTL LP_RW y o VDD 10 DRV8 TTL LP TS 1 0 VDD 10 DRV8 TTL LP CSO UO VDD 10 DRV8 TTL LP_CS1 y o VDD 10 DRV8 TTL LP CS2 y o VDD 10 DRV8 TTL LP CS3 1 0 VDD 10 DRV8 TTL LP_CS4 UO VDD 10 DRV8 TTL LP_CS5 y o VDD IO DRV8 TTL ATA ATA DACK UO VDD 10 DRV8 TTL ATA_DRQ 1 0 VDD_IO DRV8 TTL PULLDOWN ATA_INTRQ 1 0 VDD 10 DRV8 TTL PULLDOWN ATA_IOCHRDY 1 0 VDD 10 DRV8 TTL PULLUP ATA_IOR UO VDD 10 DRV8 TTL ATA_IOW 1 0 VDD_IO DRV8 TTL ATA_ISOLATION 1 0 VDD 10 DRV8 TTL Ethernet ETH 0 TX TX EN 1 0 VDD IO DRV4 TTL ETH_1 RTS TXD 0 UO VDD 10 DRV4 TTL ETH_2 USB_TXP RTX y o VDD 10 DRV4 TTL TXD 1 ETH_3 USB_PRTPWR y o VDD 10 DRV4 TTL TXD 2 ETH_4 USB_SPEED y o VDD 10 DRV4 TTL TXD 3 ETH_5 USB_SUPEND y o VDD 10 DRV4 TTL TX_ER ETH_6 USB_OE RTS y o VDD 10 DRV4 TTL MDC ETH_7 TXN MDIO 1 0 VDD_IO DRV4 TTL MPC5200B Data Sheet Rev 4 60 F
42. an do bused signals GNT and REQ have a setup of 5 ns at 66 MHz All other signals are bused 4 See the timing measurement conditions in the PCI Local Bus Specification For Measurement and Test Conditions see the PCI Local Bus Specification 1 3 8 Local Plus Bus The Local Plus Bus is the external bus interface of the MPC5200B A maximum of eight configurable chip selects CS are provided There are two main modes of operation non MUXed Legacy and Burst and MUXED The reference clock is the PCI CLK The maximum bus frequency is 66 MHz Definition of Acronyms and Terms e WS Wait State e DC Dead Cycle e LB Long Burst e DS Data Size in Bytes tpc ek PCI clock period tpppgick IPBI clock period I PCICLK IE NE X X l yi PBIck rack WU UU UU UU UU UU Figure 10 Timing Diagram IPBI and PCI clock example ratio 4 1 1 3 8 1 Non MUXed Mode Table 24 Non MUXed Mode Timing Sym Description Min Max Units Notes SpeciD tesa PCI CLK to CS assertion 4 6 10 6 ns A7 1 tcsn POlClKtoCSnegaion 29 70 ms a72 ti CS pulse vvidth 2 WS x tpcick 2 WS x Iech ns EN A7 3 to ADDR valid before CS assertion tjpBlck tecick ns m A7 4 ts ADDR hold after CS negation tIPBIck ns 2 A7 5 t4 OE assertion before CS assertion 4 8 ns A7 6 ts OE negation before CS negation 2 7 ns A7 7 te RW valid before CS assertion tPCIck ns A7 8 tz R
43. arated Historically the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance MPC5200B Data Sheet Rev 4 Freescale Semiconductor 9 Roja Resc Roca Eqn 4 Where Roja junction to ambient thermal resistance C W Rgjc junction to case thermal resistance C W Reca case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user controls the thermal environment to change the case to ambient thermal resistance Roca For instance the user can change the air flow around the device add a heat sink change the mounting arrangement on printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This description is most useful for ceramic packages with heat sinks where some 90 of the heat flow is through the case to the heat sink to ambient For most packages a better model is required A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance The junction to case covers the situation where a heat sink is used or a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board This model can be used for hand estimations or
44. ards Without COP Connector If the JTAG interface is not used JTAG_TRST should be tied to PORRESET so that it is asserted when the system reset signal PORRESET is asserted This ensures that the JTAG scan chain is initialized during power on Figure 55 shows the connection of the JTAG interface without COP connector MPC5200B Data Sheet Rev 4 68 Freescale Semiconductor PORRESET PORRESET MPC5200B Br HRESET VDD VDD wl SRESET pj JIAG TRST pj JTAG_TMS pj JTAG_TCK pj JTAG TDI p TEST SEL 0 HRESET 4 b SRESET 10Kohm e 10Kohm 10Kohm vr 10Kohm mi Figure 55 JTAG TRST Wiring for Boards without COP Connector 4 Ordering Information Table 54 Ordering Information Part Number Speed Ambient Temp Qualification Packaging MPC5200VR400B 400 0 C to 70 C Commercial RoHS 8 Pb free MPC5200CVR466B 400 40 Cto 85 C Industrial RoHS 8 Pb free SPC5200CBV400B 400 40 C to 85 C Automotive AEC Standard SPC5200CVR400B 400 40 C to 85 C Automotive AEC RoHS amp Pb free SC103335VR400B 400 40 C to 85 C Automotive AEC RoHS 8 Pb free Shipped in trays Add R2 suffix for Tape amp Reel Commercial Qualified to 250 PPM level Industrial Automotive Qualified to AEC Q100 Automotive has Zero Defect flow 3 Standard is hali
45. arge Flash and MOST Graphics mode Only available in MOST Graphics mode Deadcycles are only used if no arbitration to an other module ATA or PCI of the shared local bus happens If arbitration happens the bus can be driven within 4 IPB clocks by an other modules MPC5200B Data Sheet Rev 4 24 Freescale Semiconductor LL E El a la ty d CS x N t ta l ADDR i I OE y EHI ME BE R W Y X g 2 DATA wr X Y i I I t 1 t 1 DATA rd tig 1 uL t l ACK erh t UN A 3 tia ts q 18 d i bg TSIZ 1 2 X X i tie Figure 11 Timing Diagram Non MUXed Mode 1 3 8 2 Burst Mode Table 25 Burst Mode Timing Sym Description Min Max Units Notes SpeciD tesa PCI CLK to CS assertion 4 6 10 6 ns A7 22 tcsN PCI CLK to CS negation 2 9 7 0 ns A7 23 ty CS pulse width 1 WS 4 x 2 1 WS 4 2x ns 42 A724 x 32 DS x tecick 32 DS x tpcick to ADDR valid before CS assertion tIPBIck tPCIck ns A7 25 ta ADDR hold after CS negation 0 7 ns A7 26 t4 OE assertion before CS assertion 4 8 ns A7 27 ts OE negation before CS negation 2 7 ns A7 28 te RW valid before CS assertion tPCIck ns A7 29 t7 RW hold after CS negation tPCIck ns A7 30 tg DATA setup before rising edge of 3 6 ns A7 31 PCI clock MPC5200B Data Sheet Rev 4
46. d to the VDD IO VDD IO MEM to be in a high impedance state There is no limit to how long after VDD IO VDD IO MEM powers up before VDD CORE must power up VDD CORE should not lead the VDD IO VDD IO MEM or PLL_AVDD by more than 0 4 V during power ramp up or there will be high current in the internal ESD protection diodes The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes The recommended power up sequence is as follows Use one microsecond or slower rise time for all supplies VDD CORE PLL AVDD and VDD IO VDD IO MEM should track up to 0 9 V and then separate for the completion of ramps with VDD IO VDD IO MEM going to the higher external voltages One way to accomplish this is to use a low drop out voltage regulator 3 1 2 Power Down Sequence If VDD CORE PLL AVDD are powered down first sense circuits in the I O pads cause all output drivers to be in a high impedance state There is no limit on how long after VDD CORE and PLL_AVDD power down before VDD IO or VDD IO MEM must power down VDD CORE should not lag VDD IO VDD IO MEM or PLL_AVDD going low by more than 0 5 V during power down or there will be undesired high current in the ESD protection diodes There are no requirements for the fall times of the power supplies The recommended power down sequence is as follows 1 Drop VDD CORE PLL AVDD to 0 V 2 Drop VDD IO VDD IO MEM supplies 3 2 System and CPU Co
47. de free with Pb solder balls MPC5200B Data Sheet Rev 4 Freescale Semiconductor 5 Document Revision History Table 55 provides a revision history for this hardware specification Table 55 Document Revision History Rev No Differences 1 Clock Frequencies table 466 MHz was changed to 400 MHz for the e300 Processor Core 2 Added description for PCI CLK Slew Rate for PCI CLK Specifications table Added description for minimum rates in the DDR SDRAM Memory Write Timing table 3 Added one item to table DDR SDRAM Memory Read Timing 4 Updated table Ordering Information MPC5200B Data Sheet Rev 4 70 Freescale Semiconductor MPC5200B Data Sheet Rev 4 Freescale Semiconductor 71 How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku T
48. epresentative For information on Freescale s Environmental Products program go to http www freescale com epp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2008 2010 All rights reserved e 2 freescale semiconductor
49. errupt prioritization which may increase the latencies Because all external interrupt signals are synchronized into the internal processor bus clock domain each of these signals has to exceed a minimum pulse width of more than one IP CLK cycle Table 17 Minimum Pulse Width for External Interrupts to be Recognized Name Min Pulse Width Max Pulse Width Reference Clock SpeciD All external interrupts IRQs GPIOs gt 1 clock cycle IP_CLK A4 22 NOTES 1 The frequency of the IP_CLK depends on the register settings in Clock Distribution Module See the MPC5200B User s Manual MPC5200BUM for further information 2 If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one the second interrupt is not recognized at all Besides synchronization prioritization and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions To get a minimum interrupt service response time it is recommended to enable the instruction cache and set up the maximum core clock XL bus and IP bus frequencies depending on board design and programming In addition it is advisable to execute an interrupt handler which has been implemented in assembly code 1 3 6 SDRAM 1 3 6 1 Memory Interface Timing Standard SDRAM Read Command Table 18 Standard SDRAM Memory Read Timing
50. g modes in which the ATA Controller can communicate with the drive Faster ATA modes i e UDMA 0 1 2 are supported when the system is running at a sufficient frequency to provide adequate data transfer rates Adequate data transfer rates are a function of the following e The MPC5200B operating frequency IP bus clock frequency e Internal MPC5200B bus latencies e Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200B See the MPC5200B User s Manual MPC5200B NOTE All output timing numbers are specified for nominal 50 pF loads Table 27 PIO Mode Timing Specifications Sym PIO Timing Parameter Sue p e 0 js 1 St e S pe 4 SpeciD to Cycle Time min 600 383 240 180 120 A8 1 t Address valid to DIOR DIOW setup min 70 50 30 30 25 A8 2 b DIOR DIOW pulse width 16 bit min 165 125 100 80 70 A8 3 8 bit min 290 290 290 80 70 by DIOR DIOW recovery time min 70 25 A8 4 ta DIOW data setup min 60 45 30 30 20 A8 5 t4 DIOW data hold min 30 20 15 10 10 A8 6 ts DIOR data setup min 50 35 20 20 20 A8 7 tg DIOR data hold min 5 5 5 5 5 A8 8 to DIOR DIOW to address min 20 15 10 10 10 A8 9 valid hold ta IORDY setup max 35 35 35 35 35 A8 10 tg IORDY pulse width max 1250 1250 1250 1250 1250 A8 11 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 29 CS 0 CS 3 DA 2 0 i i i I WS hg
51. gt DIORIDIOW SH pa to D DIOR DIOW CO lt WDATA a Frak t5 te RDATA ta tg IORDY rr Figure 14 PIO Mode Timing Table 28 Multiword DMA Timing Specifications Sym Multiword DMA Timing Parameters Min Max Mode O ns Mode 1 ns Mode 2 ns SpecID to Cycle Time min 480 150 120 A8 12 tc DMACK to DMARQ delay max A8 13 to DIOR DIOW pulse width 16 bit min 215 80 70 A8 14 te DIOR data access max 150 60 50 A8 15 ta DIOR DIOW data setup min 100 30 20 A8 16 tr DIOR data hold min 5 5 5 A8 17 tu DIOW data hold min 20 15 10 A8 18 a DMACK to DIOR DIOW setp min o o 0 Asig ty DIOR DIOW to DMACK hold min 20 5 5 A8 20 tkr DIOR negated pulse width min 50 50 25 A8 21 tkw DIOW negated pulse width min 215 50 25 A8 22 m DIOR to DMARQ delay max 120 40 35 A8 23 i DIOW to DMARQ delay max 40 40 35 A8 24 MPC5200B Data Sheet Rev 4 30 Freescale Semiconductor DMR 4 TAN o Drive oc DMACK Host DIOR DIOW Host RDATA d S Drive WDATA Host Figure 15 Multiword DMA Timing NOTE The direction of signal assertion is towards the top of the page and the direction of negation is towards the bottom of the page irrespective of the electrical properties of the signal Table 29 Ultra DMA Timing Specification MODE 0 MODE 1 MODE 2 Sym ns ns
52. hos DOCU OC OO OO OI NOOO DAO DA1 DA2 l CS 0 1 ESAS Figure 21 Timing Diagram lnitiating an Ultra DMA Data Out Burst MPC5200B Data Sheet Rev 4 Freescale Semiconductor 35 mi tcyc i Lou La ma z tocyc Lt gt HSTROBE I host A l I tovs _ tovs i ipyH gt DVH c gt Ion ra I DD 0 15 pas KA KA KKK HSTROBE i device N A KU Mau XX XXX ODA KKK KKK device Figure 22 Timing Diagram Sustained Ultra DMA Data Out Burst 1 t RP 1 la i DMARQ l device EN DMACK host STOP host i DDMARDY device tRFS A Y HSTROBE X DD 0 15 host LOONA OOOO Figure 23 Timing Diagram Drive Pausing an Ultra DMA Data Out Burst MPC5200B Data Sheet Rev 4 36 Freescale Semiconductor DMARQ N device i i tu i tm l I l DMACK i l i host N ts z t l tack 8 M 1 I STOP y Ni host l I I LI TEL EM gt lioRDYZ DDMARDY y device V I i I d i lack l HSTROBE host X A PN tovs TT toa DD 0 15 i host XXX CRC E AA DAO DA1 DA2 Tack CS 0 1 A XXX Figure 24 Timing Diagram Host Terminating Ultra DMA Data Out Burst DMARQ i device N DMACK host x l t
53. hus unlike a true open drain there is a current path from the external system to the MPC5200B I O power rail if the external signal is driven above the MPC5200B UO power rail voltage 3 System Design Information 3 1 Power Up Down Sequencing Figure 51 shows situations in sequencing the I O VDD VDD IO Memory VDD VDD IO MEM PLL VDD PLL_AVDD and Core VDD VDD CORE oO S VDD IO gt VDD_IO_MEM SDR E VDD 10 MEM DDR taj o ke Q VDD_CORE PLL_AVDD p Time Note VDD CORE should not exceed VDD 10 VDD_IO_MEM or PLL_AVDD by more than 0 4 V at any time including power up Note It is recommended that VDD_CORE PLL_AVDD should track VDD IO VDD IO MEM up to 0 9 V then separate for completion of ramps Note Input voltage must not be greater than the supply voltage VDD IO VDD IO MEM VDD_CORE or PLL AVDD by more than 0 5 V at any time including during power up Note Use 1 microsecond or slower rise time for all supplies Figure 51 Supply Voltage Sequencing MPC5200B Data Sheet Rev 4 64 Freescale Semiconductor The relationship between VDD IO MEM and VDD_IO is non critical during power up and power down sequences VDD_IO_MEM 2 5 V or 3 3 V and VDD_IO are specified relative to VDD_CORE 3 1 1 Power Up Sequence If VDD IO VDD IO MEM are powered up with the VDD CORE at 0 V the sense circuits in the I O pads cause all pad output drivers connecte
54. ies Eight GPIO pins with timer capability supporting input capture output compare and pulse width modulation PWM functions Real time Clock with one second resolution Systems Protection watch dog timer bus monitor Individual control of functional block clock sources Power management Nap Doze Sleep Deep Sleep modes Support of WakeUp from low power modes by different sources GPIO RTC CAN Test Debug features JTAG IEEE 1149 1 test access port Common On chip Processor COP debug port On board PLL and clock generation es Z freescale semiconductor Table of Contents Electrical and Thermal CharacteristicS 4 1 1 DC Electrical Characteristics 4 1 1 1 Absolute Maximum RatingS 4 1 1 2 Recommended Operating Conditions 4 1 1 3 DC Electrical Specifications 5 1 1 4 Electrostatic Discharge 7 tiS Power DISSIPALONI cui aos er ins 7 1 1 6 Thermal CharacteristicS 9 1 2 Oscillator and PLL Electrical Characteristics 10 1 2 1 System Oscillator Electrical Characteristics 11 1 2 2 RTC Oscillator Electrical Characteristics 11 1 2 3 System PLL Electrical Characteristics 11 1 2 4 e300 Core PLL Electrical Characteristics 311 1 3 AC Electrical CharacteristicS 12 1 3 1 AC Test Timing Conditions 12 1 3 2 AC
55. in the table represent the worst case scenario For the VDD MEM 10 rail connected to 2 5 V the lO power is expected to be lower and bounded by the worst case with VDD MEM IO connected to 3 3 V Unloaded typical UO power is measured in Deep Sleep mode at VDD IO VDD_MEM_lOgpp 3 3 V Tj 25 C MPC5200B Data Sheet Rev 4 Freescale Semiconductor 1 1 6 Thermal Characteristics Table 7 Thermal Resistance Data Rating Board Layers Sym Value Unit Notes SpeciD Junction to Ambient Single layer board Roya 30 gw 00 D6 1 Natural Convection 1s Junction to Ambient Four layer board 2s2p Bama 22 ew 09 D6 2 Natural Convection Junction to Ambient 2200 Single layer board Bama 24 Ww M6 D6 3 ft min 1s Junction to Ambient 6200 Four layer board RGJMA 19 TN 049 D6 4 ft min 2s2p Junction to Board Dam 14 C W 4 D6 5 Junction to Case Rejc 8 C W 6 D6 6 Junction to Package Top Natural Convection Ya 2 C W 6 D6 7 1 Junction temperature is a function of die size on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal 3 Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD
56. l 50 pF load MPC5200B Data Sheet Rev 4 Freescale Semiconductor 43 SCK CLKPOL 0 Output SCK CLKPOL 1 Output ss Output MOSI Output MISO Input g Pe a q I TF OX f Ny A 2 2 9 a P 10 lt q NZ ZIL ha Figure 34 Timing Diagram SPI Master Mode Format 1 CPHA 1 Table 39 Timing Specifications SPI Slave Mode Format 1 CPHA 1 Sym Description Min Max Units SpeciD 1 Cycle time 4 1024 IP Bus Cycle A11 31 2 Clock high or low time 2 512 IP Bus Cycle A11 32 3 Slave select to clock delay 15 0 ns A11 33 4 Output data valid 50 0 ns A11 34 5 Input Data setup time 50 0 ns A11 35 6 Input Data hold time 0 0 ns A11 36 7 Slave disable lag time 15 0 ns A11 37 8 Sequential Transfer delay 1 IP Bus Cycle A11 38 1 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 44 Freescale Semiconductor SCK E e N CLKPOL 0 Input 2 clas 2 i SCK CLKPOL 1 TE Input 7 8 bd ed GJ gt SS Input CHE I I I I 6 gt o MOSI Input 4 gt j MISO jj Output KOKA Figure 35 Timing Diagram SPI Slave Mode Format 1 CPHA 1 1 3 13 MSCAN The CAN functions are available
57. l performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales r
58. meters The MPC5200B uses a 27 mm x 27 mm TE PBGA package The package parameters are as provided in the following list e Package outline 27 mm x 27 mm e Interconnects 2 e Pitch 1 27 mm MPC5200B Data Sheet Rev 4 Freescale Semiconductor 57 2 2 Mechanical Dimensions Figure 50 provides the mechanical dimensions top surface side profile and pinout for the MPC5200B 272 TE PBGA package PIN A1 INDEX ax Aolo PA 272X lt C3 0 2 A I E 7 0 35 A NOTES 1 DIMENSIONS AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A D2 e 0 2 OD ABC 4 PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF B THE SOLDER BALLS TOP VIEW MILLIMETERS DIM MIN MAX Le D1 gt A 205 265 Al 0 50 0 70 19X e m A2 0 50 0 70 A3 1 05 1 25 e00000000000000e 0006 I Y gt oa 19x eh 00000000000000000000 w Get 00000000000000000000 v GREEN 60000000000000000000 u SE A 2909 0000 El 24 13 REF 0000 P E2 23330 2470 0000 N e 1 27 BSC oo M 000 L E1 A 0060 K Aa ax e ig2 299 0000 H A3 H 0000 G 0000 F A2 0000 E A
59. mple sample sample sample sample sample sample sample sample LOCK Figure 3 Reset Configuration Word Locking NOTE Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET This may cause problems because it may change the internal clock ratios and so extend the PLL locking process 1 3 5 External Interrupts The MPC5200B provides three different kinds of external interrupts e Four IRQ interrupts e Eight GPIO interrupts with simple interrupt capability not available in power down mode e Eight WakeUp interrupts special GPIO pins The propagation of these three kinds of interrupts to the core is shown in the following graphic MPC5200B Data Sheet Rev 4 Freescale Semiconductor 15 IRQO gt cint 8 GPIOs DIA GPIO Std gt int 8 GPIOs gt GPIO WakeUp E Encoder 94 CORE CINT CORE INT Grouper e300 Core Encoder IRQ1 PX IRQ2 PIs Main Interrupt IRQ3 x Controller Notes 1 Pls Programmable Inputs 2 Grouper and Encoder functions imply programmability in software Figure 4 External Interrupt Scheme Due to synchronization prioritization and mapping of external interrupt sources the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles The following table specifies the interrupt latencies in IP_CLK cycle
60. n tPCick ns A7 55 tio ACK assertion after CS assertion tjpBlck ns 2 A7 56 tja ACK negation after CS negation tPCIck ns 2 A7 57 tja ALE negation to CS assertion tPCIck ns A7 58 tis ACK change before PCI clock 2 0 ns E A7 59 tie ACK change after PCI clock 4 4 ns 5 A7 60 NOTES 1 ACK can shorten the CS pulse width Wait States WS can be programmed in the Chip Select X Register Bit field WaitP and WaitX It can be specified from 0 65535 2 ACK is input and can be used to shorten the CS pulse width 3 Deadcycles are only used if no arbitration to an other module ATA or PCI of the shared local bus happens If arbitration happens the bus can be driven within 4 IPB clocks by an other modules MPC5200B Data Sheet Rev 4 Freescale Semiconductor Pick 1 jJ LJ Lili LJ Li LJ bl AD 31 27 wr Data x AD 30 28 wr X TSIZ 0 2 bits X Data X AD 26 25 wr Bank 0 1 bits X Data D I 1 i AD 24 0 wr D Address 7 31 X Data X AAR ts ite AD 31 0 rd Data jj a DAN ha yl ALE y i Address latch tg I I TS N I ee bo oe Ces OE tio t41 i RW X A i i tie nA t 1 ACK mi A Aa l y 5 cM uH Address tenure Data tenure Figure 13 Timing Diagram MUXed Mode 1 3 9 ATA The MPC5200B ATA Controller is completely software programmable I
61. okyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan Ofreescale com AsialPacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 186 10 5879 8000 support asia freescale com Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 1 303 675 2140 Fax 1 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MPC5200BDS Rev 4 02 2010 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actua
62. on and transmission Local memory SRAM 16 KB 6 Programmable Serial Controllers PSC UART or RS232 interface CODEC interface for Soft Modem Master Slave CODEC Mode IS and AC97 improvements in the design of its products O Freescale Semiconductor Inc 2008 2010 All rights reserved Document Number MPC5200BDS Rev 4 02 2010 VROHS TEPBGA 272 27 mm x 27 mm Full duplex SPI mode IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller FEC Supports 100Mbps IEEE 802 3 MII 10 Mbps IEEE 802 3 MIL 10 Mbps 7 wire interface Universal Serial Bus Controller USB USB Revision 1 1 Host Open Host Controller Interface OHCI Integrated USB Hub with two ports Two Inter Integrated Circuit Interfaces PC Serial Peripheral Interface SPI Dual CAN 2 0 A B Controller MSCAN Implementation of version 2 0A B CAN protocol Standard and extended data frames J1850 Byte Data Link Controller BDLC J1850 Class B data communication network interface compatible and ISO compatible for low speed 125 kbps serial data communications in automotive applications Supports 4X mode 41 6 kbps In frame response IFR types 0 1 2 and 3 supported Systems level features Interrupt Controller supports four external interrupt request lines and 47 internal interrupt sources GPIO Timer functions Up to 56 total GPIO pins that support a variety of interrupt WakeUp capabilit
63. ope time from DMACK to STOP and A8 39 HDMARDY during data out burst initiation tsp 50 30 20 STROBE to DMARDY time if DMARDY is negated A8 40 before this long after STROBE edge the recipient receives no more than one additional data word tnrs 75 60 50 Ready to Final STROBE time no STROBE edges A8 41 are sent this long after negation of DMARDY trp 160 125 100 Ready to Pause time the time recipient vvaits to A8 42 initiate pause after negating DMARDY tionDvz 20 20 20 Pull up time before allowing IORDY to be released A8 43 t ZIORDY 0 0 0 Minimum time drive waits before driving IORDY A8 44 tack 20 20 20 Setup and hold times for DMACK before assertion or A8 45 negation tss 50 50 50 Time from STROBE edge to negation of DMARQ or A8 46 assertion of STOP when sender terminates a burst NOTES 1 tur Iw ti indicate sender to recipient or recipient to sender interlocks That is one agent sender or recipient is waiting for the other agent to respond with a signal before proceeding e ty is an unlimited interlock that has no maximum time value tmu is a limited time out that has a defined minimum tjj is a limited time out that has a defined maximum 2 All timing parameters are measured at the connector of the drive to which the parameter applies For example the sender shall s
64. ow MPC5200B Data Sheet Rev 4 66 Freescale Semiconductor Normally this interface is implemented using a COP common on chip processor connector The COP allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the MPC5200B 3 4 2 e300 COP BDM Interface There are two possibilities to connect the JTAG interface using it with a COP connector and without a COP connector 3 4 2 1 The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale formerly Motorola standard COP BDM interface Table 53 gives the COP BDM interface signals The pin order shown reflects only the COP BDM connector order Table 53 COP BDM Interface Signals Boards Interfacing the JTAG Port via a COP Connector BDM MPC5200B BDM Internal External 1 01 Pin VO Pin Connector Pull Up Down Pull Up Down 16 GND 15 TEST SELO ckstp out EE 14 KEY 13 HRESET hreset 10k Pull Up O 12 GND 11 SRESET sreset 10k Pull Up O 10 N C 9 JTAG_TMS tms 100k Pull Up 10k Pull Up O 8 N C 7 JTAG_TCK tck 100k Pull Up 10k Pull Up O 6 VDD 5 halted 4 JTAG_TRST trst 100k Pull Up 10k Pull Up O 3 JTAG_TDI tdi 100k Pull Up 10k Pull Up O 2 gack O
65. peciD tmem cik MEM_CLK period 7 5 ns A5 8 lvalid Control Signals Address and MBA Valid lmem cik x 0 5 0 4 ns A5 9 after rising edge of MEM_CLK be Control Signals Address and MBA Holdafter tmem em x 0 5 ns A510 rising edge of MEM_CLK DMyalia DQM valid after rising edge of MEM CLK tmem cik x 0 25 0 4 ns A5 11 DMhold DQM hold after rising edge of Mem cik tmem cik x 0 25 0 7 ns A5 12 datavalid MDQ valid after rising edge of MEM CLK tmem cik x 0 75 0 4 ns A5 13 datanolg MDQ hold after rising edge of MEM CLK tmem cik x 0 75 0 7 ns A5 14 MPC5200B Data Sheet Rev 4 18 Freescale Semiconductor I I A A A MEM_CLK T 4 f 4 gt tvalid uei Control Signals Active Y NOP WRITE Y NOP Y NOP NOP NOP NOP pe O UN GEI DMyalig DOM Data Mask 7 T T7777 TITI DMhold f M f WEE datavalid MDQ Data TILT Ki A LLI LH MA Address lvalid lt MBA Bank Selects I T E WE un X 11 11 TT ETAT TTT Walid A thoid IKE UI ec Ia i TIX NI VITATE PTT TTE TE NOTE Control Signals are composed of RAS CAS MEM WE MEM CS MEM CS1 and CLK EN Figure 6 Timing Diagram Standard SDRAM Memory Write Timing 1 3 6 3 Memory Interface Timing DDR SDRAM Read Command The SD
66. pon whether the clock frequency is above 33 MHz 2 Rise and fall times are specified in terms of the edge rate measured in V ns This slew rate must be met across the minimum peak to peak portion of the clock waveform as shown in Figure 9 3 The minimum clock period must not be violated for any single clock cycle i e accounting for all system jitter Table 23 PCI Timing Parameters 66 MHz 33 MHz Sym Description Units Notes SpeciD Min Max Min Max Le CLK to Signal Valid Delay 2 6 2 11 ns 0 3 A6 5 bused signals tya ptp CLK to Signal Valid Delay 2 6 2 12 ns 093 A6 6 point to point ton Float to Active Delay 2 2 ns 1 A6 7 Lon Active to Float Delay 14 28 ns 1 A6 8 tsu Input Setup Time to CLK 3 7 ns 8 4 A6 9 bused signals tau ptp Jinput Setup Time to CLK point 5 10 12 ns 8 0 A6 10 to point th Input Hold Time from CLK 0 0 ns ER A6 11 NOTES 1 See the timing measurement conditions in the PCI Local Bus Specification It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc MPC5200B Data Sheet Rev 4 22 Freescale Semiconductor 2 Minimum times are measured at the package pin with the load circuit and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification 3 REQ and GNT are point to point signals and have different input setup times th
67. re AVDD Power Supply Filtering Each of the independent PLL power supplies require filtering external to the device The following drawing is a recommendation for the required filter circuit 100 STO Power AMMAS AVDD device pin supply JM e 10 uF 200 400 pF Figure 52 Power Supply Filtering 3 3 Pull up Pull down Resistor Requirements The MPC5200B requires external pull up or pull down resistors on certain pins 3 3 1 Pull down Resistor Requirements for TEST pins The MPC5200B requires pull down resistors on the test pins TEST MODE 0 TEST MODE 1 TEST SEL 1 MPC5200B Data Sheet Rev 4 Freescale Semiconductor 65 3 3 2 Pull up Requirements for the PCI Control Lines If the PCI interface is NOT used and internally disabled the PCI control pins must be terminated as indicated by the PCI Local Bus specification This is also required for MOST Graphics and Large Flash Mode PCI control signals always require pull up resistors on the motherboard not the expansion board to ensure that they contain stable values when no agent is actively driving the bus This includes PCI FRAME PCI TRDY PCI IRDY PCI DEVSEL PCI STOP PCI SERR PCI PERR and PCI REQ 3 3 3 Pull up Pull down Requirements for MEM MDQS Pins SDRAM The MEM_MDQS 3 0 signals are not used with SDR memories and require pull up or pull down resistors in SDRAM mode 3 3 4 Pull up Pull down Requirements for MEM_MDQS Pins DDR 16 bit Mode The MEM_MD
68. reescale Semiconductor Table 52 MPC5200B Pinout Listing continued Name Alias Type Power Supply SE Se eg ETH_8 RX_DV y o VDD 10 DRV4 TTL ETH_9 CD RX_CLK UO VDD_IO DRV4 Schmitt ETH_10 CTS COL y o VDD 10 DRV4 TTL ETH_11 TX_CLK UO VDD 10 DRV4 Schmitt ETH_12 RXDIOJ 1 0 VDD 10 DRV4 TTL ETH_13 USB RXD CTS y o VDD 10 DRV4 TTL RXD 1 ETH 14 USB RXP 1 0 VDD 10 DRV4 TTL UART_RX RXD 2 ETH_15 USB_RXN RX 1 0 VDD 10 DRV4 TTL RXDIS ETH_16 USB_OVRCNT 1 0 VDD 10 DRV4 TTL CTS RX_ER ETH_17 CD CRS y o VDD 10 DRV4 TTL IRDA PSC6_0 IRDA_RX RxD UO VDD IO DRV4 TTL PSC6_1 Frame CTS 1 0 VDD 10 DRV4 TTL PSC6_2 IRDA_TX TxD 1 0 VDD IO DRV4 TTL PSC6_3 IR USB CLK BitC VO VDD 10 DRV4 Schmitt Ik RTS USB USB 0 USB OE UO VDD 10 DRV4 TTL USB_1 USB_TXN 1 0 VDD IO DRV4 TTL USB_2 USB_TXP y o VDD IO DRV4 TTL USB_3 USB_RXD 1 0 VDD 10 DRV4 TTL USB_4 USB_RXP y o VDD 10 DRV4 TTL USB_5 USB_RXN 1 0 VDD 10 DRV4 TTL USB_6 USB_PRTPWR 1 0 VDD IO DRV4 TTL USB_7 USB_SPEED 1 0 VDD_IO DRV4 TTL USB_8 USB_SUPEND 1 0 VDD 10 DRV4 TTL USB_9 USB_OVRCNT UO VDD 10 DRV4 TTL Pc l2C 0 SCL y o VDD 10 DRV4 Schmitt 12C_1 SDA y o VDD 10 DRV4 Schmitt 12C_2 SCL UO VDD_IO DRV4 Schmitt MPC5200B Data Sheet Rev 4 Freescale Semiconductor 61 Table 52 MPC5200B Pinout Listing continued
69. s The IP_CLK frequency is programmable in the Clock Distribution Module see Table 16 Table 16 External Interrupt Latencies Interrupt Type Pin Name Clock Cycles Reference Clock Core Interrupt SpeciD Interrupt Requests IRQO 10 IP_CLK critical cint A4 1 IRQO 10 IP_CLK normal int A4 2 IRQ1 10 IP CLK normal int A4 3 IRQ2 10 IP CLK normal int A4 4 IRQ3 10 IP_CLK normal int A4 5 Standard GPIO Interrupts GPIO_PSC3_4 12 IP_CLK normal int A4 6 GPIO_PSC3_5 12 IP_CLK normal int A4 7 GPIO_PSC3_8 12 IP_CLK normal int A4 8 GPIO_USB_9 12 IP_CLK normal int A4 9 GPIO_ETHI_4 12 IP_CLK normal int A4 10 GPIOETHIS 12 IPCLK normal int A411 GPIO ETHI 6 12 IP CLK normal int A4 12 GPIO ETHI 7 12 IP CLK normal int A4 13 GPIO WakeUp Interrupts GPIO PSC1 4 12 IP CLK normal int A4 15 GPIO PSC2 4 12 IP CLK normal int A4 16 GPIO PSC3 9 12 IP CLK normal int A4 17 GPIO ETHI 8 12 IP CLK normal int A4 18 GPIO IRDA 0 12 IP CLK normal int A4 19 DGP INO 12 IP CLK normal int A4 20 DGP_IN1 12 IP_CLK normal int A4 21 NOTES 1 The frequency of IP_CLK depends on register settings in Clock Distribution Module See the MPC5200B User s Manual MPC5200B Data Sheet Rev 4 16 Freescale Semiconductor 2 The interrupt latency descriptions in the table above are related to non competitive non masked but enabled external interrupt sources Take care of int
70. s the bus can be driven within 4 IPB clocks by an other modules PCICLK AS 1 CS x N Ia E x d da ADDR A X Oo B OE l te 1 tz i PUN gt tg d to l DATA rd Ta O gje y bi gt 1 tio ACK N t4 tis lt 13__ TS Figure 12 Timing Diagram Burst Mode MPC5200B Data Sheet Rev 4 26 Freescale Semiconductor 1 3 8 3 MUXed Mode Table 26 MUXed Mode Timing Sym Description Min Max Units Notes SpeciD tesa PCI CLK to CS assertion 4 6 10 6 ns A7 39 tcsN PCI CLK to CS negation 2 9 7 0 ns m A7 40 tALEA PCI CLK to ALE assertion 3 6 ns A7 41 ty ALE assertion before Address Bank 5 7 ns m A7 42 TSIZ assertion b CS assertion before Address Bank 1 2 ns GE A7 43 TSIZ negation ta CS assertion before Data wr valid S 1 2 ns A7 44 t4 Data wr hold after CS negation tipBlek ns A7 45 ts Data rd setup before CS negation 8 5 ns A7 46 tg Data rd hold after CS negation 0 DC 1 xtggg ns 9 A747 t7 ALE pulse width tPCIck ns A7 48 trsa CS assertion after TS assertion 6 9 ns A7 49 tg TS pulse width tPCIck ns m A7 50 tg CS pulse width 2 WS x tegi 2 WS x tecigg ns A751 toEA OE assertion before CS assertion 4 7 ns A7 52 toEN OE negation before CS negation 5 9 ns A7 53 tio RW assertion before ALE assertion liPBIck ns A7 54 t41 RW negation after CS negatio
71. setup time 50 0 ns A11 17 7 Input Data hold time 0 0 ns A11 18 8 Slave disable lag time 15 0 ns A11 19 9 Sequential Transfer delay 1 IP Bus Cycle A11 20 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM NOTE Output timing is specified at a nominal 50 pF load MPC5200B Data Sheet Rev 4 42 Freescale Semiconductor SCK N F T X CLKPOL 0 Input 2 2 SCK CLKPOL 1 d Input S SS ln We lt gt gt pi cp S 6 7 I 4 p gt 4 MOSI X Input i X 4 5 Ap AD E X NE Figure 33 Timing Diagram SPI Slave Mode Format 0 CPHA 0 Table 38 Timing Specifications SPI Master Mode Format 1 CPHA 1 Sym Description Min Max Units SpeciD 1 Cycle time 4 1024 IP Bus Cycle A11 21 2 Clock high or low time 2 512 IP Bus Cycle A11 22 3 Slave select to clock delay 15 0 ns A11 23 4 Output data valid 20 0 ns A11 24 5 Input Data setup time 20 0 ns A11 25 6 Input Data hold time 20 0 ns A11 26 7 Slave disable lag time 15 0 ns A11 27 8 Sequential Transfer delay 1 JIP Bus Cycle A11 28 9 Clock falling time 7 9 ns A11 29 10 Clock rising time 7 9 ns A11 30 Inter Peripheral Clock is defined in the MPC5200B User s Manual MPC5200BUM NOTE Output timing is specified at a nomina
72. t can be programmed to operate with ATA protocols using their respective timing as described in the ANSI ATA 4 specification The ATA interface is completely asynchronous in nature Signal relationships are based on specific fixed timing in terms of timing units nanoseconds ATA data setup and hold times with respect to Read Write strobes are software programmable inside the ATA Controller Data setup and hold times are implemented using counters The counters count the number of ATA clock cycles needed to meet the ANSI ATA 4 timing specifications For details see the ANSI ATA 4 specification and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing See the MPC5200B User s Manual MPC5200BUM The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes e Write data is latched by the drive at the inactive edge of the WRITE strobe This gives ample setup time beyond that required by the ATA 4 specification e Data is held unchanged until the next active edge of the WRITE strobe This gives ample hold time beyond that required by the ATA 4 specification MPC5200B Data Sheet Rev 4 28 Freescale Semiconductor All ATA transfers are programmed in terms of system clock cycles IP bus clocks in the ATA Host Controller timing registers This puts constraints on the ATA protocols and their respective timin
73. top generating STROBE edges tpes after negation of DMARDY STROBE and DMARDY timing measurements are taken at the connector of the sender Even though the sender stops generating STROBE edges the receiver may receive additional STROBE edges due to propagation delays All timing measurement switching points low to high and high to low are taken at 1 5 V MPC5200B Data Sheet Rev 4 32 Freescale Semiconductor DMARQ device tui DMACK device A I tack tenv tes p s gt gt STOP i pem tzAD host ael Ny tack tenv tes lt gt lt gt lt gt HDMARDY re l host lzap ZIORDY gt DSTROBE Ce N device I I taz 4 l tovs jS lt gt Town I I p u 1 Droe Ee XXX DAO DA1 DA2 D CS 0 1 1 Figure 16 Timing Diagram lnitiating an Ultra DMA Data In Burst E tocyc SW I ioe T tcyc i i Ke tocyc a l I DSTROBE I I at device N K oun tovs oun tovs oun gt rer gt diua XX OR at device l i DSTROBE at host d I I I gt ca mu tos Io tos ge Ion DD 0 15 at host KADA XXKXKXK Figure 17 Timing Diagram Sustained Ultra DMA Data In Burst MPC5200B Data Sheet Rev 4 Freescale Semiconductor 33 DMARQ device DMARQ host trp STOP host HDMARDY host inrs
74. u Iw tack ra ja ma gt I STOP host pus i trp I I po Ion 91 DDMARDY TN device i i E I I S gt gt e tRes tu tuu tack I I HSTROBE i f host A x tovs lt gt lt _ tDVH I I 2 OOOO host ORG KX tack DAO DA1 DA2 CS 0 1 i Figure 25 Timing Diagram Drive Terminating Ultra DMA Data Out Burst MPC5200B Data Sheet Rev 4 Freescale Semiconductor 37 Table 30 Timing Specification ata_isolation Sym Description Min Max Units SpeciD 1 ata isolation setup time 7 IP Bus cycles A8 48 2 ata_isolation hold time 19 IP Bus cycles A8 49 DIOR I PA ATA ISOLATION a 1 I q lt a Figure 26 Timing Diagram ATA ISOLATION 1 3 10 Ethernet AC Test Timing Conditions e Output Loading All Outputs 25 pF Table 31 MII Rx Signal Timing Sym Description Min Max Unit SpeciD ty RXD 3 0 RX DV RX_ER to RX CLK setup 10 ns A9 1 b RX_CLK to RXD 3 0 RX_DV RX_ER hold 10 ns A9 2 ta RX_CLK pulse width high 35 65 RX CLK Period A9 3 ta RX_CLK pulse width low 35 65 RX_CLK Period A9 4 1 RX CLK shall have a frequency of 25 of data rate of the received signal See the IEEE 802 3 Specification RX_CLK Input au a RXD 3 0 inputs RX DV RX ER Figure 27 Ethernet Timing Diagram MII Rx Signal MPC5200B Data Sheet Rev 4 38 Freescale Semiconductor Table 32
75. upply voltage System APLL SYS PLL AVDD 0 3 2 1 V D1 3 Supply voltage e300 APLL CORE PLL AVDD 0 3 2 1 V D1 4 Input voltage VDD 10 Vin 0 3 VDD IO 0 3 V D1 5 Input voltage VDD MEM 10 Vin 0 3 VDD MEM IO V D1 6 0 3 Input voltage overshoot Vinos 1 0 V D1 7 Input voltage undershoot Vinus 1 0 V D1 8 Storage temperature range Tstg 55 150 DC D1 9 1 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage 1 1 2 Recommended Operating Conditions Table 2 gives the recommended operating conditions Table 2 Recommended Operating Conditions Characteristic Sym Min Max 1 Unit SpecID Supply voltage e300 core and peripheral VDD CORE 1 42 1 58 V D2 1 logic Supply voltage standard I O buffers VDD IO 3 0 3 6 V D2 2 Supply voltage memory I O buffers SDR VDD MEM lOspn 3 0 3 6 V D2 3 Supply voltage memory I O buffers DDR VDD MEM lOppn 2 42 2 63 V D2 4 Supply voltage System APLL SYS PLL AVDD 1 42 1 58 V D2 5 Supply voltage e300 APLL CORE PLL AVDD 1 42 1 58 V D2 6 MPC5200B Data Sheet Rev 4 4 Freescale Semiconductor Table 2 Recommended Operating Conditions continued Characteristic Sym Min Max 1 Unit SpecID Input voltage standard I O buffers
76. ystem PLL SYS PLL takes an external reference frequency and generates the internal system clock The system clock frequency is determined by the external reference frequency and the settings of the SYS PLL configuration e The e300 core PLL CORE PLL generates a master clock for all of the CPU circuitry The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE PLL configuration MPC5200B Data Sheet Rev 4 10 Freescale Semiconductor 1 2 1 System Oscillator Electrical Characteristics Table 8 System Oscillator Electrical Characteristics Characteristic Sym Notes Min Typical Max Unit SpeciD SYS XTAL frequency fsys xtal 15 6 33 3 35 0 MHz 01 1 Oscillator start up time lup osc 10 ms 01 2 1 2 2 RTC Oscillator Electrical Characteristics Table 9 RTC Oscillator Electrical Characteristics Characteristic Sym Notes Min Typical Max Unit SpeciD RTC_XTAL frequency frtc_xtal 32 768 kHz 02 1 1 2 3 System PLL Electrical Characteristics Table 10 System PLL Specifications Characteristic Sym Notes Min Typical Max Unit SpeciD SYS_XTAL frequency fsys xtal 1 15 6 33 3 35 0 MHz 03 1 SYS_XTAL cycle time ln 1 66 6 30 0 28 5 ns 03 2 SYS_XTAL clock input jitter litter 2 150 ps 03 3 System VCO frequency fycosys 1 250 533 800 MHz 03 4 System PLL relock time tlock 3 100 us 03 5

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