EVBUM2072 - NB4N121KMNGEVB Evaluation Board User`s Manual
Contents
1. KEYSTONE 5016 CON DSUBO9 RAMP 788796 GND Figure 14 Schematic Bypass and Supply Connector Details http onsemi com 10 NB4N121KMNGEVB Appendix 3 Device Iperf Pin 1 Load Plot of vs Iperf Current IREF 32 30 28 26 24 22 20 18 16 14 50 29 3 mA 3 0 V 3 3 V 20 C 14 54 mA 27 15 mA 15 06 mA 28 66 mA 85 C 14 92 mA 27 42 mA 15 42 mA 29 33 mA 130 C 15 05 mA 26 93 mA 14 60 mA 29 25 mA 3 6 V 15 65 mA 29 97 mA 15 86 mA 30 60 mA 16 03 mA 30 80 mA lyp 1 KQ 15 4 mA 10 Figure 15 Device Ipgr 1 Load Plot of Rrer VS Iggr Current 20 30 Rrer hitp onsemi com 11 40 50 NB4N121KMNGEVB Appendix 4 Bill of Materials Board Lamination Stackup and Fabrication Notes Bill of Materials Table 5 Cap Chip 0 1 uF 0 1 uF C1 C4 C5 C6 C7 0603 50 V 10 X7R Cap Chip 10 uF 10 uF C2 C3 Tant C 25 V 10 ANTARES 52 QFN FPO052QNO805C Alternative construction option Socket ANTARES Test Technology 3350 Scott Blvd Bldg 58 Santa Clara CA 95054 Phone 408 988 6800 www antares att com ps pomme p s poem earn oie orang 46 Connector SMA Johnson 142 0701 201 J1 J2 J3 J4 J5 J6 J7 J8 J10 J11 J12 Straight J13 14 15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J332. 10 12 14 16 18 20 22 Q 20 0 HCSL Output INVERT 24 27 29 31 33 35 37 40 Output 42 44 46 48 50 9 11 13 15 17 19 21 23 Q 20 0 HCSL Output TRUE 25 28 30 32 34 36 38 41 Output 43 45 47 49 51 Exposed Pad EP Exposed Pad The thermally exposed pad EP on package bottom see case drawing must be attached to a sufficient heat sinking con duit for proper thermal operation Note 1 hitp onsemi com 6 NB4N121KMNGEVB Appendix 2 Schematics J3 N CON SMA ST wu J4 CON SMA ST CBE J7 CON SMA ST wy Veco J8 CON SMA ST el J37 SMA ST POTBOU3269W0 50 ml O03 38i pU T 13 otk 5 LK N CON_SMA_ST ES V SZ Qoo gis 19 J10 CON SMA ST Q18 Q18 DNI R50 DNI R44 DNI E R48 2 R45 Shas J41 CON SMA ST As J42 CON SMA ST GE DNI R46 Enn J11 CON SMA ST Figure 10 Pins 1 to 13 http onsemi com 7 NB4N121KMNGEVB Figure 11 Pins 14 to 26 hitp onsemi com NB4N121KMNGEVB Figure 12 Pins 27 to 39 http onsemi com 9 NB4N121KMNGEVB 0 H ING vey ING 9 H ING LSH ed ES S ES ESL ES ES ES ES ES ES ES ES Ro S OOo 1 Ie geo ge 99 FQQoo 98 oo N NO OG amp Sag Figure 13 Pins 40 to 52 V V V CCO rg TP2 KEYSTONE 5016 Voc 1 7 C6 C1 2 C4 KEYSTONE 5016
3. aras CIRCUITS euo ate OTT L Figure 1 Front Front Notes 1 Veco and contacts must be ganged and connected together to the positive 3 3 V supply 2 CLKszr is not used SMA Back Notes 1 C2 and C3 are power supply caps 2 Rggr trimpot is connected from Iggr to GND to select output drive for 1X 0 to 1 k 2 Short to GND or 2X loading 20 K to 50 Open or Short to Vcc See Appendix 3 Device Iggr pin 1 load plot of vs Iggr current C2 and C3 Power Supply Caps h 4 4 7 8 _ oe oe Trimpot at ate 0050 kQ Y Sa wirt D e ie LI t e EI s fee ese oe 7 t oon uv a J T N t oe oe Pee e t a e a o e ee Figure 2 Back 3 Back D U T area detail See Figure 3 Odd numbered resistors R17 to R81 are populated for 1X load Even numbered resistors are not populated The even numbered resistors may be repopulated with 50 Q to GND components to convert the board to 2X load use with 50 Q scope input impedance loading presents a 25 2 parallel load to the device outputs Even numbered series shorting resistors R17 to R81 are populated zero ohm value These may be repopulated with a series resistor value to improve signal integrity Components C1 C4 C5 and C7 are
4. APPROVAL 10046 continuity and isolation test required for each fabricated PCB Final test data must be cross referenced to the IPC D 356 file provided A verification stamp is required on each PCB A TDR report shall be provided for each impedance controlled layer at the time of shipment Final acceptance shall be determined by these layers having a characteristic impedance of 50 ohms 10 Vendor can make line width adjustments on impedance controlled conductor widths of 0 0005 other artwork deviations must have prior approval from R amp D ADC ON Semiconductor and Q are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the righ
5. in per linear inch 10 5 PLATING Copper thickness for internal and external layers is specified in the stacking diagram Finished PCB to be electrodeposited hard gold plate type 1 99 7 min gold grade C knoop 11 hardness 130 200 class X 3 10 micro inches thick over entire board surface 12 Selective plating is not required Hole Plating 0 011 minimum barrel avg 0 009 absolute minimum Absolute maximum to be determined by PCB vendor based on the required finished hole diameter Hole diameters are after plating unless otherwise specified 5 1 Surface pads in this area to be free from any irregularities or defects that might hinder proper performance of the pad 6 ANNULAR RING Annular ring to be 0 005 minimum with top to bottom registration to be within 0 003 SOLDERMASK Apply soldermask color green type LP1 per artwork provided If VIA plugs are required plug pattern will be supplied with artwork SILKSCREEN To be white non conductive ink per artwork No ink is to be on plated thru hole or surface mount pads Silkscreen lines and text width are to be 0 006 minimum SOLDERABILITY Plated holes shall not be rough or irregular so as to prevent proper solder wicking DRILL CHART Hole sizes specified are finished hole sizes unless otherwise specified Standard plated hole tolerance is 30 003 Standard non plated hole tolerance is 0 002 IMPEDANCE Impedance controlled layers 1 6
6. 0 01 uF bypass caps http onsemi com 2 NB4N121KMNGEVB Test and Measurements Setup Details Step 1 Basic Equipment Signal Generator Voltmeter Oscilloscope Matched High Speed Coax Cables with SMA Power Supply Connectors Step 2 Board Test Connections Setup 1X Load configuration Inge pin shorted to GND Veco Note 1 Signal NB4L121K Oscilloscope Generator VTCLK Figure 4 NBAN121KMNGEVB Evaluation Board Connector Configuration Table 1 Power Supply Connections Positive and GND supplies must be connected to anvil clips for proper operation Bridge Vcc and board connection together Veo E Note 1 3 010 3 6 V 7 26 39 52 Note 2 Rrer to For 1x m 0 to 50 kQ For 2x loading 20 K to 50 kQ EXPOSED PAD Vias GND Thermal Conduit Exposed Pad 1 Short together and connect to Vcc supply See Appendix 4 Board Lamination Stackup 2 See Appendix 3 Device Inge 1 Load Plot of Rrer vs Igge Current http onsemi com 3 NB4N121KMNGEVB Table 1 Input Output Board to Device Pin Connections CLK CLK de imu n A 8 8 r N JBE j O JHE Cl aj ge EIE ol ol A 0 2 a AB AB E o oo N n 2 o 3j 3 aj BR oO Py Input Pins an
7. J34 J35 J36 J37 J38 J39 J40 J41 J42 J48 J49 J50 J51 J52 CON DSUBO9 J43 Optional Not Supplied RAMP 788796 Res Chip 0 R1 R3 R5 R7 R9 R11 R13 R15 R17 0603 1 16 W 5 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 R51 R53 R55 R57 R59 R61 R63 R65 R67 R69 R71 R73 R75 R77 R79 R81 R83 0 50 kQ BOURNS 3269W 1 503 R85 POTENTIOMETER TOP ADJUST Board Lamination Stackup Dielectric is FR4 interlayer between 1 2 2 3 3 4 4 5 5 6 Layers 1 Topside and 6 Bottomside are signal path copper trace width 0 014 LAMINATION DIAGRAM Layer Layer Copper Dielectric Layer Trace Number Name Thickness Thickness Material Width TOP 1 2 OZ 0 014 DIE ALa i A 2 GND 1 OZ LLLILLLLLLLLLLLLL LL 0 005 CL ENA LLY PWR1 1 OZ LLLLLLLLLLLLLLLLL LL SLL eR e LL 4 PWR2 1 OZ LLLLLLL LLL LLLLLLL 9005 SL S 4 5 GND 1 OZ VLLLILLLLLLLLLLLLL LL SAB LL ENA SLL BIN 1 2 OZ FINISHED PCB THICKNESS TO BE 0 100 10 hitp onsemi com 12 NB4N121KMNGEVB Board Fabrication Notes Unless otherwise specified d 1 ARTWORK Fabricate using ADC artwork No AZ10035 Rev A Drill locations determined by ADC file AZ10035NC DRL 8 2 MATERIAL High temp FR4 170 C Tg 3 BOARD THICKNESS Refer to stacking diagram for finished board thickness 9 4 TWIST AND WARP Board twist shall not exceed 0 5 0 005
8. NB4N121KMNGEVB NB4N121KMNGEVB Evaluation Board User s Manual Board Name NBAN121KMNGEVB Device Name NB4N121KMN Description The NB4N121K Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the performance and operation of the device under test NB4N121K The NB4N121K is a Clock differential input fanout distribution device with 1 to 21 HCSL level differential outputs optimized for ultra low propagation delay variation The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind Inputs can accept differential LVPECL CML or LVDS levels Single ended LVPECL CML LVCMOS or LVTTL levels are accepted with the proper VmgrAc supply Clock input pins incorporate an internal 50 on die termination resistors Output drive current at Iggr Pin 1 for 1X load is selected by connecting a 0 k 2 to 1 k 2 external resistor to GND To drive a 2X load connect the Pin 1 through 20 to 50 kQ external resistors The NB4N121K specifically guarantees low output to output skews Optimal design layout and processing minimize skew within a device and from device to device System designers can take advantage of the NB4N121K s performance to distribute low skew clocks across the backplane or the motherboard The device is packaged in a low profile 8 x 8 mm 52 pin QFN package This user s manual provides detailed information on the board s
9. ad Zo 50 Q Zp 502 ChP 2 pF Figure 8 Output Loading Diagram Rgi 0 Q Rggr 0 1 for 1X Load 20 K 50 K for 2X Load Rix may be open for 1X load supplied by scope input module may be 50 Q for 2X load to present a 25 Q load with scope 50 input module impedance http onsemi com 5 NB4N121KMNGEVB gt 35 65b SRBSEE SE exposed Dag EF 51 50 49 48 47 46 45 44 43 42 41 IREF _ Voc GND Jae VTCLK a6 CLK CLK O7 VTCLK as NB4N121K Voc _ a8 E e 5 O o Gc IS E O Oc Figure 9 Pinout Diagram Table 2 PIN DESCRIPTION me 10 mpm 1 IREF Output Output current programming pin to select 1X or 2X load Connect a selected resistor from IREF pin to GND See Appendix 3 Device IREF pin 1 load plot of vs Inge current 2 GND Supply Ground GND pin must be externally connected to power sup ply to guarantee proper operation 3 6 VTCLK Internal 50 2 Termination Resistor connection Pins In the differential VTCLK configuration when the input termination pins are connected to the common termination voltage and if no signal is applied then the device may be susceptible to self oscillation 4 CLK LVPECL CLOCK Input TRUE Input 5 CLK LVPECL CLOCK Input INVERT Input 7 26 39 52 Positive Supply pins Vcc pins must be externally connected to a power supply to guarantee proper operation 8
10. contents layout and use The manual should be used in conjunction with the NB4N121K data sheet which contains full technical details on device specifications and operation Semiconductor Components Industries LLC 2012 February 2012 Rev 2 ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Board Features Fully assembled evaluation board with Device Under Test DUT soldered mounted The device may be demounted and replaced by a test fixture socket ANTARES Test Technology P N FP00520N0805C 3350 Scott Blvd Bldg 58 Santa Clara CA 95054 Phone 408 988 6800 www antares att com for manual insertion of different sample device units Accommodates the electrical characterization of the NB4N121K in the OFN52 package Equal length input and output data lines to minimize skew measurement calibration Default 1X output drive 50 Q load with optional 2X load capability 25 Q load selectable by installing pulldown resistors and adjusting board Rggr setting on Ingr pin1 Adjustable Rggr resistor potentiometer for fine tuning output drive current amplitude levels e Single 3 3 V Operation for direct LOW Impedance probe connection 50 Q to GND Appendix 1 Device Information Appendix 2 Schematics Appendix 3 Iggr Pin Load Plot Appendix 4 Bill of Materials Board Stackup Publication Order Number EVBUM2072 D NB4N121KMNGEVB Board Map Voc and GND Supply Connections
11. d Signals CLK and CLK pins require differential LVPECL levels swinging around an acceptable common mode voltage per datasheet Internal impedance matching resistor of 50 Q is provided for driver termination from input pin to the respective VTx pin Typically the VTx pins are connected to a VTT of Vcc 2 0 V The differential inputs can be driven single ended per the datasheet Output Pins and Signals Output pairs in use must always be balance in each pins loading and termination even if only one side of an output pair is delivered to receiver or scope Do not unbalance an output pair by loading or probing only one line Unused outputs should be left floating open The Rs resistors values are zero Q but may be changed to value such as 6 to 12 Q to improve signal integrity For loading set Rggr potentiometer between 0 and 1 to GND for 1X loading see Appendix 1 Device Ing pin 1 load plot of Rggr vs Iger current For 50 Low Impedance probes with High Bandwidth gt 1 GHz The odd numbered Serial Resistors R17 to R81 positions are populated with zero resistors The even numbered Parallel Loading resistors R18 to R82 should not be populated open Scope module inputs will provide proper termination 50 Q to GND Un probed outputs will need to be externally loaded with 50 Q to GND for proper balanced operation For High Impedance Probes low input capacitance probe with High Bandwidth gt 1 GHz odd numbered Series Resist
12. installed odd numbered 50 2 Resistor value will present a 25 Q load to the device Un probed outputs will need to be externally loaded with 25 Q to GND for proper operation High Impedance Probes Use a high impedance low input capacitance probe with High Bandwidth gt 1 GHz and repopulate odd numbered Resistors R18 to R82 25 value Step 3 Electrical Measurements Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm Electrical parameters are guaranteed only over the declared operating temperature range Functional operation of the device exceeding these conditions is not implied Device specification limit values are applied individually under normal operating conditions and not valid simultaneously APPENDIXES Appendix 1 Device Information Device Under Test NB4N121K Package Case Identification Device Marking Diagram Device Function Diagram Output Loading Diagram Pinout Diagram a Pin Description 52 CASE 485 MN SUFFIX Figure 5 Package Case Identification Qo Qo Q1 Q19 Q19 Q20 GND Figure 7 Device Function Diagram MARKING DIAGRAM 52 XXXXXXXXX XXXXXXXXX AWLYYWWG XXXXXXXXX Device Code A Assembly Site WL Wafer Lot YY Year WW Work Week G Pb Free Package Figure 6 Device Marking Diagram 1X Lo
13. ors positions R17 to R81 are populated with 0 Q value components The even numbered Parallel Loading resistors R18 to R82 should also all be populated with 50 Q to GND components for proper termination For 2X loading set the Rggr between 20 and 50 to GND or tie Ipgp directly to For 50 Low Impedance probes with High Bandwidth gt 1 GHz the odd numbered Serial Resistors R17 to R81 positions should be populated with zero value components All even numbered Parallel Loading resistors R18 to R82 should have 50 value components installed A typical scope probe 50 Q impedance in parallel with the installed even numbered Parallel Loading 50 Q resistors R18 to R82 will present a 25 2X load to the device Un probed outputs will need to be externally loaded with 50 Q to GND to present the proper 25 2 load to the device For High Impedance Probes low input capacitance probe with High Bandwidth 21 GHz odd numbered Series Resistors positions R17 to R81 are populated with 0 value components The even numbered Parallel Loading resistors R18 to R82 should also all be populated with 25 to GND components for proper termination Low Impedance Probes Use 50 Q Low Impedance probes with High Bandwidth gt 1 GHz The odd numbered Resistors R18 to R82 positions should be populated with 50 value components http onsemi com 4 NB4N121KMNGEVB A typical scope probe 50 impedance in parallel with the
14. ts of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 E l Fa
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