Home

Using as

1. 163 8 127 2 3 Addressing Modes 164 8 127 3 SH64 Machine Directives 164 8 27 4 QOpcodes cese eet eds 164 SPARC Dependent Features ooooooooomoooo 166 8 128 5 Options obese e e e ved x n bed es 166 8 128 6 Enforcing aligned data suuuess 166 8 1287 Floating Points ed od o e 167 8 128 8 Sparc Machine Directives 167 TIC54X Dependent Features oooooooooooomoo 168 8 129 9 Options 0 eee teens 168 8 129 10 Block compra diet edad widen 168 8 129 11 Environment Settings 04 168 8 129 12 Constants Syntax 0 0 eee eee 168 8 129 138 String Substitution 00 168 8 129 14 Local Labels acer eye tada 169 8 129 15 Math Builtins 000008 169 8 129 16 Extended Addressing 171 3 129 17 DireCtives vico tii sae oe ee e 171 9 129 18 Madrona ets 176 8 129 19 Memory mapped RegistersS o o IT 48000 Dependent Features oooooocmooomoomo 178 8 130 20 OptlonS ce sk hn pce c Re 178 8 130 21 Syntax ke RR Ree eb ERREUR 178 8 130 21 1 Special Characters 178 8 130 21 2 Register Names 178 8 130 21 3 Addressing Modes 178 8 130 22 Assembler Directives for the Z8000 179 ix x 8 130 23 Opcodes 0 cece neta 179 8 131 VAX Dependent Features ooooocoo
2. 184 VAX branch improvement 182 VAX command line options ignored 180 VAX displacement sizing character 183 VAX floating point oso er pels 181 VAX immediate character 183 VAX indirect character 222200 183 VAX machine directives 0004 181 VAX opcode mnemonics 182 VAX operand notation ss esses 183 VAX register Names 0ooooooooooooomoo 183 VAX SUDDOEPL ii cee me de irene dade 180 Vax 11 C compatibility o oo o o o o o 180 VAX VMS options 0 000 005 180 version directive oooo oooooocooommm o 65 version directive TIC54X 176 version of assembler 002 eee 20 versions of symbols cosses inire ia 62 visibility 22 bees e RC RRPAS 48 50 56 VMS VAX options 0 00 180 vtable traicion 65 vtable inherit aia 65 W warning for altered difference tables 16 warning messages sese 14 warnings causing error lesse 20 warnings M32IU 2x e ERREUR bs 124 warnings suppressing lessen 20 warnings switching 00 0ooooocoocoooooo 20 weak directive ooococoooccoococcoooo 65 Wwhibespace us cra bri PERDE APER IE HEP 21 whitespace removed by preprocessor 21 wide floating point directives VAX 181 width directive TICBAX 173
3. 38 MIPS architecture options 139 MIPS big endian output 2 139 MIPS debugging directives 142 MIPS ECOFF sections 142 MIPS endianness oso opacedeseninesgeneisesizay de 8 MIPS ISA a dis bac A 8 MIPS ISA override o o oocccccccooooco nis 142 MIPS little endian output 0 139 MIPS MDMX instruction generation override IS OS 143 MIPS MIPS 3D instruction generation override Nea REO 143 MIPS option stack i22 aspas ese diene est 143 223 MIPS proGessOr ces arm EE de 139 MIT za seid tea doa pace Feu en des E dg Dac o OR Boe 128 mlib directive TICBAX 174 mlist directive TIC54X o o o o o 174 MMIX assembler directive BSPEC 149 MMIX assembler directive BYTE 148 MMIX assembler directive ESPEC 149 MMIX assembler directive GREG 148 MMIX assembler directive IS 147 MMIX assembler directive LOC 147 MMIX assembler directive LOCAL 147 MMIX assembler directive OCTA 148 MMIX assembler directive PREFIX 149 MMIX assembler directive TETRA 148 MMIX assembler directive WYDE 148 MMIX assembler directives 147 MMIX line comment characters 146 MMIX Options 65 144 MMIX pseudo op BSPEC 149 MMIX pseudo op BYTE
4. 127 M680x0 branch improvement 131 M680x0 directives lesse eere 131 M680x0 floating POlMtb 0ooooocccoccooooooo 130 M680x0 immediate character 132 M680x0 line comment character 132 M680x0 opcodes ssssseeeeeesersene 131 M680x0 options cece eee eee eee 126 M680x0 pseudo opcodes 00 000s 131 M680x0 size modifierS 0ooo ooooooooo 128 M680x0 SUPDO Coroico 126 MOSOXO Syb ici toue di 128 M68HC11 addressing modes 134 M68HC11 and M68HC12 support 133 M68HC11 assembler directive far 136 M68HC11 assembler directive interrupt 136 M68HC11 assembler directive mode 136 M68HC11 assembler directive relax 136 M68HC11 assembler directive xrefb 136 Index M68HC11 assembler directives 136 M68HC11 branch improvement 137 M68HC11 floating point 136 M68HC11 modifierS oo oooooccooocmm o 135 M68HC11 opcodesS occcococcccccccc o 137 M68HC11 options ooocccooccooocoooo 133 M68HC11 pseudo opcodes 02 04 137 M68HCII Syntax Re ete 134 M68HC12 assembler directives 136 M88K support iolecmd cides e 138 machine dependencieS 0oooocooooommoo 67 machine directives AMD 29K 69 machine directives ARC 02005 78 machine directives ARM
5. 198 literal prefix directive 0 198 little endian output MIPS 8 little endian output PJ 00 eee ee eee T little endian output MIPS 139 In directives ots pits entes 52 lo pseudo op V850 lsssseeeesseeeess 188 local common symbols 0005 51 local labels retaining in output 16 local symbol names 00 00002000 33 location Counter ire eee ee Geddes 35 location counter advancing 54 logical file AMES eser ri 47 l gical line number 5 22 porta s 51 logical line numbers 000000 22 long directive cees miri leery oad ak eee 53 long directive ARC coco cnica ea 78 long directive 1386 02 06 rese bene ra 112 long directive TICBAX o oooo mmmoooo o 173 long directive x86 64 oooooommooooo 112 longcall pseudo op V850 189 longcalls directive eee 197 longjump pseudo op V850 189 loop directive TIC54X ooommoooooo 174 LOOP instructions alignment 193 lp register V850 isis see etre stem ia 186 Ivar ti cade 179 M32R architecture options 123 M32R directives herb eme 123 M32HR OptiOBDS ure RE ER rer ene des 123 M32R SUpDOEFb ure Re Re vine pF EIS 123 MZ warnlngs 2eeck ih reb ire ss 124 M680x0 addressing modes 129 M680x0 architecture options
6. 107 8 112 15 Instruction Naming 0 108 8 112 16 Register Naming oo oooocooccoocooo 108 8 112 17 Instruction Prefixes 0oo ooooooo oooo 109 8 112 18 Memory References 0ooooocoooocoooo 110 8 112 19 Handling of Jump Instructions JT 8 112 20 Floating Point 0005 111 8 112 21 Intel s MMX and AMD s 3DNow SIMD Operations coria red hes te RR RR RR ERE 112 8 112 22 Writing 16 bit Code 112 8 112 238 AT amp T Syntax DUgS 0oooccccoocccocoo 113 8 112 24 Specifying CPU Architecture 113 8 112 2b Notes cio emere tee eee 114 Intel i860 Dependent Features o o oooooocccoooo o o 115 8 113 26 i860 Notes sssssseesssse nnn 115 8 113 27 1860 Command line Options 115 8 113 27 1 SVRA4 compatibility options 115 8 113 27 2 Other options 115 8 113 28 i860 Machine Directives 115 8 113 29 i860 Opcodes eaa eee ee eee 116 8 113 29 1 Other instruction support pseudo instructions oo oooo oo o 116 Intel 80960 Dependent Features oooooooococoooo 118 8 114 30 i960 Command line Options 118 8 114 31 Floating Point suisses ess 119 8 114 32 1960 Machine Directives 119 8 114 33 1960 Opcodes 0 eee eee eee 120 8 114 33 1 call oet tr e i une 120 8 114 33 2 Compare and Branch
7. 177 symlen subsym builtin TIC54X 177 tan math builtin TIC54X reg tanh math builtin TIC54X dl trunc math builtin TIC54X il option VAX VMS oooccccccoccccco 181 atea buses steh Lahn ict segre rt 12 2232 option 1386 perrin ped bert eR Id 107 2232 option K86 04 oes cest rm esed 107 213 64 option 1380 si oak eee as vate ee a s 107 64 option X8G GA esperese iiaei esee 107 base size default 16 126 base size default 32 126 bitwise or option M680x0 126 CONSTTUCtHHOStS esi creda ia se 141 o A edd eit wee 191 disp size default 16 126 disp size default 32 126 emulation crisaout command line option A a dented Opn Geist Met Erde Ds 83 emulation criself command line option CBS cu ties een ERES M b E d 83 enforce aligned data 166 ccfatal warnlings c i isses dud di 20 fixed special register names command line option MMIX cee eee eee 144 force long branchs 4 134 generate example 00 eee 134 CEOIOElCS dssrdcdcas suede deeded de KE ipes 191 globalize symbols command line option MMIX 0t ee bbc enmt ei dad ido eet 144 gnu syntax command line option MMIX 144 linker allocated greg
8. 2 81 machine directives H8 300 none 97 machine directives H8 500 none 99 machine directives 1860 o o ooo 116 machine directives 1960 o oooooo ooooo 119 machine directives MSP 430 152 machine directives SH oo oooooo ooooo 161 machine directives SH64 0o ooo o o ooooo 164 machine directives SPARC 167 machine directives TIC54X 171 machine directives V850 000005 187 machine directives VAX 0 181 machine independent directives 41 machine instructions not covered 12 machine independent syntax 21 Macro directives sve dd 53 macro directive TIC54X 0 5 174 MACTOS icine beeen eb ete eq pvp epus 53 Macros AMD 29K ow sccctege cece anes es 68 macros count executed lies eeeee eese 54 Macros MSP 430 cero rennes 151 macros LIODAX esse tere RR RR RS 176 Make TUES s ce uerb dale Rep dvd s 19 manual structure and purpose 11 math builtins TIC54X 0 170 Maximum number of continuation lines 17 memory references i886 05 110 memory references x86 64 110 memory mapped registers TIC54X 177 merging text and data sections 19 messages from assembler 004 14 minus permitted arguments
9. 85 8 106 D10V Dependent Features ooooooooorooromo o 87 8 106 25 D10V Options 0 cece eee 87 8 100 20 AA ae eee eth ls ERR 87 vi 8 107 8 108 8 109 8 110 8 111 8 106 26 1 Size Modifiers ooooooooo ooo 87 8 106 26 2 Sub Instructions 87 8 106 26 3 Special Characters 88 8 106 26 4 Register Names 88 8 106 26 5 Addressing Modes 89 8 106 26 6 WORD Modifier 90 8 106 27 Floating Point ssesse sese 90 8 106 28 Opcodes 0 ccc cece eee 90 D30V Dependent Features ooooooooocroomoo 91 8 107 29 D30V Options 0 0 eee eee 91 8107 30 Syntax ic ad 91 8 107 30 1 Size Modifiers ooooooooo ooo 91 8 107 30 2 Sub Instructions 91 8 107 30 3 Special Characters 91 8 107 30 4 Guarded Execution 92 8 107 30 5 Register NameS o o o oooooo 93 8 107 30 6 Addressing Modes 94 8 107 31 Floating Point 0 0 00 eee 94 107 32 OpeodeSus eds ca nee tI lea 94 H8 300 Dependent Features 0ooooooccoococoococoo 95 8 108 1 Options 0 cece s 95 IS onder dais es dad pa e ORE ea eee a 95 8 108 2 1 Special Characters 95 8 108 2 2 Register Names 0 95 8 108 2 3 Addressing Modes 95 8 108 3 Floating Point se ess
10. can be used instead of a newline to separate statements Since has no special meaning you may use it in symbol names Registers can be given the symbolic names r0 r15 fp0 fp2 fp4 fp6 By using thesse symbolic names as can detect simple syntax errors The name rarg or r arg is a synonym for r11 rtca or r tca for r12 sp r sp dsa r dsa for r13 lr or r lr for r14 rbase or r base for r3 and rpgt or r pgt for r4 is the current location counter Unlike it is always relative to the last USING di rective Note that this means that expressions cannot use multiplication as any occurrence of will be interpreted as a location counter All labels are relative to the last USING Thus branches to a label always imply the use of base displacement Many of the usual forms of address constants address literals are supported Thus using r3 L ri5 A some routine LM r6 r7 V some longlong extern Chapter 8 Machine Dependent Features 105 A r1 F 12 AH r0 H 42 ME r6 E 3 1416 MD r6 D 3 14159265358979 D r6 XL4 cacad0d0 ltorg should all behave as expected that is an entry in the literal pool will be created or reused if it already exists and the instruction operands will be the displacement into the literal pool using the current base register as last declared with the using directive 8 111 10 Floating Point The assembler generates only IEEE floating poi
11. or a prefix operator followed by an argument 6 2 2 Operators Operators are arithmetic functions like or Prefix operators are followed by an argument Infix operators appear between their arguments Operators may be preceded and or followed by whitespace 38 Using as 6 2 3 Prefix Operator as has the following prefix operators They each take one argument which must be absolute Negation Two s complement negation Complementation Bitwise not 6 2 4 Infix Operators Infix operators take two arguments one on either side Operators have precedence but operations with equal precedence are performed left to right Apart from or both arguments must be absolute and the result is absolute 1 Highest Precedence Multiplication Division Truncation is the same as the C operator Remainder lt lt lt Shift Left Same as the C operator lt lt gt gt gt Shift Right Same as the C operator gt gt 2 Intermediate precedence Bitwise Inclusive Or amp Bitwise And Bitwise Exclusive Or Bitwise Or Not 3 Low Precedence Addition If either argument is absolute the result has the section of the other argument You may not add together arguments from different sections Subtraction If the right argument is absolute the result has the section of the left argument If both arguments are in the same section the result is absolute You may
12. the current location In addition to the common forward and backward local symbol formats see Section 5 3 Symbol Names page 33 they can be specified with upper case B and F as in 8B and 9F A local label defined for the current position is written with a H appended to the number 3H LDB 0 1 2 This and traditional local label formats cannot be mixed a label must be defined and referred to using the same format There s a minor caveat just as for the ordinary local symbols the local symbols are translated into ordinary symbols using control characters are to hide the ordinal number of the symbol Unfortunately these symbols are not translated back in error messages Thus you may see confusing error messages when local symbols are used Control charac ters 003 control C and 004 control D are used for the MMIX specific local symbol syntax The symbol Main is handled specially it is always global By defining the symbols __ MMIX start text and __ MMIX start data the ad dress of respectively the text and data segments of the final program can be defined though when linking more than one object file the code or data in the object file containing the symbol is not guaranteed to be start at that position just the final executable See MMIX loc page 147 8 121 12 3 Register names Local and global registers are specified as 0 to
13. o oooooommocorooooo 186 equ directive ces aer ra Wie add ge adios 46 equ directive TIC54X o oo ooooooooo 174 equiv directive ees pericias ro daa 46 err difectlve curada ta des 46 error messages eenrsbsg ia a 14 error on valid input ad Ro 201 errors caused by warnings 20 errors continuing after 00 20 ESA 390 floating point IEEE 105 ESA 390 support lessen 104 ESA 390 Syntax ccc tmn 104 ESA 390 only directivesS 0oooooocccoccoo 105 escape codes character s esses 24 eval directive TIC54X uuueeuuus 172 2 P 179 even directive M68BO0x0D ooooocooocooooo 131 even directive TIC54X 0 0000 TZL exitm directe iron ee eRe 54 expr internal section 000000 29 expression arguments see en hn 37 expressions ix IR ERR dead Soa EIER a eee 37 expressions comparison sese esee 38 expressions empty ssseeeeee eee eee 3T expressions integer oooooooocorcoooo 37 extAuxRegister directive ARC 78 extCondCode directive ARC 78 extCoreRegister directive ARC 78 extend directive M680x0 0000 130 extend directive M68HC11 137 extended directive 1960 0 o oo o ooooo 119 extern directive 0 cece ee eee ee eee 46 extInstruction directive ARC 78
14. 148 MMIX pseudo op ESPEC 149 MMIX pseudo op GREG ssssss 148 MMIX pseudo op IS 0 0 eee eee 147 MMIX pseudo op LOC sssse 147 MMIX pseudo op LOCAL 147 MMIX pseudo op OCTA Luuuuue 148 MMIX pseudo op PREFIX 149 MMIX pseudo op TETRA 148 MMIX pseudo op WYDE 148 MMIX pseudo ops 0 0 eene 147 MMIX register names 4 146 MMIX s pport 25erieeI d Beretee pede das 144 mmixal differences o ooooooooooooo 149 mmregs directive TIC54X 174 mmsg directive TIC54X 0005 172 MMX 1380 rp Reed o opa 112 MMX x80 04 casio ra eere 112 mnemonic suffixes 1386 o o o oooooo o o o 107 mnemonic suffixes x86 64 ooo ooooo 107 mnemonics for opcodes VAX 182 mnemonics D10V 0 cee e ee eee 90 mnemonics D8OV su intra A 94 mnemonics H8 300 ssseesseesesese 97 mnemonics H8 500 0000 eee eee ee 99 mnemonics SH coca 161 mnemonics 5H64 oucoccoccancr Rl eee 165 mnemonics Z8000 2 eee eee eee eee 180 mnolist directive TIC54X 174 Motorola syntax for the 680x0 129 MOVI instructions relaxation 195 MRI compatibility mode 17 nri directive derer nomean based bee ne eee ets 52 MRI mode tempora
15. 120 IP2K Dependent Features sssssees esses 122 8 115 34 IP2K Options gee ete pede 122 M32R Dependent Features 000000 eee eens 123 8 116 353 M32R Options 0c eee ee eee 123 8 116 836 M32R Directives 0 000065 123 8 116 837 M32R Warnings esses eee 124 M680x0 Dependent Features ooooooooooooo 126 8 117 38 M680x0 Options sssssse esses 126 8S 117 39 IND 2 nd us etit tet RR RR da a 128 8 117 40 Motorola Syntax 0 ee eee eee 129 8 1741 Floating Poit edet 130 8 117 42 680x0 Machine Directives 131 SALT AS OpCOdes ace cem tee re ea dodo ap eto 131 8 117 43 1 Branch Improvement 131 vii viii 8 118 8 119 8 120 8 121 8 122 8 123 8 117 43 2 Special Characters 132 M68HC11 and M68HC12 Dependent Features 133 8 118 44 M68HC11 and M68HC12 Options 133 8 118 45 Syntax ebbe pe eb Rer d 134 8 118 46 Symbolic Operand Modifiers 135 8 118 47 Assembler DirectivesS 00oooo ooooooo o 136 8 118 48 Floating Point 005 136 8 118 49 Opcodes 0 eee eee eee 137 8 118 49 1 Branch Improvement 137 Motorola M88K Dependent Features 138 8 119 1 M88K Machine Directives 138 MIPS Dependent Features 0 0000 lessen 139 8 120 2 Assembler options
16. 191 ctraditional fOormat 3 4eLELIG Gs 19 underscore command line option CRIS 83 mui bs MR EE 20 ti option VAX VMS ssssseesseleeel 181 32addr command line option Alpha 70 a A dae 15 A Options 1900 2 2 oer RR ERIA I TS 118 OC codes Ma eee ET Ae Ra pu E EQUI wae earls 15 Sad sss aa ds a 15 A em 15 OD Q 15 O AER 15 nr 15 hsparclet a rugis 166 sAsparclite i2m a pev 166 cop T r rada 166 PAYOR LATO MM aces bon och Ur ua d e ME d 166 SAVO ua wes se eens d tete LN kant 166 PAV dH ETE 166 b option TIO cortada bere 118 Dl ii en E ee ee 160 Denia adas 15 D ignored on VAX 0 eee eee eee 180 lt d VAX Opticas RETE LES 180 SSP sive ek ada Re widths cH ERIT 160 EB command line option ARC T EB command line option ARM 80 EB option MIPS jes if rias sep eetOP PODER 139 EL command line option ARC 77 EL command line option ARM 80 EL option MIPS ssi nex rere ER TERES 139 S emus dia esa 16 F command line option Alpha 70 g command line option Alpha 70 G command line option Alpha 70 G option MIPS i esset ete sten ee tone 139 h option VAX VMS sssesseseessn 180 H option VAX VMS 000 eee 181 SI Pats write oes eons care ewe Tawa sore 16 J ignored on VAX ecciesie 180 c HM
17. extAuxRegister name address mode TODO extAuxRegister mulhi 0x12 w extCondCode suffix value TODO extCondCode is_busy 0x14 extCoreRegister name regnum mode shortcut TODO extCoreRegister mlo 57 r can_shortcut extInstruction name opcode subopcode suffixclass syntaxclass TODO extInstruction mul64 0x14 0x0 SUFFIX_COND SYNTAX_30P 0P1_MUST_BE_IMM half expressions TODO long expressions TODO option arc arc5 arc6 arc7 arc8 The option directive must be followed by the desired core version Again arc is an alias for arc CORE DEFAULT No value for ARC_CORE_DEFAULT Note the option directive overrides the command line option marc a warning is emitted when the version is not consistent between the two even for the implicit default core version arcCORE_DEFAULT NOo value for ARC CORE DEFAULT CORE DEFAULT Short expressions TODO word expressions TODO 8 103 16 Opcodes For information on the ARC instruction set see ARC Programmers Reference Manual ARC Cores Ltd Chapter 8 Machine Dependent Features 79 8 104 ARM Dependent Features 8 104 17 Options mcpu processor extension This option specifies the target processor The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor The following processor names are recognized armi arm2 arm250 arm3 arm6 arm60 arm600 arm6
18. hebx Aecx 4edx pedi hesi Zebp the frame pointer and hesp the stack pointer e the 8 16 bit low ends of these Zax bx Acx dx hdi Asi 4bp and hsp Chapter 8 Machine Dependent Features 109 e the 8 8 bit registers ah hal Abh b1 ch cl Adh and 41 These are the high bytes and low bytes of Zax bx cx and dx e the 6 section registers cs code section Ads data section Ass stack section hes hfs and Ags e the 3 processor control registers cr0 4cr2 and 4cr3 e the 6 debug registers 4db0 Adb1 db2 4db3 4db6 and db7 e the 2 test registers 4tr6 and tr7 e the 8 floating point register stack Ast or equivalently 4st 0 st 1 st 2 st 3 Ast 4 Ast b Ast 6 and 4st 7 These registers are overloaded by 8 MMX registers mm0 mm1 mm2 mm3 mm4 Amm5 mm6 and mm7 e the 8 SSE registers registers xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 and xmm7 The AMD x86 64 architecture extends the register set by e enhancing the 8 32 bit registers to 64 bit Arax the accumulator Arbx Arcx rdx Ardi Arsi 4rbp the frame point
19. 0 172 double directive VAX 0 181 double directive x86 6d o o oooooomm oooo 111 doublequote oooccccccccccccccccc o 24 drlist directive TIC54X 172 drnolist directive TIC54X 172 dual directive i860 o oo ooooooo o 116 E ECOFE sections ideo rain nets 142 ecr register V850 oooomoooooooo 187 eight byte integer eere cool ee a os 57 eipc register V850 22 22 ee eee 186 eipsw register V850 05 187 eject directive suicida o ia 45 ELF symbol type eee 64 else difeotlVe umi tr bn 45 elseif directive iced cgi ep ria a 45 empty expressions lees eene ot emsg directive TIC54X 00 eee 172 emulation atari aaa 10 end ditectiy amp s catas 45 enddual directive 1860 oooo oo oooo 116 endef directive cosa iei e pea Rr a 45 endfunc directve o eo rae REGE 45 endianness MIPS 2 cede dc Lowe cerns 8 endianness PJ esos cones ise eer ii e il endif directive ceesadio se Peu db re nds 46 endloop directive TIC54X 174 ndm directive cierro ERR P Tue 54 endm directive TIC5AX 005 174 endstruct directive TIC54X lusu 175 endunion directive TIC54X 175 219 ENTRY instructions alignment 193 environment settings TIC54X 168 EOF newline must precede 23 ep register V850
20. 83 CRIS underscore command line option 83 CRIS N command line option 83 CRIS assembler directive dword 85 CRIS assembler directive syntax 85 CRIS assembler directives 00ooo o oooo 85 CRIS instruction expansion 83 CRIS line comment characters 84 CRIS Options cs omiies ra 83 CRIS position independent code 83 CRIS pseudo op dword 0 000005 85 CRIS pseudo op syntax ee eee eee 85 CRIS pseudo ops 4 rt bene cae mee 85 CRIS register names 00000 85 CRIS SUDDOEU 2 incar ds EE To Rr e spares 83 Using as CRIS symbols in position independent code 84 ctbp register V8BH0D ooooooooomooooo 187 ctoff pseudo op V850 issssesssss 189 ctpc register V8BH0 ooooooooomooooo 187 ctpsw register V8DO oooomoooooooo oo 187 current address 2 sepak eee eee eee 35 current address advancing 54 D D10V Qword modifier oooooooccooooo 90 D10V addressing modes 89 D10V floating poimtb o oooooooooooo 90 D10V line comment character 88 D10V opcode summary eeeeeuusss 90 D10V optimization cuina men 5 DIOV Options cti adi arde 87 ID10V registers circa sense ta 89 D10V size modifie iere RD Re 87 D10V sub instruction ordering 88 D10V sub
21. endif is part of the as support for conditional assembly it marks the end of a block of code that is only assembled conditionally See Section 7 45 if page 48 7 31 equ symbol expression This directive sets the value of symbol to expression It is synonymous with set see Section 7 77 set page 59 The syntax for equ on the HPPA is symbol equ expression 7 32 equiv symbol expression The equiv directive is like equ and set except that the assembler will signal an error if symbol is already defined Note a symbol which has been referenced but not actually defined is considered to be undefined Except for the contents of the error message this is roughly equivalent to ifdef SYM err endif equ SYM VAL 7 33 err If as assembles a err directive it will print an error message and unless the Z option was used it will not generate an object file This can be used to signal error an conditionally compiled code 7 34 exitm Exit early from the current macro definition See Section 7 60 Macro page 53 7 35 extern extern is accepted in the source program for compatibility with other assemblers but it is ignored as treats all undefined symbols as external 7 36 fail expression Generates an error or a warning If the value of the expression is 500 or more as will print a warning message If the value is less than 500 as will print an error message The message will incl
22. oooooooocooooccoooo 29 numbers L6 bit 2 22 le iia ERR 48 numeric values 22e2eee eec eek mre 3T nword directive SPARC 167 O object ler 13 object file format oce eel ra 12 object file TAME o 19 object file after errors o oooooo o o o 20 obsolescent directives esses lesse 66 octa directive 2 0 0000 seed ee eee eng 54 octal character code ddd 0000005 24 Octal integers ile td ii 25 offset directive V850 00 00 ee 187 opcode mnemonics VAX ooo o 182 opcode names Xtenxa 0 eee eee 192 opcode summary D10V 005 90 opcode summary D380V 0 00008 94 opcode summary H8 300 00 0 00s 97 opcode summary H8 500 0005 99 opcode summary SH 0002000 161 opcode summary SH64 165 opcode summary Z8000 leues 180 opcodes for AMD 29K sssssluuu 69 opcodes for ARG isses cu she bte RETE 78 opcodes for ARM ussssseeeeellleeeh 82 Using as opcodes for MSP 430 ooocoooooccooooo 152 opcodes for V850 i c cab ii 188 opcodes Litio 116 opcodes 1960 oec pos 120 opcodes M680x0 eee eee eee eee 131 opcodes M68HC11 006 137 operand delimiters i386 0 107 operand delimiters x86 64 107 operand notation VAX 2
23. or e One or more decimal digits At least one of the integer part or the fractional part must be present The floating point number has the usual base 10 value as does all processing using integers Flonums are computed independently of any floating point hardware in the computer running as Chapter 4 Sections and Relocation 27 4 Sections and Relocation 4 1 Background Roughly a section is a range of addresses with no gaps all data in those addresses is treated the same for some particular purpose For example there may be a read only section The linker 1d reads many object files partial programs and combines their contents to form a runnable program When as emits an object file the partial program is assumed to start at address 0 1d assigns the final addresses for the partial program so that different partial programs do not overlap This is actually an oversimplification but it suffices to explain how as uses sections ld moves blocks of bytes of your program to their run time addresses These blocks slide to their run time addresses as rigid units their length does not change and neither does the order of bytes within them Such a rigid unit is called a section Assigning run time addresses to sections is called relocation It includes the task of adjusting mentions of object file addresses so they refer to the proper run time addresses For the H8 300 and H8 500 and for the Renesas SuperH SH a
24. size is only meaningful when generating COFF format output when as is generating b out it accepts this directive but ignores it ELF Version For ELF targets the size directive is used like this size name expression This directive sets the size associated with a symbol name The size in bytes is computed from expression which can make use of label arithmetic This directive is typically used to set the size of function symbols 7 81 sleb128 expressions sleb128 stands for signed little endian base 128 This is a compact variable length representation of numbers used by the DWARF symbolic debugging format See Section 7 93 Uleb128 page 64 7 82 skip size fill This directive emits size bytes each of value fill Both size and fill are absolute expres sions If the comma and fill are omitted fill is assumed to be zero This is the same as space 7 83 space size fill This directive emits size bytes each of value fill Both size and fill are absolute expres sions If the comma and fill are omitted fill is assumed to be zero This is the same as skip Warning space has a completely different meaning for HPPA targets use block as a substitute See HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 for the meaning of the space directive See Sec tion 8 110 5 HPPA Assembler Directives page 101 for a summary On the AMD 29K this directive is ignored it is accepted
25. 0x0000 so that the movea instruction stores OxXFFFFFFFF into r6 the right value Computes the 32 bit value of the given expression and stores it into the imme diate operand field of the given instruction which must be a mov instruction For example mov hilo here r6 computes the absolute address of label here and puts the result into register 6 Chapter 8 sdaof tdaoff zdaoff ctoff Machine Dependent Features 189 Computes the offset of the named variable from the start of the Small Data Area whoes address is held in register 4 the GP register and stores the result as a 16 bit signed value in the immediate operand field of the given instruction For example 1d w sdaoff a variable gp r6 loads the contents of the location pointed to by the label _a_variable into register 6 provided that the label is located somewhere within 32K of the address held in the GP register Note the linker assumes that the GP register contains a fixed address set to the address of the label called __gp This can either be set up automatically by the linker or specifically set by using the defsym __gp lt value gt command line option Computes the offset of the named variable from the start of the Tiny Data Area whoes address is held in register 30 the EP register and stores the result as a 4 5 7 or 8 bit unsigned value in the immediate operand field of the given instruction For e
26. 81 immediate character M680x0 132 immediate character VAX 0 183 immediate fields relaxati0N 195 immediate operands 1386 107 immediate operands x86 64 107 imul instruction 1386 esses ee snnm 114 imul instruction x86 64d 0 o ooooo oooooo 114 incbin directive ooelssu leere nes 49 include Cirective scssi hee bed ee meer 50 include directive search path 16 indirect character VAX 22 0 5 183 infi OperaborSus cie iod eso PURI Sr iaa 38 inhibiting interrupts 1386 110 TP UC oce in i 13 input file linenumbers o ooooo 13 instruction expansion CRIS 83 instruction expansion MMIX 145 instruction naming 1386 ooo ooooo 108 instruction naming x86 64 108 instruction prefixes 1386 o o o o oooo 109 221 instruction set M680x0 005 131 instruction set M68HC11 137 instruction summary DI0OV 90 instruction summary DIO V occ 94 instruction summary H8 300 97 instruction summary H8 500 99 instruction summary SH 161 instruction summary SH64 165 instruction summary Z8000 180 instructions and directives 23 int directive ce valer
27. The h n option determines how we map names This takes several values No h switch at all allows case hacking as described above A value of zero hO implies names should be upper case and inhibits the case hack A value of 2 h2 implies names should be all lower case with no case hack A value of 3 h3 implies that case should be preserved The value 1 is unused The H option directs as to display every mapped symbol during assembly Symbols whose names include a dollar sign are exceptions to the general name mapping These symbols are normally only used to reference VMS library names Such symbols are always mapped to upper case d The option causes as to truncate any symbol name larger than 31 char acters The option also prevents some code following the _main symbol normally added to make the object file compatible with Vax 11 C i This option is ignored for backward compatibility with as version 1 x H The H option causes as to print every symbol which was changed by case mapping 8 131 25 VAX Floating Point Conversion of flonums to floating point is correct and compatible with previous as semblers Rounding is towards zero if the remainder is exactly half the least significant bit D F G and H floating point formats are understood Immediate floating literals e g S 6 9 are rendered correctly Again rounding is towards zero in
28. When assembling for ECOFF the assembler uses the gp 28 register to form the address of a small object Any object in the sdata or sbss sections is considered small in this sense For external objects or for objects in the bss section you can use the gcc G option to control the size of objects addressed via gp the default value is 8 meaning that a reference to any object eight bytes or smaller uses gp Passing G 0 to as prevents it from using the gp register on the basis of object size but the assembler uses gp for objects in sdata or sbss in any case The size of an object in the bss section is set by the comm or 1comm directive that defines it The size of an external object may be set with the extern directive For example extern sym 4 declares that the object at sym is 4 bytes in length whie leaving sym otherwise undefined Using small ECOFF objects requires linker support and assumes that the gp register is correctly initialized normally done automatically by the startup code MIPS ECOFF assembly code must not modify the gp register 8 120 4 Directives for debugging information MIPS ECOFF as supports several directives used for generating debugging information which are not support by traditional MIPS assemblers These are def endef dim file Scl size tag type val stabd stabn and stabs The debugging information generated by the three stab directives can only b
29. change 32 bit operands addresses into 16 bit operands addresses while data32 and addr32 change 16 bit ones in a code16 section into 32 bit operands addresses These prefixes must appear on the same line of code as the instruction they modify For example in a 16 bit code16 section you might write 110 Using as addr32 jmpl ebx e The bus lock prefix lock inhibits interrupts during execution of the instruction it precedes This is only valid with certain instructions see a 80386 manual for details e The wait for coprocessor prefix wait waits for the coprocessor to complete the current instruction This should never be needed for the 80386 80387 combination e The rep repe and repne prefixes are added to string instructions to make them repeat Zecx times cx times if the current address size is 16 bits e The rex family of prefixes is used by x86 64 to encode extensions to 1386 instruction set The rex prefix has four bits an operand size overwrite 64 used to change operand size from 32 bit to 64 bit and X Y and Z extensions bits used to extend the register set You may write the rex prefixes directly The rex64xyz instruction emits rex prefix with all the bits set By omitting the 64 x y or z you may write other prefixes as well Normally there is no need to write the prefixes explicitly since gas will automatically generate them b
30. m32r This option can be used to restore the assembler s default behaviour of assem bling for the M32R microprocessor This can be useful if the default has been changed by a previous command line option warn explicit parallel conflicts Instructs as to produce warning messages when questionable parallel instruc tions are encountered This option is enabled by default but gcc disables it when it invokes as directly Questionable instructions are those whoes be haviour would be different if they were executed sequentially For example the code fragment mv ri r2 mv r3 r1 produces a different result from mv ri r2 n mv r3 r1 since the former moves rl into r3 and then r2 into rl whereas the later moves r2 into r1 and r3 Wp This is a shorter synonym for the warn ezplicit parallel conflicts option no warn explicit parallel conflicts Instructs as not to produce warning messages when questionable parallel in structions are encountered Wnp This is a shorter synonym for the no warn ezplicit parallel conflicts option 8 116 36 M32R Directives The Renease M32R version of as has a few architecture specific directives low expression The low directive computes the value of its expression and places the lower 16 bits of the result into the immediate field of the instruction For example or3 r0 rO ttlow 0x12345678 compute r0 rO 0x5678 add3 rO rO low fred compute rO r0 low 16 bits of address of
31. 8 and it may always be omitted along with the leading asterisk The following additional addressing modes are understood Address Register Indirect a0 through a7 hal is also known as Asp i e the Stack Pointer a6 is also known as fp the Frame Pointer Address Register Postincrement Za0 through a7 Address Register Predecrement a0 through a7 Indirect Plus Offset number 4a0 through number a7 or number pc The number may also appear within the parentheses as in number a0 When used with the pc the number may be omitted with an address register omitting the number produces Address Register Indirect mode Index number apc register size scale The number may be omitted or it may appear within the parentheses The apc may be omitted The register and the apc may appear in either order If both apc and register are address registers and the size and scale are omitted then the first register is taken as the base register and the second as the index register Postindex number apc register size scale onumber The onumber or the register or both may be omitted Either the number or the apc may be omitted but not both Preindex number apc register size scale onumber The number or the apc or the register or any two of them may be omitted The onumber may be omitted The register and the apc may app
32. 8 101 4 AMD 29K Machine Directives block size fill This directive emits size bytes each of value fill Both size and fill are absolute expressions If the comma and fill are omitted fill is assumed to be zero In other versions of the GNU assembler this directive is called space cputype This directive is ignored it is accepted for compatibility with other AMD 29K assemblers file This directive is ignored it is accepted for compatibility with other AMD 29K assemblers Warning in other versions of the GNU assembler file is used for the directive called app file in the AMD 29K support line This directive is ignored it is accepted for compatibility with other AMD 29K assemblers sect This directive is ignored it is accepted for compatibility with other AMD 29K assemblers Use section name Establishes the section and subsection for the following code section name may be one of text data datal or 1it With one of the first three section name options use is equivalent to the machine directive section name the remaining case use lit is the same as data 200 8 101 5 Opcodes as implements all the standard AMD 29K opcodes No additional pseudo instructions are needed on this family For information on the 29K machine instruction set see Am29000 User s Manual Ad vanced Micro Devices Inc 70 Using as 8 102 Alpha Dependent Features 8 102 6 Notes The documentati
33. 8 Using as print opcodes print the list of instructions with syntax and then exit generate example print an example of instruction for each possible instruction and then exit This option is only useful for testing as The following options are available when as is configured for the SPARC architecture Av6 Av7 Av8 Asparclet Asparclite Av8plus Av8plusa Av9 Av9a Explicitly select a variant of the SPARC architecture Av8plus and Av8plusa select a 32 bit environment Av9 and Av9a select a 64 bit environment Av8plusa and Av9a enable the SPARC V9 instruction set with Ultra SPARC extensions xarch v8plus xarch v8plusa For compatibility with the Solaris v9 assembler These options are equivalent to Av8plus and Av8plusa respectively bump Warn when the assembler switches to another architecture The following options are available when as is configured for the c54x architecture mfar mode Enable extended addressing mode All addresses and relocations will assume extended addressing usually 23 bits mcpu CPU VERSION Sets the CPU version being compiled for merrors to file FILENAME Redirect error output to a file for broken systems which don t support such behaviour in the shell The following options are available when as is configured for a MIPS processor G num This option sets the largest size of an object that can be referenced imp
34. ADRL nop This pseudo op will always evaluate to a legal ARM instruction that does noth ing Currently it will evaluate to MOV r0 r0 ldr register expression If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction if the constant can be generated by either of these instructions Otherwise the constant will be placed into the nearest literal pool if it not already there and a PC relative LDR instruction will be generated adr register label This instruction will load the address of label into the indicated register The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located If the label is out of range or if it is not defined in the same file and section as the ADR instruction then an error will be generated This instruction will not make use of the literal pool adrl register label This instruction will load the address of label into the indicated register The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located If a second instruction is not needed a NOP instruction will be generated in its place so that this instruction is always 8 bytes long If the label is out of range or if it is not defined in the same file and section as the ADRL instruction then an error will be generated This instruction will not mak
35. addr Direct the 16 bit or 24 bit address depending on whether the assembler is in segmented or unsegmented mode of the operand is in the instruction address rn Indexed the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand rn timm Base Address the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand rn rm Base Index the 16 or 24 bit register rn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand Hxx Immediate data xx 8 130 22 Assembler Directives for the Z8000 The Z8000 port of as includes these additional assembler directives for compatibility with other 28000 assemblers As shown these do not begin with unlike the ordinary as directives segm Generates code for the segmented Z8001 unsegm Generates code for the unsegmented Z8002 name Synonym for file global Synonym for global wval Synonym for word lval Synonym for long bval Synonym for byte sval Assemble a string sval expects one string literal delimited by single quotes It assembles each byte of the string into consecutive addresses You can use the escape sequence 4xx where xx represents a two digit hexadecimal number to represent the character whose ASCII value is xx Use this feature to describe single quote and other characters that
36. call jmp far section offset Also the far return in 108 Using as struction is lret stack adjust in AT amp T syntax Intel syntax is ret far stack adjust e The AT amp T assembler does not provide support for multiple section programs Unix style systems expect all programs to be single sections 8 112 15 Instruction Naming Instruction mnemonics are suffixed with one character modifiers which specify the size of operands The letters b w 1 and q specify byte word long and quadruple word operands If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand the last one by convention Thus mov hax Abx is equivalent to movw Zax bx also mov 1 bx is equivalent to movw 1 bx Note that this is incompatible with the AT amp T Unix assembler which assumes that a missing mnemonic suffix implies long operand size This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix Almost all instructions have the same names in AT amp T and Intel format There are a few exceptions The sign extend and zero extend instructions need two sizes to specify them They need a size to sign zero extend from and a size to zero extend to This is accomplished by using two instruction mnemonic suffixes in AT amp T syntax Base names for sign extend and zero extend are
37. global symbol symbol n def symbol symbol n ref symbol symbol n def nominally identifies a symbol defined in the current file and availalbe to other files ref identifies a symbol used in the current file but defined elsewhere Both map to the standard global directive half value value n uhalf value value n short value value n ushort value value n int value value n uint value value n word value value n uword value value n Place one or more values into consecutive words of the current section If a label is used it points to the word allocated for the first value encountered label symbol Define a special symbol to refer to the load time address of the current section program counter length width Set the page length and width of the output listing file Ignored list nolist Control whether the source listing is printed Ignored 174 Using as long value value_n ulong value value_n xlong value value_n Place one or more 32 bit values into consecutive words in the current section The most significant word is stored first long and ulong align the result on a longword boundary xlong does not loop count break condition endloop Repeatedly assemble a block of code loop begins the block and endloop marks its termination count defaults to 1024 and indicates the number of times the block shoul
38. movs and movz in AT amp T syntax movsx and movzx in Intel syntax The instruction mnemonic suffixes are tacked on to this base name the from suffix before the o suffix Thus movsbl al Zedx is AT amp T syntax for move sign extend from al to edx Possible suffixes thus are bI from byte to long bw from byte to word wl from word to long bq from byte to quadruple word wq from word to quadruple word and 1q from long to quadruple word The Intel syntax conversion instructions e cbw sign extend byte in al to word in Zax e cwde sign extend word in ax to long in Zeax e cwd sign extend word in Zax to long in 4dx ax e cdq sign extend dword in Zeax to quad in edx eax e cdqe sign extend dword in 4eax to quad in 4rax x86 64 only e cdo sign extend quad in 4rax to octuple in rdx rax x86 64 only are called cbtw cwtl cwtd cltd cltq and cqto in AT amp T naming as accepts either naming for these instructions Far call jump instructions are 1call and 1jmp in AT amp T syntax but are call far and jump far in Intel convention 8 112 16 Register Naming Register operands are always prefixed with The 80386 registers consist of e the 8 32 bit registers 4eax the accumulator
39. 112 Using as 6 e Floating point constructors are float or single double and tfloat for 32 64 and 80 bit formats These correspond to instruction mnemonic suffixes s T and t t stands for 80 bit ten byte real The 80387 only supports this format via the fldt load 80 bit real to stack top and fstpt store 80 bit real and pop stack instructions e Integer constructors are word long or int and quad for the 16 32 and 64 bit integer formats The corresponding instruction mnemonic suffixes are s single T long and q quad As with the 80 bit real format the 64 bit q format is only present in the fildq load quad integer to stack top and fistpq store quad integer and pop stack instructions Register to register operations should not use instruction mnemonic suffixes fstl Ast st 1 will give a warning and be assembled as if you wrote fst Ast st 1 since all register to register operations use 80 bit floating point operands Contrast this with fst1 4st mem which converts Ast from 80 bit to 64 bit floating point format then stores the result in the 4 byte location mem 8 112 21 Intel s MM X and AMD s 3DNow SIMD Operations as supports Intel s MMX instruction set SIMD instructions for integer data avail able on Intel s Pentium MMX processors and Pentium II proce
40. Address Register number X number Y The number may be omitted in which case 0 is assumed Direct Addressing mode xsymbol or digits Absolute symbol or digits The M68HC12 has other more complex addressing modes All of them are supported and they are represented below Constant Offset Indexed Addressing Mode number reg Chapter 8 Machine Dependent Features 135 The number may be omitted in which case 0 is assumed The register can be either X Y SP or PC The assembler will use the smaller post byte definition according to the constant value 5 bit constant offset 9 bit constant offset or 16 bit constant offset If the constant is not known by the assembler it will use the 16 bit constant offset post byte and the value will be resolved at link time Offset Indexed Indirect number reg The register can be either X Y SP or PC Auto Pre Increment Pre Decrement Post Increment Post Decrement number reg number reg number reg number reg The number must be in the range 8 8 and must not be 0 The register can be either X Y SP or PC Accumulator Offset acc reg The accumulator register can be either A B or D The register can be either Y Y SP or PC Accumulator D offset indexed indirect D reg The register can be either X Y SP
41. Its default name is a out or b out when as is configured for the Intel 80960 You can give it another name by using the o option Conventionally object file names end with o The default name is used for historical reasons older assemblers were capable of assembling self contained programs directly into a runnable program For some formats this isn t currently possible but it can be done for the a out format The object file is meant for input to the linker 1d It contains assembled program code information to help 1d integrate the assembled program into a runnable file and optionally symbolic information for the debugger 14 Using as 1 7 Error and Warning Messages as may write warnings and error messages to the standard error file usually your ter minal This should not happen when a compiler runs as automatically Warnings report an assumption made so that as could keep assembling a flawed program errors report a grave problem that stops the assembly Warning messages have the format file_name NNN Warning Message Text where NNN is a line number If a logical file name has been given see Section 7 37 file page 47 it is used for the filename otherwise the name of the current input file is used If a logical line number was given see Section 7 54 line page 51 then it is used to calculate the number printed otherwise the actual line in the current source file is printed The message text is inten
42. MMIX 147 assembler directive LOCAL MMIX 147 assembler directive OCTA MMIX 148 assembler directive PREFIX MMIX 149 assembler directive TETRA MMIX 148 assembler directive WYDE MMIX 148 assembler directives CRIS 0 85 assembler directives M68HC11 136 assembler directives M68HC12 136 assembler directives MMIX 147 assembler internal logic error 29 assembler version oooooooccoooooomoooo 20 assembler and linker o ooooooooooo 27 assembly listings enabling 15 assigning values to symbols 33 46 atmp directive 1860 116 att syntax pseudo op i386 107 att syntax pseudo op x86 64 107 attributes symbol oo ooooooooooo omo 35 auxiliary attributes COFF symbols 36 auxiliary symbol information COFF 45 B3 ntu suut naque EE ent Bena Bah stark EE 166 backslash NX icons Diabetes sets 24 backspace Nb seis assis ob rr Par gw oreas 24 balign directive cse pa pee ek bee 42 balignl directive 2 perl 42 balignw directive nr reb aida 42 bes directive TICBAX 174 big endian output MIPS 8 217 big endian output PU 2 ee eee 7 big endian output MIPS 139 DIEDUMS conocer p
43. W and no warn options no warnings are issued This only affects the warning messages it does not change any particular of how as assembles your file Errors which stop the assembly are still reported If you use the fatal warnings option as considers files that generate warnings to be in error You can switch these options off again by specifying warn which causes warnings to be output as usual 2 16 Generate Object File in Spite of Errors Z After an error message as normally produces no output If for some reason you are interested in object file output even after as gives an error message on your program use the Z option If there are any errors as continues anyways and writes an object file after a final warning message of the form n errors m warnings generating bad object file Chapter 3 Syntax 21 3 Syntax This chapter describes the machine independent syntax allowed in a source file as syntax is similar to what many other assemblers use it is inspired by the BSD 4 2 assembler except that as does not assemble Vax bit fields 3 1 Preprocessing The as internal preprocessor e adjusts and removes extra whitespace It leaves one space or tab before the keywords on a line and turns any other whitespace on the line into a single space e removes all comments replacing them with a single space or an appropriate number of newlines e converts character constants int
44. Width of continuation lines of disassembly output RARA dis 17 Width of first line disassembly output IT Width of source line output iy wmsg directive TIC54X oooommommmm o o 172 Word AMECA O cr ei 65 Using as word directive ARC 0coooccccccccccccoo 78 word directive H8 300 0 000 97 word directive H8 500 000 99 word directive 1386 oooooooooomoo 112 word directive M88K o ooo o ooooo o oo 138 word directive SPARC 0005 167 word directive TIC54X o o ooooooo ooooo 173 word directive x86 64 oooooooooo oo 112 writing patterns in Memory ooo ooooo oo o 47 Walt a li a 179 x86 64 arch directive ooooooooooooo oo o 113 x86 64 att syntax pseudo op 107 x86 64 conversion instructions 108 x86 64 floating point 000 111 x86 64 immediate operands 107 x86 64 instruction naming s 108 x86 64 intel syntax pseudo op 107 x86 64 jump optimization lesse 111 x86 64 jump call return lusus 107 x86 64 jump call operands sssse 107 x86 64 memory references ooooooooooooo 110 x86 064 OPTIONS coin RE PE ati 107 x86 64 register operands 107 x86 04 registers i e bes rere rere es 108 x86 04 SECLIONS nca hm deen adds et bale eR 108 x86 64 size suffi
45. a side effect of this is the normal as NARG dereferencing syntax is unnecessary Subsyms defined within a macro will have global scope unless the var directive is used to identify the subsym as a local macro variable see Section 8 129 17 var page 171 Substitution may be forced in situations where replacement might be ambiguous by placing colons on either side of the subsym The following code eval 10 x LAB X add 4x a When assembled becomes LAB10 add 10 a Smaller parts of the string assigned to a subsym may be accessed with the following syntax symbol char index Evaluates to a single character string the character at char index symbol start length Evaluates to a substring of symbol beginning at start with length length 8 129 14 Local Labels Local labels may be defined in two ways e N where N is a decimal number between 0 and 9 e LABEL where LABEL is any legal symbol name Local labels thus defined may be redefined or automatically generated The scope of a local label is based on when it may be undefined or reset This happens when one of the following situations is encountered e newblock directive see Section 8 129 17 newblock page 171 e The current section is changed sect text or data e Entering or leaving an included file e The macro scope where the label was defined is exited 170 Using as 8 129 15 Math Builtins The following built in functions may be used to generate a f
46. abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the alignment request in bytes For example balign 8 advances the location counter until it is a multiple of 8 If the location counter is already a multiple of 8 no change is needed The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on some systems if the section is marked as containing code and the fill value is omitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignment to be filled with no op instructions when appropriate The balignw and balignl directives are variants of the balign directive The balignw directive treats the fill pattern as a two byte word value The balignl directives treats the fill pattern as a four byte longword value For example balignw 4 0x368d will align to a multiple of 4 If it ski
47. def endef pairs Tags are used to link structure definitions in the symbol table with instances of those structures tag is only used when generating COFF format output when as is generating b out it accepts this directive but ignores it 7 90 text subsection Tells as to assemble the following statements onto the end of the text subsection num bered subsection which is an absolute expression If subsection is omitted subsection number zero is used 7 91 title heading Use heading as the title second line immediately after the source file name and pa genumber when generating assembly listings This directive affects subsequent pages as well as the current page if it appears within ten lines of the top of a page 7 92 type This directive is used to set the type of a symbol COFF Version For COFF targets this directive is permitted only within def endef pairs It is used like this 64 Using as type int This records the integer int as the type attribute of a symbol table entry type is associated only with COFF format output when as is configured for b out output it accepts this directive but ignores it ELF Version For ELF targets the type directive is used like this type name type description This sets the type of symbol name to be either a function symbol or an object symbol There are five different syntaxes supported for the type description field in order to provide c
48. is two bytes hence quad word for 8 bytes Chapter 7 Assembler Directives 57 7 73 rept count Repeat the sequence of lines between the rept directive and the next endr directive count times For example assembling rept 3 long 0 endr is equivalent to assembling long 0 long 0 long 0 7 74 sbttl subheading Use subheading as the title third line immediately after the title line when generating assembly listings This directive affects subsequent pages as well as the current page if it appears within ten lines of the top of a page 7 10 SEL class Set the storage class value for a symbol This directive may only be used inside a def endef pair Storage class may flag whether a symbol is static or external or it may record further symbolic debugging information The scl directive is primarily associated with COFF output when configured to generate b out output format as accepts this directive but ignores it 7 76 section name Use the section directive to assemble the following code into a section named name This directive is only supported for targets that actually support arbitrarily named sections on a out targets for example it is not accepted even with a standard a out section name COFF Version For COFF targets the section directive is used in one of the following ways section name flags section name subsegment If the optional argument is quoted it i
49. mbooke mbooke32 Generate code for 32 bit BookE maltivec Generate code for processors with AltiVec instructions mpower4 Generate code for Power4 architecture mcom Generate code Power PowerPC common instructions many Generate code for any architecture PWR PWRX PPC mregnames Allow symbolic names for registers mno regnames Do not allow symbolic names for registers Chapter 8 Machine Dependent Features 159 mrelocatable Support for GCC s mrelocatble option mrelocatable lib Support for GCC s mrelocatble lib option memb Set PPC EMB bit in ELF flags mlittle mlittle endian Generate code for a little endian machine mbig mbig endian Generate code for a big endian machine msolaris Generate code for Solaris mno solaris Do not generate code for Solaris 160 Using as 8 126 Renesas SuperH SH Dependent Features 8 126 1 Options as has following command line options for the Renesas formerly Hitachi SuperH SH family little Generate little endian code big Generate big endian code relax Alter jump instructions for long displacements small Align sections to 4 byte boundaries not 16 dsp Enable sh dsp insns and disable sh3e sh4 insns 8 126 2 Syntax 8 126 2 1 Special Characters 1 is the line comment character You can use instead of a newline to separate statements Since has no special meaning you may use it in symbol names 8 126 2 2 Reg
50. registers DIOV jasc ees esser i 89 registers D30V co scans LET Ov a e s 93 registers H8 500 ego catedra ered 98 registers 1986 coca give awa crac ia 108 Pegisters SM pra 160 r gisters SH64 sio ii CRY eue 163 registers TIC54X memory mapped i77 registers x86 64 0c cscs cee ee ae eee ies 108 registers Z 8000 exse e riada 178 relax directives 2c ccc 5 d eee rk ia 197 ESO 2 Revera e aream sere 194 relaxation of ADDI instructions 195 relaxation of branch instructions 194 relaxation of call instructions 194 relaxation of immediate fields 195 relaxation of L16SI instructions 195 relaxation of L16UI instructions 195 relaxation of L321 instructions 195 relaxation of L8UI instructions 195 relaxation of MOVI instructions 195 relocatlOBu 1 beo NIRE oxen secs 27 relocation example oooooooomocoomom 29 relocations Alpha ecsrsccriiesrnnspninre amis ail 226 repeat prefixes 1386 ooooooooooo o 110 reporting bugs in assembler 201 rept CireChive ve 222 espe as eru x RR 57 req directive ARM sees eee 81 reserve directive SPARC 167 return instructions i3886 004 107 return instructions x86 64 107 REX prefixes 1386 oooooocooooommoo 110 TO iran as wage aed 179 sblo
51. tag number where tag is the name of the relocation In some cases number is used to relate specific instructions The relocation is placed at the end of the instruction like so ldah 0 a 29 gprelhigh lda 0 a 0 gprellow ldq 1 b 29 literal 100 1d1l 2 0 1 lituse base 100 literal literal N Used with an 1dq instruction to load the address of a symbol from the GOT A sequence number N is optional and if present is used to pair lituse relo cations with this literal relocation The lituse relocations are used by the linker to optimize the code based on the final location of the symbol Note that these optimizations are dependent on the data flow of the program Therefore if any lituse is paired with a literal relocation then all uses of the register set by the literal instruction must also be marked with lituse relocations This is because the original literal instruction may be deleted or transformed into another instruction Also note that there may be a one to many relationship between literal and lituse but not a many to one That is if there are two code paths that load up the same address and feed the value to a single use then the use may not use a lituse relocation lituse_base N Used with any memory format instruction e g 1d1 to indicate that the literal is used for an address load The offset field of the instruction must be zero During relaxation the code may be altered to use a gp relat
52. where both components attempt to modify the same register For example these code fragments will produce this message mv r1 r2 neg r1 r3 jl r0 mv r14 ri st r2 r1 mv ri r3 mv r1 r2 ld rO Gri cmp ri r2 addx r3 r4 Both write to the condition bit 126 Using as 8 117 M680x0 Dependent Features 8 117 38 M680x0 Options The Motorola 680x0 version of as has a few machine dependent options 7 You can use the 1 option to shorten the size of references to undefined sym bols If you do not use the 1 option references to undefined symbols are wide enough for a full long 32 bits Since as cannot know where these symbols end up as can only allocate space for the linker to fill in later Since as does not know how far away these symbols are it allocates as much space as it can If you use this option the references are only one word wide 16 bits This may be useful if you want the object file to be as small as possible and you know that the relevant symbols are always less than 17 bits away register prefix optional For some configurations especially those where the compiler normally does not prepend an underscore to the names of user variables the assembler requires a W before any use of a register name This is intended to let the assembler distinguish between C variables and functions named a0 through a7 and so on The is always accepted but
53. 131 skip directive SPARC o oooooommo 167 Sleb128 directive 2 ies oe ede ee ne ee ees 60 small objects MIPS ECOFF 142 SOM symbol attributes oooooooooo oo 36 SOULCE program essensen 4 p RR LEER 13 source destination operands i386 107 source destination operands x86 64 107 SD PeEISUGE on chi Peden ee 193 sp register V850 cic eo eret EPIS 185 Space directive sioe pub erm rd 61 space directive TIC54X uuuuuuu 174 space used maximum for assembly 19 SPARC architectures 0oooooooccccoc o 166 SPARC data alignment 166 SPARC floating point IEEE 167 SPARC machine directives 167 SPARC options eeeees en nnn 166 SPARG SUPPORT larisa tati 166 special characters ARC 004 Fifi special characters M680x0 132 special purpose registers AMD 29K 68 special purpose registers MSP 430 151 specific opcodes 0 cece ee eee eens 192 sslist directive TIC54X 175 ssnolist directive TIC54X 175 Stabd directive colore ied eee ae os 61 stabri directive s t cutie eere hed ee dae 61 stabs directive ieellase tee bende oe 62 stabx directives oooooooooomommomooo 61 standard assembler secti0NS o o o 27 standard input as input file 12 statement separa
54. 255 The recognized special register names are rJ rA rB rC rD rE rF rO rH rI rk rL rM rN ro rP Chapter 8 Machine Dependent Features 147 TQ rR rS rT rU rV rW rX rY rZ rBB rTT rWW rXX rYY and rZZ A leading is optional for special register names Local and global symbols can be equated to register names and used in place of ordinary registers Similarly for special registers local and global symbols can be used Also symbols equated from numbers and constant expressions are allowed in place of a special reg ister except when either of the options no predefined syms and fixed special register names are specified Then only the special register names above are allowed for the instructions having a special register operand GET and PUT 8 121 12 4 Assembler Directives LOC The LOC directive sets the current location to the value of the operand field which may include changing sections If the operand is a constant the section is set to either data if the value is 0x2000000000000000 or larger else it is set to text Within a section the current location may only be changed to monotonically higher addresses A LOC expression must be a previously defined symbol or a pure constant An example which sets the l
55. 30 3 Special Characters 3 and are the line comment characters Sub instructions may be executed in order in reverse order or in parallel Instructions listed in the standard one per line format will be executed sequentially unless you use the 0 option To specify the executing order use the following symbols gt Sequential with instruction on the left first lt Sequential with instruction on the right first p Parallel The D30V syntax allows either one instruction per line one instruction per line with the execution symbol or two instructions per line For example abs r2 r3 gt abs r4 r5 Execute these sequentially The instruction on the right is in the right container and is executed second abs r2 r3 lt abs r4 r5 Execute these reverse sequentially The instruction on the right is in the right container and is executed first abs r2 r3 abs r4 r5 Execute these in parallel ldw r2 r3 r4 mulx r6 r8 r9 Two line format Execute these in parallel mulx a0 r8 r9 stw r2 0 r3 r4 Two line format Execute these sequentially unless 0 option is used If the Q option is used the assembler will determine if the instructions could be done in parallel the above two instructions can be done in parallel and if so emit them as parallel instructions The assembler will put them in the proper containers In the above example the assembler will put the stw instruction in left containe
56. 32 bits wide at all times mgp32 controls the size of general purpose registers and mfp32 controls the size of floating point registers mipsi6 no mipsi6 Generate code for the MIPS 16 processor This is equivalent to putting set mips16 at the start of the assembly file no mips16 turns off this option mips3d no mips3d Generate code for the MIPS 3D Application Specific Extension This tells the assembler to accept MIPS 3D instructions no mips3d turns off this option 10 Using as mdmx no mdmx Generate code for the MDMX Application Specific Extension This tells the assembler to accept MDMX instructions no mdmx turns off this option construct floats no construct floats The no construct floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register By default construct floats is selected allowing construction of these floating point constants emulation name This option causes as to emulate as configured for some other target in all respects including output format choosing between ELF and ECOFF only handling of pseudo opcodes which may generate debugging information or store symbol table information and default endianness T he available configuration names are mipsecoff mipself mipslecoff mipsbeco
57. 38 arguments in expressions o o o ooooccoooo 3T arithmetic functions seis es Re na S arithmetic OPerandS o oooooccoooccccono co 37 arm directive ARM occooccccccccccccccc 81 ARM floating point IEEE 0 81 Index ARM identifiers 0 00000 eee 81 ARM immediate character 81 ARM line comment character 80 ARM line separator 0000 ee eeeee 80 ARM machine directives 04 81 ARM opcodes 1m rte ce dada 82 ARM options none 0 000000 79 ARM register names oo ooooooooommmmccs 81 ARM SUpport uvas a dis 79 ascii directive c ssc eee eed ro 42 sciz directive ocio 42 asg directive TICS54X iscecs niece sani 171 assembler bugs reporting 201 assembler crash 0 see eee eee eeee 201 assembler directive dword CRIS 85 assembler directive far M68HC11 136 assembler directive interrupt M68HC11 136 assembler directive mode M68HC11 136 assembler directive relax M68HC11 136 assembler directive syntax CRIS 85 assembler directive xrefb M68HC11 136 assembler directive BSPEC MMIX 149 assembler directive BYTE MMIX 148 assembler directive ESPEC MMIX 149 assembler directive GREG MMIX 148 assembler directive IS MMIX 147 assembler directive LOC
58. All of the Intel i860XR and i860XP machine instructions are supported Please see either 1860 Microprocessor Programmer s Reference Manual or 1860 Microprocessor Architecture for more information 8 113 29 1 Other instruction support pseudo instructions For compatibility with some other i860 assemblers a number of pseudo instructions are supported While these are supported they are a very undesirable feature that should be avoided in particular when they result in an expansion to multiple actual i860 instructions Below are the pseudo instructions that result in expansions e Load large immediate into general register The pseudo instruction mov imm rn where the immediate does not fit within a signed 16 bit field will be expanded into orh large_immCh r0 rn or large_immCl rn rn e Load store with relocatable address expression For example the pseudo instruction 1d b addr_exp 4rx Arn will be expanded into orh addr_exp ha rx 7 r31 1d 1 addr_exp 1 r31 rn The analogous expansions apply to 1d x st x fld x pfld x fst x and pst x as well e Signed large immediate with add subtract If any of the arithmetic operations adds addu subs subu are used with an im mediate larger than 16 bits signed then they will be expanded For instance the pseudo instruction adds large_imm rx rn expands to Chapter 8 Machine Dependent Features 117 orh large_imm h r0 r31 or large_imm 1 r31 r31 adds r31 rx rn e
59. Displacement T 68020 68000 10 not PC relative OK Pseudo Op BYTE WORD LONG ABSOLUTE LONG JUMP kk n jbsr bsrs bsrw bsrl jsr jra bras braw bral jmp jXX bXXs bXXw bXX1 bNXs jmp dbXX N A dbXXw dbXX bras bral dbXX bras jmp fjXX N A fbXXw fbxXX1 N A XX condition NX negative of condition XX jbsr jra see full description below this expansion mode is disallowed by pcrel These are the simplest jump pseudo operations they always map to one partic ular machine instruction depending on the displacement to the branch target This instruction will be a byte or word branch is that is sufficient Otherwise a long branch will be emitted if available If no long branches are available and the pcrel option is not given an absolute long jump will be emitted instead If no long branches are available the pcrel option is given and a word branch cannot reach the target an error message is generated 132 jXX dbXX fjXX Using as In addition to standard branch operands as allows these pseudo operations to have all operands that are allowed for jsr and jmp substituting these instruc tions if the operand given is not valid for a branch instruction Here jXX stands for an entire family of pseudo operations where XX is a conditional branch or condition code test The full list of pseudo ops in this family is jhi jls jcc jes jne jeq jvc jvs jpl jmi jge jlt jgt jle Usually eac
60. F fail ditecllves o sisas ia 46 far mode directive TIC54X 172 faster processing f o oooooococccocccoc 16 fatal Signal ariRepeeni REO T pP EE 201 fclist directive TIC5AX 173 fcnolist directive TIC54X 173 fepc register V850 ooooooooomoo omo 187 fepsw register V8B50 ooooooooooooooo 187 ffloat directive M88K 138 ffloat directive VAX ooooooocccccccco co 181 field directive TICBAX 173 file direclive 2 oialeca ai cia AT file directive AMD 29K 69 file directive MSP 430 152 file name logical 2 err rh AT files icluding us reet epi 50 fil s input Su ideo ERE RR RR aie 13 fill directive oia od ERI Eroni AT filling Memory eset Rr tages ed gees 60 61 220 float directlve eode ERE IHREN EO 47 float directive 1386 o oooooo 111 float directive M680x0 o oooooo oooooo 130 float directive M68HC11 136 float directive TICBAX 172 float directive VAX 000002 ee eee 181 float directive x86 64 004 111 floating point numbers 0 200 25 floating point numbers double 45 floating point numbers single 47 60 floating point Alpha IEEE 0 0oooo o o o 73 floating point AMD 29K IEEE 68 f
61. M section is mergeable S section contains zero terminated strings The optional type argument may contain one of the following constants progbits section contains data Cnobits section does not contain data i e section only occupies space Note on targets where the character is the start of a comment eg ARM then another character is used instead For example the ARM port uses the character If flags contains M flag type argument must be specified as well as entsize argument Sections with M flag but not S flag must contain fixed size constants each entsize octets long Sections with both M and S must contain zero terminated strings where each character Chapter 7 Assembler Directives 59 is entsize bytes long The linker may remove duplicates within sections with the same name same entity size and same flags If no flags are specified the default flags depend upon the section name If the section name is not recognized the default will be for the section to have none of the above flags it will not be allocated in memory nor writable nor executable The section will contain data For ELF targets the assembler supports another type of section directive for compat ibility with the Solaris assembler section name flags Note that the section name is quoted There may be a sequence of comma separated flags alloc section is allocatable write section is writable execinstr section is executable This d
62. Reds 44 def directive M88K 2 004 138 def directive TICBAX cocci n ne etts 173 density directive oooooooooooooo 196 density instructions 0oooooooccccccocooo 193 density option Xtensa ooooooooo oo 191 Index dependency tracking oooooo oo oo 19 deprecated directiveS ooooooooocmmooo 66 desc diIr GllVeg s Der ne ERR ER 44 descriptor of a out symbol 36 dfloat directive M88K oooooo o ooooo 138 dfloat directive VAX 00ooooocccccccocococoo 181 difference tables altered 65 difference tables warning 16 differences mmixal eueees 149 dim direcUlve eli eph hp arenis rud 45 directives and instructionS o 0oooo oooo 23 directives M92R ac nic esa eet dede nus 123 directives M680x0 ssuseeeeeeess 191 directives machine independent 41 directives precedence 2 00000 196 directives Xtensa 0 0 cess eee eens 196 directives Z8000 cece eee ee eee 179 displacement sizing character VAX 183 dollar local symbols 000000 34 dob symbol rre 35 double directive 2 cece eee ee eee 45 double directive i386 ooooooooo oooo o Til double directive M680x0 0 130 double directive M68HC11 131 double directive TIC54X
63. Title Page as authors one or more persons or entities responsible for authorship of the modifications in the Modified Version together with at least five of the principal authors of the Document all of its principal authors if it has less than five C State on the Title page the name of the publisher of the Modified Version as the publisher D Preserve all the copyright notices of the Document E Add an appropriate copyright notice for your modifications adjacent to the other copyright notices F Include immediately after the copyright notices a license notice giving the public permission to use the Modified Version under the terms of this License in the form shown in the Addendum below G Preserve in that license notice the full lists of Invariant Sections and required Cover Texts given in the Document s license notice H Include an unaltered copy of this License I Preserve the section entitled History and its title and add to it an item stating at least the title year new authors and publisher of the Modified Version as given on the 210 Using as Title Page If there is no section entitled History in the Document create one stating the title year authors and publisher of the Document as given on its Title Page then add an item describing the Modified Version as stated in the previous sentence J Preserve the network location if any given in the Document for public access to a Transparent copy of
64. a PUSHJ instruction into a series of instructions The shortest expansion is to not expand it but just mark the call as redi rectable to a stub which 1d creates at link time but only if the original PUSHJ instruction is found not to reach the target The stub consists of the necessary instructions to form a jump to the target This happens if as can assert that the PUSHJ instruction can reach such a stub The option no pushj stubs disables this shorter expansion and the longer series of instructions is then created at assembly time The option no stubs is a syn onym intended for compatibility with future releases where generation of stubs for other instructions may be implemented Chapter 8 Machine Dependent Features 145 Usually a two operand expression see GREG base page 148 without a matching GREG directive is treated as an error by as When the option linker allocated gregs is in effect they are instead passed through to the linker which will allocate as many global registers as is needed 8 121 11 Instruction expansion When as encounters an instruction with an operand that is either not known or does not fit the operand size of the instruction as and 1d will expand the instruction into a sequence of instructions semantically equivalent to the operand fitting the instruction Expansion will take place for the following instructions GETA Expands to a sequence of four inst
65. a out 36 Using as 5 5 3 1 Descriptor This is an arbitrary 16 bit value You may establish a symbol s descriptor value by using a desc statement see Section 7 21 desc page 44 A descriptor value means nothing to as 5 5 3 2 Other This is an arbitrary 8 bit value It means nothing to as 5 5 4 Symbol Attributes for COFF The COFF format supports a multitude of auxiliary symbol attributes like the primary symbol attributes they are set between def and endef directives 5 5 4 1 Primary Attributes The symbol name is set with def the value and type respectively with val and type 5 5 4 2 Auxiliary Attributes The as directives dim line scl size and tag can generate auxiliary symbol table information for COFF 5 5 5 Symbol Attributes for SOM The SOM format for the HPPA supports a multitude of symbol attributes set with the EXPORT and IMPORT directives The attributes are described in HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 under the IMPORT and EXPORT assembler directive documentation Chapter 6 Expressions 37 6 Expressions An expression specifies an address or numeric value Whitespace may precede and or follow an expression The result of an expression must be an absolute number or else an offset into a particular section If an expression is not absolute and there is not enough information when as sees the expression to know its section a second pass over t
66. an empty statement instruction operand_1 operand_2 3 6 Constants A constant is a number written so that its value is known by inspection without knowing any context Like this byte 74 0112 092 Ox4A OX4a J J All the same value ascii Ring the bell 7 A string constant octa 0x123456789abcdef0123456789ABCDEFO A bignum float 0f 314159265358979323846264338327N 95028841971 693993751E 40 pi a flonum 3 6 1 Character Constants There are two kinds of character constants A character stands for one character in one byte and its value may be used in numeric expressions String constants properly called string literals are potentially many bytes and their values may not be used in arithmetic expressions 3 6 1 1 Strings A string is written between double quotes It may contain double quotes or null charac ters The way to get special characters into a string is to escape these characters precede them with a backslash V character For example represents one backslash the first A 24 Using as is an escape which tells as to interpret the second character literally as a backslash which prevents as from recognizing the second as an escape character The complete list of escapes follows b Mnemonic for backspace for ASCII this is octal code 010 f Mnemonic for FormFeed for ASCII this is octal code 014 n Mnemonic for newline for ASCII this is octal code 012 r Mnemonic for ca
67. and make it the current section symbol set value symbol equ value Equate a constant value to a symbol which is placed in the symbol table symbol may not be previously defined Chapter 8 Machine Dependent Features 175 Space size in bits bes size in bits Reserve the given number of bits in the current section and zero fill them If a label is used with space it points to the first word reserved With bes the label points to the last word reserved sslist ssnolist Controls the inclusion of subsym replacement in the listing output Ignored String string string_n pstring string string_n Place 8 bit characters from string into the current section string zero fills the upper 8 bits of each word while pstring puts two characters into each word filling the most significant bits first Unused space is zero filled If a label is used it points to the first word initialized stag struct offset name 1 element count 1 name 2 element count 2 tname tag stagx tcount name n element count n ssize endstruct label tag stag tab Assign symbolic offsets to the elements of a structure stag defines a symbol to use to reference the structure offset indicates a starting value to use for the first element encountered otherwise it defaults to zero Each element can have a named offset name which is a symbol assigned the value of the element s offset into the structu
68. are generic which means the assembler is required to preserve their semantics but may not translate them directly to the specific opcodes with the same names Instead the assembler may optimize a generic opcode and select a better instruction to use in its place see Section 8 133 8 Xtensa Optimizations page 193 or the assembler may relax the instruction to handle operands that are out of range for the corresponding specific opcode see Section 8 133 9 Xtensa Relaxation page 194 Only use specific opcodes when it is essential to select the exact machine instructions produced by the assembler Using specific opcodes unnecessarily only makes the code less efficient by disabling assembler optimization and less flexible by disabling relaxation Note that this special handling of underscore prefixes only applies to Xtensa opcodes not to either built in macros or user defined macros When an underscore prefix is used with a macro e g _NOP it refers to a different macro The assembler generally provides built in macros both with and without the underscore prefix where the underscore versions behave as if the underscore carries through to the instructions in the macros For example _NOP expands to OR a1 a1 a1 The underscore prefix only applies to individual instructions not to series of instructions For example if a series of instructions have underscore prefixes the assembler will not transform the individual instructions but i
69. as a contiguous program with zeros filled in the gaps between the LOC directives If you need sparse programs you might try and get the wanted effect with a linker script and splitting up the code parts into sections see Section 7 76 Section page 57 Assembly code for this to be compatible with mmixal would look something like if 0 LOC away_expression else section away ax fi as will not execute the LOC directive and mmixal ignores the lines with This construct can be used generally to help compatibility Symbols can t be defined twice not even to the same value Instruction mnemonics are recognized case insensitive though the IS and GREG pseudo operations must be specified in upper case characters There s no unicode support The following is a list of programs in mmix tar gz available at http www cs faculty stanford edu knuth mmix news html last checked with the version dated 2001 08 25 md5sum c393470cfc86fac040487d22d2bf0172 that assemble with mmixal but do not assemble with as silly mms LOC to a previous address sim mms Redefines symbol Done test mms Uses the serial operator amp Chapter 8 Machine Dependent Features 151 8 122 MSP 430 Dependent Features 8 122 14 Options as has only m flag which selects the mpu arch Currently has no effect 8 122 15 Syntax 8 122 15 1 Macros The macro syntax used on the MSP 430 is like that described in the MSP 430 F
70. data 1 Skip This is functionally identical to the space directive Word On the Sparc the word directive produces 32 bit values instead of the 16 bit values it produces on many other machines xword On the Sparc V9 processor the xword directive produces 64 bit values 168 Using as 8 129 TIC54X Dependent Features 8 129 9 Options The TMS320C54x version of as has a few machine dependent options You can use the mfar mode option to enable extended addressing mode All addresses will be assumed to be gt 16 bits and the appropriate relocation types will be used This option is equivalent to using the far_mode directive in the assembly code If you do not use the mfar mode option all references will be assumed to be 16 bits This option may be abbreviated to mf You can use the mcpu option to specify a particular CPU This option is equivalent to using the version directive in the assembly code For recognized CPU codes see See Section 8 129 17 version page 171 The default CPU version is 542 You can use the merrors to file option to redirect error output to a file this pro vided for those deficient environments which don t provide adequate output redirection This option may be abbreviated to me 8 129 10 Blocking A blocked section or memory block is guaranteed not to cross the blocking boundary usually a page or 128 words if it is smaller than th
71. e g jsr while synthetic instructions remained shrinkable jbsr John fixed many bugs including true tested cross compilation support and one bug in relaxation that took a week and required the proverbial one bit fix Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k completed support for some COFF targets 68k 1386 SVR3 and SCO Unix added support for MIPS ECOFF and ELF targets wrote the initial RS 6000 and PowerPC assembler and made a few other minor patches 1 Any more details 206 Using as Steve Chamberlain made as able to generate listings Hewlett Packard contributed support for the HP9000 300 Jeff Law wrote GAS and BFD support for the native HPPA object format SOM along with a fairly extensive HPPA testsuite for both SOM and ELF object formats This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support Support for ELF format files has been worked on by Mark Eichin of Cygnus Support original incomplete implementation for SPARC Pete Hoogenboom and Jeff Law at the University of Utah HPPA mainly Michael Meissner of the Open Software Foundation 1386 mainly and Ken Raeburn of Cygnus Support sparc and some initial 64 bit support Linas Vepstas added GAS support for the ESA 390 IBM 370 architecture Richard Henderson rewrote the Alpha assembler Klaus Kaempf wrote GAS and BFD support for openVMS Alpha Timothy Wall Mi
72. endorsements of your Modified Version by various parties for example statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard You may add a passage of up to five words as a Front Cover Text and a passage of up to 25 words as a Back Cover Text to the end of the list of Cover Texts in the Modified Version Only one passage of Front Cover Text and one of Back Cover Text may be added by or through arrangements made by any one entity If the Document already includes a cover text for the same cover previously added by you or by arrangement made by the same entity you are acting on behalf of you may not add another but you may replace the old one on explicit permission from the previous publisher that added the old one The author s and publisher s of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version COMBINING DOCUMENTS You may combine the Document with other documents released under this License under the terms defined in section 4 above for modified versions provided that you include in the combination all of the Invariant Sections of all of the original documents Appendix A GNU Free Documentation License 211 unmodified and list them all as Invariant Sections of your combined work in its license notice The combined work need only contain one copy of this License an
73. enter locct leave macro listoff Beyond those implemented for compatibility as supports one additional assembler di rective for the HPPA param It conveys register argument locations for static functions Its syntax closely follows the export directive These are the additional directives in as for the HPPA block n blockz n Reserve n bytes of storage and initialize them to zero call Mark the beginning of a procedure call Only the special case with no arguments is allowed callinfo param value flag Specify a number of parameters and flags that define the environment for a procedure param may be any of frame frame size entry gr end of general regis ter range entry_fr end of float register range entry_sr end of space register range The values for flag are calls or caller proc has subroutines no calls proc does not call subroutines save_rp preserve return pointer save_sp proc preserves stack pointer no_unwind do not unwind this proc hpux_int proc is interrupt routine code Assemble into the standard section called TEXT subsection CODE copyright string In the SOM object format insert string into the object code marked as a copyright string copyright string In the ELF object format insert string into the object code marked as a version string enter Not yet supported the assembler
74. extended basic block That is the relocation with the lowest address must be executed first at runtime Used with an 1da instruction to load the address of a TLS descriptor for the current module in the GOT Similar in other respects to t1sgd Used with an 1dq instruction to load the offset of the TLS symbol within its module s thread local storage block Also known as the dynamic thread pointer offset or dtp relative offset Like gprel relocations except they compute dtp relative offsets Used with an 1dq instruction to load the offset of the TLS symbol from the thread pointer Also known as the tp relative offset Like gprel relocations except they compute tp relative offsets 8 102 9 Floating Point The Alpha family uses both IEEE and VAX floating point numbers 8 102 10 Alpha Assembler Directives as for the Alpha supports many additional directives for compatibility with the native assembler l his section describes them only briefly These are the additional directives in as for the Alpha arch cpu Specifies the target processor This is equivalent to the mcpu command line option See Section 8 102 7 Alpha Options page 70 for a list of values for cpu 74 Using as ent function n Mark the beginning of function An optional number may follow for compat ibility with the OSF 1 assembler but is ignored When generating mdebug information this will create a procedure descriptor for the function I
75. for compatibility with other AMD 29K assemblers Warning In most versions of the GNU assembler the directive space has the effect of block See Chapter 8 Machine Dependencies page 67 Chapter 7 Assembler Directives 61 7 84 stabd stabn stabs There are three directives that begin stab All emit symbols see Chapter 5 Symbols page 33 for use by symbolic debuggers The symbols are not entered in the as hash table they cannot be referenced elsewhere in the source file Up to five fields are required string This is the symbol s name It may contain any character except 000 so is more general than ordinary symbol names Some debuggers used to code arbitrarily complex structures into symbol names using this field type An absolute expression The symbol s type is set to the low 8 bits of this expression Any bit pattern is permitted but 1d and debuggers choke on silly bit patterns other An absolute expression The symbol s other attribute is set to the low 8 bits of this expression desc An absolute expression The symbol s descriptor is set to the low 16 bits of this expression value An absolute expression which becomes the symbol s value If a warning is detected while reading a stabd stabn or stabs statement the symbol has probably already been created you get a half formed symbol in your object file This is compatible with earlier assemblers Stabd type other desc The name o
76. for these control registers and status bits psw bpsw pc bpc rpt_c rpt_s rpt_e mod_s mod_e iba fO f1 2 f3 f4 f5 f6 f7 Processor Status Word Backup Processor Status Word Program Counter Backup Program Counter Repeat Count Repeat Start address Repeat End address Modulo Start address Modulo End address Instruction Break Address Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 94 Using as s Same as flag 4 saturation flag v Same as flag 5 overflow flag va Same as flag 6 sticky overflow flag le Same as flag 7 carry borrow flag b Same as flag 7 carry borrow flag 8 107 30 6 Addressing Modes as understands the following addressing modes for the D30V Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct Rn Register indirect Rn Register indirect with post increment Rn Register indirect with post decrement SP Register indirect with pre decrement disp Rn Register indirect with displacement addr PC relative address for branch or rep imm Immediate data the is optional and ignored 8 107 31 Floating Point The D30V has no hardware floating point but the float and double directives gen erates IEEE floating point numbers for compatibility with other development tools 8 107 382 Opcodes For detailed information on the D30V machine instruction set see D30V Architecture A VLIW Micropr
77. fred high expression The high directive computes the value of its expression and places the upper 16 bits of the result into the immediate field of the instruction For example seth r0 high 0x12345678 compute rO 0x12340000 seth r0 high fred compute r0 upper 16 bits of address of fred 124 Using as shigh expression The shigh directive is very similar to the high directive It also computes the value of its expression and places the upper 16 bits of the result into the immediate field of the instruction The difference is that shigh also checks to see if the lower 16 bits could be interpreted as a signed number and if so it assumes that a borrow will occur from the upper 16 bits To compensate for this the shigh directive pre biases the upper 16 bit value by adding one to it For example For example seth r0 shigh 0x12345678 compute rO seth r0 shigh 0x00008000 compute rO 0x12340000 0x00010000 In the second example the lower 16 bits are 0x8000 If these are treated as a signed value and sign extended to 32 bits then the value becomes Oxffff8000 If this value is then added to 0x00010000 then the result is 0x00008000 This behaviour is to allow for the different semantics of the or3 and add3 instructions The or3 instruction treats its 16 bit immediate argument as un signed whereas the add3 treats its 16 bit immediate as a signed value So for example seth r0 shigh 0x00008000 add3 r0 r0 1lo
78. function name The linker will attempt to shorten this call sequence if name is within a 22bit offset of the call Only valid if the mrelax command line switch has been enabled longjump name Indicates that the following sequence of instructions is a long jump to label name The linker will attempt to shorten this code sequence if name is within 190 Using as a 22bit offset of the jump Only valid if the mrelax command line switch has been enabled For information on the V850 instruction set see V850 Family 32 16 Bit single Chip Microcontroller Architecture Manual from NEC Ltd Chapter 8 Machine Dependent Features 191 8 133 Xtensa Dependent Features This chapter covers features of the GNU assembler that are specific to the Xtensa archi tecture For details about the Xtensa instruction set please consult the Xtensa Instruction Set Architecture ISA Reference Manual 8 133 6 Command Line Options The Xtensa version of the GNU assembler supports these special options density no density Enable or disable use of the Xtensa code density option 16 bit instructions See Section 8 133 8 1 Using Density Instructions page 193 If the processor is configured with the density option this is enabled by default otherwise it is always disabled relax no relax Enable or disable relaxation of instructions with immediate operands that are outside the legal range for the instructions See Section 8 133 9 Xtensa
79. in a document you have written include a copy of the License in the document and put the following copyright and license notices just after the title page Copyright C year your name Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 1 or any later version published by the Free Software Foundation with the Invariant Sections being list their titles with the Front Cover Texts being list and with the Back Cover Texts being list A copy of the license is included in the section entitled GNU Free Documentation License If you have no Invariant Sections write with no Invariant Sections instead of saying which ones are invariant If you have no Front Cover Texts write no Front Cover Texts instead of Front Cover Texts being list likewise for Back Cover Texts If your document contains nontrivial examples of program code we recommend releasing these examples in parallel under your choice of free software license such as the GNU General Public License to permit their use in free software Index Midi dida ii tas 22 PARP nuria in ido wee Ba ad din 21 FNOLAPP sion a oe iia ice 21 in symbol names 88 92 98 160 163 acos math builtin TIC54X 170 asin math builtin TIC54X 170 atan math builtin TIC54X 170 atan2 math builtin TIC54X 170 ceil
80. is edes Rc 1 7 Error and Warning Messages 000 eee eeeeee 2 Command Line Options 2 1 Enable Listings alcdhins 00000045 2 2 Diada 2 0 Work Faster SL acordar da a 2 4 include Search Path SP path 000 2 5 Difference Tables K 0 0 0 0 c eee eects 2 6 Include Local Labels L 00 0 0 eee 2 7 Configuring listing output listing 2 8 Assemble in MRI Compatibility Mode M 2 9 Dependency Tracking MD 0 00 ellen 2 10 Name the Object File 0 0 cece ee eee eee 2 11 Join Data and Text Sections R 0000 2 12 Display Assembly Statistics statistics 2 13 Compatible Output traditional format 2 14 Announce Version v 0 eee eee eee eee 2 15 Control Warnings W warn no warn fatal warnings ee cee ete nee 2 16 Generate Object File in Spite of Errors Z 3E 0000 CPC 3 1 Preprocessing sseeeeeeeee heh hh 3 2 Whitespace eiie datada oon e ESCENA dee 3 9 A toon od e rede tion rte a Rena hod BA SYMONS iicet pini ee aote ad pate us han ed RARE 3 0 Statements or on e RACER HRS Cee eae aed BRE Cum 3 6 1 Character Constants ssssse sees eese 9 L 1 Strings ed ex e bere rere dena 39 0 L2 Characters arrasa
81. line that has zero or more input file names The input files are read from left file name to right A command line argument in any position that has no special meaning is taken to be an input file name If you give as no file names it attempts to read one input file from the as standard input which is normally your terminal You may have to type to tell as there is no more program to assemble Use if you need to explicitly name the standard input file in your command line If the source is empty as produces a small empty object file Filenames and Line numbers There are two ways of locating a line in the input file or files and either may be used in reporting error messages One way refers to a line number in a physical file the other refers to a line number in a logical file See Section 1 7 Error and Warning Messages page 14 Physical files are those files named in the command line given to as Logical files are simply names declared explicitly by assembler directives they bear no relation to physical files Logical file names help error messages reflect the original source file when as source is itself synthesized from other files as understands the directives emitted by the gcc preprocessor See also Section 7 37 file page 47 1 6 Output Object File Every time you run as it produces an output file which is your assembly language program translated into numbers This file is the object file
82. listing You can use other letters to select specific options for the list ah requests a high level language listing al requests an output program assembly listing and as requests a symbol table listing High level listings require that a compiler debugging option like g be used and that assembly listings al be requested also Use the ac option to omit false conditionals from a listing Any lines which are not assembled because of a false if or ifdef or any other conditional or a true if followed by an else will be omitted from the listing Use the ad option to omit debugging directives from the listing Once you have specified one of these options you can further control listing output and its appearance using the directives list nolist psize eject title and sbttl The an option turns off all forms processing If you do not request listing output with one of the a options the listing control directives have no effect The letters after a may be combined into one option e g aln Note if the assembler source is coming from the standard input eg because it is being created by gcc and the pipe command line switch is being used then the listing will not contain any comments or preprocessor directives This is because the listing code buffers input source lines from stdin only after they have been preprocessed by the assembler This reduce
83. math builtin TIC54X 170 cos math builtin TIC54X 170 cosh math builtin TIC54X 170 cvf math builtin TIC54X 170 cvi math builtin TIC54X 170 exp math builtin TIC5AX Luuuuu 170 fabs math builtin TIC54X 170 firstch subsym builtin TIC54X 177 floor math builtin TIC54X 170 fmod math builtin TIC54X 170 int math builtin TIC54X 170 iscons subsym builtin TIC54X 177 isdefed subsym builtin TIC54X 177 ismember subsym builtin TIC54X 177 isname subsym builtin TIC54X 177 isreg subsym builtin TIC54X Dr 1astch subsym builtin TIC54X 177 1dexp math builtin TIC54X 170 log math builtin TIC54X 170 log10 math builtin TIC54X 170 max math builtin TIC54X 170 min math builtin TIC54X 171 pow math builtin TIC54X Luuuuu 171 round math builtin TIC54X 171 sgn math builtin TIC54X 171 sin math builtin TIC54X 171 sinh math builtin TIC54X 171 sqrt math builtin TIC54X 171 structacc subsym builtin TIC54X 177 structsz subsym builtin TIC54X Lie symcmp subsym builtin TIC54X
84. minus the address of the long jump to sym2 6 If there were several occurrences of word symi sym2 before the secondary jump table all of them are adjusted If there was a word sym3 sym4 that also did not fit in sixteen bits a long jump to sym4 is included in the secondary jump table and the word directives are adjusted to contain sym3 minus the address of the long jump to sym4 and so on for as many entries in the original jump table as necessary 66 Using as 7 100 Deprecated Directives One day these directives won t work They are included for compatibility with older assemblers abort line Chapter 8 Machine Dependent Features 67 8 Machine Dependent Features The machine instruction sets are almost by definition different on each machine where as runs Floating point representations vary as well and as often supports a few additional directives or command line options for compatibility with other assemblers on a particu lar platform Finally some versions of as support special pseudo instructions for branch optimization This chapter discusses most of these differences though it does not include details on any machine s instruction set For details on that subject see the hardware manufacturer s manual 68 Using as 8 101 AMD 29K Dependent Features 8 101 1 Options as has no additional command line options for the AMD 29K family 8 101 2 Syntax 8 101 2 1 Macros The macro syntax us
85. mno mfpt Enable or disable the use of the MFPT instruction mmultiproc mno multiproc Enable or disable the use of multiprocessor instructions TSTSET and WRTLCK mmxps mno mxps Enable or disable the use of the MFPS and MTPS instructions mspl mno spl Enable or disable the use of the SPL instruction Enable or disable the use of the microcode instructions LDUB MED and XFC 8 123 19 3 CPU Model Options These options enable the instruction set extensions supported by a particular CPU and disables all other extensions mkaii KA11 CPU Base line instruction set only mkb11 KB11 CPU Enable extended instruction set and SPL mkdiila KD11 A CPU Enable limited extended instruction set mkdiib KD11 B CPU Base line instruction set only mkdiid KD11 D CPU Base line instruction set only mkdite KD11 E CPU Enable extended instruction set MFPS and MTPS mkdiif mkdiih mkdiiq KD11 F KD11 H or KD11 Q CPU Enable limited extended instruction set MFPS and MTPS mkdiilk KD11 K CPU Enable extended instruction set LDUB MED MFPS MFPT MTPS and XFC mkdiiz KD11 Z CPU Enable extended instruction set CSM MFPS MFPT MTPS and SPL mfii F11 CPU Enable extended instruction set MFPS MFPT and MTPS mjii J11 CPU Enable extended instruction set CSM MFPS MFPT MTPS SPL TSTSET and WRTLCK mtii T11 CPU Enable limited extended instruction set MFPS and MTPS Chapter 8 Mach
86. not subtract arguments from different sections Is Equal To lt gt Is Not Equal To lt Is Less Than gt Is Greater Than gt Is Greater Than Or Equal To lt Is Less Than Or Equal To Chapter 6 Expressions 39 The comparison operators can be used as infix operators A true results has a value of 1 whereas a false result has a value of 0 Note these operators perform signed comparisons 4 Lowest Precedence amp amp Logical And Logical Or These two logical operations can be used to combine the results of sub expressions Note unlike the comparison operators a true result returns a value of 1 but a false results does still return 0 Also note that the logical or operator has a slightly lower precedence than logical and In short it s only meaningful to add or subtract the offsets in an address you can only have a defined section in one of the two arguments 40 Using as Chapter 7 Assembler Directives 41 7 Assembler Directives All assembler directives have names that begin with a period The rest of the name is letters usually in lower case This chapter discusses directives that are available regardless of the target machine configuration for the GNU assembler Some machine configurations provide additional di rectives See Chapter 8 Machine Dependencies page 67 7 1 abort This directive stops the assembly immediately It is for compatibility with other assem blers The origi
87. or PC For example ldab 1024 sp ldd 10 x orab 3 x stab 2 y ldx a pc sty d sp 8 118 46 Symbolic Operand Modifiers The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands The general syntax is the following modifier symbol addr This modifier indicates to the assembler and linker to use the 16 bit physical address corresponding to the symbol This is intended to be used on memory window systems to map a symbol in the memory bank window If the symbol is in a memory expansion part the physical address corresponds to the symbol address within the memory bank window If the symbol is not in a memory ex pansion part this is the symbol address using or not using the addr modifier has no effect in that case page This modifier indicates to use the memory page number corresponding to the symbol If the symbol is in a memory expansion part its page number is computed by the linker as a namber used to map the page containing the symbol 136 Using as in the memory bank window If the symbol is not in a memory expansion part the page number is 0 hi This modifier indicates to use the 8 bit high part of the physical address of the symbol hlo This modifier indicates to use the 8 bit low part of the physical address of the symbol For example a 68HC12 call to a function foo_example stored in memory expansion part could be written as follows call addr f
88. possible to receive spurious warnings due to using exact bit patterns as immediate constants Specifies that the assembled code should be marked as being targeted at the V850 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850E1 processor This allows the linker to detect attempts to link such code with code assembled for other processors Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended vari ants of the process This allows the production of binaries that contain target specific code but which are also intended to be used in a generic fashion For example libgcc a contains generic routines used by the code produced by GCC for all versions of the v850 architecture together with support routines only used by the V850E architecture Chapter 8 Machine Dependent Features 185 mrelax Enables relaxation This allows the longcall and longjump pseudo ops to be used in the assembler source code These ops label sections of code which are either a long function call or a long branch The assembler will then flag thes
89. predefined special register names except when used in PUT and GET instructions By default some instructions are expanded to fit the size of the operand or an external symbol see Section 8 121 11 MMIX Expand page 145 By passing no expand no such expansion will be done instead causing errors at link time if the operand does not fit The mmixal documentation see mmixsite page 145 specifies that global registers allocated with the GREG directive see MMIX greg page 148 and initialized to the same non zero value will refer to the same global register This isn t strictly enforceable in as since the final addresses aren t known until link time but it will do an effort unless the no merge gregs option is specified Register merging isn t yet implemented in 1d as will warn every time it expands an instruction to fit an operand unless the option x is specified It is believed that this behaviour is more useful than just mimicking mmixal s behaviour in which instructions are only expanded if the x option is specified and assembly fails otherwise when an instruction needs to be expanded It needs to be kept in mind that mmixal is both an assembler and linker while as will expand instructions that at link stage can be contracted Though linker relaxation isn t yet implemented in 1d The option x also imples linker allocated gregs If instruction expansion is enabled as can expand
90. registers in certain cases Unfortunately gcc and possibly many other programs use this reversed syntax so we re stuck with it For example fsub st st 3 results in st 3 being updated to 4st st 3 rather than the expected st 3 st This happens with all the non commutative arithmetic floating point operations with two register operands where the source register is Ast and the destination register is sti 8 112 24 Specifying CPU Architecture as may be told to assemble for a particular CPU architecture with the arch cpu type directive This directive enables a warning when gas detects an instruction that is not supported on the CPU specified The choices for cpu type are 18086 1186 1286 1386 1486 1586 i686 pentium pentiumpro pentium4 k6 athlon sledgehammer Apart from the warning there are only two other effects on as operation Firstly if you specify a CPU other than i486 then shift by one instructions such as sarl 1 eax will automatically use a two byte opcode sequence The larger three byte opcode sequence is used on the 486 and when no architecture is specified because it executes faster on the 486 Note that you can explicitly request the two byte opcode by writing sarl eax Secondly if you specify 18086 i186 or i286 and code16 or codei6gcc then byte offset conditiona
91. represent Chapter 8 Machine Dependent Features 177 symlen str Returns the length of str symcmp str1 str2 Returns 0 if str str2 non zero otherwise firstch str ch Returns index of the first occurrence of character constant ch in str lastch str ch Returns index of the last occurrence of character constant ch in str isdefed symbol Returns zero if the symbol symbol is not in the symbol table non zero other wise ismember symbol list Assign the first member of comma separated string list to symbol list is re assigned the remainder of the list Returns zero if list is a null string Both arguments must be subsyms iscons expr Returns 1 if string expr is binary 2 if octal 3 if hexadecimal 4 if a character 5 if decimal and zero if not an integer isname name Returns 1 if name is a valid symbol name zero otherwise isreg reg Returns 1 if reg is a valid predefined register name ARO AR7 only structsz stag Returns the size of the structure or union represented by stag structacc stag Returns the reference point of the structure or union represented by stag Al ways returns zero 8 129 19 Memory mapped Registers The following symbols are recognized as memory mapped registers 178 Using as 8 130 Z8000 Dependent Features The Z8000 as supports both members of the Z8000 family the unsegmented Z8002 with 16 bit addresses and the segmented Z8001 with 24 bit addresses W
92. rue UD Ede 153 SIDBo fpa s suco oro ats nien bet a MUR Gale co 153 yino fplls ve bbER RI ener e auri eva bee Eum 153 mno kev 11 no scees ch 2 ee e TEDT PPS 153 mno limited eis llle ee ee eee 154 nino mfpi snoleireeleleleertekeerviteBIveS 154 mno microcode 0 eee eene 154 st no mullpro6 2 lex ies etree be aed 154 MANO MAPS vis rai ke euer Ra 154 AMOO PIC so da sew a oad ada 153 Zinho Spl aei ird hard de acs gists METER deir 154 moabi command line option ARM 80 Sup T P 153 mrelax command line option V850 184 A 133 mshort do ble iia da PER RSS 133 SIBSDL fin 2o ii 154 zB ossis deni nae tos Garba gz SE HU a a RUE 154 mthumb command line option ARM 80 mthumb interwork command line option ARM 80 mv850 command line option V850 184 mv850any command line option V850 184 mv850e command line option V850 184 mv850e1 command line option V850 184 N command line option CRIS 83 no mdebug command line option Alpha 70 n relax option 1er 119 no warn explicit parallel conflicts option WAS ARK E M ETE 123 nocpp ignored MIPS ssssussse 141 RO aeaea ii dia som deeds 19 Pus LAE DAP aorta Bae 19 gt A t pde etes dur dh 160 relax command line option Alpha 70 S ignored on VAX 0oooocccccccccrrr eee 180 A es due gue raa a edge eese 160 215 t i
93. s machine architecture manual for this information 1 2 The GNU Assembler GNU as is really a family of assemblers If you use or have used the GNU assembler on one architecture you should find a fairly similar environment when you use it on another architecture Each version has much in common with the others including object file formats most assembler directives often called pseudo ops and assembler syntax as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker 1d Nevertheless we ve tried to make as assemble correctly everything that other assemblers for the same machine would assemble Any exceptions are documented explicitly see Chapter 8 Machine Dependencies page 67 This doesn t mean as always uses the same syntax as another assembler for the same architecture for example we know of several incompatible versions of 680x0 assembly language syntax Unlike older assemblers as is designed to assemble a source program in one pass of the source file This has a subtle impact on the org directive see Section 7 63 org page 54 1 3 Object File Formats The GNU assembler can be configured to produce several alternative object file formats For the most part this does not affect how you write assembly language programs but di rectives for debugging symbols are typically different in different file formats See Section 5 5 Symbol Attributes page 35 1 4 Command Line After
94. specified the assembler will use the setting for mcpu The architecture option can be extended with the same instruction set extension options as the mcpu option mfpu floating point format This option specifies the floating point format to assemble for The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit The following format options are recognized softfpa fpe fpe2 fpe3 fpa fpa10 fpa11 arm7500fe softvfp softvfptvfp vfp vfp10 vfpiO rO vfp9 vfpxd arm1020t and arm1020e In addition to determining which instructions are assembled this option also affects the way in which the double assembler directive behaves when assem bling little endian code 80 Using as The default is dependent on the processor selected For Architecture 5 or later the default is to assembler for VFP instructions for earlier architectures the default is to assemble for FPA instructions mthumb This option specifies that the assembler should start assembling Thumb in structions that is it should behave as though the file starts with a code 16 directive mthumb interwork This option specifies that the output generated by the assembler should be marked as supporting interworking mapcs 26 32 This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure Callin
95. text section literals op tion is not used The assembler will automatically place text section literal pools before ENTRY instruc tions so the literal_position directive is only needed to specify some other location for a literal pool You may need to add an explicit jump instruction to skip over an inline literal pool For example an interrupt vector does not begin with an ENTRY instruction so the as sembler will be unable to automatically find a good place to put a literal pool Moreover the code for the interrupt vector must be at a specific starting address so the literal pool cannot come before the start of the code The literal pool for the vector must be explic itly positioned in the middle of the vector before any uses of the literals of course The literal_position directive can be used to do this In the following code the literal for Mw will automatically be aligned correctly and is placed after the unconditional jump global M code_start j continue literal_position align 4 continue movi a4 M 8 133 10 7 literal prefix The literal_prefix directive allows you to specify different sections to hold literals from different portions of an assembly file With this directive a single assembly file can be used to generate code into multiple sections including literals generated by the assembler begin literal prefix name end literal prefix Chapter 8 Machine Dependent Features 199 For the cod
96. the CRIS specific options The following options are available when as is configured for a D10V processor 0 Optimize output by parallelizing instructions The following options are available when as is configured for a D30V processor 0 Optimize output by parallelizing instructions n Warn when nops are generated N Warn when a nop after a 32 bit multiply instruction is generated The following options are available when as is configured for the Intel 80960 processor 6 Using as ACA ACA A ACB ACC AKA AKB AKC AMC Specify which variant of the 960 architecture is the target b Add code to collect statistics about branches taken no relax Do not alter compare and branch instructions for long displacements error if necessary The following options are available when as is configured for the Ubicom IP2K series mip2022ext Specifies that the extended IP2022 instructions are allowed mip2022 Restores the default behaviour which restricts the permitted instructions to just the basic IP2022 ones The following options are available when as is configured for the Renesas M32R formerly Mitsubishi M32R series m32rx Specify which processor in the M32R family is the target The default is nor mally the M32R but this option changes it to the M32RX warn explicit parallel conflicts or Wp Produce warning messages when questionable parallel constructs are encoun tered no warn explicit parall
97. the Document and likewise the network locations given in the Document for previous versions it was based on These may be placed in the History section You may omit a network location for a work that was published at least four years before the Document itself or if the original publisher of the version it refers to gives permission K In any section entitled Acknowledgements or Dedications preserve the section s title and preserve in the section all the substance and tone of each of the contributor acknowledgements and or dedications given therein L Preserve all the Invariant Sections of the Document unaltered in their text and in their titles Section numbers or the equivalent are not considered part of the section titles M Delete any section entitled Endorsements Such a section may not be included in the Modified Version N Do not retitle any existing section as Endorsements or to conflict in title with any Invariant Section If the Modified Version includes new front matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document you may at your option designate some or all of these sections as invariant To do this add their titles to the list of Invariant Sections in the Modified Version s license notice These titles must be distinct from any other section titles You may add a section entitled Endorsements provided it contains nothing but
98. the H8 300 family h8300hn Recognize and emit additional instructions for the H8 300H variant in normal mode and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family h8300sn Recognize and emit additional instructions for the H8S variant in normal mode and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family On the H8 300 family including the H8 300H word directives generate 16 bit num bers 8 108 5 Opcodes For detailed information on the H8 300 machine instruction set see H8 300 Series Pro gramming Manual For information specific to the H8 300H see H8 300H Series Program ming Manual Renesas as implements all the standard H8 300 opcodes No additional pseudo instructions are needed on this family Four H8 300 instructions add cmp mov sub are defined with variants using the suffixes b w and 1 to specify the size of a memory operand as supports these suffixes but does not require them since one of the operands is always a register as can deduce the correct size For example since rO refers to a 16 bit register mov r0 foo is equivalent to mov w rO 0foo If you use the size suffixes as issues a warning when the suffix and the register size do not match 98 Using as 8 109 H8 500 Dependent Features 8 109 1 Options as has no additional command line options for the Renesas formerly Hitachi H8 500 fa
99. the program name as the command line may contain options and file names Options may appear in any order and may be before after or between file names The order of file names is significant two hyphens by itself names the standard input file explicitly as one of the files for as to assemble Except for any command line argument that begins with a hyphen is an option Each option changes the behavior of as No option changes the way another option works An option is a followed by one or more letters the case of the letter is important All options are optional Some options expect exactly one file name to follow them The file name may either immediately follow the option s letter compatible with older assemblers or it may be the next command argument GNU standard These two command lines are equivalent Chapter 1 Overview 13 as o my object file o mumble s as omy object file o mumble s 1 5 Input Files We use the phrase source program abbreviated source to describe the program input to one run of as The program may be in one or more files how the source is partitioned into files doesn t change the meaning of the source The source program is a concatenation of the text in all the files in the order specified Each time you run as it assembles exactly one source program The source program is made up of one or more files The standard input is also a file You give as a command
100. the section of new Ic is the same as the current subsection org may only increase the location counter or leave it unchanged you cannot use org to move the location counter backwards Because as tries to assemble programs in one pass new lc may not be undefined If you really detest this restriction we eagerly await a chance to share your improved assembler Beware that the origin is relative to the start of the section not to the start of the subsection This is compatible with other people s assemblers When the location counter of the current subsection is advanced the intervening bytes are filled with fill which should be an absolute expression If the comma and fill are omitted fill defaults to zero 7 64 p2align wl abs expr abs expr abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the number of low order zero bits the location counter must have after advancement For example p2align 3 advances the location counter until it a multiple of 8 If the location counter is already a multiple of 8 no change is needed Chapter 7 Assembler Directives 55 The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on some systems if the section is marked as containing code and the fill value is o
101. to recognize the symbol syntax used for ELF SVR4 PIC position independent code see crispic page 84 This will also affect expansion of instructions The expansion with pic will use PC relative rather than slightly faster absolute addresses in those expansions When N is specified as will emit a warning when a 16 bit branch instruction is ex panded into a 32 bit multiple instruction construct see Section 8 105 23 CRIS Expand page 83 8 105 23 Instruction expansion as will silently choose an instruction that fits the operand size for register constant operands For example the offset 127 in move d r3 127 r4 fits in an instruction using a signed byte offset Similarly move d r2 32767 r1 will generate an instruction using a 16 bit offset For symbolic expressions and constants that do not fit in 16 bits including the sign bit a 32 bit offset is generated For branches as will expand from a 16 bit branch instruction into a sequence of in structions that can reach a full 32 bit address Since this does not correspond to a single instruction such expansions can optionally be warned about See Section 8 105 22 CRIS Opts page 83 8 105 24 Syntax There are different aspects of the CRIS assembly syntax 84 Using as 8 105 24 1 Special Characters The character is a line comment character It starts a comment if and only if it is placed at the beginning of a line A character star
102. understand e A guess about what the bug is or what it depends on Such guesses are usually wrong Even we cannot guess right about such things without first using the debugger to find the facts 204 Using as Chapter 10 Acknowledgements 205 10 Acknowledgements If you have contributed to as and your name isn t listed here it is not meant as a slight We just don t know about it Send mail to the maintainer and we ll correct the situation Currently the maintainer is Ken Raeburn email address raeburn cygnus com Dean Elsner wrote the original GNU assembler for the VAX Jay Fenlason maintained GAS for a while adding support for GDB specific debug infor mation and the 68k series machines most of the preprocessing pass and extensive changes in messages c input file c write c K Richard Pixley maintained GAS for a while adding various enhancements and many bug fixes including merging support for several processors breaking GAS up to handle multiple object file format back ends including heavy rewrite testing an integration of the coff and b out back ends adding configuration including heavy testing and verifica tion of cross assemblers and file splits and renaming converted GAS to strictly ANSI C including full prototypes added support for m680 34 0 and cpu32 did considerable work on i960 including a COFF port including considerable amounts of reverse engineering a SPARC opcode file rewrite DECstat
103. write where the first escapes the second As you can see the quote is an acute accent not a grave accent A newline immediately following an acute accent is taken as a literal character and does not count as the end of a statement The value of a character constant in a numeric expression is the machine s byte wide code for that character as assumes your character code is ASCII A means 65 B means 66 and so on Chapter 3 Syntax 25 3 6 2 Number Constants as distinguishes three kinds of numbers according to how they are stored in the target machine Integers are numbers that would fit into an int in the C language Bignums are integers but they are stored in more than 32 bits Flonums are floating point numbers described below 3 6 2 1 Integers A binary integer is Ob or OB followed by zero or more of the binary digits 01 An octal integer is 0 followed by zero or more of the octal digits 01234567 A decimal integer starts with a non zero digit followed by zero or more digits 0123456789 A hexadecimal integer is Ox or OX followed by one or more hexadecimal digits chosen from 0123456789abcdef ABCDEF Integers have the usual values To denote a negative integer use the prefix operator discussed under expressions see Section 6 2 3 Prefix Operators page 38 3 6 2 2 Bignums A bignum has the same syntax and semantics as an integer except that the n
104. 0 8 102 8 2 Register Names 0 71 8 102 8 3 Relocations 0000 ooo 71 8 102 9 Floating Point 0 ee eee eee 73 8 102 10 Alpha Assembler Directives 73 8 102 11 Opcodes cu esed cere ai 75 8 103 ARC Dependent Features 0 0 00 cece eens 77 8 103 12 Options iussu dene a Rep 77 8 103 13 Syntax 22i dac pea dd mea reed 77 8 103 13 1 Special Characters 77 8 103 13 2 Register Names 77 8 103 14 Floating Point 000 2 000 77 8 103 15 ARC Machine Directives Ty 8 103 16 Opcodes 0 eee esses 78 8 104 ARM Dependent Features ss esses elei 79 S 104 17 JODUOIBSu io rotas aa ida be 79 8104 19 A a eden tay eee nee ed eae 80 8 104 18 1 Special Characters 80 8 104 18 2 Register NamesS oo ooo o ooo o o 81 8 104 19 Floating Point 00 nataas 81 8 104 20 ARM Machine Directives 81 8 104 21 Opcodes 0 cece eee tee ee 82 8 105 CRIS Dependent Features 00 000 cece eee 83 8 105 22 Command line Options 83 8 105 23 Instruction expansion s esee esee 83 8 105 24 Syntax rises edie e E Yo Eod Ud 83 8 105 24 1 Special Characters 83 8 105 24 2 Symbols in position independent code E des 84 8 105 24 3 Register names ooo oooocoooo 85 8 105 24 4 Assembler Directives
105. 0 r11 r12 r13 ri4 ri5 The D10V also has predefined symbols for these control registers and status bits psw Processor Status Word bpsw Backup Processor Status Word pc Program Counter bpc Backup Program Counter rpt_c Repeat Count rpt_s Repeat Start address rpt_e Repeat End address mod_s Modulo Start address mod_e Modulo End address iba Instruction Break Address fO Flag 0 f1 Flag 1 c Carry flag 8 106 26 5 Addressing Modes as understands the following addressing modes for the D10V Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct Rn Register indirect 90 Using as ORn Register indirect with post increment Rn Register indirect with post decrement SP Register indirect with pre decrement disp Rn Register indirect with displacement addr PC relative address for branch or rep imm Immediate data the is optional and ignored 8 106 26 6 eWORD Modifier Any symbol followed by word will be replaced by the symbol s value shifted right by 2 This is used in situations such as loading a register with the address of a function or any other code fragment For example if you want to load a register with the location of the function main then jump to that function you could do it as follows ldi r2 main word jmp r2 8 106 27 Floating Point The D10V has no hardware floating point but the float and double directives gen erates IEEE flo
106. 10 arm620 arm7 arm7m arm7d arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710t arm720 arm720t arm740t arm710c arm7100 arm7500 arm7500fe arm7t arm7tdmi arm8 arm810 strongarm strongarml strongarm110 strongarm1100 strongarm1110 arm9 arm920 arm920t arm922t arm940t arm9tdmi arm9e arm946e r0 arm946e arm966e r0 arm966e arm10t armiOe arm1020 arm1020t arm1020e ep9312 ARM920 with Cirrus Maverick coprocessor i80200 Intel XScale processor iwmmxt Intel r XScale processor with Wireless MMX tm technology coprocessor and xscale The special name all may be used to allow the assembler to accept instructions valid for any ARM processor In addition to the basic instruction set the assembler can be told to ac cept various extension mnemonics that extend the processor using the co processor instruction space For example mcpu arm920 maverick is equiv alent to specifying mcpu ep9312 The following extensions are currently sup ported maverick iwmmxt and xscale march architecture extension This option specifies the target architecture The assembler will issue an er ror message if an attempt is made to assemble an instruction which will not execute on the target architecture The following architecture names are recog nized armvi armv2 armv2a armv2s armv3 armv3m armv4 armv4xm armv4t armv4txm armv5 armvbt armv5txm armvbte armv5texp iwmmxt and xscale If both mcpu and march are
107. 132 3 Floating Point The V850 family uses IEEE floating point numbers 8 132 4 V850 Machine Directives offset expression Moves the offset into the current section to the specified amount Section name type This is an extension to the standard section directive It sets the current section to be type and creates an alias for this section called name v850 Specifies that the assembled code should be marked as being targeted at the V850 processor This allows the linker to detect attempts to link such code with code assembled for other processors v850e Specifies that the assembled code should be marked as being targeted at the V850E processor This allows the linker to detect attempts to link such code with code assembled for other processors 188 v850e1 Using as Specifies that the assembled code should be marked as being targeted at the V850E1 processor This allows the linker to detect attempts to link such code with code assembled for other processors 8 132 5 Opcodes as implements all the standard V850 opcodes as also implements the following pseudo ops hid loQ hiQ hilo Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction For example mulhi hiO here there r5 r6 computes the difference between the address of labels here and there takes the upper 16 bits of this difference shift
108. 16 k command line option ARM 80 UL m 16 I option M68BOXO ooooccococccccccccc oo 126 ALL ra cs 160 O I7 O PENTE A ETTE ESET 155 A a wh exa E rr res 155 sull PP 155 MO cerise P ed RP RO edes 155 Using as A oi See aden Gas ERARE 155 ada rre ada 155 SMM e intel as 155 Spr E 155 STM WA LBA m 155 amia Rr 155 SUP nc MR MP 155 Anil JA shee beeen ebbe Re Eg be 155 SMA Leere oes ay Decide ee METER E E bee ee 155 SA og eagm Rei dvbe dd 155 mill SOs soba ee bende Eve DET ET TIC 155 Si ID doe hebr ide Kid 155 sInl1 55 2 exckeldr fewer arse gue n add 155 SMU CO 22 ses nl A Eerecerume ox erre EY 155 emTl TU veni punere RA REUS ITE EI 155 mi Tdi 155 Mi src da il iaa 155 A 155 O 155 a arden Rede yet ae ad 155 em32r option M32R ess sois REIR taaan 123 m32rx option M32RX susssss 123 m68000 and related options 127 a AAA A as Bates E 133 MOTA CA aia 133 m6SHES12 5 ox PREPARES RUPEE 133 A eeAePRRERe4ae eA 153 mall extensions s esses eere 153 mapcs command line option ARM 80 mapcs float command line option ARM 80 mapcs reentrant command line option ARM O pactus bade e deest dob 80 marc 5 6 7 8 command line option ARC 77 march command line option ARM 79 matpcs command line option ARM 80 SMCS os RGA ows van ened ate he ied See E 153 mcpu command line option Alpha 70 mepu option CD
109. 183 operands in expressions sese eees 3T operator precedence sseeeeeee ees 38 operators in expressions esee eese 37 operators permitted arguments 38 optimization DIOV cocino da 60 rr 5 optimization D30V rese rr pi 5 optimizatiolis ideneokrcetu efe eee eas 193 option directive ARC co cicureccrieresiicere 78 option directive TIC5AX 174 option SUMMA Y e idad a eee 1 options for Alpha oooooocccccccccccco oo 70 options for AMD29K none 68 options for ARC none 0000 77 options for ARM none 00005 79 Options for 1386 tr ia orale 107 options for MSP430 none 151 optionsdor PDP 1 2222 ao hie eee a eh ae 153 options for PowerPC 0000 08 158 options for SPARC 222220000 166 options for V850 none 205 184 options for VAX VMS 05 180 options for x86 64 o o ooooooccooooccoooo ooo 107 options all versions of assembler 15 options command line o ooooooo o oooo 12 options CRIS 00000 add Rx odd Ps 83 options Di Visio Puto dea 87 options D30V ec nacsccees ba dr 91 options H8 300 none 0 000000 95 options H8 500 none 00 000 98 Options 1900 cocer arica dee bie feeds 118 options IP2K e crims aii pit Peed oy Seed now ee 122 options MIR secte REPE aces ote 12
110. 3 options M680x0 2c eee eee bn 126 options M68HC11 008 133 options MMIX i ieserciex a 144 options Plata taria 157 options SE ob dore eases Bands ala Speed 160 options SHOL i taria ea ioe is 163 options TIC54X eco Leyce RE reri 168 options Z8000 cede eere ee ee 178 org directlye cier 54 other attribute of a out symbol 36 oubputhile air mi e ES ene t iere 13 Index P p2align directive erre E ees 55 p2align directive codon erem 55 p2alignw directive ce ceecei eee Ce iieri ik 55 padding the location counter 41 padding the location counter given a power of two See ccesbenttexpeeemeireberee e RP TOI 55 padding the location counter given number of A e Re a a OEE 42 page in stings 4s rreke Rer be PIX 45 paper size for listingS oo oooo 56 paths for include 2 ev es 16 patterns writing in memory 47 PDP 11 comments Re 155 PDP 11 floating point register syntax 155 PDP 11 general purpose register syntax 155 PDP 11 instruction naming 156 PDP 11 support rere 153 PDP T1Ssyntax igit ee eda edebat 155 PIC code generation for ARM 80 PJ endiannessc sc nnsenept me tse Fd iP ERIS T PJ Options ii AS 157 PJ SUPpoOrtb anat saciar 157 plus permitted arguments 38 popsection directive 0oooooooooooo oo 55 Position independent
111. 4 4 XX condition NX negative of condition XX jbsr jbra joxx These are the simplest jump pseudo operations they always map to one partic ular machine instruction depending on the displacement to the branch target Here jbXX stands for an entire family of pseudo operations where XX is a conditional branch or condition code test The full list of pseudo ops in this family is jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi For the cases of non PC relative displacements and long displacements as issues a longer code fragment in terms of NX the opposite condition to XX For example for the non PC relative case jbXX foo gives bNXs oof jmp foo oof 138 Using as 8 119 Motorola M88K Dependent Features 8 119 1 M88K Machine Directives The M88K version of the assembler supports the following machine directives align This directive aligns the section program counter on the next 4 byte boundary dfloat expr This assembles a double precision 64 bit floating point constant ffloat expr This assembles a single precision 32 bit floating point constant half expr This directive assembles a half word 16 bit constant word expr This assembles a word 32 bit constant String str This directive behaves like the standard ascii directive for copying str into the object file The string is not terminated wit
112. 51 Assemble 68851 MMU instructions This is the default for the 68020 68030 and 68060 The 68040 accepts a somewhat different set of MMU instructions m68851 and m68040 should not be used together mno 68851 Do not assemble 68851 MMU instructions This is the default for the 68000 68010 and the CPU32 The 68040 accepts a somewhat different set of MMU instructions This syntax for the Motorola 680x0 was developed at MIT Chapter 8 Machine Dependent Features 129 The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler Intervening periods are ignored for example mov1 is equivalent to mov 1 In the following table apc stands for any of the address registers a0 through a7 the program counter Apc the zero address relative to the program counter zpc a suppressed address register 4za0 through za7 or it may be omitted entirely The use of size means one of w or 1 and it may be omitted along with the leading colon unless a scale is also specified The use of scale means one of 1 2 4 or 8 and it may always be omitted along with the leading colon The following addressing modes are understood Immediate number Data Register 0 through d7 Address Register had through a7 hal is also known as sp i e the Stack Pointer a6 is also know
113. 6 turning preprocessing on and off 21 type directive COFF version 64 type directive ELF version 64 type of a Symbol i cis ta 35 U nalong directive SH 2o oee rapera 161 uaword directive SH oo ooooooooooo 161 ubyte directive TIC54X ooooooooommmoo 172 uchar directive TICBAX 172 uhalf directive TICBAX 173 uint directive TIC54X 173 uleb128 directive oooooooocoooom ooo 64 ulong directive TIC54X ooooooooommoo o 173 undefined section sissies aape a 29 union directive TIC54X o o o o oooo 175 porro vn 179 use directive AMD 29K ssss 69 usect directive TICBAX 176 ushort directive TIC54X 173 uword directive TIC54X 173 228 y V850 command line options 184 V850 floating point IEEE oooocoo ooooo 187 V850 line comment character 185 V850 machine directiveS o0oooocooooo 187 V850 opcodes cease ds ichownl deehaeheee 188 V850 options none 0 0 00 0 08 184 V850 register names 0000 00006 185 V S50 SUPPO sad od iode et ia 184 val directivo cade tener ie drid 65 value attribute COFF o o oooooccoooccoomo 65 value of a symbol so 22er rr ben 35 var directive TIC5AX 000 176 VAX bitfields not supported
114. 6 documents use Intel syntax Notable differences between the two syntaxes are e AT amp T immediate operands are preceded by Intel immediate operands are undelim ited Intel push 4 is AT amp T push1 4 AT amp T register operands are preceded by 4 Intel register operands are undelimited AT amp T absolute as opposed to PC relative jump call operands are prefixed by they are undelimited in Intel syntax e AT amp T and Intel syntax use the opposite order for source and destination operands Intel add eax 4 is addl 4 eax The source dest convention is maintained for compatibility with previous Unix assemblers Note that instructions with more than one source operand such as the enter instruction do not have reversed order Section 8 112 23 i386 Bugs page 113 e In AT amp T syntax the size of memory operands is determined from the last character of the instruction mnemonic Mnemonic suffixes of b w 1 and q specify byte 8 bit word 16 bit long 32 bit and quadruple word 64 bit memory references Intel syn tax accomplishes this by prefixing memory operands not the instruction mnemonics with byte ptr word ptr dword ptr and qword ptr Thus Intel mov al byte ptr foo is movb foo fal in AT amp T syntax e Immediate form long jumps and calls are lcall ljmp section offset in AT amp T syntax the Intel syntax is
115. 67 and underscores For the AMD 29K family is also allowed in the body of a symbol name though not at its beginning Case of letters is significant foo is a different symbol name than Foo Each symbol has exactly one name Each name in an assembly language program refers to exactly one symbol You may use that symbol name any number of times in a program Local Symbol Names Local symbols help compilers and programmers use names temporarily They create symbols which are guaranteed to be unique over the entire scope of the input source code and which can be referred to by a simple notation To define a local symbol write a label of the form N where N represents any positive integer To refer to the most recent previous definition of that symbol write Nb using the same number as when you defined the label To refer to the next definition of a local label write Nf The b stands for backwards and the f stands for forwards 34 Using as There is no restriction on how you can use these labels and you can reuse them too So that it is possible to repeatedly define the same local label using the same number N although you can only refer to the most recently defined local label of that number for a backwards reference or the next definition of a specific local label for a forward reference It is also worth noting that the first 10 local labels 0 9 are implemente
116. 8 126 4 SH Machine Directives uaword ualong as will issue a warning when a misaligned word or long directive is used You may use uaword or ualong to indicate that the value is intentionally misaligned 8 126 5 Opcodes For detailed information on the SH machine instruction set see SH Microcomputer User s Manual Renesas or SH 4 32 bit CPU Core Architecture SuperH and SuperH SH 64 Bit RISC Series SuperH 162 Using as as implements all the standard SH opcodes No additional pseudo instructions are needed on this family Note however that because as supports a simpler form of PC relative addressing you may simply write for example mov l bar r0 where other assemblers might require an explicit displacement to bar from the program counter mov 1 disp PC Chapter 8 Machine Dependent Features 163 8 127 SuperH SH64 Dependent Features 8 127 1 Options isa shmedia isa shcompact Specify the default instruction set SHmedia specifies the 32 bit opcodes and SHcompact specifies the 16 bit opcodes compatible with previous SH families The default depends on the ABI selected the default for the 64 bit ABI is SHmedia and the default for the 32 bit ABI is SHcompact If neither the ABI nor the ISA is specified the default is 32 bit SHcompact Note that the mode pseudo op is not permitted if the ISA is not specified on the command line abi 32 abi 64 Specify the default ABI If the ISA is specified and the ABI
117. 80x0 ssssssue 131 pseudo opcodes M68HC11 137 225 pseudo ops for branch VAX 182 pseudo ops ORIS since erdt RA 85 pseudo ops machine independent 41 pseudo ops MMIX useeessss 147 psize directive i oves aos 56 pstring directive TIC54X 175 psw register V850 ws coded ober Rep bs 187 purgem directive 2 5 leesse ree 56 purpose of GNU assembler 12 pushsection directive oooooooooo 56 Q quad directive esseri rede ble Free 5T quad directive 1386 o ooo ooo o 112 quad directive x86 64 oooooooooooooo 112 R real mode code i386 o oo ooooooooooo 112 ref directive TICBAX 178 register directive SPARC 167 register names Alpha 000 71 register names AMD 29K 68 register names ARC 00 eee eee 77 register names ARM 2200005 81 register names CRIS 2 05 85 register names H8 300 0 000 95 register names MMIX 146 register names MSP 430 151 register names V850 2008 185 register names VAX eee ee eeee 183 register names Xtensa 2 00 193 register operands 1386 0 oooo ooooo o oo 107 register operands x86 64 04 107
118. 9 104 Using as 8 111 ESA 390 Dependent Features 8 111 7 Notes The ESA 390 as port is currently intended to be a back end for the GNU CC compiler It is not HLASM compatible although it does support a subset of some of the HLASM direc tives The only supported binary file format is ELF none of the usual MVS VM OE USS object file formats such as ESD or XSD are supported When used with the GNU CC compiler the ESA 390 as will produce correct fully relo cated functional binaries and has been used to compile and execute large projects How ever many aspects should still be considered experimental these include shared library support dynamically loadable objects and any relocation other than the 31 bit relocation 8 111 8 Options as has no machine dependent command line options for the ESA 390 8 111 9 Syntax The opcode operand syntax follows the ESA 390 Principles of Operation man ual assembler directives and general syntax are loosely based on the prevailing AT T SVR4 ELF Solaris style notation HLASM style directives are not supported for the most part with the exception of those described herein A leading dot in front of directives is optional and the case of directives is ignored thus for example using and USING have the same effect A colon may immediately follow a label definition This is simply for compatibility with how most assembly language programmers write code is the line comment character
119. DDMI ADDI sequence will be used Finally if the immediate is outside of this range and a free register is available an L32R ADD sequence will be used with a literal allocated from the literal pool For example addi ab a6 O addi ab a6 512 addi ab a6 513 addi a5 a6 50000 is assembled into the following literal L1 50000 mov n ab a6 addmi a5 a6 0x200 addmi a5 a6 0x200 addi ab ab 1 196 Using as 132r ab L1 add ab a6 ab 8 133 10 Directives The Xtensa assember supports a region based directive syntax begin directive options nnd directive All the Xtensa specific directives that apply to a region of code use this syntax The directive applies to code between the begin and the end The state of the option after the end reverts to what it was before the begin A nested begin end region can further change the state of the directive without having to be aware of its outer state For example consider begin no density L add a0 al a2 begin density M add a0 al a2 end density N add a0 ai a2 end no density The generic ADD opcodes at L and N in the outer no density region both result in ADD machine instructions but the assembler selects an ADD N instruction for the generic ADD at M in the inner density region The advantage of this style is that it works well inside macros which can preserve the context of their callers When command line options and assembler directives are us
120. DENT WORKS A compilation of the Document or its derivatives with other separate and independent documents or works in or on a volume of a storage or distribution medium does not as a whole count as a Modified Version of the Document provided no compilation copyright is claimed for the compilation Such a compilation is called an aggregate and this License does not apply to the other self contained works thus compiled with the Document on account of their being thus compiled if they are not themselves derivative works of the Document If the Cover Text requirement of section 3 is applicable to these copies of the Document then if the Document is less than one quarter of the entire aggregate the Document s Cover Texts may be placed on covers that surround only the Document within the aggregate Otherwise they must appear on covers around the whole aggregate 8 TRANSLATION Translation is considered a kind of modification so you may distribute translations of the Document under the terms of section 4 Replacing Invariant Sections with translations requires special permission from their copyright holders but you may include translations of some or all Invariant Sections in addition to the original versions of these Invariant Sections You may include a translation of this License provided that you also include the original English version of this License In case of a disagreement 212 Using as 10 between the translation and th
121. EEE 32 bit floating point numbers 8 122 117 MSP 430 Machine Directives file This directive is ignored it is accepted for compatibility with other MSP 430 assemblers Warning in other versions of the GNU assembler file is used for the directive called app file in the MSP 430 support line This directive is ignored it is accepted for compatibility with other MSP 430 assemblers arch Currently this directive is ignored it is accepted for compatibility with other MSP 430 assemblers 8 122 18 Opcodes as implements all the standard MSP 430 opcodes No additional pseudo instructions are needed on this family For information on the 430 machine instruction set see MSP430 User s Manual docu ment slau049b Texas Instrument Inc Chapter 8 Machine Dependent Features 153 8 123 PDP 11 Dependent Features 8 123 19 Options The PDP 11 version of as has a rich set of machine dependent options 8 123 19 1 Code Generation Options mpic mno pic Generate position independent or position dependent code The default is to generate position independent code 8 123 19 2 Instruction Set Extension Options These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP 11 CPU the KA11 Most options come in two variants a nextension that enables extension and a mno extension that disables extension The default is to enable all extensions mall mall exte
122. ENPIAIOREP URERE Hs E 25 binary constants TIC54X 168 binary files including ooooooo 49 binary integers cicio eor pp e ede 25 bitfields not supported on VAX 184 PLOCK cg Rus dd pe ebat Ha ERU Regg 179 block directive AMD 29K 69 branch improvement M680x0 131 branch improvement M68HC11 137 branch improvement VAX 182 branch instructions relaxation 194 branch recording 1960 00 118 branch statistics table 1960 118 branch target alignment 0 193 break directive TIC54X 0 174 BSD Syntax urnas a 155 bss directive 1960 ooooooocoooomm o 119 bss directive M88K o ooccoooocoooom o o 138 bss directive TICBAX oo kc cca ems 172 DSS SECHON ii rara 28 30 DUE Criteria iie mie iere Re ERU PNE ERE 201 bug YeDOLis 22seeste RES RHENO eee d 201 bugs in assembler ooo ooooooooo 201 builtin math functions TIC54X 170 builtin subsym functions TIC54X 176 bus lock prefixes i386 ooooooooo ooo 110 Dalias erede de 179 byte directives ices coss eee eret ea 42 byte directive TIC5AX oooooommmmmmmo o 172 C c mode directive TIC54X 172 CBAXDSP DIR environment variable TIC54X PPS 168 call instructions 1386 o ooooooo ooooo o 108 call i
123. ES 100 supporting files including 50 suppressing warnings cessere 20 oru Rm 179 symbol attributes sarn eek pere er eee 35 symbol attributes A OUt o ooooooooooooo o 35 symbol attributes COFF 36 symbol attributes SOM Lluuuuueue 36 symbol descriptor COFF Lussuue 44 symbol modifiers 22e er PR ndn 135 symbol Names iria eau elie ese aes 33 symbol names in 88 92 98 160 163 symbol names local sssleeeeses 33 symbol names temporary 0 33 symbol storage class COFF 57 Symbol YD isos ori 35 symbol type COFF umi sedas peas wens 9x 64 symbol type ELF ooooooooomo o 64 Symbol value euet e a 35 symbol value setting oooo o oo o o o 59 symbol values assigning ooooooooocoooo 33 symbol versioning ooooooooooooooomoo 62 symbol common mm eee perve 43 symbol making visible to linker 47 symbolic debuggers information for 61 A tara e EEEa X ertet rs 33 Symbols in position independent code CRIS 84 symbols with uppercase VAX VMS 180 symbols assigning values to 0oooooooo 46 symbols local common 0000005 51 symver directive ooooooooocoormmoooo 62 syntax compatibility 1386 107 syntax compatibility x86 64 107 sy
124. H8 300 20 95 addressing modes H8 500 20 98 addressing modes M680x0 Luuue 129 addressing modes M68HC11 134 addressing modes SH 0 0 161 addressing modes SH64 0 164 addressing modes Z8000 0 178 ADR reg label pseudo op ARM 82 ADRL reg lt label gt pseudo op ARM 82 advancing location counter 54 align directive esi rrr RREDPT REY A1 Using as align directive ARM oooomcccococm 81 align directive M88K ooo oooooo ooo 138 align directive SPARC oooommccocommo 167 align directive TIC54X 000 171 alignment of branch targets 193 alignment of ENTRY instructions 193 alignment of LOOP instructions 193 Alpha floating point IEEE 73 Alpha line comment character ral Alpha line separator 0000 000 0 71 Alpha note viniera il 70 Alpha OptJOn8 1m6 dere IRR REV ETE RES 70 Alpha r gisters cesse RP RET VY Ped 71 Alpha relocati0NS 0ooooooccccccccccooo oo rail Alpha Support sei pd e ERR Reed 70 Alpha yate oli sedo a a aid 70 Alpha only directives 0 0 00 eee eee 73 altered difference tables 65 alternate syntax for the 680x0 129 AMD 29K floating point IEEE 68 AMD 29K i
125. If BR represents a conditional branch instruction the following represents the code generated by the assembler when b is specified call increment routine word 0 pre counter Label BR call increment routine word 0 post counter The counter following a branch records the number of times that branch was not taken the differenc between the two counters is the number of times the branch was taken A table of every such Label is also generated so that the external postprocessor gbr960 supplied by Intel can locate all the counters This table is always labeled BRANCH TABLE this is a local symbol to permit collecting statistics for many separate object files The table is word aligned and begins with a two word header The first word initialized to 0 is used in maintaining linked lists of branch tables The second word is a count of the number of entries in the table which follow immediately each is a word pointing to one of the labels illustrated above Chapter 8 Machine Dependent Features 119 no relax 8 114 31 NEXT COUNT N BRLAB 1 o BRLAB N _ BRANCH_TABLE__ layout The first word of the header is used to locate multiple branch tables since each object file may contain one Normally the links are maintained with a call to an initialization routine placed at the beginning of each function in the file The GNU C compiler generates these calls automatically when you give it
126. RY instruction however there are two cases where this is not true 1 The size of the stack frame is too big to fit in the immediate field of the ENTRY instruc tion 2 The frame pointer is different than the stack pointer as with functions that call alloca 200 Using as Chapter 9 Reporting Bugs 201 9 Reporting Bugs Your bug reports play an essential role in making as reliable Reporting a bug may help you by bringing a solution to your problem or it may not But in any case the principal function of a bug report is to help the entire community by making the next version of as work better Bug reports are your contribution to the maintenance of as In order for a bug report to serve its purpose you must include the information that enables us to fix the bug 9 1 Have You Found a Bug If you are not sure whether you have found a bug here are some guidelines e If the assembler gets a fatal signal for any input whatever that is a as bug Reliable assemblers never crash e If as produces an error message for valid input that is a bug e If as does not produce an error message for invalid input that is a bug However you should note that your idea of invalid input might be our idea of an extension or support for traditional practice e If you are an experienced user of assemblers your suggestions for improvement of as are welcome in any case 9 2 How to Report Bugs A number of companies and individua
127. Relax ation page 194 The default is relax and this default should almost always be used If relaxation is disabled with no relax instruction operands that are out of range will cause errors Note In the current implementation these options also control whether assembler optimizations are performed making these options equivalent to generics and no generics generics no generics Enable or disable all assembler transformations of Xtensa instructions including both relaxation and optimization The default is generics no generics should only be used in the rare cases when the instructions must be exactly as specified in the assembly source As with no relax using no generics causes out of range instruction operands to be errors text section literals no text section literals Control the treatment of literal pools The default is no text section literals which places literals in a separate section in the output file This allows the literal pool to be placed in a data RAM ROM and it also allows the linker to combine literal pools from separate object files to remove redundant literals and improve code size With text section literals the literals are interspersed in the text section in order to keep them as close as possible to their references This may be necessary for large assembly files target align no target align Enable or disab
128. SCII without markup Texinfo input format LaTeX input format SGML or XML using a publicly available DTD and standard conforming simple HTML designed for human modifica tion Opaque formats include PostScript PDF proprietary formats that can be read and edited only by proprietary word processors SGML or XML for which the DTD and or processing tools are not generally available and the machine generated HTML produced by some word processors for output purposes only The Title Page means for a printed book the title page itself plus such following pages as are needed to hold legibly the material this License requires to appear in the title page For works in formats which do not have any title page as such Title Page means the text near the most prominent appearance of the work s title preceding the beginning of the body of the text VERBATIM COPYING You may copy and distribute the Document in any medium either commercially or noncommercially provided that this License the copyright notices and the license notice saying this License applies to the Document are reproduced in all copies and that you add no other conditions whatsoever to those of this License You may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute However you may accept compensation in exchange for copies If you distribute a large enough number of copies you must also follow the conditio
129. U iiic 05 aii 168 mcpu command line option ARM 79 SCSI 2 id dati A AE RUP NUR 153 mdebug command line option Alpha 70 me option stderr redirect o o 168 m 2 153 merrors to file option stderr redirect 168 mf option far mode 0 0000 168 O A hi budad pieee PP 154 mfar mode option far mode 168 SMS cidad dire dba die 153 3mtp l11 ia ida 153 IPP praia ide ad iris 153 AMP da ta 153 mfpu command line option ARM 79 mip2022 option IP2K or ubl tea 122 mip2022ext option P2022 122 mui Hr 154 MKATI PHP 154 mkl ius vu ace hits dere iE eR ER ges 154 Dui cllc 154 Index 2 ETE 154 SMA GU eos pa RE ed edna ab add 154 SMU GF P 154 mkdir te 154 A Wand xenEueRI Dueb ads 154 mkd lI kE mesener dh e trei hen ulis 154 smkdllq i wos tide eee ee n Ead pe 154 MK ios ob O di dkeweeeesdss 154 Mk ddr ee Een 153 mlimited el8 comercio cree teens cae beet 154 SSM LONG ieee ee T 133 mlong double ovine dade ser re Paina 133 AM MUP G24 4 25 e E deep odeur tes De dd adco 154 AMMICTOCOG omar pede daa hod ave does 154 MUDO Crier wees eae arate RP PP don ante 154 MADS sae NA A e ree 154 Sud ERIT 153 MOCOS ipsun REGERE I PERLE 153 smmno eis edam bea ua kso RE Ed b RES 153 Ino extensiohg 2 22 mc asm mb a 153 MNG 28435 iex adiectae etse Pare mn Danaea 153 mnostp Tl aues elas dew tee alee
130. Unsigned large immediate with logical operations Logical operations or andnot or xor also result in expansions The pseudo instruction or large_imm rx rn results in orh large_imm h rx 4r31 or large_imm 1 r31 rn Similarly for the others except for and which expands to andnot 1 large_imm h rx r31 andnot 1 large imm 01 r31 7 rn 118 Using as 8 114 Intel 80960 Dependent Features 8 114 30 1960 Command line Options ACA ACA_A ACB ACC AKA AKB AKC AMC Select the 80960 architecture Instructions or features not supported by the selected architecture cause fatal errors ACA is equivalent to ACA_A AKC is equivalent to AMC Synonyms are provided for compatibility with other tools If you do not specify any of these options as generates code for any instruction or feature that is supported by some version of the 960 even if this means mix ing architectures In principle as attempts to deduce the minimal sufficient processor type if none is specified depending on the object code format the processor type may be recorded in the object file If it is critical that the as output match a specific architecture specify that architecture explicitly Add code to collect information about conditional branches taken for later optimization using branch prediction bits The conditional branch instructions have branch prediction bits in the CA CB and CC architectures
131. Using as The GNU Assembler Version 2 14 90 0 7 The Free Software Foundation Inc thanks The Nice Computer Company of Australia for loaning Dean Elsner to write the first Vax version of as for Project GNU The proprietors management and staff of TNCCA thank FSF for distracting the boss while they got some work done Dean Elsner Jay Fenlason z friends Using as Edited by Cygnus Support Copyright c 1991 92 93 94 95 96 97 98 99 2000 2001 2002 Free Software Foundation Inc Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 1 or any later version published by the Free Software Foundation with no Invariant Sections with no Front Cover Texts and with no Back Cover Texts A copy of the license is included in the section entitled GNU Free Documentation License Chapter 1 Overview 1 1 Overview This manual is a user guide to the GNU assembler as Here is a brief summary of how to invoke as For details see Chapter 2 Command Line Options page 15 as a edhlns file D defsym sym val gstabs gstabs gdwarf2 help I dir LJ CK LL listing lhs width NUM listing Ihs width2 NUM listing rhs width NUM listing cont lines NUM keep locals o objfile R statistics v version version W warn fatal warnings w Ex Z target help target options I fil
132. VAX 0ooooccccccccccoooo 181 hi pseudo op V850 0 00 eee eee eee 188 hi0 pseudo op V850 000 e eee eee 188 hidden directives iss oeisse ee ents hued 48 hilo pseudo op V850 2 esse s 188 HPPA directives not supported 101 HPPA floating point IEEE seus 100 HPPA Syntax an sve ei eit e apo 100 HPPA only directives ooooooooccooo 101 hword directive cscs sa seme ple ket eed gs 48 I 1910 SU pDOEU essi cLethER tee Re bd RR pe 104 1386 16 bit code ee eee eres 112 1386 arch directive ooooooooomoooo 113 1386 att syntax pseudo op 04 107 1386 conversion instructions suse 108 1386 floating POiMb oooooccccccccoooooo 111 i386 immediate operands 107 1386 instruction naming 000 108 1386 instruction prefixes 04 109 1386 intel syntax pseudo op 04 107 1386 jump optimization 04 111 i386 jump call return 0 04 107 i386 jump call operamdS 0ooooooocoomo 107 1386 memory references ooooooooomooo 110 1386 mul imul instructions 114 1980 OPTIONS Lec ween IR Lr RS 107 1386 register operands 005 107 1986 registets 2c reso iia Er 108 Index 1980 SOCLIONS ecos date asite rp Gegen aie des 108 1386 size SUMIXES 604 5 5650 beet daha eens Soe ee 107 1386 source destination op
133. a b option For further details see the documentation of gbr960 Normally Compare and Branch instructions with targets that require displace ments greater than 13 bits or that have external targets are replaced with the corresponding compare or chkbit and branch instructions You can use the no relax option to specify that as should generate errors instead if the target displacement is larger than 13 bits This option does not affect the Compare and Jump instructions the code emit ted for them is always adjusted when necessary depending on displacement size regardless of whether you use no relax Floating Point as generates IEEE floating point numbers for the directives float double extended and single 8 114 32 1960 Machine Directives bss symbol length align Reserve length bytes in the bss section for a local symbol aligned to the power of two specified by align length and align must be positive absolute expressions This directive differs from 1comm only in that it permits you to specify an alignment See Section 7 52 1comm page 51 extended flonums extended expects zero or more flonums separated by commas for each flonum extended emits an IEEE extended format 80 bit floating point number leafproc call lab bal lab You can use the leafproc directive in conjunction with the optimized callj instruction to enable faster ca
134. a file Other than that the exact order of register allocation and elimination is undefined For example the order is undefined when more than one file with such directives are linked together With the options x and linker allocated gregs GREG directives for two operand cases like the one mentioned above can be omitted Sufficient global registers will then be allocated by the linker The BYTE directive takes a series of operands separated by a comma If an operand is a string see Section 3 6 1 1 Strings page 23 each character of that string is emitted as a byte Other operands must be constant expres sions without forward references in the range 0 255 If you need operands having expressions with forward references use byte see Section 7 7 Byte page 42 An operand can be omitted defaulting to a zero value Chapter 8 Machine Dependent Features 149 The directives WYDE TETRA and OCTA emit constants of two four and eight bytes size respectively Before anything else happens for the directive the current location is aligned to the respective constant size boundary If a label is defined at the beginning of the line its value will be that after the alignment A single operand can be omitted defaulting to a zero value emitted for the directive Operands can be expressed as strings see Section 3 6 1 1 Strings page 23 in which case each character in the string is emitted as
135. a mix between the effect of the GOT and the PLT suffix the difference to GOT is that there will be a procedure linkage table entry created and that the symbol is assumed to be a function entry and will be resolved by the run time resolver as with PLT The relocation is R_CRIS_32_GOTPLT Example jsr r0 fnname GOTPLT GOTPLT16 A variant of GOTPLT giving a 16 bit value Its relocation name is R_CRIS_16_GOTPLT Example jsr r0 fnname GOTPLT16 GOTOFF This suffix must only be attached to a local symbol but may be used in an expression adding an offset The value is the address of the symbol relative to the start of the global offset table The relocation name is R_CRIS_32_GOTREL Example move d r0 localsym GOTOFF r3 8 105 24 3 Register names A character may always prefix a general or special register name in an instruction operand but is mandatory when the option no underscore is specified or when the syntax register_prefix directive is in effect see crisnous page 85 Register names are case insensitive 8 105 24 4 Assembler Directives There are a few CRIS specific pseudo directives in addition to the generic ones See Chapter 7 Pseudo Ops page 41 Constants emitted by pseudo directives are in little endian order for CRIS There is no support for floating point specific directives for CRIS dword EXPRESSIONS The dword directive is a synonym for int e
136. a separate constant of the size indicated by the directive PREFIX The PREFIX directive sets a symbol name prefix to be prepended to all sym bols except local symbols see Section 8 121 12 2 MMIX Symbols page 146 that are not prefixed with until the next PREFIX directive Such prefixes accumulate For example PREFIX a PREFIX b c IS 0 defines a symbol abc with the value 0 BSPEC ESPEC A pair of BSPEC and ESPEC directives delimit a section of special contents without specified semantics Example BSPEC 42 TETRA 1 2 3 ESPEC The single operand to BSPEC must be number in the range 0 255 The BSPEC number 80 is used by the GNU binutils implementation 8 121 13 Differences to mmixal The binutils as and 1d combination has a few differences in function compared to mmixal see mmixsite page 145 The replacement of a symbol with a GREG allocated register see GREG base page 148 is not handled the exactly same way in as as in mmixal This is apparent in the mmixal example file inout mms where different registers with different offsets eventually yielding the same address are used in the first instruction This type of difference should however not affect the function of any program unless it has specific assumptions about the allocated register number Line numbers in the mmo object format are currently not supported Expression operator precedence is not that
137. aahb pdf Chapter 8 Machine Dependent Features 77 8 103 ARC Dependent Features 8 103 12 Options marc 5161718 This option selects the core processor variant Using marc is the same as marc_CORE_DEFAULT No value for ARC_CORE_DEFAULT which is also the default arcb arc6 arc arc8 Base instruction set Jump and link jl instruction No requirement of an instruction between setting flags and conditional jump For example mov f r0 rl1 beq foo Break brk and sleep sleep instructions Software interrupt swi instruction Note the option directive can to be used to select a core variant from within assembly code EB This option specifies that the output generated by the assembler should be marked as being encoded for a big endian processor EL This option specifies that the output generated by the assembler should be marked as being encoded for a little endian processor this is the default 8 103 13 Syntax 8 103 13 1 Special Characters TODO 8 103 13 2 Register Names TODO 8 103 14 Floating Point The ARC core does not currently have hardware floating point support Software floating point support is provided by GCC and uses IEEE floating point numbers 78 Using as 8 103 15 ARC Machine Directives The ARC version of as supports the following additional machine directives 2byte expressions TODO 3byte expressions TODOS Abyte expressions TODO
138. abel prev to the current location and updates the current location to eight bytes forward prev LOC 0 8 When a LOC has a constant as its operand a symbol __ MMIX start text or __ MMIX start data is defined depending on the address as mentioned above Each such symbol is interpreted as special by the linker locating the section at that address Note that if multiple files are linked the first object file with that section will be mapped to that address not necessarily the file with the LOC definition LOCAL Example LOCAL external_symbol LOCAL 42 local asymbol This directive operation generates a link time assertion that the operand does not correspond to a global register The operand is an expression that at link time resolves to a register symbol or a number A number is treated as the register having that number There is one restriction on the use of this directive the pseudo directive must be placed in a section with contents code or data IS The IS directive asymbol IS an_expression sets the symbol asymbol to an_expression A symbol may not be set more than once using this directive Local labels may be set using this directive for example 5H IS 4 148 GREG BYTE WYDE TETRA OCTA Using as This directive reserves a global register gives it an initial value and optionally gives it a symbolic name Some examples areg GREG breg GREG data_value GREG data_buffer greg creg another d
139. addressing modes 000 164 SH64 ISA options sseeseeesseeee 163 SH64 line comment character 163 SH64 line separator esses 163 SH64 machine directiveS o 00ooooo oooo 164 SH64 opcode summary 165 SHOA Options ocres rad 163 SHGA registers i ech cde a 163 SHOA support 24 5 o Coby eae ERepUPHERa TA 163 short dir ctive els ao sur RR AR gs 59 short directive ARC 0 oooccccoooooooco o 78 short directive TIC54X 173 Using as SIMD 1386 cuentas nrbe se pease us Bone nak 112 SIMD x86 064 cereis eres di pale RE das 112 single character constant oooooooooooo 24 single directive is iege teh bb Rs 60 single directive 1386 esee 111 single directive x86 64 oo ooooooooo T sixteen bit integers ooooooooooooooo 48 sixteen byte integer oooooooooommmooo 54 size directive COFF version 60 size directive ELF version 60 size modifiers D1OV 2 08 87 size modifiers D30V oooooooocooooo 91 size modifiers M680x0 0 128 size prefixes 1386 0 0 eee renee 109 size suffixes H8 300 0 00 0005 97 sizes operands i886 0 cece eee eee 107 sizes operands x86 64 0 000 000 107 skip directive ko osse E ERR ERROR GI e 60 skip directive M680x0 0
140. also have auxiliary attributes If you use a symbol without defining it as assumes zero for all these attributes and probably won t warn you This makes the symbol an externally defined symbol which is generally what you would want 5 5 1 Value The value of a symbol is usually 32 bits For a symbol which labels a location in the text data bss or absolute sections the value is the number of addresses from the start of that section to the label Naturally for text data and bss sections the value of a symbol changes as 1d changes section base addresses during linking Absolute symbols values do not change during linking that is why they are called absolute The value of an undefined symbol is treated in a special way If it is 0 then the symbol is not defined in this assembler source file and 1d tries to determine its value from other files linked into the same program You make this kind of symbol simply by mentioning a symbol name without defining it A non zero value represents a comm common declaration The value is how much common storage to reserve in bytes addresses The symbol refers to the first address of the allocated storage 5 5 2 Type The type attribute of a symbol contains relocation section information any flag settings indicating that a symbol is external and optionally other information for linkers and debuggers The exact format depends on the object code output format in use 5 5 3 Symbol Attributes
141. am begins running It is used to hold uninitialized variables or common storage The length of each partial program s bss section is important but because it starts out containing zeroed bytes there is no need to store explicit zero bytes in the object file The bss section was invented to eliminate those explicit zeros from object files Chapter 4 Sections and Relocation 29 absolute section Address 0 of this section is always relocated to runtime address 0 This is useful if you want to refer to an address that 1d must not change when relocating In this sense we speak of absolute addresses being unrelocatable they do not change during relocation undefined section This section is a catch all for address references to objects not in the preceding sections An idealized example of three relocatable sections follows The example uses the tradi tional section names text and data Memory addresses are on the horizontal axis Partial program 1 text data bss ttttt dddd 00 Partial program 2 text data bss TIT DDDD 000 linked program text data bss TTT ttttt dddd DDDD 00000 addresses Wire 4 3 Assembler Internal Sections These sections are meant only for the internal use of as They have no meaning at run time You do not really need to know about these sections for most purposes but they can be mentioned in as warning messages so it might be hel
142. amily Assembler Specification Normal as macros should still work Additional built in macros are llo exp Extracts least significant word from 32 bit expression exp lhi exp Extracts most significant word from 32 bit expression exp hlo exp Extracts 3rd word from 64 bit expression exp hhi exp Extracts 4rd word from 64 bit expression exp They normally being used as an immediate source operand mov 1lo 1 r10 mov 1 r10 mov 1hi 1 r10 mov 0 r10 8 122 15 2 Special Characters is the line comment character The character in jump instructions indicates current location and implemented only for TI syntax compatibility 8 122 15 3 Register Names General purpose registers are represented by predefined symbols of the form rN for global registers where N represents a number between 0 and 15 The leading letters may be in either upper or lower case for example r13 and R7 are both valid register names Register names PC SP and SR cannot be used as register names and will be treated as variables Use rO r1 and r instead 8 122 15 4 Assembler Extensions QrN As destination operand being treated as O rn O rN As source operand being treated as rn jCOND N Skips next N bytes followed by jump instruction and equivalent to jCOND N 2 152 Using as 8 122 16 Floating Point The MSP 430 family uses I
143. ant J JUMPify Longer Branches Many 32 bit computers permit a variety of branch instructions to do the same job Some of these instructions are short and fast but have a limited range others are long and slow but can branch anywhere in virtual memory Often there are 3 flavors of branch short medium and long Some other assemblers would emit short and medium branches unless told by this option to emit short and long branches t Temporary File Directory Some other assemblers may use a temporary file and this option takes a filename being the directory to site the temporary file Since as does not use a temporary disk file this option makes no difference t needs exactly one filename The Vax version of the assembler accepts additional options when compiled for VMS h n External symbol or section used for global variables names are not case sensi tive on VAX VMS and always mapped to upper case This is contrary to the C language definition which explicitly distinguishes upper and lower case To im plement a standard conforming C compiler names must be changed mapped to preserve the case information The default mapping is to convert all lower Chapter 8 Machine Dependent Features 181 case characters to uppercase and adding an underscore followed by a 6 digit hex value representing a 24 digit binary value The one digits in the binary value represent which characters are uppercase in the original symbol name
144. arator character is considered part of the preceding statement Newlines and separators within character constants are an exception they do not end statements It is an error to end any statement with end of file the last character of any input file should be a newline An empty statement is allowed and may include whitespace It is ignored A statement begins with zero or more labels optionally followed by a key symbol which determines what kind of statement it is The key symbol determines the syntax of the rest of the statement If the symbol begins with a dot then the statement is an assembler directive typically valid for any computer If the symbol begins with a letter the statement is an assembly language instruction it assembles into a machine language instruction Different versions of as for different computers recognize different instructions In fact the same symbol may represent a different instruction in a different computer s assembly language A label is a symbol immediately followed by a colon Whitespace before a label or after a colon is permitted but you may not have whitespace between a label s symbol and its colon See Section 5 1 Labels page 33 For HPPA targets labels need not be immediately followed by a colon but the definition of a label must begin in column zero This also implies that only one label may be defined on each line label directive followed by something another_label This is
145. ased on the instruction operands 8 112 18 Memory References An Intel syntax indirect memory reference of the form section base index scale disp is translated into the AT amp T syntax section disp base index scale where base and index are the optional 32 bit base and index registers disp is the optional displacement and scale taking the values 1 2 4 and 8 multiplies index to calculate the address of the operand If no scale is specified scale is taken to be 1 section specifies the optional section register for the memory operand and may override the default section register see a 80386 manual for section register defaults Note that section overrides in AT amp T syntax must be preceded by a If you specify a section override which coincides with the default section register as does not output any section register override prefixes to assemble the given instruction Thus section overrides can be specified to emphasize which section register is used for a given memory operand Here are some examples of Intel and AT amp T style memory references AT amp T 4 febp Intel ebp 4 base is Aebp disp is 4 section is missing and the default section is used Ass for addressing with 4ebp as the base register index scale are both missing AT amp T foo eax 4 Intel foo eax 4 index is Zeax scaled by a scale 4 disp is foo All other fields are missing Th
146. ata value The symbolic register name can be used in place of a non special register If a value isn t provided it defaults to zero Unless the option no merge gregs is specified non zero registers allocated with this directive may be eliminated by as another register with the same value used in its place Any of the in structions CSWAP GO LDA LDBU LDB LDHT LDOU LDO LDSF LDTU LDT LDUNC LDVTS LDWU LDW PREGO PRELD PREST PUSHGO STBU STB STCO STHT STOU STSF STTU STT STUNC SYNCD SYNCID can have a value nearby an initial value in place of its second and third operands Here nearby is defined as within the range 0 255 from the initial value of such an allocated register bufferi BYTE 0 0 0 0 0 buffer2 BYTE 0 0 0 0 0 GREG bufferi LDOU 42 buffer2 In the example above the Y field of the LDOUI instruction LDOU with a constant Z will be replaced with the global register allocated for buffer1 and the Z field will have the value 5 the offset from buffer1 to buffer2 The result is equivalent to this code bufferi BYTE 0 0 0 0 0 buffer2 BYTE 0 0 0 0 0 tmpreg GREG bufferi LDOU 42 tmpreg buffer2 buffer1 Global registers allocated with this directive are allocated in order higher to lower within
147. ating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register This feature is useful if the processor support the FR bit in its status register and this bit is known by the programmer to be set This bit prevents the aliasing of the double width register by the single width registers By default construct floats is selected allowing construction of these floating point constants trap no break as automatically macro expands certain division and multiplication instruc tions to check for overflow and division by zero This option causes as to generate code to take a trap exception rather than a break exception when an error is detected The trap instructions are only supported at Instruction Set Architecture level 2 and higher break no trap Generate code to take a break exception rather than a trap exception when an error is detected This is the default mpdr mno pdr Control generation of pdr sections Off by default on IRIX on elsewhere n When this option is used as will issue a warning every time it generates a nop instruction from a macro 142 Using as 8 120 3 MIPS ECOFF object code Assembling for a MIPS ECOFF target supports some additional sections besides the usual text data and bss The additional sections are rdata used for read only data sdata used for small data and sbss used for small common objects
148. ating point numbers for compatibility with other development tools 8 106 28 Opcodes For detailed information on the D10V machine instruction set see D10V Architecture A VLIW Microprocessor for Multimedia Applications Mitsubishi Electric Corp as imple ments all the standard D10V opcodes The only changes are those described in the section on size modifiers Chapter 8 Machine Dependent Features 91 8 107 D30V Dependent Features 8 107 29 D30V Options The Mitsubishi D30V version of as has a few machine dependent options Q The D30V can often execute two sub instructions in parallel When this option is used as will attempt to optimize its output by detecting when instructions can be executed in parallel n When this option is used as will issue a warning every time it adds a nop instruction N When this option is used as will issue a warning if it needs to insert a nop after a 32 bit multiply before a load or 16 bit multiply instruction 8 107 30 Syntax The D30V syntax is based on the syntax in Mitsubishi s D30V architecture manual The differences are detailed below 8 107 30 1 Size Modifiers The D30V version of as uses the instruction names in the D30V Architecture Manual However the names in the manual are sometimes ambiguous There are instruction names that can assemble to a short or long form opcode How does the assembler pick the correct form as will always pick the smallest form if it can Wh
149. bar 8 131 29 VAX Operands The immediate character is for Unix compatibility not 4 as DEC writes it The indirect character is for Unix compatibility not as DEC writes it The displacement sizing character is an accent grave for Unix compatibility not as DEC writes it The letter preceding may have either case G is not understood but all other letters b i 1 s w are understood 184 Using as Register names understood are r0 r1 r2 rib ap fp sp pc Upper and lower case letters are equivalent For instance tstb w 4 r5 Any expression is permitted in an operand Operands are comma separated 8 131 830 Not Supported on VAX Vax bit fields can not be assembled with as Someone can add the required code if they really need it 8 132 v850 Dependent Features 8 132 1 Options as supports the following additional command line options for the V850 processor family wsigned_overflow Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants wunsigned overflow mv850 mv850e mv850e1 mv850any Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes By default this option is disabled as it is
150. bility The line comment character is unless the bitwise or option is used If a appears at the beginning of a line it is treated as a comment unless it looks like line file in which case it is treated normally Chapter 8 Machine Dependent Features 133 8 118 M68HC11 and M68HC12 Dependent Features 8 118 44 M68HC11 and M68HC12 Options The Motorola 68HC11 and 68HC12 version of as have a few machine dependent options m68hc11 m68hc12 m68hcs12 mshort mlong This option switches the assembler in the M68HC11 mode In this mode the assembler only accepts 68HC11 operands and mnemonics It produces code for the 68HC11 This option switches the assembler in the M68HC12 mode In this mode the assembler also accepts 68HC12 operands and mnemonics It produces code for the 68HC12 A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications This option switches the assembler in the M68HCS12 mode This mode is similar to m68hc12 but specifies to assemble for the 68HCS12 series The only difference is on the assembling of the movb and movw instruction when a PC relative operand is used This option controls the ABI and indicates to use a 16 bit integer ABI It has no effect on the assembled instructions This is the default This option controls the ABI and indicates to use a 32 bit integer ABI mshort double This option
151. ble Otherwise BNEZ would be used 8 133 9 2 Function Call Relaxation Function calls may require relaxation because the Xtensa immediate call instructions CALLO CALL4 CALL8 and CALL12 provide a PC relative offset of only 512 Kbytes in either direction For larger programs it may be necessary to use indirect calls CALLXO CALLX4 CALLX8 and CALLX12 where the target address is specified in a register The Xtensa assembler can automatically relax immediate call instructions into indirect call instructions This relaxation is done by loading the address of the called function into the callee s return address register and then using a CALLX instruction So for example call8 func might be relaxed to literal L1 func 132r a8 L1 callx8 a8 Because the addresses of targets of function calls are not generally known until link time the assembler must assume the worst and relax all the calls to functions in other source files not just those that really will be out of range The linker can recognize calls that Chapter 8 Machine Dependent Features 195 were unnecessarily relaxed but it can only partially remove the overhead introduced by the assembler Call relaxation has a negative effect on both code size and performance so this relaxation is disabled by default If a program is too large and some of the calls are out of range function call relaxation can be enabled using the longcalls command line option or the longcalls
152. cal absolute symbols from the outgoing symbol table v version Print the as version version Print the as version and exit W no warn Suppress warning messages Chapter 1 Overview 5 fatal warnings Treat warnings as errors warn Don t suppress warning messages or treat them as errors W Ignored x Tgnored Z Generate an object file even after errors files Standard input or source files to assemble The following options are available when as is configured for an ARC processor marc 5161718 This option selects the core processor variant EB EL Select either big endian EB or little endian EL output The following options are available when as is configured for the ARM processor family mcpu processor extension Specify which ARM processor variant is the target march architecture extension Specify which ARM architecture variant is used by the target mfpu floating point format Select which Floating Point architecture is the target mthumb Enable Thumb only instruction decoding mapcs 32 mapcs 26 mapcs float mapcs reentrant moabi Select which procedure calling convention is in use EB EL Select either big endian EB or little endian EL output mthumb interwork Specify that the code has been generated with interworking between Thumb and ARM code in mind k Specify that PIC code has been generated See the info pages for documentation of
153. can be done with imul 69 eax rather than imul 69 4eax eax Chapter 8 Machine Dependent Features 115 8 113 Intel i860 Dependent Features 8 113 26 i860 Notes This is a fairly complete i860 assembler which is compatible with the UNIX System V 860 Release 4 assembler However it does not currently support SVR4 PIC i e GOT GOTOFF PLT Like the SVR4 860 assembler the output object format is ELF32 Currently this is the only supported object format If there is sufficient interest other formats such as COFF may be implemented Both the Intel and AT amp T SVR4 syntaxes are supported with the latter being the default One difference is that AT amp T syntax requires the prefix on register names while Intel syntax does not Another difference is in the specification of relocatable expressions The Intel syntax is hajexpression whereas the SVR4 syntax is expression ha and similarly for the 1 and h selectors 8 113 27 i860 Command line Options 8 113 27 1 SVR4 compatibility options V Print assembler version Qy Ignored Qn Ignored 8 113 27 2 Other options EL Select little endian output this is the default EB Select big endian output Note that the i860 always reads instructions as little endian data so this option only effects data and not instructions mwarn expand Emit a warning message if any pseudo instruction expansions occurred For ex ample a or instruction with an imme
154. cases the comment is equivalent to one space Anything from through the next is a comment This means you may not nest these comments 22 Using as The only way to include a newline n in a comment is to use this sort of comment This sort of comment does not nest Anything from the line comment character to the next newline is considered a comment and is ignored The line comment character is for the AMD 29K family on the ARC on the ARM for the H8 300 family for the H8 500 family for the HPPA on the i386 and x86 64 on the i960 for the PDP 11 for picoJava for Motorola PowerPC for the Renesas SuperH SH on the SPARC on the ip2k on the m32r on the 680x0 on the 68HC11 and 68HC12 on the M880x0 on the Vax for the Z8000 on the V850 for Xtensa systems see Chapter 8 Machine Dependencies page 67 On some machines there are two different line comment characters One character only begins a comment if it is the first non whitespace character on a line while the other always begins a comment The V850 assembler also supports a double dash as starting a comment that extends to the end of the line as To be compatible with past assemblers lines that begin with have a special inter pretation Following th
155. cation Number DZ9AR004 Chapter 8 Machine Dependent Features 107 8 112 80386 Dependent Features The 1386 version as supports both the original Intel 386 architecture in both 16 and 32 bit mode as well as AMD x86 64 architecture extending the Intel architecture to 64 bits 8 112 13 Options The i386 version of as has a few machine dependent options 32 64 Select the word size either 32 bits or 64 bits Selecting 32 bit implies Intel 1386 architecture while 64 bit implies AMD x86 64 architecture These options are only available with the ELF object file format and require that the necessary BFD support has been included on a 32 bit platform you have to add enable 64 bit bfd to configure enable 64 bit usage and use x86 64 as target platform n By default x86 GAS replaces multiple nop instructions used for alignment within code sections with multi byte nop instructions such as leal 0 esi 1 esi This switch disables the optimization 8 112 14 AT amp T Syntax versus Intel Syntax as now supports assembly using Intel assembler syntax intel syntax selects Intel mode and att syntax switches back to the usual AT amp T mode for compatibility with the output of gcc Either of these directives may have an optional argument prefix or noprefix specifying whether registers require a prefix AT amp T System V 386 assembler syntax is quite different from Intel syntax We mention these differences because almost all 8038
156. causes the symbol to be entered into the global offset table The value is a 32 bit index for that sym bol into the global offset table The name of the corresponding relocation is R_CRIS_32_GOT Example move d r0 extsym GOT r9 GOT16 Same as for GOT but the value is a 16 bit index into the global offset ta ble The corresponding relocation is R_CRIS_16_GOT Example move d r0 asymbol GOT16 r10 PLT This suffix is used for function symbols It causes a procedure linkage table an array of code stubs to be created at the time the shared object is created or linked against together with a global offset table entry The value is a pc relative offset to the corresponding stub code in the procedure linkage table This arrangement causes the run time symbol resolver to be called to look up and set the value of the symbol the first time the function is called at latest depending environment variables It is only safe to leave the symbol unresolved this way if all references are function calls The name of the relocation is R_CRIS_32_PLT_PCREL Example add d fnname PLT pc PLTG Chapter 8 Machine Dependent Features 85 Like PLT but the value is relative to the beginning of the global offset table The relocation is R_CRIS_32_PLT_GOTREL Example move d fnname PLTG r3 GOTPLT Similar to PLT but the value of the symbol is a 32 bit index into the global offset table This is somewhat of
157. chael Hayes and Greg Smart contributed to the various tic flavors David Heine Sterling Augustine Bob Wilson and John Ruttenberg from Tensilica Inc added support for Xtensa processors Several engineers at Cygnus Support have also provided many small bug fixes and con figuration enhancements Many others have contributed large or small bugfixes and enhancements If you have contributed significant work and are not mentioned on this list and want to be let us know Some of the history has been lost we are not intentionally leaving anyone out Appendix A GNU Free Documentation License 207 Appendix A GNU Free Documentation License Version 1 1 March 2000 Copyright C 2000 Free Software Foundation Inc 59 Temple Place Suite 330 Boston MA 02111 1307 USA Everyone is permitted to copy and distribute verbatim copies of this license document but changing it is not allowed 0 PREAMBLE The purpose of this License is to make a manual textbook or other written document free in the sense of freedom to assure everyone the effective freedom to copy and redistribute it with or without modifying it either commercially or noncommercially Secondarily this License preserves for the author and publisher a way to get credit for their work while not being considered responsible for modifications made by others This License is a kind of copyleft which means that derivative works of the document must themselves be free in
158. ck directive TIC54X 174 sbttl directive sir aa 57 SCL directive cde papas oa 57 sdaoff pseudo op V850 2 008 188 search path for include suus 16 sect directive AMD 29K 69 sect directive MSP 430 152 sect directive TIC5AX luuuuss 174 section directive COFF version 58 section directive ELF version 58 section directive V8B50 ooooooooomoooo 187 section override prefixes 1386 109 Section Stack cei ecol Re 55 56 58 62 section relative addressing 28 Section ib ewe 27 sections in messages internal 29 Sections 19805 ed ood di 108 sections named toto rad 28 sections x86 04 Li icec bere ii PES 108 seg directive SPARC 0000 167 SO Miastenia 179 Set directive Jouer rea E REN GER TUE 59 set directive M88K o oooooocoooooo ooo 138 set directive TICBAX 174 SH addressing modes 0000 161 SH floating point IEEE 0 161 SH line comment character 160 SH line separator seeeeeee eere 160 SH machine directiveS o o ooooooo oo 161 SH opcode summary 20005 161 DH Options cubres PO ee eee eet 160 SH register iia riders 160 SH support ore bei o id 160 SH64 ABI options 0020000 163 SH64
159. code CRIS 83 Position independent code symbols in CRIS 84 PowerPC architectures o oooooooooooo 158 PowerPC options 0 e ee eeeeee 158 PowerPC support 2c esse eens 158 precedence of directives o o oooooo 196 precedence of operators 000 ee o 38 precision floating point 0 25 prefix operators 0 cece eee eee eee ee 38 prefixes 1980 1 ime esp piese ta urru aeaa E 109 preprocessinE i carpa ria 21 preprocessing turning on and off 21 previous directive ooooooooooooooo 55 primary attributes COFF symbols 36 print directives iile deb RU Red futs 56 proc directive SPARC o oo occccococooo oo 167 protected directive oooooooo 56 protected registers AMD 29K 68 pseudo op dword CRIS 004 85 pseudo op syntax CRIS 0000 85 pseudo op BSPEC MMIX 149 pseudo op BYTE MMIX 148 pseudo op ESPEC MMIX 149 pseudo op GREG MMIX 148 pseudo op IS MMIX ssseessees 147 pseudo op LOC MMIX 147 pseudo op LOCAL MMIX 147 pseudo op OCTA MMIX 148 pseudo op PREFIX MMIX 149 pseudo op TETRA MMIX 148 pseudo op WYDE MMIX 148 pseudo opcodes M6
160. controls the ABI and indicates to use a 32 bit float ABI This is the default mlong double This option controls the ABI and indicates to use a 64 bit float ABI strict direct mode You can use the strict direct mode option to disable the automatic trans lation of direct page mode addressing into extended mode when the instruction does not support direct mode For example the clr instruction does not sup port direct page mode addressing When it is used with the direct page mode as will ignore it and generate an absolute addressing This option prevents as from doing this and the wrong usage of the direct page mode will raise an error short branchs The short branchs option turns off the translation of relative branches into absolute branches when the branch offset is out of range By default as transforms the relative branch bsr bgt bge beq bne ble blt phi bcc bls bcs bmi bvs bvs bra into an absolute branch when the offset is out of the 128 127 range In that case the bsr instruction is translated into a jsr the bra instruction is translated into a jmp and the conditional branchs instructions are inverted and followed by a jmp This 134 Using as option disables these translations and as will generate an error if a relative branch is out of range This option does not affe
161. ct the optimization associated to the jbra jbsr and jbXX pseudo opcodes force long branchs The force long branchs option forces the translation of relative branches into absolute branches This option does not affect the optimization associated to the jbra jbsr and jbXX pseudo opcodes print insn syntax You can use the print insn syntax option to obtain the syntax description of the instruction when an error is detected print opcodes The print opcodes option prints the list of all the instructions with their syntax The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction The list is printed in alphabetical order Once the list is printed as exits generate example The generate example option is similar to print opcodes but it gen erates an example for each instruction instead 8 118 45 Syntax In the M68HC11 syntax the instruction name comes first and it may be followed by one or several operands up to three Operands are separated by comma In the normal mode as will complain if too many operands are specified for a given instruction In the MRI mode turned on with M option it will treat them as comments Example inx lda 23 bset 2 x 4 brclr bot 8 foo The following addressing modes are understood for 68HC11 and 68HC12 Immediate number
162. ction name This is one of the ELF section stack manipulation directives The others are section see Section 7 76 Section page 57 pushsection see Section 7 71 PushSection page 56 popsection see Section 7 66 PopSection page 55 and previous see Section 7 65 Previous page 55 This directive replaces the current subsection with name The current section is not changed The replaced subsection is put onto the section stack in place of the then current top of stack subsection 7 88 symver Use the symver directive to bind symbols to specific version nodes within a source file This is only supported on ELF platforms and is typically used when assembling files to be linked into a shared library There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library For ELF targets the symver directive can be used like this symver name name20nodename If the symbol name is defined within the file being assembled the symver directive effectively creates a symbol alias with the name name2 nodename and in fact the main reason that we just don t try and create a regular alias is that the character isn t permitted in symbol names The name2 part of the name is the actual name of the symbol by which it will be externally referenced The name name itself is merely a name of convenience that is used so that it is possible to have
163. d p2 evaluating to b When you call a macro you can specify the argument values either by position or by keyword For example sum 9 17 is equivalent to sum to 17 from 9 endm Mark the end of a macro definition 54 Using as exitm Exit early from the current macro definition as maintains a counter of how many macros it has executed in this pseudo variable you can copy that number to your output with but only within a macro definition 7 61 nolist Control in conjunction with the 1ist directive whether or not assembly listings are generated These two directives maintain an internal counter which is zero initially list increments the counter and nolist decrements it Assembly listings are generated whenever the counter is greater than zero 1 62 octa bignums This directive expects zero or more bignums separated by commas For each bignum it emits a 16 byte integer The term octa comes from contexts in which a word is two bytes hence octa word for 16 bytes 7 63 org new lc fill Advance the location counter of the current section to new lc new lc is either an absolute expression or an expression with the same section as the current subsection That is you can t use org to cross sections if new lc has the wrong section the org directive is ignored To be compatible with former assemblers if the section of new lc is absolute as issues a warning then pretends
164. d be repeated break terminates the loop so that assembly begins after the endloop directive The optional condition will cause the loop to terminate only if it evaluates to zero macro name macro parami param n mexit endm See the section on macros for more explanation See Section 8 129 18 TIC54X Macros page 176 nlib filename filename Load the macro library filename filename must be an archived library BFD ar compatible of text files expected to contain only macro definitions The standard include search path is used mlist mnolist Control whether to include macro and loop block expansions in the listing output Ignored mmregs Define global symbolic names for the c54x registers Supposedly equivalent to executing set directives for each register with its memory mapped value but in reality is provided only for compatibility and does nothing newblock This directive resets any TIC54X local labels currently defined Normal as local labels are unaffected option option list Set listing options Ignored Sblock section name section name name n name n Designate section name for blocking Blocking guarantees that a section will start on a page boundary 128 words if it would otherwise cross a page bound ary Only initialized sections may be designated with this directive See also See Section 8 129 10 TIC54X Block page 168 sect section name Define named initialized section
165. d in a slightly more efficient manner than the others Here is an example 1 branch 1f 2 branch 1b 1 branch 2f 2 branch 1b Which is the equivalent of label 1 branch label 3 label 2 branch label 1 label 3 branch label 4 label 4 branch label 3 Local symbol names are only a notational device They are immediately transformed into more conventional symbol names before the assembler uses them The symbol names stored in the symbol table appearing in error messages and optionally emitted to the object file The names are constructed using these parts L All local labels begin with L Normally both as and 1d forget symbols that start with L These labels are used for symbols you are never intended to see If you use the L option then as retains these symbols in the object file If you also instruct 1d to retain these symbols you may use them in debugging number This is the number that was used in the local label definition So if the label is written 55 then the number is 55 C B This unusual character is included so you do not accidentally invent a symbol of the same name The character has ASCII value of 002 control B ordinal number This is a serial number to keep the labels distinct The first definition of 0 gets the number 1 The 15th definition of 0 gets the number 15 and so on Likewise the first definition of 1 gets the number 1 and its 15t
166. d multiple identical Invariant Sections may be replaced with a single copy If there are multiple Invariant Sections with the same name but different contents make the title of each such section unique by adding at the end of it in parentheses the name of the original author or publisher of that section if known or else a unique number Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work In the combination you must combine any sections entitled History in the various original documents forming one section entitled History likewise combine any sec tions entitled Acknowledgements and any sections entitled Dedications You must delete all sections entitled Endorsements 6 COLLECTIONS OF DOCUMENTS You may make a collection consisting of the Document and other documents released under this License and replace the individual copies of this License in the various documents with a single copy that is included in the collection provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects You may extract a single document from such a collection and distribute it individu ally under this License provided you insert a copy of this License into the extracted document and follow this License in all other respects regarding verbatim copying of that document 7 AGGREGATION WITH INDEPEN
167. d these opcodes Here are the mnemonics and the code they can expand into jbsb Jsb is already an instruction mnemonic so we chose jbsb byte displacement bsbb word displacement bsbw long displacement jsb jbr jr Unconditional branch byte displacement brb word displacement brw long displacement jmp jCOND COND may be any one of the conditional branches neq nequ eql eqlu gtr geq 1ss gtru lequ vc vs gequ cc 1ssu cs COND may also be one of the bit tests bs bc bss bcs bsc bcc bssi bcci lbs 1bc NOTCOND is the opposite condition to COND byte displacement bCOND word displacement bNOTCOND foo brw foo long displacement bNOTCOND foo jmp foo jacbX X may be one of bd f ghlw word displacement OPCODE Chapter 8 jaobYYY jsobZZZ aobleq aoblss sobgeq sobgtr Machine Dependent Features 183 long displacement OPCODE foo brb bar foo jmp bar YYY may be one of 1ss leq ZZZ may be one of geq gtr byte displacement OPCODE word displacement OPCODE foo brb bar foo brw destination bar long displacement OPCODE foo brb bar foo jmp destination bar byte displacement OPCODE word displacement OPCODE foo brb bar foo brw destination bar long displacement OPCODE foo brb bar foo jmp destination
168. data structures in your own code 8 128 7 Floating Point The Sparc uses IEEE floating point numbers 8 128 8 Sparc Machine Directives The Sparc version of as supports the following additional machine directives align This must be followed by the desired alignment in bytes common This must be followed by a symbol name a positive number and bss This behaves somewhat like comm but the syntax is different half This is functionally identical to short nword On the Sparc the nword directive produces native word sized value ie if as sembling with 32 it is equivalent to word if assembling with 64 it is equivalent to xword proc This directive is ignored Any text following it on the same line is also ignored register This directive declares use of a global application or system register It must be followed by a register name g2 96g3 V6g6 or g7 comma and the symbol name for that register If symbol name is scratch it is a scratch register if it is ignore it just suppresses any errors about using undeclared global register but does not emit any information about it into the object file This can be useful e g if you save the register before use and restore it after reserve This must be followed by a symbol name a positive number and bss This behaves somewhat like 1comm but the syntax is different Seg This must be followed by text data or datai It behaves like text data or
169. ded to be self explanatory in the grand Unix tradition Error messages have the format file_name NNN FATAL Error Message Text The file name and line number are derived as for warning messages The actual message text may be rather less explanatory because many of them aren t supposed to happen Chapter 2 Command Line Options 15 2 Command Line Options This chapter describes command line options available in all versions of the GNU as sembler see Chapter 8 Machine Dependencies page 67 for options specific to particular machine architectures If you are invoking as via the GNU C compiler you can use the Wa option to pass arguments through to the assembler The assembler arguments must be separated from each other and the Wa by commas For example gcc c g 0 Wa alh L file c This passes two options to the assembler alh emit a listing to standard output with high level and assembly source and L retain local symbols in the symbol table Usually you do not need to use this Wa mechanism since many compiler command line options are automatically passed to the assembler by the compiler You can call the GNU compiler driver with the v option to see precisely what options it passes to each compilation pass including the assembler 2 1 Enable Listings a cdhlns These options enable listing output from the assembler By itself a requests high level assembly and symbols
170. definitions for multiple versions of a function within a single source file and so that the compiler can unambiguously know which version of a function is being mentioned The nodename portion of the alias should be the name of a node specified in the version script supplied to the linker when building a shared library If you are attempting to override a versioned symbol from a shared library then nodename should correspond to the nodename of the symbol you are trying to override Chapter 7 Assembler Directives 63 If the symbol name is not defined within the file being assembled all references to name will be changed to name2 nodename If no reference to name is made name20nodename will be removed from the symbol table Another usage of the symver directive is symver name name200nodename In this case the symbol name must exist and be defined within the file being assembled It is similar to name20nodename The difference is name200nodename will also be used to resolve references to name2 by the linker The third usage of the symver directive is symver name name2000nodename When name is not defined within the file being assembled it is treated as name20nodename When name is defined within the file being assembled the symbol name name will be changed to name200nodename 7 89 tag structname This directive is generated by compilers to include auxiliary debugging information in the symbol table It is only permitted inside
171. dentifiers 0000000 68 AMD 29K line comment character 68 AMD 29K machine directives 69 AMD 29K macros 00000ceeeeeeeeee 68 AMD 29K opcodes constr dede ped 69 AMD 29K options none ssusss 68 AMD 29K protected registers 68 AMD 29K register names 004 68 AMD 29K special purpose registers 68 AMD 29K support ssseseeseee eese 68 ARC floating point IEEE isses TT ARC machine directivesS ooooocooooooooo 78 ARC opcodeS 000 20 ccc ees 78 ARC options none sesseessuss fs ARC register names eeeseeeeeeees 77 ARC special characters 0005 aff ARG SUDDOELb usada we E e Riego 77 arch arco ARO ta d xp TED dd TT arc6 arc6 ARCO adds TT arc arer ARO paa TT arc8 arcs ARO a TT arch directive 1386 oooooooocooooo 113 arch directive x86 64 o ooooooo ooooo 113 architecture options 1960 o ooooo ooo o 118 architecture options P2022 122 architecture options IP2K 122 architecture options M32R 123 architecture options M32RX 123 architecture options M680x0 127 architectures PowerPC 158 architectures SPARC Luuuuuuesss 166 arguments for addition 38 arguments for subtraction 0
172. des for the H8 300 rn Register direct rn Register indirect d rn d 16 rn d 24 rn Register indirect 16 bit or 24 bit displacement d from register n 24 bit dis placements are only meaningful on the H8 300H rn Register indirect with post increment rn Register indirect with pre decrement 96 aa aa aa aa Hxx xx Hxx Hxx aa aa 16 24 16 32 8 Using as Absolute address aa The address size 24 only makes sense on the H8 300H Immediate data xx You may specify the 8 16 or 32 for clarity if you wish but as neither requires this nor uses it the data size required is taken from context Memory indirect You may specify the 8 for clarity if you wish but as neither requires this nor uses it 8 108 3 Floating Point The H8 300 family has no hardware floating point but the float directive generates IEEE floating point numbers for compatibility with other development tools Chapter 8 Machine Dependent Features 97 8 108 4 H8 300 Machine Directives as has the following machine dependent directives for the H8 300 h8300h Recognize and emit additional instructions for the H8 300H variant and also make int emit 32 bit numbers rather than the usual 16 bit for the H8 300 family h8300s Recognize and emit additional instructions for the H8S variant and also make int emit 32 bit numbers rather than the usual 16 bit for
173. diate larger than 16 bits will be expanded into two instructions This is a very undesirable feature to rely on so this flag can help detect any code where it happens One use of it for instance has been to find and eliminate any place where gcc may emit these pseudo instructions mxp Enable support for the i860XP instructions and control registers By default this option is disabled so that only the base instruction set i e i860XR is supported mintel syntax The i860 assembler defaults to AT amp T SVRA syntax This option enables the Intel syntax 116 Using as 8 113 28 1860 Machine Directives dual Enter dual instruction mode While this directive is supported the preferred way to use dual instruction mode is to explicitly code the dual bit with the d prefix enddual Exit dual instruction mode While this directive is supported the preferred way to use dual instruction mode is to explicitly code the dual bit with the d prefix atmp Change the temporary register used when expanding pseudo operations The default register is r31 The dual enddual and atmp directives are available only in the Intel syntax mode Both syntaxes allow for the standard align directive However the Intel syntax addi tionally allows keywords for the alignment parameter align type where type is one of short long quad single double representing alignments of 2 4 16 4 and 8 respectively 8 113 29 1860 Opcodes
174. directive see Section 8 133 10 3 longcalls page 197 8 133 9 3 Other Immediate Field Relaxation The MOVI machine instruction can only materialize values in the range from 2048 to 2047 Values outside this range are best materialized with L32R instructions Thus movi a0 100000 is assembled into the following machine code literal L1 100000 132r a0 L1 The L8UI machine instruction can only be used with immediate offsets in the range from 0 to 255 The L16SI and L16UI machine instructions can only be used with offsets from 0 to 510 The L321 machine instruction can only be used with offsets from 0 to 1020 A load offset outside these ranges can be materalized with an L32R instruction if the destination register of the load is different than the source address register For example 132i ai a0 2040 is translated to literal L1 2040 132r al L1 addi al a0 al 132i al al 0 If the load destination and source address register are the same an out of range offset causes an error The Xtensa ADDI instruction only allows immediate operands in the range from 128 to 127 There are a number of alternate instruction sequences for the generic ADDI operation First if the immediate is 0 the ADDI will be turned into a MOV N instruction or the equivalent OR instruction if the code density option is not available If the ADDI immediate is outside of the range 128 to 127 but inside the range 32896 to 32639 an ADDMI instruction or A
175. e should be an absolute expression see Chapter 6 Expressions page 37 the logical line number of the next line Then a string see Section 3 6 1 1 Strings page 23 is allowed if present it is a new logical file name The rest of the line if any should be whitespace If the first non whitespace characters on the line are not numeric the line is ignored Just like a comment This is an ordinary comment 42 6 new_file_name New logical file name This is logical line 36 This feature is deprecated and may disappear from future versions of as 3 4 Symbols A symbol is one or more characters chosen from the set of all letters both upper and lower case digits and the three characters _ On most machines you can also use in symbol names exceptions are noted in Chapter 8 Machine Dependencies page 67 No symbol may begin with a digit Case is significant There is no length limit all characters are significant Symbols are delimited by characters not in that set or by the beginning of a file since the source program must end with a newline the end of a file is not a possible symbol delimiter See Chapter 5 Symbols page 33 3 5 Statements A statement ends at a newline character n or line separator character The line separator is usually unless this conflicts with the comment character see Chapter 8 Chapter 3 Syntax 23 Machine Dependencies page 67 The newline or sep
176. e sections of code and the linker will attempt to relax them 8 132 2 Syntax 8 132 2 1 Special Characters is the line comment character 8 132 2 2 Register Names as supports the following names for registers general register 0 r0 zero general register 1 rl general register 2 r2 hp general register 3 r3 sp general register 4 r4 gp general register 5 r5 tp general register 6 r6 general register 7 r7 general register 8 r8 general register 9 r9 general register 10 r10 general register 11 r11 general register 12 r12 186 general register 13 r13 general register 14 r14 general register 15 r15 general register 16 r16 general register 17 r17 general register 18 r18 general register 19 r19 general register 20 r20 general register 21 r21 general register 22 r22 general register 23 r23 general register 24 r24 general register 25 r25 general register 26 r26 general register 27 r27 general register 28 r28 general register 29 r29 general register 30 r30 ep general register 31 r31 lp Using as Chapter 8 Machine Dependent Features 187 system register 0 eipc system register 1 eipsw system register 2 fepc system register 3 fepsw system register 4 ecr system register 5 psw system register 16 ctpc system register 17 ctpsw system register 18 dbpc system register 19 dbpsw system register 20 ctbp 8
177. e Chapter 2 Command Line Options page 15 Quotation marks are required around file 7 48 int expressions Expect zero or more expressions of any section separated by commas For each expres sion emit a number that at run time is the value of that expression The byte order and bit size of the number depends on what kind of target the assembly is for 7 49 internal names This one of the ELF visibility directives The other two are hidden see Section 7 42 hidden page 48 and protected see Section 7 68 protected page 56 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to internal which means that the symbols are considered to be hidden i e not visible to other components and that some extra processor specific processing must also be performed upon the symbols as well 7 50 irp symbol values Evaluate a sequence of statements assigning different values to symbol The sequence of statements starts at the irp directive and is terminated by an endr directive For each value symbol is set to value and the sequence of statements is assembled If no value is listed the sequence of statements is assembled once with symbol set to the null string To refer to symbol within the sequence of statements use symbol For example assembling Arp param 1 2 3 move d param sp endr is equivalent to assembling
178. e all symbol arithmetic into the object file because not all symbol arithmetic can be represented However the option can still be useful in specific applications This option is used when the compiler generates debug information When gcc is using mips tfile to generate debug information for ECOFF local labels must be passed through to the object file Otherwise this option has no effect A local common symbol larger than size is placed in bss while smaller symbols are placed in sbss These options are ignored for backward compatibility 8 102 8 Syntax The assembler syntax closely follow the Alpha Reference Manual assembler directives and general syntax closely follow the OSF 1 and OpenVMS syntax with a few differences for ELF Chapter 8 Machine Dependent Features 71 8 102 8 1 Special Characters is the line comment character can be used instead of a newline to separate statements 8 102 8 2 Register Names The 32 integer registers are referred to as n or rn In addition registers 15 28 29 and 30 may be referred to by the symbols fp at gp and sp respectively The 32 floating point registers are referred to as fn 8 102 8 3 Relocations Some of these relocations are available for ECOFF but mostly only for ELF They are modeled after the relocation format introduced in Digital Unix 4 0 but there are additions The format is tag or
179. e and Jump instructions with target displace ments larger than 13 bits 8 114 33 1 callj You can write callj to have the assembler or the linker determine the most appro priate form of subroutine call call bal or calls If the assembly source contains enough information a leafproc or sysproc directive defining the operand then as translates the ca11j if not it simply emits the ca11j leaving it for the linker to resolve 8 114 33 2 Compare and Branch The 960 architectures provide combined Compare and Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself However if you specify a branch target far enough away that its address won t fit in 13 bits the assembler can either issue an error or convert your Compare and Branch instruction into separate instructions to do the compare and the branch Whether as gives an error or expands the instruction depends on two choices you can make whether you use the no relax option and whether you use a Compare and Branch instruction or a Compare and Jump instruction The Jump instructions are always expanded if necessary the Branch instructions are expanded when necessary un less you specify no relax in which case as gives an error instead These are the Compare and Branch instructions their Jump variants and the instruc tion pairs they may expand into Compare a
180. e blocking size or to start on a page boundary if it is larger than the blocking size 8 129 11 Environment Settings C54XDSP_DIR and A_DIR are semicolon separated paths which are added to the list of directories normally searched for source and include files C54XDSP_DIR will override A_DIR 8 129 12 Constants Syntax The TIC54X version of as allows the following additional constant formats using a suffix to indicate the radix Binary 000000B 011000b Octal 10Q 224q Hexadecimal 45h OFH 8 129 13 String Substitution A subset of allowable symbols which we ll call subsyms may be assigned arbitrary string values This is roughly equivalent to C preprocessor define macros When as encounters one of these symbols the symbol is replaced in the input stream by its string value Subsym names must begin with a letter Chapter 8 Machine Dependent Features 169 Subsyms may be defined using the asg and eval directives See Section 8 129 17 asg page 171 See Section 8 129 17 eval page 171 Expansion is recursive until a previously encountered symbol is seen at which point substitution stops In this example x is replaced with SYM2 SY M2 is replaced with SYM1 and SYM1 is replaced with x At this point x has already been encountered and the substitution stops asg x SYM1 asg SYM1 SYM2 asg SYM2 x add x a final code assembled is add x a Macro parameters are converted to subsyms
181. e input file will make the bug go away and which changes will not affect it Chapter 9 Reporting Bugs 203 This is often time consuming and not very useful because the way we will find the bug is by running a single example under the debugger with breakpoints not by pure deduction from a series of examples We recommend that you save your time for something else Of course if you can find a simpler example to report instead of the original one that is a convenience for us Errors in the output will be easier to spot running under the debugger will take less time and so on However simplification is not vital if you do not want to do this report the bug anyway and send us the entire test case you used e A patch for the bug A patch for the bug does help us if it is a good one But do not omit the necessary information such as the test case on the assumption that a patch is all we need We might see problems with your patch and decide to fix the problem another way or we might not understand it at all Sometimes with a program as complicated as as it is very hard to construct an example that will make the program follow a certain path through the code If you do not send us the example we will not be able to construct one so we will not be able to verify that the bug is fixed And if we cannot understand what bug you are trying to fix or why your patch should be an improvement we will not install it A test case will help us to
182. e inside the delimited region the assembler puts literals in the section name literal If this section does not yet exist the assembler creates it The name parameter is optional If name is not specified the literal prefix is set to the default for the file This default is usually literal but can be changed with the rename section command line argument 8 133 10 8 freeregs This directive tells the assembler that the given registers are unused in the region begin freeregs ril ri end freeregs This allows the assembler to use these registers for relaxations or optimizations They are actually only for relaxations at present but the possibility of optimizations exists in the future Nested freeregs directives can be used to add additional registers to the list of those available to the assembler For example begin freeregs a3 a4 begin freeregs a5 has the effect of declaring a3 a4 and a5 all free 8 133 10 9 frame This directive tells the assembler to emit information to allow the debugger to locate a function s stack frame The syntax is frame reg size where reg is the register used to hold the frame pointer usually the same as the stack pointer and size is the size in bytes of the stack frame The frame directive is typically placed immediately after the ENTRY instruction for a function In almost all circumstances this information just duplicates the information given in the function s ENT
183. e instructions have alternative names BCC BHIS BCS BLO L2DR L2D L3DR L3D SYS TRAP 8 123 23 Synthetic Instructions The JBR and JCC synthetic instructions are not supported yet Chapter 8 Machine Dependent Features 157 8 124 picoJava Dependent Features 8 124 1 Options as has two additional command line options for the picoJava architecture ml This option selects little endian data output mb This option selects big endian data output 158 Using as 8 125 PowerPC Dependent Features 8 125 2 Options The PowerPC chip family includes several successive levels using the same core instruc tion set but including a few additional instructions at each level There are exceptions to this however For details on what instructions each variant supports please see the chip s architecture reference manual The following table lists all available PowerPC options mpwrx mpwr2 Generate code for POWER 2 RIOS2 mpwr Generate code for POWER RIOS1 m601 Generate code for PowerPC 601 mppc mppc32 m603 m604 Generate code for PowerPC 603 604 m403 m405 Generate code for PowerPC 403 405 m440 Generate code for PowerPC 440 BookE and some 405 instructions m7400 m7410 m7450 m7455 Generate code for PowerPC 7400 7410 7450 7455 mppc64 m620 Generate code for PowerPC 620 625 630 mppc64bridge Generate code for PowerPC 64 including bridge insns mbooke64 Generate code for 64 bit BookE
184. e original English version of this License the original English version will prevail TERMINATION You may not copy modify sublicense or distribute the Document except as expressly provided for under this License Any other attempt to copy modify sublicense or distribute the Document is void and will automatically terminate your rights under this License However parties who have received copies or rights from you under this License will not have their licenses terminated so long as such parties remain in full compliance FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new revised versions of the GNU Free Documentation License from time to time Such new versions will be similar in spirit to the present version but may differ in detail to address new problems or concerns See http www gnu org copyleft Each version of the License is given a distinguishing version number If the Document specifies that a particular numbered version of this License or any later version applies to it you have the option of following the terms and conditions either of that specified version or of any later version that has been published not as a draft by the Free Software Foundation If the Document does not specify a version number of this License you may choose any version ever published not as a draft by the Free Software Foundation ADDENDUM How to use this License for your documents To use this License
185. e read by GDB not by traditional MIPS debuggers this enhancement is required to fully support C debugging These directives are primarily used by compilers not assembly language programmers 8 120 5 Directives to override the ISA level GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly set mipsn n should be a number from 0 to 5 or 32 3212 64 or 64r2 The values other than 0 make the assembler accept instructions for the corresponding ISA level from that point on in the assembly set mipsn affects not only which instructions are permitted but also how certain macros are expanded set mipsO restores the ISA level to its original level either the level you selected with command line options or the default for your configuration You can use this feature to permit specific RA000 instructions while assembling in 32 bit mode Use this directive with care The directive set mipsi6 puts the assembler into MIPS 16 mode in which it will assemble instructions for the MIPS 16 processor Use set nomips16 to return to normal 32 bit mode Traditional MIPS assemblers do not support this directive Chapter 8 Machine Dependent Features 143 8 120 6 Directives for extending MIPS 16 bit instructions By default MIPS 16 instructions are automatically extended to 32 bits when necessary The directive set noautoextend will turn this off When set noautoextend is in ef
186. e section register here defaults to Ads AT amp T foo 1 Intel foo This uses the value pointed to by foo as a memory operand Note that base and index are both missing but there is only one This is a syntactic exception Chapter 8 Machine Dependent Features 111 AT amp T Ags foo Intel gs foo This selects the contents of the variable foo with section register section being Yes Absolute as opposed to PC relative call and jump operands must be prefixed with If no is specified as always chooses PC relative addressing for jump call labels Any instruction that has a memory operand but no register operand must specify its size byte word long or quadruple with an instruction mnemonic suffix b w 1 or q respectively The x86 64 architecture adds an RIP instruction pointer relative addressing This addressing mode is specified by using rip as a base register Only constant offsets are valid For example AT amp T 1234 rip Intel rip 1234 Points to the address 1234 bytes past the end of the current instruction AT amp T symbol rip Intel rip symbol Points to the symbol in RIP relative way this is shorter than the default abso lute addressing Other addressing modes remain unchanged in x86 64 architecture except registers used are 64 bit instead of 32 bit 8 112 19 Handling of Jump I
187. e the logical line number line number must be an absolute expression The next line has that logical line number Therefore any other statements on the current line after a statement separator character are reported as on logical line number line number 1 One day as will no longer support this directive it is recognized only for compatibility with existing assembler programs Warning In the AMD29K configuration of as this command is not available use the synonym 1n in that context Even though this is a directive associated with the a out or b out object code formats as still recognizes it when producing COFF output and treats line as though it were the COFF 1n if it is found outside a def endef pair Inside a def line is instead one of the directives used by compilers to generate auxiliary symbol information for debugging 52 Using as 7 55 linkonce type Mark the current section so that the linker only includes a single copy of it This may be used to include the same section in several different object files but ensure that the linker will only include it once in the final output file The linkonce pseudo op must be used for each instance of the section Duplicate sections are detected based on the section name so it should be unique This directive is only supported by a few object file formats as of this writing the only object file format which supports it is the Portable Executable format us
188. e things the linker uses symbols to link and the debugger uses symbols to debug Warning as does not place symbols in the object file in the same order they were declared This may break some debuggers 5 1 Labels A label is written as a symbol immediately followed by a colon The symbol then represents the current value of the active location counter and is for example a suitable instruction operand You are warned if you use the same symbol to represent two different locations the first definition overrides any other definitions On the HPPA the usual form for a label need not be immediately followed by a colon but instead must start in column zero Only one label may be defined on a single line To work around this the HPPA version of as also provides a special directive label for defining labels more flexibly 5 2 Giving Symbols Other Values A symbol can be given an arbitrary value by writing a symbol followed by an equals sign followed by an expression see Chapter 6 Expressions page 37 This is equivalent to using the set directive See Section 7 77 set page 59 5 3 Symbol Names Symbol names begin with a letter or with one of _ On most machines you can also use in symbol names exceptions are noted in Chapter 8 Machine Dependencies page 67 That character may be followed by any string of digits letters dollar signs unless otherwise noted in Chapter 8 Machine Dependencies page
189. e use of the literal pool For information on the ARM or Thumb instruction sets see ARM Software Development Toolkit Reference Manual Advanced RISC Machines Ltd Chapter 8 Machine Dependent Features 83 8 105 CRIS Dependent Features 8 105 22 Command line Options The CRIS version of as has these machine dependent command line options The format of the generated object files can be either ELF or a out specified by the command line options emulation crisaout and emulation criself The default is ELF criself unless as has been configured specifically for a out by using the configura tion name cris axis aout There are two different link incompatible ELF object file variants for CRIS for use in environments where symbols are expected to be prefixed by a leading _ character and for environments without such a symbol prefix The variant used for GNU Linux port has no symbol prefix Which variant to produce is specified by either of the options underscore and no underscore The default is underscore Since symbols in CRIS a out objects are expected to have a _ prefix specifying no underscore when generating a out objects is an error Besides the object format difference the effect of this option is to parse register names differently see crisnous page 85 The no underscore option makes a register prefix mandatory The option pic must be passed to as in order
190. ear in either order If both apc and register are address registers and the size and scale are omitted then the first register is taken as the base register and the second as the index register 8 117 41 Floating Point Packed decimal P format floating literals are not supported Feel free to add the code The floating point formats generated by directives are these float Single precision floating point constants double Double precision floating point constants Chapter 8 Machine Dependent Features 131 extend double Extended precision long double floating point constants 8 117 42 680x0 Machine Directives In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives datal data2 even Skip This directive is identical to a data 1 directive This directive is identical to a data 2 directive This directive is a special case of the align directive it aligns the output to an even byte boundary This directive is identical to a space directive 8 117 43 Opcodes 8 117 43 1 Branch Improvement Certain pseudo opcodes are permitted for branch instructions They expand to the shortest branch instruction that reach the target Generally these mnemonics are made by substituting j for b at the start of a Motorola mnemonic The following table summarizes the pseudo operations A flags cases that are more fully described after the table
191. ed Feel free to add the code The floating point formats generated by directives are these Chapter 8 float double extend Ldouble Machine Dependent Features 137 Single precision floating point constants Double precision floating point constants Extended precision long double floating point constants 8 118 49 Opcodes 8 118 49 1 Branch Improvement Certain pseudo opcodes are permitted for branch instructions They expand to the shortest branch instruction that reach the target Generally these mnemonics are made by prepending j to the start of Motorola mnemonic These pseudo opcodes are not affected by the short branchs or force long branchs options The following table summarizes the pseudo operations Displacement Width 4 Options short branchs force long branchs 4 4 Op BYTE WORD BYTE WORD 4 AO bsr bsr lt pc rel gt lt error gt jsr lt abs gt bra bra lt pc rel gt lt error gt jmp lt abs gt jbsr bsr lt pc rel gt sr lt abs gt bsr lt pc rel gt sr abs jbra bra lt pc rel gt jmp lt abs gt bra lt pc rel gt jmp lt abs gt bXX bXX lt pc rel gt error bNX 3 jmp abs jbXX bXX lt pc rel gt bNX 3 bXX lt pc rel gt bNX 3 jmp abs jmp abs
192. ed at the same time and conflict the one that overrides a default behavior takes precedence over one that is the same as the default For example if the code density option is available the default is to select density instructions whenever possible So if the above is assembled with the no density flag which overrides the default all the generic ADD instructions result in ADD machine instructions If assembled with the density flag which is already the default the no density directive takes precedence and only one of the generic ADD instruc tions is optimized to be a ADD N machine instruction An underscore prefix identifying a specific opcode always takes precedence over directives and command line flags The following directives are available 8 133 10 1 density The density and no density directives enable or disable optimization of generic in structions into density instructions within the region See Section 8 133 8 1 Using Density Instructions page 193 begin no density end no density This optimization is enabled by default unless the Xtensa configuration does not support the code density option or the no density command line option was specified Chapter 8 Machine Dependent Features 197 8 133 10 2 relax The relax directive enables or disables relaxation within the region See Section 8 133 9 Xtensa Relaxation page 194 Note In the current implementation these directives also control wh
193. ed on Windows NT The type argument is optional If specified it must be one of the following strings For example linkonce same_size Not all types may be supported on all object file formats discard Silently discard duplicate sections This is the default one only Warn if there are duplicate sections but still keep only one copy same size Warn if any of the duplicates have different sizes same contents Warn if any of the duplicates do not have exactly the same contents 7 56 1n line number 1n is a synonym for line 7 57 mri val If val is non zero this tells as to enter MRI mode If val is zero this tells as to exit MRI mode This change affects code assembled until the next mri directive or until the end of the file See Section 2 8 MRI mode page 17 7 58 list Control in conjunction with the nolist directive whether or not assembly listings are generated These two directives maintain an internal counter which is zero initially list increments the counter and nolist decrements it Assembly listings are generated whenever the counter is greater than zero By default listings are disabled When you enable them with the a command line option see Chapter 2 Command Line Options page 15 the initial value of the listing counter is one 7 59 long expressions long is the same as int see Section 7 48 int page 50 Chapter 7 Assembler Directives 53 7 60 macro T
194. ed on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification Normal as macros should still work 8 101 2 2 Special Characters is the line comment character The character is permitted in identifiers but may not begin an identifier 8 101 2 3 Register Names General purpose registers are represented by predefined symbols of the form GRnnn for global registers or LRnnn for local registers where nnn represents a number between 0 and 127 written with no leading zeros The leading letters may be in either upper or lower case for example gr13 and LR7 are both valid register names You may also refer to general purpose registers by specifying the register number as the result of an expression prefixed with to flag the expression as a register number hhexpression where expression must be an absolute expression evaluating to a number between 0 and 255 The range 0 127 refers to global registers and the range 128 255 to local registers In addition as understands the following protected special purpose register names for the AMD 29K family vab chd pco ops chc pci cps rbp pc2 cfg tmc mmu cha tmr lru These unprotected special purpose register names are also recognized ipc alu fpe ipa bp inte ipb fc fps q cr exop 8 101 3 Floating Point The AMD 29K family uses IEEE floating point numbers Chapter 8 Machine Dependent Features 69
195. ee 44 desc symbol abs expression esses 44 O E 44 double flon ms sic co da ees ISR deeb eee ed 45 ejectus ib ea hee ad de dor uie ad 45 elS8L eee a Rete is 45 eliana extiende 45 end epa pe und ches ped oe ae dne pud eden epu ed en 45 endel gs P 45 A erede E 45 endif sese Rd vespa RE edad Peden ede 45 equ symbol eXxpressiO0l oiuiesde e br deren 46 equiv symbol expression essere 46 Clo A EE 46 enm s 46 o pu 46 fall expression leid dare ue ei iacere era acis 46 LALO SUEID 26423 dex dais dani Eee d nd ide 46 Till repeat size y value dac pe eed Res 47 float PLONUMS i2 enra E A RES 47 fune name Tabel 2i iive RAE MID DEDE AT global symbol globl symbol o oooooooooooo 47 Bidden names iaa a e E aca ER 48 hword expressions eek hn da 48 O 48 if absolute expression sreski ai 48 incbin file skip count 49 include file ca a ra naa a s 49 inb OXPESSSIODS 04 dele tia uu d e ooo 50 internal names eg Rad ry ees pro 50 itp symbol valu6S od dd aed e aun des dd 50 irpc symbol valUG6S c lem Rb Ree RR md 50 lcomm symbol length sede mh rm 51 A uoa tee PRA saci aia Pa edie 51 line Iine numbDer e rey nn bte he nn 51 linkonce typel l viene dae Ct tte rna 51 In 1ine number eek ees er en 52 Iri Valais exer uk ated red YU Und oh Sad BA d tt 52 M PP ms 52 lo
196. el conflicts or Wnp Do not produce warning messages when questionable parallel constructs are encountered The following options are available when as is configured for the Motorola 68000 series 1 Shorten references to undefined symbols to one word instead of two m68000 m68008 m68010 m68020 m68030 m68040 m68060 m68302 m68331 m68332 m68333 m68340 mcpu32 m5200 Specify what processor in the 68000 family is the target The default is normally the 68020 but this can be changed at configuration time m68881 m68882 mno 68881 mno 68882 The target machine does or does not have a floating point coprocessor The default is to assume a coprocessor for 68020 68030 and cpu32 Although the basic 68000 is not compatible with the 68881 a combination of the two can be specified since it s possible to do emulation of the coprocessor instructions with the main processor m68851 mno 68851 The target machine does or does not have a memory management unit co processor The default is to assume an MMU for 68020 and up For details about the PDP 11 machine dependent features options see Section 8 123 19 PDP 11 Options page 153 Chapter 1 Overview 7 mpic mno pic Generate position independent or position dependent code The default is mpic mall mall extensions Enable all instruction set extensions This is the default mno extensions Disable all instruction set ext
197. en dealing with a symbol that is not defined yet when a line is being assembled it will always use the long form If you need to force the assembler to use either the short or long form of the instruction you can append either s short or 1 long to it For example if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program you can write bra s foo Objdump and GDB will always append s or 1 to instructions which have both short and long forms 8 107 30 2 Sub Instructions The D30V assembler takes as input a series of instructions either one per line or in the special two per line format described in the next section Some of these instructions will be short form or sub instructions These sub instructions can be packed into a single instruction The assembler will do this automatically It will also detect when it should not pack instructions For example when a label is defined the next instruction will never be packaged with the previous one Whenever a branch and link instruction is called it will not be packaged with the next instruction so the return address will be valid Nops are automatically inserted when necessary If you do not want the assembler automatically making these decisions you can control the packaging and execution type parallel or sequential with the special execution symbols described in the next section 92 Using as 8 107
198. ences you can use in as strings Warning The HPPA version of string differs from the usual as definition it does not write a zero byte after copying str Stringz str Like string but appends a zero byte after copying str to object file subspa name params nsubspa name params Similar to space but selects a subsection name within the current section You may only specify params when you create a subsection in the first instance of subspa for this name If specified the list params declares attributes of the subsection identified by keywords The keywords recognized are quad expr quadrant for this subsection align expr alignment for beginning of this subsection a power of two access expr value for access rights field sort expr sorting order for this subspace in link code_only subsection contains only code unloadable subsection cannot be loaded into memory common subsection is common block dup_comm initialized data may have duplicate names or zero subsection is all zeros do not write in object file nsubspa always creates a new subspace with the given name even if one with the same name already exists version str Write str as version identifier in object code 8 110 6 Opcodes For detailed information on the HPPA machine instruction set see PA RISC Architec ture and Instruction Set Reference Manual HP 09740 9003
199. ensions mextension mno extension Enable or disable a particular instruction set extension mcpu Enable the instruction set extensions supported by a particular CPU and dis able all other extensions mmachine Enable the instruction set extensions supported by a particular machine model and disable all other extensions The following options are available when as is configured for a picoJava processor mb Generate big endian format output ml Generate little endian format output The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series m68hc11 m68hc12 m68hcs12 Specify what processor is the target The default is defined by the configuration option when building the assembler mshort Specify to use the 16 bit integer ABI mlong Specify to use the 32 bit integer ABI mshort double Specify to use the 32 bit double ABI mlong double Specify to use the 64 bit double ABI force long branchs Relative branches are turned into absolute ones This concerns conditional branches unconditional branches and branches to a sub routine 8 short branchs Do not turn relative branchs into absolute ones when the offset is out of range strict direct mode Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode print insn syntax Print the syntax of instruction in case of error
200. er 4rsp the stack pointer e the 8 extended registers 4r8 Ar15 e the 8 32 bit low ends of the extended registers 4r8d Aribd e the 8 16 bit low ends of the extended registers 4r8w Aribw e the 8 8 bit low ends of the extended registers Ar8b ri5b e the 4 8 bit registers sil Adil Abpl spl e the 8 debug registers 4db8 Adb15 e the 8 SSE registers Axmm8 xmm15 8 112 17 Instruction Prefixes Instruction prefixes are used to modify the following instruction They are used to repeat string instructions to provide section overrides to perform bus lock operations and to change operand and address sizes Most instructions that normally operate on 32 bit operands will use 16 bit operands if the instruction has an operand size prefix Instruction prefixes are best written on the same line as the instruction they act upon For example the scas scan string instruction is repeated with repne scas es jedi fal You may also place prefixes on the lines immediately preceding the instruction but this circumvents checks that as does with prefixes and will not work with all prefixes Here is a list of instruction prefixes c e Section override prefixes cs ds ss es fs gs These are automatically added by specifying using the section memory operand form for memory references e Operand Address size prefixes data16 and addr16
201. erands 107 1980 SUPPO o ot iespia ete acto b Soa 107 1386 syntax compatibility 107 180306 SUuppOott spioon genine nieten eR 107 i860 machine directivesS o ooooooooooo 116 1860 ODCOGeS u parsha neime cea trt E dees 116 1800 SUDPOT Divo circa 115 1960 architecture options 118 1960 branch recording 0 00 118 1960 ca11j pseudo opcode 120 i960 compare and jump expansions 120 1960 compare branch instructions 120 1960 floating point IEEE 119 i960 machine directivesS oooooooooooo 119 1960 opcodes ose erre ir ile 120 1960 Options Lite o da 118 1960 SUPPOP Gc iii er ped re Eb eee ted 118 ident Girective 2e dur atr RR 48 identifiers AMD 29K sssssseeees 68 identifiers ARM ziii iR a iba 81 identifiers MSP 430 0 0 oooocccooccocooo 151 3f difectlye aie eats wh sidere Rr nic Ed 48 IEC directives rra 48 3fdef direccionar Re EUR dea 48 ifeg directives eco ci ERR ERR EE 49 ifege directives eos ese inde lo 49 Tf ger direcllve e e Ro edes scene eters 49 Tf Pt dire llye ciere d ere roro prebere 49 ifle directive osse oe oce REED MER 49 DEVE CIP Chive Sinatra 49 3fnc CIPECHIVEs coles aia 49 ifndef directive ciar 49 afne directives dar bomen ove hate ees 49 ifnes GITECHVE cima adele seus Pure bb dre 49 ifnotdef direcilve 22cm ere 49 immediate character ARM
202. ery byte assembled into that section Because subsections are merely a convenience restricted to as there is no concept of a subsection location counter There is no way to directly manipulate a location counter but the align directive changes it and any label definition captures its current value The location counter of the section where statements are being assembled is said to be the active location counter 4 5 bss Section The bss section is used for local common variable storage You may allocate address space in the bss section but you may not dictate data to load into it before your program executes When your program starts running all the contents of the bss section are zeroed bytes The 1comm pseudo op defines a symbol in the bss section see Section 7 52 1comm page 51 Chapter 4 Sections and Relocation 31 The comm pseudo op may be used to declare a common symbol which is another form of uninitialized symbol see See Section 7 8 comm page 43 When assembling for a target which supports multiple sections such as ELF or COFF you may switch into the bss section and define symbols as usual see Section 7 76 section page 57 You may only assemble zero values into the section Typically the section will only contain symbol definitions and skip directives see Section 7 82 skip page 60 32 Using as Chapter 5 Symbols 33 5 Symbols Symbols are a central concept the programmer uses symbols to nam
203. es Target Alpha options mcpu mdebug no mdebug relax g Gsize F 32addr Target ARC options marc 5 6177 8 EB EL Target ARM options mepu processor extension march architecture textension mfpu floating point fromat mthumb EB EL mapcs 32 mapcs 26 mapcs float mapcs reentrant mthumb interwork moabi k Target CRIS options underscore no underscore pic N emulation criself emulation crisaout Target D10V options 0 Target D30V options O n N Target i386 options 32 64 n Target i960 options ACA ACA_A ACB ACC AKA AKB AKC AMC b no relax Target IP2K options mip2022 mip2022ext Target M32R options m32rx no warn explicit parallel conflicts Wl n pl Target M680X0 options 1 m68000 m68010 m68020 Target M68HC11 options m68hc11 m68hc12 m68hcs12 mshort mlong mshort double mlong double force long branchs short branchs strict direct mode print insn syntax print opcodes generate example Target MCORE options jsri2bsr sifilter relax mcpu 210 340 Target MIPS options nocpp EL EB n O optimization level g debug level G num KPIC call_shared non shared xgot membedded pic mabi ABI 32 n32 64 mfp32 mgp32 march CPU mtune CPU mip
204. es page 33 Normally you do not see such labels when debugging because they are intended for the use of programs like compilers that compose assembler programs not for your notice Normally both as and 1d discard such labels so you do not normally debug with them This option tells as to retain those L symbols in the object file Usually if you do this you also tell the linker 1d to preserve symbols whose names begin with L By default a local label is any label beginning with L but each target is allowed to redefine the local label prefix On the HPPA local labels begin with L 2 7 Configuring listing output listing The listing feature of the assembler can be enabled via the command line switch a see Section 2 1 a page 15 This feature combines the input source file s with a hex dump of the corresponding locations in the output object file and displays them as a listing file The format of this listing can be controlled by pseudo ops inside the assembler source see Section 7 58 List page 52 see Section 7 91 Title page 63 see Section 7 74 Sbttl page 57 see Section 7 69 Psize page 56 see Section 7 24 Eject page 45 and also by the following switches Chapter 2 Command Line Options 17 listing lhs width number Sets the maximum width in words of the first line of the hex byte dump This dump appears on the left hand side of the listing output listing lhs width2 nu
205. es esses 96 8 108 4 H8 300 Machine Directives 97 8 108 5 ODpGOdes isa Id nu oerte etes as PA TU 97 H8 500 Dependent Features o oooooccoocooomcmcoo 98 8 109 1 OPONS esiri er Ri idm AO ER 98 8 109 2 Syntax Rer ERE Per pH VE d 98 8 109 2 1 Special Characters 98 8 109 2 2 Register NamesS oooo oooocooooo 98 8 109 2 3 Addressing Modes 98 8 109 3 Floating Point 0 ee eee eee 99 8 109 4 H8 500 Machine Directives 99 8 109 5 Opcodes 0 cece cc ccc i rosiorii mapi 99 HPPA Dependent Features 000 00 eeeeee 100 8 110 1 NOUGS 4 1 o e emo ee Rr ce e ere ere 100 8 110 2 Options creed Ree hr t deae 100 8 110 3 Syntax vies ini oes rad lr eR E RR ed 100 8 10 4 Floating Pomb a seco er nnd 100 8 110 5 HPPA Assembler Directives 100 8 110 6 Opcodes cece cece essen 103 ESA 390 Dependent Features oooooooooccocco 104 GILT A ees obec cone Bee ae ae 104 SATS OPNS areires ai aiii eee Mala m ELE dU 104 SILIO Syntax 2e2leSbeddauedbed oues o UU Rd RE dius 104 Using as 8 112 8 113 8 114 8 115 8 116 8 117 8 111 10 Floating Point sues eese 105 8 111 11 ESA 390 Assembler Directives 105 SAILI Opcodes ise eee e erre 106 80386 Dependent Features oo ooooooooommoo 107 8 112 13 OPUS ecos cR dea 107 8 112 14 AT amp T Syntax versus Intel Syntax
206. ess GAS is explicitly configured with 64 bit environment support Av8plusa and Av9a enable the SPARC V9 instruction set with Ultra SPARC extensions xarch v8plus xarch v8plusa For compatibility with the Solaris v9 assembler These options are equivalent to Av8plus and Av8plusa respectively bump Warn whenever it is necessary to switch to another level If an architecture level is explicitly requested GAS will not issue warnings until that level is reached and will then bump the level as required except between incompatible levels 32 64 Select the word size either 32 bits or 64 bits These options are only available with the ELF object file format and require that the necessary BFD support has been included 8 128 6 Enforcing aligned data SPARC GAS normally permits data to be misaligned For example it permits the long pseudo op to be used on a byte boundary However the native SunOS and Solaris assemblers issue an error when they see misaligned data You can use the enforce aligned data option to make SPARC GAS also issue an error about misaligned data just as the SunOS and Solaris assemblers do Chapter 8 Machine Dependent Features 167 The enforce aligned data option is not the default because gcc issues misaligned data pseudo ops when it initializes certain packed data structures structures defined using the packed attribute You may have to assemble with GAS in order to initialize packed
207. ether assembler optimizations are performed making them equivalent to the generics and no generics directives begin no relax end no relax Relaxation is enabled by default unless the no relax command line option was spec ified 8 133 10 3 longcalls The longcalls directive enables or disables function call relaxation See Section 8 133 9 2 Function Call Relaxation page 194 begin no longcalls end no longcalls Call relaxation is disabled by default unless the longcalls command line option is specified 8 133 10 4 generics This directive enables or disables all assembler transformation including relaxation see Section 8 133 9 Xtensa Relaxation page 194 and optimization see Section 8 133 8 Xtensa Optimizations page 193 begin no generics end no generics Disabling generics is roughly equivalent to adding an underscore prefix to every opcode within the region so that every opcode is treated as a specific opcode See Section 8 133 7 1 Opcode Names page 192 In the current implementation of as built in macros are also disabled within a no generics region 8 133 10 5 literal The literal directive is used to define literal pool data i e read only 32 bit data accessed via L32R instructions literal label value value This directive is similar to the standard word directive except that the actual location of the literal data is determined by the assembler and linker not b
208. eved to indicate the offset from the CFA to the saved argument registers prologue n Indicate that the stack frame is set up and all registers have been spilled The argument n indicates whether and how the function uses the incoming procedure vector the address of the called function in 27 0 indicates that 27 is not used 1 indicates that the first two instructions of the function use 27 to perform a load of the GP register 2 indicates that 27 is used in some non standard way and so the linker cannot elide the load of the procedure vector during relaxation usepv function which Used to indicate the use of the 27 register similar to prologue but without the other semantics of needing to be inside an open ent end block The which argument should be either no indicating that 27 is not used or std indicating that the first two instructions of the function perform a GP load Chapter 8 Machine Dependent Features 75 One might use this directive instead of prologue if you are also using dwarf2 CFI directives gprel32 expression Computes the difference between the address in expression and the GP for the current object file and stores it in 4 bytes In addition to being smaller than a full 8 byte address this also does not require a dynamic relocation when used in a shared library t_floating expression Stores expression as an IEEE double precision value s_floating expression Stores expression as an IEEE sin
209. expressiOol leedgae Red Fried psg de 61 subsection NaMe sooo cirri ege rr hrec dns 62 En A cade Aha ied neon eae eae 62 bag structname 2000 ds te hr a hi od 63 text SUDSOCLIOD eoe dae wise deere bine ut as dun lip ades 63 title heading bes ded eed end mated he es 63 JUYDeuo tasse RE RR eR Rer eed Redde dua d 63 ulebi128 expression cepi s pira dtd Rs AR us dor s 64 Val addr i i oie ch eR ree Ek 64 version string secus pA ad ad ov A eia ees 64 vtable entry table offset les 00000 64 Vtable inherit child parent s sess 65 Weak names sucio nice exe Gad eine d oed redet RU a 65 Word expressionsus lo ss kasd eer Ra ees 65 Deprecated Directives ooooooooocooorommmmoo 65 Using as 8 Machine Dependent Features 67 8 101 AMD 29K Dependent Features 02 0000 68 S 101 1 Options oerte adds 68 8 101 2 Md a die die des eoe Rea eu 68 8 101 2 T Mattos iii is 68 8 101 2 2 Special Characters 68 8 101 2 3 Register Names o oooo oooocooo 68 8 101 3 Floating Point 0 0 eee eee eee 68 8 101 4 AMD 29K Machine Directives 68 8 101 5 Opcodes a sc s re base ebd a 69 8 102 Alpha Dependent Features 0 00 00 eee eee 70 8 102 0 Note cos tenet adie ERE Pes dag dad ERE 70 8 1027 OptlonS ii eee eats cede edd aa C eee 70 IA cei eae a ceeding dae bee t 70 8 102 8 1 Special Characters 7
210. f the symbol generated is not even an empty string It is a null pointer for compatibility Older assemblers used a null pointer so they didn t waste space in object files with empty strings The symbol s value is set to the location counter relocatably When your program is linked the value of this symbol is the address of the location counter when the stabd was assembled stabn type other desc value The name of the symbol is set to the empty string Stabs string type other desc value All five fields are specified 7 85 string str Copy the characters in str to the object file You may specify more than one string to copy separated by commas Unless otherwise specified for a particular machine the assembler marks the end of each string with a 0 byte You can use any of the escape sequences described in Section 3 6 1 1 Strings page 23 62 Using as 7 86 struct expression Switch to the absolute section and set the section offset to expression which must be an absolute expression You might use this as follows struct 0 fieldl struct fieldi 4 field2 struct field2 4 field3 This would define the symbol field1 to have the value 0 the symbol field2 to have the value 4 and the symbol field3 to have the value 8 Assembly would be left in the absolute section and you would need to use a section directive of some sort to change to some other section before further assembly 7 87 subse
211. fect any 32 bit instruction must be explicitly extended with the e modifier e g li e 4 1000 The directive set autoextend may be used to once again automatically extend instructions when necessary This directive is only meaningful when in MIPS 16 mode Traditional MIPS assemblers do not support this directive 8 120 7 Directive to mark data as an instruction The insn directive tells as that the following data is actually instructions This makes a difference in MIPS 16 mode when loading the address of a label which precedes instructions as automatically adds 1 to the value so that jumping to the loaded address will do the right thing 8 120 8 Directives to save and restore options The directives set push and set pop may be used to save and restore the current settings for all the options which are controlled by set The set push directive saves the current settings on a stack The set pop directive pops the stack and restores the settings These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro Traditional MIPS assemblers do not support these directives 8 120 9 Directives to control generation of MIPS ASE instructions The directive set mips3d makes the assembler accept instructions from the MIPS 3D Application Specific Extension from that point on in the assembl
212. ff mipslelf mipsbelf The first two do not alter the default endianness from that of the primary target for which the assembler was configured the others change the default to little or big endian as indicated by the b or 1 in the name Using EB or EL will override the endianness selection in any case This option is currently supported only when the primary target as is config ured for is a MIPS ELF or ECOFF target Furthermore the primary target or others specified with enable targets at configuration time must include support for the other format if both are to be available For example the Irix 5 configuration includes support for both Eventually this option will support more configurations with more fine grained control over the assembler s behavior and will be supported for more processors nocpp as ignores this option It is accepted for compatibility with the native tools trap no trap break no break Control how to deal with multiplication overflow and division by zero trap or no break which are synonyms take a trap exception and only work for Instruction Set Architecture level 2 and higher break or no trap also synonyms and the default take a break exception 6 n When this option is used as will issue a warning every time it generates a nop instruction from a macro The following options are available when as is configu
213. ffset from the current CFA register This is transformed to cfi_offset using the known displacement of the CFA register from the CFA This is often easier to use because the number will match the code it s annotating 7 17 cfi_window_save SPARC register window has been saved 7 18 cfi escape expression Allows the user to add arbitrary bytes to the unwind info One might use this to add OS specific CFI opcodes or generic CFI opcodes that GAS does not yet support 7 19 data subsection data tells as to assemble the following statements onto the end of the data subsection numbered subsection which is an absolute expression If subsection is omitted it defaults to zero 7 20 def name Begin defining debugging information for a symbol name the definition extends until the endef directive is encountered This directive is only observed when as is configured for COFF format output when producing b out def is recognized but ignored 7 21 desc symbol abs expression This directive sets the descriptor of the symbol see Section 5 5 Symbol Attributes page 35 to the low 16 bits of an absolute expression The desc directive is not available when as is configured for COFF output it is only for a out or b out object format For the sake of compatibility as accepts it but produces no output when configured for COFF Chapter 7 Assembler Directives 45 1 22 dim This directive is generated by compi
214. fied varies from system to system For the a29k arc hppa 1386 using ELF i860 132000 m68k m88k or32 s390 sparc tic4x tic80 and xtensa the first expression is the alignment request in bytes For example align 8 advances the location counter until it is a multiple of 8 If the location counter is already a multiple of 8 no change is needed For the tic54x the first expression is the alignment request in words For other systems including the i386 using a out format and the arm and strongarm it is the number of low order zero bits the location counter must have after advancement For example align 3 advances the location counter until it a multiple of 8 If the location counter is already a multiple of 8 no change is needed 42 Using as This inconsistency is due to the different behaviors of the various native assemblers for these systems which GAS must emulate GAS also provides balign and p2align directives described later which have a consistent behavior across all architectures but are specific to GAS 1 4 ascii string ascii expects zero or more string literals see Section 3 6 1 1 Strings page 23 sep arated by commas It assembles each string with no automatic trailing zero byte into consecutive addresses a asciz string asciz is just like ascii but each string is followed by a zero byte The z in asciz stands for zero 7 6 balign wl abs expr abs expr
215. for compatibility with older versions of as In future R may work this way When as is configured for COFF or ELF output this option is only useful if you use sections named text and data R is not supported for any of the HPPA targets Using R generates a warning from as 2 12 Display Assembly Statistics statistics Use statistics to display two statistics about the resources used by as the max imum amount of space allocated during the assembly in bytes and the total execution time taken for the assembly in CPU seconds 2 13 Compatible Output traditional format For some targets the output of as is different in some ways from the output of some existing assembler This switch requests as to use the traditional format instead For example it disables the exception frame optimizations which as normally does by default on gcc output 20 Using as 6 2 14 Announce Version v You can find out what version of as is running by including the option v which you can also spell as version on the command line 6 2 15 Control Warnings W warn no warn fatal warnings as should never give a warning or error message when assembling compiler output But programs written by people often cause as to give a warning that a particular assumption was made All such warnings are directed to the standard error file If you use the
216. g Standard matpcs This option specifies that the output generated by the assembler should be marked as supporting the Arm Thumb Procedure Calling Standard If enabled this option will cause the assembler to create an empty debugging section in the object file called arm atpcs Debuggers can use this to determine the ABI being used by mapcs float This indicates the the floating point variant of the APCS should be used In this variant floating point arguments are passed in FP registers rather than integer registers mapcs reentrant This indicates that the reentrant variant of the APCS should be used This variant supports position independent code EB This option specifies that the output generated by the assembler should be marked as being encoded for a big endian processor EL This option specifies that the output generated by the assembler should be marked as being encoded for a little endian processor k This option specifies that the output of the assembler should be marked as position independent code PIC moabi This indicates that the code should be assembled using the old ARM ELF conventions based on a beta release release of the ARM ELF specifications rather than the default conventions which are based on the final release of the ARM ELF specifications 8 104 18 Syntax 8 104 18 1 Special Characters The presence of a on a line indicates the start of a comment that extends to the end of the current l
217. g mode a0C disp 4d0 as though disp is a 32 bit value You may use the disp size default 16 option to tell as to instead assume that the displacement is 16 bits In this case as will assemble a0 disp d0 as though disp is a 16 bit value You may use the disp size default 32 option to restore the default behaviour Chapter 8 pcrel m68000 Machine Dependent Features 127 Always keep branches PC relative In the M680x0 architecture all branches are defined as PC relative However on some processors they are limited to word displacements maximum When as needs a long branch that is not available it normally emits an absolute jump instead This option disables this substitu tion When this option is given and no long branches are available only word branches will be emitted An error message will be generated if a word branch cannot reach its target This option has no effect on 68020 and other proces sors that have long branches see Section 8 117 43 1 Branch Improvement page 131 as can assemble code for several different members of the Motorola 680x0 family The default depends upon how as was configured when it was built normally the default is to assemble code for the 68020 microprocessor The following options may be used to change the default These options control which in structions and addressing modes are permitted The members of the 680x0 family are very similar For de
218. g these would require enhancing each object file format individually These are e global symbols in common section The m68k MRI assembler supports common sections which are merged by the linker Other object file formats do not support this as handles common sections by treating them as a single common symbol It permits local symbols to be defined within a common section but it can not support global symbols since it has no way to describe them e complex relocations The MRI assemblers support relocations against a negated section address and reloca tions which combine the start addresses of two or more sections These are not support by other object file formats e END pseudo op specifying start address The MRI END pseudo op permits the specification of a start address This is not supported by other object file formats The start address may instead be specified using the e option to the linker or in a linker script e IDNT ident and NAME pseudo ops The MRI IDNT ident and NAME pseudo ops assign a module name to the output file This is not supported by other object file formats 18 Using as ORG pseudo op The m68k MRI ORG pseudo op begins an absolute section at a given address This differs from the usual as org pseudo op which changes the location within the current section Absolute sections are not supported by other object file formats The address of a section may be assigned within a linker script There are so
219. general network using public has access to download anonymously at no charge using public standard network protocols If you use the latter option you must take reasonably prudent steps when you begin distribution of Opaque copies in quantity to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy directly or through your agents or retailers of that edition to the public It is requested but not required that you contact the authors of the Document well before redistributing any large number of copies to give them a chance to provide you with an updated version of the Document 4 MODIFICATIONS You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above provided that you release the Modified Version under precisely this License with the Modified Version filling the role of the Document thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it In addition you must do these things in the Modified Version A Use in the Title Page and on the covers if any a title distinct from that of the Document and from those of previous versions which should if there were any be listed in the History section of the Document You may use the same title as a previous version if the original publisher of that version gives permission B List on the
220. gle precision value f floating expression Stores expression as a VAX F format value g floating expression Stores expression as a VAX G format value d floating expression Stores expression as a VAX D format value set feature Enables or disables various assembler features Using the positive name of the feature enables while using nofeature disables at macro move reorder volatile Indicates that macro expansions may clobber the assembler tem porary at or 28 register Some macros may not be expanded without this and will generate an error message if noat is in effect When at is in effect a warning will be generated if at is used by the programmer Enables the expansion of macro instructions Note that variants of real instructions such as br label vs br 31 1abel are considered alternate forms and not macros These control whether and how the assembler may re order instruc tions Accepted for compatibility with the OSF 1 assembler but as does not do instruction scheduling so these features are ignored The following directives are recognized for compatibility with the OSF 1 assembler but are ignored proc reguse option ugen alias aproc livereg aent eflag noalias 76 Using as 8 102 11 Opcodes For detailed information on the Alpha machine instruction set see the Alpha Architec ture Handbook located at ftp ftp digital com pub Digital info semiconductor literature alph
221. gnored om VAX cs ieee tudes ERE Re 180 T ignored on VAX sess eR DEP RR 180 Mo pce dert cs bad PR M PR a doe pads 20 V redundant on VAX uuuuuuuus 180 So hernani e parra ure eer Peds EEA 20 un 20 warn explicit parallel conflicts option MB2RX ir Abe hand Pek ino 123 Wnp option M32RX 2 00 0 123 Wp option M32RX cocino cetera cede ee 123 wsigned_overflow command line option V850 is HM 184 wunsigned overflow command line option V850 rS 184 x command line option MMIX 144 gt Symbol 4 ceased onpeeizrteche e r Aa 35 high directive M32R ino e ERR 123 o 9 eet oP RES Iun de pO a ee 143 low directive M32R o oo oooooooo o o 123 ltorg directive ARM ooo ocoomcommo o 81 VOU aee pru bae A ire E E des E ge e qoid 13 param on HPPA 2 pP PIE ENS 101 pool directive ARM oooo ooommmmoo 82 Set AUTOSXTOMA cuco ase 143 SOU MANX rr EY er EE EEEREN Pers 143 Set mips3d e I gua e RE RE PUER 143 Set MP an e DIG rre 142 set noautoextend sss esee lees 143 Set NOMAN berrerosi PP LCS REY AE Y ES 143 set nomips9Od pes a e 143 JSet POP vanas e NO laeua 143 SO pusb cii2esx B RIbe 4e E E ERES 143 Shigh directive M32R o ooo mooooo o 124 850 directive V850 ooooooooomomoo 187 v850e directive V8B50 oooooooooooo 187 v850e1 directive V85D o ocooooco ooooo o 187 Mabel ias da
222. h a null byte set symbol value This directive creates a symbol named symbol which is an alias for another sym bol possibly not yet defined This should not be confused with the mnemonic set which is a legitimate M88K instruction def symbol value This directive is synonymous with set and is presumably provided for com patibility with other M88K assemblers bss symbol length align Reserve length bytes in the bss section for a local symbol aligned to the power of two specified by align length and align must be positive absolute expressions This directive differs from 1comm only in that it permits you to specify an alignment See Section 7 52 1comm page 51 Chapter 8 Machine Dependent Features 139 8 120 MIPS Dependent Features GNU as for MIPS architectures supports several different MIPS processors and MIPS ISA levels I through V MIPS32 and MIPS64 For information about the MIPS instruction set see MIPS RISC Architecture by Kane and Heindrich Prentice Hall For an overview of MIPS assembly conventions see Appendix D Assembly Language Programming in the same work 8 120 2 Assembler options The MIPS configurations of GNU as support these special options G num This option sets the largest size of an object that can be referenced implicitly with the gp register It is only accepted for targets that use ECOFF format The default value is 8 EB EL Any MIPS configuration of as can select big end
223. h defintion gets 15 as well So for example the first 1 is named L1C B1 the 44th 3 is named L3C B44 Dollar Local Labels as also supports an even more local form of local labels called dollar labels These labels go out of scope ie they become undefined as soon as a non local label is defined Thus they remain valid for only a small region of the input source code Normal local labels by contrast remain in scope for the entire file or until they are redefined by another occurrence of the same local label Dollar labels are defined in exactly the same way as ordinary local labels except that instead of being terminated by a colon they are terminated by a dollar sign eg 55 Chapter 5 Symbols 35 They can also be distinguished from ordinary local labels by their transformed name which uses ASCII character 001 control A as the magic character to distinguish them from ordinary labels Thus the 5th defintion of 6 is named L6C 45 5 4 The Special Dot Symbol The special symbol refers to the current address that as is assembling into Thus the expression melvin long defines melvin to contain its own address Assigning a value to is treated the same as a org directive Thus the expression 4 is the same as saying space 4 5 5 Symbol Attributes Every symbol has as well as its name the attributes Value and Type Depending on output format symbols can
224. h of these pseudo operations expands to a single branch instruction However if a word branch is not sufficient no long branches are available and the pcrel option is not given as issues a longer code fragment in terms of NX the opposite condition to XX For example under these conditions jXX foo gives bNXs oof jmp foo oof The full family of pseudo operations covered here is dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt Motorola dbXX instructions allow word displacements only When a word displacement is sufficient each of these pseudo operations expands to the cor responding Motorola instruction When a word displacement is not sufficient and long branches are available when the source reads dbXX foo as emits dbXX ooi bras oo2 ooi bral foo 002 If however long branches are not available and the pcrel option is not given as emits dbXX ooi bras oo2 oo1 jmp foo 002 This family includes fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun Each of these pseudo operations always expands to a single Motorola coproces sor branch instruction word or long All Motorola coprocessor branch instruc tions allow both word and long displacements 8 117 43 2 Special Characters The immediate character is for Sun compati
225. he mad and maduw instruction and to not schedule nop instructions around accesses to the HI and LO registers no m4650 turns off this option m3900 no m3900 m4100 no m4100 For each option mnnnn generate code for the MIPS Rnnnn chip This tells the assembler to accept instructions specific to that chip and to schedule for that chip s hazards march cpu Generate code for a particular MIPS cpu It is exactly equivalent to mcpu except that there are more value of cpu understood Valid cpu value are 6 Chapter 8 Machine Dependent Features 141 mtune cpu mabi abi nocpp 2000 3000 3900 4000 4010 4100 4111 vr4120 vr4130 vr4181 4300 4400 4600 4650 5000 rm5200 rm5230 rm5231 rm5261 rm5721 vr5400 vr5500 6000 rm7000 8000 rm9000 10000 12000 mips32 4k sb1 Schedule and tune for a particular MIPS cpu Valid cpu values are identical to march cpu Record which ABI the source code uses The recognized arguments are 32 n32 064 64 and eabi This option is ignored It is accepted for command line compatibility with other assemblers which use it to turn off C style preprocessing With GNU as there is no need for nocpp because the GNU assembler itself never runs the C preprocessor construct floats no construct floats The no construct floats option disables the construction of double width flo
226. he commands macro and endm allow you to define macros that generate assembly output For example this definition specifies a macro sum that puts a sequence of numbers into memory macro sum from 0 to 5 long from if to from sum from i to endif endm With that definition SUM 0 5 is equivalent to this assembly input long long long long long long oP WNF oO macro macname macro macname macargs Begin the definition of a macro called macname If your macro definition re quires arguments specify their names after the macro name separated by com mas or spaces You can supply a default value for any macro argument by following the name with deflt For example these are all valid macro statements macro comm Begin the definition of a macro called comm which takes no argu ments macro plus1 p pl macro plusi p pl Either statement begins the definition of a macro called plus1 which takes two arguments within the macro definition write Ap or Ap1 to evaluate the arguments macro reserve_str p1 0 p2 Begin the definition of a macro called reserve_str with two argu ments The first argument has a default value but not the second After the definition is complete you can call the macro either as reserve_str a b with p1 evaluating to a and p2 evaluating to b or as reserve_str b with p1 evaluating as the default in this case 0 an
227. he source program might be necessary to interpret the expression but the second pass is currently not implemented as aborts with an error message in this situation 6 1 Empty Expressions An empty expression has no value it is just whitespace or null Wherever an absolute expression is required you may omit the expression and as assumes a value of absolute 0 This is compatible with other assemblers 6 2 Integer Expressions An integer expression is one or more arguments delimited by operators 6 2 1 Arguments Arguments are symbols numbers or subexpressions In other contexts arguments are sometimes called arithmetic operands In this manual to avoid confusing them with the instruction operands of the machine language we use the term argument to refer to parts of expressions only reserving the word operand to refer only to machine instruction operands Symbols are evaluated to yield section NNN where section is one of text data bss absolute or undefined NNN is a signed 2 s complement 32 bit integer Numbers are usually integers A number can be a flonum or bignum In this case you are warned that only the low order 32 bits are used and as pretends these 32 bits are an integer You may write integer manipulating instructions that act on exotic constants compatible with other assemblers Subexpressions are a left parenthesis C followed by an integer expression followed by a right parenthesis
228. hen the assembler is in unsegmented mode specified with the unsegm directive an address takes up one word 16 bit sized register When the assembler is in segmented mode specified with the segm directive a 24 bit address takes up a long 32 bit register See Section 8 130 22 Assembler Directives for the Z8000 page 179 for a list of other Z8000 specific assembler directives 8 130 20 Options as has no additional command line options for the Zilog Z8000 family 8 130 21 Syntax 8 130 21 1 Special Characters I is the line comment character You can use instead of a newline to separate statements 8 130 21 2 Register Names The Z8000 has sixteen 16 bit registers numbered 0 to 15 You can refer to different sized groups of registers by register number with the prefix r for 16 bit registers rr for 32 bit registers and rq for 64 bit registers You can also refer to the contents of the first eight of the sixteen 16 bit registers by bytes They are named rnh and rn1 byte registers r01 rOh rih ril r2h r21 r3h r31 r4h r41 r5h r51 r6h r61 r7h rT71 word registers rO ri r2 r3 r4 rb r6 17 r8 r9 r10 rit r12 r13 r14 ris long word registers rr0 rr2 rr4 rr6 rr8 rr 10 rri2 rr14 quad word registers rq0 rq4 rq8 rqi2 8 130 21 3 Addressing Modes as understands the following addressing modes for the Z8000 rn Register direct Orn Indirect register Chapter 8 Machine Dependent Features 179
229. hen the instructions must be exactly as specified in the assembly source text section literals no text section literals With text section literals literal pools are interspersed in the text section The default is no text section literals which places literals in a separate section in the output file target align no target align Enable or disable automatic alignment to reduce branch penalties at the expense of some code density The default is target align longcalls no longcalls Enable or disable transformation of call instructions to allow calls across a greater range of addresses The default is no longcalls 1 1 Structure of this Manual This manual is intended to describe what you need to know to use GNU as We cover the syntax expected in source files including notation for symbols constants and expressions the directives that as understands and of course how to invoke as 12 Using as This manual also describes some of the machine dependent features of various flavors of the assembler On the other hand this manual is not intended as an introduction to programming in assembly language let alone programming in general In a similar vein we make no attempt to introduce the machine architecture we do not describe the instruction set standard mnemonics registers or addressing modes that are standard to a particular archi tecture You may want to consult the manufacturer
230. i 23 word modifier D1OV 4 90 opcode prefix sse sie dae rsen 192 216 V doublequote character 00005 24 AN character nani dit 24 b backspace character 0 00000 eee 24 ddd octal character code 004 24 f formfeed character 0 eee eee 24 n newline character 000 eee ee eee 24 Vr carriage return character 24 NE bab a crisol dada o 24 xd hex character code o oo o ooo o 24 1 16 bit code 1386 rerit 112 2 20K Supports citrico e dad 68 2byte directive ARC oooooccococmccccc 78 3 3byte directive ARC oooooooccommccmcm 78 SD NOW 138604 wid vr Hee Ie RI REPE DES 112 3DNowl 80 Dd ocio bo Dai 112 4 430 SU ppotb li lore epe RRRRRREREMCSe REL 151 4byte directive ARC ooooooooocccrcccooo 78 lw 13 a out symbol attributes o o 35 A_DIR environment variable TIC54X 168 ABI options SH64 creber expen 163 abort directive isis pre dae 41 ABORT directive said re EM NAH eerie 41 absolute section lseese esee 28 ADDI instructions relaxation 195 addition permitted arguments 38 Addressess sies os da Dandaka e 37 addresses format of 00 c eee ee eee eee 28 addressing modes D1IOV 89 addressing modes D30V 94 addressing modes
231. ian or little endian output at run time unlike the other GNU development tools which must be configured for one or the other Use EB to select big endian output and EL for little endian mipsi mips2 mips3 mips4 mipsb5 mips32 mips32r2 mips64 mips64r2 Generate code for a particular MIPS Instruction Set Architecture level mipsi corresponds to the R2000 and R3000 processors mips2 to the R6000 processor mips3 to the R4000 processor and mips4 to the R8000 and R10000 processors mips5 mips32 mips32r2 mips64 and mips64r2 correspond to generic MIPS V MIPS32 MIPS32 RELEASE 2 MIPS64 and MIPS64 RELEASE 2 ISA processors respectively You can also switch instruction sets during the assembly see Section 8 120 5 MIPS ISA page 142 mgp32 mfp32 Some macros have different expansions for 32 bit and 64 bit registers The register sizes are normally inferred from the ISA and ABI but these flags force a certain group of registers to be treated as 32 bits wide at all times mgp32 controls the size of general purpose registers and mfp32 controls the size of floating point registers On some MIPS variants there is a 32 bit mode flag when this flag is set 64 bit instructions generate a trap Also some 32 bit OSes only save the 32 bit registers on a context switch so it is essential never to use the 64 bit registers 140 Using as
232. ign no longcalls a cdhlimns D Turn on listings in any of a variety of ways ac omit false conditionals ad omit debugging directives ah include high level source al include assembly am include macro expansions an omit forms processing as include symbols file set the name of the listing file 6 You may combine these options for example use aln for assembly listing without forms processing The file option if used must be the last one By itself a defaults to ahls Ignored This option is accepted for script compatibility with calls to other assemblers defsym sym value f gstabs gstabs Define the symbol sym to be value before assembling the input file value must be an integer constant As in C a leading Ox indicates a hexadecimal value and a leading 0 indicates an octal value fast skip whitespace and comment preprocessing assume source is compiler output Generate stabs debugging information for each assembler line This may help debugging assembler code if the debugger can handle it Generate stabs debugging information for each assembler line with GNU exten sions that probably only gdb can handle and that could make other debuggers crash or refuse to read your program This may help debugging assembler code Currently the only GNU extension is the location of the current working directory at assembling time 4 Using a
233. imum of 16 The syntax for comm differs slightly on the HPPA The syntax is symbol comm length symbol is optional 6 9 cfi startproc cfi startproc is used at the beginning of each function that should have an entry in eh frame It initializes some internal data structures and emits architecture dependent initial CFI instructions Don t forget to close the function by cfi_endproc 7 10 cfi_endproc cfi_endproc is used at the end of a function where it closes its unwind entry previously opened by cfi_startproc and emits it to eh_frame 7 11 cfi def cfa register offset cfi_def_cfa defines a rule for computing CFA as take address from register and add offset to it 7 12 cfi_def_cfa_register register cfi_def_cfa_register modifies a rule for computing CFA From now on register will be used instead of the old one Offset remains the same 7 13 cfi def cfa offset offset cfi def cfa offset modifies a rule for computing CFA Register remains the same but offset is new Note that it is the absolute offset that will be added to a defined register to compute CFA address 44 Using as 7 14 cfi_adjust_cfa_offset offset Same as cfi_def_cfa_offset but offset is a relative value that is added substracted from the previous offset 7 15 cfi_offset register offset Previous value of register is saved at offset offset from CFA 7 16 cfi_rel_offset register offset Previous value of register is saved at offset o
234. ine If a 4 appears as the first character of a line the whole line is treated as a comment Chapter 8 Machine Dependent Features 81 The character can be used instead of a newline to separate statements Either or can be used to indicate immediate operands TODO Explain about data modifier on symbols 8 104 18 2 Register Names TODO Explain about ARM register naming and the predefined names 8 104 19 Floating Point The ARM family uses IEEE floating point numbers 8 104 20 ARM Machine Directives align expression expression This is the generic align directive For the ARM however if the first argument is zero ie no alignment is needed the assembler will behave as if the argument had been 2 ie pad to the next four byte boundary This is for compatibility with ARM s own assembler name req register name This creates an alias for register name called name For example foo req rO code 16132 This directive selects the instruction set being generated The value 16 selects Thumb with the value 32 selecting ARM thumb This performs the same action as code 16 arm This performs the same action as code 32 force thumb This directive forces the selection of Thumb instructions even if the target processor does not support those instructions thumb func This directive specifies that the following symbol is the name of a Thumb en coded function This information is necessary i
235. ine Dependent Features 155 8 123 19 4 Machine Model Options These options enable the instruction set extensions supported by a particular machine model and disables all other extensions m11 03 Same as mkd11f m11 04 Same as mkd11d m11 05 m11 10 Same as mkd11b m11 15 m11 20 Same as mka11 m11 21 Same as mti1 m11 23 m11 24 Same as mf11 m11 34 Same as mkd11e m11 34a Ame as mkdile mfpp m11 35 m11 40 Same as mkdi11a m11 44 Same as mkd11z m11 45 m11 50 m11 55 m11 70 Same as mkb11 m11 53 m11 73 m11 83 m11 84 m11 93 m11 94 Same as mj11 m11 60 Same as mkd11k 8 123 20 Assembler Directives The PDP 11 version of as has a few machine dependent assembler directives bss Switch to the bss section even Align the location counter to an even number 8 123 21 PDP 11 Assembly Language Syntax as supports both DEC syntax and BSD syntax The only difference is that in DEC syntax a character is used to denote an immediate constants while in BSD syntax the character for this purpose is eneral purpose registers are named r0 through r7 Mnemonic alternatives for r6 and r7 are sp and pc respectively Floating point registers are named acO through ac3 or alternatively fro through fr3 Comments are started with a or a character and extend to the end of the line FIXME clash with immediates 156 Using as 8 123 22 Instruction Naming Som
236. ing point pairs mtrx0 through mtrx48 multiples of 16 only for 4x4 matrices of single precision floating point registers pc for the program counter and fpscr for the floating point status and control register You can also refer to the control registers by the mnemonics sr ssr pssr intevt expevt pexpevt tra spc pspc resvec vbr tea dcr kcr0 keri ctc and usr 8 127 2 3 Addressing Modes SH64 operands consist of either a register or immediate value The immediate value can be a constant or label reference or portion of a label reference as in this example movi 4 r2 pt function tr4 movi function gt gt 16 amp 65535 r0 shori function 65535 rO 1d 1 r0 4 r0 Instruction label references can reference labels in either SHmedia or SHcompact To differentiate between the two labels in SHmedia sections will always have the least signifi cant bit set i e they will be odd which SHcompact labels will have the least significant bit reset i e they will be even If you need to reference the actual address of a label you can use the datalabel modifier as in this example long function long datalabel function In that example the first longword may or may not have the least significant bit set depending on whether the label is an SHmedia label or an SHcompact label The second longword will be the ac
237. ing the no density directive see Section 8 133 10 1 density page 196 It is a good idea not to use the density instructions directly The assembler will auto matically select dense instructions where possible If you later need to avoid using the code density option you can disable it in the assembler without having to modify the code 8 133 8 2 Automatic Instruction Alignment The Xtensa assembler will automatically align certain instructions both to optimize performance and to satisfy architectural requirements When the target align command line option is enabled see Section 8 133 6 Com mand Line Options page 191 the assembler attempts to widen density instructions pre ceding a branch target so that the target instruction does not cross a 4 byte boundary Similarly the assembler also attempts to align each instruction following a call instruction If there are not enough preceding safe density instructions to align a target no widening will be performed This alignment has the potential to reduce branch penalties at some expense in code size The assembler will not attempt to align labels with the prefixes Ln and LM since these labels are used for debugging information and are not typically branch targets The LOOP family of instructions must be aligned on either a 1 or 2 mod 4 byte boundary The assembler knows about this restriction and inserts the minimal number of 2 or 3 byte no op instructions to satisfy it When no o
238. ing variants of if are also supported ifdef symbol Assembles the following section of code if the specified symbol has been defined Note a symbol which has been referenced but not yet defined is considered to be undefined ifc stringl string2 Assembles the following section of code if the two strings are the same The strings may be optionally quoted with single quotes If they are not quoted the first string stops at the first comma and the second string stops at the end of the line Strings which contain whitespace should be quoted The string comparison is case sensitive Chapter 7 Assembler Directives 49 ifeq absolute expression Assembles the following section of code if the argument is zero ifeqs string1 string2 Another form of ifc The strings must be quoted using double quotes ifge absolute expression Assembles the following section of code if the argument is greater than or equal to zero ifgt absolute expression Assembles the following section of code if the argument is greater than zero ifle absolute expression Assembles the following section of code if the argument is less than or equal to Zero iflt absolute expression Assembles the following section of code if the argument is less than zero ifnc stringl string2 Like ifc but the sense of the test is reversed this assembles the following section of code if the two strings are not the same ifndef symbol ifnotdef symbol Assembles the fol
239. instructions 0ooocoocccooooccoo o 87 DION SUPpOTbais susi i id 87 DIOV 8yniax eerror ida derie rinti 87 D30V addressing modes 94 I930V floating polht oce tebeer e 94 D30V Guarded Execution 93 D30V line comment character 92 D380 BODS 5a eon rer Fe tret pps hte p etie peers 5 D30V nops after 32 bit multiply 5 D30V opcode summary 94 D30V optimization a2 29 eee pe Eme ex Y 5 DION iopllonDs erfecI9 R acre tends 91 DION registers miii patin RE RR Ye 93 D30V size modifierS o oooooocoooo o 91 D30V sub instruction ordering 92 D30V sub instructions lesse eee 91 ID30V SUpDOEFls sesionar 91 DION syntax i sje pr sar are hr eder aos 91 data alignment on SPARC sssss 166 data and text sections joining 19 data directive ssec Feed deter hr 44 data directive TIC54X 172 Gata sectione cias nedre a RR Rr red bis 28 datal directive M680x0 ooo o oooooo o o 131 data2 directive M680x0 o ooooo ooooooo o t31 datalabel SH64 cooperar 164 dbpc register V850 oooooooomoooooo 187 dbpsw register V8B5DD oooooooooooooooo 187 debuggers and symbol order 33 debugging COFF symbols 44 DEC SYNTAX cols renew e p edd eae ERPUS 155 decimal integers s t ree rh 25 def directive sse c ub ag Ti EIL
240. ion rs6000 and hp300hpux host ports updated know assertions and made them work much other reorganization cleanup and lint Ken Raeburn wrote the high level BFD interface code to replace most of the code in format specific I O modules The original VMS support was contributed by David L Kashtan Eric Youngdale has done much work with it since The Intel 80386 machine description was written by Eliot Dresselhaus Minh Tran Le at IntelliCorp contributed some AIX 386 support The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science Keith Knowles at the Open Software Foundation wrote the original MIPS back end tc mips c tc mips h and contributed Rose format support which hasn t been merged in yet Ralph Campbell worked with the MIPS code to support a out format Support for the Zilog Z8k and Renesas H8 300 and H8 500 processors tc z8k tc h8300 tc h8500 and IEEE 695 object file format obj ieee was written by Steve Chamberlain of Cygnus Support Steve also modified the COFF back end to use BFD for some low level operations for use with the H8 300 and AMD 29k targets John Gilmore built the AMD 29000 support added include support and simplified the configuration of which versions accept which directives He updated the 68k machine description so that Motorola s opcodes always produced fixed size instructions
241. ion on the left first lt Sequential with instruction on the right first H Parallel The D10V syntax allows either one instruction per line one instruction per line with the execution symbol or two instructions per line For example abs al gt abs rO Execute these sequentially The instruction on the right is in the right container and is executed second abs r0 lt abs al Execute these reverse sequentially The instruction on the right is in the right container and is executed first ld2w r2 r8 mac a0 r0 r7 Execute these in parallel 1d2w r2 r8 mac a0 r0 r7 Two line format Execute these in parallel ld2w r2 r8 mac a0 r0 r7 Two line format Execute these sequentially Assembler will put them in the proper containers ld2w r2 r8 gt mac a0 r0 r7 Two line format Execute these sequentially Same as above but second in struction will always go into right container Since has no special meaning you may use it in symbol names Chapter 8 Machine Dependent Features 89 8 106 26 4 Register Names You can use the predefined symbols ro through r15 to refer to the D10V registers You can also use sp as an alias for r15 The accumulators are a0 and ai There are special register pair names that may optionally be used in opcodes that require even numbered registers Register names are not case sensitive Register Pairs rO ri r2 r3 r4 r5 r6 r7 r8 r9 ri
242. irective replaces the current section and subsection The replaced section and subsection are pushed onto the section stack See the contents of the gas testsuite directory gas testsuite gas elf for some examples of how this directive and the other section stack directives work 7 77 set symbol expression Set the value of symbol to expression This changes symbol s value and type to conform to expression If symbol was flagged as external it remains flagged see Section 5 5 Symbol Attributes page 35 You may set a symbol many times in the same assembly If you set a global symbol the value stored in the object file is the last value stored into it The syntax for set on the HPPA is symbol set expression 7 78 short expressions Short is normally the same as word See Section 7 99 word page 65 In some configurations however short and word generate numbers of different lengths see Chapter 8 Machine Dependencies page 67 7 79 single flonums This directive assembles zero or more flonums separated by commas It has the same effect as float The exact kind of floating point numbers emitted depends on how as is configured See Chapter 8 Machine Dependencies page 67 60 Using as 7 80 size This directive is used to set the size associated with a symbol COFF Version For COFF targets the size directive is only permitted inside def endef pairs It is used like this size expression
243. is not the default ABI depends on the ISA with SHmedia defaulting to 64 bit and SHcompact defaulting to 32 bit Note that the abi pseudo op is not permitted if the ABI is not specified on the command line When the ABI is specified on the command line any abi pseudo ops in the source must match it shcompact const crange Emit code range descriptors for constants in SHcompact code sections no mix Disallow SHmedia code in the same section as constants and SHcompact code no expand Do not expand MOVI PT PTA or PTB instructions expand pt32 With abi 64 expand PT PTA and PTB instructions to 32 bits only 8 127 2 Syntax 8 127 2 1 Special Characters 1 is the line comment character You can use instead of a newline to separate statements Since has no special meaning you may use it in symbol names 8 127 2 2 Register Names You can use the predefined symbols ro through r63 to refer to the SH64 general regis ters cr0 through cr63 for control registers trO through tr7 for target address registers fro through fr63 for single precision floating point registers dro through dr62 even numbered registers only for double precision floating point registers vO through fv60 164 Using as multiples of four only for single precision floating point vectors fp0 through fp62 even numbered registers only for single precision float
244. is not required for certain configurations notably sun3 The register prefix optional option may be used to permit omitting the even for configurations for which it is normally required If this is done it will generally be impossible to refer to C variables and functions with the same names as register names bitwise or Normally the character is treated as a comment character which means that it can not be used in expressions The bitwise or option turns into a normal character In this mode you must either use C style comments or start comments with a character at the beginning of a line base size default 16 base size default 32 If you use an addressing mode with a base register without specifying the size as will normally use the full 32 bit value For example the addressing mode a0 d0 is equivalent to Za0 dO 1 You may use the base size default 16 option to tell as to default to using the 16 bit value In this case a0 d0 is equivalent to a0 4d0 w You may use the base size default 32 option to restore the default behaviour disp size default 16 disp size default 32 If you use an addressing mode with a displacement and the value of the dis placement is not known as will normally assume that the value is 32 bits For example if the symbol disp has not been defined as will assemble the ad dressin
245. ister Names You can use the predefined symbols r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 and r15 to refer to the SH registers The SH also has these control registers pr procedure register holds return address pc program counter mach macl high and low multiply accumulator registers sr status register gbr global base register vbr vector base register for interrupt vectors Chapter 8 Machine Dependent Features 161 8 126 2 3 Addressing Modes as understands the following addressing modes for the SH Rn in the following refers to any of the numbered registers but not the control registers Rn Register direct ORn Register indirect Rn Register indirect with pre decrement Rn Register indirect with post increment disp Rn Register indirect with displacement RO Rn Register indexed disp GBR GBR offset RO GBR GBR indexed addr disp PC PC relative address for branch or for addressing memory The as implemen tation allows you to use the simpler form addr anywhere a PC relative address is called for the alternate form is supported for compatibility with other as semblers imm Immediate data 8 126 3 Floating Point The SH family has no hardware floating point but the float directive generates IEEE floating point numbers for compatibility with other development tools
246. ive load 72 Using as lituse_jsr N Used with a register branch format instruction e g jsr to indicate that the literal is used for a call During relaxation the code may be altered to use a direct branch e g bsr lituse_bytoff N Used with a byte mask instruction e g extb1 to indicate that only the low 3 bits of the address are relevant During relaxation the code may be altered to use an immediate instead of a register shift lituse_addr N Used with any other instruction to indicate that the original address is in fact used and the original 1dq instruction may not be altered or deleted This is useful in conjunction with lituse_jsr to test whether a weak symbol is defined ldq 27 f00 29 literal 1 beq 27 is_undef lituse_addr 1 jsr 26 27 foo lituse_jsr 1 lituse_tlsgd N Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the thread local storage variable whose descriptor was loaded with tlsgd N lituse tlsldm N Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the base of the thread local storage block for the current module The descriptor for the module must have been loaded with tlsldm N gpdisp N Used with 1dah and 1da to load the GP from the current address a la the 1dgp macro The source register for the 1dah instruction must co
247. ix Operator eddie eee edad whe oT 6 2 4 Infix Operators 0 cece eee eee 38 7 Assembler DirectivesS 41 GA ALO isa a a Ae eii ria ead 41 7 2 ABOR Too oo a eo oe o AAA ae e ada aol ta 41 7 3 align abs expr abs expr abS expr 41 TA a8Scll String vivi iran dd oc ce RUP E eas 42 To ASC1IZ String v g di li et p REGE aree PERRA a 42 7 6 balign wl abs expr abs expr abs expr 42 T T byte expressions lees 42 7 8 comm symbol length eee eee eee 42 TO S6ficstattpEOO L2 Idae eode d E OR eR ER a a d 43 CAO S6fisendpEOGua o erro cea xe Abe ea aed 43 T 1l cfi def cfa register offset 43 7 12 cfi def cfa register register 43 7 13 cfi def cfa offset offset s esse ssh 43 7 14 cfi adjust cfa offset offset 00 43 7 15 cfi offset register offset 0 44 Using as 7 16 7 17 7 18 7 19 7 20 7 21 7 22 7 23 7 24 7 25 7 26 7 27 7 28 7 29 7 30 7 31 7 32 7 33 7 34 7 39 7 36 7 37 7 38 7 39 7 40 7 41 7 42 7 43 7 44 1 45 7 46 7 47 7 48 7 49 7 50 7 51 7 52 7 53 7 54 7 55 7 56 7 57 7 58 7 59 7 60 7 61 7 62 7 63 cfi rel offset register offset 44 CLA window Vid ed de cen add ados 44 cfi_escape expression ias kuo e be EVE tO 44 data subsection oocooccoocccocc hn 44 A hd ee aed RA eidem eru deed
248. l jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target 114 Using as Following the CPU architecture you may specify jumps or nojumps to control auto matic promotion of conditional jumps jumps is the default and enables jump promotion All external jumps will be of the long variety and file local jumps will be promoted as nec essary see Section 8 112 19 i386 Jumps page 111 nojumps leaves external conditional jumps as byte offset jumps and warns about file local conditional jumps that as promotes Unconditional jumps are treated as for jumps For example arch i8086 nojumps 8 112 25 Notes There is some trickery concerning the mul and imul instructions that deserves mention The 16 32 64 and 128 bit expanding multiplies base opcode Oxf6 extension 4 for mul and 5 for imul can be output only in the one operand form Thus imul ebx eax does not select the expanding multiply the expanding multiply would clobber the edx register and this would confuse gcc output Use imul ebx to get the 64 bit product in pedx eax We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register This is just a shorthand so that multiplying heax by 69 for example
249. le automatic alignment to reduce branch penalties at some ex pense in code size See Section 8 133 8 2 Automatic Instruction Alignment page 193 This optimization is enabled by default Note that the assembler will always align instructions like LOOP that have fixed alignment requirements longcalls no longcalls Enable or disable transformation of call instructions to allow calls across a greater range of addresses See Section 8 133 9 2 Function Call Relaxation 192 Using as page 194 This option should be used when call targets can potentially be out of range but it degrades both code size and performance The default is no longcalls 8 133 7 Assembler Syntax Block comments are delimited by and End of line comments may be introduced with either 4 or Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma separated list of operands opcode operand Instructions must be separated by a newline or semicolon 8 133 7 1 Opcode Names See the Xtensa Instruction Set Architecture ISA Reference Manual for a complete list of opcodes and descriptions of their semantics The Xtensa assembler distinguishes between generic and specific opcodes Specific op codes correspond directly to Xtensa machine instructions Prefixing an opcode with an underscore character _ identifies it as a specific opcode Opcodes without a leading underscore
250. lers to include auxiliary debugging information in the symbol table It is only permitted inside def endef pairs dim is only meaningful when generating COFF format output when as is generating b out it accepts this directive but ignores it 7 23 double flonums double expects zero or more flonums separated by commas It assembles floating point numbers The exact kind of floating point numbers emitted depends on how as is configured See Chapter 8 Machine Dependencies page 67 7 24 eject Force a page break at this point when generating assembly listings 7 25 else else is part of the as support for conditional assembly see Section 7 45 if page 48 It marks the beginning of a section of code to be assembled if the condition for the preceding if was false 7 26 elseif elseif is part of the as support for conditional assembly see Section 7 45 if page 48 It is shorthand for beginning a new if block that would otherwise fill the entire else section 7 27 end end marks the end of the assembly file as does not process anything in the file past the end directive 7 28 endef This directive flags the end of a symbol definition begun with def endef is only meaningful when generating COFF format output if as is configured to generate b out it accepts this directive but ignores it 7 29 endfunc endfunc marks the end of a function specified with func 46 Using as 7 30 endif
251. licitly with the gp register It is only accepted for targets that use ECOFF format such as a DECstation running Ultrix The default value is 8 EB Generate big endian format output EL Generate little endian format output Chapter 1 Overview 9 mipsi mips2 mips3 mips4 mipsb5 mips32 mips32r2 mips64 mips64r2 Generate code for a particular MIPS Instruction Set Architecture level mips1 is an alias for march r3000 mips2 is an alias for march r6000 mips3 is an alias for march r4000 and mips4 is an alias for march r8000 mips5 mips32 mips32r2 mips64 and mips64r2 correspond to generic MIPS V MIPS32 MIPS32 Release 2 MIPS64 and MIPS64 Release 2 ISA processors respectively march CPU Generate code for a particular MIPS cpu mtune cpu Schedule and tune for a particular MIPS cpu mfix7000 mno fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions mdebug no mdebug Cause stabs style debugging output to go into an ECOFF style mdebug section instead of the standard ELF stabs sections mpdr mno pdr Control generation of pdr sections mgp32 mfp32 The register sizes are normally inferred from the ISA and ABI but these flags force a certain group of registers to be treated as
252. lls of leaf procedures If a procedure is known to call no other procedures you may define an entry point that skips procedure prolog code and that does not depend on system supplied saved context and declare it as the bal lab using leafproc If the procedure also has an entry point that goes through the normal prolog you can specify that entry point as call lab 120 Using as A leafproc declaration is meant for use in conjunction with the optimized call instruction cal1j the directive records the data needed later to choose between converting the callj into a bal or a call call lab is optional if only one argument is present or if the two arguments are identical the single argument is assumed to be the bal entry point Sysproc name index The sysproc directive defines a name for a system procedure After you define it using sysproc you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction callj Both arguments are required index must be between 0 and 31 inclusive 8 114 33 1960 Opcodes All Intel 960 machine instructions are supported see Section 8 114 30 i960 Command line Options page 118 for a discussion of selecting the instruction subset for a particular 960 architecture Some opcodes are processed beyond simply emitting a single corresponding instruction callj and Compare and Branch or Compar
253. loating point ARC IEEE 77 floating point ARM IEEE 81 floating point DIOV 0002004 90 floating point D30V 000 2 0 94 floating point ESA 390 IEEE 105 floating point H8 300 IEEE 96 floating point H8 500 IEEE 99 floating point HPPA IEEE 100 floating point Ocio se ee eee irira 111 floating point 1960 IEEE 119 floating point M680x0 ooocooooccoooo 130 floating point M68HC11 136 floating point MSP 430 IEEE 152 floating point SH IEEE 161 floating point SPARC IEEE 167 floating point V850 IEEE 187 floating point VAX isssssssslleeee 181 floating point x86 64 oooccooooccoomooco 111 HOMUMS 5 3 ien ia A Ges 25 force thumb directive ARM 81 format of error messages o oooooccooocco 14 format of warning messages 14 forinfeed N osssisdeccekr edere de ges 24 frame diteclve i4 rad ERI x 199 freeregs directive cose n 199 func directive icono bn 47 functions in expressi0OS o oocoooccooooo oo 37 G gbr960 1960 postprocessor oooo ooooo 118 generic OPcodes seva 192 generics directive cocos ke rr edes 197 gfloat directive VAX o ooooommooom mo 181 A A due qa erg s aea doble dur
254. loating point value All return a floating point value except cvi int and sgn which return an integer value acos expr Returns the floating point arccosine of expr asin expr Returns the floating point arcsine of expr atan expr Returns the floating point arctangent of expr atan2 expri expr2 Returns the floating point arctangent of expr1 expr2 ceil expr Returns the smallest integer not less than expr as floating point cosh expr Returns the floating point hyperbolic cosine of expr cos expr Returns the floating point cosine of expr cvf expr Returns the integer value expr converted to floating point cvi expr Returns the floating point value expr converted to integer exp expr Returns the floating point value e expr fabs expr Returns the floating point absolute value of expr floor expr Returns the largest integer that is not greater than expr as floating point fmod expr1 expr2 Returns the floating point remainder of expr1 expr2 int expr Returns 1 if expr evaluates to an integer zero otherwise ldexp expr1 expr2 Returns the floating point value expr1 2 expr2 log10 expr Returns the base 10 logarithm of expr log expr Returns the natural logarithm of expr Chapter 8 Machine Dependent Features 171 max expri expr2 Returns the floating point maximum of expr1 and expr2 nin expri expr2 Returns the floating point mini
255. lowing section of code if the specified symbol has not been defined Both spelling variants are equivalent Note a symbol which has been referenced but not yet defined is considered to be undefined ifne absolute expression Assembles the following section of code if the argument is not equal to zero in other words this is equivalent to if ifnes string1 string2 Like ifeqs but the sense of the test is reversed this assembles the following section of code if the two strings are not the same 7 46 incbin file skip count The incbin directive includes file verbatim at the current location You can control the search paths used with the I command line option see Chapter 2 Command Line Options page 15 Quotation marks are required around file The skip argument skips a number of bytes from the start of the file The count argument indicates the maximum number of bytes to read Note that the data is not aligned in any way so it is the user s responsibility to make sure that proper alignment is provided both before and after the incbin directive 50 Using as 7 47 include file This directive provides a way to include supporting files at specified points in your source program The code from file is assembled as if it followed the point of the include when the end of the included file is reached assembly of the original file continues You can control the search paths used with the I command line option se
256. ls offer support for GNU products If you obtained as from a support organization we recommend you contact that organization first You can find contact information for many support companies and individuals in the file etc SERVICE in the GNU Emacs distribution In any event we also recommend that you send bug reports for as to pug binutils gnu org The fundamental principle of reporting bugs usefully is this report all the facts If you are not sure whether to state a fact or leave it out state it Often people omit facts because they think they know what causes the problem and assume that some details do not matter Thus you might assume that the name of a symbol you use in an example does not matter Well probably it does not but one cannot be sure Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory perhaps if the name were different the contents of that location would fool the assembler into doing the right thing despite the bug Play it safe and give a specific complete example That is the easiest thing for you to do and the most helpful Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us Therefore always write your bug reports on the assumption that the bug has not been reported previously 202 Using as Sometimes people give a few sketchy facts and ask Does this ring a bell This cannot hel
257. may not appear in string literals as themselves For example the C statement char a he said V it s 50 off is represented in Z8000 assembly language shown with the assembler output in hex at the left as 68652073 sval he said 22it 27s 50 25 o0ff 22 00 61696420 22697427 73203530 25206F66 662200 rsect synonym for section block synonym for space even special case of align aligns output to even byte boundary 180 Using as 8 130 23 Opcodes For detailed information on the Z8000 machine instruction set see 28000 Technical Manual 8 131 VAX Dependent Features 8 131 24 VAX Command Line Options The Vax version of as accepts any of the following options gives a warning message that the option was ignored and proceeds These options are for compatibility with scripts designed for other people s assemblers D Debug S Symbol Table T Token Trace These are obsolete options used to debug old assemblers d Displacement size for JUMPs This option expects a number following the d Like options that expect file names the number may immediately follow the d old standard or constitute the whole of the command line argument that follows d GNU standard V Virtualize Interpass Temporary File Some other assemblers use a temporary file This option commanded them to keep the information in active memory rather than in a disk file as always does this so this option is redund
258. mber Sets the maximum width in words of any further lines of the hex byte dump for a given input source line If this value is not specified it defaults to being the same as the value specified for listing lhs width If neither switch is used the default is to one listing rhs width number Sets the maximum width in characters of the source line that is displayed alongside the hex dump The default value for this parameter is 100 The source line is displayed on the right hand side of the listing output listing cont lines number Sets the maximum number of continuation lines of hex dump that will be dis played for a given single line of source input The default value is 4 2 8 Assemble in MRI Compatibility Mode M The M or mri option selects MRI compatibility mode This changes the syntax and pseudo op handling of as to make it compatible with the ASM68K or the ASM960 depending upon the configured target assembler from Microtec Research The exact nature of the MRI syntax will not be documented here see the MRI manuals for more information Note in particular that the handling of macros and macro arguments is somewhat different The purpose of this option is to permit assembling existing MRI assembler code using as The MRI compatibility is not complete Certain operations of the MRI assembler de pend upon its object file format and can not be supported using other object file formats Supportin
259. me other features of the MRI assembler which are not supported by as typically either because they are difficult or because they seem of little consequence Some of these may be supported in future releases EBCDIC strings EBCDIC strings are not supported packed binary coded decimal Packed binary coded decimal is not supported This means that the DC P and DCB P pseudo ops are not supported FEQU pseudo op The m68k FEQU pseudo op is not supported NOOBJ pseudo op The m68k NOOBJ pseudo op is not supported OPT branch control options The m68k OPT branch control options B BRS BRB BRL and BRW are ignored as automatically relaxes all branches whether forward or backward to an appropriate size so these options serve no purpose OPT list control options The following m68k OPT list control options are ignored C CEX CL CRE E G I M MEX MC MD X other OPT options The following m68k OPT options are ignored NEST 0 OLD OP P PCO PCR PCS R OPT D option is default The m68k OPT D option is the default unlike the MRI assembler OPT NOD may be used to turn it off XREF pseudo op The m68k XREF pseudo op is ignored debug pseudo op The i960 debug pseudo op is not supported extended pseudo op The i960 extended pseudo op is not supported List pseudo op The various options of the 1960 list pseudo op are not supported optimize pseudo op The i960 optimize pseudo op is not supported output
260. mgp64 Assume that 64 bit general purpose registers are available l his is provided in the interests of symmetry with gp32 mipsi6 no mipsi6 Generate code for the MIPS 16 processor This is equivalent to putting set mipsi6 at the start of the assembly file no mips16 turns off this option mips3d no mips3d Generate code for the MIPS 3D Application Specific Extension This tells the assembler to accept MIPS 3D instructions no mips3d turns off this option mdmx no mdmx Generate code for the MDMX Application Specific Extension This tells the assembler to accept MDMX instructions no mdmx turns off this option mfix7000 mno fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions mfix vr4122 bugs no mfix vr4122 bugs Insert nop instructions to avoid errors in certain versions of the vr4122 core This option is intended to be used on GCC generated code it is not designed to catch errors in hand written assembler code m4010 no m4010 Generate code for the LSI R4010 chip This tells the assembler to accept the R4010 specific instructions addciu ffc etc and to not schedule nop instructions around accesses to the HI and LO registers no m4010 turns off this option m4650 no m4650 Generate code for the MIPS R4650 chip This tells the assembler to accept t
261. mily 8 109 2 Syntax 8 109 2 1 Special Characters is the line comment character can be used instead of a newline to separate statements Since has no special meaning you may use it in symbol names 8 109 2 2 Register Names You can use the predefined symbols ro r1 r2 r3 r4 r5 r6 and rT to refer to the H8 500 registers The H8 500 also has these control registers cp code pointer dp data pointer bp base pointer tp stack top pointer ep extra pointer sr status register ccr condition code register All registers are 16 bits long To represent 32 bit numbers use two adjacent registers for distant memory addresses use one of the segment pointers cp for the program counter dp for r0 r3 ep for r4 and r5 and tp for r6 and r7 8 109 2 3 Addressing Modes as understands the following addressing modes for the H8 500 Rn Register direct ORn Register indirect d 8 Rn Register indirect with 8 bit signed displacement Chapter 8 Machine Dependent Features 99 d 16 Rn Register indirect with 16 bit signed displacement Rn Register indirect with pre decrement Rn Register indirect with post increment aa 8 8 bit absolute address aa 16 16 bit absolute address xx 8 8 bit immediate xx 16 16 bit immediate 8 109 3 Floating Point The H8 500 family has no hardware floating point but the float directive generates IEEE floati
262. mitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignment to be filled with no op instructions when appropriate The p2alignw and p2alignl directives are variants of the p2align directive The p2alignw directive treats the fill pattern as a two byte word value The p2alignl di rectives treats the fill pattern as a four byte longword value For example p2alignw 2 0x368d will align to a multiple of 4 If it skips two bytes they will be filled in with the value 0x368d the exact placement of the bytes depends upon the endianness of the processor If it skips 1 or 3 bytes the fill value is undefined 7 65 previous This is one of the ELF section stack manipulation directives The others are section see Section 7 76 Section page 57 subsection see Section 7 87 SubSection page 62 pushsection see Section 7 71 PushSection page 56 and popsection see Section 7 66 PopSection page 55 This directive swaps the current section and subsection with most recently referenced section and
263. move d1 sp0 move d2 sp0 move d3 spQ 7 51 irpc symbol values Evaluate a sequence of statements assigning different values to symbol The sequence of statements starts at the irpc directive and is terminated by an endr directive For Chapter 7 Assembler Directives 51 each character in value symbol is set to the character and the sequence of statements is assembled If no value is listed the sequence of statements is assembled once with symbol set to the null string To refer to symbol within the sequence of statements use symbol For example assembling irpc param 123 move dNparam sp endr is equivalent to assembling move d1 sp0 move d2 sp0 move d3 spQ 7 52 lcomm symbol length Reserve length an absolute expression bytes for a local common denoted by symbol The section and value of symbol are those of the new local common The addresses are allocated in the bss section so that at run time the bytes start off zeroed Symbol is not declared global see Section 7 41 global page 47 so is normally not visible to 1d Some targets permit a third argument to be used with 1comm This argument specifies the desired alignment of the symbol in the bss section The syntax for 1comm differs slightly on the HPPA The syntax is symbol 1comn length symbol is optional 7 53 lflags as accepts this directive for compatibility with other assemblers but ignores it 7 54 line line number Chang
264. mum of expr1 and expr2 pow expr1 expr2 Returns the floating point value expr1 expr2 round expr Returns the nearest integer to expr as a floating point number sgn expr Returns 1 0 or 1 based on the sign of expr sin expr Returns the floating point sine of expr sinh expr Returns the floating point hyperbolic sine of expr sqrt expr Returns the floating point square root of expr tan expr Returns the floating point tangent of expr tanh expr Returns the floating point hyperbolic tangent of expr trunc expr Returns the integer value of expr truncated towards zero as floating point 8 129 16 Extended Addressing The LDX pseudo op is provided for loading the extended addressing bits of a label or address For example if an address label resides in extended program memory the value of label may be loaded as follows ldx label 16 a loads extended bits of label or label a loads lower 16 bits of label bacc a full address is in accumulator A 8 129 17 Directives align size even Align the section program counter on the next boundary based on size size may be any power of 2 even is equivalent to align with a size of 2 1 Align SPC to word boundary 2 Align SPC to longword boundary same as even 128 Align SPC to page boundary 172 Using as asg string name Assign name the string string String replacement is performed on string before assignment eval string name Eval
265. n ELF it will mark the symbol as a function a la the generic type directive end function Mark the end of function In ELF it will set the size of the symbol a la the generic size directive mask mask offset Indicate which of the integer registers are saved in the current function s stack frame mask is interpreted a bit mask in which bit n set indicates that register n is saved The registers are saved in a block located offset bytes from the canonical frame address CFA which is the value of the stack pointer on entry to the function The registers are saved sequentially except that the return address register normally 26 is saved first This and the other directives that describe the stack frame are currently only used when generating mdebug information They may in the future be used to generate DWARF2 debug frame unwind information for hand written as sembly fmask mask offset Indicate which of the floating point registers are saved in the current stack frame The mask and offset parameters are interpreted as with mask frame framereg frameoffset retreg argoffset Describes the shape of the stack frame The frame pointer in use is framereg normally this is either fp or sp The frame pointer is frameoffset bytes below the CFA The return address is initially located in retreg until it is saved as indicated in mask For compatibility with OSF 1 an optional argoffset parameter is accepted and ignored It is beli
266. n as fp the Frame Pointer Address Register Indirect 20 through a7 Address Register Postincrement Ra0 through a7 Address Register Predecrement fa00 through a7 Indirect Plus Offset apc number Index apc number register size scale The number may be omitted Postindex apc number onumber register size scale The onumber or the register but not both may be omitted Preindex apc number register size scale onumber The number may be omitted Omitting the register produces the Postindex addressing mode Absolute symbol or digits optionally followed by b w or 1 8 117 40 Motorola Syntax The standard Motorola syntax for this chip differs from the syntax already discussed see Section 8 117 39 Syntax page 128 as can accept Motorola syntax for operands even if MIT syntax is used for other operands in the same instruction The two kinds of syntax are fully compatible 130 Using as In the following table apc stands for any of the address registers a0 through a7 the program counter pc the zero address relative to the program counter 4zpc or a suppressed address register 4za0 through za7 The use of size means one of w or 1 and it may always be omitted along with the leading dot The use of scale means one of 1 2 4 or
267. n ee one 3 6 2 Number Constants ss esses sees 5 0 2 1 Integers eM RE 3 6 2 2 BignudmB 25 24e ren on e eos 20 0 2 9 FONUS ee ouae gaa a i 4 Sections and Relocation 27 Al Backsroundu deest e e Ata 27 4 2 Linker Sections esaia mandana dda nee te la Rd es 28 4 3 Assembler Internal Sections 00 0 0 e ee ee eee 29 4 4 SUb SECtIONS us ood eer ed dae 29 4 5 bss Section iii eene I o ee eee ad 30 D SV MONS ensena eee vine wees ORE a s did was oon 33 S Labels ss Cm 33 5 2 Giving Symbols Other Values o ooooooooooo o 33 5 3 Symbol Namesicuinosoa das tadas edd E a 33 5 4 The Special Dot Symbol oooooooccocccoccccoco oo 35 5 5 Symbol Attributes sssssssssesee sse 35 Dil Vallarta ete da eae ed aad d 35 9 52 LYpeucnssssedestice Pe ep TERM t AR 35 5 5 3 Symbol Attributes a Q0Ub oo ooooooo 35 5 5 3 1 Descriptor 0 eee eee eris 35 5 5 9 2 Di o csetera Gees cte 36 5 5 4 Symbol Attributes for COFF 36 5 5 4 1 Primary Attributes 36 5 5 4 2 Auxiliary Attributes o 36 5 5 5 Symbol Attributes for SOM oo oooo oooo 36 6 Expressions iem my ROnRPSCEVREUERTES 37 6 1 Empty Expressi0MS oocococoooconnccrnc tateari 37 6 2 Integer Expressions seeeeeeeeee ee 37 6 2 1 Arguments 0 0 cece cece eee eee eee 37 6 2 2 Operators een pinia enn 37 0 2 9 Pref
268. n order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be per formed The presence of this directive also implies thumb thumb set This performs the equivalent of a set directive in that it creates a symbol which is an alias for another symbol possibly not yet defined This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point in the same way that the thumb func directive does 82 ltorg pool Using as This directive causes the current contents of the literal pool to be dumped into the current section which is assumed to be the text section at the current location aligned to a word boundary GAS maintains a separate literal pool for each section and each sub section The 1torg directive will only affect the literal pool of the current section and sub section At the end of assembly all remaining un empty literal pools will automatically be dumped Note older versions of GAS would dump the current literal pool any time a section change occurred This is no longer done since it prevents accurate control of the placement of literal pools This is a synonym for ltorg 8 104 21 Opcodes as implements all the standard ARM opcodes It also implements several pseudo op codes including several synthetic load instructions NOP LDR ADR
269. nal idea was that the assembly language source would be piped into the assembler If the sender of the source quit it could use this directive tells as to quit also One day abort will not be supported 7 2 ABORT When producing COFF output as accepts this directive as a synonym for abort When producing b out output as accepts this directive but ignores it 7 3 align abs expr abs expr abs expr Pad the location counter in the current subsection to a particular storage boundary The first expression which must be absolute is the alignment required as described below The second expression also absolute gives the fill value to be stored in the padding bytes It and the comma may be omitted If it is omitted the padding bytes are normally zero However on some systems if the section is marked as containing code and the fill value is omitted the space is filled with no op instructions The third expression is also absolute and is also optional If it is present it is the maximum number of bytes that should be skipped by this alignment directive If doing the alignment would require skipping more bytes than the specified maximum then the alignment is not done at all You can omit the fill value the second argument entirely by simply using two commas after the required alignment this can be useful if you want the alignment to be filled with no op instructions when appropriate The way the required alignment is speci
270. nce ad de rte nha pandas 196 8 133 10 1 density 00 eee eee eee 196 8 133 10 2 relax iori beer bei p e 196 8 133 10 3 longcallS 0 ooooooooooooo 197 8 133 10 4 genericS oooo oooccooccomo om 197 8 133 10 5 literal nn pita a ea 197 8 133 10 6 literal_position 198 8 133 10 7 literal_prefix ooooooo oooo o 198 8 133 10 8 freeregs 0 00 cece ee eee oo 199 8 133 10 9 fr nie ie er dota e a 199 9 Reporting Bugs ooooo 201 9 1 Have You Found a Bug 00 0 esses 201 9 2 How to Report Bugs 00 cee eee eee eee 201 10 Acknowledgements o oooooooo o o 205 Using as Appendix A GNU Free Documentation License A AAA ERAS 207 ADDENDUM How to use this License for your documents 212 xi Using as
271. nd Chapter 8 Machine Dependent Features Branch bbc bbs cmpibe cmpibg cmpibge cmpibl cmpible cmpibno cmpibne cmpibo cmpobe cmpobg cmpobge cmpobl cmpoble cmpobne Jump cmpije cmpijg cmpijge cmpijl cmpijle cmpijno cmpijne cmpijo cmpoje cmpojg cmpojge cmpojl cmpojle cmpojne Expanded to chkbit bno chkbit bo cmpi be cmpi bg cmpi bge cmpi bl cmpi ble cmpi bno cmpi bne cmpi bo cmpo be cmpo bg cmpo bge cmpo bl cmpo ble cmpo bne 121 122 Using as 8 115 IP2K Dependent Features 8 115 34 IP2K Options The Ubicom IP2K version of as has a few machine dependent options mip2022ext as can assemble the extended 1P2022 instructions but it will only do so if this is specifically allowed via this command line option mip2022 This option restores the assembler s default behaviour of not permitting the extended P2022 instructions to be assembled Chapter 8 Machine Dependent Features 123 8 116 M32R Dependent Features 8 116 35 M32R Options The Renease M32R version of as has a few machine dependent options m32rx as can assemble code for several different members of the Renesas M32R fam ily Normally the default is to assemble code for the M32R microprocessor This option may be used to change the default to the M32RX microprocessor which adds some more instructions to the basic M32R instruction set and some additional parameters to some of the original instructions
272. ng expressiOns erisir iii r Er ENPI bh 52 niteke ao mim ins E de RE EE 52 NOMS uri ri ees tt Re nee hee 54 Octa DI BNUMS b e deae iia 54 Org new lc TUI pana rains aus ree dA RAE Roe not led 54 ii 7 64 7 65 7 66 7 67 7 68 7 69 7 70 7 71 7 72 7 73 7 74 7 75 7 76 7 77 7 78 7 79 7 80 7 81 7 82 7 83 7 84 7 85 7 86 7 87 7 88 7 89 7 90 7 91 7 92 7 93 7 94 7 95 7 96 7 97 7 98 7 99 7 100 p2align w1 abs expr abs expr abs expr 54 A exse eredi aud nadie dus desine bus eid 55 sPOPSCCELON fs ieee dieses bed eee eh eee RE RE E RR 55 print string i sco ga eens dne tea bee d 55 j protected names iii ia wed di E YR 55 spSize lines columns 2 ea 56 putgen name iege seed stie BA Ao da Rr arc 56 pushsection name subsection ss sss 56 quad bignums wicca lg RR she RE e Re 56 LOPE COM P m 56 iSbttl subheading loses cerei ween 57 SCL Classis teda bere d addens tee eed i 57 B ction Dame aci a a a a ane ee oe dae 57 set symbol CXpreSSiON cece cece irr eee 59 Short EXPFeSSIOUS 00 ewe wid ete eoe ees 59 Single flonums 206i isse eh sh Rh RE Rond 59 SU LG M 59 s1eb128 expressions are reg ah 60 SEYp size y fill ii a Pathe ee ees esa 60 SSpace SIZO y 3T 5d daretur a Grece iet 60 Stabd stabn StabS ooooooooomooooo oo 60 SCLIN sr aces do n dod ceder aod e Y eod te PUR ds 61 struct
273. ng point numbers for compatibility with other development tools 8 109 4 H8 500 Machine Directives as has no machine dependent directives for the H8 500 However on this platform the int and word directives generate 16 bit numbers 8 109 5 Opcodes For detailed information on the H8 500 machine instruction set see H8 500 Series Pro gramming Manual Renesas M21T001 as implements all the standard H8 500 opcodes No additional pseudo instructions are needed on this family 100 Using as 8 110 HPPA Dependent Features 8 110 1 Notes As a back end for GNU CC as has been throughly tested and should work extremely well We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers The format of the debugging sections has changed since the original as port version 1 3X was released therefore you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats Additional relocation support will be added as it becomes necessary 8 110 2 Options as has no machine dependent command line options for the HPPA 8 110 3 Syntax The assembler syntax closely follows the HPPA instruction set reference manual as sembler directives and general syntax closely follow the HPPA assembly language refe
274. ng tokens are absent size is assumed to be 1 7 39 float flonums This directive assembles zero or more flonums separated by commas It has the same effect as single The exact kind of floating point numbers emitted depends on how as is configured See Chapter 8 Machine Dependencies page 67 7 40 func name label func emits debugging information to denote function name and is ignored unless the file is assembled with debugging enabled Only gstabs is currently supported label is the entry point of the function and if omitted name prepended with the leading char is used leading char is usually _ or nothing depending on the target All functions are currently defined to have void return type The function must be terminated with endfunc 7 41 global symbol globl symbol global makes the symbol visible to 1d If you define symbol in your partial program its value is made available to other partial programs that are linked with it Otherwise symbol takes its attributes from a symbol of the same name from another file linked into the same program Both spellings globl and global are accepted for compatibility with other as semblers 48 Using as On the HPPA global is not always enough to make it accessible to other partial programs You may need the HPPA only EXPORT directive as well See Section 8 110 5 HPPA Assembler Directives page 101 7 42 hidden names This one of
275. ns in section 3 You may also lend copies under the same conditions stated above and you may publicly display copies COPYING IN QUANTITY If you publish printed copies of the Document numbering more than 100 and the Document s license notice requires Cover Texts you must enclose the copies in covers that carry clearly and legibly all these Cover Texts Front Cover Texts on the front cover and Back Cover Texts on the back cover Both covers must also clearly and legibly identify you as the publisher of these copies The front cover must present the full title with all words of the title equally prominent and visible You may add other material on the covers in addition Copying with changes limited to the covers as long Appendix A GNU Free Documentation License 209 as they preserve the title of the Document and satisfy these conditions can be treated as verbatim copying in other respects If the required texts for either cover are too voluminous to fit legibly you should put the first ones listed as many as fit reasonably on the actual cover and continue the rest onto adjacent pages If you publish or distribute Opaque copies of the Document numbering more than 100 you must either include a machine readable Transparent copy along with each Opaque copy or state in or with each Opaque copy a publicly accessible computer network location containing a complete Transparent copy of the Document free of added ma terial which the
276. ns default to 32 bit size This is so that the stack pointer is manipulated in the same way over function calls allowing access to function parameters at the same stack offsets as in 32 bit mode code16gcc also automatically adds address size prefixes where necessary to use the 32 bit addressing modes that gcc generates Chapter 8 Machine Dependent Features 113 The code which as generates in 16 bit mode will not necessarily run on a 16 bit pre 80386 processor To write code that runs on such a processor you must refrain from using any 32 bit constructs which require as to output address or operand size prefixes Note that writing 16 bit code instructions by explicitly specifying a prefix or an instruc tion mnemonic suffix within a 32 bit code section generates different machine instructions than those generated for a 16 bit code segment In a 32 bit code section the following code generates the machine opcode bytes 66 6a 04 which pushes the value 4 onto the stack decrementing hesp by 2 pushw 4 The same code in a 16 bit code section would generate the machine opcode bytes 6a 04 ie without the operand size prefix which is correct since the processor default operand size is assumed to be 16 bits in a 16 bit code section 8 112 23 AT amp T Syntax bugs The UnixWare assembler and probably other AT amp T derived ix86 Unix assemblers generate floating point instructions with reversed source and destination
277. nsions Enable all instruction set extensions mno extensions Disable all instruction set extensions mcis mno cis Enable or disable the use of the commercial instruction set which consists of these instructions ADDNI ADDN ADDPI ADDP ASHNI ASHN ASHPI ASHP CMPCI CMPC CMPNI CMPN CMPPI CMPP CVTLNI CVTLN CVTLPI CVTLP CVTNLI CVTNL CVTNPI CVTNP CVTPLI CVTPL CVTPNI CVTPN DIVPI DIVP L2DR L3DR LOCCI LOCC MATCI MATC MOVCI MOVC MOVRCI MOVRC MOVTCI MOVTC MULPI MULP SCANCI SCANC SKPCI SKPC SPANCI SPANC SUBNI SUBN SUBPI and SUBP mcsm mno csm Enable or disable the use of the CSM instruction meis mno eis Enable or disable the use of the extended instruction set which consists of these instructions ASHC ASH DIV MARK MUL RTT SOB SXT and XOR mfis mkev11 mno fis mno kev11 Enable or disable the use of the KEV11 floating point instructions FADD FDIV FMUL and FSUB mfpp mfpu mfp 11 mno fpp mno fpu mno fp 11 Enable or disable the use of FP 11 floating point instructions ABSF ADDF CFCC CLRF CMPF DIVF LDCFF LDCIF LDEXP LDF LDFPS MODF MULF NEGF 154 Using as SETD SETF SETI SETL STCFF STCFI STEXP STF STFPS STST SUBF and TSTF mlimited eis mno limited eis Enable or disable the use of the limited extended instruction set MARK RTT SOB SXT and XOR The mno limited eis options also implies mno eis mmfpt
278. nstructions Jump instructions are always optimized to use the smallest possible displacements This is accomplished by using byte 8 bit displacement jumps whenever the target is sufficiently close If a byte displacement is insufficient a long displacement is used We do not support word 16 bit displacement jumps in 32 bit mode i e prefixing the jump instruction with the data16 instruction prefix since the 80386 insists upon masking eip to 16 bits after the word displacement is added See also see Section 8 112 24 i386 Arch page 113 Note that the jcxz jecxz loop loopz loope loopnz and loopne instruc tions only come in byte displacements so that if you use these instructions gcc does not use them you may get an error message and incorrect code The AT amp T 80386 assembler tries to get around this problem by expanding jcxz foo to jcxz cx_zero jmp cx_nonzero cx_zero jmp foo cx_nonzero 8 112 20 Floating Point All 80387 floating point types except packed BCD are supported BCD support may be added without much difficulty These data types are 16 32 and 64 bit integers and single 32 bit double 64 bit and extended 80 bit precision floating point Each supported type has an instruction mnemonic suffix and a constructor associated with it Instruction mnemonic suffixes specify the operand s data type Constructors build these data types into memory
279. nstructions relaxation 194 call instructions x86 64 ooooooooo ooooo 108 callj i960 pseudo opcode 120 carriage return WO sone ns cat 24 cfi endproc directive oo oooooocoooo 43 cfi startproc directive o 43 char directive TICBAX 172 character Constants cuina 23 character escape codes ss esses esses 24 character single 46enreRe ai unie ti Rn 24 characters used in symbols 22 clink directive DICBAX eecscriisatrisi eners 172 code directive ARM 0 occcccccccccccccccc 81 code16 directive 1386 o o ooooooo o oo 112 codel6gcc directive 1386 ooooooo o 112 code32 directive 1386 o oooooooo ooo 112 code64 directive 1386 o oooooooo o oo 112 code64 directive x86 64 0ooooooooooooo 112 COFF auxiliary symbol information 45 COFF structure debugging 63 218 COFF symbol attributes 0 36 COFF symbol descriptor 0 00 44 COFF symbol storage clasS 57 COFF symbol type 5 64 COFF symbols debugging 44 COFF value attribute o o oooooooooo 65 COMDAT i 6o ep dese A 52 commi directive olo e seed donee EF IbU TELE 43 command line conventions esses 12 command line options V850 184 command line options ign
280. nt numbers The older floating point formats are not supported 8 111 11 ESA 390 Assembler Directives as for the ESA 390 supports all of the standard ELF SVRA assembler directives that are documented in the main part of this documentation Several additional directives are supported in order to implement the ESA 390 addressing model The most important of these are using and ltorg These are the additional directives in as for the ESA 390 dc A small subset of the usual DC directive is supported drop regno Stop using regno as the base register The regno must have been previously declared with a using directive in the same section as the current section ebcdic string Emit the EBCDIC equivalent of the indicated string The emitted string will be null terminated Note that the directives string etc emit ascii strings by default EQU The standard HLASM style EQU directive is not supported however the stan dard as directive equ can be used to the same effect ltorg Dump the literal pool accumulated so far begin a new literal pool The literal pool will be written in the current section in order to generate correct assembly a using must have been previously specified in the same section Using expr regno Use regno as the base register for all subsequent RX RS and SS form instruc tions The expr will be evaluated to obtain the base address usually expr will merely be This assembler allows two using direc
281. nt to do a branch to a symbol that is defined later in your program you can write bra s foo Objdump and GDB will always append s or 1 to instructions which have both short and long forms 8 106 26 2 Sub Instructions The D10V assembler takes as input a series of instructions either one per line or in the special two per line format described in the next section Some of these instructions will be short form or sub instructions These sub instructions can be packed into a single instruction The assembler will do this automatically It will also detect when it should not 88 Using as pack instructions For example when a label is defined the next instruction will never be packaged with the previous one Whenever a branch and link instruction is called it will not be packaged with the next instruction so the return address will be valid Nops are automatically inserted when necessary If you do not want the assembler automatically making these decisions you can control the packaging and execution type parallel or sequential with the special execution symbols described in the next section 8 106 26 3 Special Characters 5 and are the line comment characters Sub instructions may be executed in order in reverse order or in parallel Instructions listed in the standard one per line format will be executed sequentially To specify the executing order use the following symbols gt Sequential with instruct
282. ntain the address of the 1dah instruction There must be exactly one 1da instruction paired with the 1dah instruction though it may appear anywhere in the instruction stream The immediate operands must be zero bsr 26 foo ldah 29 0 26 gpdisp 1i lda 29 0 29 gpdisp i gprelhigh Used with an 1dah instruction to add the high 16 bits of a 32 bit displacement from the GP gprellow Used with any memory format instruction to add the low 16 bits of a 32 bit displacement from the GP gprel Used with any memory format instruction to add a 16 bit displacement from the GP Isamegp Used with any branch format instruction to skip the GP load at the target address The referenced symbol must have the same GP as the source object Chapter 8 Machine Dependent Features 73 t1sgd It1sgd N tlsldm tlsldm N gotdtprel Idtprelhi dtprello dtprel gottprel Itprelhi tprello tprel file and it must be declared to either not use 27 or perform a standard GP load in the first two instructions via the prologue directive Used with an lda instruction to load the address of a TLS descriptor for a symbol in the GOT The sequence number N is optional and if present it used to pair the descriptor load with both the literal loading the address of the __tls_get_addr function and the lituse_tlsgd marking the call to that function For proper relaxation both the t1sgd literal and lituse relocations must be in the same
283. ntax DIOV ssc dorar e RE REDUEE RS 87 Syntax DIO Vico cre ots exu E pa cis 91 227 syntax M680K0 errasse unn E rore 128 syntax M68HC11 134 135 syntax machine independent 21 syntax Xtensa assembler 192 sysproc directive 1960 ooooooomoooo 120 T tab NE duco nce pra 24 tab directive TICBAX 175 tag ditectlye ciar uvi aae kini Pori ar peas 63 tag directive TICBAX miooo ette 175 tdaoff pseudo op V850 0 00 189 temporary symbol nameS 0 ooooooooooooo 33 text and data sections joining 19 text directive s c De REED e deen 63 text SeCLlOn ssec hn mr m ped nep 28 tfloat directive 1386 oo oooooo TIE tfloat directive x86 64d o o ooooooo ooooo T1 thumb directive ARM o ooococccoooooooo 81 Ehiimb supportei 2824 rer air 79 thumb func directive ARM 81 thumb set directive ARM 0 oo o oooo 81 TIC54X builtin math functions 170 TIC54X machine directives o o o oo 171 TIC54X memory mapped registers 177 TIC54X ODLIODS m2 ii a aa 168 TIC54X subsym builtins 176 TICHAXN SUPPO iii ina 168 TIC54X specific macros ooooooooccoomoo 176 time total for assembly 19 title directives o ei pil ita 63 tp register VSDO i isses as anges 185 trusted compiler 2 esse deen ne 1
284. o declare the number of lines and optionally the number of columns to use for each page when generating listings If you do not use psize listings use a default line count of 60 You may omit the comma and columns specification the default width is 200 columns as generates formfeeds whenever the specified number of lines is exceeded or whenever you explicitly request one using eject If you specify lines as 0 no formfeeds are generated save those explicitly specified with eject 7 70 purgem name Undefine the macro name so that later uses of the string will not be expanded See Section 7 60 Macro page 53 7 71 pushsection name subsection This is one of the ELF section stack manipulation directives The others are section see Section 7 76 Section page 57 subsection see Section 7 87 SubSection page 62 popsection see Section 7 66 PopSection page 55 and previous see Section 7 65 Previous page 55 This directive is asynonym for section It pushes the current section and subsection onto the top of the section stack and then replaces the current section and subsection with name and subsection 7 72 quad bignums quad expects zero or more bignums separated by commas For each bignum it emits an 8 byte integer If the bignum won t fit in 8 bytes it prints a warning message and just takes the lowest order 8 bytes of the bignum The term quad comes from contexts in which a word
285. o the appropriate numeric values It does not do macro processing include file handling or anything else you may get from your C compiler s preprocessor You can do include file processing with the include directive see Section 7 47 include page 50 You can use the GNU C compiler driver to get other CPP style preprocessing by giving the input file a S suffix See section Options Controlling the Kind of Output in Using GNU CC Excess whitespace comments and character constants cannot be used in the portions of the input text that are not preprocessed If the first line of an input file is NO APP or if you use the f option whitespace and comments are not removed from the input file Within an input file you can ask for whitespace and comment removal in specific portions of the by putting a line that says APP before the text that may contain whitespace or comments and putting a line that says NO_APP after this text This feature is mainly intend to support asm statements in compilers whose output is otherwise free of comments and whitespace 3 2 Whitespace Whitespace is one or more blanks or tabs in any order Whitespace is used to separate symbols and to make programs neater for people to read Unless within character constants see Section 3 6 1 Character Constants page 23 any whitespace means the same as exactly one space 3 3 Comments There are two ways of rendering comments to as In both
286. ocessor for Multimedia Applications Mitsubishi Electric Corp as imple ments all the standard D30V opcodes The only changes are those described in the section on size modifiers Chapter 8 Machine Dependent Features 95 8 108 H8 300 Dependent Features 8 108 1 Options as has no additional command line options for the Renesas formerly Hitachi H8 300 family 8 108 2 Syntax 8 108 2 1 Special Characters is the line comment character can be used instead of a newline to separate statements Therefore you may not use in symbol names on the H8 300 8 108 2 2 Register Names You can use predefined symbols of the form rnh and rnl to refer to the H8 300 registers as sixteen 8 bit general purpose registers n is a digit from 0 to 7 for instance both roh and r71 are valid register names You can also use the eight predefined symbols rn to refer to the H8 300 registers as 16 bit registers you must use this form for addressing On the H8 300H you can also use the eight predefined symbols ern er0 er7 to refer to the 32 bit general purpose registers The two control registers are called pc program counter a 16 bit register except on the H8 300H where it is 24 bits and ccr condition code register an 8 bit register r7 is used as the stack pointer and can also be called sp 8 108 2 3 Addressing Modes as understands the following addressing mo
287. of mmixal operator precedence is that of the C programming language It s recommended to use parentheses to explicitly specify wanted operator precedence whenever more than one type of operators are used The serialize unary operator amp the fractional division operator the logical not operator and the modulus operator are not available Symbols are not global by default unless the option globalize symbols is passed Use the global directive to globalize symbols see Section 7 41 Global page 47 150 Using as Operand syntax is a bit stricter with as than mmixal For example you can t say addu 1 2 3 instead you must write addu 1 2 3 You can t LOC to a lower address than those already visited i e backwards A LOC directive must come before any emitted code Predefined symbols are visible as file local symbols after use In the ELF file that is the linked mmo file has no notion of a file local symbol Some mapping of constant expressions to sections in LOC expressions is attempted but that functionality is easily confused and should be avoided unless compatibility with mmixal is required A LOC expression to 0x2000000000000000 or higher maps to the data section and lower addresses map to the text section see MMIX loc page 147 The code and data areas are each contiguous Sparse programs with far away LOC directives will take up the same amount of space
288. of what behavior you observe that you believe is incorrect For example It gets a fatal signal Of course if the bug is that as gets a fatal signal then we will certainly notice it But if the bug is incorrect output we might not notice unless it is glaringly wrong You might as well not give us a chance to make a mistake Even if the problem you experience is a fatal signal you should still say so explicitly Suppose something strange is going on such as your copy of as is out of synch or you have encountered a bug in the C library on your system This has happened Your copy might crash and ours would not If you told us to expect a crash then when ours fails to crash we would know that the bug was not happening for us If you had not told us to expect a crash then we would not be able to draw any conclusion from our observations e If you wish to suggest changes to the as source send us context diffs as generated by diff with the u c or p option Always send diffs from the old file to the new file If you even discuss something in the as source refer to it by context not by line number The line numbers in our development sources will not match those in your sources Your line numbers would convey no useful information to us Here are some things that are not necessary e A description of the envelope of the bug Often people who encounter a bug spend a lot of time investigating which changes to th
289. ol pe e OULERES 50 int directive H8 300 2 0 005 97 int directive H8S 500 oooooocccccccccoo 99 int directive 1386 000 iaa 112 int directive TICBAX cooper corras 173 int directive x86 64 oo ooooooooooo 112 integer expressiODnS iis e pn pr hr td 3T integer lO byl esce sd te Rex REP 54 integer 8 byte vemm rr ERU 5T MER Em 25 integers LO Dit serca is 48 integers 32 bit mcr ae TRY 50 integers binary dere ERIS ada 25 integers decimal vias or 25 integers hexadecimal 25 integers Octal vips 25 integers one byte 42 intel syntax pseudo op 1386 107 intel syntax pseudo op x86 64 107 internal assembler sections suus 29 internal directive 0oooooooocmoooo 50 invalid input 22432222 RR id 201 INVOCALION Summary so s ERR ba we ds 1 IP2K architecture options o o 122 IPK ODLIOBS iare tea UOETRBISRSSG Us 122 IP2K SUpDOEb pp rx llos det toes a 122 irp directlVe censa RR ER ERR LER LASS 50 irpe directlye i i en reddis o 51 ISA options SH64 Luuuuueesseess 163 J joining text and data sections 19 jump instructions 1386 ooooooo oooo 108 jump instructions x86 64 108 jump optimization 1386 o oooooooo ooo TI jump optimization x86 64 111 jump call operands 1386 000 107 jump call ope
290. ompatibility with various other assemblers The syntaxes supported are type lt name gt function type lt name gt object type lt name gt function type lt name gt object type lt name gt function type lt name gt object type lt name gt function type lt name gt object type lt name gt STT_FUNCTION type lt name gt STT_OBJECT 7 93 uleb128 expressions uleb128 stands for unsigned little endian base 128 This is a compact variable length representation of numbers used by the DWARF symbolic debugging format See Section 7 81 Sleb128 page 60 7 94 val addr This directive permitted only within def endef pairs records the address addr as the value attribute of a symbol table entry val is used only for COFF output when as is configured for b out it accepts this directive but ignores it 7 95 version string This directive creates a note section and places into it an ELF formatted note of type NT_VERSION The note s name is set to string Chapter 7 Assembler Directives 65 7 96 vtable_entry table offset This directive finds or creates a symbol table and creates a VTABLE_ENTRY relocation for it with an addend of offset 7 97 vtable_inherit child parent This directive finds the symbol child and finds or creates the symbol parent and then creates a VTABLE_INHERIT relocation for the parent whose addend is the value of the child symbol As a special case the
291. on here is primarily for the ELF object format as also supports the ECOFF and EVAX formats but features specific to these formats are not yet documented 8 102 7 Options mcpu mdebug This option specifies the target processor If an attempt is made to assemble an instruction which will not execute on the target processor the assembler may either expand the instruction as a macro or issue an error message This option is equivalent to the arch directive The following processor names are recognized 21064 21064a 21066 21068 21164 21164a 21164pc 21264 21264a 21264b ev4 ev5 1ca45 ev5 ev56 pca56 ev6 ev67 ev68 The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor In order to support existing practice in OSF 1 with respect to arch and exist ing practice within MILO the Linux ARC bootloader the numbered processor names e g 21064 enable the processor specific PALcode instructions while the electro vlasic names e g ev4 do not no mdebug relax 32addr Enables or disables the generation of mdebug encapsulation for stabs directives and procedure descriptors The default is to automatically enable mdebug when the first stabs directive is seen This option forces all relocations to be put into the object file instead of saving space and resolving some relocations at assembly time Note that this option does not propagat
292. oo eee ee 180 8 131 24 VAX Command Line Options 180 8 131 25 VAX Floating Point 181 8 131 26 Vax Machine Directives 181 8 131 27 VAX Opcodes 0 nsan otau naases 181 8 131 28 VAX Branch Improvement 182 8 131 29 VAX Operands 0 00 c eee eee eee 183 8 131 380 Not Supported on VAX o o ooo oooo 184 8 132 v850 Dependent Features 0 00 cece eee eee 184 8 132 1 Options eee a eee eee 184 8 182 2 Syntax err ameona Re doti 1 iad 185 8 132 2 1 Special Characters 185 8 132 2 2 Register Names 185 8 132 3 Floating Pointed aeree am es 187 8 132 4 V850 Machine Directives o o o oooooo o 187 8 132 5 Opcodesa ie dis a Rega 188 8 133 Xtensa Dependent Features 0 oooooooooooo 191 8 133 6 Command Line Options 191 8 133 7 Assembler Syntax 0 00 0c eee ee eee 192 8 133 7 1 Opcode Names 0oooooooooo o 192 8 133 7 2 Register NameS o oooooooo o 192 8 133 8 Xtensa Optimizations lesse esses 193 8 133 8 1 Using Density Instructions 193 8 133 8 2 Automatic Instruction Alignment 193 8 133 9 Xtensa Relaxation 000 nunne 194 8 133 9 1 Conditional Branch Relaxation 194 8 133 9 2 Function Call Relaxation 194 8 133 9 3 Other Immediate Field Relaxation 195 8 133 10 DirectiveS i
293. oo_example page foo_example and this is equivalent to call foo_example And for 68HC11 it could be written as follows ldab page foo_example stab _page_switch jsr addr foo_example 8 118 47 Assembler Directives The 68HC11 and 68HC12 version of as have the following specific assembler directives relax The relax directive is used by the GNU Compiler to emit a specific relocation to mark a group of instructions for linker relaxation T he sequence of instruc tions within the group must be known to the linker so that relaxation can be performed mode mshort mlong mshort double mlong double This directive specifies the ABI It overrides the mshort mlong mshort double and mlong double options far symbol This directive marks the symbol as a far symbol meaning that it uses a call rtc calling convention as opposed to jsr rts During a final link the linker will identify references to the far symbol and will verify the proper calling convention interrupt symbol This directive marks the symbol as an interrupt entry point This information is then used by the debugger to correctly unwind the frame across interrupts xrefb symbol This directive is defined for compatibility with the Specification for Motorola 8 and 16 Bit Assembly Language Input Standard and is ignored 8 118 48 Floating Point Packed decimal P format floating literals are not support
294. or as portable directive org param name typ param r Similar to export but used for static procedures proc Use preceding the first statement of a procedure procend Use following the last statement of a procedure label reg expr Synonym for equ define label with the absolute expression expr as its value Space secname params Switch to section secname creating a new section by that name if necessary You may only use params when creating a new section not when switching to an existing one secname may identify a section by number rather than by name If specified the list params declares attributes of the section identified by key words The keywords recognized are spnum exp identify this section by the number exp an absolute expression sort exp order sections according to this sort key when linking exp is an absolute expression unloadable sec tion contains no loadable data notdefined this section defined elsewhere and private data in this section not available to other programs Spnum secnam Allocate four bytes of storage and initialize them with the section number of the section named secnam You can define the section number with the HPPA Space directive Chapter 8 Machine Dependent Features 103 string str Copy the characters in the string str to the object file See Section 3 6 1 1 Strings page 23 for information on escape sequ
295. ored VAX 180 comments aia ttem PERI 21 comments M680x0 sseeeeeeess 132 comments removed by preprocessor 21 common directive SPARC 167 COMMON Sections s do bee Ae es dae ees 52 common variable storage ooooooooo 30 compare and jump expansions i960 120 compare branch instructions i960 120 comparison expressions esee eee eene 38 conditional assembly 00ooooooooocccoooo 48 constant single character luus 24 COUDSUADUS Lo oU ERE ID PR ea 23 constants bignum eee ese e een 25 constants charactel ooooooooocooooo 23 constants converted by preprocessor 21 constants floating point 25 constants Integer i 22 2 ec ve e eg eden 25 constants number iniciada er ee eee Ra 25 constants siringasil ssereeresus anre dad eet 23 constants TIC5AX coccion err ar Rma 168 conversion instructions 1386 108 conversion instructions x86 64 108 coprocessor wait 1386 oooooooooooo o o 110 copy directive TIC54X o ooocoooooo oo 172 cputype directive AMD 29K 69 crash of assembler oooooooccocoooo ooo 201 CRIS emulation crisaout command line OPIO ideata ee ada 83 CRIS emulation criself command line option EP 83 CRIS no underscore command line option A sd 83 CRIS pic command line option
296. p instructions are added any label immediately preceding the original loop will be moved in order to refer to the loop instruction not the newly generated no op instruction 194 Using as Similarly the ENTRY instruction must be aligned on a 0 mod 4 byte boundary The assembler satisfies this requirement by inserting zero bytes when required In addition labels immediately preceding the ENTRY instruction will be moved to the newly aligned instruction location 8 133 9 Xtensa Relaxation When an instruction operand is outside the range allowed for that particular instruction field as can transform the code to use a functionally equivalent instruction or sequence of instructions This process is known as relaxation This is typically done for branch instructions because the distance of the branch targets is not known until assembly time The Xtensa assembler offers branch relaxation and also extends this concept to function calls MOVI instructions and other instructions with immediate fields 8 133 9 1 Conditional Branch Relaxation When the target of a branch is too far away from the branch itself i e when the offset from the branch to the target is too large to fit in the immediate field of the branch instruction it may be necessary to replace the branch with a branch around a jump For example beqz a2 L may result in bnez n a2 M j L M The BNEZ N instruction would be used in this example only if the density option is availa
297. p to a multiple of four bytes Subsections may be padded a different amount on different flavors of as Subsections appear in your object file in numeric order lowest numbered to highest All this to be compatible with other people s assemblers The object file contains no representation of subsections 1d and other programs that manipulate object files see no trace of them They just see all your text subsections as a text section and all your data subsections as a data section To specify which subsection you want subsequent statements assembled into use a nu meric argument to specify it in a text expression or a data expression statement When generating COFF or ELF output you can also use an extra subsection argument with arbitrary named sections section name expression Expression should be an absolute expression See Chapter 6 Expressions page 37 If you just say text then text 0 is assumed Likewise data means data 0 Assembly begins in text 0 For instance text 0 The default subsection is text 0 anyway ascii This lives in the first text subsection text 1 ascii But this lives in the second text subsection data 0 ascii This lives in the data section ascii in the first data subsection text 0 ascii This lives in the first text section ascii immediately following the asterisk Each section has a location counter incremented by one for ev
298. p us fix a bug so it is basically useless We respond by asking for enough details to enable us to investigate You might as well expedite matters by sending them to begin with To enable us to fix the bug you should include all these things e The version of as as announces it if you start it with the version argument Without this we will not know whether there is any point in looking for the bug in the current version of as e Any patches you may have applied to the as source e The type of machine you are using and the operating system name and version number e What compiler and its version was used to compile as e g gcc 2 7 e The command arguments you gave the assembler to assemble your example and observe the bug To guarantee you will not omit something important list them all A copy of the Makefile or the output from make is sufficient If we were to try to guess the arguments we would probably guess wrong and then we might not encounter the bug e A complete input file that will reproduce the bug If the bug is observed when the assembler is invoked via a compiler send the assembler source not the high level language source Most compilers will produce the assembler source when run with the S option If you are using gcc use the options v save temps this will save the assembler source in a file with an extension of s and also show you exactly how as is being run e A description
299. parent name of 0 is treated as refering the ABS section 7 98 weak names This directive sets the weak attribute on the comma separated list of symbol names If the symbols do not already exist they will be created 7 99 word expressions This directive expects zero or more expressions of any section separated by commas The size of the number emitted and its byte order depend on what target computer the assembly is for Warning Special Treatment to support Compilers Machines with a 32 bit address space but that do less than 32 bit addressing require the following special treatment If the machine of interest to you does 32 bit addressing or doesn t require it see Chapter 8 Machine Dependencies page 67 you can ignore this issue In order to assemble compiler output into something that works as occasionally does strange things to word directives Directives of the form word symi sym2 are often emitted by compilers as part of jump tables Therefore when as assembles a directive of the form word symi sym2 and the difference between sym1 and sym2 does not fit in 16 bits as creates a secondary jump table immediately before the next label This secondary jump table is preceded by a short jump to the first byte after the secondary table This short jump prevents the flow of control from accidentally falling into the new table Inside the table is a long jump to sym2 The original word contains sym1
300. pful to have an idea of their meanings to as These sections are used to permit the value of every expression in your assembly language program to be a section relative address ASSEMBLER INTERNAL LOGIC ERROR An internal assembler logic error has been found This means there is a bug in the assembler expr section The assembler stores complex expression internally as combinations of symbols When it needs to represent an expression as a symbol it puts it in the expr section 4 4 Sub Sections Assembled bytes conventionally fall into two sections text and data You may have separate groups of data in named sections that you want to end up near to each other in the object file even though they are not contiguous in the assembler source as allows you 30 Using as to use subsections for this purpose Within each section there can be numbered subsections with values from 0 to 8192 Objects assembled into the same subsection go into the object file together with other objects in the same subsection For example a compiler might want to store constants in the text section but might not want to have them interspersed with the program being assembled In this case the compiler could issue a text 0 before each section of code being output and a text 1 before each group of constants being output Subsections are optional If you do not use subsections everything goes in subsection number zero Each subsection is zero padded u
301. ps two bytes they will be filled in with the value 0x368d the exact placement of the bytes depends upon the endianness of the processor If it skips 1 or 3 bytes the fill value is undefined 7 7 byte expressions byte expects zero or more expressions separated by commas Each expression is as sembled into the next byte Chapter 7 Assembler Directives 43 7 8 comm symbol length comm declares a common symbol named symbol When linking a common symbol in one object file may be merged with a defined or common symbol of the same name in another object file If 1d does not see a definition for the symbol just one or more common symbols then it will allocate length bytes of uninitialized memory length must be an absolute expression If 1d sees multiple common symbols with the same name and they do not all have the same size it will allocate space using the largest size When using ELF the comm directive takes an optional third argument This is the desired alignment of the symbol specified as a byte boundary for example an alignment of 16 means that the least significant 4 bits of the address should be zero The alignment must be an absolute expression and it must be a power of two If 1d allocates uninitialized memory for the common symbol it will use the alignment when placing the symbol If no alignment is specified as will set the alignment to the largest power of two less than or equal to the size of the symbol up to a max
302. pseudo op The i960 output pseudo op is not supported Chapter 2 Command Line Options 19 e setreal pseudo op The i960 setreal pseudo op is not supported 2 9 Dependency Tracking MD as can generate a dependency file for the file 1t creates This file consists of a single rule suitable for make describing the dependencies of the main source file The rule is written to the file named in its argument This feature is used in the automatic updating of makefiles 2 10 Name the Object File o There is always one object file output when you run as By default it has the name a out or b out for Intel 960 targets only You use this option which takes exactly one filename to give the object file a different name Whatever the object file is called as overwrites any existing file of the same name 2 11 Join Data and Text Sections R R tells as to write the object file as if all data section data lives in the text section This is only done at the very last moment your binary data are the same but data section parts are relocated differently The data section part of your object file is zero bytes long because all its bytes are appended to the text section See Chapter 4 Sections and Relocation page 27 When you specify R it would be possible to generate shorter address displacements because we do not have to cross between text and data section We refrain from doing this simply
303. r and the mulx instruction in the right container 6 stw r2 0 r3 r4 gt mulx a0 r8 r9 Two line format Execute the stw instruction followed by the mulx instruc tion sequentially The first instruction goes in the left container and the second instruction goes into right container The assembler will give an error if the machine ordering constraints are violated stw r2 0 r3 r4 mulx a0 r8 r9 Same as previous example except that the mulx instruction is executed before the stw instruction Since has no special meaning you may use it in symbol names Chapter 8 Machine Dependent Features 93 8 107 30 4 Guarded Execution as supports the full range of guarded execution directives for each instruction Just append the directive after the instruction proper The directives are p T T nt TAR ee Execute the instruction if flag f0 is true Execute the instruction if flag f0 is false Execute the instruction if flag fl is true Execute the instruction if flag f1 is false Execute the instruction if both flags f0 and fl are true Execute the instruction if flag f0 is true and flag f1 is false 8 107 30 5 Register Names You can use the predefined symbols ro through r63 to refer to the D30V registers You can also use sp as an alias for r63 and link as an alias for r62 The accumulators are a0 and al The D30V also has predefined symbols
304. rands x86 64 107 222 L L16SI instructions relaxation 195 L16UI instructions relaxation 195 L321 instructions relaxation 195 L8UI instructions relaxation 195 labels Meese eine Al tte gid Ast Mood tats cence 23 label directive TIC5AX 173 labels orita po nenin E RI PHENOM 33 lcomm directive cocido ceremonia ol e 13 ldouble directive M680x0 130 ldouble directive M68HC11 137 ldouble directive TIC54X 172 LDR reg lt label gt pseudo op ARM 82 leafproc directive i960 119 length directive TIC54X 0 oooommmmooo 173 length of symbols o oooooooocoomooo 22 lflags directive ignored 51 line comment character lesse 22 line comment character Alpha ql line comment character AMD 29K 68 line comment character ARM 80 line comment character D10V 88 line comment character D30V 92 line comment character H8 300 95 line comment character H8 500 98 line comment character M680x0 132 line comment character MSP 430 151 line comment character SH 160 line comment character SH64 163 line comment character V850 185 line commen
305. re If stag is missing these become global symbols count adjusts the offset that many times as if element were an array element may be one of byte word long float or any equivalent of those and the structure offset is adjusted accordingly field and string are also allowed the size of field is one bit and string is considered to be one word in size Only element descriptors structure union tags align and conditional assembly directives are allowed within struct endstruct align aligns member offsets to word boundaries only ssize if provided will always be assigned the size of the structure The tag directive in addition to being used to define a structure union ele ment within a structure may be used to apply a structure to a symbol Once applied to label the individual structure elements may be applied to label to produce the desired offsets using label as the structure base Set the tab size in the output listing Ignored 176 Using as utag union name_1 element count_1 name_2 element count_2 tname tag utagx tcount name_n element count_n usize endstruct label tag utag Similar to struct but the offset after each element is reset to zero and the usize is set to the maximum of all defined elements Starting offset for the union is always zero symbol usect section name size blocking flag alignment_flag Reserve space for variables in a named uninitialized sec
306. red for an MCore processor jsri2bsr nojsri2bsr Enable or disable the JSRI to BSR transformation By default this is enabled The command line option nojsri2bsr can be used to disable it Chapter 1 Overview 11 sifilter nosifilter Enable or disable the silicon filter behaviour By default this is disabled The default can be overridden by the sifilter command line option relax Alter jump instructions for long displacements mcpu 210 340 Select the cpu type on the target hardware This controls which instructions can be assembled EB Assemble for a big endian target EL Assemble for a little endian target See the info pages for documentation of the MMIX specific options The following options are available when as is configured for an Xtensa processor density no density Enable or disable use of instructions from the Xtensa code density option This is enabled by default when the Xtensa processor supports the code density option relax no relax Enable or disable instruction relaxation This is enabled by default Note In the current implementation these options also control whether assembler optimizations are performed making these options equivalent to generics and no generics generics no generics Enable or disable all assembler transformations of Xtensa instructions The default is generics no generics should be used only in the rare cases w
307. rejects programs containing this directive entry Mark the beginning of a procedure exit Mark the end of a procedure 102 Using as export name typ 1 param r Make a procedure name available to callers typ if present must be one of absolute code ELF only not SOM data entry data entry millicode plabel pri_prog or sec_prog param if present provides either relocation information for the procedure ar guments and result or a privilege level param may be argwn where n ranges from 0 to 3 and indicates one of four one word arguments rtnval the pro cedure s result or priv_lev privilege level For arguments or the result r specifies how to relocate and must be one of no not relocatable gr argu ment is in general register fr in floating point register or fu upper half of float register For priv_lev r is an integer half n Define a two byte integer constant n synonym for the portable as directive short import name typ Converse of export make a procedure available to call The arguments use the same conventions as the first two arguments for export label name Define name as a label for the current assembly location leave Not yet supported the assembler rejects programs containing this directive origin lc Advance location counter to Ic Synonym for the No value f
308. rence manual with a few noteworthy differences First a colon may immediately follow a label definition This is simply for compatibility with how most assembly language programmers write code Some obscure expression parsing problems may affect hand written code which uses the spop instructions or code which makes significant use of the line separator as is much less forgiving about missing arguments and other similar oversights than the HP assembler as notifies you of missing arguments as syntax errors this is regarded as a feature not a bug Finally as allows you to use an external symbol without explicitly importing the symbol Warning in the future this will be an error for HPPA targets Special characters for HPPA targets include is the line comment character can be used instead of a newline to separate statements Since has no special meaning you may use it in symbol names 8 110 4 Floating Point The HPPA family uses IEEE floating point numbers Chapter 8 Machine Dependent Features 101 8 110 5 HPPA Assembler Directives as for the HPPA supports many additional directives for compatibility with the native assembler This section describes them only briefly For detailed information on HPPA specific assembler directives see HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 as does not support the following assembler directives described in the HP manual endm liston
309. rily 000 52 MSP 430 floating point IEEE 152 MSP 430 identifiersS ooooooooccooooo 151 MSP 430 line comment character 151 MSP 430 machine directives 152 MSP 430 MaG OS visas atrio stg aap RR RR Berne 151 224 MSP 430 opeodes cemere 152 MSP 430 options none sessesse 151 MSP 430 register names iol MSP 430 support eme enrio ede Epai 151 MSP430 Assembler Extensions 151 mul instruction 1386 cuco bees ee bee es 114 mul instruction x86 64 004 114 DAME MP 179 NAME SECO coi sees ere ere nd a 57 Named SECOS emos cta lie 28 names Symbol 22 ieee ga ed E RARI bau 33 naming object file oooooooo 19 new page in listings 45 newblock directive TIC54X 174 newline Xn zi ndice pd aa 24 newline required at file end 23 no density directive ooooooo 196 no generics directive ooooooooooooo o 197 no longcalls directiv iiis esos e eas 197 no relax directive 6 0 00sec cesis 197 nolist directive lese ir 54 nolist directive TIC5AX 173 NOP pseudo op ARM ssssssslsese 82 notes for Alpha iore twm 70 null terminated StridgS 0oooooooccocooooo 42 number constants sees 25 number of macros executed oo oooooocooooo 54 numbered subsections
310. rriage Return for ASCII this is octal code 015 ME Mnemonic for horizontal Tab for ASCII this is octal code 011 Vdigit digit digit An octal character code The numeric code is 3 octal digits For compatibility with other Unix systems 8 and 9 are accepted as digits for example 008 has the value 010 and 009 the value 011 Xx hex digits A hex character code All trailing hex digits are combined Either upper or lower case x works M Represents one V character om Represents one character Needed in strings to represent this character because an unescaped would end the string anything else Any other character when escaped by gives a warning but assembles as if the V was not present The idea is that if you used an escape sequence you clearly didn t want the literal interpretation of the following character However as has no other interpretation so as knows it is giving you the wrong code and warns you of the fact Which characters are escapable and what those escapes represent varies widely among assemblers The current set is what we think the BSD 4 2 assembler recognizes and is a subset of what most C compilers recognize If you are in doubt do not use an escape sequence 3 6 1 2 Characters A single character may be written as a single quote immediately followed by that char acter The same escapes apply to characters as to strings So if you want to write the character backslash you must
311. ructions SETL INCML INCMH and INCH The operand must be a multiple of four Conditional branches A branch instruction is turned into a branch with the complemented condition and prediction bit over five instructions four instructions setting 255 to the operand value which like with GETA must be a multiple of four and a final GO 255 255 0 PUSHJ Similar to expansion for conditional branches four instructions set 255 to the operand value followed by a PUSHGO 255 255 0 JMP Similar to conditional branches and PUSHJ The final instruction is GO 255 255 0 The linker 1d is expected to shrink these expansions for code assembled with relax though not currently implemented 8 121 12 Syntax The assembly syntax is supposed to be upward compatible with that described in Sections 1 3 and 1 4 of The Art of Computer Programming Volume 1 Draft versions of those chapters as well as other MMIX information is located at http www cs faculty stanford edu knuth mmix news html Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files with a few noteworthy exceptions see Section 8 121 13 MMIX mmixal page 149 Before an instruction is emitted the current location is aligned to the next four byte boundary If a label is defined at the beginning of the line its value will be the aligned value In addition to the traditional hex prefix O
312. s gdwarf2 Generate DWARF 2 debugging information for each assembler line This may help debugging assembler code if the debugger can handle it Note this option is only supported by some targets not all of them help Print a summary of the command line options and exit target help Print a summary of all target specific options and exit Idir Add directory dir to the search list for include directives J Don t warn about signed overflow K Issue warnings when difference tables altered for long displacements L keep locals Keep in the symbol table local symbols On traditional a out systems these start with L but different systems have different local label prefixes listing lhs width number Set the maximum width in words of the output data column for an assembler listing to number listing lhs width2 number Set the maximum width in words of the output data column for continuation lines in an assembler listing to number listing rhs width number Set the maximum width of an input source line as displayed in a listing to number bytes listing cont lines number Set the maximum number of lines printed in a listing for a single line of input to number 1 o objfile Name the object file output from as objfile R Fold the data section into the text section statistics Print the maximum space in bytes and total time in seconds used by assem bly strip local absolute Remove lo
313. s command line option MMIX contada avec den cada 145 listing cont lines opi ho die tees 17 IE sting 1hS Width momia o a DER Lr listing lhs width2 2 09 yen s listing rhs width e so dee epe xd 17 longcalls i ds it ERO ad 191 SSMD ci daria rien 19 no construct floatS ooooooocococooooooo 141 SNO deNS1t Yai soe pss ii a eae 191 no expand command line option MMIX 144 SSNO PENETICS rra aaa 191 no longCallS 244 22 4 2A a ad 191 no merge gregs command line option MMIX TIE 144 no predefined syms command line option MMI soso pedo RE de 144 no pushj stubs command line option MMIX o are cba ten be de SU 144 o uva Wr ahd EPQURPPT Y n 191 no stubs command line option MMIX 144 CRO target align i i i44c nas es x d p a 191 no text section literals 191 no underscore command line option CRIS dad iio 83 e A he we vis eerte ieu s 20 SH A dire ted deme PEE as 126 pic command line option CRIS 83 eccprint insn syntaX olo e v eos 134 print opcodeS awa eR YR SE 134 register prefix optional option M680x0 E a A poe 126 214 zu d c CEP 191 relax command line option MMIX 144 esshortebranchs8 212 x ade tages Rs 133 Statistics c cud eh ns REY eines 19 strict direct mode uuu 133 ctarget align 214452 is dob taiii 191 text section literals
314. s also writes to the object file details of the relocation needed To perform relocation 1d must know each time an address in the object file is mentioned e Where in the object file is the beginning of this reference to an address e How long in bytes is this reference e Which section does the address refer to What is the numeric value of 28 Using as address start address of section e Is the reference to an address Program Counter relative In fact every address as ever uses is expressed as section offset into section Further most expressions as computes have this section relative nature For some object formats such as SOM for the HPPA some expressions are symbol relative instead In this manual we use the notation secname N to mean offset N into section secname Apart from text data and bss sections you need to know about the absolute section When 1d mixes partial programs addresses in the absolute section remain unchanged For example address absolute 0 is relocated to run time address 0 by 1d Although the linker never arranges two partial programs data sections with overlapping addresses after linking by definition their absolute sections must overlap Address absolute 239 in one part of a program is always the same address when the program is running as address absolute 239 in any other part of the program The idea of sections is extended to the undefined section Any addre
315. s it down 16 bits and then mutliplies it by the lower 16 bits in register 5 putting the result into register 6 Computes the lower 16 bits of the given expression and stores it into the im mediate operand field of the given instruction For example addi lo here there r5 r6 computes the difference between the address of labels here and there takes the lower 16 bits of this difference and adds it to register 5 putting the result into register 6 Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction For example the following code can be used to compute the address of the label here and store it into register 6 movhi hi here r0 r6 movea lo here r6 r6 The reason for this special behaviour is that movea performs a sign exten sion on its immediate operand So for example if the address of here was OxFFFFFFFF then without the special behaviour of the hi pseudo op the movhi instruction would put OxFFFF0000 into r6 then the movea instruc tion would takes its immediate operand OxFFFF sign extend it to 32 bits OxFFFFFFFF and then add it into r6 giving OxXFFFEFFFF which is wrong the fifth nibble is E With the hi pseudo op adding in the top bit of the lo pseudo op the movhi instruction actually stores 0 into r6 OxFFFF 1
316. s memory usage and makes the code more efficient 2 2 D This option has no effect whatsoever but it is accepted to make it more likely that scripts written for other assemblers also work with as 16 Using as 2 3 Work Faster f should only be used when assembling programs written by a trusted compiler f stops the assembler from doing whitespace and comment preprocessing on the input file s before assembling them See Section 3 1 Preprocessing page 21 6 Warning if you use f when the files actually need to be preprocessed if they contain comments for example as does not work correctly 2 4 include Search Path I path Use this option to add a path to the list of directories as searches for files specified in include directives see Section 7 47 include page 50 You may use I as many times as necessary to include a variety of paths The current working directory is always searched first after that as searches any I directories in the same order as they were specified left to right on the command line 2 5 Difference Tables K as sometimes alters the code emitted for directives of the form word sym1 sym2 see Section 7 99 word page 65 You can use the K option if you want a warning issued when this is done 2 6 Include Local Labels L Labels beginning with L upper case only are called local labels See Section 5 3 Symbol Nam
317. s pads sections if needed to ensure they end on a word sixteen bit boundary An object file written by as has at least three sections any of which may be empty These are named text data and bss sections When it generates COFF or ELF output as can also generate whatever other named sections you specify using the section directive see Section 7 76 section page 57 If you do not use any directives that place output in the text or data sections these sections still exist but are empty When as generates SOM or ELF output for the HPPA as can also generate what ever other named sections you specify using the space and subspace directives See HP9000 Series 800 Assembly Language Reference Manual HP 92432 90001 for details on the space and subspace assembler directives Additionally as uses different names for the standard text data and bss sections when generating SOM output Program text is placed into the CODE section data into DATA and BSS into BSS Within the object file the text section starts at address 0 the data section follows and the bss section follows the data section When generating either SOM or ELF output files on the HPPA the text section starts at address 0 the data section at address 0x4000000 and the bss section follows the data section To let 1d know which data changes when the sections are relocated and how to change that data a
318. s taken as flags to use for the section Each flag is a single character The following flags are recognized b bss section uninitialized data 58 Using as n section is not loaded W writable section d data section r read only section x executable section s shared section meaningful for PE targets a ignored For compatibility with the ELF version If no flags are specified the default flags depend upon the section name If the section name is not recognized the default will be for the section to be loaded and writable Note the n and w flags remove attributes from the section rather than adding them so if they are used on their own it will be as if no flags had been specified at all If the optional argument to the section directive is not quoted it is taken as a sub segment number see Section 4 4 Sub Sections page 29 ELF Version This is one of the ELF section stack manipulation directives The others are subsection see Section 7 87 SubSection page 62 pushsection see Section 7 71 PushSection page 56 popsection see Section 7 66 PopSection page 55 and previous see Section 7 65 Previous page 55 For ELF targets the section directive is used like this section name flags type entsize The optional flags argument is a quoted string which may contain any combination of the following characters a section is allocatable Ww section is writable x section is executable
319. s11 mips2 mips3 mips4 mips5 mips32 mips32r2 mips64 mips64r2 construct floats no construct floats trap no break break no trap mfix7000 mno fix7000 mips16 no mips16 mips3d no mips3d mdmx no mdmx mdebug no mdebug mpdr mno pdr Target MMIX options fixed special register names globalize symbols gnu syntax relax no predefined symbols no expand no merge gregs x linker allocated gregs Target PDP11 options mpic mno pic mall mno extensions mextension mno extension mcpu mmachine Target picoJava options mb me Target PowerPC options mpwrx mpwr2 mpwr m601 mppc mppc32 m603 m604 m403 m405 mppc64 m620 mppc64bridge mbooke mbooke32 mbooke64 mcom many maltivec memb mregnames mno regnames mrelocatable mrelocatable lib mlittle mlittle endian mbig mbig endian Using as Chapter 1 Overview 3 msolaris mno solaris Target SPARC options Av6 Av7 Av8 Asparclet Asparclite Av8plus Av8plusa Av9 Av9a xarch v8plus xarch v8plusa bump 32 1 64 Target TIC54X options mcpu 54 123589 mcpu 54 56 lp mfar mode mf merrors to file lt filename gt me lt filename gt Target Xtensa options no density no relax no generics no text section literals no target al
320. ss whose section is unknown at assembly time is by definition rendered undefined U where U is filled in later Since numbers are always defined the only way to generate an undefined address is to mention an undefined symbol A reference to a named common block would be such a symbol its value is unknown at assembly time so it has section undefined By analogy the word section is used to describe groups of sections in the linked program 1d puts all partial programs text sections in contiguous addresses in the linked program It is customary to refer to the text section of a program meaning all the addresses of all partial programs text sections Likewise for data and bss sections Some sections are manipulated by 1d others are invented for use of as and have no meaning except during assembly 4 2 Linker Sections 1d deals with just four kinds of sections summarized below named sections text section data section These sections hold your program as and 1d treat them as separate but equal sections Anything you can say of one section is true of another When the pro gram is running however it is customary for the text section to be unalterable The text section is often shared among processes it contains instructions con stants and the like The data section of a running program is usually alterable for example C variables would be stored in the data section bss section This section contains zeroed bytes when your progr
321. ssors AMD s K6 and K6 2 processors Cyrix M2 processor and probably others It also supports AMD s 3DNow instruction set SIMD instructions for 32 bit floating point data available on AMD s K6 2 processor and possibly others in the future Currently as does not support Intel s floating point SIMD Katmai KNI The eight 64 bit MMX operands also used by 3DNow are called mm0 mm1 Amm7 They contain eight 8 bit integers four 16 bit integers two 32 bit integers one 64 bit integer or two 32 bit floating point values The MMX registers cannot be used at the same time as the floating point stack See Intel and AMD documentation keeping in mind that the operand order in instruc tions is reversed from the Intel syntax 8 112 22 Writing 16 bit Code While as normally writes only pure 32 bit 1386 code or 64 bit x86 64 code depending on the default configuration it also supports writing code to run in real mode or in 16 bit protected mode code segments To do this put a code16 or codei6gcc directive before the assembly language instructions to be run in 16 bit mode You can switch as back to writing normal 32 bit code with the code32 directive codei6gcc provides experimental support for generating 16 bit code from gcc and differs from code16 in that call ret enter leave push pop pusha popa pushf and popf instructio
322. ssse eese 139 8 120 3 MIPS ECOFF object code 141 8 120 4 Directives for debugging information 142 8 120 5 Directives to override the ISA level 142 8 120 6 Directives for extending MIPS 16 bit instructions PaE aE aX d Re pP PEU Ended 142 8 120 7 Directive to mark data as an instruction 143 8 120 8 Directives to save and restore options 143 8 120 9 Directives to control generation of MIPS ASE instructions ir s eem engen ok ns Sheek E RR 143 MMIX Dependent Features 0 0000 esse 144 8 121 10 Command line Options 144 8 121 11 Instruction expansion esses 145 8 121 12 Syntax cbe eed e re RD n e wees 145 8 121 12 1 Special Characters 145 8 amp 121 12 2 Symbols rede 146 8 121 12 3 Register names 146 8 121 12 4 Assembler Directives 147 8 121 138 Differences to mmixal 149 MSP 430 Dependent Features o oooooooooom o 151 8 122 14 OPUS Vii ia o RR RS 151 8 122 1b Syntax m cer eed obra dns Eu ah s 151 8 122 15 1 M CrTOS 2 one RR s 151 8 122 15 2 Special Characters 151 8 122 15 3 Register Names 151 8 122 15 4 Assembler Extensions 151 8 122 16 Floating Point sess pesman mada spana saasa 151 8 122 17 MSP 430 Machine Directives 152 8 122 18 Opcodes 0 cece eects 152 PDP 11 Dependent Fea
323. subsection prior to this one Multiple previous directives in a row will flip between two sections and their subsections In terms of the section stack this directive swaps the current section with the top section on the section stack 7 66 popsection This is one of the ELF section stack manipulation directives The others are section see Section 7 76 Section page 57 subsection see Section 7 87 SubSection page 62 pushsection see Section 7 71 PushSection page 56 and previous see Section 7 65 Previous page 55 This directive replaces the current section and subsection with the top section and subsection on the section stack This section is popped off the stack 7 67 print string as will print string on the standard output during assembly You must put string in double quotes 56 Using as 7 68 protected names This one of the ELF visibility directives The other two are hidden see Section 7 42 Hidden page 48 and internal see Section 7 49 Internal page 50 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to protected which means that any references to the symbols from within the components that defines them must be resolved to the definition in that component even if a definition in another component would normally preempt this 7 69 psize lines columns Use this directive t
324. t Features 125 as an input register in the left hand instruction For example in this code fragment mv r1 r2 neg r2 r3 register r2 is the destination of the neg instruction and the input to the move instruction instruction is for the M32RX only This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor and the m32rx command line flag has not been specified to allow assembly of such instructions unknown instruction This message is produced when the assembler encounters an instruction which it does not recognise only the NOP instruction can be issued in parallel on the m32r This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the m32rx command line flag has not been specified Only the M32Rx processor is able to execute two instructions in parallel instruction cannot be executed in parallel This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel Instructions share the same execution pipeline This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline Instructions write to the same destination register This message is produced when the assembler encounters a parallel instruction
325. t character Z8000 178 line comment characters CRIS 84 line comment characters MMIX 146 line directive ina 51 line directive AMD 29K 69 line directive MSP 430 152 line numbers in input files 13 line numbers in warnings errors 14 line separator character lusus 22 line separator Alpha oooocooocccccccoo 71 line separator ARM 00000000 80 line separator H8 300 resser isisa torini ti 95 line separator H8 500 ooooooccccoococ oo 98 line separator SH ooooooocccoooc ooo 160 line separator SH64 ooocooocccooomo 163 line separator Z8000 ooooooccocoocccoooo 178 lines starting with amp esee 22 ket eua oet VE eM pepe ia 13 linker and assembler ssuuess 2T linkonce directive 0 cece eee eee 52 list Girechive nai 52 list directive TICBAX o o o oooooo o oo 173 listing control turning off 00 54 listing control turning on 52 listing control new page oooooccccoccoooooo 45 listing control paper SiZO ooooo oooooo o o 56 listing control subtitle 57 Using as listing control title line o oooo 63 listings enabling vejosci n pisar ras 15 literal directlve i eee re mem 197 literal position directive
326. t may insert other instructions between them e g to align a LOOP instruction To prevent the assembler from modifying a series of instructions as a whole use the no generics directive See Section 8 133 10 4 generics page 197 Chapter 8 Machine Dependent Features 193 8 133 7 2 Register Names An initial character is optional in all register names General purpose registers are named a0 a15 Additional registers may be added by processor configuration options In particular the MAC16 option adds a MR register bank Its registers are named mO m3 As a special feature sp is also supported as a synonym for a1 8 133 8 Xtensa Optimizations The optimizations currently supported by as are generation of density instructions where appropriate and automatic branch target alignment 8 133 8 1 Using Density Instructions The Xtensa instruction set has a code density option that provides 16 bit versions of some of the most commonly used opcodes Use of these opcodes can significantly reduce code size When possible the assembler automatically translates generic instructions from the core Xtensa instruction set into equivalent instructions from the Xtensa code density option This translation can be disabled by using specific opcodes see Section 8 133 7 1 Opcode Names page 192 by using the no density command line option see Sec tion 8 133 6 Command Line Options page 191 or by us
327. tailed information about the differences see the Motorola manuals m68000 m68ec000 m68hc000 m68hc001 m68008 m68302 m68306 n68307 m68322 m68356 Assemble for the 68000 m68008 m68302 and so on are syn onyms for m68000 since the chips are the same from the point of view of the assembler m68010 Assemble for the 68010 m68020 m68ec020 Assemble for the 68020 This is normally the default m68030 m68ec030 Assemble for the 68030 m68040 m68ec040 Assemble for the 68040 m68060 m68ec060 Assemble for the 68060 128 8 117 39 Syntax Using as mcpu32 m68330 n68331 n68332 m68333 m68334 m68336 m68340 m68341 m68349 m68360 Assemble for the CPU32 family of chips m5200 m5202 m5204 m5206 m5206e m528x m5307 m5407 ncfv4 mcfv4e Assemble for the ColdFire family of chips m68881 m68882 Assemble 68881 floating point instructions This is the default for the 68020 68030 and the CPU32 The 68040 and 68060 always support floating point instructions mno 68881 Do not assemble 68881 floating point instructions This is the de fault for 68000 and the 68010 The 68040 and 68060 always support floating point instructions even if this option is used m688
328. the ELF visibility directives The other two are internal see Section 7 49 internal page 50 and protected see Section 7 68 protected page 56 This directive overrides the named symbols default visibility which is set by their bind ing local global or weak The directive sets the visibility to hidden which means that the symbols are not visible to other components Such symbols are always considered to be protected as well 7 43 hword expressions This expects zero or more expressions and emits a 16 bit number for each This directive is a synonym for short depending on the target architecture it may also be a synonym for word 7 44 ident This directive is used by some assemblers to place tags in object files as simply accepts the directive for source file compatibility with such assemblers but does not actually emit anything for it 7 45 if absolute expression if marks the beginning of a section of code which is only considered part of the source program being assembled if the argument which must be an absolute expression is non zero The end of the conditional section of code must be marked by endif see Section 7 30 endif page 46 optionally you may include code for the alternative condition flagged by else see Section 7 25 else page 45 If you have several conditions to check elseif may be used to avoid nesting blocks if else within each subsequent else block The follow
329. the boundary case The float directive produces f format numbers The double directive produces d format numbers 8 131 26 Vax Machine Directives The Vax version of the assembler supports four directives for generating Vax floating point constants They are described in the table below dfloat This expects zero or more flonums separated by commas and assembles Vax d format 64 bit floating point constants ffloat This expects zero or more flonums separated by commas and assembles Vax f format 32 bit floating point constants gfloat This expects zero or more flonums separated by commas and assembles Vax 8 g format 64 bit floating point constants hfloat This expects zero or more flonums separated by commas and assembles Vax h format 128 bit floating point constants 182 Using as 8 131 27 VAX Opcodes All DEC mnemonics are supported Beware that case instructions have exactly 3 operands The dispatch table that follows the case instruction should be made with word statements This is compatible with all unix assemblers we know of 8 131 28 VAX Branch Improvement Certain pseudo opcodes are permitted They are for branch instructions They expand to the shortest branch instruction that reaches the target Generally these mnemonics are made by substituting j for b at the start of a DEC mnemonic This feature is included both for compatibility and to help compilers If you do not need this feature avoi
330. the same sense It complements the GNU General Public License which is a copyleft license designed for free software We have designed this License in order to use it for manuals for free software because free software needs free documentation a free program should come with manuals providing the same freedoms that the software does But this License is not limited to software manuals it can be used for any textual work regardless of subject matter or whether it is published as a printed book We recommend this License principally for works whose purpose is instruction or reference APPLICABILITY AND DEFINITIONS This License applies to any manual or other work that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License The Document below refers to any such manual or work Any member of the public is a licensee and is addressed as you A Modified Version of the Document means any work containing the Document or a portion of it either copied verbatim or with modifications and or translated into another language A Secondary Section is a named appendix or a front matter section of the Document that deals exclusively with the relationship of the publishers or authors of the Document to the Document s overall subject or to related matters and contains nothing that could fall directly within that overall subject For example if the Document is in part a te
331. tion is used as will attempt to optimize its output by detecting when instructions can be executed in parallel nowarnswap To optimize execution performance as will sometimes swap the order of in structions Normally this generates a warning When this option is used no warning will be generated when instructions are swapped gstabs packing no gstabs packing as packs adjacent short instructions into a single packed instruction no gstabs packing turns instruction packing off if gstabs is specified as well gstabs packing the default turns instruction packing on even when gstabs is specified 8 106 26 Syntax The D10V syntax is based on the syntax in Mitsubishi s D10V architecture manual The differences are detailed below 8 106 26 1 Size Modifiers The D10V version of as uses the instruction names in the D10V Architecture Manual However the names in the manual are sometimes ambiguous There are instruction names that can assemble to a short or long form opcode How does the assembler pick the correct form as will always pick the smallest form if it can When dealing with a symbol that is not defined yet when a line is being assembled it will always use the long form If you need to force the assembler to use either the short or long form of the instruction you can append either s short or 1 long to it For example if you are writing an assembly program and you wa
332. tion similar to bss usect allows definitions sections independent of bss symbol points to the first location reserved by this allocation The symbol may be used as a variable name size is the allocated size in words blocking flag indicates whether to block this section on a page boundary 128 words see Section 8 129 10 TIC54X Block page 168 alignment flag indicates whether the section should be longword aligned var sym sym n Define a subsym to be a local variable within a macro See See Section 8 129 18 TIC54X Macros page 176 Vversion version Set which processor to build instructions for Though the following values are accepted the op is ignored 541 542 543 545 545LP 546LP 548 549 8 129 18 Macros Macros do not require explicit dereferencing of arguments i e ARG During macro expansion the macro parameters are converted to subsyms If the number of arguments passed the macro invocation exceeds the number of parameters defined the last parameter is assigned the string equivalent of all remaining arguments If fewer arguments are given than parameters the missing parameters are assigned empty strings To include a comma in an argument you must enclose the argument in quotes The following built in subsym functions allow examination of the string value of subsyms or ordinary strings The arguments are strings unless otherwise indicated subsyms passed as args will be replaced by the strings they
333. tives to be simultaneously outstanding one in the text section and one in another section typically the data section This feature allows dynamically loaded objects to be implemented in a relatively straightforward way A using directive must always be specified 106 Using as in the text section this will specify the base register that will be used for branches in the text section A second using may be specified in another section this will specify the base register that is used for non label address literals When a second using is specified then the subsequent 1torg must be put in the same section otherwise an error will result Thus for example the following code uses r3 to address branch targets and r4 to address the literal pool which has been written to the data section The is the constants A some_routine H 42 and E 3 1416 will all appear in the data section data using LITPOOL r4 text BASR r3 0 using r3 B START long LITPOOL START L r4 4 r3 L r 5 A some routine LTR rid5 r15 BNE LABEL AH r0 H 42 LABEL ME r6 E 3 1416 data LITPOOL ltorg Note that this dual using directive semantics extends and is not compatible with HLASM semantics Note that this assembler directive does not support the full range of HLASM semantics 8 111 12 Opcodes For detailed information on the ESA 390 machine instruction set see ESA 390 Princi ples of Operation IBM Publi
334. tor character 22 statement separator Alpha 71 statement separator ARM 80 statement separator H8 300 ssss 95 statement separator H8 500 98 statement separator SH 160 statement separator SH64 163 statement separator Z8000 178 Index statements structure of oooocooocccooo o 22 statistics about assembly 19 stopping the assembly 00 05 41 String constantis esris rada id 23 String directive cese heer ieee iEn ed 62 string directive on HPPA 102 string directive M88K ooo o ooooo o 138 string directive TIC54X 175 sting teralsis calido 42 string copying to object file 62 struct difectiy me oops ii 62 struct directive TICBAX 175 structure debugging COFF 63 sub instruction ordering D10V 88 sub instruction ordering D30V 92 sub instructions D10V o ooooocccooocooooo 8T sub instructions D30V oooooocccooocooooo 91 SUDEXPLeESSIONS ciencia Ot subsection directive 0000 62 subsym builtins TIC54X 00 176 subtitles for listingS o oooooooooooooo 57 subtraction permitted arguments 38 summary Of options 2 ie eet RE d hee bs il SUPDO Diosa a a e oon BE
335. ts a comment anywhere on the line causing all characters up to the end of the line to be ignored A character is handled as a line separator equivalent to a logical new line character except in a comment so separate instructions can be specified on a single line 8 105 24 2 Symbols in position independent code When generating position independent code SVR4 PIC for use in cris axis linux gnu shared libraries symbol suffixes are used to specify what kind of run time symbol lookup will be used expressed in the object as different relocation types Usually all absolute symbol values must be located in a table the global offset table leaving the code position independent independent of values of global symbols and independent of the address of the code The suffix modifies the value of the symbol into for example an index into the global offset table where the real symbol value is entered or a PC relative value or a value relative to the start of the global offset table All symbol suffixes start with the character omitted in the list below Every symbol use in code or a read only section must therefore have a PIC suffix to enable a useful shared library to be created Usually these constructs must not be used with an additive constant offset as is usually allowed i e no 4 as in symbol 4 is allowed This restriction is checked at link time not at assembly time GOT Attaching this suffix to a symbol in an instruction
336. tual address of the label regardless of what type of label it is 8 127 3 SH64 Machine Directives In addition to the SH directives the SH64 provides the following directives mode shmedia shcompact isa shmedia shcompact Specify the ISA for the following instructions the two directives are equivalent Note that programs such as objdump rely on symbolic labels to determine when such mode switches occur by checking the least significant bit of the label s address so such mode isa changes should always be followed by a label in practice this is true anyway Note that you cannot use these directives if you didn t specify an ISA on the command line abi 32164 Specify the ABI for the following instructions Note that you cannot use this di rective unless you specified an ABI on the command line and the ABls specified must match uaquad Like uaword and ualong this allows you to specify an intentionally unaligned quadword 64 bit word Chapter 8 Machine Dependent Features 165 8 127 4 Opcodes For detailed information on the SH64 machine instruction set see SuperH 64 bit RISC Series Architecture Manual SuperH Inc as implements all the standard SH64 opcodes In addition the following pseudo opcodes may be expanded into one or more alternate opcodes movi If the value doesn t fit into a standard movi opcode as will replace the movi with a sequence of movi and shori opcodes pt This expands to a sequence of mo
337. tures 0 00000 153 8 123 19 Options siati seug ia gi puin Re eee wee nee a 153 8 123 19 1 Code Generation Options 153 8 123 19 2 Instruction Set Extension Options 153 8 123 19 3 CPU Model Options 154 8 123 19 4 Machine Model Options 154 8 123 20 Assembler Directives o 155 Using as 8 124 8 125 8 126 8 127 8 128 8 129 8 130 8 123 21 PDP 11 Assembly Language Syntax 155 8 123 22 Instruction Naming 0 155 8 123 23 Synthetic Instructions 156 picoJava Dependent Features 0 00 eee ee 157 8 124 1 Options coercere ober eb eet ds 157 PowerPC Dependent Features o o oooooooooo 158 8 125 2 OPiS cecus Rb eek bee eee ae 158 Renesas SuperH SH Dependent Features 160 8126 1 Optlons uan ld deeds 160 8 120 2 INMI mirad diia ira 160 8 126 2 1 Special Characters 160 8 126 2 2 Register Names 160 8 126 2 3 Addressing Modes 160 8 126 3 Floating Point 0 cee eee 161 8 126 4 SH Machine Directives 0oooooooooo o 161 8126 5 OpCodesiiciictau cade e ete a nes 161 SuperH SH64 Dependent Features o o o o o 163 8 127 l Options ca corona ede eae 163 8 127 2 SYNTA a seater xe ora e y os ee Saeed 163 8 127 2 1 Special Characters 163 8 127 2 2 Register Names
338. uate the contents of string string and assign the result as a string to the subsym name String replacement is performed on string before assignment bss symbol size blocking flag alignment_flag Reserve space for symbol in the bss section size is in words If present block ing flag indicates the allocated space should be aligned on a page boundary if it would otherwise cross a page boundary If present alignment flag causes the assembler to allocate size on a long word boundary byte value value n ubyte value value n char value value n uchar value value n Place one or more bytes into consecutive words of the current section The upper 8 bits of each word is zero filled If a label is used it points to the word allocated for the first byte encountered clink section name Set STYP CLINK flag for this section which indicates to the linker that if no symbols from this section are referenced the section should not be included in the link If section name is omitted the current section is used c_mode TBD copy filename filename include filename filename Read source statements from filename The normal include search path is used Normally copy will cause statements from the included file to be printed in the assembly listing and include will not but this distinction is not currently implemented data Begin assembling code into the data section double value val
339. ude the value of expression This can occasionally be useful inside complex nested macros or conditional assembly Chapter 7 Assembler Directives 47 7 37 file string file tells as that we are about to start a new logical file string is the new file name In general the filename is recognized whether or not it is surrounded by quotes but if you wish to specify an empty file name you must give the quotes This statement may go away in future it is only recognized to be compatible with old as programs In some configurations of as file has already been removed to avoid conflicts with other assemblers See Chapter 8 Machine Dependencies page 67 7 38 fill repeat size value repeat size and value are absolute expressions This emits repeat copies of size bytes Repeat may be zero or more Size may be zero or more but if it is more than 8 then it is deemed to have the value 8 compatible with other people s assemblers The contents of each repeat bytes is taken from an 8 byte number The highest order 4 bytes are zero The lowest order 4 bytes are value rendered in the byte order of an integer on the computer as is assembling for Each size bytes in a repetition is taken from the lowest order size bytes of this number Again this bizarre behavior is compatible with other people s assemblers size and value are optional If the second comma and value are absent value is assumed zero If the first comma and followi
340. ue n ldouble value value n float value value n xfloat value value n Place an IEEE single precision floating point representation of one or more floating point values into the current section All but xfloat align the result on a longword boundary Values are stored most significant word first drlist drnolist Control printing of directives to the listing file Ignored emsg string mmsg string wnsg string Emit a user defined error message or warning respectively Chapter 8 Machine Dependent Features 173 far mode Use extended addressing when assembling statements This should appear only once per file and is equivalent to the mfar mode option see Section 8 129 9 mf ar mode page 168 fclist fcnolist Control printing of false conditional blocks to the listing file field value size Initialize a bitfield of size bits in the current section If value is relocatable then size must be 16 size defaults to 16 bits If value does not fit into size bits the value will be truncated Successive field directives will pack starting at the current word filling the most significant bits first and aligning to the start of the next word if the field size does not fit into the space remaining in the current word A align directive with an operand of 1 will force the next field directive to begin packing into a new word If a label is used it points to the word that contains the specified field
341. umber or its negative takes more than 32 bits to represent in binary The distinction is made because in some places integers are permitted while bignums are not 3 6 2 3 Flonums A flonum represents a floating point number The translation is indirect a decimal floating point number from the text is converted by as to a generic binary floating point number of more than sufficient precision This generic floating point number is converted to a particular computer s floating point format or formats by a portion of as specialized to that computer A flonum is written by writing in order e The digit 0 0 is optional on the HPPA e A letter to tell as the rest of the number is a flonum e is recommended Case is not important On the H8 300 H8 500 Renesas SuperH SH and AMD 29K architectures the letter must be one of the letters DFPRSX in upper or lower case On the ARC the letter must be one of the letters DFRS in upper or lower case On the Intel 960 architecture the letter must be one of the letters DFT in upper or lower case On the HPPA architecture the letter must be E upper case only e An optional sign either or e An optional integer part zero or more decimal digits 26 Using as e An optional fractional part followed by zero or more decimal digits e An optional exponent consisting of e An E or e e Optional sign either
342. us 179 global directive iei ase e Rs 4T global directive TIC54X oooooooooo 173 gp register MIPS cocida 142 Ep register V850 correr ei 185 grouping datas desir pb RR dais 29 Using as H H8 300 addressing modes 0oooccoccccccco 95 H8 300 floating point IEEE 96 H8 300 line comment character 95 H8 300 line separator ooooccocccoccccccooo 95 H8 300 machine directives none 97 H8 300 opcode summary ooccoccccccccccooo 97 H8 300 options none ssseesesss 95 H8 300 registers ooocoocccocccocccccco 95 H8 300 size suffixes 0 0000000000000 97 H8 300 SUPPOT Dio oce erem ro Rm Ren 95 H8 300H assembling for o ooooccocccoo 97 H8 500 addressing modes 0oooccoccccccoo 98 H8 500 floating point IEEE 99 H8 500 line comment character 98 H8 500 line separator 0 0 000000 98 H8 500 machine directives none 99 H8 500 opcode summary 0 205 99 H8 500 options none sssessuess 98 H8 500 registers esses 98 H8 500 support ssessee ee 98 half directive ARC 000000 78 half directive M88K o oooooc ooooo oo 138 half directive SPARC 000 167 half directive TIC54X 173 hex character code xd e000 eee eee eee 24 hexadecimal integers oooooooo 25 hfloat directive
343. vi and shori opcode followed by a ptrel opcode or to a pta or ptb opcode depending on the label referenced 166 Using as 8 128 SPARC Dependent Features 8 128 5 Options The SPARC chip family includes several successive levels using the same core instruction set but including a few additional instructions at each level There are exceptions to this however For details on what instructions each variant supports please see the chip s architecture reference manual By default as assumes the core instruction set SPARC v6 but bumps the archi tecture level as needed it switches to successively higher architectures as it encounters instructions that only exist in the higher levels If not configured for SPARC v9 sparc64 GAS will not bump passed sparclite by default an option must be passed to enable the v9 instructions GAS treats sparclite as being compatible with v8 unless an architecture is explicitly requested SPARC v9 is always incompatible with sparclite Av6 Av7 Av8 Asparclet Asparclite Av8plus Av8plusa Av9 Av9a Use one of the A options to select one of the SPARC architectures explicitly If you select an architecture explicitly as reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level Av8plus and Av8plusa select a 32 bit environment Av9 and Av9a select a 64 bit environment and are not available unl
344. w 0x00008000 Produces the correct result in r0 whereas seth r0 shigh 0x00008000 or3 r0 rO low 0x00008000 Stores Oxffff8000 into r0 Note the shigh directive does not know where in the assembly source code the lower 16 bits of the value are going set so it cannot check to make sure that an or3 instruction is being used rather than an add3 instruction It is up to the programmer to make sure that correct directives are used 8 116 37 M32R Warnings There are several warning and error messages that can be produced by as which are specific to the M32R output of 1st instruction is the same as an input to 2nd instruction is this intentional This message is only produced if warnings for explicit parallel conflicts have been enabled It indicates that the assembler has encountered a parallel in struction in which the destination register of the left hand instruction is used as an input register in the right hand instruction For example in this code fragment mv r1 r2 neg r3 r1 register rl is the destination of the move instruction and the input to the neg instruction output of 2nd instruction is the same as an input to 1st instruction is this intentional This message is only produced if warnings for explicit parallel conflicts have been enabled It indicates that the assembler has encountered a parallel in struction in which the destination register of the right hand instruction is used Chapter 8 Machine Dependen
345. x a hexadecimal number can also be specified by the prefix character After all operands to an MMIX instruction or directive have been specified the rest of the line is ignored treated as a comment 146 Using as 8 121 12 1 Special Characters The characters and are line comment characters each start a comment at the beginning of a line but only at the beginning of a line A prefixes a hexadecimal number if found elsewhere on a line Two other characters and each start a comment anywhere on the line Thus you can t use the modulus and not operators in expressions normally associated with these two characters A is a line separator treated as a new line so separate instructions can be specified on a single line 8 121 12 2 Symbols The character is permitted in identifiers There are two exceptions to it being treated as any other symbol character if a symbol begins with it means that the symbol is in the global namespace and that the current prefix should not be prepended to that symbol see MMIX prefix page 149 The is then not considered part of the symbol For a symbol in the label position first on a line a at the end of a symbol is silently stripped off A label is permitted but not required to be followed by a as with many other assembly formats The character in an expression is a synonym for
346. xample sld w tdaoff a variable ep r6 loads the contents of the location pointed to by the label _a_variable into register 6 provided that the label is located somewhere within 256 bytes of the address held in the EP register Note the linker assumes that the EP register contains a fixed address set to the address of the label called __ep This can either be set up automatically by the linker or specifically set by using the defsym __ep lt value gt command line option Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction For example movea zdaoff a variable zero r6 puts the address of the label _a_variable into register 6 assuming that the label is somewhere within the first 32K of memory Strictly speaking it also possible to access the last 32K of memory as well as the offsets are signed Computes the offset of the named variable from the start of the Call Table Area whoes address is helg in system register 20 the CTBP register and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data For example callt ctoff table funci will put the call the function whoes address is held in the call table at the location labeled table func1 longcall name Indicates that the following sequence of instructions is a long call to
347. xes 0 00 cee eee eee 107 x86 64 source destination operands 107 x86 04 SPPON trocear RE 107 x86 64 syntax compatibility 107 xfloat directive TIC54X 172 xlong directive TIC54X ooooooooooo o 173 Xtensa architecture oooo ooooccoooooo 191 Xtensa assembler syntax oooooooocooooo 192 Xtensa density option 00 191 Xtensa directives ooo oooooccmooomm m o 196 Xtensa opcode names eee eee 192 Xtensa register Names oooooooooooo 193 xword directive SPARC 0 167 Z Z800 addressing modes sese 178 28000 directives oooooococoocccooccoo 179 Z8000 line comment character 178 28000 line separator 000000 178 48000 opcode summary sese 180 ZB8000 Options 2 22 rhe e a 178 Z8000 registers eee 178 Z8000 support fem e RE ROI 178 zdaoff pseudo op V850 00 189 zero register V850 ooo ooooomoooooo 185 zero terminated StridgS ooooooooooo o 42 Table of Contents l OVGEVIOW 94 605552056 626 454 rear 5058 1 1 Structure of this Manual 0 0 00 eee eee ee ee 1 2 The GNU Assembler 00 00 cece eee eee eee 1 3 Object File Formats 0 0 c cece eee eee ees L4 Command Lime cd diet eae eas 1 5 Input E168 2 2 od Crate HE e ent ed nte oos Lo Output Object Fleur big
348. xpecting zero or more EXPRES SIONS separated by commas For each expression a 32 bit little endian con stant is emitted syntax ARGUMENT The syntax directive takes as ARGUMENT one of the following case sensitive choices no_register_prefix The syntax no_register_prefix directive makes a character prefix on all registers optional It overrides a previous setting in cluding the corresponding effect of the option no underscore If this directive is used when ordinary symbols do not have a _ 86 Using as character prefix care must be taken to avoid ambiguities whether an operand is a register or a symbol using symbols with names the same as general or special registers then invoke undefined behavior register_prefix This directive makes a character prefix on all registers manda tory It overrides a previous setting including the corresponding effect of the option underscore leading_underscore This is an assertion directive emitting an error if the no underscore option is in effect no_leading_underscore This is the opposite of the syntax leading_underscore directive and emits an error if the option underscore is in effect Chapter 8 Machine Dependent Features 87 8 106 D10V Dependent Features 8 106 25 D10V Options The Mitsubishi D10V version of as has a few machine dependent options 0 The D10V can often execute two sub instructions in parallel When this op
349. xtbook of mathematics a Secondary Section may not explain any mathematics The relationship could be a matter of historical connection with the subject or with related matters or of legal commercial philosophical ethical or political position regarding them The Invariant Sections are certain Secondary Sections whose titles are designated as being those of Invariant Sections in the notice that says that the Document is released under this License 208 Using as The Cover Texts are certain short passages of text that are listed as Front Cover Texts or Back Cover Texts in the notice that says that the Document is released under this License A Transparent copy of the Document means a machine readable copy represented in a format whose specification is available to the general public whose contents can be viewed and edited directly and straightforwardly with generic text editors or for images composed of pixels generic paint programs or for drawings some widely avail able drawing editor and that is suitable for input to text formatters or for automatic translation to a variety of formats suitable for input to text formatters copy made in an otherwise Transparent file format whose markup has been designed to thwart or discourage subsequent modification by readers is not Transparent A copy that is not Transparent is called Opaque Examples of suitable formats for Transparent copies include plain A
350. y The set nomips3d directive prevents MIPS 3D instructions from being accepted The directive set mdmx makes the assembler accept instructions from the MDMX Ap plication Specific Extension from that point on in the assembly The set nomdmx directive prevents MDMX instructions from being accepted Traditional MIPS assemblers do not support these directives 144 Using as 8 121 MMIX Dependent Features 8 121 10 Command line Options The MMIX version of as has some machine dependent options When fixed special register names is specified only the register names speci fied in Section 8 121 12 3 MMIX Regs page 146 are recognized in the instructions PUT and GET You can use the globalize symbols to make all symbols global This option is useful when splitting up a mmixal program into several files 3 The gnu syntax turns off most syntax compatibility with mmixal Its usability is currently doubtful The relax option is not fully supported but will eventually make the object file prepared for linker relaxation If you want to avoid inadvertently calling a predefined symbol and would rather get an error for example when using as with a compiler or other machine generated code specify no predefined syms This turns off built in predefined definitions of all such symbols including rounding mode symbols segment symbols BIT symbols and TRAP symbols used in mmix system calls It also turns off
351. y the position of the literal directive Using this directive gives the assembler freedom to locate the literal data in the most appropriate place and possibly to combine identical literals For example the code entry sp 40 literal L1 sym 132r a4 L1 198 Using as can be used to load a pointer to the symbol sym into register a4 The value of sym will not be placed between the ENTRY and L32R instructions instead the assembler puts the data in a literal pool By default literal pools are placed in a separate section however when using the text section literals option see Section 8 133 6 Command Line Options page 191 the literal pools are placed in the current section These text section literal pools are created automatically before ENTRY instructions and manually after literal_position directives see Section 8 133 10 6 literal_position page 198 If there are no preceding ENTRY instructions or literal_position directives the assembler will print a warning and place the literal pool at the beginning of the current section In such cases explicit literal_position directives should be used to place the literal pools 8 133 10 6 literal_position When using text section literals to place literals inline in the section being assembled the literal_position directive can be used to mark a potential location for a literal pool literal_position The literal_position directive is ignored when the

Using as

Contents

Download Pdf Manuals

Related Search

Related Contents