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Series IP1K110 Industrial I/O Pack Reconfigurable Digital

1. al E av3H NVd 9 X ZW w CT CT LO YOLOSNNOO ld u J r1 GuvOd 40 MJOVdS 391 LNS3NOdWOO 9 lt CW 1 JINGON 40 3015 INJ3NOdNWOO LIT N LI M3MOS QV3H 1V 14 OR 9 X ZN 1 22 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com RECONFIGURABLE DIGITAL MODULE SERIES IP1K110 INDUSTRIAL I O PACK 79 108 318v9 IWNOIS 066 4206 1380 SH38NnN 1494 9 LYVd LIOIG N3A3S 310N 1NOJ 3313Y 315 1 1530 SI L Nid 2165 9001 318VO NO 3O103NNOO x Nac 27 1128 2002 96 900 2158 9001 NOIO3NNOO aay MAIA 401 1334 lt X T3Nvd 9d Sd NO 0 1 QNVOB 91459 265 6206 13008 0996 0 963AAV a al ld 24 JU VWN3HOS 08469 4209 13490 iD s TO CN
2. 00 r 1 st IO 23 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE TO MODEL 5025 552 TERMINATION PANEL 50 PIN CONNECTOR 1004 512 KEY PIN 1 k 4501 46 5 1 T pe 1 N 11 1 1 I 1 r 55 E idi 52 5 e 3 N 23 i 1 S E I s en 1 5 207 zi uu x e NN NN z be ni gee 3 287 85 d sie TM IEEE X dl bes Tem E gt 282 E e e SADRONIMNATSD E i sooo oo E 00 NN eee Q9 0 r Q 10 s T0 ON N a SS wt w S02 828 Zon ZOO MANNNNNNNNANN ee ee eee ee O49 TO VI SE 9 NI P2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 K
3. Y 891 4 dl NOILLVOTIddV 50 21901 4 1 SNE LdNYYSLNI ONIQOO3Q 553 00 508 58415948 SNLVLS 1 SMH31SI93M 104 Igne 3L 58415944 5 151934 84 503151939 318VN3 LdNdyslNi NOLIVM3N39 58415938 1081 NOILOAYIG 49019 SH3lSIO3M I3NNVHO LNdLNO LANI VOd4 011314 NOWINOO 5 SI 86 i 2011 1 9807 000 l SYJAIJ SNYYL 0 ILL 1 n 508 NOIIO3HIO iy P8207 N n8 INdLNO LANI Ps m 2 00071 000 1 94 9850 S3AIOSNVML 207 108 335 ATNNHBIX3 1S0 ONY 38 AV 14 YOLSISSY NOILVNINYSL ILON 20 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com RECONFIGURABLE DIGITAL MODULE SERIES IP1K110 INDUSTRIAL I O PACK 1997 SNOISSINW3 3O9NVQ3dWI MOT 530 9 JHL ANY 3SION 330WN NONWNOO Q39fnQNI X04 HLVd
4. Altera Maxplus ASCII text file that stores information about connected pin and device assignments as well as configuration settings for the Compiler Simulator and Timing Analyzer for an entire project File can be imported to Quartus II Clock Generator Clock Generator Cypress CY22150 Frequency range 250KHz to 100MHz C executable program which provides the register values need to program the clock generator chip for your selected frequency This program is included in the Engineering Design kit for the IP1K110 1 The final letter of the file name indicates revision number and may differ from the files provided BitCalc2k1 exe 18 APPENDIX CABLE MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded cable according to model number The shielded cable is highly recommended for optimum performance with analog input or output modules Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 APC8610 or APC8620 1 non intelligent carrier board connectors both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise
5. Pola ojo NIN mia 99 Table 2 2 IP1K110 Model Channel Assignments Noise and Grounding Considerations The IP1K110 is non isolated between the logic and field I O grounds since output common is electrically connected to the IP module ground Consequently the field I O connections are not isolated from the carrier board and backplane Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce impedance drops and switching transients However care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections To minimize high levels of EMI the signal ground connection at the field I O port pin 50 should be used to provide a path for induced common mode noise and currents The ground path provides a low impedance path to reduce emissions EIA RS485 RS422 communication distances are generally limited to less than 4000 feet To minimize transmission line problems all nodes connected to the cable must use minimum stub length connections The optimal configuration for the RS485 RS422 bus is a daisy chain connection from node 1 to node 2 to node 3 to node n The bus must form a single continuous path and the nodes in the middle of the bus must not Register Bits See Table 2 1 for Pin Assignments IP1K110 0024 Differential RS485 Channels 0 to 23 IP1K11
6. OL GASN 38 LSNW NO JHL IWS JO T3A31 3ZININIW OL NOIHSV4 NIVHO V NI G3193NNOO GINOHS S3GON TIY ATIVAC SNOILOSNNOO 1H9N31 811 3SN ISAW 318v9 3HL OL Q3193NNOO S3Q00N 71 SW31803Md 3NIT NOISSIASNVMLE 3ZIWININ 1 51548 39V Id NI NOLLVNIAS3 IL OY NV ONISN NOILVdISSIG 3ZIWININ 01 91815504 OSIY SI MOT SI VIVG ANY 5 SI 318VO 3 1818SOd SI SIHL 440 1431 38 NYO 5940151534 NOILVdISSIO N3MOd 3ZINININ OL SNOILO3 1H3H 3NI 1 NOISSINSNVH L SSYSAGV LIN3A33d SI NOLLVNIWH31 40 35048404 300N HOV3 lv LON 508 SHL JO SQN3 3A331X3 3HL LV 93499071 AINO 5 38 GINOHS NOLLVNIWH31 AWIL V LY SAILOV 38 5 AINO 108 SNE TVNOILO3NIO I8 AVH v SI SNA JHL 508 5 OL 03193NNOO 38 OL SSHHAIO3S SJAINHG EE OL SMOTIV GYVONVLS 987 504 FHL 21901 FINGOW 31907 FINGON CHANNEL 1 0 DIRECTION H 170 CHANNEL DIRECTION L N LINN 2 LINN 170 1 0 170 21901 SINGOW 0 1 TANNVHO 0 1 AA id N LINN LINN AYOMLIN LNIOdILINW X31dnQ S8vSM SALON NOILLO3IG TINNYHO
7. MODEL 5025 551 SCHEMATIC 24 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1 12 34 5 6 7 9 10 111213 14 15 16 17 18 19 20 21 22 2324 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TB1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC 3 032 77 0 TB1 9 eu C Qc U OG 9 UO UO XO C v IT GO 9G G2 CO QU OQ Og UO 0 0o OC 0 9o 0 C C Y lt 5 515 135 0 TOP VIEW 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 56 40 42 44 46 48 50 1 3 5 7 9 1113 15 17 19 2123 25 27 29 31 33 35 37 39 41 43 45 47 49 2 205 5
8. 07 e Interrupt Vector Not Used Register Bit 0 controls operation of the IP1K110 in user mode and configuration mode via control of pin 168 of the Altera FPGA When bit 0 is set to logic low the IP1K110 will be in user mode Setting bit 0 to a logic high places the IP1K110 in configuration mode Upon issue of an IP bus reset this register bit will be clear placing the IP1K110 in user mode Also initial configuration of the Altera FPGA sets bit 0 to a logic low holding the FPGA in user mode Bits 10 to 8 are used to set the IP1K110 model corresponding to your mix This will allow the Altera FPGA to properly map Input Output registers to the 1 transceivers present on your module Bits 10 to 8 should be set as identified in the following table to identify the model corresponding to your Memory Data Register IP1K110 Control Register Bits 10 9 and 8 IP Model Disabled Memory Address Register Clock Control Register 1 IP1K110 2412 IP1K110 4800 Ee IP1K110 0024 o o 1 1 o o Doi d oo i Clock Control Register 2 Bit 11 is reserved for factory testing See EDK documentation for further details For normal operation this bit Clock Control should be set to logic low NOT USED Register 3 Bit 15 can be used to issue a software reset When bit 15 is Clock Generator set to a logic high a software reset will occur NOT USED Trigger Register
9. Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 Channel read or write operations use 8 bit or 16 bit data transfers The upper 8 bits of this register are Not Used and will always read low 0 s for D16 accesses Note that interrupts will not occur unless they are enabled All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the digital input channel Interrupt Polarity Register Interrupt Status Registers Read Write Base OFH The Interrupt Status Register reflects the status of each of the interrupting channels A 1 bit indicates that an interrupt is pending for the corresponding channel A channel that does not have interrupts enabled will never set its interrupt status flag A 5 interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status Register writing a 1 acts as a reset signal to clear the set state This is known as the Release On Register Access RORA method as defined in the VME System architecture specification However if the condition which caused the interrupt to occur remains the interrupt will be generated again unless disabled via the Interrupt Enable Register In addition an interrupt will be generated if any of the channels enabled for interrupt have an interrupt pending i e one that has not been cleared Writing 0 to a bit location has no effect t
10. as 2 1 unanimi i diets a ft PA M BE A q q Y FRONT VIEW e 805 1 09 8 29 lt 10 31 261 9 gt 5 MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 465 NOTE DIMENSIONS ARE IN INCHES MILLIMETERS 25 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
11. Reading this register will return logic low on all data lines bits except for bits 11 to 8 bit 0 which will reflect their last written NOT USED state Notes Table 3 3 1 The IP will respond to addresses that are Not Used with an active IP module acknowledge Data read at Not Used addresses will be driven low 8 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE Input Output Registers The register bits not listed will not be used See the memory Read Write Base 02H to 07H map to identify the addresses required to control I O registers Forty eight possible input output channels numbered 0 Table 3 4 Input Output Registers through 47 may be individually accessed via these registers The Input Output Channel registers are used to monitor read or Register Bits set write channels 0 through 47 The first eight channels are aL mm See Table 2 1 for Pin Assignments accessed at the carrier base address 03H via the low data byte IP1K110 0024 Differential RS485 Channels 0 to 23 The next eight channels are accessed at the carrier base address Hita Register Bits 0 to 23 02H via the high data byte The remaining 32 channels are IP1K110 2412 Differential RS485 TTL Channels accessed similarly at the carrier base address offsets shown in Channels 12 to 23 0 to 23 Tables Re
12. The IP1K110 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density and is an ideal choice for a wide range of industrial control and monitor applications that require high density high reliability and high performance at a low cost KEY IP1K110 FEATURES Reconfigurable Altera FPGA In system configuration of a 100 000 gate FPGA is implemented via the IP bus interface This provides a means for implementation of custom user defined digital designs Bus Interface The Altera FPGA is directly connected to all IP bus logic signals Custom designs can thus support all IP module access types including ID 1 Interrupt Memory and DMA High Channel Count Digital Interface Differential and TTL interface options are allowed Interfaces with up to 24 differential or a mix of 12 differential and 24 TTL or up to 48 TTL digital input output channels Channel Input Output Control The bidirectionality of the TTL digital channels is controlled in groups of 8 channels The bidirectionality of the differential digital signals is controlled in groups of 4 channels Long Distance Data Transmission Data transmission with RS485 RS422 Transceivers allow up to 32 nodes and up to 4000 feet of transmission cable 64Kx16 SRAM A 64K x 16 static random access memory SRAM is directly accessed by the Altera device Custom user defined design logic for the Altera FPGA will permit
13. For the supplied IP module example wait states are utilized for all read and write operations see specifications for detailed information SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board A wide range of other Acromag IP modules and carriers are also available to serve your signal conditioning and interface needs The cables and termination panels described in the following paragraphs represent some of the accessories available from Acromag Each Acromag carrier has its own unique accessories They are not all listed in this document Consult your carrier board documentation for the correct interface product part numbers to ensure compatibility with your carrier board Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Termination Panel Model 5025 552 A DIN rail mountable panel that provides 50 screw terminals for universal field 1 termination Connects to all Acromag carriers or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551
14. IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 2000 XP Vista 7 applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual Visual Basic Borland Builder and others The DLL functions provide a high level interface to the carriers and IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of IP module VxWorks libraries This software Model IPSW API VXW MSDOS format is composed of VxWorks real time operating system libraries for Acromag IP modules and carriers The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag IP modules and carriers The IP1K110 support programs implement the transfer of developed code between the user s processor and the Altera FPGA 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water staine
15. ODD Byte Base D07 DOO Addr T Not Used Control Status Register Not Used Configuration Data Register IP1K110 Configuration Procedure The IP1K110 implements configuration of the Altera FPGA over the IP bus interface The IP1K110 uses the Altera passive parallel asynchronous scheme with the IP bus serving as the download path Thus download and configuration is implemented with no special hardware or cables An example program written in C and available from Acromag implements configuration of the IP1K110 over the IP iG bus The program requires the configuration file to be in the Intel Hex format Using the Altera MAX PLUS II software you can generate the required hex file as follows 1 Inthe MAX PLUS II Compiler choose the Convert SRAM Object Files command 2 Inthe Convert SRAM Object Files dialog box select your SOF file and then select hex in the File Format box Click OK For further information on generating hex files refer to the documentation supplied with the EDK The steps implemented by the example C program are listed next 1 Start in configuration mode Upon system power up the IP1K110 is in configuration mode If the Altera FPGA is currently configured and operational configuration mode can be entered by driving pin 168 of the Altera FPGA to a logic high via the control register bit O Pin 168 is the Config_Enable signal which upon system power up is held high by a pullup resistor 2 Y
16. by a positive differential voltage between the terminals measured A to B or to The line receivers convert these signals to the conventional TTL level Memory Interface The IP1K110 interfaces to a 64K word SRAM device This memory interface utilizes the address signals 1 to RAMa16 data signals RAMd0 to RAMd15 and the read write control signals nWE RAM nBLE RAM nBHE RAM and nOE RAM as listed in Table 4 1 The RAM device is the Integrated Device Technology IDT71016 or the Cypress Cy7C1021 IP Bus Interface The IP1K110 interfaces to the carrier board per IP Module specification ANSI VITA 4 1995 The FPGA signals utilized are 16 data lines DATAO to DATA15 and six address lines A 1 to 6 The many control lines that comprise the IP bus include IP Reset nlOsel nlDsel nMEMsel nINTsel nW nAck nintReqO nintReq1 nDMAReqO nDMAReq1 nDMAck nDMAend nStrobe nBSO and nBS1 Table 4 1 lists the FPGA pins corresponding to these signals The IP bus 8MHz clock signal is present on pin IP CLK The function and timing requirements of all IP bus signals are specified in the ANSI VITA 4 1995 specification Copies of the ANSI VITA 4 1995 specification are available from VITA www vita com Clock Generator Interface A clock generator chip Cypress CY22150 is available to provide a user programmable clock frequency between 250KHz and 100MHz A total of four signals are utilized Ref Clock SCLK SDATA and Gen Clock
17. 041 21901 FINGON 21 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com RECONFIGURABLE DIGITAL MODULE SERIES IP1K110 INDUSTRIAL I O PACK JIVEV LOS qavoa LINDYID AYN H3AO SGNNOd HONI HO NOLMAN 922 0 SI GAGNAWWOOSY SA0VId NALHOIL WALI SHAOVdS OLNI ANY QHVOS H3lHHVO JO 341 5 HONOYHL 9 WALI 5 5 QV3H NVd LYSSNI 19 45 SYHAOVdS ANY SHOLOANNOO 9 SS3ud H3lHHVO OL FINGOW dl NOMV ATID338VO LINDYIO ADVNVG AVN H3AO SQNfIOd HONI 2 HO H3 L3IA NOLMAN 9260 SI ANDYOL d3QN3NINOO3H d31V3sS AT313 Id WOO SI H3OVdS 14 SA0V1d 7 ANY WALI SH30VdS OLNI 3 1n3ON dl 30 adis H3d10Ss H NOHHL v WALI SM3HOS QV3H 1V14 LH3SNI Squvoa SAdAL TIY 3 1811VdlNOO 38 LON AYN 3H8VMQHVH ONILNNOW SIN3aWaalinoag SLI 3NIINH3 3Q OL QHVOS H3lHHVO MOSHO 5 SQHVO8 0996 0596 3INAV ASN SHAOVdS dudnaaooud ATEWASSV 5 AIlHN3SSV IVOINVHOJN OL 41000891 dl NOLI93NNOO
18. Type Configuration Register The Interrupt Polarity register at the carriers base address offset 11H is used to control channels 00 through 07 For example channel 00 is controlled via data bit 0 as seen in the table below Interrupt Polarity Register MSB LSB Data Data Data Data Data Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 The upper 8 bits of this register are Not Used and will always read low 0 s for D16 accesses All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are below TTL threshold provided they are enabled for interrupt on level Interrupt Vector Register Read Write Base 13H The Interrupt Vector Register maintains an 8 bit interrupt pointer for all channels configured as input channels The Vector Register can be written with an 8 bit interrupt vector This vector is provided to the carrier and system bus upon an active INTSEL cycle Reading or writing to this register is possible via 16 bit or 8 bit data transfers Interrupt Vector Register 07 06 05 04 03 01 O0 Interrupts are released on register access to the Interrupt Status register Issue of a software or hardware reset will clear the contents of this register to 0 Memory Data Register Read Write 14H The Memory Data register is used to provide read or write access to SRAM memory Reading or writing to this register is possi
19. and its corresponding VHDL source are provided with the IP1K110 Engineering Design Kit To take advantage of the example VHDL program the user must be proficient in the use of VHDL and the Altera Maxplus I or Quartus software tools The IP1K110 provides several different interface options which allow a mix of differential digital and TTL digital input output channels The models and their corresponding combination of channels are given in the table below TTL 485 422 Channels Channels Temperature Range 110 0024 0 24 0700 IP1K110 2412 0 to 70 C 1 1 110 4800 48 0 0700 10 0024 0 4085 iPiK110 4800 48 0 40 to 85 C The IP1K110 can be programmed to support all types of IP cycles at either 8 or 32 MHz operation The IP1K110 comes with a simple example Altera design file that can be enhanced for implementation of custom digital logic functions Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE The example design supplied with the IP1K110 is provided as a VHDL file for Altera s Max Plus or Quartus Il software The example design includes an IP bus interface to ID space IO space and Interrupt space space is used to access a 64K x 16 RAM array control field data 1 and control a clock generation chip
20. of this register are Not Used and will always Interrupts are only available on the first eight channels read low 0 s for D16 accesses Interrupt Enable Register All input channel interrupts are disabled set to 507 following MSB LSB a power on or software reset Data Data Data Data Data Data Data Data 1 i Bit Bit Bit Bit Bit Bit Bit Bit Interrupt Type COS or H L Configuration Registers The Interrupt Type Configuration Registers determine the type of input channel transition that will generate an interrupt for each of the 8 possible interrupting channels A 0 bit selects 9 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at the carrier s base address offset is used to control channels 00 through 07 For example channel 00 is controlled via data bit O as seen in the table below Interrupt Type COS or H L Configuration Register MSB LSB Data Data Data Data Data Data Data Data
21. signals TTL DIR 1 6 control data direction of the 48 TTL I O channels EIA RS485 AND RS422 SERIAL INTERFACE The EIA RS485 and RS422 interface specifies a balanced driver with balanced receivers Balanced data transmission refers to the fact that two conductors are switched per signal and the logical state of the data is referenced by the difference in potential between the two conductors not with respect to signal ground The differential method of data transmission makes EIA RS485 and RS422 ideal for noisy environments since it minimizes the effects of coupled noise and ground potential differences That is since these effects are seen as common mode voltages common to both lines not differential they are rejected by the receivers The EIA RS422 standard defines a bus with a single driver and multiple receivers The EIA RS485 standard defines a bi directional terminated driver and receiver configuration Half duplex operation is mandated by the sharing of a single data path for transmit and receive The maximum data transmission cable length is generally limited to 4000 feet without a signal repeater installed With respect to EIA RS485 and RS422 logic states are represented by differential voltages from 1 5 to 5V The polarity of the differential voltage determines the logical state A logic 0 is represented by a negative differential voltage between the terminals measured A to B or to A logic 1 is represented
22. use of the SRAM as FIFO memory or single port memory as required by the application Example Design Provided Example VHDL design which includes implementation of the IP bus interface and control of digital with software programmable Interrupts is provided Clock Speed Supports an 8 or 32 MHz IP bus clock speed Programmable Clock Generator A clock generator IC is provided for applications requiring a custom user specified clock frequency The clock generator can be programmed to any desired frequency value between 250KHz and 100MHz e Configuration Jumpers or Switches All configuration is performed through software commands with no internal jumpers to configure or switches to set Power Up amp System Reset is Failsafe For safety all channels are configured as input upon power up and after a system reset INDUSTRIAL I O PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Up to four units may be mounted on a 6U VMEbus carrier board or five units may be mounted on a PCI carrier board Local ID Each IP module has its own 8 bit ID information which is accessed via data transfers in the ID Read space 16 bit amp 8 bit Channel register Read Write is performed through D16 008 EO data transfer cycles in the IP module 1 space 3 High Speed Access times for all data transfer cycles described in terms of wait states
23. 0 21 ACPC8630 35 and ACPC8625 The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag IP modules and carriers The IP1K110 support programs implement the transfer of developed code between the user s processor and the Altera FPGA Programming Interrupts Digital input channels can be programmed to generate interrupts for the following conditions e Change of State COS at selected input channels e Input level polarity match at selected input channels Interrupts generated by the IP1K110 use interrupt request line INTREQO Interrupt Request 0 The interrupt release mechanism employed is the Release On Register Access RORA type This means that the interrupter will release the Industrial Pack interrupt request line INTREQO after all pending interrupts have been cleared by writing a 1 to the appropriate bit positions in the input channel Interrupt Status Register In VMEbus systems the Interrupt Vector Register contains a pointer vector to an interrupt handling routine One interrupt handling routine must be used to service all possible channel interrupts When using interrupts input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a given input channel this could happen if multiple changes occur before the channel s interrupt is serviced The response time of the input channels should also b
24. 0 2412 Differential RS485 TTL Channels Channels 12 to 523 0 to 23 IP1K110 4800 TTL Channels 0 to 47 be at the ends of long branches spokes or stubs See Drawing 4501 702 for example connection and termination practices Transmission line signal reflections can be minimized with proper termination The EIA RS485 RS422 standard allows up to 32 driver receivers to be connected to a single bus Termination resistors should only be used at the two extreme ends of the bus and not at each of the nodes of the bus Termination resistors are not provided on the IP1K110 They can be added to the field wiring as near to the IP module as possible IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 3 Note that the IP1K110 does not utilize all of the logic sign
25. 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 100 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type 11 Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 551 X Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 0 to 70 Storage Temperature 25 C to 85 Shipping Weight 1 25 pounds 0 6Kg packaged 19 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com RECONFIGURABLE DIGITAL MODULE SERIES IP1K110 INDUSTRIAL I O PACK 3OV3S31NI 21901 1 6 10 NOWWOO AlddNS AlddNS 0140 318vN3 21501
26. 8 5 TERMINATION PANEL ACROMAG PART NUMBER 4001 0490 S SIDE VIEW RAIL DIN MOUNTING SHOWN HERE DIN EN 50035 32mm RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35mm LEN SCREWDRIVER SLOT FOR REMOVAL FROM RAIL NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 40 020 0 5 MODEL 5025 552 TERMINATION PANEL 4501 464A FRONT VIEW A B C D 1 2 3 48 49 50 1 2 3 48 49 50 1 2 3 48 49 50 1 2 3 48 49 50 la CONNECTORS ON PC BOARD MODEL 5 MODULE SCHEMATIC m 1 2 3 48 49 50 1 2 3 48 49 50 1 2 3 48 49 50 1 2 5 48 49 50 FRONT PANEL B C D TOP VIEW 9 19 233 4 gt A c 2 e E e 2 010 a o Hd q 3 15 lt o Te 3 35 80 2 LEN 85 1 a o p q j 11 i aj t E j
27. AND CARD CAGE BOARD CONFIGURATION IP Field Connector 2 Noise and Grounding Considerations IP Logic Interface Connector P1 3 0 PROGRAMMING IN SYSTEM CONFIGURATION ADDRESS MAPS IP1K110 Configuration Procedure Altera FPGA Logic Requirements IP Identification Space Example Altera FPGA Control Register niece Input Output Registers Direction Control Interrupt Enable 5 Interrupt Type Configuration Register Interrupt Status 10 Interrupt Polarity 10 Interrupt Vector 10 Memory Data 10 Memory Address 11 Clock Control Register 1 11 Clock Control Regist
28. Acromag l4 Series IP1K110 Industrial I O Pack Reconfigurable Digital Board USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2004 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 724 F11M004 SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Page 1 0 GENERAL KEY IP1K110 INDUSTRIAL I O PACK INTERFACE FEATUREG SIGNAL INTERFACE IP MODULE Win32 DRIVER SOFTWARE IP MODULE VxWORKS 2 0 PREPARATION FOR USE UNPACKING
29. CONFIGURABLE DIGITAL MODULE Pin Signal 59 GND Output 61 Output DIOO 63 Bi Dir 64 Bi Dir 65 Bi Dir 3 3Volts 67 Bi Dir Bi Dir DIO6 BiDir 70 Bi Dir 71 Bi Dir 72 2 5Volts DIO9 N Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http Awww acromag com 15 yo DIO10 Bi Dir DIO10 Bi Dir W 0 5 GND 2 5Volts Input IP Bus IP Module Clock Input IP Bus GND Bi Dir 3 3Volts Bi Dir Bi Dir Bi Dir Bi Dir Bi Dir Bi Dir 2 5Volts Bi Dir Bi Dir Bi Dir Bi Dir Bi Dir Bi Dir 3 3Volts 100 101 102 103 i 104 i 105 Input From CPLD 106 2 5Volts 107 Input Tied High N E 74 75 76 78 79 81 82 83 84 85 87 88 91 92 93 94 95 97 020 w g SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE yo Pin Output Pulled High Pin 5 140 141 Output Pulled Low 142 Output Pulled Low TTL DIRI Output Pulled High TTL DIR2 Output Pulled High 143 Input From CPLD 144 Bi Dir D8 IP Bus Input From CPLD 145 GND Input From CPLD 146 3 3Volts 147 Bi Dir D9 IP Bus 5 0 SERVICE AND REPAIR 148 Bi Dir D10 IP Bus 149 Bi Dir 011 IP Bus SERVICE AND REPAIR ASSISTANCE 150 Bi Dir D12 IP Bus 151 GND Surface Mounted Technology SMT boards are generally 152 2 5Volts difficult to repair It is highly recommended
30. E MODEL 5025 552 18 TRANSITION MODULE MODEL 19 DRAWINGS Page 4501 971 IP1K110 BLOCK 20 4501 702 RS485 I O CONNECTIONS 21 4501 434 IP MECHANICAL ASSEMBLY 22 4501 462 CABLE 5025 550 NON SHIELDED 23 4501 463 CABLE 5025 551 SHIELDED 24 4501 464 TERMINATION PANEL 5025 552 25 4501 465 TRANSITION MODULE TRANS GP 25 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility All trademarks are the property of their respective owners 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series IP1K110 module is a reconfigurable digital input output board The IP1K110 contains a 100 000 gate Altera amp Field Programmable Gate Array FPGA which is in system reconfigurable This allows designers to implement logic functions unique to their application and in system configure the Altera FPGA via the IP bus interface An example Altera FPGA configuration file
31. LE DIGITAL MODULE 5 Write to the Clock Control Register at base address plus an offset of 1DH using the data provided by the program 6 Write 1H to the Clock Trigger Register at base address plus an offset of 1FH After approximately 1 2ms programming is complete and the clock is available for use by the FPGA A software or hardware reset during programming will cause errors If a reset occurs restart the above procedure IP1K110 PROGRAMMING CONSIDERATIONS Acromag provides a software product sold separately to facilitate the development of Windows 98 2000 applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual Visual Basic Borland Builder and others The DLL functions provide a high level interface to the carriers and IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of IP module VxWorks libraries This software Model IPSW API VXW MSDOS format is composed of VxWorks real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9660 9630 APC862
32. Output Voltage Common Mode Output TTL TRANSCEIVERS Channel Configuration Integrated Circuit Device Termination Resistors are not provided Termination resistors are recommended at network end points only see Drawing 4501 702 for location 5V Maximum 1 5V Minimum with 270 load 3V Maximum 250mA Maximum 70mV 0 Up 48 non isolated TTL signals Selected in blocks of 8 channels when ordered Pericom PI74FCT623T http www pericom com INDUSTRIAL I O PACK COMPLIANCE Specification Electrical Mechanical Space 2 ID Memory tinens Interrupts Handling Format This device meets or exceeds all written Industrial Pack specifications per ANSI VITA 4 1995 for 8MHz or 32MHz operation for Type Modules Single Size IP Module 16 bit and 8 bit 16 and 8 bit Supports Type 1 32 bytes per IP consecutive odd byte addresses IPAH is used to indicate 32MHz operation 8 2 operation is also supported Supported by hardware but not implemented in example design Generates INTREQO interrupt request per IP and interrupt acknowledge cycles via access to IP INT space INTREQ1 available but not driven by example FPGA design Two IP request levels available but not implemented in e
33. X Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from a VMEbus card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X IP1K110 FPGA ENGINEERING DESIGN KIT Acromag provides an engineering design kit for the IP1K110 sold separately a must buy for first time IP1K110 module purchasers The design kit model IP 1K110 EDK provides the user with the basic information required to develop a custom FPGA program for download to the Altera FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source example configuration file and other utility files The IP1K110 is intended for users fluent in the use of Altera MaxPlus or Quartus design tools Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE
34. ailable from Acromag 6 0 SPECIFICATIONS 188 i igurati i i Configuration Single Industrial Pack Module 9 880 in 98 5 Width neninesnan 1 780 in 45 2 mm Board Thickness 0 062 in 1 59 mm Max Component Height 0 290 in 7 37 mm Connectors P1 IP Logic Interface 50 pin female receptacle header Bus AMP 173279 3 or equivalent 5 P2 Field l O 50 pin female receptacle header SUR Output CY22150 AMP 173279 3 or equivalent SDATA Output CY22150 Data TTL DIR6 Output Pulled High 16 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE Power 5 Volts 59 410mA Typical for Acromag configuration file 480mA Maximum 47 12 Volts 55965 from P1 Not Used Maximum Vcc Rise Time 100m seconds ENVIRONMENTAL Operating Temperature Standard Unit 0 to 70 E Version 40 to 85 C Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Resistance to Complies with IEC1000 4 3 3 V m 80 to 1000MHz AM amp 900MHz Keyed a
35. alibration information ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC ISA or PCI buses The IP1K110 ID space will read differently in configuration mode than it does in user mode In configuration mode the IP model code at base address OBhex will read a 42hex while in user mode the same byte will read 43hex In addition the CRC byte at base address 17hex will read a 4Fhex in configuration mode and read 2Ehex in user mode other ID space bytes will read the same in both configuration mode and user mode The example Altera FPGA file provided with the IP1K110 EDK implements the ID Space as shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID information Execution of an ID Space Read operation requires 0 wait states Table 3 2 IP1K110 ID Space Identification ID Hex Offset From ID ASCII Numeric Character quivalent 32MHz IP s have IPAH Acromag ID Code IP Model Code 42 42 Config 43 Mode 43 User Mode Revision 0 900 Reserved ID Low sye ID High BUS ID Bytes CRC 4 4 Config Mode 2E 2 User Mode 191035 NetUsed Notes Table 3 2 1 The IP model number is repr
36. als defined for the P1 connector and these are indicated in BOLD ITALICS Table 2 3 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number DOO A e 9 oe 310 f ose Do 13 e a M Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model 2 3 A4 STROBE Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE 3 0 PROGRAMMING INFORMATION This board is addressable in the Industrial Pack 1 space to control in system configuration of an Altera FPGA After the Altera FPGA is configured the IP space is used to control data transfer and steering logic of the mix of up to 24 EIA RS485 RS422 serial channels and up to 48 digital TTL channels The IP1K110 includes a 64K x 16 static memory device and clock generator chip which are also both accessed via the IP bus interface through the Altera FPGA Upon an initial power reset the IP1K110 responds to IP bus ID space accesses and 1 space accesses The ID space accesses allow board identification The space accesses allow configuration of the Altera FPGA After the Altera FPGA is successfully configured the IP bus interface functions as defined by the logic program of the Altera FPGA Th
37. and power loss Cable 50 wire flat ribbon cable 28 gage Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 8M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes See Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packaged TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 APC8610 or APC8620 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U APC8610 or APC8620 1 non intelligent carrier boards field connectors only via a flat ribbon cable Model 5025 551 x The A D connectors on the carrier board connect the field signals to the P2 connector on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 assignments Refer to the IP module manual for correct wiring c
38. as a program CyberClocks available to aid with calculations Note that the user will have to combine the individual variables into the control words as outlined in the register descriptions The CY22150 Specification Sheets and CyberClocks program are available from Cypress at WWW Cypress com The reference frequency input to the Cypress CY22150 is the same as the carrier clock either 8MHz or 32MHz Procedure 1 Start the BitCalc2K1 Version 2 program enter the desired frequency and select the IP clock speed i i 1 IP Clock Speed Desired Frequency MHz Jemen Expected Frequency in MHz 2 000000 z Expected Frequency Error PPM 0 000000 p Register Data INSTRUCTIONS Enter the desired Clock Control Register 1 0084 Clock Control Register 2 2000 Clock Control Register 3 0000 Hit the Calculate Button frequency in the box and select the proper IP Carrier Clock speed 8 2 is default Then click the Calculate button Message Box will appear when the calculation is complete Write to the Clock Control Register 1 at base address plus an offset of 18H using the data provided by the program Write to the Clock Control Register 2 at base address plus an offset of 1AH using the data provided by the program Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURAB
39. as seen in Table 4 1 Signal Description Ref Clock The Ref Clock or reference clock is a 8MHz p clock generated by the FPGA from the IP carrier clock signal This is the serial clock to the CY22150 It is used for clock frequency programming The serial data is sent from the FPGA to the CY22150 on this pin for clock frequency programming Gen Clock The clock frequency generated by the Initialization Interface The configuration method used by the IP1K110 is the Altera passive parallel asynchronous The initialization interface utilizes eight signals nConfig Conf Done RDYnBUSY Init Done nStatus nWS CS and nCS The function and timing requirements of these signals are defined by the Altera Configuring Devices Application Note 116 A copy of the Configuring Devices Application note 116 is available from Altera www altera com SIGNAL PIN ASSIGNMENTS The signal pin assignments for the IP1K110 are listed in table 4 1 The pin assignments shown must be fixed in your Altera ACF file An example ACF file is provided with the design files that accompany the IP1K110 EDK Table 4 1 Altera FPGA Pin Assignments Pin Signal VO Input Pull Down Output 2 CPLD 6 GND GND 8 RAMa2 9 Output 14 Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RE
40. ase address 0 hex with Data line 0 set high Setting Config Enable high returns the IP1K110 to configuration mode 4 Afterthe Altera FPGA has returned control back to configuration mode the Altera FPGA must also a disable drive of the IP bus Ack signal b disable drive of the 16 IP bus data lines and c and disable IP bus write cycles on the Altera FPGA The following VHDL code serves as an example of these requirements Process ACK Config Enable Begin If Config Enable 0 Then n lt not Else ACK_n lt 7 End If End Process RD Enable not Config Enable and IO Enable Process RD Data RD Enable Begin If RD Enable 1 Then IP Data RD Data Else Data lt others gt Z End If End Process Write Strobe lt MEMSEL and INTSEL and IDSEL n and not IOSEL n and not RD Write n and not BSO n and not Config Enable IP Identification Space Read Only 32 odd byte addresses Each IP module contains identification ID information that resides in the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID space Fixed information includes the IPAH identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP1K110 ID space does not contain any variable e g unique c
41. ble via 16 bit data transfers only In order to properly access the memory which constitutes 64K words an address pointer to a single word in memory must first be specified The address is specified via the Memory Address register The value written into the Memory Address register is used to point to one of the 64K words All read or write accesses to the Memory Data register will in turn implement an access to memory at the address specified by the Memory Address register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE The address specified in the Memory Address register will be automatically incremented after the read or write cycle is completed Thus when consecutive locations within the memory are accessed the Memory Address register need not be manually updated by software Read or write accesses to this register require four wait states A software or hardware reset has no affect on this register Memory Address Register Write Only 16H The Memory Address register is used to point to one of 64K words in memory The 16 bits of this register are used to specify one of 64K words that can be accessed via a read or write to the Memory Data register Writing to this register is possible via 16 bit data transfers only The address specified in the Memory Address register will be automatically increment
42. d request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions lt is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power SENSITIVE ELECTRONIC DEVICES 7 The board utilizes static sensitive and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for c
43. damage LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 3 P1 also provides 5V power the module 12 is not used Note that the ERROR signal is not used An FPGA installed on the IP Module provides an interface to the carrier board per IP Module specification ANSI VITA 4 1995 The supplied FPGA logic example includes address decoding and ID read write control circuitry interrupt handling and ID storage implementation Address decoding of the six IP address signals A 1 6 is implemented in the FPGA in conjunction with the IP select signals to identify access to the IP module s ID or space In addition the byte strobes BS0 and BS1 are decoded to identify low byte high byte or double byte data transfers The carrier to IP module interface allows access to both ID and 1 space via 16 or 8 bit data transfers Read only access to ID space provides the identification for the individual module as given in Table 3 2 per the IP specification Read and write accesses to the 1 space provide a means to control the IP1K110 The IP1K110 has 64K words of SRAM available Read and write accesses to the SRAM are implemented through the IP module 1 space A start address is specified in the Memory Address register This start address will automatically be incremented by hardware for each access to the Memory Data register The IP1K110 also has a Clock Generat
44. e IP1K110 in system configuration logic will be disabled by the newly configured Altera FPGA IN SYSTEM CONFIGURATION ADDRESS MAPS The 1 space address map for the IP1K110 when in configuration mode is as shown in Table 3 1 The IP1K110 is in configuration mode upon system power up and when the Config Enable line on pin168 of the Altera FPGA is a logic high The Config Enable line must be held low by the Altera FPGA after successful configuration to disable configuration mode Note that upon initial power up a pull up resistor connected to pin 168 of the Altera FPGA keeps the IP1K110 in configuration mode After the FPGA is configured the internal logic of the FPGA must pull this resistor down to a logic low to disable configuration mode If you have a configured FPGA and then wanted to re configure the FPGA again you must enable configuration mode This is accomplished by driving pin 168 of the FPGA to a logic high level via control register bit 0 If you change your mind and want to return control back to the FPGA an IP bus reset can be used to clear or drive pin 168 to a logic low level see example VHDL file Note that the Altera FPGA must not drive the IP bus data lines or the ACK signal after you return to configuration mode from a configured FPGA Also IP bus write cycles must be disabled from changing the registers of your configured FPGA while in configuration mode Table 3 1 IP1K110 Configuration Address Map IO Space ODD
45. e considered when calculating this bandwidth The total response time is the sum of the input buffer response time plus the interrupt logic circuit response time and this time must pass before another interrupt 12 condition will be recognized The Interrupt Input Response Time is specified in section 6 The following programming examples assume that the IP1K110 is installed onto an Acromag AVME9630 9660 carrier board consult your carrier board documentation for compatibility details Programming Example for AVME9630 9660 Carrier Boards 1 Clear the global interrupt enable bit in the Carrier Board Status Register by writing a 0 to bit 3 2 Perform Specific IP Module Programming see the Change of State or Level Match programming examples that follow as required for your application 3 Write to the carrier board Interrupt Level Register to program the desired interrupt level per bits 2 1 amp 0 4 Write 1 to the carrier board IP Interrupt Clear Register corresponding to the IP interrupt request s being configured 5 Write 1 to the carrier board IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the carrier board by writing a 1 to bit 3 the Global Interrupt Enable Bit of the Carrier Board Status Register Programming Example for Change of State Interrupts 1 Program the Interrupt Vector Register with the user specified interrup
46. e individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Registers 5 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Interrupts can now be generated by matching the input level with the selected polarity for programmed interrupt channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE General Sequence of Events for Processing an Interrupt 1 The IP1K110 asserts the Interrupt Request 0 Line INTREQO in response to an interrupt condition at one or more inputs 2 The AVME9630 9660 carrier board acts as an interrupter in making the VMEbus interrupt request asserts IRQx corresponding to the IP interrupt request 3 The VMEbus host interrupt handler asserts IACK and the level of the interrupt it is seeking on A01 A03 4 When the asserted VMEbus IACKIN signal daisy chained is passed to the AVME9630 9660 the carrier board will check if the level requested matches that specified by the host If it matches the carrier board will assert the INTSEL line to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to IntReq0 A1 high corresponds to INTREQ1 5 The IP1K110 puts the appropriate in
47. ed after the read or write cycle to the Memory Data register is completed Thus when consecutive locations within the memory are accessed the Memory Address register need not be manually incremented by software A write access to this register requires one wait state A software or hardware reset will clear this register to zero Clock Control Reg 1 Read Write Base 18H The Clock Control Register 1 is a 16 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock The register contains the following control bits as specified in the Cypress CY22150 spec sheet Do 00 DIV1N 2 3 DIVIN 4 DIVIN 5 A software or hardware reset will clear this register to zero Clock Control Reg 2 Read Write Base The Clock Control Register 2 is a 16 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock The register contains the following control bits as specified in the Cypress CY22150 spec sheet 0 PB CLKSRCO De 6 CLKSRC1 CLKSRC2 A software or hardware reset will clear this register to zero 11 Clock Control Reg 3 Read Write Base 1DH The Clock Control Register 3 is an 8 bit read write register This is used as part of the control for the Cypress CY22150 Programmable Clock In this register only DO bit 0 and D7 bit 7 are required The o
48. er 2 11 Clock Control Register 3 11 Clock Trigger 11 Program Procedure to Set Clock Frequency 11 IP1K110 PROGRAMMING CONSIDERATIONS 12 Programming 12 4 0 THEORY OF OPERATION 13 FIELD INPUT OUTPUT 5 5 13 LOGIC POWER 13 EIA RS485 AND RS422 SERIAL INTERFACE 14 SIGNAL PIN 5 0 14 5 0 SERVICE AND 16 SERVICE AND REPAIR 55 5 16 PRELIMINARY SERVICE PROCEDURE 16 6 0 16 ARARA IR IR RR GC CC aa iei cei 16 ENVIRONMENTAL esee 17 EIA RS485 RS422 5 17 TTE TRANSGEIVERSG eene 17 INDUSTRIAL I O PACK COMPLIANCE 17 IP1K110 ENGINEERING DESIGN KIT 18 2 APPENDIX inm tc teen 18 CABLE MODEL 5025 551 18 CABL
49. esented by a two digit code within the ID space the IP1K110 model is represented by 42 Hex when in configuration mode and 43 Hex in user mode Example Altera FPGA Design The example design provided with the IP1K110 EDK consists of IP bus interface logic Altera interface to 64K x 16 static RAM Altera interface to clock generator chip and interface to differential or TTL I O The IP1K110 hardware supports a direct connection to all IP bus signals as listed in Table 2 2 As such hardware will support all IP bus cycles including ID 1 Interrupt Memory and DMA The example design provided uses all but the Memory and DMA cycle types Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE The space address map for this example design is given in Table 3 3 The differential or TTL I O clock generator chip The base address for the IP module 1 space see your and 64K x 16 static RAM can be controlled and accessed through carrier board instructions must be added to the addresses shown space in Table 3 3 to properly access the 1 space Accesses can be performed on an 8 bit DOB EO or 16 bit 016 word basis Table 3 3 IP1K110 FPGA Address Space EVEN The memory for this module is given assuming byte Base EVEN Byte NZON Base accesses using the Big Endian byte o
50. gister Bits 321043 Register Bits 0 to 23 If the Input Output port is to be selected as an output you should first set the output register bit as desired before setting the Direction Control register Note if you select as output before setting this Input Output register the output will be logic low as this is the power up reset state of the output register bits TTL Channels 0 to 47 Register Bits 0 to 47 Channel read write operations use 8 bit or 16 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or software reset The unused upper bits of these registers will always read low 075 Table 3 4 shows all channels and their corresponding data register bit for each of the IP1K110 models Direction Control Register Read Write Base 08H and 09H The data direction input or output of the digital channels is selected via this register The data direction of all differential channels are set as a group of two or four channels while data direction of all TTL channels is controlled as a group of 8 channels Setting a bit high configures the data direction for the identified channels as output Setting the control bit low configures the corresponding channel s data direction for input The default power up state of these registers is logic low Thus all channels are configured as inp
51. hat is a pending interrupt will remain pending Note that interrupts are not prioritized via hardware The system software must handle interrupt prioritization The Interrupt Status register at the carrier s base address offset OFH is used to monitor pending interrupts corresponding to channels 00 through 07 For example channel 00 is monitored via data 1 0 as seen in the table below Interrupt Status Register MSB LSB Data Data Data Data Data Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 The unused upper 8 bits of this register are Not Used and will always read low 0 s for D16 accesses All bits are set to 0 following a reset which means that all interrupts are cleared 10 Interrupt Polarity Registers Read Write Base 11H The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts A 0 bit specifies that an interrupt will occur when the corresponding input channel is low i e a 0 in the digital input channel data register A 1 bit means that an interrupt will occur when the input channel is high i e a 1 in the digital input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt
52. ion mode and remains in that mode until the Altera FPGA is successfully configured Once the Altera FPGA is successfully configured control is automatically transferred to user mode and the Altera FPGA has control of the IP bus interface In order to implement this transition the following requirements must be respected by the Altera FPGA 1 Pin 168 of the Altera FPGA is reserved Config Enable control When Pin 168 is driven low the IP1K110 is in user mode and the Altera FPGA has control of the IP bus interface When Pin 168 Config Enable is driven high the IP1K110 is in configuration mode Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE 2 Config Enable signal Pin 168 should be driven by Altera FPGA logic similar to that shown in the following VHDL process Notice that after the Altera FPGA is configured the Config Enable signal is driven to a logic low by the configured Altera FPGA A logic low holds the IP1K110 in user mode Process Clock Reset Begin If Reset 1 Then Config Enable lt 0 Elsif Clock event and Clock 1 Then If Write_Enable 1 Then Config Enable lt IP Bus 00 Else Config Enable lt Config Enable End If End If End Process 3 The Config Enable signal Pin 168 can be driven to a logic high via an IP bus write cycle to carrier b
53. ld be disabled or reconfigured B If other IP modules have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the board Refer to the Block Diagram shown in Drawing 4501 971 as you review this material FIELD INPUT OUTPUT SIGNALS The field interface to the IP module is provided through connector P2 refer to Table 2 1 These pins are tied to the inputs and outputs of EIA RS485 RS422 line transceivers or TTL transceivers RS485 signals received are converted from the required EIA RS485 RS422 voltages signals to the TTL levels required by the FPGA Likewise TTL signals are converted to the 443 EIA RS485 RS422 voltages for data output transmission The FPGA provides the necessary interface to the RS485 RS422 transceivers or TTL transceivers for control of data output or input and monitoring of input signals for generation of interrupts if enabled The field interface to the carrier board is provided through connector P2 refer to Table 2 1 Field points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause operational errors and with extreme abuse possible circuit
54. nd European Norm EN50082 1 with no digital upsets Electromagnetic Interference Immunity No register upsets under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Electric Fast Transient Immunity Complies with IEC1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class A equipment Warning This is a class A product In a domestic environment this product may cause radio interference in which the user may be required to take adequate measures TTL 485 422 Channels Channels Operating Temperature Range IPIK110 0004 o 00705 110 4800 48 0 0 706 IPIKT10 0024E o 40t085 C IPIKT10 4800E 48 0 400856 EIA RS485 TRANSCEIVERS Channel Configuration Up to 24 non isolated EIA RS485 RS422 serial ports with a common signal return connection Selected in blocks of 4 signal pairs channels when ordered Data Rate 30M bits sec Maximum Cable Length 4000 feet Maximum Use ofa signal repeater can extend transmission distances beyond this limit 17 Termination Resistors Differential
55. oncern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and the following discussion for configuration and assembly instructions Model IP1K110 Boards have no jumpers or switches to configure all configuration is through software commands CONNECTORS IP Field Connector P2 P2 provides the field I O interface connector for mating IP modules to the carrier board P2 is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrie
56. onnections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 APC8610 or APC8620 1 P1 50 pin male header with strain relief ejectors Use Acromag 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 0 to 70 Storage Temperature 25 C to 85 Shipping Weight 1 25 pounds 0 6kg packaged Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025
57. or chip A clock frequency from 250KHz to 100MHz is programmable via the IP module 1 space The generated clock frequency is input to the FPGA on pin 183 This clock can be used to synchronize I O operations with other IP modules Interrupt Operation For the supplied FPGA configuration digital input channels of this model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions at enabled inputs An 8 bit interrupt service routine vector is provided during interrupt acknowledge cycles on data lines 00 07 The interrupt release mechanism employed is Release On Register Access Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http Awww acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE Fail Safe Operation The IP1K110 operation is considered Fail safe That is the input output channels are always configured as input upon power up reset and a system software reset This is done for safety reasons to ensure reliable control of the output state under all conditions Digital I O Interface The IP1K110 allows interface with a mix of up to 48 TTL I O channel or up to 24 differential signals The signals DIOO to DIO47 are utilized for digital input output control to the field signals The six signals DIFF DIR 1 6 given in Table 4 1 control data direction of the 24 differential 1 signals The six
58. ou can verify that you are in configuration mode by reading ID space at base address OBhex The byte read will be 42hex when in configuration mode and 43hex when in user mode 3 Configuration is started by setting bit O of the control register at base address 01H to a logic high 4 This same register bit O must be read next When read as a logic high software can proceed to the data transfer phase A polling method should be used here since this bit will not be read high until 5u seconds after the control bit is set high 5 status of the Altera FPGA during configuration can be monitored via the Status register at base address 01H Bit 1 monitors the Altera nStatus signal which must remain high during configuration Bit 2 of the Status register reflects the Altera FPGA CONF DONE signal The CONF DONE signal must remain at a logic low until configuration has completed 6 Write program data one byte at a time to the Configuration Data register at base address 03H 7 Upon successful configuration control of the IP bus will automatically be switched to user mode and the Altera FPGA will have control of the IP bus interface This is accomplished by the newly configured Altera FPGA taking control of the Config Enable signal pin 168 and pulling this signal low Altera FPGA Logic Requirements There are two main modes of operation on the IP1K110 module configuration mode and user mode The IP1K110 powers up in configurat
59. r board you should verify this for your carrier board When reading Table 2 1 notice that 5485 input output channels as well as digital TTL input output channels are listed with their corresponding connector pin number Each point will be either RS485 TTL defined by your IP1K110 model Table 2 2 lists the channels dedicated to each of the IP1K110 models Acromag Inc 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE Table 2 1 IP1K110 Field I O Pin Connections P2 Pin Description Pin Description RS485 TTL RS485 TTL 1 000 1 000 1 012 1 025 26 1 000 1 001 1013 1 026 27 001 1 002 1 013 1 027 28 1 001 1 003 1 014 1 028 29 002 1 004 1 014 1 029 30 1 002 1 005 015 1 030 31 1 003 1 006 1 015 1 031 32 1 003 1 007 016 1 032 33 004 1 008 1 016 1 033 34 1 004 1 009 1 017 1 034 35 1005 1 010 1 017 1 035 36 1 005 1 011 l O18 1 036 37 1 006 1 012 1 018 1 037 38 1 006 1 013 l O19 1 038 39 007 1014 1 019 1 039 40 1 007 1 015 1 020 1 040 41 008 1 016 1 020 1 041 42 1 008 1 017 1 021 1 042 43 1 009 1 018 1 021 1 043 44 1 009 1 019 1 022 1 044 45 1010 1 020 1 022 1 045 46 1 010 1 021 1 023 1 046 47 011 1 022 1 023 1 047 48 1 011 1 023 24 NC NC 49 12 1 024 25 GND GND 50 gt ole a of o
60. rdering format Big 15 D07 Endian is the convention used in the Motorola 68000 PowerPC microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses The Intel x86 family of microprocessors uses the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of the memory map for this module on a PC carrier board will require the use of the even address locations to access the lower 8 bit data On a VMEbus carrier use of odd address locations are required to access the lower 8 bit data as shown in Table 3 1 and 3 3 Control Register Input Output Input Output Registers Registers CH15 e 8 7 e CH00 Input Output Input Output Registers Registers lt 24 23 e CH16 Input Output Input Output Registers Registers 47 e 40 9 e CH32 Direction Control Register Biti1 e Control Register Read Write Base 00H This read write register is used to transfer control back to configuration mode when in user mode set your specific model of the IP1K110 and issue a software reset R W Interrupt Not Used Enable Channels CHO7 e R W Interrupt Not Used Type Channels 07 e R W Interrupt Not Used Status Channels CHO7 e R W Interrupt Not Used Polarity Channels
61. t vector This vector forms a pointer to a location in memory that contains the address of the interrupt handling routine 2 Select channel Change of State interrupts by writing a 1 to each channel s respective bit in the Interrupt Type Register Note that Change Of State interrupts specified with 1 may be mixed with polarity match interrupts specified with 0 3 Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register 4 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Change of State Interrupts may now be generated by the input channels programmed above for any Change Of State transition Programming Example for Level Polarity Match Interrupts 1 Program the Interrupt Vector Register with the user specified interrupt vector This vector forms a pointer to a location in memory that contains the address of the interrupt handling routine 2 Select channel polarity match interrupts by writing a 0 to each channel s respective bit in the Interrupt Type Registers Note that Change Of State interrupts specified with 1 may be mixed with polarity match interrupts specified with O 3 Select the desired polarity High Low level for interrupts by writing a 0 Low or 1 High level to each channel s respective bit in the Interrupt Polarity Registers 4 Enabl
62. terrupt vector on the local data bus 000 007 for the 008 interrupter and asserts to the carrier board The carrier board passes this along to the VMEbus DO8 O and asserts DTACK 6 The host uses the vector to form a pointer to an interrupt service routine for the interrupt handler to begin execution 7 Example of Generic Interrupt Handler Actions A Disable the interrupting IP by writing O to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register B Disable the interrupting channel s by writing a 0 to the appropriate bits in the IP1K110 Interrupt Enable Register C Clear the interrupting channel s by writing a 1 to the appropriate bits in the IP1K110 Interrupt Status Register D Enable the interrupting channel s by writing a 1 to the appropriate bits in the 110 Interrupt Enable Register E Clear the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Clear Register F Enable the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 9660 IP Interrupt Enable Register 8 If the IP1K110 interrupt stimulus has been removed and no other IP modules have interrupts pending the interrupt cycle is complete i e the carrier board negates its interrupt request IRQ If the IP1K110 interrupt stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed the IP1K110 shou
63. that a non functioning 153 Pulled High board be returned to Acromag for repair The board can be easily 154 Input Tied Low damaged unless special SMT repair and service tools are used 155 Input Pulled High Further Acromag has automated test equipment that thoroughly 156 PDOO From CPLD checks the performance of each board When a board is first 157 Bi Dir D1 IP Bus produced and when any repair is made it is tested placed in a 158 Bi Dir D2 IP Bus burn in room at elevated temperature and retested before 159 Bi Dir D3 IP Bus shipment 160 Bi Dir D13 IP Bus 161 Bi Dir D4 IP Bus Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the module with one that is 170 known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Initial testing and use of the IP1K110 should be implemented with the Acromag supplied FPGA configuration file This will allow one to verify the correct operation of the IP1K110 hardware Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also av
64. ther bits D1 D6 are not used The value for DO is zero if the carrier board provides an 8MHz clock to the FPGA DO is logic high if the carrier board provides a 32MHz signal to the FPGA D7 is an enable disable signal for the CY22150 IC Writing a 1 to bit 7 will disable the clock generator chip including the programming function Setting D7 to zero will allow for normal operation A software or hardware reset will clear this register to zero Clock Trigger Register Read Write Base 1FH The Clock Trigger Register is an 8 bit register To initiate programming of the Cypress CY22150 Programmable Clock write a 1 to bit O of this register During programming bit O will remain logic high The programming process takes approximately 1 2ms to complete after the initial trigger A software or hardware reset has no affect on this register Program Procedure to Set Clock Frequency At power up the programmable clock has no valid output The clock can be programmed for an output frequency from 250 KHz to 100 MHz The clock can be programmed at any time during device operation Program the clock using the following process The program words required for Clock Control Register 1 2 and 3 can be calculated using a program provided by Acromag BitCalc2K1 Version 2 supplied with the EDK Alternately using the Clock Control Registers Data Maps and the CY22150 specification sheet the necessary values can be calculated Cypress h
65. uts on system reset or power up The unused upper nibble D15 to D12 of the register at base address 08H will always read low 05 All not used bits will also read low See Table 2 1 for field I O pin assignments corresponding to each of the RS485 and TTL channels listed below Direction Control Register Modei 1 D11 Dio Do9 007 006 Dos 004 002 001 DOO IP1K110 0024 Not Not Not Not Not Not Ch 10 Ch Ch 6 Ch Ch Ch Used Used Used Used Used Used 11 22 8 9 7 4 5 2 3 0 1 23 20 21 18 19 16 17 14 15 12 13 Used Used Used Ch 16 Ch8 Ch 0 Ch 23 Ch 21 Ch19 Ch 17 Ch 15 Ch13 Ch 23 Ch 15 Ch 7 IP1K110 4800 TTL TTL TTL TTL TTL TTL Not Not Not Not Not Not Ch 40 Ch 32 Ch 24 Ch 16 Ch 8 Ch 0 Used Used Used Used Used Used Ch 47 Ch 39 Ch 31 Ch 23 Ch 15 Ch 7 Interrupt Enable Registers Read Write Base OBH The Interrupt Enable register at the carrier s base address offset OBH is used to control channels 00 through 07 For The Interrupt Enable Registers provide a mask bit for the first example channel 00 is controlled via data bit 0 as seen in the 8 channels A 0 bit will prevent the corresponding input channel prior table from generating an external interrupt A 1 bit will allow the corresponding input channel to generate an interrupt Only those Channel read operations use 8 bit or 16 bit data transfers channels enabled for interrupts can generate interrupts The upper 8 bits
66. xample FPGA design An 8 bit vector is provided during interrupt acknowledge cycles on data lines DO D7 The release mechanism is RORA type Release On Register Access Altera EP1K100QC208 1 100K typical gates and 49 152 RAM bits Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES IP1K110 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL MODULE IP1K110 Engineering Design Kit Model IP 1K110 EDK Engineering design kit provides the user with the basic information required to develop a custom FPGA program for download to the Altera FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source example configuration file and other utility files The IP1K110 is intended for users fluent in the use of Altera MaxPlus or Quartus design tools NineK468d hex Hexadecimal Intel Format configuration file The Hex file is an ASCII file in the Intel Hex format The file is generated by the Altera software and is used to program the Altera FPGA over the IP bus interface NineK468d vhd Acromag provided VHDL hardware design language source file supports IP bus interface to ID IO and INT space Acromag provided VHDL hardware design language source file that provides a interface for programming the CY22150 468

Series IP1K110 Industrial I/O Pack Reconfigurable Digital

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