Using DMACII (Burst Transfer)
Contents
1. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Techno2. DMACII setting dm_index mod all 0x0026 Transfer Unit 8bit Transfer Data Memory REJ05B0639 0100 Rev 1 00 May 2005 Page 5 of 9 ENESAS M32C 80 Series Using DMACII Burst Transfer Transfer Source Forward Transfer Destination Fixed Calculation Transfer None x Burst Transfer Burst Interrupt None Chained Transfer None Multiple Transfer None x dm_index count 5 number of transfer 5 dm_index sadr data Source of transfer beginning address of the data array dm_index dadr amp dest Destination of transfer dest Set the interrupt used for DMAC II rlvl 0x20 int0ic 0x07 INTO interrupt level 7 while 1 4 2 Relocatable Vector Tables section vector ROMDATA variable vector table org VECTOR ADR lword dummy_int BRK software int 0 lword dummy_int i lword dummy_int p lword dummy_int lword dummy_int lword dummy_int 7 lword dummy_int A lword dummy_int 7 lword dummy_int DMAO software int 8 r F Omission E 7 lword dummy_int INT5 software int 26 lword dummy_int INT4 software int 27 lword dummy_int INT3 software int 28 lword dummy_int INT2 software int 29 lword dummy_int INT1 software int 30 glb dm index Iword dm index INTO software int 31 lword dummy_int TIMER B5 software int 32 r F Omission Interrupt priority l
3. ENESAS APPLICATION NOTE M32C 80 Series Using DMACII Burst Transfer 1 Abstract This application note describes how to use DMACII in burst transfer 2 Introduction The explanation of this issue is applied to the following condition Applicable MCU M32C 80 Series This program can also be used when operating other microcomputers within the M16C family provided they have DMACII function However some functions may have been modified Refer to the User s Manual for details Use functions covered in this Application Note only after careful evaluation 3 Detailed description The following explains an example use of DMACII transfer for the case where when an interrupt request which has had its priority level set to 7 by the interrupt control register occurs data is transferred from one memory location to another by a DMACII transfer a specified number of times successively During a burst transfer the user program is not executed Nor are interrupts accepted 3 1 DMAC II Transfer Mode This application note example offers functions of single transfer mode shown in Table 1 Table 1 Selectable Functions in Single Transfer Mode Item Definition Selection T ter Block 8 bits Yes ransfer Bloc 16 bits Immediate data Transfer Data Data in memory Yes Fixed address Source Direction Forward address Yes m Fixed address Yes Destination Direction Forward address Cal
4. export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein REJ05B0639 0100 Rev 1 00 May 2005 Page 9 of 9
5. LENAME rej05b0639 src c Mer z 1 00 FUNCTION DMACII Burst Transfer x RK I IK kok k o kok o oko k oko kok ko oko k AA k k kok k k AR IRA IR IIR IAI IR IIR A I ORK kok k oko kok k oko k kok k oko k oko I include file BA ORK IK kok k kok k oko k kok k kok kok oko I include lt stdio h gt include sfr32c83 h ORK IK oko k I KK IK I I I I px DMACII o ok k k oko k k oko kok kok k k kok k kok I struet union struct4 char size l Transfer Unit Select Bit char imm 1 Transfer Data Select Bit char upds l Transfer Source Direction Select Bit char updd 1 Transfer Destination Direction Select Bit char oper 1 Calculation Transfer Function Select Bit char brstz1 Burst Transfer Select Bit char inte 1 End of Transfer Interrupt Select Bit char chain 1 Chained Transfer Select Bit char reserve 7 char mult 1 Multiple Transfer Select Bit pot unsigned short all Jmod unsigned short count Transfer count unsigned char near sadr Transfer source address unsigned char near dadr Transfer destination address Jdm index Transfer data array static unsigned char near data 5 0x11 0x22 0x33 0x44 0x55 Transfer destination static unsigned char near dest FORK kok k oko oko k k oko k k kok k oko I main RK IKK IK I KK IK I IK I void main void asm felr i w Interrupt disable
6. OPER BRST INTE CHAIN MULT 2 Transfer count COUNT b15 bo For a burst transfer once the cause of a DMACII transfer occurs a DMACII transfer is performed a number of times as set by the transfer count Detailed description the following register settings must be taken place step by step For detail configuration of each register please refer to M32C 80 Series Transfer Unit Select Bit 0 8 bits 1 16 bits Transfer Data Select Bit 0 Immediate data 1 Memory Transfer Source Direction Select Bit 0 Fixed address 1 Forward address Transfer Destination Direction Select Bit 0 Fixed address 1 Forward address Calculation Transfer Function Select Bit 0 Not used 1 Used Burst Transfer Select Bit 1 Burst transfer End of Transfer Interrupt Select Bit 0 Interrupt not used 1 Use interrupt Chained Transfer Select Bit 0 Chained transfer not used 1 Use chained transfer Nothing is assigned Set to 0000000b Multiple Transfer Select Bit 0 Multiple transfer not used Set the number of times transferred 3 Transfer source address SADR b15 bo Set the source address of transfer 4 Transfer destination address DADR b15 bo 16 bits Set the destination address of transfer REJ05B0639 0100 Rev 1 00 May 2005 M32C 80 Series Using DMACII Burst Transfer Page 3 of 9 ENESAS M320 80 Series Using DMACII Burst Tran
7. culation Transfer Without Calculation Transfer Yes Function Function With Calculation Transfer Function Interrupts not used Yes End of Transfer Interrupt P Interrupts used Not chai f Ye Chained Transfer Function ote aun ianslened Chain transferred REJ05B0639 0100 Rev 1 00 May 2005 Page 1 of 9 ENESAS M320 80 Series Using DMACII Burst Transfer 3 2 DMAC II Index The DMAC II index is configured with 8 bytes when interrupts and chain transfers are not used in burst transfer mode The DMAC II index must be located on the RAM area Beginning address of DMACII index BASE BASE 2 Transfer mode Transfer counter BASE 4 Transfer source address BASE 6 Transfer destination address Figure 1 DMAC II Index 3 3 DMAC II Transfer The interrupt requests from all peripheral functions whose ILVL2 ILVLO bits in the interrupt control register have been set to 111b constitute the cause of requests to DMAC II In this application note the INTO interrupt is used for the cause of DMAC II request 3 4 Setting Up the Relocatable Vector Table Set the beginning address of the DMAC II index in the interrupt vector for the peripheral function interrupt that constitutes the cause of DMAC II request REJ05B0639 0100 Rev 1 00 May 2005 Page 2 of 9 ENESAS 3 5 Register Setting To enable the operation defined in Section 3 HARDWARE MANUAL 1 Transfer mode MOD SIZE IMM UPDS UPDD
8. evel 7 is used for DMAC II transfers used for DMACII REJ05B0639 0100 Rev 1 00 May 2005 Page 6 of 9 ENESAS M320 80 Series Using DMACII Burst Transfer 5 Reference Renesas Technology Corporation Home Page http www renesas com E mail Support E mail csc renesas com Hardware Manual M 32C 80 Group Hardware Manual Use the latest version on the home page http www renesas com TECHNICAL UPDATE TECHNICAL NEWS Use the latest information on the home page http www renesas com REJ05B0639 0100 Rev 1 00 May 2005 Page 7 of 9 ENESAS REVISION HISTORY M32C 80 Series Using DMACII Burst Transfer Rev Date Description Summary 1 00 2005 05 20 Page First edition issued REJ05B0639 0100 Rev 1 00 May 2005 Page8of9 ENESAS M320 80 Series Using DMACII Burst Transfer Keep safety first in your circuit designs Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap
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10. sfer 5 RLVL register b7 bo ojoliloloj RLVL2 to RLVLO Stop Wait Mode Exit Minimum Interrupt Priority Level Control Bit FSIT High Speed Interrupt Set Bit Set to 0 DMAC II and high speed interrupts cannot be Nothing is assigned 9 used at the same time gt Set to 0 x DMAII DMAC II Select Bit Set to 1 Nothing is assigned Set to 00b 6 Interrupt Control Register Set all interrupt request registers for the b7 bo interrupts to be used as the cause of DMAC II olol loli lili requests ILVL2 to ILVLO Interrupt Priority Level Select Bit Set to 111b Set the priority level of the interrupt used as IR Interrupt Request Bit the cause of DMAC II request to 7 Set to 0 POL Polarity Switch Bit INTOIC to INT5IC 0 Selects falling edge or L 1 Selects rising edge or H LVS Level Sensitive Edge Sensitive Switch Bit INTOIC to INT5IC 0 Edge sensitive 1 Level sensitive The POL and LVS bits are accommodated in the INTOIC 3 Nothing is assigned INT5IC registers In other interrupt request registers set it Set to 00b ce REJ05B0639 0100 Rev 1 00 May 2005 Page 4 of 9 ENESAS M320 80 Series Using DMACII Burst Transfer 4 Example of a Sample Program 4 1 C language source KK IKK IR A KR k o kok o kok kok oko k kok k kok kok oko k kok k kok k k kok k k kok k kok k k kok k k kok k kk k kok OK FI
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