User Manual: S-band Transmitter (STX)
Contents
1. DRI1 0 Data rate of the encoder DR1 DRO 0 0 Full data rate 0 1 1 2 data rate 1 O 1 4 data rate 1 1 1 3 data rate QPSK or OQPSK modulation O QPSK 0 QPSK 1 OQPSK Pulse shaping filter active low roll off 0 35 French South African 18 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt FSATI PC registers Rev 1 6 French South African Institute of Technology nFILTER 0 Filter enabled 1 Filter disabled 9 2 3 Register 0x02 Debug register Bit 7 Bit6 Bit5 Bit4 Bit3 Bt2 Bit1 Bu e LED2 LED1 LEDO Writing to the debug register will activate the LEDs The debug LEDs are active high LEDs are not populated on flight boards unless otherwise specified 9 2 4 Register 0x03 PA power level register Bit 7 Bt6 Bit5 Bt4 Bit3 Bit2 Bit 1 Bit 0 PWR1 PWRO PWR 1 0 Power level of the power amplifier PWR1 PWRO 0 0 21 dBm 0 1 24 dBm 1 0 27 dBm 1 1 30 dBm 9 2 5 Register 0x04 Synth offset register Bit 7 Bit6 Bit5 Bt4 Bt3 Bt2 Btl Bt0 e D6 D5 D4 D3 D2 D1 DO A programmable frequency synthesizer is used to generate the STX carrier frequency The default frequency of 2400 MHz may be adjusted in steps of 500 kHz to a maximum of 2450 MHz When a value is written to the Synth offset register the synthesizer is reprogrammed to the new frequency which2. 20 9 2 10 Register 0x14 amp 0x15 Buffer underruns register 21 9 2 11 Register 0x16 amp 0x17 Buffer overruns register 21 9 2 12 Register 0x18 amp 0x19 Buffer count register o 21 9 2 13 Register Ox1A amp 0x1B RF output power register 21 9 2 14 Register 0x1C amp Ox1D PA temperature 22 9 2 15 Register 0x1E amp 0x1F Board temperature sensor top 22 9 2 16 Register 0x20 amp 0x21 Board temperature sensor bottom 22 9 2 17 Register 0x22 amp 0x23 Battery current register 23 9 2 18 Register 0x24 amp 0x25 Battery voltage register 23 9 2 19 Register 0x26 amp 0x27 PA current register ss ss 23 9 2 20 Register 0x26 amp 0x27 PA voltage register i 23 9 3 SPL Interface as EE a da te EED ede are SG 24 93 1 Transmit Ready 4 24 4 8 24h RR GR IE a ee a es 24 10 Test procedures 25 10 1 Transmit full buffer with buffer emptied i 25 10 2 Continuous transmit of user data with buffer not emptied 26 11 Special note regarding transmit power 27 iii List of Figures System block diagram Mechanical diagram shown in mm ESQ 126 13 G D header shown Telemetry data from STX ee es Block diagram of the CSK header connections and system layout PC 104 header pinouts Syn a BE prea on Rte od atte Gate oF WN RA iv List of Tables NOoTKR WN r
3. Amplifier RF Out Detect Figure 3 Telemetry data from STX French South African 9 of 27 www cput ac za fsati Institute of Technology System operation CPUT UM STX 01 Telemetry data Rev 1 6 french South African Institute of Technology The following telemetry data may be read from the STX via DC e Current drawn from the battery bus e Current drawn by the driver amplifier and power amplifier e Battery bus voltage level e Power amplifier voltage level e RF output power level e Power amplifier temperature e STX top side board temperature e STX bottom side board temperature The various analogue sensors used to measure these parameters are connected to an ADC The ADC values are read by the onboard processor and are made available via 12C A detailed list of the DC registers is provided in Section 9 2 French South African 10 of 27 www cput ac za fsati Institute of Technology Hardware interfacing CPUT UM STX 01 Rev 1 6 DAR gt FSATI French South African Institute of Technology 8 Hardware interfacing 8 1 CSK header connections PC 104 Header z E E E 5 2 2 3 2 E PSU Reset ERGA Supervisor PLL Dual DAC 2400 MHz 2450 MHz Telemetry ADC Ed o 25 as o gt Modulator lt Driver m gt Power Amplifier Figure 4 Block diagram of the CSK header conn
4. 1 s 1 4 1 2 and 1 W The transmit power levels have been optimised for 2400 MHz operation and as such the transmit power increases significantly as the transmit frequency is increased towards 2450 MHz If the power is set to 1 2 W at 2400 MHz the STX will output approximately 1 W at 2450 MHz The 1 W setting may overdrive the power amplifier at the higher frequencies in the range which may or may not damage it While this might not be an issue if the STX is to be used at a single frequency which is usually the case the transmit power levels must be recalibrated if it is to be used at a frequency higher than approximately 2405 MHz The calibration should be performed at manufacture yet the client will not be charged if this occurs at a later date it would however be best to make such a change at our premises The adjustment requires the replacement of a single resistor If no such adjustment is made the STX will continue to perform as expected yet attention must be paid to the power level settings at particular frequencies If the user has specified a particular startup frequency then the STX would be optimized accordingly for that selection at manufacture French South African 27 of 27 www cput ac za fsati Institute of Technology
5. D6 D5 D4 D3 D2 D1 DO This register contains the most recent power amplifier voltage reading It should have a nominal value of 5 Volts when the PA is in use Voltage value dec x 4 x 1073 V French South African 23 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt y SAT SPI Interface Rev 1 6 French South African Institute of Technology 9 3 SPI Interface The SPI interface is the High speed data interface to the STX Once the STX has been cor rectly configured data can be clocked in via SPI The user must ensure that buffer underruns and overruns do not occur by monitoring the Transmit Ready line H1 13 The SPI mode setting for the interface is Mode 0 CPOL 0 polarity CPHA 0 phase This means that the serial data MOST will be sampled on the rising edge of SCLK 9 3 1 Transmit Ready The data buffer size of the STX is 4096 bytes The Transmit Ready TR line will be a logic HIGH while data can be safely written to the data buffer The TR line will become a logic LOW when the buffer is filled with more than 512 bytes No more than 4096 bytes of data should be written to the data buffer via SPI at any one time this is to ensure that overruns do not occur It is recommended that the OBC sending data to the STX monitors the TR line when the TR line is HIGH it then sends user data while TR is LOW it waits The state of TR is
6. South African Institute of Technology Parameter Notes Min Typ Max Unit Physical L W H Dimensions 96 90 2 17 mm Weight 90 95 100 g Input ports Header connector PC 104 Output ports RF connector SMA 5 2 Materials Table 4 List of materials Materials Manufacturer TML CVCM WVR Application Note Scotch Weld 3M 0 97 0 02 0 32 Adhesive 2216 Epoxy Fixing B A PCB Material FR4 0 62 0 0 1 PCB Board NASA Worst Case Solder Resist CARAPACE 0 95 0 02 0 31 Solder Mask EMP110 Solder Sn63 5 3 Mechanical configuration French South African 5 of 27 www cput ac za fsati Institute of Technology ASotomm2at JO se3n31I3SUT 1Z JO 9 veau ymos your TesJ ez Doe ndo mmm 81 03 es 3816 77 47 i 55 22 724 79 i LS I vu EEEEEHEEEEEEEREEEEEHEEHEEE O HEREHEHEEHEEHEHEEEEHEHEHEEHEHHEHHEEE I wl EI EE EE EE EE EES EE EE EES EE EI DE EER EE ER ER HE EE EE Ee EE Ee a as DUDo RR S Ol Io ER a Sg a Sr e 0 n oooool
7. ground station receiver If the PA is used in the test e Write a value of 0x82 to register 0x00 This will put the STX into data mode with the PA on 0x02 may be written if the PA is not to be used e Wait for 33 ms at full data rate e Write a value of 0x01 to register 0x00 This will put the STX into sync mode with the PA off e Retrieve overrun underrun and buffer count telemetry data A small amount of underruns and a buffer count of zero indicates that all the data was sent e Write a value of 0x00 to register 0x00 This will reset the buffer and the overruns underruns and buffer count registers French South African 25 of 27 www cput ac za fsati Institute of Technology Test procedures CPUT UM STX 01 gt FSATI Continuous transmit of user Rev 1 6 French South African Institute of Technology 10 2 Continuous transmit of user data with buffer not emptied e Write a value of 0x00 to register 0x00 This will reset the buffer and the overruns underruns and buffer count registers e Write a value of 0x02 to register 0x03 This will configure the PA to have a 27 dBm power output Only necessary if the PA is used in the test e Confirm that the buffer is empty by checking the buffer count register e Write a value of 0x01 to register 0x00 This will put the STX into sync mode with the PA off e Transfer 4096 bytes of user data via SPI to the STX e Confirm buffer has been filled with no overruns by checking
8. level 04 h D6 D5 D4 D3 D2 D1 DO r w Synth offset 05 h nRST w Reset 11h D7 D6 D5 D4 D3 D2 D1 DO r Firmware version 12 h 8 8 PWRGD TXL r Status 13 h TR r Transmit ready 14h D15 D14 D13 D12 D11 D10 D9 D8 r Buffer underruns UB 15h D7 D6 D5 D4 D3 D2 D1 DO r Buffer underruns LB 16 h D15 D14 D13 D12 D11 D10 D9 D8 r Buffer overruns UB 17h D7 D6 D5 D4 D3 D2 D1 DO r Buffer overruns LB 18 h D12 D11 D10 D9 D8 r Buffer count UB 19 h D7 D6 D5 D4 D3 D2 D1 DO r Buffer count LB 1Ah D11 D10 D9 D8 r RF output power UB 1B h D7 D6 D5 D4 D3 D2 D1 DO r RF output power LB 1C h D11 D10 D9 Ds r PA temperature UB 1D h D7 D6 D5 D4 D3 D2 D1 DO r PA temperature LB 1E h T T10 T9 T8 T7 T6 T5 T4 r Board temperature top UB 1F h T3 T2 T1 TO r Board temperature top LB S 19751991 Dl BurejI9 ur Je Y NOU 91 TOX IS TNO LAdO NGojouyaay Jo ae 931 Wnos yauayy ILYS 3 VEE ASoj ouypay JO e3n3I3SUT UeoILIJVY ymos Uouexf LG JO LT es ez oe NAS MMM 9 2 16 9 2 17 9 2 18 9 2 19 9 2 20 Address MSB D7 D6 D5 D4 D3 D2 D1 LSB DO r w Register group 20 h TI T10 T9 T8 T7 T6 T5 T4 r Board temperature bottom UB 21 h T
9. o0 oo m beee NA 5 1 21 Dn DH m S ag i 5 85 oe 3 06 gee sae 000 508 E SKS H o 0 QO Oo Ei y LO O A DI Je ososm T in co 0000 ooo 200 CD QO Ow DON RS NNA ol ei ei Q bal SS LO N oi ei g EI ry S mol IIt N I KR LO N LO OO o 2 64 N Y 5 21 72 14 a S 4 80 01 84 10 Oooo 85 22 m Figure 2 Mechanical diagram shown in mm ESQ 126 13 G D header shown 5 77 alen _ 1105 mi g 7 335 Sep E 1 60 PT 13 TOMe In5TUOD TEIUBUIOWN SOTISII9JIBIBYO JeorTUeITD29JV QT Aen 10 XLSWA LAdO Waat Jo aynyiysuy eat yinos youayy IlLYS 3 Handling and storage CPUT UM STX 01 gt y SATI Rev 1 6 French South African Institute of Technology 6 Handling and storage Specific guidelines must be adhered to when handling transporting and storing the transmit ter Failure to follow these guidelines may result in damage to the unit or degradation in performance Although the unit has been tested at full RF output power across the temperature range 1t is advisable to fit an appropriate heat strap between the power amplifier and the chassis metal The heat strap may be attached to the bottom side of the unit where mounting holes have been provided around the power amplifier A heat strap may be cut from
10. the overrun and buffer count telemetry registers e Write a value of 0x81 to register 0x00 This will turn the PA on while still in sync mode 0x01 may be sent if the PA is not used in the test e Loop Monitor receive ready flag if flag is high then immediately transmit user data via SPI to the buffer otherwise do not transmit data via SPI Loop as many times as desired e Monitor transmit ready flag when the flag goes from low to high indicating less than 513 bytes in the buffer promptly stop sending SPI data to the STX and write a value of 0x01 to register 0x00 This will put the STX into Sync mode with the PA off e Retrieve overrun underrun and buffer count telemetry data The buffer count register should indicate a value less than 513 bytes if the data transfers were successful during the test then the overrun and underrun registers should be zero indicating that the data transfer timing is correct e Write a value of 0x00 to register 0x00 This will reset the buffer and the overruns underruns and buffer count registers and place the STX into Configuration mode French South African 26 of 27 www cput ac za fsati Institute of Technology Special note regarding transmit CPUT UM STX 01 gt j S ATI Rev 1 6 French South African Institute of Technology 11 Special note regarding transmit power Each STX s RF frequency is 2400 MHz at startup default transmit frequency Four power steps are selectable
11. 08 based encoding which ensures compatibility with low cost commercial ground segment receivers The STX frequency of operation is selectable from 2 4 2 45 GHz amateur band The frequency of operation is user selectable within the band The carrier frequency is adjustable in 500 kHz steps Output power is adjustable in 3 dB steps from 21 dBm to 30 dBm The STX is configured via an 12C data bus and high speed payload data is sent via SPI Data transmission rates of up to 2 Mbps are supported with 1 2 1 4 and Lis rate modes The STX is powered from the battery bus yet may be powered down externally via an enable line from the PC 104 header French South African 1 of 27 www cput ac za fsati Institute of Technology Overview CPUT UM STX 01 Encoding and modulation Rev 1 6 french South African Institute of Technology 2 1 Encoding and modulation overview e QPSK and OQPSK modulation schemes e Open Network Encoding scheme based on IntelSAT IESS 308 specifications e V 35 IntelSAT scrambler Differential encoding e Half rate convolutional encoding K 7 Pulse shaping filter 0 35 roll off factor e 2 Mbps data rate with full 1 2 1 4 and 1 8 data rate modes 1 Mbps maximum user data as half rate convolutional encoding is implemented French South African 2 of 27 www cput ac za fsati Institute of Technology Absolute maximum ratings CPUT UM STX 01 gt i SAT Rev 1 6 French South African Institute of Techno
12. 1 mm thick copper or brass plate and fastened to the unit with M1 6 screws washers and nuts 6 1 Power amplifier protection Caution must be taken to ensure that an appropriate 50 Q RF load at least 2 W A rating is presented to the RF output of the STX while the power amplifier is enabled Failure to do so could result in permanent damage to the power amplifier unit 6 2 Antenna impedance Physically touching an antenna or bringing reflective obstacles in close proximity to an antenna can affect the antenna s impedance and reflection coefficient at the frequencies AN at which it was designed thereby causing excessive RF power to be reflected which may cause permanent damage to the transmitter Care should be taken to keep the area around the antenna free of room reflections 6 3 ESD protection The STX incorporates static sensitive devices and care should be taken when han dling the module Under no circumstances should the transceiver be handled without appropriate electrostatic protection The STX should only be handled in a static dissipative environment 6 4 General handling The transmitter has been designed to withstand satellite flight conditions but care must still be taken when handling the hardware French South African 7 of 27 www cput ac za fsati Institute of Technology Handling and storage CPUT UM STX 01 Storage and shipping Rev 1 6 french South African Institute of Technology e Do not drop the h
13. 3 T2 T1 TO r Board temperature bottom LB 22 h D15 D14 D13 D12 D11 D10 D9 D8 r Battery current UB 23 h D7 D6 D5 D4 D3 D2 D1 DO r Battery current LB 24 h D12 D11 D10 D9 D8 r Battery voltage UB 25 h D7 D6 D5 D4 D3 D2 D1 DO r Battery voltage LB 26 h D15 D14 D13 D12 D11 D10 D9 D8 r PA current UB 27 h D7 D6 D5 D4 D3 D2 D1 DO r PA current LB 28 h al D12 D11 D10 D9 D8 r PA voltage UB 29 h D7 D6 D5 D4 D3 D2 D1 DO r PA voltage LB S 19751991 Dl 5UIOBJI97UT Ie Y MOM 91 1O X LS WA LAdO oe Sr Sp LYS JC NGojouyaay Jo aynyysu eauyy Wnos yauayy Data interfacing CPUT UM STX 01 gt y SAT PC registers Rev 1 6 French South African Institute of Technology 9 2 1 Register 0x00 Control register Bit 7 Bit6 Bt5 Bit4 Bt3 Bit 2 Bit 1 Bit 0 PA MODE1 MODEO MODEI1 0 Operating mode for the STX Model Mode 0 0 Configuration 0 1 Synchronisation Send sync word iL 0 Data Transmit real data from FIFO 1 1 Test data Transmit test counter PA O Power amplifer disabled 1 Power amplifier enabled Note If the PA enable bit is set while in Configuration mode the PA will remain disabled until the STX is changed to either Synchronisation Data or Test data mode 9 2 2 Register 0x01 Encoder register Bit 7 Bit6 Bt5 Bit4 Bit 3 Bit 2 Bit 1 Bit0 nFILTER O QPSK DR1 DRO
14. A off e Request telemetry relating to overruns underruns and the buffer count as a source of transmit verification e Place STX into config mode Notes In order to free up the OBC for the maximum amount of time when the STX is in data mode and operating the SPI transfer at 4 MHz 4096 bytes of user data may be placed into the buffer when the transmit ready flag indicates that there are 512 bytes or less in the buffer The amount of time that it takes for the SPI to transfer the data into the buffer is enough time for the FIFO to lower the amount of data bytes in the buffer and therefore balance the amount of data coming into the buffer and the amount going out of it On entering data mode from sync test data or config mode a filler byte 0x55 is first trans mitted indicating a change in the mode which is then followed by the user data French South African 14 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt y SAT PC registers Rev 1 6 French South African Institute of Technology When the buffer is filled with 4096 bytes of data it typically takes 33 ms to transmit all the data from the buffer at full data rate If the STX is in data mode with the PA off the buffer will still send data out and operate as per usual yet the data will not actually be transmitted to the ground station as the PA is not active The STX has a 15 minute failsafe timeout which disables the PA
15. Absolute maximum ratings SE SE SE SE ss 3 Electrical characteristics oaoa a ee 4 Mechanical specifications in ui ee e E a E aE SS T Se 5 List of materials Lat ia we e SE xe a Be oa ge isn e Aa RE is 5 PC 104 header pinout definitions i 12 GT 16 Temperature sensor data format 22 Nomenclature Abbreviations ADC Analogue to Digital Converter BCD Binary Coded Decimal CSK CubeSat Kit FIFO First In First Out FPGA Field Programmable Gate Array MC Major Component OBC On Board Computer PA Power Amplifier SPI Serial Peripheral Interface STX S band Transmitter TBD To Be Determined vi Overview CPUT UM STX 01 gt i SAT Rev 1 6 French South African Institute of Technology 1 Introduction This document describes the operation handling and storage of the first generation of the S band Transmitter STX The STX is an integrated RF data transmitter module supporting a maximum transmission bit rate of 2 Mbps 1 Mbps user data 1 Mbps encoding An overview of the STX is shown in Figure 1 Patch Power Vea Power Supply er RF Module i Control Telemetry e Control and Data Encoder Module High speed Data SR Figure 1 System block diagram 2 Overview The STX is a compact S band Transmitter designed for CubeSat nanosatellite missions It is compatible with the CubeSat nanosatellite standard with a CubeSat Kit PC 104 form factor The STX implements QPSK or OQPSK modulation with Intelsat IESS 3
16. Computer or Mass Storage should monitor the Transmit Ready TR line and send data as quickly as possible if the TR line is high to ensure that a buffer underrun does not occur FIFO empty condition The TR line is active high when there are less than 513 bytes in the buffer It is recommended French South African 13 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt y SAT Modes of operation Rev 1 6 French South African Institute of Technology that the SPI data source sends data to the STX at twice the required transmission rate If a buffer underrun occurs dummy data 0x55 will be transmitted 9 1 4 Test data mode Test data mode will continuously encode and send a test counter of data The counter begins at 0x00 and continues until OxFF before beginning again In this mode the data buffer will accept data via the SPI interface only until the internal FIFO is full 9 1 5 Recommended procedure for transmitting data A recommended procedure for transmitting user data with the STX is as follows e Ensure that a 50 Q load is connected at all times e Configure STX registers Power level data rate e Place STX into sync mode with PA on e Fill buffer with 4096 bytes of user data e Allow enough time for sync to occur with ground station e Place STX into data mode e Monitor transmit ready line transfer additional data to the buffer as required e Place STX into sync mode with P
17. FPGA RESET Input FPGA reset active low Yes H1 10 STX_EN Input STX enable active high Yes H2 45 VBATT_BUS Power Battery bus supply No H2 46 VBATT_BUS Power Battery bus supply No H2 29 GND Power Power ground No H2 30 GND Power Power ground No H2 32 GND Power Power ground No Either the DC or alternative I C option must be chosen not both 8 2 RF connector An SMA connector is used to connect the RF output of the STX to an antenna Please ensure that the correct connector is used and that it is correctly tightened and torqued When not transmitting into an antenna ensure that an appropriate 50 Q RF load is connected to prevent damaging the transmitter Refer to the mechanical dimensions of the STX shown in Figure 2 for the connector placement 8 3 STX enable The STX enable line allows the board to be powered down when not in use This is a hard line connected to the PC 104 header and its functionality needs to be configured at manufacture The STX may be configured to always be enabled if so desired negating the use of the enable line The enable line includes a pull up Pull below 1 2 V to disable the STX Float to enable or apply LVCMOS logic 1 8 V 3 3 V to enable the board French South African 12 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt y SAT Rev 1 6 French South African Institute of Technology 9 Data interfacing 9 1 Modes of operation The STX ha
18. Sa v Cape Peninsula D F SATI University of Technology French South African Institute of Technology User Manual S band Transmitter STX Document no CPUT UM STX 01 Revision 1 6 Date 28 February 2014 Name Date Signed Author Jason Quibell 28 February 2014 Author Charl Jooste 28 February 2014 Approved Francois Visser 28 February 2014 Document Control Rev 1 0 D 1 2 1 3 1 4 1 5 1 6 Date 26 July 2012 Revision Control Product S band Transmitter Section All Hardware and Description of Change First Release Reason for Change 14 September Additional data S 3 2012 8 information interfacing 28 January Data Additional Buffer size increased in 2013 interfacing information software version 1 2 Data 28 March interfacing Additional Soft E 2013 and test information ae pe arr gree procedures 16 September Additional 2013 All EEN Hardware update 27 November Additional 2013 All A Hardware update 28 February Additional 2014 All Ee Software update Revisions Part Number Notes Covered CPUT STX 01 1 7 Related Documents No Document Name Document Reference CPUT ICD STX STX Interface Control 01 Document CPUT TR STX STX Test Results XX Document Contents Document Control Revision Control Related Documents Nomenclature 1 Introduction 2 Overview 2 1 Encoding and modulation overview 3 Absolute maximum ratings 4 Electrical characte
19. also available via 12C when reading the Transmit Ready register 0x13 The availability of free slots in the buffer may be monitored by viewing the buffer count register 0x18 amp 0x19 French South African 24 of 27 www cput ac za fsati Institute of Technology Test procedures CPUT UM STX 01 gt FSATI Rev 1 6 French South African Institute of Technology 10 Test procedures This section describes the process of testing the STX When testing with the power amplifier on be sure to connect the RE output port to an appropriate 50 Q load Use an attenuator if required 10 1 Transmit full buffer with buffer emptied e Write a value of 0x00 to register 0x00 This will reset the buffer and the overruns underruns and buffer count registers e Write a value of 0x02 to register 0x03 This will configure the PA to have a 27 dBm power output Only necessary if the PA is used in the test e Confirm that the buffer is empty by checking the buffer count register e Write a value of 0x01 to register 0x00 This will put the STX into sync mode with the PA off e Transfer 4096 bytes of user data via SPI to the STX e Confirm buffer has been filled with no overruns by checking the overrun and buffer count telemetry registers e Write a value of 0x81 to register 0x00 This will turn the PA on while still in sync mode 0x01 may be sent if the PA is not used in the test e Wait for five seconds to allow for a sync lock occur with the
20. ardware e All work must be done in a clean room environment e Keep all metal objects away from the module to prevent accidental short circuiting e Gloves should be worn when handling flight hardware e Anti static procedures should be followed at all times 6 5 Storage and shipping The STX is shipped in anti static packaging enclosed in a hard protective case When storing the STX it should be placed in an anti static package and preferably stored in the hard protective case French South African 8 of 27 www cput ac za fsati Institute of Technology System operation CPUT UM STX 01 wei d S ATI Rev 1 6 French South African Institute of Technology 7 System operation The operation of the STX as well as the initialisation process is described in this section 7 1 Method of operation e The STX will be configured through commands sent via DC The commands set parame ters such as output power carrier frequency and transmission data rate Telemetry such as buffer underruns and overruns as well as data read from the ADC channels are made available A detailed description of all DC commands is provided in Section 9 2 e After configuration the STX may be placed into data mode where real time data from the SPI bus is encoded modulated and transmitted 7 2 Telemetry data Battery Bus 12C Bus Voltage VBAT Current Sensor Processor Regulation PA Current Sensor STX Board Temperature PA Temp Output Power
21. ections and system layout H2 H1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 34 36 38 40 42 44 48 50 52 113 5 7 9 11 18 15 17 19 21 23 25 27 31 33 35 37 39 41 43 47 49 51 2 4 6 8 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 1 3157 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 H1 0 STX enable HI m SPI signals 2 Ground H1 Ready signal H1 i5 FPGA Reset H1 21 2 Go Alternate I2C Figure 5 PC 104 header pinouts French South African Institute of Technology 11 of 27 H1 41 43 FG H2 5 Power Battery www cput ac za fsati Hardware interfacing CPUT UM STX 01 gt E i S AT RF connector Rev 1 6 French South African Institute of Technology Table 5 PC 104 header pinout definitions Pin Pin name I O type Description Optional H1 41 SDA Bidirectional DC serial data Yes H1 43 SCL Input DC serial clock Yes H1 23 SDA ALT Bidirectional Alternate I2C data Yes H1 21 SCL_ALT Input Alternate DC clock Yes H1 13 TR Output Transmitter ready for data Yes H1 09 COMM_SCLK Input SPI clock Yes H1 11 COMM_MOSI Input SPI data Yes H1 12 COMM_CS Input SPI chip select Yes H1 15 n
22. if it is left on accidentally The timer operates independently from the other control logic and as such the I C config register will indicate that the PA is on The PA would need to be disabled first before trying to use it again once a timeout has occurred 9 2 DC registers The STX is controlled by the following 8 bit registers which are accessed via the 12C interface The STX s PC address is 0x26 3810 All command registers 0x00 to 0x04 will default to 0x00 upon reset unless otherwise specified at manufacture Writing to DC The first byte of a transaction is always the pointer address of register and the second byte is the value to write to the register Reading from DC A write transaction is performed first to set the pointer register address Thereafter a read transaction is performed Further read transactions will auto increment the pointer French South African 15 of 27 www cput ac za fsati Institute of Technology ASoj ouypay JO e3n3I3SUT MEAT Y Y Nog YIUSIT LG Jo 9I mes ez oe NAS MMM 9 2 12 9 2 13 9 2 14 9 2 15 Table 6 I C register map Address MSB D7 D6 D5 D4 D3 D2 D1 LSB DO r w Register group 00 h PA MODE1 MODEO r w Control 01 h nFILTER O QPSK DR1 DRO r w Encoder 02 h E e e LED2 LED1 LEDO r w Debug 03 h z PWR1 PWRO r w PA power
23. logy 3 Absolute maximum ratings Table 1 Absolute maximum ratings Parameter Notes Value Unit Supply voltage Battery bus 14 V STX_EN STX enable 0 3 to 5 V Operating temperature 25 to 61 C Storage temperature 40 to 85 C French South African 3 of 27 www cput ac za fsati Institute of Technology Electrical characteristics CPUT UM STX 01 gt y S AT Rev 1 6 French South African Institute of Technology 4 Electrical characteristics Table 2 Electrical characteristics Parameter Notes Min Typ Max Unit Power Input voltage Battery bus 6 7 2 12 V Input current Vbatt 7 2 V 1 3 W RF power 0 31 A 1 4 W RF power 0 42 A 1 2 W RF power 0 55 A 1 W RF power 0 83 A Idle power PA off 0 6 0 7 W RF characteristics Frequency range Amateur band 2400 2450 MHz Output power 3 dBm increments 21 30 dBm Output return loss D dB Frequency stability 2 5 ppm Channel spacing 500 kHz PC Transmission speed 50 400 500 kbps Node address 0x26 hex Address scheme 7 bit SPI Transmission speed 4 8 Mbps French South African 4 of 27 www cput ac za fsati Institute of Technology Mechanical characteristics CPUT UM STX 01 Rev 5 Mechanical characteristics 5 1 Specifications 1 6 DAR Table 3 Mechanical specifications FSATI French
24. lots available Any data added to the transmit buffer while it is full will be dropped If this type of error is occuring then care must be taken as to when new data is added to the transmit buffer 9 2 12 Register 0x18 amp 0x19 Buffer count register Addr Bit7 Bt6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 0x18 D12 D11 D10 D9 D8 0x19 D7 D6 D5 D4 D3 D2 D1 DO This register provides an indication of how many bytes of the buffer are currently in use This value will lower as the transmitter sends out data and increase as the SPI data source sends data to the STX It is limited to a count of 4096 9 2 13 Register Ox1A amp 0x1B RF output power register Addr Bit7 Bt6 Bt5 Bt4 Bit3 Bit2 Bit1 Bit 0 Ox1A D11 D10 D9 D8 0x1B D7 D6 D5 D4 D3 D2 D1 DO This register contains the most recent RF power output reading Refer to the test results document for an explanation of the Vpgr value _ value dec x3 28 Voer 1096 x s V French South African 21 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt i S AT PC registers Rev 1 6 French South African Institute of Technology Temperature C Digital output Binary Hex 50 0011 0010 0000 320 25 0001 1001 0000 190 0 25 0000 0000 0100 004 0 25 1111 1111 1100 FFC 25 1110 0111 0000 E70 Table 7 Temperature sen
25. ristics 5 Mechanical characteristics KL Specifications A a a aod en a EE A DD Materiale Ty Bee nde een A e a Sao care ebe et E 5 3 Mechanical configuration pa e 6 Handling and storage 6 1 Power amplifier protection a a 6 2 Antenna impedance 6 3 tere s a Re Ws RE ae Gee as Ve A Ee edd Oe e e 64 General Handling Senon A ead e er a As eke e EE S 6 5 Storage and shipping i 7 System operation 7 1 Method of operation 7 2 Telemetry data aio Got had aed Sa Eee ee ee 8 Hardware interfacing 8 1 CSK header connections 9 Data interfacing 9 1 Modes of operation mo wie a ag ee oe ed LE a A NN 9 1 1 Configuration mode SS SS SS a SS SS e Se 9 1 2 Synchronisation mode a aaa 0002 SS SS ee 91 4 Testidata modes a a dee A 9 1 5 Recommended procedure for transmitting data OD a A EE 11 11 12 12 9 2 1 Register 0x00 Control resister o ces be A e Da STE e Dalal es 18 9 2 2 Register 0x01 Encoder register o e e 18 9 2 3 Register 0x02 Debug register 2 aa SS SS 19 9 2 4 Register 0x03 PA power level register 19 9 2 5 Register 0x04 Synth offset register 19 9 2 6 Register 0x05 Reset register o ee 20 9 2 7 Register 0x11 Firmware version register o a 20 9 2 8 Register 0x12 Status register i 20 9 2 9 Register 0x13 Transmit ready register o
26. s three basic modes of operation e Configuration mode e Synchronisation mode e Data mode 9 1 1 Configuration mode At power up the S band transmitter is in configuration mode The I C interface should be used to send telecommands to the STX to set it up prior to the transmission of data data rate transmit frequency transmit power etc 9 1 2 Synchronisation mode After configuration a telecommand may be sent to put the STX into Synchronisation Mode In this mode when the PA is activated synchronisation bytes will be sent from the transmitter no real data is read from the SPI input data FIFO This allows the ground station receiver to achieve lock synchronisation before actual payload data is transmitted over the link In this mode the data buffer will accept data via the SPI interface only until the internal FIFO is full indicated via the transmit ready line going low The synchronisation word is a CCSDS 32bit Attached Sync Marker ASM for non turbo coded data 0x1ACFFCID 9 13 Data mode In data mode data from the SPI input FIFO is transmitted The transmitter should only be placed into Data Mode when the SPI FIFO contains data indicated by the transmit ready line low this will avoid an initial buffer underrun condition Each SPI bus transaction transfers one or more byte s of data a maximum of 4096 bytes may be transferred per SPI transaction The buffer is 4096 bytes deep The source of the SPI data On Board
27. sati Institute of Technology Data interfacing CPUT UM STX 01 gt i S AT PC registers Rev 1 6 French South African Institute of Technology 9 2 17 Register 0x22 amp 0x23 Battery current register Addr Bit7 Bt6 Bt5 Bit4 Bt3 Bt2 Bit1 Bit0 0x22 D15 D14 D13 D12 D11 D10 D9 D8 0x23 D7 D6 D5 D4 D3 D2 D1 DO This register contains the most recent reading from the battery bus current sensor It returns a two s complement signed value with D15 being the signed bit Current value dec x 40 x 1078 A 9 2 18 Register 0x24 amp 0x25 Battery voltage register Addr Bit7 Bit6 Bt5 Bt4 Bit3 Bt2 Bit1 Bit0 0x24 D12 D11 D10 D9 D8 0x25 D7 D6 D5 D4 D3 D2 D1 DO This register contains the most recent battery voltage reading Voltage value dec x 4 x 1073 V 9 2 19 Register 0x26 amp 0x27 PA current register Addr Bit7 Bit6 Bt5 Bt4 Bit3 Bt2 Bit1 Bit0 0x26 D15 D14 D13 D12 D11 D10 D9 D8 0x27 D7 D6 D5 D4 D3 D2 D1 DO This register contains the most recent reading from the power amplifier current sensor It returns a signed value with D15 being the signed bit Negative values are returned in two s complement Current value dec x 40 x 1078 A 9 2 20 Register 0x26 amp 0x27 PA voltage register Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 0x28 D12 D11 D10 D9 D8 0x29 D7
28. sor data format 9 2 14 Register 0x1C amp 0x1D PA temperature Addr Bit7 Bt6 Bt5 Bt4 Bit3 Bit2 Bit1 Bit 0 0x1C D11 D10 D9 D8 0x1D D7 D6 D5 D4 D3 D2 D1 DO This register contains the most recent reading from the PA s temperature sensor The temper ature sensor is only enabled when the PA is being used _ lue dec x3 o Temperature e 0 5 x 100 C 9 2 15 Register 0x1E amp 0x1F Board temperature sensor top Addr Bit7 Bt6 Bt5 Bt4 Bit3 Bit2 Bit1 Bit0 0x1E T11 T10 9 T8 T7 T6 T5 T4 0x1F T3 T2 T1 TO This register contains the most recent reading from the temperature sensor located on the top of the board T11 is a signed bit Negative values are returned in two s complement The data format of the temperature sensor is illustrated in Table 7 Temperature T11 TO x 0 0625 C 9 2 16 Register 0x20 amp 0x21 Board temperature sensor bottom Addr Bit7 Bt6 Bt5 Bit4 Bit3 Bt2 Bit1 Bit0 0x20 T11 T10 T9 T8 T7 T6 T5 T4 0x21 T3 T2 T1 TO This register contains the most recent reading from the temperature sensor located on the bottom of the board T11 is a signed bit Negative values are returned in two s complement The data format of the temperature sensor is illustrated in Table 7 Temperature T11 TO x 0 0625 C French South African 22 of 27 www cput ac za f
29. supply is operating correctly whilst the PA is activated 9 2 9 Register 0x13 Transmit ready register Bit 7 Bit6 Bit5 Bit4 Bt3 Bt2 Btl Bt0 TR The transmit ready TR signal register provides an indication as to when data can be written to the STX s buffer This is identical to the TR hard signal made available to the PC 104 header if requested at manufacture although as a pollable register The TR signal has its bit set if data in the transmit buffer drops below a threshold value of 513 bytes of the 4096 byte buffer French South African 20 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt i S AT PC registers Rev 1 6 French South African Institute of Technology 9 2 10 Register 0x14 amp 0x15 Buffer underruns register Addr Bit7 Bt6 Bt5 Bit4 Bt3 Bt2 Bit1 Bit0 0x14 D15 D14 D13 D12 D11 D10 D9 D8 0x15 D7 D6 D5 D4 D3 D2 D1 DO The transmit buffer underrun register increments by one each time a filler byte 0x55 is transmitted while in data mode 9 2 11 Register 0x16 amp 0x17 Buffer overruns register Addr Bit7 Bt6 Bt5 Bit4 Bt3 Bt2 Bit1 Bit0 0x16 D15 D14 D13 D12 D11 D10 D9 D8 0x17 D7 D6 D5 D4 D3 D2 D1 DO The transmit buffer overrun register increments by one each time a byte is written to the transmit buffer when there are no free s
30. will be equal to the default frequency of 2400 MHz plus the value in the Synth offset register in 500 kHz increments E g if Synth offset register 0x01 1 then f 2400 5 MHz E g if Synth offset register 0x64 100 then f 2450 MHz French South African 19 of 27 www cput ac za fsati Institute of Technology Data interfacing CPUT UM STX 01 gt FSATI PC registers Rev 1 6 French South African Institute of Technology 9 2 6 Register 0x05 Reset register Bit 7 Bit6 Bt5 Bit4 Bt3 Bit2 Btl Bit 0 nRST Writing a 0 to this register will cause a soft reset of the FPGA logic placing it into a known good state This will reset all registers to their default values 9 2 7 Register 0x11 Firmware version register Bit 7 Bit6 Bit5 Bt4 Bt3 Bt2 Btl Bt0 D7 D6 D5 D4 D3 D2 D1 DO This register is a BCD encoded value Bits 7 4 represent the Major number whilst bits 3 0 represent the Minor number A firmware version of 1 5 has a Major number equal to 1 and a Minor number equal to 5 0x15 in hex 9 2 8 Register 0x12 Status register Bit 7 Bit6 Bit5 Bit4 Bt3 Bit 2 Bit 1 Bit 0 PWRGD TXL This register contains the frequency lock detect signal for the transmitter TXL A value of 1 indicates that a lock was achieved The power good PWRGD signal will be 1 indicating that the PA power
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