ISL33001, ISL33002, ISL33003 Datasheet
Contents
1. TEMP MIN MAX PARAMETER SYMBOL CONDITIONS C Note 9 TYP Note 9 UNITS POWER SUPPLIES Vcc4 Supply Range Veca Full 2 3 5 5 Vcc2 Supply Range Vcc2 ISL33002 and ISL33003 Full 2 3 5 5 Supply Current from Vcc4 lect Vcc4 5 5V ISL33001 only Note 11 Full 2 1 4 0 mA Veca Vcc2 5 5V ISL33002 and ISL33003 Full 2 0 3 0 mA Note 11 Supply Current from Veco lcco Vec2 Vec1 5 5V ISL33002 and ISL33003 Full 0 22 0 6 mA Note 11 Veca Shut down Supply ISHDN4 Veca 5 5V VEN GND ISL33001 only Full 0 5 HA Current Veca Voc2 5 5V Ven GND ISL33003 only Full 0 05 pA Note 13 Vcc2 Shut down Supply ISHDN2 Veca Vcc2 5 5V VEN GND ISL33003 only Full u 0 06 yA Current Note 13 START UP CIRCUITRY Precharge Circuitry VpRE SDA and SCL pins floating Full 0 8 1 1 2 V Voltage Enable High Threshold VEN H 25 0 5 Voc 0 7 Vcc V Voltage Enable Low Threshold VEN L 25 0 3 Vcc 0 5 Vcc V Voltage Enable Pin Input Current lEN Enable from OV to Vcc4 ISL33001 and Full 1 0 1 1 uA ISL33003 Enable Delay On Off tEN HL ISL33001 and ISL33003 Note 10 25 10 ns Enable Delay Off On tEN LH ISL33001 and ISL33003 Figure 3 25 86 us Bus Idle Time tipLE Figure 4 Note 12 Full 50 83 150 us Ready Pin OFF State lorr ISL33001 only 25 1 0 1 1 uA Leakage Current Ready Delay On Off tREADY HL_ 19L33001 only Note 10 25 10 ns S2. 85 C 8 Ld MSOP Package Notes 4 7 151 50 ESD Ratings See ESD PROTECTION on page 5 8 Ld SOIC Package Notes 4 7 120 56 Maximum Storage Temperature Range 65 C to 150 C Operating Conditions Maximum Junction Temperature 150 C Pb Free Reflow Profile see TB493 Temperature Range Ta 40 C to 85 C Vcc4 and Vcco Supply Voltage Range 2 3V to 5 5V CAUTION Do not operate at or near the maximum ratings listed for extended periods of time Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTES 4 0jA is measured with the component mounted on a high effective thermal conductivity test board in free air See Tech Brief TB379 for details 5 0jA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 6 For 0jc the case temp location is the center of the exposed metal pad on the package underside 7 For Ojc the case temp location is taken at the package top center Electrical Specifications Ven Vcc4 Veca 2 3V to 5 5V Veco 2 3V to 5 5V unless otherwise noted Note 8 Boldface limits apply over the operating temperature range 40 C to 85 C
3. 10 11 FIGURE 18 SDA SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs TEMPERATURE Vos mV ACCELERATOR PULSE WIDTH ns T 25 C T 40 C 0 1 2 3 4 5 6 7 8 10 11 loL mA FIGURE 20 INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs TEMPERATURE 800 See Figure 9 700 T 25 C 600 40 T 85 C J T 40 C 500 400 300 200 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Vcc V FIGURE 22 ACCELERATOR PULSE WIDTH vs Vec Submit Document Feedback 12 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 a Typical Performance Curves Continued CiN Cour 10pF Veca Vcc2 Voc Ta 25 C Unless Otherwise 50 gt Oo Oooo 50 EET RpuLL uP 2 7kQ r died CiN 10pF T 85 C Court 100pF 40 40 7 7 E X T 25 C x 30 30 a a z z o o E E lt 20 T 40 C 20 Ls Vec 3 3V RpuLL uP 10kQ Cin 50pF 02 Se pe 0 L 20 25 30 35 40 45 50 55 60 0 100 200 300 400 500 600 700 800 900 Vec V Court pF FIGURE 23 PROPAGATION DELAY H L vs Voc FIGURE 24 PROPAGATION DELAY H L vs Cour a a a Die Characteristics 12 SUBSTRATE AND TDFN THERMAL PAD POTENTIAL 41 Vec 2 3V LLL LL y POWERED UP GND T
4. intersil I7c Bus Buffer with Rise Time Accelerators and Hot Swap Capability ISL33001 ISL33002 ISL33003 The ISL33001 ISL33002 ISL33003 are 2 Channel Bus Buffers that provide the buffering necessary to extend the bus capacitance beyond the 400pF maximum specified by the 2c specification In addition the ISL33001 ISL33002 ISL33003 feature rise time accelerator circuitry to reduce power consumption from passive bus pull up resistors and improve data rate performance All devices also include hot swap circuitry to prevent corruption of the data and clock lines when I C devices are plugged into a live backplane and the ISL33002 and ISL33003 add level translation for mixed supply voltage applications The ISL33001 ISL33002 ISL33003 operate at supply voltages from 2 3V to 5 5V at a temperature range of 40 C to 85 C Summary of Features PART LEVEL ENABLE READY ACCELERATOR NUMBER TRANSLATION PIN PIN DISABLE ISL33001 No Yes Yes No ISL33002 Yes No No Yes ISL33003 Yes Yes No No Related Literature AN1543 ISL33001MSOPEVAL1Z ISL33002MSOPEVAL1Z ISL33003MSOPEVAL1Z Evaluation Board User s Manual AN1637 Level Shifting Between 1 8V and 3 3V Using i c Buffers BACK PLANE FIGURE 1 TYPICAL OPERATING CIRCUIT Features 2 Channel 12C compatible bi directional buffer e 2 3VDC to 5 5VDC supply range gt 400kHz operation Bus capacitance buffering Rise time accelerat
5. 2 PROCESS S 0 25um CMOS lt E lt lt 6 s 7 6 30 10 10 30 50 70 90 TEMPERATURE C FIGURE 25 SDA SCL PIN CAPACITANCE vs TEMPERATURE vs Vcc For additional products see www intersil com en products html Intersil products are manufactured assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www intersil com en support qualandreliability html Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com Submit Document Feedback 13 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Revision History The revision history provided is for informational purposes only and is believed to be accurate but not warranted Please go to web to make sure you have the latest revision
6. DATE REVISION CHANGE July 11 2014 FN7560 6 In Features on page 1 changed Low quiescent Current from 2 2mA to 2 1mA On page 4 added Pb Free Reflow Profile entry to Thermal Info section In Electrical Spec table on page 4 changed Vcc to Vcc4 in the Supply Current from Veco row In Electrical Spec table on page 5 for parameter Input Low Threshold moved the TYP column entry to the MAX column On page 6 Figure 4 clarified the associated notes On page 7 Figure 8 changed lacc to IrRAN acc and noted that the AV At is for the accelerator portion of the waveform December 19 2013 FN7560 5 Added Note 13 at the end of the Elec Spec table on page 5 as follows 13 If the Vcc1 and Vcc2 voltages diverge then the shut down Icc increases on the higher voltage supply Added reference Note 13 after ISL33003 only in rows for Vcc1 and Vcc2 Shut down Supply current parameters last 2 rows of Power Supplies section on page 4 October 12 2012 FN7560 4 Changed SDA IN SCL IN 0 3V to Vcc4 0 3 V SDA OUT SCL_OUT 0 3V to Vcc2 0 3 V ENABLE READY ACC 0 3V to Vcc4 0 3 V to SDA IN SCL IN SDA OUT SCL OUT READY 0 3V to 7V ENABLE ACC 0 3V to Vcc4 0 3 V in the Absolute Maximum Ratings section at the top of page 4 Removed Pb free Reflow Profile and link from Thermal Information section at the top of page 4 Added open drain and Connect to 1
7. Pin Configurations ISL33001 ISL33001 8 LD TDFN 8 LD SOIC MSOP TOP VIEW TOP VIEW EN Vcc1 EN 1 8 Vcc1 EN H SCL OUT 2 SDA OUT SCL_OUT 2 SDA_OUT scL IN 3 6 sDA IN SCL IN 3 6 SDA IN GND GND 4 FS READY 4 5 READY ISL33002 ISL33002 8 LD TDFN 8 LD MSOP TOP VIEW TOP VIEW Vcc2 1 8 Vcc1 Vcc2 1 8 Vcc1 SCL_OUT 2 SDA_OUT scL our 2 SDA_OUT SCL_IN 3 6 SDA IN SCL IN 3 6 SDA IN eND 1 s Acc GND 4 5 Acc Submit Document Feedback 2 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Pin Configurations Continued ISL33003 8 LD TDFN TOP VIEW ISL33003 8 LD MSOP TOP VIEW Vcc2 1 8 Vcc1 Vcc2 1 8 Vcc1 SCL_OUT 2 SDA_OUT SCL_OUT 2 SDA_OUT SCL_IN 3 6 SDA IN SCL IN 3 6 SDA IN GND 4 5 EN cnND 4 5 EN a a a Pin Descriptions PIN PIN NAME NUMBER FUNCTION NOTES Vcci 8 Vcc4 power supply 2 3V to 5 5V Decouple Vcc to ground with a high frequency 0 01pF to O 1pF capacitor Vcc2 1 Vcc2 power supply 2 3V to 5 5V Decouple Vcc2 to ground with a high frequency ISL33002 8 LD TDFN 8 LD MSOP 0 01pF to 0 1yF capacitor In level shifting applications SDA OUT and SCL OUT logic ISL33003 8 LD TDFN 8 LD MSOP thresholds are referenced to Vcc2 supply levels Connect pull up resistors on these pins to Voca GND 4 Device Ground Pin EN 1 Buffe
8. and SCLpins 25 0 3 Vcc4 V Input Output Offset Vos Vcc4 3 3V 10kO to Vcc4 on SDA and SCL pins Full 0 50 150 mV Voltage ViNpuT 0 2V Vcc2 3 3V ISL33002 and ISL33003 Figure 5 Output Low Voltage VoL Voc4 2 7V Vinput OV Isink 3mA on Full 0 4 V SDA SCL pins Veco 2 7V ISL33002 and ISL33003 Figure 6 Buffer SDA and SCL Pins Cin Figure 25 25 10 pF Input Capacitance Input Leakage Current ILEAK SDA and SCL pins Vcc4 5 5V Full 5 0 1 5 pA Vcc2 5 5V ISL33002 and ISL33003 TIMING CHARACTERISTICS SCL SDA Propagation tPHL CLoap 100pF 2 7kQ to Vcc4 on SDA and SCL 25 0 27 100 ns Delay High to Low pins Vcc4 3 3V Veco 3 3V ISL33002 and ISL33003 Figure 7 SCL SDA Propagation tPLH CLoap 100pF 2 7KQ to Vcc4 on SDA and SCL 25 0 2 26 ns NOTES 8 The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data sheet 9 Parameters with MIN and or MAX limits are 10096 tested at 25 C unless otherwise specified Temperature limits established by characterization and are not production tested 10 Typical value determined by design simulations Parameter not tested 11 Buffer is in the connected state 12 ISL33002 and ISL33003 limits established by characterization Not production tested 13 If the Vcc4 and Vcco voltages diverge then the shut down Icc increases on the higher voltage supply Submit Document Feedbac
9. per ANSI Y14 5M 1994 Package length does not include mold flash protrusions or gate burrs Mold flash protrusion and gate burrs shall not exceed 0 15mm 0 006 inch per side Package width does not include interlead flash or protrusions Interlead flash and protrusions shall not exceed 0 25mm 0 010 inch per side feature must be located within the crosshatched area Terminal numbers are shown for reference only The lead width as measured 0 36mm 0 014 inch or greater above the The chamfer on the body is optional If it is not present a visual index seating plane shall not exceed a maximum value of 0 61mm 0 024 inch necessarily exact Controlling dimension MILLIMETER Converted inch dimensions are not This outline conforms to JEDEC publication MS 012 AA ISSUE C Submit Document Feedback 18 intersil FN7560 6 July 11 2014
10. s products address some of the largest markets within the industrial and infrastructure mobile computing and high end consumer markets For the most updated datasheet application notes related documentation and related parts please see the respective product information page found at www intersil com You may report errors or suggestions for improving this datasheet by visiting www intersil com ask Reliability reports are also available from our website at www intersil com support Submit Document Feedback 14 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Package Outline Drawing L8 3x3H 8 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE TDFN Rev 0 2 08 PIN 1 INDEX AREA 4X TOP VIEW 2 88 FA tro tr 2 80 2 20 Hh wn TYPICAL RECOMMENDED LAND PATTERN PIN 1 INDEX AREA 8 X 0 40 20 5 x 0 10 MC AB 8 X 0 25 BOTTOM VIEW SEE DETAIL X 0 80 MAX 7 ooe BASE PLANE SEATING PLANE oes c SIDE VIEW DETAIL X NOTES 1 Dimensions are in millimeters Dimensions in for Reference Only 2 Dimensioning and tolerancing conform to AMSE Y14 5m 1994 3 Unless otherwise specified tolerance Decimal 0 05 4 Lead width dimension applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip 5 Tiebar shown if present is a non functional feature 6 The configuration of
11. 0kQ pull up resistor to Vcc4 in Pin Descriptions in the READY section on page 3 October 11 2011 FN7560 3 Converted to new datasheet template Changed Title of datasheet from 2 Wire Bus Buffer With Rise Time Accelerators and Hot Swap Capability to I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability Pg 1 added to Related Literature AN1637 Level Shifting Between 1 8V and 3 3V Using I2C Buffers Replaced POD M8 118 Rev 3 with Rev 4 due to the following changes Corrected lead width dimension in side view 1 from 0 25 0 036 to 0 25 0 36 Replaced POD M8 15 Rev 1 with Rev 3 due to the following changes Changed in Typical Recommended Land Pattern the following 2 41 0 095 to 2 20 0 087 0 76 0 030 to 0 60 0 023 0 200 to 5 20 0 205 Figure 3 was Fig1 Added I tDELAY1 lt tEN LH then tDELAY2 tEN LH tIDLE tREADY LH If tDELAY1 gt tEN LH then tDELAY2 tEN LH tREADY LH and replaced graph September 13 2010 FN7560 2 Added SOIC package information to datasheet for ISL33001 April 30 2010 FN7560 1 Changed typical value of Supply Current from Vcc4 on page 4 for ISL33001 only from 2 2mA to 2 1mA Changed typical value of Input Output Offset Voltage on page 5 from 100mV to 50mV March 18 2010 FN7560 0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions The company
12. MP RANGE PACKAGE PKG Notes 1 2 3 MARKING C Pb free DWG ISL33001IRTZ 3001 40 to 85 8 Ld TDFN 0 65mm Pitch L8 3x3A ISL33001IRT2Z 01R2 40 to 85 8 Ld TDFN 0 5mm Pitch L8 3x3H ISL33001IBZ 33001 IBZ 40 to 85 8 Ld SOIC M8 15 ISL330011UZ 33001 40 to 85 8 Ld MSOP M8 118 ISL33002IRTZ 3002 40 to 85 8 Ld TDFN 0 65mm Pitch L8 3x3A ISL33002IRT2Z 02R2 40 to 85 8 Ld TDFN 0 5mm Pitch L8 3x3H ISL330021UZ 33002 40 to 85 8 Ld MSOP M8 118 ISL33003IRTZ 3003 40 to 85 8 Ld TDFN 0 65mm Pitch L8 3x3A ISL33003IRT2Z O3R2 40 to 85 8 Ld TDFN 0 5mm Pitch L8 3x3H ISL33003IUZ 33003 40 to 85 8 Ld MSOP M8 118 ISL33001MSOPEVAL1Z ISL33001 Evaluation Board ISL33002MSOPEVAL1Z ISL33002 Evaluation Board ISL33003MSOPEVAL1Z ISL33003 Evaluation Board NOTES 1 Add T suffix for tape and reel Please refer to TB347 for details on reel specifications 2 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and 10096 matte tin plate plus anneal e3 termination finish which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 3 For Moisture Sensitivity Level MSL please see device information page for ISL33001 ISL33002 ISL33003 For more information on MSL please see techbrief TB363
13. URE 7A TEST CIRCUIT FIGURE 7B MEASUREMENT POINTS FIGURE 7 PROPAGATION DELAY ITRAN Acc CAVIAt AVIAt is for only the accelerator portion of the waveform 2 TkQ 27kQ 2 7kO 10kQ Vx lt Vcc1 See Figure 22 FIGURE 8 ACCELERATOR CURRENT TEST CIRCUIT FIGURE 9 ACCELERATOR PULSE WIDTH TEST CIRCUIT Submit Document Feedback 7 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 m SDAIN a TE SDA_OUT M2 M1 RSETME Hj ISL33001 ONLY ACCELERATOR Ir BN Su i LOGIC CONTROL I START UP CIRCUITRY S Vcc1 ad HEU Vcc2 H ISL33002 AND ISL33003 ISL33001 AND ISL33003 P Precarce gt j ISL33002 ONLY SEEN TE SCL OUT M3 LS E FIGURE 10 CIRCUIT BLOCK DIAGRAM M4 Application Information The ISL33001 ISL33002 ISL33003 ICs are 2 Wire Bidirectional Bus Buffers designed to drive heavy capacitive loads in open drain open collector systems The ISL33001 ISL33002 ISL33003 incorporate rise time accelerator circuitry that improves the rise time for systems that use a passive pull up resistor for logic HIGH These devices also feature hot swapping circuitry for applications that require hot insertion of boards into a host system i e servers racks and I O card modules The ISL33001 features a logic output flag READY that signals the status of the buffer and an EN pin to enable or disable the buffer The ISL33002 features two separate supply pins for voltage level shifting on the I O p
14. cc4 5 33002 AND FIGURE 14 Icc4 DISABLED CURRENT vs Veca ISL33003 ISL33003 0 24 r 60 Vcc1 5 5V T S325 G Vec1 5 5V 0 22 50 T 40 C 0 20 T 85 C 40 018 8 g T 85 C T 25 C 0 16 2 k 20 0 14 10 0 12 0 10 0 20 25 30 35 40 45 50 55 60 20 25 30 35 40 45 50 55 60 Vcc2 V Vcc2 V FIGURE 15 Icc2 ENABLED CURRENT vs Vcc2 ISL33002 AND FIGURE 16 Icc2 DISABLED CURRENT vs Vcc2 ISL33003 ISL33003 Submit Document Feedback 11 intersil FN7560 6 July 14 2014 ISL33001 ISL33002 ISL33003 a Typical Performance Curves Continued CiN Court 10pF Veca Vcco Voc Ta 25 C Unless Otherwise 120 100 80 60 VoL mV 40 20 0 1 2 3 4 5 6 7 8 9 10 1 lo mA FIGURE 17 SDA SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs Vcc 100 90 Vec 5 5V 80 70 50 40 Vcc 2 3V Vcc 3 3V Vos mV 30 20 10 VIN 0 2V 0 1 2 3 4 5 6 7 8 9 10 11 lo mA FIGURE 19 INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs Vec ACCELERATOR CURRENT mA 20 25 30 35 40 45 50 55 6 0 Vcc V FIGURE 21 ACCELERATOR PULL UP CURRENT vs Vcc VoL mV 120 100 T 40 C 80 60 40 20 4 5 6 lot mA 7 8
15. cing conform to JEDEC MO 187 AA and AMSEY14 5m 1994 Plastic or metal protrusions of 0 15mm max per side are not included Plastic interlead protrusions of 0 15mm max per side are not included 4 A Dimensions are measured at Datum Plane H 6 Dimensions in are for reference only Submit Document Feedback 17 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Package Outline Drawing M8 15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4 1 12 DETAIL A AN 1 27 0 050 a 0 40 0 016 0 60 0 023 ae 27 0 050 A INDEX 6 20 0 244 ae AREA 5 80 0 228 0 50 0 20 4 00 0 157 0 25 0 01 3 80 0 150 L J rf U 8 d Sus A l 0 25 0 010 0 19 0 008 TOP VIEW SIDE VIEW B 2 20 0 087 gt ls SEATING PLANE NEN m 5 00 0 197 gt 1 75 0 069 3 4 80 0 189 1 35 0 053 N 3 dae C 4 5 lt 1 27 0 050 0 25 0 010 Jd m 0 10 0 004 0 51 0 020 0 33 0 013 adii lt 520 0205 SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES 1 2 Dimensioning and tolerancing
16. d when crossing the buffer release threshold When ACC is driven low the accelerators are disabled For lightly loaded buses having the accelerators active may cause ringing or noise on the rising edge transition Disabling the accelerators will have the buffers continue to perform level shifting with the Vcc4 and Veco supplies and provide capacitance buffering Propagation Delays On a low to high transition the rising edge signal is determined by the bus pull up resistor load capacitance and the accelerator current from the ISL33001 ISL33002 ISL33003 buffer Prior to the accelerators becoming active the buffer is connected and the output voltage will track the input of the buffer When the accelerators activate the buffer connection is released and the signal on each side of the buffer rises independently The accelerator current on both sides of the buffer will be equal If the pull up resistance on both sides of the buffer are also equal then differences in the rise time will be proportional to the difference in capacitive loading on the two sides Submit Document Feedback 9 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Because the signals on each side of the buffer rise independently the propagation delay can be positive or negative If the input side rises slowly relative to the output i e heavy capacitive loading on the input and light load on the output then the propagation delay tp y is ne
17. dless of the bus capacitance seen on the SDA SCL lines The Bus Idle or Stop Bit condition requires valid logic high voltages to give a valid connection state Pull up resistor values 20k0 or smaller are recommended to overcome the typical 150k0 impedance of the pre charge circuitry delivering valid high levels Submit Document Feedback 10 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 a Typical Performance Curves c c 10pF Voc1 Veco Vec Ta 25 C Unless Otherwise Specified 2 4 600 2 3 550 2 2 Edi 24 2 0 450 T 25 C lt 19 z 400 FY 85 C E 18 350 o o 9 47 300 1 6 250 1 5 14 200 13 150 1 2 100 20 25 30 35 40 45 50 55 60 20 25 30 35 40 45 50 5 5 6 0 Vcc1 V Vcc4 V FIGURE 11 Icc4 ENABLED CURRENT vs Vcc1 ISL33001 FIGURE 12 Icc4 DISABLED CURRENT vs Vcc4 ISL33001 24 60 I 2 3 I Vcc2 5 5V Vcc2 5 5V 2 2 50 2 1 2 0 40 T 19 T E c lt 18 30 T 25 C 8 1 7 O T 85 C 1 6 20 1 5 1 4 10 1 3 1 2 0 20 25 30 35 40 45 50 55 60 20 25 30 35 40 45 50 55 60 Vcc1 V Vcc1 V FIGURE 13 Icc4 ENABLED CURRENT vs V
18. e output of the buffer will have an input to output offset voltage The output voltage of the buffer is determined by Equation 1 Vout Viv Vos IVcc PpuLL ue fon EQ 1 Where Vos is the buffer internal offset voltage Rpyj up is the pull up resistance on the SDA SCL pin to Vcc and ron is the ON resistance of the buffer s internal NMOS pull down device The last term of the equation is the additional voltage drop developed by sink current and the internal resistance of the transistor The Vos of the buffer can be determined by Figures 19 20 and is typically 40mV Reducing the pull up resistor values increases the sink current and increases the output voltage of the buffer for a given input low voltage Figures 17 through 20 Rise Time Accelerators The ISL33001 ISL33002 ISL33003 buffer rise time accelerators on the SDA SCL pins improve the transient performance of the system Heavy load capacitance or weak pull up resistors on an Open Drain bus cause the rise time to be excessively long which leads to data errors or reduced data rate performance The rise time accelerators are only active on the low to high transitions and provide an active constant current source to slew the voltage on the pin quickly Figure 21 The rise time accelerators are triggered immediately after the buffer release threshold approximately 3096 of Vcc on both sides of the buffer is crossed Once triggered the accelerators are active for a defined
19. gative If the output side rises slowly relative to the input tp u is positive For high to low transitions there is a finite propagation delay through the buffer from the time an external low on the input drives the NMOS output low This propagation delay will always be positive because the buffer connect threshold on the falling edge is below the measurement points of the delay In addition to the propagation delay of the buffer there will be additional delay from the different capacitive loading of the buffer Figures 23 and 24 show how the propagation delay from high to low tpp is affected by Vcc and capacitive loading The buffer s propagation delay times for rising and falling edge signals must be taken into consideration for the timing requirements of the system SETUP and HOLD times may need to be adjusted to take into account excessively long propagation delay times caused by heavy bus capacitances Pull Up Resistor Selection While the ISL33001 ISL33002 ISL33003 2 Channel buffers are designed to improve the rise time of the bus in passive pull up systems proper selection of the pull up resistor is critical for system operation when a buffer is used For a bus that is operating normally without active rise time circuitry using the ISL33001 ISL33002 ISL33003 buffer allows larger pull up resistor values to reduce sink currents when the bus is driving low However choose a pull up resistor value of no larger than 20kO regar
20. ins and a logic input to disable the rise time accelerator circuitry The ISL33003 features an EN pin and the level shifting functionality I C and SMBUS Compatibility The ISL33001 ISL33002 ISL33003 ICs are 12C and SMBUS compatible devices designed to work in open drain open collector bus environments The ICs support both clock stretching and bus arbitration on the SDA and SCL pins They are designed to operate from DC to more than 400kHz supporting Fast Mode data rates of the 2c specification In addition the buffer rise time accelerators are designed to increase the capacitive drive capability of the bus With careful choosing of components driving a bus with the 2c specified maximum bus capacitance of 400pF at 400kHz data rate is possible Start Up Sequencing and Hot Swap Circuitry The ISL33001 ISL33002 ISL33003 buffers contain undervoltage lock out UVLO circuitry that prevents operation of the buffer until the IC receives the proper supply voltage For Vcc4 and Veco this voltage is approximately 1 8V on the rising edge of the supply voltage Externally driven signals at the SDA SCL pins are ignored until the device supply voltage is above 1 8V This prevents communication errors on the bus until the device is properly powered up The UVLO circuitry is also triggered on the falling edge when the supply voltage drops below 1 7V Once the IC comes out of the UVLO state the buffer remains disconnected until it detects a valid co
21. k 5 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Test Circuits and Waveforms SDA_OUT and SCL pins connected to Vcc VsDA IN VsDA OUT VscL our VEN Vcc Enable Delay Time Measured on ISL33001 only EN Logic Input must be high for t gt Enable Delay tey LH ISL33003 performance inferred from ISL33001 prior to SCL IN transition E Bus Idle Time Measured on ISL33001 only If tDELAY1 lt teN LH then tDELAY2 tEN LH tipLE tREADY LH ISL33002 and ISL33003 performance inferred from ISL33001 If tpe Ay1 gt tEN LH then tpg Ay2 tgN LH tREADY LH VEN Vcc 05 Vcc P Vcc ov VspA_IN VREADY ov Vcc 0 5Vcc VREADY ov lt gt lt tpELAY1 t READY LH it p gt Y tDELAY2 tipLE FIGURE 3 ENABLE DELAY TIME FIGURE 4 BUS IDLE TIME 3 3V 10kO SCL_IN OR SDA_IN SDA_OUT SCL_OUT OR wf _ SDA_OUT Vos Vo 0 2V FIGURE 5A TEST CIRCUIT FIGURE 5B MEASUREMENT POINTS FIGURE 5 INPUT TO OUTPUT OFFSET VOLTAGE 2 7V 9000 Vec1 SDA_OUT V SCL OUT Vec1 VoL SDA OUT FIGURE 6A TEST CIRCUIT FIGURE 6B MEASUREMENT POINTS FIGURE 6 OUTPUT LOW VOLTAGE Submit Document Feedback 6 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Test Circuits and Waveforms continued 43 3V SF SCL_INOR SDA_IN SCL_OUT OR SDA_OUT lt lt tPLH tPHL Propagation delay measured between 50 of Vcc4 FIG
22. nnection state A valid connection state is either a BUS IDLE condition see Figure 4 ora STOP BIT condition a rising edge on SDA IN when SCL IN is high along with the SCL OUT and SDA OUT pins being logic high Note For the ISL33001 and ISL33003 with EN pins after coming out of UVLO there will be an additional delay from the enable circuitry if the EN pin voltage is not rising at the same time as the supply pins see Figure 3 before a valid connection state can be established Coming out of UVLO but prior to a valid connection state the SDA and SCL pins are pre charged to 1V to allow hot insertion Because the bus at any time can be between OV and Vcc pre charging the I O pins to 1V reduces the maximum differential voltage from the buffer I O pin and the active bus Submit Document Feedback 8 intersil I FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 The pre charge circuitry reduces system disturbance when the IC is hot plugged into a live back plane that may have the bus communicating with other devices Note For The ISL33001 and ISL33003 with EN pins the pre charge circuitry is active only after coming out of UVLO and having the device enabled Connection Circuitry Once a valid connection condition is met the buffer is active and the input stage of the SDA SCL pins is controlled by external drivers The output of the buffer will follow the input of the buffer The directionality of the IN OUT pins are no
23. ors Hot swapping capability 6kV Class 3 HBM ESD protection on all pins 12kV HBM ESD protection on SDA SCL pins Enable pin ISL33001 and ISL33003 Logic level translation ISL33002 and ISL33003 READY logic pin ISL33001 Accelerator disable pin ISL33002 Pb free RoHS Compliant 8 Ld SOIC ISL33001 only 8 Ld TDFN Smmx3mm and 8 Ld MSOP packages Low quiescent current 2 1mA typ Low shutdown current 0 5yA typ Applications e I2C bus extender and capacitance buffering Server racks for telecom datacom and computer servers Desktop computers Hot swap board insertion and bus isolation 100kHz I2C BUS WITH 2 7kQ PULL UP RESISTOR AND 400pF BUS CAPACITANCE WITHOUT BUFFER WITH BUFFER VOLTAGE 1V DIV TIME 2us DIV FIGURE 2 BUS ACCELERATOR PERFORMANCE July 11 2014 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures FN7560 6 1 888 INTERSIL or 1 888 468 3774 Copyright Intersil Americas LLC 2010 2014 All Rights Reserved Intersil and design is a trademark owned by Intersil Corporation or one of its subsidiaries All other trademarks mentioned are the property of their respective owners ISL33001 ISL33002 ISL33003 Ordering Information PART NUMBER PART TE
24. pulse width Figure 22 with the current source turning off as it approaches the supply voltage Enable Pin ISL33001 and ISL33003 When driven high the enable pin puts the buffer into its normal operating state After power up EN high will activate the bus pre charge circuitry and wait for a valid connection state to enable the buffer and the accelerator circuitry Driving the EN pin low disables the accelerators disables the buffer so that signals on one side of the buffer will be isolated from the other side disables the pre charge circuit and places the device in a low power shutdown state READY Logic Pin ISL33001 Only The READY pin is a digital output flag for signaling the status of the buffer The pin is the drain of an Open Drain NMOS Connect a resistor from the READY pin to Vcc4 to provide the high pull up The recommended value is 10kQ When the buffer is disabled by having the EN pin low or if the start up sequencing is not complete the READY pin will be pulled low by the NMOS When the buffer has the EN pin high and a valid connection state is made at the SDA SCL pins the READY pin will be pulled high by the pull up resistor The READY pin is capable of sinking 3mA when pulled low while maintaining a voltage of less than O 4V ACC Accelerator Pin ISL33002 Only The ACC logic pin controls the rise time accelerator circuitry of the buffer When ACC is driven high the accelerators are enabled and will be triggere
25. r Enable Pin Logic 0 disables the device Logic 1 enables the device Logic ISL33001 8 LD TDFN 8 LD SOIC MSOP threshold referenced to Vcc4 5 ISL33003 8 LD TDFN 8 LD MSOP READY 5 Buffer active Ready open drain logic output When buffer is active READY is high ISL33001 only impedance When buffer is inactive READY is low impedance to ground Connect to 10k pull up resistor to Vcc4 ACC 5 Rise Time Accelerator Enable Pin Logic O disables the accelerator Logic 1 ISL33002 only enables the accelerator Logic threshold referenced to Vcc4 SDA IN 6 Data I O Pins SDA_OUT 7 SCL_IN 3 Clock I O Pins SCL_OUT 2 PAD Thermal pad should be connected to ground or floated Thermal Pad TDFN only Submit Document Feedback 3 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Absolute Maximum Ratings Thermal Information All voltages referenced to GND Voti VGOGO esee naa ha aaa nile ire inxta eens 0 3V to 7V Thermal Resistance Oya C W 6c C W SDA_IN SCL_IN SDA_OUT SCL_OUT READY 0 3V to 7V 8 Ld TDFN Package Notes 5 6 47 4 EN ACC ci ioni dri dou 2a ae Sea dys aval a ace alana 0 3V to Vcc4 0 3 V 0 50mm Pitch Maximum Sink Current SDA and SCL Pins 20mA 8 Ld TDFN Package Notes 5 6 48 6 Maximum Sink Current READY pin 7mA 0 65mm Pitch Latch Up Tested per JESD78 Level 2 Class A
26. s to the metallized terminal and is measured between 0 15mm and 0 20mm from the terminal tip A Tiebar shown if present is a non functional feature The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature 7 Compliant to JEDEC MO 229 WEEC 2 except for the foot length Submit Document Feedback 16 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Package Outline Drawing M8 118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rey 4 7 11 3 0 0 05 M D 8 I 4 940 15 3 00 05 _ A N PIN 1 ID Uu 1 2 B i 0 65 BSC TOP VIEW 0 855010 0 855010 E S HAR 0 25 0 36 SIDE VIEW 1 5 80 4 40 3 00 FES 1 0 65 0 40 a LE TYPICAL RECOMMENDED LAND PATTERN DETAIL X f P um 1 10 MAX m N 7 Par SIDEVIEW 2 0 09 0 20 0 95 REF GAUGE I PLANE 0 25 s d l 7 o 0 55 0 15 MM DETAIL X NOTES 1 Dimensions are in millimeters 2 Dimensioning and toleran
27. t exclusive bi directional operation and functionally behave identical to each other Being a two channel buffer the SDA and SCL pins also behave identically In addition the SDA and SCL portions of the buffer are independent from each other The SDA pins can be driven in one direction while the SCL pins can be driven opposite Refer to Figure 10 for the operation of the bi directional buffer When the input stage of the buffer on one side is driven low by an external device the output of the buffer drives an open drain transistor to pull the output pin low The output pin will continue to be held low by the transistor until the external driver on the input releases the bus To prevent the buffer from entering a latched condition where both internal transistors are actively pulling the I O pins low the buffer is designed to be active in only one direction The buffer logic circuitry senses which input stage is being externally driven low and sets that buffer to be the active one For example referring to Figure 10 if SDA OUT is externally driven low buffer U2 will be active and buffer U1 is inactive M1 is turned on to drive SDA IN low effectively buffering the signal from SDA OUT to SDA IN The low signal at the input of U1 will not turn M2 on because U1 remains inactive preventing a latch condition Buffer Output Low and Offset Voltage By design when a logic input low voltage is forced on the input of the buffer th
28. the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature Submit Document Feedback 15 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Package Outline Drawing L8 3x3A 8 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE Rev 4 2 10 I 2 30 3 00 A m 1 95 Lacs I iB 8X 0 50 A s 1 50 PIN 1 290 INDEX AREA i 4x Z 0 15 i ede p TOP VIEW PIN 1 6x 0 65 L 8 X0 30 TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL X 2X 1 950 _ 7 0 10 C 6X 0 65 0 75 0 05 d c a ol PIN 1 1 j C 0 08 C INDEX AREA TU UU z SIDE VIEW A a 1 50 0 10 L f1 f C 8 C 0 2REF A 8X 0 30 0 10 IE A l L X m 0 10 M C AB 2 30 0 10 E Lo 02 NOM BOTTOM VIEW DETAIL X NOTES 1 Dimensions are in millimeters Dimensions in for Reference Only 2 Dimensioning and tolerancing conform to ASME Y14 5m 1994 3 Unless otherwise specified tolerance Decimal 0 05 Dimension applie
29. ubmit Document Feedback 4 intersil FN7560 6 July 11 2014 ISL33001 ISL33002 ISL33003 Electrical Specifications ven Vcca Vcci 2 3V to 5 5V Veco 2 3V to 5 5V unless otherwise noted Note 8 Boldface limits apply over the operating temperature range 40 C to 85 C Continued Delay Low to High pins Veca E 3 3V Vcc2 3 3V ISL33002 and ISL33003 Figure 7 TEMP MIN MAX PARAMETER SYMBOL CONDITIONS C Note 9 TYP Note 9 UNITS Ready Delay Off On tREADY LH ISL33001 only Note 10 25 10 ns Ready Output Low Voltage VoL READY Vcci 2 5V IPULLUP 3mA ISL33001 only Full 0 4 V RISE TIME ACCELERATORS Transient Accelerator HRAN ACC Voc 2 7V Vcc2 2 7V ACC 0 7 Vcc4 for 25 5 mA Current ISL33002 only Figure 8 Accelerator Pin Enable VACC EN ISL33002 only 25 0 5 Vcc4 0 7 Vcc4 V Threshold Accelerator Pin Disable Vacc pis 19L33002 only 25 O 3 Vcc4 0 5 Vcc4 E V Threshold Accelerator Pin Input lACC ISL33002 only 25 1 0 1 1 pA Current Accelerator Delay On Off tPDOFF ISL33002 only Note 10 25 10 ns ESD PROTECTION SDA SCL I O Pins Human Body Model SDA and SCL pins to ground 25 12 kV only JESD22 A114 All Pins Machine Model JESD22 A115 25 400 V Class 3 HBM ESD JESD22 A114 25 6 kV INPUT OUTPUT CONNECTIONS Input Low Threshold VIL Vcc4 Vec2 10kO to Vcc4 on SDA
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