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MOVE

1. MOVE to ACCext01 EMAC 0xAB 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 0 Source Effective Address Mode Register MOVE from ACCext01 EMAC OxAB8 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 0 0 Register Rx MOVE to MASK 0xAD 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 1 Source Effective Address Mode Register MOVE from MASK 0xAD8 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 1 0 Register Rx MOVE to ACCext23 EMAC OXAF 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 1 Source Effective Address Mode Register MOVE from ACCext23 EMAC OxAF8 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 1 0 Register Rx M MOTOROLA Chapter 9 Instruction Format Summary 9 13 Operation Code Map MOV3Q 0xA 15 14 13 12 11 10 9 7 4 3 2 1 0 1 0 1 0 Immediate Data 0 Destination Effective Address Mode Register CMP 0xB 15 14 13 12 11 10 9 7 4 3 2 1 0 1 0 1 1 Register Dx Opmode Source Effective Address Mode Register CMPA 0xB 15 14 13 12 11 10 9 7 4 3 2 1 0 1 0 1 1 Destination Opmode Source Eff
2. Instruction Fields e Vector field Specifies the trap vector to be taken M mororoLA Chapter 4 Integer User Instructions 4 81 TST Test an Operand TST All ColdFire Processors Operation Source Operand Tested CCR Assembler Syntax TST sz lt ea gt y Attributes Size byte word longword Description Compares the operand with zero and sets the condition codes according to the results of the test The size of the operation is specified as byte word or longword Not affected Set if the operand Is negative cleared otherwise Set if the operand was zero cleared otherwise Always cleared Always cleared Condition X N Z V C Codes men 0 0 O lt NZX Instruction 15 14 13 12 11 10 9 8 7 6 AAEE Instruction Fields 5 4 3 2 1 0 Destination Effective Address e Size field Specifies the size of the operation 00 byte operation 1 word operation 10 longword operation 11 word operation e Destination Effective Address field Specifies the addressing mode for the destination operand lt ea gt x as listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax 001 reg number Ax xxx L 111 001 Ax 010 reg number Ax lt data gt 111 100 Ax 011 reg number Ax Ax 100 reg number Ax d 6 AX 101 reg number A
3. MSAC with load MAC OXA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rw 1 Rw Source Effective Address Mode Register Register Rx sz Scale Factor U Lx U Ly Mask 0 Register Ry MSAC with load EMAC 0xA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rw ACC Rw Source Effective Address Isb Mode Register Register Rx sz Scale Factor U Lx U Ly Mask ACC Register Ry msb MOVE to ACC MAC OXA1 15 14 13 12 11 10 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 0 Source Effective Address Mode Register MOVE to ACC EMAC 0xA Source Effective Address MOVE from ACC EMAC OxA 8 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 0 ACC 1 0 0 0 Register Rx MOVCLR EMAC 0xA C 9 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aee sO ag a a EEN RE ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map MOVE from MACSR 0xA98 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 0 0 Register Rx MOVE to MACSR 0xA9 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 0 Source Effective Address Mode Register MOVE from MACSR to CCR OxA9CO 15 14 13 12 11 10 4 3 2 1 0 1 0 1 0 1 0 0 0 0 0 0
4. Instruction Operand Operand Size Operation Syntax Privileged FRESTORE lt ea gt y none FPU State Frame Internal FPU State FSAVE lt ea gt x none Internal FPU State FPU State Frame HALT none none Halt processor core synchronizes pipeline MOVE from SR SR Dx W SR Destination MOVE from USP USPDx L USP Destination MOVE to SR lt ea gt y SR W Source SR Dy or lt data gt source only synchronizes pipeline MOVE to USP Ay USP L Source USP MOVEC Ry Re L Ry Re synchronizes pipeline RTE none none 2 SP SR 4 SP PC SP 8 SP Adjust stack according to format synchronizes pipeline STOP lt data gt none Immediate Data SR STOP synchronizes pipeline WDEBUG lt ea gt y L Addressed Debug WOMREG Command Executed synchronizes pipeline Debug Functions PULSE none none Set PST 0x4 WDDATA lt ea gt y B W L Source DDATA port Trap Generating ILLEGAL none none SP 4 SP PC SP PC SP 2 SP SR SP SP 2 SP Vector Offset SP VBR 0x10 PC TRAP lt vector gt none 1 S Bit of SR SP 4 SP nextPC SP SP 2 gt SP SR gt SP SP 2 SP Format Offset SP VBR 0x80 4 n PC where n is the TRAP number 1 Supported starting with V4 on devices containing an MMU 3 1 8 Cache Maintenance Instructions The cache instructions provide maintenance functions for managin
5. 4 36 ColdFire Family Programmer s Reference Manual M MOTOROLA JMP JMP Jump All ColdFire Processors Operation Destination Address PC Assembler Syntax JMP lt ea gt y Attributes Unsized Description Program execution continues at the effective address specified by the instruction Condition Codes Instruction 5 14 Not affected 4 3 2 1 Format 0 1 Source Effective Address Mode Register Instruction Field e Source Effective Address field Specifies the address of the next instruction lt ea gt y use the control addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt Ay Ay d1 Ay 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 M MOTOROLA Chapter 4 Integer User Instructions 4 37 JSR JSR Jump to Subroutine All ColdFire Processors Operation SP 4 SP nextPC SP Destination Address PC Assembler Syntax JSR lt ea gt y Attributes Unsized Description Pushes the longword address of the instruction immediately following the JSR instruction onto the system stack Program execution then continues at the address specifi
6. O lt NZX Normally CCR Z is set explicitly via programming before the start of an SUBX operation to allow successful testing for zero results upon completion of multiple precision operations Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 Olt Oe Register Dx 1 1 0 lo 0 0 Register Dy Instruction Fields e Register Dx field Specifies the destination data register Dx e Register Dy field Specifies the source data register Dy M mororoLA Chapter 4 Integer User Instructions 4 77 SWAP Swap Register Halves SWAP All ColdFire Processors Operation Register 3 1 16 gt Register 15 0 Assembler Syntax SWAP W Dx Attributes Size Word Description Exchange the 16 bit words halves of a data register Condition X N Z V C X Not affected Codes 0 0 N Set if the msb of the result is set cleared otherwise ones Z Setif the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 0 0 0 0 1 0 0 0 Register Dx Instruction Fields e Register field Specifies the destination data register Dx 4 78 ColdFire Family Programmer s Reference Manual M MOTOROLA TAS Test and Set an Operand TAS Supported starting with V4 Operation Destination Tested CCR 1 bit 7 of Destination
7. Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 MVZ V2 V3 Core V4 Core Opcode present No Yes Operand sizes supported B W M mororoLA Chapter 4 Integer User Instructions 4 57 N EG Negate N EG All ColdFire Processors Operation 0 Destination Destination Assembler Syntax NEG L Dx Attributes Size longword Description Subtracts the destination operand from zero and stores the result in the destination location The size of the operation is specified as a longword Condition X N Z V C X Setthe same as the carry bit Codes x x N Set if the result is negative cleared otherwise s Z Set if the result is zero cleared otherwise V Set if an overflow is generated cleared otherwise C Cleared if the result is zero set otherwise EN wo Instruction 15 14 13 12 11 10 9 8 7 6 5 2 1 0 Format 0 1 0 0 0 1 0 0 1 0 0 0 0 Register Dx Instruction Fields e Register field Specifies data register Dx 4 58 ColdFire Family Programmer s Reference Manual M MOTOROLA N EGX Negate with Extend N EGX All ColdFire Processors
8. Instruction na Operand Size Operation yntax ASL Dy Dx L CCR X C Dx lt lt Dy 0 lt data gt Dx L CCR X C Dx lt lt lt data gt 0 ASR Dy Dx L msb Dx gt gt Dy CCRIX C lt data gt Dx L msb Dx gt gt lt data gt CCR X C LSL Dy Dx L CCR X C Dx lt lt Dy 0 lt data gt Dx L CCR X C Dx lt lt lt data gt 0 LSR Dy Dx L 0 Dx gt gt Dy gt CCR X C lt data gt Dx L 0 Dx gt gt lt data gt CCR X C SWAP Dx W MSW of Dx amp LSW of Dx 3 1 5 Bit Manipulation Instructions BTST BSET BCLR and BCHG are bit manipulation instructions All bit manipulation operations can be performed on either registers or memory The bit number is specified either as immediate data or in the contents of a data register Register operands are 32 bits long and memory operands are 8 bits long Table 3 6 summarizes bit manipulation operations Table 3 6 Bit Manipulation Operation Format Instruction Operand Syntax Operand Size Operation BCHG Dy lt ea gt x B L lt bit number gt of Destination CCR Z lt data gt lt ea gt x B L lt bit number gt of Destination BCLR Dy lt ea gt x B L lt bit number gt of Destination CCRIZ lt data gt lt ea gt x B L 0 lt bit number gt of Destination BSET Dy lt ea gt x B L lt bit number gt of Destination CCRIZ lt data gt lt ea gt x B L
9. 1 Only if format is byte word longword or single precision If R M 0 this field is unused and should be all zeros R M field Specifies the source operand address mode 1 The operation is lt ea gt y to register 0 The operation is register to register Source specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy Destination register field Specifies the destination floating point register FPx If R M 0 and the source and destination fields are equal the input operand is taken from the specified floating point data register and the result is written into the same register If the single register syntax is used Motorola assemblers set the source and destination fields to the same value M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 19 Instruction Descriptions FINTRZ Floating Point Integer Round to Zero FINTRZ Operation Integer Part of Source FPx Assembler Syntax FINTRZ fmt lt ea gt y FPx FINTRZ D FPy FPx FINTRZ D FPx Attributes Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and extracts the integer part and converts it to a double precision number Stores the result in the destination floating point data register The int
10. Instruction Fields e Register Dx field Specifies the destination data register Dx e Register Dy field Specifies the source data register Dy M mororoLA Chapter 4 Integer User Instructions 4 7 AND AND Logical AND All ColdFire Processors Operation Source amp Destination Destination Assembler Syntax AND L lt ea gt y Dx AND L Dy lt ea gt x Attributes Size longword Description Performs an AND operation of the source operand with the destination operand and stores the result in the destination location The size of the operation is specified as a longword Address register contents may not be used as an operand The Dx mode is used when the destination is a data register the destination lt ea gt mode is invalid for a data register ANDI is used when the source is immediate data Condition X N Z V C X Not affected Codes 0 0 N Set if the msb of the result is set cleared otherwise odes Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 43 12 u 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 0 0 Data Register Opmode Effective Address Mode Register Instruction Fields e Register field Specifies any of the 8 data registers e Opmode field Byte Word Longword Operation 010 lt ea gt y amp Dx Dx 110 Dy amp lt ea gt x gt lt ea gt x 4 8 ColdFire
11. PAV3 PAV2 PAV1 PAVO OMC S U F I R T N Z V EV Source lt ea gt bit 11 10 9 8 7 6 5 4 3 2 1 0 Instruction 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 Format 1 0 1 0 1 0 0 1 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay lt data gt 111 100 Ay Ay di6 Ay di6 PC dg Ay Xi dg PC Xi M MOTOROLA Chapter 6 EMAC User Instructions MOVE to MASK MOVE to MASK Move to the MAC MASK Register Operation Source MASK Assembler Syntax MOVE L Ry MASK MOVE L lt data gt MASK Attributes Size longword Description Moves a 16 bit value from the lower word of a register or an immediate operand into the MASK register MACSR Not affected Instruction Format 15 14 13 12 4 3 2 1 1 0 1 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the fo
12. Table 1 8 describes MMU base address register fields Table 1 8 MMU Base Address Register Field Descriptions Bits Name Description 31 16 BA Base address Defines the base address for the 64 Kbyte address space mapped to the MMU 15 1 Reserved should be cleared 0 V Valid 1 5 8 RAM Base Address Registers RAMBARO RAMBAR1 RAMBAR registers determine the base address of the internal SRAM modules and indicate the types of references mapped to each Each RAMBAR includes a base address write protect bit address space mask bits and an enable bit RAM base address alignment is implementation specific A specific ColdFire processor may implement 2 1 or 0 RAMBARs Bit functions and positions can vary among ColdFire processor implementations Refer to a specific device or core user s manual for further information 1 5 9 ROM Base Address Registers ROMBAR0O ROMBAR1 ROMBAR registers determine the base address of the internal ROM modules and indicate the types of references mapped to each Each ROMBAR includes a base address write protect bit address space mask bits and an enable bit ROM base address alignment is implementation specific A specific ColdFire processor may implement 2 1 or 0 ROMBARs Bit functions and positions can vary among ColdFire processor implementations Refer to a specific device or core user s manual for further information 1 5 10 Module Base Address Register
13. e Register Dw field Specifies the remainder register Dw M mororoLA Chapter 4 Integer User Instructions 4 67 REMU REMU Unsigned Divide Remainder All ColdFire Processors Starting with MCF5206e Operation Destination Source Remainder Assembler Syntax REMU L lt ea gt y Dw Dx 32 bit Dx 32 bit lt ea gt y 32r in Dw where r indicates the remainder Attributes Size longword Description Divide the unsigned destination operand by the unsigned source and store the unsigned remainder in another register If Dw is specified to be the same register as Dx the DIVU instruction is executed rather than REMU To determine the quotient use DIVU An attempt to divide by zero results in a divide by zero exception and no registers are affected The resulting exception stack frame points to the offending REMU opcode If overflow is detected the destination register is unaffected An overflow occurs if the quotient is larger than a 32 bit signed integer Condition X N Z V C X Not affected Codes 0 N Cleared if overflow is detected otherwise set if the quotient is negative cleared if positive Z Cleared if overflow is detected otherwise set if the quotient is zero cleared if nonzero V Set if an overflow occurs cleared otherwise C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 0 0 Source Effective Address Mode Register 0 Register
14. FPCC m Exception Status Byte EXC 1 AEXC Byte _ 31 28 27 26 25 24 23 16 15 14 13 12 11 10 9 8 7 6 5 4 3 20 N Z 1 NAN BSUN INAN OPERR OVFL UNFL DZ INEX IDE IOP OVFL UNFL DZ INEX Figure 7 1 Floating Point Status Register FPSR Table 7 1 describes FPSR fields Table 7 1 FPSR Field Descriptions Bits Field Description 31 24 FPCC Floating point condition code byte Contains four condition code bits that are set after completion of all arithmetic instructions involving the floating point data registers The floating point store operation FMOVEM and move system control register instructions do not affect the FPCC 31 28 Reserved should be cleared 27 N Negative 26 Z Zero 25 l Infinity 24 NAN Not a number 23 16 Reserved should be cleared M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 1 Floating Point Status Register FPSR Table 7 1 FPSR Field Descriptions Continued Bits Field Description 15 8 EXC Exception status byte Contains a bit for each floating point exception that might have occurred during the most recent arithmetic instruction or move operation 15 BSUN Branch set on unordered 14 INAN Input not a number 13 OPERR Operand error 12 OVFL Overflow 11 UNFL Underflow 10 DZ D
15. M mororoLA Chapter 4 Integer User Instructions 4 41 LSL LSR Logical Shift LSL LSR x lt Set according to the last bit shifted out of the operand unaffected for a shift count of zero Set if result is negative cleared otherwise Set if the result is zero cleared otherwise Always cleared Set according to the last bit shifted out of the operand cleared for a shift count of zero Condition X N Z V C Codes d t 0 s O lt NZ Instruction 15 14 43 12 11 10 9 8 7 6 5 4 3 2 4 0 Format 1 1 1 0 Count or dr 1 0 i r 0 1 Register Dx Register Dy Instruction Fields e Count Register field If i r 0 this field contains the shift count values 1 7 represent shifts of 1 7 value of 0 specifies shift count of 8 Ifi r 1 data register Dy specified in this field contains shift count modulo 64 e dr field Specifies the direction of the shift 0 shift right shift left e i r field 0 immediate shift count register shift count e Register field Specifies a data register Dx to be shifted 4 42 ColdFire Family Programmer s Reference Manual M MOTOROLA MOV3Q Move 3 Bit Data Quick MOV3Q Supported starting with V4 Operation 3 bit Immediate Data gt Destination Assembler Syntax MOV3Q L lt data gt lt ea gt x Attributes Size longword Description Move the immediate data to the operand at the destination location The data range is from 1 to 7 ex
16. Opmode Instruction Rounding Precision 0000100 FSQRT Rounding precision specified by the FPCR 1000001 FSSQRT Single precision rounding 1000101 FDSQRT Double precision rounding M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 39 Instruction Descriptions FS U B Floating Point Subtract FS U B Operation FPx Source FPx Assembler syntax FSUB fmt lt ea gt y FPx FSUB D FPy FPx FrSUB fmt lt ea gt y FPx FrSUB D FPy FPx where r is rounding precision S or D Attributes Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and subtracts it from the number in the destination floating point data register Stores the result in the destination floating point data register i 1 Operation ee Source Destination Table In Range Zero Infinity In Range g Subtract Subtract inf inf Zero 0 0 0 0 Subtract inf inf l 0 0 0 02 y Infinity inf inf NANS inf 4 inf inf inf NANS 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number 2 Returns 0 0 in rounding modes RN RZ and RP returns 0 0 in RM 3 Sets the OPERR bit in the FPSR exception byte FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 et if source and destination
17. dg PC Xi 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros e R M field Specifies the source operand address mode The operation is lt ea gt y to register The operation is register to register e Source Specifier field Specifies the source register or data format If R M 1 specifies the source data format Table 7 6 shows source data format encoding If R M 0 specifies the source floating point data register FPy e Destination Register field Specifies the destination floating point data register FPx e Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0011000 FABS Rounding precision specified by FPCR 1011000 FSABS Single precision rounding 1011100 FDABS Double precision rounding 7 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FADD FADD Floating Point Add Operation Source FPx FPx Assembler Syntax FADD fmt lt ea gt y FPx FADD D FPy FPx FrADD fmt lt ea gt y FPx FrADD D FPy FPx where r is rounding precision S or D Attributes Description Converts the source operand to double precision if necessary and adds that number to the number in the destination floating point data register Stores the result in the destination floating point data
18. xxx L _ Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC dg Ay Xi dg PC Xi e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 e sz field Specifies the size of the input operands 0 word longword e Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1 10 reserved 11 product gt gt 1 e U Lx U Ly Specifies which 16 bit operand of the source register Rx Ry is used for a word sized operation 0 lower word 1 upper word e Mask field Specifies whether or not to use the MASK register in generating the source effective address lt ea gt y 0 do not use MASK use MASK e Register Ry field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 M MOTOROLA Chapter 6 EMAC User Instructions 6 5 MOVCLR MOVCLR Movefrom Accumulator and Clear Operation Accumulator Destination 0 Accumulator Assembler syntax MOVCLR L ACCy Rx Attributes Size longword Description Moves a 32 bit accumulator value into a general purpose register Rx The selected accumulator is cleared after the store to the Rx register is complete This clearing operation also
19. cee ceeeeeseeeeeeeeeeeeees 2 5 Address Register Indirect with Scaled Index and 8 Bit Displacement Mode 2 6 Program Counter Indirect with Displacement Mode eeeeseeeseceeeeeees 2 6 Program Counter Indirect with Scaled Index and 8 Bit Displacement Mode 2 7 Absolute Short Addressing Mode 2 8 Absolute Long Addressing Mode nanvennsevennenseenensenneevenreeseenencenneen 2 9 Emerald tn ent ne Saved nnn 2 9 Effective Addressing Mode Summary 2 10 SAGE Rss nn ER E nn a NN 2 2 10 Chapter 3 Instruction Set Summary Instr cti n Summary LL es Re re ne A an en ct es ns s 3 1 Data Movement Instuctions szis nine riatilantes 3 4 Integer Arithmetic Instructions nrs 3 5 E gical STUNT nt en et nr tante RER 3 7 SOLS CHOSE LR RS etant et 3 7 Bit Manipulation Instructions ss hante lentenetietses 3 8 Program Control Instructions shine nanustenienandehenestteliansse 3 8 System Control ANS MUCTIONS ze Sansen den erdee an arden bele tree 3 10 ColdFire Family Programmer s Reference Manual M MOTOROLA CONTENTS Paragraph Page Number Me Number 3 1 8 Cache Maintenance Instructions ssspccascacvcchsaiorcdarasavadeicisncdantarecabiel res 3 10 3 1 9 Floating Point Arithmetic Instructions eseseseseseeseseseeressereresrersersresreeseeee 3 11 32 Instruction Set AGG GMS Ent RAT en AR Re nn 3 12 Chapter 4 Integer User Instructions Chapter 5 Multiply Accumulate Unit MAC User Instructions Chapter 6 Enhanced Mu
20. Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi 4 44 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE Move Data from Source to Destination MOVE Instruction fields continued e Source Effective Address field Specifies source operand lt ea gt y the table below lists possible addressing modes The restrictions on combinations of source and destination addressing modes are listed in the table at the bottom of the next page Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 NOTE Not all combinations of source destination addressing modes are possible The table below shows the possible combinations Starting with V4 the combination of lt xxx gt d Ax can be used with MOVE B and MOVE W opcodes Source Addressing Mode Destination Addressing Mode Dy Ay Ay Ay Ay All possible dig Ay d16 PC All possible except dg Ax Xi xxx W xxx L d8 Ay Xi d8 PC Xi xxx W xxx L lt xxx gt All
21. ss 3 20 7 1 FPSR Field DESCAPUONS SR neue nues eene 7 1 7 2 FPSR EXC BUS Rs ne eee en te en E nr 7 3 7 3 BPCC PMC OCI GS eene ns nn dde t nt E ES nn tgene 7 4 M mororoLA Tables xi TABLES Table F Page Number Tile Number 1 4 Floating Point Conditional TEsts ssssntnideeendin ne 7 5 7 5 FPCR EXC Byte Exception Enabled Disabled Results 7 6 7 6 Data Format Encoding us snsssitansiinunantninsdnnnneniinbetesentl 7 8 8 1 State Frames ES een ne ent ne nt eal a aie tt ne 8 3 8 2 State Frames eee EEE 8 5 8 3 ColdFire CPU Space AsSlBRMENES Sid nn a deed 8 14 9 1 Operation Code Maps men a ne RE CS 9 1 10 1 PST DDATA Specification for User Mode Instructions nennen 10 2 10 2 PST DDATA Values for User Mode Multiply Accumulate Instructions 10 5 10 3 PST DDATA Values for User Mode Floating Point Instructions 10 6 10 4 Data Markers and FPU Operand Format Specifier ennen eene enne enneennenn 10 7 10 5 PST DDATA Specifications for Supervisor Mode Instructions eee eeeeeeeeeeee 10 7 11 1 Exception Vectot ASSISES nt be LR RSR ce ES ne A 11 2 11 2 Format Vecto WOrd sentent Le cata Anne ten ee dunes ta 11 5 11 3 Exceptions sua ina mer admin nds 11 6 11 4 Exception Priorities est benenden abe dele a e heeele enbrel ien 11 9 11 5 BSUN Exception Enabled Disabled Results nonnen eeenseevenne eenen 11 11 11 6 INAN Exception Enabled Disabled Results 11 11 11 7 IDE Exception Enabled Disabled Results 4 11 12 11
22. The store accumulator function is quite complex and a function of the EMAC configuration defined by the MACSR The following pseudocode defines its operation in this description ACC 47 0 represents the concatenation of the 32 bit accumulator and the 16 bit extension word if MACSR S U F I 00 signed integer mod if MACSR OMC then ACC 31 0 Rx saturation disabled else if ACC 47 31 0x0000_0 or OxFFFF 1 then ACC 31 0 Rx else if ACC 47 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx if MACSR S U F I 10 unsigned integer mod if MACSR OMC then ACC 31 0 Rx saturation disabled else if ACC 47 32 0x0000 then ACC 31 0 Rx else OxFFFF_FFFF Rx if MACSR F I signed fractional mode if MACSR OMC S U R T 000 no saturation no 16 bit rnd no 32 bit rnd then ACC 39 8 Rx if MACSR OMC S U R T 001 no saturation no 16 bit rnd 32 bit rnd then ACC 39 8 rounded by contents of 7 0 Rx if MACSR OMC S U 01 no saturation 16 bit rounding then 0 Rx 31 16 ACC 39 24 rounded by contents of 23 0 Rx 15 0 if MACSR OMC S U R T 100 saturation no 16 bit rnd no 32 bit rnd if ACC 47 39 0x00_0 or OxFF_1 then ACC 39 8 Rx else if ACC 47 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx if MACSR OMC S U R T 101 saturation no 16 bit rnd 32 bit rounding Temp 47 8 ACC 47 8 rounded by contents of
23. msb Mode Register Register Rx SZ Scale Factor U Lx U Ly Mask ACC msb Register Ry Instruction Fields e Register Rw 6 11 9 field Specifies the destination register Rw where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e ACC field Specifies the destination accumulator ACCx Bit 4 of the extension word is the msb and bit 7 of the operation word is the inverse of the Isb unlike the MSAC without load The value of these two bits specify the accumulator number as shown in the following table Ext word 4 Op word 7 Accumulator 0 1 ACCO 0 0 ACC1 1 1 ACC2 1 0 ACC3 M MOTOROLA 6 23 Chapter 6 EMAC User Instructions MSAC Multiply Subtract with Load Instruction Fields continued MSAC Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table 6 24 Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W Ay xxx L _ Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC dg Ay Xi dg PC Xi Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7
24. 15 14 O lt NZX Set the same as the carry bit Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Set if an overflow is generated cleared otherwise Set if an carry is generated cleared otherwise 4 3 2 1 0 4 1 Register Opmode Effective Address Mode Register Instruction Fields e Register field Specifies the data register e Opmode field 4 2 Byte Longword Operation 010 110 lt ea gt y Dx Dx Dy lt ea gt x gt lt ea gt x ColdFire Family Programmer s Reference Manual M MOTOROLA ADD Add ADD Instruction Fields continued e Effective Address field Determines addressing mode For the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 Ay 101 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 For the destination operand lt ea gt x use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx xxx W 111 000
25. Ay 100 reg number Ay d1 Ay 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 4 ColdFire Family Programmer s Reference Manual M MOTOROLA ADDI Add Immediate ADDI All ColdFire Processors Operation Immediate Data Destination Destination Assembler Syntax ADDI L lt data gt Dx Attributes Size longword Description Operates similarly to ADD but is used when the source operand is immediate data Adds the immediate data to the destination operand and stores the result in the destination data register Dx The size of the operation is specified as longword The size of the immediate data is specified as a longword Note that the immediate data is contained in the two extension words with the first extension word bits 15 0 containing the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z V C X Set the same as the carry bit Codes N Setif the result is negative cleared otherwise 4 Z Set if the result is zero cleared otherwise V Set if an overflow is generated cleared otherwise C Set if an carry is generated cleared otherwise Instruction 15 14 43 12 u 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 0 1 1 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Destination Register field
26. Destination ISA_A 3 12 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Set Additions Table 3 14 ColdFire User Instruction Set Summary Continued Instruction Operand Syntax nen Operation ISA ASL Dy Dx L CCR X C Dx lt lt Dy 0 ISA_A lt data gt Dx L CCRIX C Dx lt lt lt data gt 0 ASR Dy Dx L msb Dx gt gt Dy CCR X C ISA_A lt data gt Dx L msb Dx gt gt lt data gt CCR X C Bee lt label gt B W L If Condition True Then PC dp gt PC ISA_A BCHG Dy lt ea gt x B L lt bit number gt of Destination CCR Z gt ISA_A lt data gt lt ea gt x B L lt bit number gt of Destination BCLR Dy lt ea gt x B L lt bit number gt of Destination CCR Z ISA_A lt data gt lt ea gt x B L 0 lt bit number gt of Destination BRA lt label gt B W L PC d PC ISA_A BSET Dy lt ea gt x B L lt bit number gt of Destination CCRIZ ISA_A lt data gt lt ea gt x B L 1 lt bit number gt of Destination BSR lt label gt B W L SP 4 gt SP nextPC SP PC dn PC ISA_A BTST Dy lt ea gt x B L lt bit number gt of Destination CCR Z ISA_A lt data gt lt ea gt x B L CLR lt ea gt X B W L 0 Destination ISA_A CMP lt ea gt y Dx B W L Destination Source CCR ISA_A CMPA lt ea gt y Ax W L3 CMPI lt data gt Dx
27. ACCext01 Extensions for ACCO and ACC1 ACCext23 Extensions for ACC2 and ACC3 MASK MAC mask register Figure 1 8 EMAC Programming Model 1 4 1 MAC Status Register MACSR Figure 1 9 shows the EMAC MACSR which contains an operational mode field and two sets of flags 1 8 ColdFire Family Programmer s Reference Manual M MOTOROLA 31 EMAC User Programming Model 12 11 10 9 8 7 6 5 4 3 2 1 Prod acc overflow flags Operational Mode Flags PAV3 PAV2 PAV1 PAVO OMC S U F I R T N Z V Figure 1 9 MAC Status Register MACSR Table 1 5 describes EMAC MACSR fields Table 1 5 MACSR Field Descriptions Bits Field Description 31 12 Reserved should be cleared 11 8 PAVx Product accumulation overflow flags one per accumulator 7 4 OMF Operational mode field Defines the operating configuration of the EMAC unit 7 OMC Overflow saturation mode 6 S U Signed unsigned operations 5 F I Fraction integer mode 4 R T Round truncate mode 3 0 Flags Flags Contains indicator flags from the last MAC instruction execution 3 N Negative 2 Z Zero 1 V Overflow 0 C Carry This field is always zero 1 4 2 MAC Accumulators ACC 0 3 The EMAC implements four 48 bit accumulators The 32 bit ACCx registers along with the accumulator extension words contain the accumulator data Figure 1 10 shows the data contai
28. Bit number is specified in a second word of the instruction 2 Register Specified data register contains the bit number Condition X N Z V C X Not affected Codes N Not affected Z Set if the bit tested is zero cleared otherwise V Not affected C Not affected Bit Number Static Specified as Immediate Data Instruction 15 14 13 12 ii 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 1 0 0 0 1 0 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number M mororoLA Chapter 4 Integer User Instructions 4 17 BCLR BCLR Test a Bit and Clear Instruction Fields e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W _ Ax xxx L Ax 010 reg number Ax lt data gt En Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi dg PC Xi e Bit Number field Specifies the bit number Bit Number Dynamic Specified in a Register Instruction 15 14 43 12 11 10 9 8 7 6 5 44 3 2 1 0 Format 0 0 0 0 Data Register Dy 1 1 0
29. FNEG rounds the result to the precision selected in the FPCR FSNEG and FDNEG round the result to single or double precision respectively regardless of the rounding precision selected in the FPCR Operation ne Source Destination Table In Range Zero Infinity Result Negate 0 0 0 0 inf inf 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 0 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 5 14 13 12 11 10 9 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM 0 Source Specifier Destination Opmode Register FPx M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 35 Instruction Descriptions FN EG Floating Point Negate FN EG Instruction fields Effective Address field Determines the addressing mode for external operands If R M 1 this field specifies the location of the source operand Only modes in the following table can be used 7 7 36 Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg
30. Instruction Descriptions FBcc Floating Point Branch Conditionally FBcc Operation If Condition True Then PC d PC Assembler Syntax FBcc fmt lt label gt Attributes Format word longword Description If the specified condition is met execution continues at PC displacement a 2 s complement integer that counts relative distance in bytes The PC value determining the destination is the branch address plus 2 For word displacement a 16 bit value is stored in the word after the instruction operation word For longword displacement a 32 bit value is stored in the longword after the instruction operation word The specifier cc selects a test described in Section 7 2 Conditional Testing FPSR FPCC Not affected FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC Set if the NAN bit is set and the Not affected condition selected is an IEEE nonaware test FPSR IOP OVFL UNFL DZ INEX AEXC Setif EXC BSUN is set Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 1 Size Conditional Predicate 16 Bit Displacement or Most Significant Word of 32 bit Displacement Least Significant Word of 32 bit Displacement if needed Instruction fields e Size field Specifies the size of the signed displacement If size 1 displacement is 32 bits If size 0 displaceme
31. MOVE MACSR MOVE MACSR to CCR Move from the to CCR MACSR to the CCR Operation MACSR CCR Assembler Syntax MOVE L MACSR CCR Attributes Size longword Description Moves the MACSR condition codes into the Condition Code Register The opcode for MOVE MACSR to CCR is OxA9CO MACSR Not affected Condition X N Z V C X Always cleared Codes 0 N Set if MACSRIN 1 cleared otherwise odes Z Set if MACSR Z 1 cleared otherwise V Set if MACSR V 1 cleared otherwise C Set if MACSR EV 1 cleared otherwise Instruction 15 14 13 12 11 10 9 8 7 6 5 44 3 2 1 0 Format 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 M mororoLA Chapter 6 EMAC User Instructions 6 15 MOVE MOVE to ACC Moveto to ACC Accumulator Operation Source Accumulator Assembler syntax MOVE L Ry ACCx MOVE L lt data gt ACCx Attributes Size longword Description Moves a 32 bit value from a register or an immediate operand into an accumulator If the EMAC is operating in signed integer mode MACSR 6 5 00 the 16 bit accumulator extension is loaded with the sign extension of bit 31 of the source operand while operation in unsigned integer mode MACSR 6 5 10 clears the entire 16 bit field If operating in fractional mode MACSR 5 1 the upper 8 bits of the accumulator extension are loaded with the sign extension of bit 31 of the source operand while the low order 8 bits of the extension are cleared The appropriate product
32. Operation 0 Destination CCR X Destination Assembler Syntax NEGX L Dx Attributes Size longword Description Subtracts the destination operand and CCR X from zero Stores the result in the destination location The size of the operation is specified as a longword Set the same as the carry bit Set if the result is negative cleared otherwise Cleared if the result is nonzero unchanged otherwise Set if an overflow is generated cleared otherwise Set if a borrow occurs cleared otherwise Condition X N Z V C Codes 5 i 5 O lt NZX Normally CCR Z is set explicitly via programming before the start of an NEGX operation to allow successful testing for zero results upon completion of multiple precision operations Instruction i5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 0 0 0 0 1 0 0 0 0 Register Dx Instruction Fields e Register field Specifies data register Dx M mororoLA Chapter 4 Integer User Instructions 4 59 NO P No Operation NO P All ColdFire Processors Operation None Assembler Syntax NOP Attributes Unsized Description Performs no operation The processor state other than the program counter is unaffected Execution continues with the instruction following the NOP instruction The NOP instruction does not begin execution until all pending bus cycles have completed synchronizing the pipeline and preven
33. Register Instruction Fields e Data field 3 bits of immediate data representing 8 values 0 7 with the immediate values 1 7 representing values of 1 7 respectively and 0 representing a value of 8 e Destination Effective Address field specifies the destination location use only those alterable addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax 001 reg number Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi 110 reg number Ax dg PC Xi 4 76 ColdFire Family Programmer s Reference Manual M MOTOROLA S U BX Subtract Extended S U BX All ColdFire Processors Operation Destination Source CCR X Destination Assembler Syntax SUBX L Dy Dx Attributes Size longword Description Subtracts the source operand and CCR X from the destination operand and stores the result in the destination location The size of the operation is specified as a longword Set the same as the carry bit Set if the result is negative cleared otherwise Cleared if the result is non zero unchanged otherwise Set if an overflow is generated cleared otherwise Set if an carry is generated cleared otherwise Condition X N Z V C Codes i d
34. Specifies the destination data register Dx M mororoLA Chapter 4 Integer User Instructions 4 5 ADDQ ADDQ Add Quick All ColdFire Processors Operation Immediate Data Destination Destination Assembler Syntax ADDQ L lt data gt lt ea gt x Attributes Size longword Description Operates similarly to ADD but is used when the source operand is immediate data ranging in value from 1 to 8 Adds the immediate value to the operand at the destination location The size of the operation is specified as longword The immediate data is zero filled to a longword before being added to the destination When adding to address registers the condition codes are not altered Condition X N Z V C X Set the same as the carry bit Codes N Set if the result is negative cleared otherwise odes Z Set if the result is zero cleared otherwise V Set if an overflow is generated cleared otherwise C Set if an carry is generated cleared otherwise Instruction 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Format 0 1 0 1 Data 0 1 0 Destination Effective Address Mode Register Instruction Fields e Data field 3 bits of immediate data representing 8 values 0 7 with 1 7 representing values of 1 7 respectively and 0 representing a value of 8 e Destination Effective Address field Specifies the destination location lt ea gt x use only those alterable addressing mo
35. 0 0 0 0 200 0 0 0 0 0 0 NAN Infinity inf inf 2 inf inf _ inf inf NAN inf inf 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number 2 Sets the OPERR bit in the FPSR exception byte FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 Set for 0 x es cleared See Table 7 2 0 See otherwise Table 7 2 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Register FPx Opmiade M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 33 Instruction Descriptions FMUL Floating Point Multiply FMUL Instruction fields e Effective address field Determines the addressing mode for external operands If R M 1 this field specifies the location of the source operand Only the addressing modes listed in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay di6 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi
36. 1 0 1 0 Register Rx 0 Rx 0 0 Register Ry EE E sz Scale Factor U Lx U Ly _ MAC EMAC OXA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rx ACC Rx 0 0 Register Ry Isb msb sz Scale Factor U Lx U Ly ACC msb MAC with load MAC 0xA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rw 1 Rw Source Effective Address Mode Register Register Rx sz Scale Factor U Lx U Ly Mask 0 Register Ry MAC with load EMAC 0xA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rw ACC Rw Source Effective Address Isb Mode Register Register Rx sz Scale Factor U Lx U Ly Mask ACC Register Ry msb MSAC MAC 0xA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rx 0 Rx 0 0 Register Ry sz Scale Factor U Lx U Ly MSAC EMAC 0xA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 0 1 0 Register Rx ACC Rx 0 0 Register Ry Isb msb sz Scale Factor U Lx U Ly ACC msb M MOTOROLA Chapter 9 Instruction Format Summary 9 11 Operation Code Map
37. 1 upper word ColdFire Family Programmer s Reference Manual M MOTOROLA MSAC MSAC Multiply Subtract with Load Operation ACCx Ry Rx lt lt gt gt SF ACCx lt ea gt y Rw Assembler syntax MAC sz Ry U L Rx U L SE lt ea gt y amp Rw ACCx where amp enables the use of the MASK Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 40 bit result then subtract this product shifted as defined by the scale factor from an accumulator If 16 bit operands are used the upper or lower word of each register must be specified In parallel with this operation a 32 bit operand is fetched from the memory location defined by lt ea gt y and loaded into the destination register Rw If the MASK register is specified to be used the lt ea gt y operand is ANDed with MASK prior to being used by the instruction Condition N Z V PAVx EV N Set if the msb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if a product or accumulation overflow is MACSR generated or PAVx 1 cleared otherwise PAVx Set if a product or accumulation overflow is generated unchanged otherwise EV Set if accumulation overflows lower 32 bits integer or lower 40 bits fractional cleared otherwise Instruction 12 11 Format 1 0 1 0 15 14 10 9 N D a 4 3 2 1 0 Register Rw 0 Rw Source Effective Address
38. 2datas Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay d4g PC 111 010 dg Ay Xi dg PC Xi 7 30 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FMOVEM Move Multiple Floating Point FMOVEM Data Registers Operation Register List Destination Source Register List Assembler syntax FMOVEM D list lt ea gt x FMOVEM D lt ea gt y list Attributes Format double precision Description Moves one or more double precision numbers to or from a list of floating point data registers No conversion or rounding is performed during this operation and the FPSR is not affected by the instruction Exceptions are not taken upon execution of this instruction Any combination of the eight floating point data registers can be transferred with selected registers specified by a user supplied mask This mask is an 8 bit number where each bit corresponds to one register if a bit is set in the mask that register is moved Note that a null register list all zeros generates a line F exception FMOVEM allows two addressing modes address register indirect and base register plus 16 bit displacement where the base is an address register or for loads only the program counter In all cases the processor calculates the starting address and then increments by 8 bytes for each register moved The transfer order is always
39. Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay d46 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 46 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVEM MOVEM Move Multiple Registers All ColdFire Processors Registers Destination Source Registers Assembler Syntax MOVEM L list lt ea gt x MOVEM L lt ea gt y list Operation Attributes Size longword Description Moves the contents of selected registers to or from consecutive memory locations starting at the location specified by the effective address A register is selected if the bit in the mask field corresponding to that register is set The registers are transferred starting at the specified address and the address is incremented by the operand length 4 following each transfer The order of the registers is from DO to D7 then from AO to A7 Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 Format 0 1 0 0 1 dr 0 0 1 Effective Address Mode Register Register List Mask Instruction Fields e dr field Specifies the direction of the transfer 0 register to memory memory to register e Effective Address field Specifies the memory address for the data transfer For register to memory transfers use the followin
40. Branch set on unordered Set on FBcc if the NAN bit is set and the condition selected is an IEEE nonaware test cleared otherwise INAN Input not a number Set if either input operand is a NAN cleared otherwise IDE Input denormalized number Set if either input operand is a denormalized number cleared otherwise Operand error Set under the following conditions FADD 00 oo or 2 00 FDIV 0 0 or oo co FMOVE OUT to B W L Integer overflow source is NAN or FMUL Source is lt 0 or v FSQRT One operand is 0 and the other is oo FSUB 02 oo or T ce c Cleared otherwise Overflow Set during arithmetic operations if the destination is a floating point data register or memory when the intermediate result s exponent is greater than or equal to the maximum exponent value of the selected rounding precision Cleared otherwise Overflow occurs only when the destination is S or D precision format overflows for other formats are handled as operand errors Underflow Set if the intermediate result of an arithmetic instruction is too small to be represented as a normalized number in a floating point register or memory using the selected rounding precision that is when the intermediate result exponent is less than or equal to the minimum exponent value of the selected rounding precision Cleared otherwise Underflow can only occur when the destination format is single or double precisio
41. PST 0xB DD source operand or l Dy lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination ori l lt data gt Dx PST 0x1 pea l lt ea gt y PST 0x1 PST 0xB DD destination operand pulse PST 0x4 rems lt ea gt y Dw Dx PST 0x1 PST 0xB DD source operand remu lt ea gt y Dw Dx PST 0x1 PST 0xB DD source operand rts PST 0x1 PST 0x5 0x9 0xA 0xB target address PST 0x1 PST 0xB DD source operand PST 0x5 PST 0x9 0xA 0xB DD target address sats Dx PST 0x1 scc b Dx PST 0x1 sub lt ea gt y Dx PST 0x1 PST 0xB DD source operand sub Dy lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination suba lt ea gt y Ax PST 0x1 PST 0xB DD source operand subi lt data gt Dx PST 0x1 subq lt data gt lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination subx Dy Dx PST 0x1 swap w Dx PST 0x1 tas b lt ea gt X PST 0x1 0x8 source 0x8 destination tpf PST 0x1 tpf l lt data gt PST 0x1 tpf w lt data gt PST 0x1 trap lt data gt PST 0x1 tst b lt ea gt x PST 0x1 PST 0x8 DD source operand tst l lt ea gt y PST 0x1 PST 0xB DD source operand tst w lt ea gt y PST 0x1 PST 0x9 DD source operand unlk Ax PST 0x1 PST 0xB DD destination operand wddata b lt ea gt y PST 0x4 PST 0x8 DD source operand wddata lt ea gt y PST 0x4
42. PST 0xB DD source operand wddata w lt ea gt y PST 0x4 PST 0x9 DD source operand 10 4 ColdFire Family Programmer s Reference Manual M MOTOROLA User Instruction Set 1 During normal exception processing the PST output is driven to a OxC indicating the exception processing state The exception stack write operands as well as the vector read and target address of the exception handler may also be displayed Exception Processing PST Oxc PST OxB DD destination stack frame PST 0xB DD destination stack frame PST 0xB DD source vector read PST 0x5 PST 0x9AB DD target handler PC The PST DDATA specification for the reset exception is shown below Exception Processing PST OxC PST 0x5 PST 0x9AB DD target handler PC The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches For all types of exception processing the PST OxC value is driven at all times unless the PST output is needed for one of the optional marker values or for the taken branch indicator 0x5 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This includes the following lt ea gt x values An d16 An d8 An Xi d8 PC Xi For Move Multiple instructions MOVEM the processor automaticall
43. dg PC Xi 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros e R M field Specifies the source operand address mode The operation is lt ea gt y to register The operation is register to register e Source specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy e Destination register field Specifies the destination floating point register FPx e Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0100011 FMUL Rounding precision specified by the FPCR 1100011 FSMUL Single precision rounding 1100111 FDMUL Double precision rounding 7 34 ColdFire Family Programmer s Reference Manual M MOTOROLA FNEG Operation Assembler syntax Attributes Floating Point Negate Source FPx FNEG fmt lt ea gt y FPx FNEG D FPy FPx FNEG D FPx FrNEG fmt lt ea gt y FPx FrNEG D FPy FPx FrNEG D FPx where r is rounding precision S or D Instruction Descriptions FNEG Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and inverts the sign of the mantissa Stores the result in the destination floating point data register FPx
44. initiating a floating point instruction other than FSAVE FMOVEM FMOVE of system registers or another FRESTORE causes a pending exception The programmer s model is unaffected by loading this type of state frame except FPSR and FPCR are loaded from the state frame FPSR Cleared if NULL frame format otherwise loaded from state frame FPCR Cleared if NULL frame format otherwise loaded from state frame FPIAR Cleared if NULL frame format otherwise unchanged M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 3 FRESTORE Restore Internal Floating Point State FRESTORE Floating point data registers Set to NANs if NULL frame format otherwise unaffected Instruction 15 14 13 12 11 10 9 4 3 2 1 0 Format 1 1 1 1 0 0 1 Source Effective Address Mode Register Instruction field e Source Effective Address field Specifies the addressing mode lt ea gt y for the state frame Only modes in the following table can be used ColdFire Family Programmer s Reference Manual Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay Ay di6 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi M MOTOROLA FSAVE Save Internal FSAVE Float
45. number Ax dg PC Xi En TAS V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported B M mororoLA Chapter 4 Integer User Instructions 4 79 TPF Trap False TPF All ColdFire Processors Operation No Operation Assembler Syntax TPF PC 2 PC TPE W lt data gt PC 4 PC TPEL lt data gt PC 6 PC Attributes Size unsized word longword Description Performs no operation TPF can occupy 16 32 or 48 bits in instruction space effectively providing a variable length single cycle no operation instruction When code alignment is desired TPF is preferred over the NOP instruction as the NOP instruction also synchronizes the processor pipeline resulting in multiple cycle operation TPE WL can be used for elimination of unconditional branches for example if a b which typically compiles to cmp 1 do d1 compare a b beq b label0 branch if equal movq 1 2 d2 z 2 bra b labell continue label0 movq l 1 d2 3 Zz 21 labell For this type of sequence the BRA B instruction can be replaced with a TPF W or TPF L opcode depending on the length of the instruction at label0 in this case a TPF W opcode would be applicable The instruction s at the first label effectively become packaged as extension words of the TPF instruction and the branch is completely eliminated Condition Codes Not affected Instruction 15 14 13 12
46. word sized operation 0 lower word 1 upper word 5 14 ColdFire Family Programmer s Reference Manual M MOTOROLA MSAC Multiply Subtract with Load MSAC Operation ACC Ry Rx lt lt gt gt SF ACC lt ea gt y Rw Assembler syntax MSAC sz Ry U L Rx U L SK lt ea gt y amp Rw where amp enables the use of the MASK Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 32 bit result then subtract this product shifted as defined by the scale factor from the accumulator If 16 bit operands are used the upper or lower word of each register must be specified In parallel with this operation a 32 bit operand is fetched from the memory location defined by lt ea gt y and loaded into the destination register Rw If the MASK register is specified to be used the lt ea gt y operand is ANDed with MASK prior to being used by the instruction Condition N Z V N Set if the msb of the result is set cleared otherwise Cod Z Set if the result is zero cleared otherwise odes V Set if an overflow is generated unchanged otherwise MACSR Instruction 15 14 13 12 t 10 9 8 7 6 5 Belk Ad 0 Format 1 0 1 0 Register Rw 0 1 Rw Source Effective Address Mode Register Register Rx SZ Scale 1 U Lx U Ly Mask 0 Register Ry Factor Instruction Fields e Register Rw 6 11 9 field Specifies the destination reg
47. 0 specifies the source floating point data register FPy e Destination register field Specifies the destination floating point register FPx e Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0100000 FDIV Rounding precision specified by FPCR 1100000 FSDIV Single precision rounding 1100100 FDDIV Double precision rounding M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 17 Instruction Descriptions FINT Floating Point Integer FINT Operation Integer Part of Source FPx Assembler Syntax FINT fmt lt ea gt y FPx FINT D FPy FPx FINTD FPx Attributes Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary extracts the integer part and converts it to a double precision value Stores the result in the destination floating point data register The integer part is extracted by rounding the double precision number to an integer using the current rounding mode selected in the FPCR mode control byte Thus the integer part returned is the number to the left of the radix point when the exponent is zero after rounding For example the integer part of 137 57 is 137 0 for round to zero and round to negative infinity modes and 138 0 for round to nearest and round to positive infinity modes Note that the result of this operation is a floating po
48. 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx 0000000 1000000 or 1000100 FMOVE 0xF2 0 Register to memory operation FPy lt ea gt x 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Destination Effective Address Mode Register 0 1 1 Destination Format Source 0 0 0 0 0 0 0 Register FPy FINT OxF2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination 0 0 0 0 0 0 1 Register FPx M MOTOROLA Chapter 9 Instruction Format Summary Operation Code Map FINTRZ OXF2 3 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 1 0 0 1 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination 0 0 0 0 1 1 Register FPx Source Effective Address 0 R M 0 Source Specifier Destination Opmode Register FPx 0000100 1000001 or 1000101 FABS OxF2 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx 0011000 1011000 or 1011100 FNEG OxF2 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Reg
49. 0x8 is AO OxF is A7 sz field Specifies the size of the input operands 0 word longword Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1 10 reserved 11 product gt gt 1 U Lx U Ly Specifies which 16 bit operand of the source register Rx Ry is used for a word sized operation 0 lower word 1 upper word Mask field Specifies whether or not to use the MASK register in generating the source effective address lt ea gt y 0 do not use MASK use MASK Register Ry field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 ColdFire Family Programmer s Reference Manual M MOTOROLA Floating Point Status Register FPSR Chapter 7 Floating Point Unit FPU User Instructions This chapter contains the instruction descriptions implemented in the optional floating point unit FPU Common information on the effects on the floating point status register FPSR and conditional testing has been consolidated in the front of the chapter 7 1 Floating Point Status Register FPSR The FPSR Figure 7 1 contains a floating point condition code byte FPCC a floating point exception status byte EXC and a floating point accrued exception byte AEXC The user can read or write all FPSR bits Execution of most floating point instructions modifies FPSR
50. 1 lt bit number gt of Destination BTST Dy lt ea gt x B L lt bit number gt of Destination CCR Z lt data gt lt ea gt x B L 3 1 6 Program Control Instructions A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations Also included are test operand instructions TST and FTST which set the integer or floating point condition codes for use by other program and system control instructions NOP forces synchronization of the internal pipelines TPF is a no operation instruction that does not force pipeline synchronization Table 3 7 summarizes these instructions 3 8 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Summary Table 3 7 Program Control Operation Format Instruction Operand Syntax Operand Size Operation Conditional Bee lt label gt B W L If Condition True Then PC d PC FBcc lt label gt W L If Condition True Then PC d gt PC Scc Dx B If Condition True Then 1s Destination Else Os Destination Unconditional BRA lt label gt B W L PC d PC BSR lt label gt B W L SP 4 gt SP nextPC SP PC dn PC FNOP none none PC 2 PC FPU pipeline synchronized JMP lt ea gt y none Source Address PC JSR lt ea gt y none SP 4 SP nextPC SP Source PC NOP none none PC 2 PC
51. 1 0 0 0 0 1 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number BCLR 0x08 00 Bit number static specified as immediate data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 1 0 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number BSET 0x08 00 Bit number static specified as immediate data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 1 1 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number EORI 0x0A8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o o o o ne Upper Word of Immediate Data Lower Word of Immediate Data M MOTOROLA Chapter 9 Instruction Format Summary 9 3 Operation Code Map CMPI 0x0C 1 14 139 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 Size 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data MOVE 0x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Size Destination Effective Address Source Effective Address Register Mode Mode Register MOVEA 0x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Size Destination 0 0 1 Source Effective Address Register Ax Mode Register NEGX 0x408 15 14 13 12 11 10 9 8 7 6 5 4 3
52. 10 reserved 11 product gt gt 1 U Lx Specifies which 16 bit operand of the source register Rx is used for a word sized operation 0 lower word 1 upper word U Ly Specifies which 16 bit operand of the source register Ry is used for a word sized operation 0 lower word 1 upper word M MOTOROLA Chapter 6 EMAC User Instructions 6 3 MAC MAC Multiply Accumulate with Load Operation ACCx Ry Rx lt lt gt gt SF ACCx lt ea gt y Rw Assembler syntax MAC sz Ry U L Rx U L SE lt ea gt y amp Rw ACCx where amp enables the use of the MASK Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 40 bit result then add this product shifted as defined by the scale factor to an accumulator If 16 bit operands are used the upper or lower word of each register must be specified In parallel with this operation a 32 bit operand is fetched from the memory location defined by lt ea gt y and loaded into the destination register Rw If the MASK register is specified to be used the lt ea gt y operand is ANDed with MASK prior to being used by the instruction Condition N Z V PAVx EV N Set if the msb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if a product or accumulation overflow is MACSR generated or PAVx 1 cleared otherwise PAVx Set if a product or accumulation overflow is g
53. 11 1 ILLUSTRATIONS Page Ting Number Address Register Indirect with Scaled Index and 8 Bit Displacement 2 6 Program Counter Indirect with Displacement ennen evenneeeenservenseerenverenn 2 7 Program Counter Indirect with Scaled Index and 8 Bit Displacement 2 8 Absolute Short Addressing e ei eer ances ood aE Re te 2 8 Absolute Long Addressing paissisiaisisesdcasasdstaacsesdecedenscbadseaesdancasdanes eadadedaresapladtousedeatanecead 2 9 Imm diate Data Adresses nant Ras ns nada ada craie init 2 9 Stack Growth from High Memory to Low Memory 2 11 Stack Growth from Low Memory to High Memory 2 11 Floating Point Status Register FPSR lune nantes 7 1 Exception Stack Beanie wesende etn etn 11 5 ColdFire Family Programmer s Reference Manual M MOTOROLA TABLES Table Page Number ue Number 1 1 COR Bit Descriptions Aie a taime amande re 1 3 1 2 BEER PIeld DES Crip itl OMS ST M nn AT ne ti se 1 5 1 3 EESB PIEIT DESCADUONSS St nn a E E T E eRe 1 5 1 4 MACSR Field Descriptions senen teen senden seen 1 7 1 5 MACS RK Field Descriptions ERN nend 1 9 1 6 Implemented Supervisor Registers by Device ss 1 12 1 7 Stats Field Descriptions fans ne dee A ef ce E e ER 1 13 1 8 MMU Base Address Register Field Descriptions 1 15 1 9 MBAR Field DESCTIPHONS 5 00 nn rt ete Se a ee de 1 16 1 10 Integer Data BornialSs tinten nenten aba sn RS Meese one ie oet eens 1 16 1 11 Real Format Summary eii ne as
54. 11 2 M MOTOROLA Index Index 9 INDEX Index 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Introduction Addressing Capabilities Instruction Set Summary Integer User Instructions MAC User Instructions EMAC User Instructions FPU User Instructions Supervisor Instructions Instruction Format Summary PST DDATA Encodings Exception Processing Processor Instruction Summary S Record Output Format Index ES INID N IND Introduction Addressing Capabilities Instruction Set Summary Integer User Instructions MAC User Instructions EMAC User Instructions FPU User Instructions Supervisor Instructions Instruction Format Summary PST DDATA Encodings Exception Processing Processor Instruction Summary S Record Output Format Index
55. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oee fo els Jo 4 Joel intone Preacat 16 bit displacement or most significant word of 32 bit displacement Least significant word of 32 bit displacement if needed FMOVE to FPIAR 0xF2 8400 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 M MOTOROLA Chapter 9 Instruction Format Summary 9 17 Operation Code Map FMOVE to FPSR 0xF2 8800 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Source Effective Address Mode Register 1 0 0 0 1 0 0 0 0 0 0 FMOVE to FPCR 0xF2 9000 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Source Effective Address Mode Register 1 0 0 1 0 0 0 0 0 0 0 FMOVE from FPIAR 0xF2 A400 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Destination Effective Address Mode Register 1 0 1 0 0 1 0 0 0 0 0 FMOVE from FPSR 0xF2 A800 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Destination Effective Address Mode Register 1 0 1 0 1 0 0 0 0 0 0 FMOVE from FPCR 0xF2 B000 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Destination Effective Address Mode Register 1
56. 3 0 mn BSUN INAN OPERR OVFL UNFL DZ INEX IDE PREC RND Figure 1 4 Floating Point Control Register FPCR Table 1 2 describes FPCR fields 1 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Floating Point Unit User Programming Model Table 1 2 FPCR Field Descriptions Bits Field Description 31 16 Reserved should be cleared 15 8 EE Exception enable byte Each EE bit corresponds to a floating point exception class The user can separately enable traps for each class of floating point exceptions 15 BSUN Branch set on unordered 14 INAN Input not a number 13 OPERR Operand error 12 OVFL Overflow 11 UNFL Underflow 10 DZ Divide by zero 9 INEX Inexact operation 8 IDE Input denormalized 7 0 MC Mode control byte Controls FPU operating modes 7 Reserved should be cleared 6 PREC Rounding precision 5 4 RND Rounding mode 3 0 Reserved should be cleared 1 2 2 Floating Point Status Register FPSR The FPSR Figure 1 5 contains a floating point condition code byte FPCC a floating point exception status byte EXC and a floating point accrued exception byte AEXC The user can read or write all FPSR bits Execution of most floating point instructions modifies FPSR FPSR is loaded by using FMOVE or FRESTORE A pr
57. 8 Possible Operand Errors jsiscascsccceisisdeataseshas oeedscade n catesdaeea n N 11 12 11 9 OPERR Exception Enabled Disabled Results oon eeenne erneer 11 12 11 10 OVEL Exception Enabled Disabled Results 11 13 11 11 UNFL Exception Enabled Disabled Results 11 14 11 12 DZ Exception Enabled Disabled Results 11 14 11 13 Inexact Rounding Mode Vall es assente hiene de ee 11 14 11 14 INEX Exception Enabled Disabled Results 11 15 11 15 OEP EX Cycle Operations ananas suntan lire 11 16 12 1 Standard POUCES He ee n ed eind 12 1 12 2 ColdFire Instruction Set and Processor Cross Reference nnen veen eennnenn 12 2 12 3 ColdFire MAC and EMAC Instruction Sets 12 4 12 4 Co ldFire PRU INSEE tenet adders ronse nnen ne hanen 12 5 xii ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 1 Introduction This manual contains detailed information about software instructions used by the Version 2 V2 Version 3 V3 and Version 4 V4 ColdFire microprocessors The ColdFire Family programming model consists of two register groups user and supervisor Programs executing in the user mode use only the registers in the user group System software executing in the supervisor mode can access all registers and use the control registers in the supervisor group to perform supervisor functions The following paragraphs provide a brief description of the registers in the user and supervisor models as well as the data organization in th
58. 89B source fintrz sz lt ea gt y FPx PST 0x1 89B source fmove sz lt ea gt y FPx PST 0x1 89B source fmove sz FPy lt ea gt x PST 0x1 89B destination fmove lt ea gt y FP R PST 0x1 B source fmove FP R lt ea gt x PST 0x1 B destination fmovem lt ea gt y list PST 0x1 fmovem list lt ea gt x PST 0x1 fmul sz lt ea gt y FPx PST 0x1 89B source 10 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Supervisor Instruction Set Table 10 3 PST DDATA Values for User Mode Floating Point Instructions Continued Instruction Operand Syntax PST DDATA fneg sz lt ea gt y FPx PST 0x1 89B source fnop PST 0x1 fsqrt sz lt ea gt y FPx PST 0x1 89B source fsub sz lt ea gt y FPx PST 0x1 89B source fist sz lt ea gt y PST 0x1 89B source 1 The FP R notation refers to the floating point control registers FRCR FPSR and FPIAR Depending on the size of any external memory operand specified by the f lt op gt fmt field the data marker is defined as shown in Table 10 4 Table 10 4 Data Markers and FPU Operand Format Specifiers Format Specifier Data Marker b 8 W 9 B S B d Never captured 10 2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below The PST DDATA specification for these opcode
59. Assembler Syntax TAS B lt ea gt x Attributes Size byte Description Tests and sets the byte operand addressed by the effective address field The instruction tests the current value of the operand and sets CCR N and CCR Z appropriately TAS also sets the high order bit of the operand The operand uses a read modify write memory cycle that completes the operation without interruption This instruction supports use of a flag or semaphore to coordinate several processors Note that unlike 68K Family processors Dx is not a supported addressing mode Condition X N Z V C X Not affected 3 0 0 N Set if the msb of the operand was set cleared Codes otherwise Z Set if the operand was zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 413 12 n 10 9 8 7 6 5 4 3 2 4 0 Format 0 1 0 0 1 0 1 0 1 1 Destination Effective Address Mode Register Instruction Fields e Destination Effective Address field Specifies the destination location lt ea gt x the possible data alterable addressing modes are listed in the table below Addressing Mode Mode Register Addressing Mode Mode Register Dx xx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi 110 reg
60. Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 Ax 101 reg number Ax d 6 PC dg Ax Xi 110 reg number Ax dg PC Xi Du M mororoLA Chapter 4 Integer User Instructions 4 3 ADDA Operation Add Address All ColdFire Processors Assembler Syntax ADDA L lt ea gt y Ax Attributes Size longword Source Destination Destination ADDA Description Operates similarly to ADD but is used when the destination register is an address register rather than a data register Adds the source operand to the destination address register and stores the result in the address register The size of the operation is specified as a longword Condition Codes Not affected Instruction 5 14 Format 1 1 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 Destination 1 1 1 Source Effective Address Register Ax Mode Register Instruction Fields e Destination Register field Specifies the destination register Ax e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay
61. Dx 0 0 0 0 0 0 0 0 0 Register Dw Instruction Fields e Register Dx field Specifies the destination register Dx e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi e Register Dw field Specifies the remainder register Dw 4 68 ColdFire Family Programmer s Reference Manual M MOTOROLA RTS Return from Subroutine RTS All ColdFire Processors Operation SP PC SP 4 SP Assembler Syntax RTS Attributes Unsized Description Pulls the program counter value from the stack The previous program counter value is lost The opcode for RTS is 0x4E75 Condition Codes Not affected wo D Instruction 15 14 13 12 1 10 9 8 7 6 5 4 Format lo Tare rek rara Cr Te Tale TA do M mororoLA Chapter 4 Integer User Instructions 4 69 SATS Signed Saturate SATS Supported starting with V4 Operation Tf CCR V 1 then if Dx 31 0 then Dx 31 0 0x80000000 else Dx 31 0 OxX7FF
62. Ei 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 1 0 0 0 1 1 1 1 1 1 Opmode Optional Immediate Word Optional Immediate Word Instruction Fields e Opmode field Specifies the number of optional extension words 010 one extension word 011 two extension words 100 no extension words 4 80 ColdFire Family Programmer s Reference Manual M MOTOROLA TRAP Trap TRAP All ColdFire Processors Operation 1 gt S Bit of SR SP 4 SP nextPC SP SP 2 SP SR SP SP 2 SP Format Offset SP VBR 0x80 4 n PC where n is the TRAP vector number Assembler Syntax TRAP lt vector gt Attributes Unsized Description Causes a TRAP lt vector gt exception The TRAP vector field is multiplied by 4 and then added to 0x80 to form the exception address The exception address is then added to the VBR to index into the exception vector table The vector field value can be 0 15 providing 16 vectors Note when SR is copied onto the exception stack frame it represents the value at the beginning of the TRAP instruction s execution At the conclusion of the exception processing the SR is updated to clear the T bit and set the S bit Note also that for processors beginning with V4 for devices which have an MMU the SSP is used for this operation Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format MoU ics RTE NE eV NE l1 o Vo INA 10 Vector
63. FPO FP7 NOTE FMOVEM offers the only way to move floating point data between the FPU and memory without converting data or affecting condition code and exception status bits FPSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Effective Address Mode Register 1 1 dr 1 0 0 0 0 Register List M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 31 Instruction Descriptions FMOVEM Move Multiple Floating Point Data Registers FMOVEM Instruction fields e Effective address field Specifies the addressing mode For memory to register the allowed lt ea gt y modes are shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay Ay d16 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi TE e Effective address field Specifies the addressing mode For register to memory the allowed lt ea gt x modes are shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx xxx W Ax xxx L Ax 010 reg number Ax lt data gt re Ax Ax en di6 Ax 101 reg number Ax d45 PC dg Ax Xi dg
64. Family Programmer s Reference Manual M MOTOROLA DIVS Signed Divide DIVS All ColdFire Processors Starting with MCF5206e Operation Destination Source Destination Assembler Syntax DIVS W lt ea gt y Dx 32 bit Dx 16 bit lt ea gt y 16r 16q in Dx DIVS L lt ea gt y Dx 32 bit Dx 32 bit lt ea gt y 32q in Dx where q indicates the quotient and r indicates the remainder Attributes Size word longword Description Divide the signed destination operand by the signed source and store the signed result in the destination For a word sized operation the destination operand is a longword and the source is a word the 16 bit quotient is in the lower word and the 16 bit remainder is in the upper word of the destination Note that the sign of the remainder is the same as the sign of the dividend For a longword sized operation the destination and source operands are both longwords the 32 bit quotient is stored in the destination To determine the remainder on a longword sized operation use the REMS instruction An attempt to divide by zero results in a divide by zero exception and no registers are affected The resulting exception stack frame points to the offending divide opcode If overflow is detected the destination register is unaffected An overflow occurs if the quotient is larger than a 16 bit W or 32 bit L signed integer Condition X N Z V C X Not affected Codes 0 N Cleared if overflow is detected othe
65. Growth from High Memory to Low Memory To implement stack growth from low memory to high memory use An to push data on the stack and An to pull data from the stack After either a push or pull operation the address register points to the next available space on the stack LOW MEMORY BOTTOM OF STACK e e e 7 TOP OF STACK An FREE HIGH MEMORY Figure 2 16 Stack Growth from Low Memory to High Memory M mororoLA Chapter 2 Addressing Capabilities 2 11 Stack 2 12 ColdFire Family Programmer s Reference Manual AA MOTOROLA Chapter 3 Instruction Set Summary This section briefly describes the ColdFire Family instruction set using Motorola s assembly language syntax and notation It includes instruction set details such as notation and format 3 1 Instruction Summary Instructions form a set of tools that perform the following types of operations Data movement Program control Integer arithmetic System control Logical operations Cache maintenance Shift operations Floating point arithmetic Bit manipulation The following paragraphs detail the instruction for each type of operation Table 3 1 lists the notations used throughout this manual In the operand syntax statements of the instruction definitions the operand on the right is the destination operand M mororoLa Chapter 3 Instruction Set Summary 3 1 Instruction Summary Table 3 1 Notational Conventions Single And Double
66. If R M 0 the operation is register to register If R M 1 the operation is lt ea gt y to register Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi e Source specifier field Specifies the source register or data format If R M 0 specifies the source floating point data register FPy If R M 1 specifies the source data format See Table 7 6 e Destination register field Specifies the destination floating point register FPx e Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0000000 FMOVE Rounding precision specified by the FPCR 1000000 FSMOVE Single precision rounding 1000100 FDMOVE Double precision rounding M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 23 Instruction Descriptions FMOVE Move Floating Point Data Register FMOVE Register to memory operation FPy lt ea gt x Rounds the source operand to the specified destination format and stores it at the destination effective address lt ea gt x Note that the rounding mode in FPCR is ignored for register to memory operations FPSR FPCC Not affected
67. Immediate Data M MOTOROLA Chapter 9 Instruction Format Summary 9 9 Operation Code Map MVS 0x7 15 14 13 12 11 10 9 7 6 4 3 2 1 0 0 1 1 1 Register Dx 0 Size Source Effective Address Mode Register MVZ 0x7 15 14 13 12 11 10 9 7 6 4 3 2 1 0 0 1 1 1 Register Dx 1 Size Source Effective Address Mode Register OR 0x8 15 14 13 12 11 10 9 7 6 4 3 2 1 0 1 0 0 0 Register Opmode Effective Address Mode Register DIVU W 0x8 15 14 13 12 11 10 9 7 6 4 3 2 1 0 1 0 0 0 Register Dx 1 1 Source Effective Address Mode Register DIVS W 0x8 15 14 13 12 11 10 9 7 6 4 3 2 1 0 1 0 0 0 Register Dx 1 1 Source Effective Address Mode Register SUB 0x9 15 14 13 12 11 10 9 7 6 4 3 2 1 0 1 0 0 1 Register Opmode Effective Address Mode Register SUBX 0x9 15 14 13 12 11 10 9 7 2 1 0 1 0 0 1 Register Dx 1 0 0 0 Register Dy SUBA 0x9 15 14 13 12 11 10 9 7 6 4 3 2 1 0 1 0 0 1 Destination 1 1 Source Effective Address Register Ax 2 Mode Register 9 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map MAC MAC OXA 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0
68. MBAR The supervisor level MBAR Figure 1 18 specifies the base address and allowable access types for all internal peripherals MBAR can be read or written through the debug module as a read write register only the debug module can read MBAR All internal peripheral registers occupy a single relocatable memory block along 4 Kbyte boundaries MBAR masks specific address spaces using the address space fields Refer to a specific device or core user s manual for further information M mororoLA Chapter 1 Introduction 1 15 Integer Data Formats Attribute Mask Bits 31 1211 9 8 7 6 5 4 3 2 1 0 BA WP AM ca sc so uc uo v Figure 1 18 Module Base Address Register MBAR Table 1 9 describes MBAR fields Table 1 9 MBAR Field Descriptions Bits Field Description 31 12 BA Base address Defines the base address for a 4 Kbyte address range 11 9 Reserved should be cleared 8 1 AMB Attribute mask bits 8 WP Write protect Mask bit for write cycles in the MBAR mapped register address range 7 Reserved should be cleared 6 AM Alternate master mask 5 C I Mask CPU space and interrupt acknowledge cycles 4 SC Setting masks supervisor code space in MBAR address range 3 SD Setting masks supervisor data space in MBAR address range 2 UC Setting masks user code space in MBAR address range 1 UD S
69. N Not affected Z Set if the bit tested is zero cleared otherwise V Not affected C Not affected Bit Number Static Specified as Immediate Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction 0 0 0 0 1 0 0 0 0 1 Destination Effective Address Format Mode Register 0 0 0 0 0 0 0 0 Bit Number M mororoLA Chapter 4 Integer User Instructions 4 15 BCHG BCHG Test a Bit and Change Instruction Fields e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W _ Ax xxx L Ax 010 reg number Ax lt data gt En Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi dg PC Xi e Bit Number field Specifies the bit number Bit Number Dynamic Specified in a Register Instruction 15 14 43 12 11 10 9 8 7 6 5 44 3 2 1 0 Format 0 0 0 0 Data Register Dy 1 0 1 Destination Effective Address Mode Register Instruction Fields e Data Register field Specifies the data register Dy that contains the bit
70. PC to the destination PC If the 8 bit displacement field in the instruction word is 0 a 16 bit displacement the word immediately following the instruction is used If the 8 bit displacement field in the instruction word is all ones OxFF the 32 bit displacement longword immediately following the instruction is used A branch to the next immediate instruction automatically uses the 16 bit displacement format because the 8 bit displacement field contains 0x00 zero offset Condition codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format o i 1 0 0 0 o 0 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displacement if 8 bit displacement OxFF Instruction Fields e 8 bit displacement field Two s complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed e 16 bit displacement field Used for displacement when the 8 bit displacement contains 0x00 e 32 bit displacement field Used for displacement when the 8 bit displacement contains OxFF BRA V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported B W B W L M mororoLA Chapter 4 Integer User Instructions 4 19 BS ET Test a Bit and Set BS ET All ColdFire Processors Operation lt bit number gt of Destination CCR Z 1 gt lt bit number gt of Destinat
71. Programmer s Reference Manual M MOTOROLA Chapter 11 Exception Processing This chapter describes exception processing for the ColdFire family 11 1 Overview Exception processing for ColdFire processors is streamlined for performance Differences from previous M68000 Family processors include the following e A simplified exception vector table e Reduced relocation capabilities using the vector base register e A single exception stack frame format e Use of a single self aligning stack pointer Because the V4 core can implement an MMU exception processing for devices containing an MMU is slightly modified Differences from previous ColdFire Family processors include the following e An instruction restart model for translation TLB miss and access faults This new functionality extends the existing ColdFire access error fault vector and exception stack frames e Use of separate system stack pointers for user and supervisor modes Previous ColdFire processors V2 and V3 use an instruction restart exception model but require additional software support to recover from certain access errors Exception processing can be defined as the time from the detection of the fault condition until the fetch of the first handler instruction has been initiated It consists of the following four major steps 1 The processor makes an internal copy of the status register SR and then enters supervisor mode by setting SR S and disabling trace m
72. REMS To determine the quotient use DIVS An attempt to divide by zero results in a divide by zero exception and no registers are affected The resulting exception stack frame points to the offending REMS opcode If overflow is detected the destination register is unaffected An overflow occurs if the quotient is larger than a 32 bit signed integer Condition X N Z V C X Not affected Codes 0 N Cleared if overflow is detected otherwise set if the quotient is negative cleared if positive Z Cleared if overflow is detected otherwise set if the quotient is zero cleared if nonzero V Set if an overflow occurs cleared otherwise C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 0 0 0 1 Source Effective Address Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 0 Register Dw Instruction Fields e Register Dx field Specifies the destination register Dx e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi
73. Record Length Address Code Data Checksum Figure A 1 Five Fields of an S Record Table A 1 Field Composition of an S Record Field AE Contents Characters Type 2 S record type S0 S1 etc Record Length 2 The count of the character pairs in the record excluding the type and record length Address 4 6 or 8 The 2 3 or 4 byte address at which the data field is to be loaded into memory Code Data 0 2n From 0 to n bytes of executable code memory loadable data or descriptive information Some programs may limit the number of bytes to as few as 28 56 printable characters in the S record Checksum 2 The least significant byte of the one s complement of the sum of the values represented by the pairs of characters making up the record length address and the code data fields M mororoLa Appendix A S Record Output Format A 1 S Record Types When downloading S records each must be terminated with a CR Additionally an S record may have an initial field that fits other data such as line numbers generated by some time sharing systems The record length byte count and checksum fields ensure transmission accuracy A 2 S Record Types There are eight types of S records to accommodate the encoding transportation and decoding functions The various Motorola record transportation control programs e g upload download etc cross assemblers linkers and other file creating or debugging programs o
74. See Table 7 2 0 See re like signed infinities Table 7 2 leared otherwise FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 B 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx 7 40 ColdFire Family Programmer s Reference Manual M MOTOROLA FSUB Instruction fields Instruction Descriptions FSUB Floating Point Subtract Effective address field Determines the addressing mode for external operands If R M 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes listed in the following table can be used 7 Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay di6 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi dg PC Xi Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros R M field Specifies the source operand address mode 1 The operation is lt ea gt y to register 0 The operation is register to register Source Specifier field Specifies the s
75. Unsigned Multiply MULU All ColdFire Processors Operation Source Destination gt Destination Assembler Syntax MULU W lt ea gt y Dx 16 x 16 gt 32 MULU L lt ea gt y Dx 32 x 32 32 Attributes Size word longword Description Multiplies two unsigned operands yielding an unsigned result This instruction has a word operand form and a longword operand form In the word form the multiplier and multiplicand are both word operands and the result is a longword operand A register operand is the low order word the upper word of the register is ignored All 32 bits of the product are saved in the destination data register In the longword form the multiplier and multiplicand are both longword operands and the destination data register stores the low order 32 bits of the product The upper 32 bits of the product are discarded Note that CCR V is always cleared by MULU unlike the 68K family processors Condition X N Z V C X Not affected Codes 0 0 N Set if result is negative cleared otherwise oqes Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 0 0 Register Dx 0 1 1 Source Effective Address Word Mode Register Instruction Fields Word e Register field Specifies the destination data register Dx e Effective Address field Specifies the source operand lt ea gt y use only those data addres
76. Xi M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions MOVE to MASK MOVE to MASK Move to the MAC MASK Register Operation Source MASK Assembler Syntax MOVE L Ry MASK MOVE L lt data gt MASK Attributes Size longword Description Moves a 16 bit value from the lower word of a register or an immediate operand into the MASK register MACSR Not affected Instruction Format 15 14 13 12 4 3 2 1 1 0 1 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay lt data gt 111 100 Ay Ay dig Ay di6 PC dg Ay Xi Due dg PC Xi esi 5 12 ColdFire Family Programmer s Reference Manual M MOTOROLA MSAC Multiply Subtract MSAC Operation ACC Ry Rx lt lt gt gt SF ACC Assembler syntax MSAC sz Ry U L Rx U L SF Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 32 bit result then subtract this product shifted as defined by the scale factor from the accumulator If 16
77. a processor status encoding matching the PULSE instruction 0x4 before the referenced operand is displayed on the DDATA outputs Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 m Res Instruction Fields 5 4 3 2 1 0 Source Effective Address e Size field specifies the size of the operand data 00 byte operation 01 word operation 10 longword operation 11 reserved e Source Effective Address field Determines the addressing mode for the operand lt ea gt y to be written to the DDATA signal pins use only those memory alterable addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC En dg Ay Xi 110 reg number Ay dg PC Xi 4 84 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions This chapter describes the user instructions for the optional multiply accumulate MAC unit in the ColdFire family of processors A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic For instructions implemented by the Enhanced Multiply Accumulate Unit EMAC refer to Chap
78. a specific EMAC accumulator register ACCx ACCy Destination and source accumulators respectively ACCext01 Four extension bytes associated with EMAC accumulators 0 and 1 ACCext23 Four extension bytes associated with EMAC accumulators 2 and 3 EV Extension overflow flag in MACSR MACSR MAC status register MASK MAC mask register PAVx Product accumulation overflow flags in MACSR RxSF A register containing a MAC operand that is to be scaled Rw Destination register for a MAC with load operation M MOTOROLA Chapter 3 Instruction Set Summary Instruction Summary Table 3 1 Notational Conventions Continued Floating Point Operations fmt Format of operation Byte B Word W Longword L Single precision S Double precision D inf Positive infinity inf Negative infinity FPx FPy Destination and source floating point data registers respectively FPCR Floating point control register FPIAR Floating point instruction address register FPSR Floating point status register NAN Not a number 3 1 1 Data Movement Instructions The MOVE and FMOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data MOVE instructions transfer byte word and longword operands from memory to memory memory to register register to memory and register to register MOVEA instructions transfer word and longword operands and ensure that only valid address mani
79. a specific register Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used An instruction s addressing mode specifies the value of an operand a register that contains the operand or how to derive the effective address of an operand in memory Each addressing mode has an assembler syntax Some instructions imply the addressing mode for an operand These instructions include the appropriate fields for operands that use only one addressing mode 2 2 1 Data Register Direct Mode In the data register direct mode the effective address field specifies the data register containing the operand Generation EA Dn Assembler Syntax Dn EA Mode Field 000 EA Register Field Register number Number of Extension Words Data Register Operand Figure 2 3 Data Register Direct 2 2 2 Address Register Direct Mode In the address register direct mode the effective address field specifies the address register containing the operand Generation EA An Assembler Syntax An EA Mode Field 001 EA Register Field Register number Number of Extension Words 0 Address Register Operand Figure 2 4 Address Register Direct 2 2 3 Address Register Indirect Mode In the address register indirect mode the operand is in memory The effective address field specifies the address register containing the address of the operand in memory M
80. accumulation overflow bit is cleared Condition N Z V PAVx EV N Set if the msb of the result is set cleared otherwise 0 0 0 Z Set if the result is zero cleared otherwise Codes V Always cleared MACSR PAVx Always cleared EV Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 0 ACC 1 0 0 Source Effective Address Mode Register Instruction Fields e ACC Specifies the destination accumulator The value of bits 10 9 specify the accumulator number e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay lt data gt 111 100 Ay Ay rn d16 Ay die PC dg Ay Xi dg PC Xi 6 16 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE MOVE to ACCextO1 move to Accumulator to ACCext01 0 and 1 Extensions Operation Source Accumulator 0 and 1 extension words Assembler syntax MOVE L Ry ACCext01 MOVE L lt data gt ACCext01 Attributes Size longword Description Moves a 32 bit value from a register or an immediate operand into the four extension bytes associated with accumulators 0 and 1 The accumulator extension by
81. affects the accumulator extension bytes and the product accumulation overflow indicator The store accumulator function is quite complex and a function of the EMAC configuration defined by the MACSR The following pseudocode defines its operation in this description ACC 47 0 represents the concatenation of the 32 bit accumulator and the 16 bit extension word if MACSR S U F I 00 signed integer mod if MACSR OMC then ACC 31 0 Rx saturation disabled else if ACC 47 31 0x0000_0 or OxFFFF_1 then ACC 31 0 Rx else if ACC 47 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx if MACSR S U F I 10 unsigned integer mod if MACSR OMC then ACC 31 0 Rx saturation disabled else if ACC 47 32 0x0000 then ACC 31 0 Rx else OxFFFF_FFFF Rx if MACSR F I signed fractional mode OMC S U R T 000 no saturation no 16 bit rnd no 32 bit rnd 1f MACSR then ACC 39 8 Rx if MACSR OMC S U R T 001 no saturation no 16 bit rnd 32 bit rnd then ACC 39 8 rounded by contents of 7 0 Rx if MACSR OMC S U 01 no saturation 16 bit rounding then 0 Rx 31 16 ACC 39 24 rounded by contents of 23 0 Rx 15 0 if MACSR OMC S U R T 100 saturation no 16 bit rnd no 32 bit rnd if ACC 47 39 0x00_0 or OxFF_1 then ACC 39 8 Rx else if ACC 47 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx if MACSR OMC S U R T 101
82. all zeros R M field Specifies the source operand address mode The operation is lt ea gt y to register 0 The operation is register to register Source specifier field Specifies the source register or data format If R M l specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPx Destination register field FTST uses the command word format used by all FPU arithmetic instructions but ignores and does not overwrite the register specified by this field This field should be cleared for compatibility with future devices however because this field is ignored for the FTST instruction the FPU does not signal an exception if the field is not zero M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 43 Instruction Descriptions 7 44 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 8 Supervisor Privileged Instructions This section contains information about the supervisor privileged instructions for the ColdFire Family Each instruction is described in detail with the instruction descriptions arranged in alphabetical order by instruction mnemonic Supervisor instructions for optional core modules for example the floating point unit are also detailed in this section Not all instructions are supported by all ColdFire processors The original ColdFire Instruction Set Architecture ISA_A is supported by V2 and V3
83. cores The V4 core supports ISA_B which encompasses all of ISA_A extends the functionality of some ISA_A instructions and adds several new instructions These extensions can be identified by a table which appears at the end of each instruction description where there are ISA_B differences M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 1 CPUSHL Push and Possibly CPUSHL Invalidate Cache All ColdFire Processors Operation If Supervisor State Then if Data Valid and Modified Push Cache Line Then Invalidate Line if Programmed in CACR Else Privilege Violation Exception Assembler Syntax CPUSHL dc Ax data cache CPUSHL ic Ax instruction cache CPUSHL bc Ax both caches or unified cache Attributes Unsized Description Pushes a specified cache line if modified and invalidates it if programmed to do so by CACR DPI Care should be exercised when clearing lines from both caches if the sizes of the caches are different For example using a device with a 16K instruction cache and an 8K data cache an address of 0x800 applied to both caches is referencing cache address 0x80 of the instruction cache but address 0x00 of the data cache Note that this instruction synchronizes the pipeline Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 1 0 0 Cache Register Ax mn oO Instruction Fields e Cache Specifies the aff
84. e Bits 3 0 of the first word define the specific control register DRc to write The table below contains DRc definitions Note that some cores implement a subset of the debug registers Refer to a specific device or core user s manual for more information DRc 4 0 Register Name DRc 4 0 Register Name 0x00 Configuration status register 0x10 0x1 Reserved Ox01 0x0 Reserved 0x14 PC breakpoint ASID register 0x04 PC breakpoint ASID control 0x15 Reserved 0x05 BDM address attribute register 0x16 Address attribute trigger register 1 0x06 Address attribute trigger register 0x17 Extended trigger definition register 0x07 Trigger definition register 0x18 Program counter breakpoint 1 register 0x08 Program counter breakpoint register 0x19 Reserved 0x09 Program counter breakpoint mask Ox1A Program counter breakpoint register 2 register 0x0A 0x0B Reserved 0x1B Program counter breakpoint register 3 0x0C Address breakpoint high register 0x1C Address high breakpoint register 1 0x0D Address breakpoint low register 0x1D Address low breakpoint register 1 Ox0E Data breakpoint register Ox1E Data breakpoint register 1 Ox0F Data breakpoint mask register Ox1F Data breakpoint mask register 1 e Data 31 0 is the 32 bit operand to be written e The fourth word is unused 8 18 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 9 Instruction Format Summary This chapter contain
85. field Specifies the addressing mode for external operands If R M 1 this field specifies the location of the source operand lt ea gt y Only modes in the following table can be used 7 Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay di6 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi dg PC Xi Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros R M field Specifies the source operand address mode The operation is lt ea gt y to register 0 The operation is register to register Source specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy Destination register field Specifies the destination floating point register FPx If R M 0 and source and destination fields are equal the input operand comes from the specified floating point data register and the result is written into the same register If single register syntax is used Motorola assemblers set the source and destination fields to the same value Opmode field Specifies the instruction and rounding precision
86. for comparison Not affected Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Set if an overflow occurs cleared otherwise Set if a borrow occurs cleared otherwise Condition X N Z V C Codes i id 5 O lt NZX Instruction 15 14 13 12 11 10 9 Format BER Md Register Ax Instruction Fields e Address Register field Specifies the destination register Ax e Opmode field Byte Word Longword Operation 011 111 AX lt ea gt y e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 CMPA V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported L W L M mororoLa Chapter 4 Integer User Instructions 4 27 CMPI Compare Immediate CMPI All ColdFire Processors B and W supported starting with V4 Operation Destination Immediate Data cc Assembler Syntax CMPI sz lt data gt Dx Attributes Size byte word l
87. gt y Ax W L3 CMPI lt data gt Dx B W L Destination Immediate Data cc User CPUSHL ic Ax none If data is valid and modified push cache line Super dc Ax invalidate line if programmed in CACR bc Ax INTOUCH Ax none Instruction fetch touch at Ax Super MOV3Q lt data gt lt ea gt x L Immediate Data Destination User MOVE lt ea gt y lt ea gt x B W L Source Destination User MOVE from USP Dx L USP Destination Super USP MOVE to USP Ay USP L Source USP Super MOVEA lt ea gt y Ax W L L Source gt Destination User MVS lt ea gt y Dx B W Source with sign extension Destination User MVZ lt ea gt y Dx B W Source with zero fill Destination User SATS Dx L If CCR V 1 User then if Dx 31 0 then Dx 31 0 0x80000000 else Dx 31 0 Ox7FFFFFFF else Dx 31 0 is unchanged TAS lt ea gt X B Destination Tested Condition Codes User a fF UO N 3 18 Longword supported starting with V4 Byte and word supported starting with V4 Word supported starting with V4 Additional addressing modes supported starting with V4 Supported starting with V4 on devices containing an MMU ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Set Additions Table 3 17 summarizes the instruction set supported by the original MAC unit Table 3 17 MAC Instruction Set Summary Operand A Super Instruction Operand Syntax Size Operation User MAC Ry RxSF ACC W L
88. in CACR bc Ax synchronizes pipeline FRESTORE lt ea gt y none FPU State Frame Internal FPU State FPU FSAVE lt ea gt X none Internal FPU State FPU State Frame FPU HALT none none Halt processor core ISA _A INTOUCH Ay none Instruction fetch touch at Ay ISA _B MOVE from SR SR Dx W SR Destination ISA _A MOVE from USP Dx L USP Destination ISA _B USP MOVE to SR lt ea gt y SR W Source SR Dy or lt data gt source only ISA_A MOVE to USP Ay USP L Source USP ISA B MOVEC Ry Re L Ry gt Re ISA_A RTE none none 2 SP SR 4 SP PC SP 8 SP ISA_A Adjust stack according to format STOP lt data gt none Immediate Data SR STOP ISA_A WDEBUG lt ea gt y L Addressed Debug WOMREG Command Executed ISA_A 1 Supported starting with V4 on devices containing an MMU M MOTOROLA Chapter 3 Instruction Set Summary 3 17 Instruction Set Additions Table 3 16 summarizes the additional instructions for the ISA_B instruction set Table 3 16 ColdFire ISA _B Additions Summary 1 bit 7 of Destination Operand 3 Super Instruction Operand Syntax Size Operation User Bee lt label gt B W L If Condition True Then PC d PC User BRA lt label gt B W L PC d PC User BSR lt label gt B W L SP 4 gt SP PC gt SP PC d PC User CMP lt ea gt y Dx B W L Destination Source cc User CMPA lt ea
89. is affected by instructions such as the LINK UNLK RTE and PEA To maximize performance A7 must be longword aligned at all times Therefore when modifying A7 be sure to do so in multiples of 4 to maintain alignment To further ensure alignment of A7 during exception handling the ColdFire architecture implements a self aligning stack when processing exceptions Users can employ other address registers to implement other stacks using the address register indirect with postincrement and predecrement addressing modes With an address register users can implement a stack that fills either from high memory to low memory or vice versa Users should keep in mind these important directives 2 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Stack e Use the predecrement mode to decrement the register before using its contents as the pointer to the stack e Use the postincrement mode to increment the register after using its contents as the pointer to the stack e Maintain the stack pointer correctly when byte word and longword items mix in these stacks To implement stack growth from high memory to low memory use An to push data on the stack and An to pull data from the stack For this type of stack after either a push or a pull operation the address register points to the top item on the stack LOW MEMORY FREE An TOP OF STACK e E e BOTTOM OF STACK HIGH MEMORY Figure 2 15 Stack
90. is evaluated as if it were the equivalent IEEE aware conditional predicate No exceptions are taken Enabled The processor takes a floating point pre instruction exception INAN Disabled If the destination data format is single or double precision a NAN is generated with a mantissa of all ones and a sign of zero transferred to the destination If the destination data format is B W or L a constant of all ones is written to the destination Enabled The result written to the destination is the same as the exception disabled case unless the exception occurs on a FMOVE OUT in which case the destination is unaffected 7 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions Table 7 5 FPCR EXC Byte Exception Enabled Disabled Results Continued EXC Bit Exception Description IDE Disabled The operand is treated as zero INEX is set and processing continues Enabled If an operand is denormalized an IDE exception is taken but INEX is not set so that the handler can set INEX appropriately The destination is overwritten with the same value as if IDE were disabled unless the exception occurred on a FMOVE OUT in which case the destination is unaffected OPERR Disabled When the destination is a floating point data register the result is a double precision NAN with its mantissa set to all ones and the sign set to zero positive For a FMOVE OUT instruction w
91. may optionally contain the 2 byte address of the instruction to which control is to be passed If this address is not specified the first entry point specification encountered in the object module input will be used There is no code data field Each block of S records uses only one termination record S7 and S8 records are only active when control passes to a 3 or 4 byte address otherwise an S9 is used for termination A 2 ColdFire Family Programmer s Reference Manual M MOTOROLA S Record Creation Normally there is only one header record although it is possible for multiple header records to occur A 3 S Record Creation Dump utilities debuggers or cross assemblers and linkers produce S record format programs Programs are available for downloading or uploading a file in S record format from a host system to a microprocessor based system A typical S record format module is printed or displayed as follows 00600004844521B 1130000285F245F2212226A000424290008237C2A S11300100002000800082629001853812341001813 S113002041E900084E42234300182342000824A952 S107003000144ED492 S9030000FC The module has an SO record four S1 records and an S9 record The following character pairs comprise the S record format module S0 Record SO S record type SO indicating that it is a header record 06 Hexadecimal 06 decimal 6 indicating that six character pairs or ASCII bytes follow 0000 A 4 character 2 byte add
92. mororoLA Chapter 2 Addressing Capabilities 2 3 Effective Addressing Modes Generation EA An Assembler Syntax An EA Mode Field 010 EA Register Field Register number Number of Extension Words 0 31 0 Address Register Operand Pointer Points to Memory Operand Figure 2 5 Address Register Indirect 2 2 4 Address Register Indirect with Postincrement Mode In the address register indirect with postincrement mode the operand is in memory The effective address field specifies the address register containing the address of the operand in memory After the operand address is used it is incremented by one two or four depending on the size of the operand 1 e byte word or longword respectively Note that the stack pointer A7 is treated exactly like any other address register Generation EA An An An Size Assembler Syntax An EA Mode Field 011 EA Register Field Register number Number of Extension Words 0 31 0 Address Register Contents Operand Length Size 1 2 or 4 31 0 Operand Pointer Contents Points to Memory J Operand Figure 2 6 Address Register Indirect with Postincrement 2 2 5 Address Register Indirect with Predecrement Mode In the address register indirect with predecrement mode the operand is in memory The effective address field specifies the address register containing the address of
93. number e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax d45 PC dg Ax Xi 110 reg number Ax dg PC Xi 4 16 ColdFire Family Programmer s Reference Manual M MOTOROLA BCLR Test a Bit and Clear BCLR All ColdFire Processors Operation lt bit number gt of Destination CCR Z 0 lt bit number gt of Destination Assembler Syntax BCLR sz Dy lt ea gt x BCLR sz lt data gt lt ea gt x Attributes Size byte longword Description Tests a bit in the destination operand and sets CCR Z appropriately then clears the specified bit in the destination When a data register is the destination any of the 32 bits can be specified by a modulo 32 bit number When a memory location is the destination the operation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate
94. of the data register Condition X N Z Vv C X Not affected Codes 0 0 N Set if result is negative cleared otherwise s Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 0 0 Opmode 0 0 0 Register Dx Instruction Fields e Opmode field Specifies the size of the sign extension operation 10 sign extend low order byte of data register to word 11 sign extend low order word of data register to longword 111 sign extend low order byte of data register to longword e Register field Specifies the data register Dx to be sign extended M mororoLA Chapter 4 Integer User Instructions 4 35 ILLEGAL Take Illegal Instruction Trap ILLEGAL All ColdFire Processors Operation SP 4 gt SP PC SP forcing stack to be longword aligned SP 2 gt SP SR SP SP 2 gt SP Vector Offset SP VBR 0x10 PC Assembler Syntax ILLEGAL Attributes Unsized Description Execution of this instruction causes an illegal instruction exception The opcode for ILLEGAL is Ox4AFC Starting with V4 for devices which have an MMU the Supervisor Stack Pointer SSP is used for this instruction Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 5 i 4 Formats Ora ei IE OT AE EE VAE AAT AI eo 0
95. operations the MASK contents can optionally be included in all memory effective address calculations 1 5 Supervisor Programming Model System programmers use the supervisor programming model to implement operating system functions All accesses that affect the control features of ColdFire processors must be made in supervisor mode The following paragraphs briefly describe the supervisor registers which can be accessed only by privileged instructions The supervisor programming model consists of the registers available to users as well as the registers listed in Figure 1 14 M MOTOROLA Chapter 1 Introduction 1 11 Supervisor Programming Model 31 19 15 0 SR Status register OTHER_A7 Supervisor A7 stack pointer Must be zeros VBR Vector base register CACR Cache control register ASID Address space ID register ACRO Access control register 0 data ACR1 Access control register 1 data ACR2 Access control register 2 instruction ACR3 Access control register 3 instruction MMUBAR MMU base address register ROMBARO ROM base address register 0 ROMBAR1 ROM base address register 1 RAMBARO RAM base address register 0 RAMBAR1 RAM base address register 1 MBAR Module base address register Figure 1 14 Supervisor Programming Model Note that not all registers are implemented on every ColdFire device refer to Table 1 6 Future devices will implement registers that are not implemented on cur
96. possible except dg Ax Xi xxx W xxx L MOVE V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported B W L B W L except including MOVE sz lt data gt di6 Ax MOVE B W lt data gt d46 AX M MOTOROLA Chapter 4 Integer User Instructions 4 45 MOVEA Move Address from Source to Destination MOV EA All ColdFire Processors Operation Source Destination Assembler Syntax MOVEA sz lt ea gt y Ax Attributes Size word longword Description Moves the address at the source to the destination address register The size of the operation may be specified as word or longword Word size source operands are sign extended to 32 bit quantities before the operation is done Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 Size Destination 0 0 1 Source Effective Address Register Ax Mode Register Instruction fields e Size field Specifies the size of the operand to be moved Ox reserved 11 word operation 10 longword operation e Destination Register field Specifies the destination address register Ax e Source Effective Address field Specifies the source operand lt ea gt y the table below lists possible modes Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000
97. register Format byte word longword single precision double precision FADD rounds the result to the precision selected in FPCR FSADD and FDADD round the result to single or double precision respectively regardless of the rounding precision selected in FPCR Operation ae Source Destination Table In Range Zero Infinity manag SE Add Add inf inf 2 SPTO i Add ee a inf inf Infinity inf inf inf NAN inf inf NANS inf 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number 2 Returns 0 0 in rounding modes RN RZ and RP returns 0 0 in RM 3 Sets the OPERR bit in the FPSR exception byte FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 Set if source and destination See Table 7 2 0 See are opposite signed infinities Table 7 2 cleared otherwise FPSR AEXC See Section 7 1 Floating Point Status Register FPSR M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 11 Instruction Descriptions FADD Floating Point Add FADD Instruction 15 14 13 12 11 10 9 7 6 5 4 3 1 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx Instruction fields e Source Effective Address field Determines the addre
98. source operand to the status register The source operand is a word and all implemented bits of the status register are affected Note that this instruction synchronizes the pipeline Condition X Codes N Z V C Instruction 15 Format Instruction Field O lt NZX Set to the value of bit 4 of the source operand Set to the value of bit 3 of the source operand Set to the value of bit 2 of the source operand Set to the value of bit 1 of the source operand Set to the value of bit 0 of the source operand 8 7 6 5 4 3 2 1 0 0 0 1 1 Source Effective Address Mode Register e Effective Address field Specifies the location of the source operand use only those data addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay lt data gt 111 100 Ay lt Ay d16 Ay 5 d1g PC dg Ay Xi dg PC Xi M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 11 MOVE to USP Move to User Stack Pointer Supported Starting with V4 Operation If Supervisor State Then Source USP Else Privilege Violation Exception Assembler Syntax MOVE L Ay USP Attributes Size longword MOVE to USP Description Moves the contents o
99. specifies a bit number that selects one bit the bit operand in the base byte The msb of the byte is 7 7 0 7 0 7 0 7 0 Byte n 1 7654 ale 10 Byte n 1 Byte n 2 Bit Data A Base Address Bit Number 7 0 7 0 7 0 7 0 Byte n 1 msb Byten Isb Byte n 1 Byte n 2 Byte Data Address 7 0 15 017 0 7 0 Byte n 1 msb Word Integer Isb Byte n 2 Byte n 3 Word Data A Address 7 0 31 0 7 0 Byte n 1 msb Longword Integer Isb Byte n 4 Longword A Data Address Figure 1 28 Memory Organization for Integer Operands 1 22 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 2 Addressing Capabilities Most operations compute a source operand and destination operand and store the result in the destination location Single operand operations compute a destination operand and store the result in the destination location External microprocessor references to memory are either program references that refer to program space or data references that refer to data space They access either instruction words or operands data items for an instruction Program space is the section of memory that contains the program instructions and any immediate data operands residing in the instruction stream Data space is the section of memory that contains the program data The program counter relative addressing modes can be classified as data references 2 1 Instruction Format ColdFire Family
100. tests The other 16 do not cause an exception IEEE aware tests The set of IEEE nonaware tests is best used in one of the following cases e When porting a program from a system that does not support the IEEE standard to a conforming system e When generating high level language code that does not support IEEE floating point concepts that is the unordered condition An unordered condition occurs when one or both of the operands in a floating point compare operation is a NAN The inclusion of the unordered condition in floating point branches destroys the familiar trichotomy relationship greater than equal less than that exists for integers For example the opposite of floating point branch greater than FBGT 7 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Conditional Testing is not floating point branch less than or equal FBLE Rather the opposite condition is floating point branch not greater than FBNGT If the result of the previous instruction was unordered FBNGT is true whereas both FBGT and FBLE would be false because unordered fails both of these tests and sets BSUN Because it is common for compilers to invert the sense of conditions compiler code generators should be particularly careful of the lack of trichotomy in the floating point branches When using the IEEE nonaware tests the user receives a BSUN exception if a branch is attempted and FPCC NAN is set unless the branch is an FBEQ or an FB
101. the operand in memory Before the operand address is used it is decremented by one two or four depending on the operand size 1 e byte word or longword respectively Note that the stack pointer A7 is treated just like the other address registers 2 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Effective Addressing Modes Generation EA An Size An An Size Assembler Syntax An EA Mode Field 100 EA Register Field Register number Number of Extension Words 0 31 0 Address Register Contents Operand Length Size MEN 1 2 or 4 31 y 0 Operand Pointer Contents Points to Memory Operand Figure 2 7 Address Register Indirect with Predecrement 2 2 6 Address Register Indirect with Displacement Mode In the address register indirect with displacement mode the operand is in memory The operand address in memory consists of the sum of the address in the address register which the effective address specifies and the sign extended 16 bit displacement integer in the extension word Displacements are always sign extended to 32 bits prior to being used in effective address calculations Generation EA An dig Assembler Syntax d4g An EA Mode Field 101 EA Register Field Register number Number of Extension Words 1 31 0 Address Register Contents 31 15 0 Displacement Sign Extension Integer 31 0 Opera
102. the processor operating mode as shown in the following if SR S 1 then A7 Supervisor Stack Pointer other_A7 User Stack Pointer else A7 User Stack Pointer other_A7 Supervisor Stack Pointer M mororoLA Chapter 1 Introduction 1 13 Supervisor Programming Model 1 5 3 Vector Base Register VBR The vector base register contains the 1 MByte aligned base address of the exception vector table in memory The displacement of an exception vector adds to the value in this register which accesses the vector table VBRI 19 0 are filled with zeros 31 20 19 0 Exception vector table base address Figure 1 16 Vector Base Register VBR 1 5 4 Cache Control Register CACR The CACR controls operation of both the instruction and data cache memory It includes bits for enabling freezing and invalidating cache contents It also includes bits for defining the default cache mode and write protect fields Bit functions and positions may vary among ColdFire processor implementations Refer to a specific device or core user s manual for further information 1 5 5 Address Space Identifier ASID Only the low order 8 bits of the 32 bit ASID register are implemented The ASID value is an 8 bit identifier assigned by the operating system to each process active in the system It effectively serves as an extension to the 32 bit virtual address Thus the virtual reference now becomes a 40 bit value the 8 bit ASID concate
103. to the destination is the same as the exception disabled case unless the enabled exception occurs on a FMOVE OUT in which case the destination is unaffected 11 1 7 Input Denormalized Number IDE The input denorm bit FPCR IDE provides software support for denormalized operands When the IDE exception is disabled the operand is treated as zero FPSR INEX is set and the operation proceeds When the IDE exception is enabled and an operand is M MOTOROLA Chapter 11 Exception Processing 11 11 Overview denormalized an IDE exception is taken but FPSR INEX is not set to allow the handler to set it appropriately See Table 11 7 Note that the FPU never generates denormalized numbers If necessary software can create them in the underflow exception handler Table 11 7 IDE Exception Enabled Disabled Results Condition IDE Description Exception 0 Any denormalized operand is treated as zero FPSRIINEX is set and the operation proceeds disabled Exception 1 The result written to the destination is the same as the exception disabled case unless the enabled exception occurs on a FMOVE OUT in which case the destination is unaffected FPSR INEX is not set to allow the handler to set it appropriately 11 1 8 Operand Error OPERR The operand error exception encompasses problems arising in a variety of operations including errors too infrequent or trivial to merit a specific exceptional c
104. 0 0 1 0 0 0 0 1 Source Effective Address Mode Register EXT EXTB 0x4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 Opmode 0 0 0 Register Dx MOVEM 0x4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 dr 0 0 1 1 Effective Address Mode Register Register List Mask M MOTOROLA Chapter 9 Instruction Format Summary 9 5 Operation Code Map TST 0x4A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 Size Destination Effective Address Mode Register TAS 0x4A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 1 1 Destination Effective Address Mode Register HALT 0x4AC8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 PULSE Ox4ACC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 ILLEGAL 0x4AFC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 0 0 MULU L 0x4C 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 0 0 0 0 Source Effective Address Mode Register 0 Register Dx 0 0 0 0 0 0 0 0 0 0 0 0 MULS L 0x4C 800 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0
105. 0 1 1 0 0 0 0 0 0 0 FMOVEM OxF2 0 15 14 13 12 11 10 4 3 2 1 0 1 1 1 1 0 0 Effective Address Mode Register 1 1 dr 1 0 0 Register List 9 18 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map FNOP OxF280 0000 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSAVE OxF3 15 14 13 12 11 10 9 8 6 4 3 2 1 0 1 1 1 1 0 0 1 1 0 0 Destination Effective Address Mode Register FRESTORE OxF3 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 1 1 1 1 0 0 1 1 0 1 Source Effective Address Mode Register INTOUCH OxF42 15 14 13 12 11 10 8 7 6 4 3 2 1 0 1 1 1 1 0 1 0 0 0 0 0 1 Register Ax CPUSHL OxF4 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 1 1 1 1 0 1 0 0 Cache 0 1 Register Ax WDDATA OxFB 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 1 1 1 1 1 0 1 1 Size Source Effective Address Mode Register WDEBUG OxFB 0003 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 1 1 1 1 1 0 1 1 1 1 Source Effective Address Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 M MOTOROLA Chapter 9 Instruction Format Summary 9 19 Operation Code Map 9 20 ColdFi
106. 01 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 Instruction 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Format 0 1 0 1 1 0 0 Source Effective Address Longword Mode Register 0 Register Dx 0 0 0 0 0 0 0 0 Register Dx Instruction Fields Longword e Register field Specifies the destination register Dx Note that this field appears twice in the instruction format e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi 4 32 ColdFire Family Programmer s Reference Manual M MOTOROLA EOR Exclusive OR Logical EOR All ColdFire Processors Operation Source Destination Destination Assembler Syntax EOR L Dy lt ea gt x Attributes Size longword Description Performs an exclusive OR operation on the destination operand using the source operand and stores the result in the destination location The size of the operation is specified as a longword The source operand must be a data register The destination operand is specified in th
107. 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 M mororoLA Chapter 6 EMAC User Instructions 6 13 MOVE MOVE ACC to ACC Copy an ACC to ACC Accumulator Operation Source Accumulator Destination Accumulator Assembler syntax MOVE L ACCy ACCx Attributes Size longword Description Moves the 48 bit source accumulator contents and its associated PAV flag into the destination accumulator This operation is fully pipelined within the EMAC so no pipeline stalls are associated with it This instruction provides better performance than the two step process of moving an accumulator to a general purpose register Rn then moving Rn into the destination accumulator Condition N Z V PAVx EV N Set if the msb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if PAVy 1 cleared otherwise MACSR PAVx Set to the value of the source PAVy flag EV Setif the source accumulator overflows lower 32 bits in integer mode or lower 40 bits in fractional mode cleared otherwise Instruction 15 14 13 12 EF 10 9 8 7 6 5 4 E 2 1 0 Format 1 0 1 o o ACCx 1 0 0 0 1 o 0 ACCy Instruction Fields e ACCx Specifies the destination accumulator The value of bits 10 9 specify the accumulator number e ACCy Specifies the source accumulator The value of bits 1 0 specify the accumulator number 6 14 ColdFire Family Programmer s Reference Manual M MOTOROLA
108. 1 ACCext23 1 11 Address register direct mode 2 3 general AO A7 1 2 indirect mode displacement 2 5 postincrement 2 4 predecrement 2 4 regular 2 3 scaled index and 8 bit displacement 2 6 Address space identifier ASID 1 14 B Bit manipulation instructions 3 8 Branch set on unordered BSUN 11 11 C Cache control register CACR 1 14 maintenance instructions 3 10 Condition code register CCR 1 2 Conditional testing 7 3 D Data formats and type summary 1 18 multiply accumulate 1 20 Data movement instructions 3 4 Data register direct mode 2 3 general D0 D7 1 2 Data immediate 2 9 Divide by zero DZ 11 14 E EMAC accumulators 1 9 user instructions 6 1 6 24 user programming model 1 8 Exception processing model V4 changes 11 15 Exception stack frame definition 11 4 M MOTOROLA INDEX Exceptions floating point arithmetic 11 9 processor 11 5 F Floating point arithmetic exceptions 11 9 arithmetic instructions 3 11 control register FPCR 1 4 data formats 1 16 data registers FPO FP7 1 4 data types denormalized numbers 1 18 not a number 1 18 zeros 1 17 instruction address register FPIAR 1 6 descriptions 7 9 7 43 status register FPSR 1 5 7 1 Formats floating point data 1 16 integer data 1 16 FPU user programming model 1 4 Inexact result INEX 11 14 Infinities 1 17 Input denormalized number 11 11 not a number INAN 11 11 Instruct
109. 1 0 Figure 1 24 Two s Complement Signed Fractional Equation This format can represent numbers in the range 1 lt operand lt 1 ZEND For words and longwords the largest negative number that can be represented is 1 whose internal representation is 0x8000 and 0x8000 0000 respectively The largest positive word is Ox7FFF or 1 2 the most positive longword is 0x7FFF_FFFF or 1 Ze 1 9 Organization of Data in Registers This section describes data organization within the data address and control registers 1 9 1 Organization of Integer Data Formats in Registers Each integer data register is 32 bits wide Byte and word operands occupy the lower 8 and 16 bit portions of integer data registers respectively Longword operands occupy entire data registers A data register that is either a source or destination operand only uses or 1 20 ColdFire Family Programmer s Reference Manual M MOTOROLA Organization of Data in Registers changes the appropriate lower 8 or 16 bits in byte or word operations respectively The remaining high order portion does not change and is unused and unchanged The address of the least significant bit lsb of a longword integer is zero and the most significant bit msb is 31 Figure 1 25 illustrates the organization of integer data in data registers 31 30 1 0 msb Isb Bit 0 lt bit number lt 31 31 8 7 6 1 0 Not used msb Low order byte Isb Byte 8 bit
110. 1 0 0 1 1 0 0 0 0 Source Effective Address Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 0 0 0 0 DIVU L 0x4C 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 0 0 0 1 Source Effective Address Mode Register 0 Register Dx 0 0 0 0 0 0 0 0 0 Register Dx 9 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map REMU L 0x4C 00 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 0 0 0 1 Source Effective Address Mode Register 0 Register Dx 0 0 0 0 0 0 0 0 Register Dw DIVS L 0x4C 80 15 14 13 12 11 10 8 7 6 4 3 2 1 0 0 1 0 0 1 1 0 0 0 1 Source Effective Address Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 Register Dx REMS L 0x4C 80 15 14 13 12 11 10 8 7 6 4 3 2 1 0 0 1 0 0 1 1 0 0 0 1 Source Effective Address Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 Register Dw SATS 0x4C8 15 14 13 12 11 10 8 7 6 4 3 2 1 0 0 1 0 0 1 1 0 0 1 0 0 0 Register Dx TRAP 0x4E4 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 Vector LINK 0x4E5 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 0 Register Ay Word Displace
111. 1 0 1 Destination Effective Address Mode Register BCLR 0x0 Bit number dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Data Register Dy 1 1 0 Destination Effective Address Mode Register BSET 0x0 Bit number dynamic specified in a register 15 14 13 12 11 10 9 5 4 3 2 1 0 Data Register Dy Destination Effective Address Effective Address ANDI 0x028 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data SUBI 0x048 Register Dx Upper Word of Immediate Data ColdFire Family Programmer s Reference Manual Lower Word of Immediate Data M MOTOROLA Operation Code Map ADDI 0x068 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data BTST 0x08 00 Bit number static specified as immediate data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 0 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number BCHG 0x08 00 Bit number static specified as immediate data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0
112. 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 For the destination operand lt ea gt x use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx ox W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi M mororoLA Chapter 4 Integer User Instructions 4 73 SUBA Operation Subtract Address All ColdFire Processors Assembler Syntax SUBA L lt ea gt y Ax Attributes Size longword Destination Source Destination SUBA Description Operates similarly to SUB but is used when the destination is an address register rather than a data register Subtracts the source operand from the destination address register and stores the result in the address register The size of the operation is specified as a longword Condition Codes Not affected Instruction 15 14 Format 1 0 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 Destination 1 1 1 Source Effective Address Register Ax Mode Register Instruction Fields e Destination Register field Specifies the destination address register Ax e Source Effective Address field Specifies th
113. 2 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 Register Dx MOVE from SR 0x40C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 Register Dx LEA 0x4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 Register Ax 1 1 1 Source Effective Address Mode Register CLR 0x42 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 Size Destination Effective Address Mode Register MOVE from CCR 0x42C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 Register Dx 9 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map NEG 0x448 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 Register Dx MOVE to CCR 0x44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 0 1 1 Source Effective Address Mode Register NOT 0x468 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 Register Dx MOVE to SR 0x46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 0 1 1 Source Effective Address Mode Register SWAP 0x484 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 Register Dx PEA 0x48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1
114. 7 0 23 16 ACCext2 15 8 15 8 ACCext2 7 0 7 0 MACSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 loli o 1 1 1 1 1 lololo Register Rx Instruction Field e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 M mororoLA Chapter 6 EMAC User Instructions 6 11 MOVE MOVE from MACSR Move from the from MACSR MACSR Operation MACSR Destination Assembler Syntax MOVE L MACSR Rx Attributes Size longword Description Moves the MACSR register contents into a general purpose register Rx Rx 31 12 are cleared MACSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 0 0 1 1 0 0 0 Register Rx Instruction Field e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 6 12 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE MOVE from MASK Move from the from MASK MAC MASK Register Operation MASK Destination Assembler Syntax MOVE L MASK Rx Attributes Size longword Description Moves the MASK register contents into a general purpose register Rx Rx 31 16 are set to OxFFFF MACSR Not affected Instruction 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 1 0 1 1 0 0 0 Register Rx Instruction Field e Register Rx field Specifies a source register operand where
115. 7 0 if Temp 47 39 0x00_0 or OxFF_1 then Temp 39 8 Rx else if Temp 47 0 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx 6 8 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE MOVE from ACC Move from an from ACC Accumulator if MACSR OMC S U 11 saturation 16 bit rounding Temp 47 24 ACC 47 24 rounded by the contents of 23 0 if Temp 47 39 0x00_0 or OxFF_1 then 0 Rx 31 16 Temp 39 24 Rx 15 0 else if Temp 47 then 0x0000_7FFF Rx else 0x0000_8000 Rx 0 ACCx ACCextx MACSR PAVx Condition N Z V PAVx EV N Not affected Codes Z Not affected V Not affected MACSR PAVx Not affected EV Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 E 2 1 0 Format 1 OF l1 o 0 ACC 1 1 olo 0 Register Rx Instruction Fields e ACC Specifies the destination accumulator The value of bits 10 9 specify the accumulator number e Register Rx field Specifies a destination register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 M MOTOROLA Chapter 6 EMAC User Instructions 6 9 MOVE from MOVE from ACCext01 Move from Accumulator ACCext01 0 and 1 Extensions Operation Accumulator 0 and 1 extension words Destination Assembler syntax MOVE L ACCext01 Rx Attributes Size longword Description Moves the contents of the four extension bytes associated with accumulators 0 and 1 into a gener
116. ACC Ry Rx lt lt gt gt SF ACC User Ry RxSF lt ea gt y Rw W L ACC Ry Rx lt lt gt gt SF ACC ACC lt ea gt y amp MASK Rw MOVE MACcr Dx L Source Destination User lt ea gt y MACcr L where MACcr can be any MAC control register ACC MACSR MASK MSAC Ry RxSF ACC W L ACC Ry Rx lt lt gt gt SF ACC User Ry RxSF lt ea gt y Rw W L ACC Ry Rx lt lt gt gt SF ACC ACC lt ea gt y amp MASK Rw Table 3 18 summarizes the changes to the instruction set due to the enhancements in the EMAC unit Table 3 18 EMAC Instruction Set Enhancements Summary Operand Super Instruction Operand Syntax Size Operation User MAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx User Ry RxSF lt ea gt y Rw W L ACCx Ry Rx lt lt gt gt SF ACCx ACCx lt ea gt y amp MASK Rw MOVCLR ACCy Rx L Accumulator Destination 0 Accumulator User MOVE MACcr Dx L Source Destination User lt ea gt y MACcr L where MACcr can be any MAC control register ACCx ACCext01 ACCext23 MACSR MASK MSAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx User Ry RxSF lt ea gt y Rw W L ACCx Ry Rx lt lt gt gt SF ACCx ACCx lt ea gt y amp MASK Rw 1 The EMAC has 4 accumulators M MOTOROLA Chapter 3 Instruction Set Summary 3 19 Instruction Set Additions Table 3 19 summari
117. ASK Register Ry field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 6 Enhanced Multiply Accumulate Unit EMAC User Instructions This chapter describes the user instructions for the optional enhanced multiply accumulate EMAC unit in the ColdFire family of processors A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic For instructions implemented by the Multiply Accumulate Unit MAC refer to Chapter 5 Multiply Accumulate Unit MAC User Instructions M MOTOROLA Chapter 6 EMAC User Instructions 6 1 MAC Multiply Accumulate MAC Operation ACCx Ry Rx lt lt gt gt SF ACCx Assembler syntax MAC sz Ry U L Rx U L SKACCx Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 40 bit result then add this product shifted as defined by the scale factor to an accumulator If 16 bit operands are used the upper or lower word of each register must be specified Condition N Z V PAVX EV N Set if the msb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if a product or accumulation overflow is MACSR generated or PAVx 1 cleared otherwise PAVx Set if a product or accumulation overflow is generated unchanged o
118. At this point operations performed in the first cycle are complete so 1f the destination write takes any type of access error Ay is updated After the access error handler executes and the faulting instruction restarts the processor s operation is incorrect because the source address register has an incorrect post incremented value To recover the original state of the programming model for all instructions the V4 core adds the needed hardware to support full register recovery This hardware allows program visible registers to be restored to their original state for multi cycle instructions so that the instruction restart mechanism is supported Memory to memory moves and move multiple loads are representative of the complex instructions needing the special recovery support 11 16 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 12 Processor Instruction Summary This chapter provides a quick reference of the ColdFire instructions Table 12 2 lists the ColdFire instructions by mnemonic the descriptive name and the cores that support them The Version 2 and 3 cores V2 and V3 support ISA_A and the Version 4 core V4 supports ISA_B Table 12 3 lists the instructions supported by the optional MAC unit both fractional and integer only and the optional enhanced MAC unit EMAC Table 12 4 lists the instructions supported by the optional floating point unit FPU The standard products available at the tim
119. B W L Destination Immediate Data CCR ISA_A DIVS DIVU lt ea gt y Dx W L Destination Source Destination ISA_A Signed or Unsigned EOR Dy lt ea gt x L Source Destination Destination ISA_A EORI lt data gt Dx L Immediate Data Destination Destination ISA_A EXT Dx B W Sign Extended Destination Destination ISA_A Dx W gt L EXTB Dx BoL FABS lt ea gt y FPx B W L S D Absolute Value of Source FPx FPU FPy FPx D FPx D Absolute Value of FPx FPx FADD lt ea gt y FPx B W L S D Source FPx FPx FPU FPy FPx D FBcc lt label gt W L If Condition True Then PC d PC FPU FCMP lt ea gt y FPx B W L S D FPx Source FPU FPy FPx D FDABS lt ea gt y FPx B W L S D Absolute Value of Source FPx round FPU FPy FPx D destination to double FPx D Absolute Value of FPx FPx round destination to double FDADD lt ea gt y FPx B W L S D Source FPx FPx round destination to double FPU FPy FPx D FDDIV lt ea gt y FPx B W L S D FPx Source FPx round destination to double FPU FPy FPx D M MOTOROLA Chapter 3 Instruction Set Summary 3 13 Instruction Set Additions Table 3 14 ColdFire User Instruction Set Summary Continued Instruction Operand Syntax eee Operation ISA FDIV lt ea gt y FPx B W L S D FPx Source FPx FPU FPy FPx D FDMOVE FPy FPx D Source Destination round destination to double FPU FDMUL
120. C Move from Accumulator X X MOVE from ACCext01 Move from Accumulator 0 and 1 X Extensions MOVE from ACCext23 Move from Accumulator 2 and 3 X Extensions MOVE from MACSR Move from MAC Status Register X X MOVE from MACSR to Move from MAC Status Register to X X CCR Condition Code Register MOVE from MASK Move from MAC Mask Register MOVE to ACC Move to Accumulator X MOVE to ACCext01 Move to Accumulator 0 and 1 Extensions MOVE to ACCext23 Move to Accumulator 2 and 3 X Extensions MOVE to MACSR Move to MAC Status Register MOVE to MASK Move to MAC Mask Register X X MSAC Multiply and Subtract 12 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Table 12 4 ColdFire FPU Instruction Set Mnemonic Description FABS FSABS FDABS Floating Point Absolute Value FADD FSADD FDADD Floating Point Add FBcc Floating Point Branch Conditionally FCMP floating Point Compare FDIV FSDIV FDDIV FINT FSINT FDINT Floating Point Divide Floating Point Integer FINTRZ Floating Point Integer Round to Zero FMOVE FSMOVE FDMOVE Move Floating Point Data Register FMOVE from FPCR Move from the Floating Point Control Register FMOVE from FPIAR Move from the Floating Point Instruction Address Register FMOVE from FPSR FMOVE to FPCR Move from the Floating Point Status Register Move to the Floating Point Control Register FMOVE to FPIAR Mov
121. CCR V and CCR Z respectively Code Condition Encod Test Code Condition Encod Test ing ing CC HS Carry clear 0100 C LS Lower or same 0011 CIZ CS LO Carry set 0101 C LT Less than 1101 N amp VIN amp V EQ Equal 0111 Z MI Minus 1011 N F False 0001 NE Not equal 0110 Z GE Greater or equal 1100 N amp VIN amp V PL Plus 1010 N GT Greater than 1110 N amp V amp ZIN amp VEZ T True 0000 1 HI High 0010 C amp Z VC Overflow clear 1000 V LE Less or equal 1111 ZIN amp VIN amp V VS Overflow set 1001 V Condition Codes Not affected Instruction 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 Format o l1 0 l1 Condition 1 1 0 lo 0 Register Dx Instruction Fields e Condition field Binary code for one of the conditions listed in the table e Register field Specifies the destination data register Dx M MOTOROLA Chapter 4 Integer User Instructions 4 71 SUB Operation Subtract All ColdFire Processors Destination Source Destination Assembler Syntax SUB L lt ea gt y Dx SUB L Dy lt ea gt x Attributes Size longword SUB Description Subtracts the source operand from the destination operand and stores the result in the destination The size of the operation is specified as a longword The mode of the instruction indicates which operand is the source and which is the destination The Dx mode is used when the destination is
122. Chapter 7 Floating Point Unit FPU User Instructions 7 5 Instruction Results when Exceptions Occur Table 7 4 Floating Point Conditional Tests Continued Mnemonic Definition Equation Predicate EXC BSUN Set ULE Unordered or less or equal NAN Z N 001101 No OGE Ordered greater than or equal Z NAN IN 000011 No ULT Unordered or less than NAN N amp Z 001100 No Ordered less than NAN Z 000100 Unordered or greater or equal 001011 Ordered less than or equal 000101 Unordered or greater than 001010 Ordered greater or less than 000110 Unordered or equal 001001 Ordered NAN 000111 Unordered 001000 000000 T True True 001111 No SF Signaling false False 010000 Yes ST Signaling true True 011111 Yes SEQ Signaling equal Z 010001 Yes SNE Signaling not equal Z 011110 Yes 1 This column refers to the value in the instructions conditional predicate field that specifies this test 7 3 Instruction Results when Exceptions Occur Instruction execution results may be different depending on whether exceptions are enabled in the FPCR as shown in Table 7 5 An exception is enabled when the value of the EXC bit is 1 disabled when the value is 0 Note that if an exception is enabled and occurs on a FMOVE OUT the destination is unaffected Table 7 5 FPCR EXC Byte Exception Enabled Disabled Results EXC Bit Exception Description BSUN Disabled The floating point condition
123. ColdFire Family Programmer s Reference Manual CFPRM D Rev 2 07 2001 DE Di gitalDN A 68KoldFIRE M MOTOROLA am Motorola ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola Inc PC isa registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motoro
124. Cx ACCx lt ea gt y amp MASK Rw M MOTOROLA Chapter 3 Instruction Set Summary 3 15 Instruction Set Additions Table 3 14 ColdFire User Instruction Set Summary Continued Instruction Operand Syntax Lu Operation ISA MULS MULU lt ea gt y Dx W W L Source Destination Destination ISA_A L L L Signed or Unsigned MVS lt ea gt y Dx B W Source with sign extension Destination ISA _B MVZ lt ea gt y Dx B W Source with zero fill Destination ISA_B NEG Dx L 0 Destination Destination ISA_A NEGX Dx L 0 Destination CCR X Destination ISA_A NOP none none PC 2 PC Integer Pipeline Synchronized ISA_A NOT Dx L Destination Destination ISA _A OR lt ea gt y Dx L Source Destination Destination ISA_A Dy lt ea gt x L ORI lt data gt Dx L Immediate Data Destination Destination ISA_A PEA lt ea gt y L SP 4 gt SP lt ea gt y SP ISA_A PULSE none none Set PST 0x4 ISA_A REMS REMU lt ea gt y Dw Dx L Destination Source Remainder ISA_A Signed or Unsigned RTS none none SP gt PC SP 4 gt SP ISA_A SATS Dx L If CCR V 1 ISA_B then if Dx 31 0 then Dx 31 0 0x80000000 else Dx 31 0 Ox7FFFFFFF else Dx 31 0 is unchanged Scc Dx B If Condition True Then 1s Destination ISA_A Else Os Destination SUB lt ea gt y Dx L Destination Source D
125. Destination Assembler Syntax MOVEQ L lt data gt Dx Attributes Size longword Description Moves a byte of immediate data to a 32 bit data register Dx The data in an 8 bit field within the operation word is sign extended to a longword operand in the data register as it is transferred Condition X N Z V C X Not affected Codes 0 0 N Set if result is negative cleared otherwise Z Setif the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 43 12 11 10 9 8 7 6 5 4 3 2 4 0 Format 0 1 1 1 Register Dx 0 Immediate Data Instruction Fields e Register field Specifies the data register Dx to be loaded e Data field 8 bits of data which are sign extended to a longword operand M mororoLA Chapter 4 Integer User Instructions 4 49 MOVE MOVE from CCR Move from the from CCR Condition Code Register All ColdFire Processors Operation CCR Destination Assembler Syntax MOVE W CCR Dx Attributes Size Word Description Moves the condition code bits zero extended to word size to the destination location Dx The operand size is a word Unimplemented bits are read as zeros Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 0 0 1 0 1 1 0 0 0 Register Dx Instruction Field e Register field Specifies destination data register Dx 4 50 ColdFire Family Programmer s Reference Manual
126. Destination Effective Address Mode Register Instruction Fields e Data Register field Specifies the data register Dy that contains the bit number e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax d45 PC dg Ax Xi 110 reg number Ax dg PC Xi 4 18 ColdFire Family Programmer s Reference Manual M MOTOROLA BRA Branch Always BRA All ColdFire Processors L supported starting with V4 Operation PC d PC Assembler Syntax BRA sz lt label gt Attributes Size byte word longword longword supported starting with V4 Description Program execution continues at location PC displacement Branches can be forward with a positive displacement or backward with a negative displacement The PC contains the address of the instruction word of the BRA instruction plus two The displacement is a two s complement integer that represents the relative distance in bytes from the current
127. F lt ea gt y Rw ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx lt ea gt y amp MASK Rw MSAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF gt ACCx Ry RxSF lt ea gt y Rw ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx lt ea gt y amp MASK Rw MULS MULU lt ea gt y Dx W Wo gt L Source Destination Destination L LoL Signed or Unsigned NEG Dx L 0 Destination Destination NEGX Dx L 0 Destination CCR X Destination REMS REMUS lt ea gt y Dw Dx L Destination Source Remainder Signed or Unsigned SATS Dx L If CCR V 1 then if Dx 31 0 then Dx 31 0 0x80000000 else Dx 31 0 Ox7FFFFFFF else Dx 31 0 is unchanged SUB lt ea gt y Dx L Destination Source Destination Dy lt ea gt x L SUBA lt ea gt y Ax L 3 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Summary Table 3 3 Integer Arithmetic Operation Format Continued SUBI lt data gt Dx L Destination Immediate Data Destination SUBQ lt data gt lt ea gt x L SUBX Dy Dx L Destination Source CCR X Destination Byte and word supported starting with V4 Word supported starting with V4 Supported starting with the 5206e The accumulator does not need to be specified on the original MAC unit Supported starting with V4 a fF wo N 3 1 3 Logical Instructions The instructions AND OR EOR and NOT perform logi
128. FFFFF else Dx 31 0 is unchanged Assembler Syntax SATS L Dx Attributes Size longword Description Update the destination register only if the overflow bit of the CCR is set If the operand is negative then set the result to greatest positive number otherwise set the result to the largest negative value The condition codes are set according to the result Not affected Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Always cleared Always cleared Condition X N Z V C Codes ae 0 0 O lt NZX Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 0 0 1 0 0 0 0 Register Dx Instruction Fields e Register field Specifies the destination data register Dx SATS V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported L 4 70 ColdFire Family Programmer s Reference Manual M MOTOROLA Scc Operation Set According to Condition All ColdFire Processors If Condition True Then 1s Destination Else Os Destination Assembler Syntax Scc B Dx Attributes Size byte Scc Description Tests the specified condition code if the condition is true sets the lowest byte of the destination data register to TRUE all ones Otherwise sets that byte to FALSE all zeros Condition code cc specifies one of the following conditional tests where C N V and Z represent CCR C CCR N
129. FPO FP7 e 32 bit floating point control register FPCR e 32 bit floating point status register FPSR e 32 bit floating point instruction address register FPIAR 63 31 0 FPO Floating point data registers FP1 FP2 FP3 FP4 FP5 FP6 FP7 FPCR Floating point control register FPSR Floating point status register FPIAR Floating point instruction address register Figure 1 3 ColdFire Family Floating Point Unit User Programming Model 1 2 1 Floating Point Data Registers FPO FP7 Floating point data registers are analogous to the integer data registers for the 68K ColdFire family The 64 bit floating point data registers always contain numbers in double precision format All external operands regardless of the source data format are converted to double precision values before being used in any calculation or being stored in a floating point data register A reset or a null restore operation sets FPO FP7 to positive nonsignaling not a numbers NANS 1 2 1 1 Floating Point Control Register FPCR The FPCR Figure 1 4 contains an exception enable byte EE and a mode control byte MC The user can read or write to FPCR using FMOVE or FRESTORE A processor reset or a restore operation of the null state clears the FPCR When this register is cleared the FPU never generates exceptions m Exception Enable Byte EE mM Mode Control Byte MC 31 16 15 14 13 12 11 10 9 8 7 6 5 4
130. FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 Set if source operand is co 0 0 0 See format B W or if destination size is Table 7 2 GET ee exceeded after conversion and rounding cleared otherwise format S or 0 See Table 7 2 0 D FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 t 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Destination Effective Address FPy lt ea gt x Mode Register 0 1 1 Destination Source Register 0 0 0 0 0 0 0 Format FPy Instruction fields e Destination Effective Address field Specifies the destination location lt ea gt x Only modes in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx ww Ax xxx L Ax 010 reg number Ax lt data gt En Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d45 PC 1 Only if format is byte word longword or single precision e Destination Format field Specifies the data format of the destination operand See Table 7 6 e Source Register field Specifies the source floating point data register FPy 7 24 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FMOVE FM
131. Family Programmer s Reference Manual M MOTOROLA AND AND Logical AND Instruction Fields continued e Effective Address field Determines addressing mode For the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 For the destination operand lt ea gt x use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx ox W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi M mororoLA Chapter 4 Integer User Instructions 4 9 ANDI AND Immediate ANDI All ColdFire Processors Operation Immediate Data amp Destination Destination Assembler Syntax ANDI L lt data gt Dx Attributes Size longword Description Performs an AND operation of the immediate data with the destination operand and stores the result in the destination data regis
132. Format 1 0 1 1 Destination Opmode Source Effective Address Register Dx Mode Register Instruction Fields e Register field Specifies the destination register Dx e Opmode field Byte Word Longword Operation 000 001 010 Dx lt ea gt y e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 CMP V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported L B W L 4 26 ColdFire Family Programmer s Reference Manual M MOTOROLA CMPA Compare Address CMPA All ColdFire Processors W supported starting with V4 Operation Destination Source cc Assembler Syntax CMPA sz lt ea gt y Ax Attributes Size word longword word supported starting with V4 Description Operates similarly to CMP but is used when the destination register is an address register rather than a data register The operation size can be word or longword Word length source operands are sign extended to 32 bits
133. Integer pipeline synchronized TPF none none PC 25 PC lt data gt W PC 4 PC lt data gt L PC 6 PC Pipeline not synchronized Returns RTS none none SP gt PC SP 4 SP Test Operand TAS lt ea gt X B Destination Tested CCR 1 bit 7 of Destination FTST lt ea gt y B W L S D Source Operand Tested FPCC TST lt ea gt y B W L Source Operand Tested CCR 1 Longword supported starting with V4 2 Supported starting with V4 Letters cc in the integer instruction mnemonics Bee and See specify testing one of the following conditions CC Carry clear GE Greater than or equal LS Lower or same PL Plus CS Carry set GT Greater than LT Less than T Always true EQ Equal HI Higher MI Minus VC Overflow clear F Never true LE Less than or equal NE Not equal VS Overflow set 1 Not applicable to the Bcc instructions For the definition of cc for FBcc refer to Section 7 2 Conditional Testing M mororoLA Chapter 3 Instruction Set Summary 3 9 Instruction Summary 3 1 7 System Control Instructions This type of instruction includes privileged and trapping instructions as well as instructions that use or modify the CCR FSAVE and FRESTORE save and restore the nonuser visible portion of the FPU during context switches Table 3 8 summarizes these instructions Table 3 8 System Control Operation Format
134. M MOTOROLA MOVE to CCR Operation Attributes Move to the Condition Code Register All ColdFire Processors Source CCR Assembler Syntax MOVE B Dy CCR MOVE B lt data gt CCR Size Byte MOVE to CCR Description Moves the low order byte of the source operand to the condition code register The upper byte of the source operand is ignored the upper byte of the status register is not altered Condition X Codes 5 Instruction 15 O lt NZX Set to the value of bit 4 of the source operand Set to the value of bit 3 of the source operand Set to the value of bit 2 of the source operand Set to the value of bit 1 of the source operand Set to the value of bit 0 of the source operand 4 3 2 1 0 Format 0 Source Effective Address Mode Register Instruction Field e Effective Address field Specifies the location of the source operand use only those data addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay o lt data gt 111 100 Ay Ay di6 Ay dig PC zi dg Ay Xi dg PC Xi En M MOTOROLA Chapter 4 Integer User Instructions 4 51 MULS Signed Multiply MULS All ColdFire Processors Operation
135. Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay d4g PC 111 010 dg Ay Xi dg PC Xi M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 29 Instruction Descriptions FMOVE FMOVE to FPSR Move to the Floating to FPSR Point Status Register Operation Source FPSR Assembler syntax FMOVE L lt ea gt y FPSR Attributes Format longword Description Loads the FPSR from an effective address A 32 bit transfer is always performed even though the FPSR does not have 32 implemented bits Unimplemented bits are ignored during writes must be zero for compatibility with future devices Exceptions are not taken upon execution of this instruction FPSR All bits are modified to reflect the source operand value Instruction 15 14 13 132 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt y shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay
136. NE If the BSUN exception is enabled in FPCR the exception takes a BSUN trap Therefore the IEEE nonaware program is interrupted if an unexpected condition occurs Users knowledgeable of the IEEE 754 standard should use IEEE aware tests in programs that contain ordered and unordered conditions Because the ordered or unordered attribute is explicitly included in the conditional test EXC BSUN is not set when the unordered condition occurs Table 7 4 summarizes conditional mnemonics definitions equations predicates and whether EXC BSUN is set for the 32 floating point conditional tests The equation column lists FPCC bit combinations for each test in the form of an equation Condition codes with an overbar indicate cleared bits all other bits are set Table 7 4 Floating Point Conditional Tests Mnemonic Definition Equation Predicate EXC BSUN Set IEEE Nonaware Tests 000001 Not equal Z 001110 Greater than NANT Z N 010010 Not greater than NAN Z N 011101 Greater than or equal Z NAN N 010011 Not greater than or equal NAN N amp Z 011100 Less than NAN TZ 010100 Not less than 011011 Less than or equal 010101 Not less than or equal 011010 Greater or less than Z 010110 Not greater or less than Z 011001 Greater less or equal 010111 Not greater less or equal 011000 Equal 000001 Not equal Z 001110 OGT Ordered greater than NAN ZIN 000010 No M mororoLA
137. OVE from FPCR Move from the Floating from FPCR Point Control Register Operation FPCR Destination Assembler syntax FMOVE L FPCR lt ea gt x Attributes Format longword Description Moves the contents of the FPCR to an effective address A 32 bit transfer is always performed even though the FPCR does not have 32 implemented bits Unimplemented bits of a control register are read as zeros Exceptions are not taken upon execution of this instruction FPSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Destination Effective Address Mode Register 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt x shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W LL Ax xxx L Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax di6 PC dg Ax Xi dg PC Xi M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 25 Instruction Descriptions FMOVE FMOVE from FPIAR move fromthe Floating from FPIAR Point Instruction Address Register Operation FPIAR Destination Assembler syntax FMOVE L FPIAR lt ea gt x Att
138. Operand Operations Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator x Arithmetic multiplication Arithmetic division Invert operand is logically complemented amp Logical AND Logical OR A Logical exclusive OR gt Source operand is moved to destination operand gt Two operands are exchanged lt op gt Any double operand operation lt operand gt tested Operand is compared to zero and the condition codes are set appropriately sign extended All bits of the upper portion are made equal to the high order bit of the lower portion Other Operations If lt condition gt then lt operations gt else lt operations gt Test the condition If true the operations after then are performed If the condition is false and the optional else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the Bcc instruction description as an example Register Specifications An Any address register n example A3 is address register 3 Ax Ay Destination and source address registers respectively Dn Any data register n example D5 is data register 5 Dx Dy Destination and source data registers respectively Dw Data register containing a remainder Rc Control regis
139. PC Xi e dr field Specifies the direction of the transfer 0 Move the listed registers from memory to the FPU 1 Move the listed registers from the FPU to memory e Register list field Contains the register select mask If a register is to be moved the corresponding mask bit is set as shown below otherwise it is zero 7 6 5 4 3 2 1 0 FPO FP1 FP2 FP3 FP4 FP5 FP6 FP7 7 32 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FMUL Floating Point Multiply FMUL Operation Source FPx FPx Assembler syntax FMUL fmt lt ea gt y FPx FMUL D FPy FPx FrMUL fmt lt ea gt y FPx FrMUL D FPy FPx where r is rounding precision S or D Attributes Format byte word longword single precision double precision Description Converts source operand to double precision if necessary and multiplies that number by the number in destination floating point data register Stores result in the destination floating point data register FMUL rounds the result to the precision selected in FPCR FSMUL and FDMUL round the result to single or double precision respectively regardless of the rounding precision selected in FPCR Operation HE Source Destination Table In Range Zero Infinity In Range 0 0 0 0 inf inf Multiply 0 0 0 0 inf inf Zero 40 0 0 0
140. PES til de nn ot en d an nt 1 17 M MOTOROLA Contents v Paragraph Number 1 7 1 1 1 7 1 2 1 7 1 3 1 7 1 4 1 7 1 5 1 7 2 1 8 1 9 1 9 1 1 9 2 2 1 Zed 22 1 222 2 2 3 2 2 4 229 2 2 6 Zedel 2 2 8 2 2 9 2 2 10 22011 2212 2 2 13 2 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 1 5 3 1 6 3 1 7 vi CONTENTS x Page Title Number Normalized NUMA OLS scana pn saa ns aa dee 1 17 ZETOS rm nd te Meda aarden 1 17 MIES ENS A Onnen a TE MT aetghe 1 17 Not A Number sienne astienieed nes sinusite 1 18 Denormalized Numbers nan eed eee 1 18 FPU Data Format and Type Summary onno onneevenneevenneevenneevenveren 1 18 Multiply Accumulate Data Formats 1 20 Organization of Data in Registers enne onneevenneevenservennervenvervenvereennen 1 20 Organization of Integer Data Formats in Registers ee eeeeeeeeeeneeeneeees 1 20 Organization of Integer Data Formats in Memory 1 22 Chapter 2 Addressing Capabilities Instruction BOOM Senden rentmeester 2 1 Effective Addressing MOSS nne eeen 2 2 Data Register Direct Mode oo etende ede 2 3 Address Register Direct Mode seche Mines dus dia 2 3 Address Register Indirect Mode ss sverneverrnervnaseernnerssdnanesraer ontenetnavesdanessses 2 3 Address Register Indirect with Postincrement Mode 2 4 Address Register Indirect with Predecrement Mode nnee 2 4 Address Register Indirect with Displacement Mode
141. Point Divide FPx Source FPx Assembler Syntax FDIV fmt lt ea gt y FPx FDIV D FPy FPx FrDIV fmt lt ea gt y FPx FrDIV D FPy FPx where r is rounding precision S or D Attributes FDIV Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and divides it into the number in the destination floating point data register Stores the result in the destination floating point data register FDIV rounds the result to the precision selected in FPCR FSDIV and FDDIV round the result to single or double precision respectively regardless of the rounding precision selected in FPCR Operation HE Source Destination Table In Range Zero Infinity In Range ade inf inf 0 0 0 0 z inf inf2 0 0 0 0 Zero 0 0 0 0 0 0 0 0 _ 0 0 0 0 NAN 0 0 0 0 Infinity inf inf inf inf 3 _ inf inf inf inf NAN 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number 2 Sets the DZ bit in the FPSR exception byte 3 Sets the OPERR bit in the FPSR exception byte FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 Set for0 0 See Table 7 2 Set if source is 0 See or co oo and destination is in Table 7 2 cleared range cleared otherwise otherwise FPSR AEXC See Sectio
142. Px FPx round destination to double FDSUB lt ea gt y FPx B W L S D FPx Source FPx round destination to double User FPy FPx D FINT lt ea gt y FPx B W L S D Integer Part of Source FPx User FPy FPx D FPx D Integer Part of FPx FPx FINTRZ lt ea gt y FPx B W L S D Integer Part of Source FPx round to zero User FPy FPx D FPx D Integer Part of FPx FPx round to zero FMOVE lt ea gt y FPx B W L S D Source Destination User FPy lt ea gt x B W L S D FPy FPx D FPcr lt ea gt x L FPcr can be any floating point control register lt ea gt y FPcr L FPCR FPIAR FPSR FMOVEM list lt ea gt x D Listed registers Destination User lt ea gt y list Source Listed registers 3 20 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Set Additions Table 3 19 Floating Point Instruction Set Summary Operand Super Instruction Operand Syntax Size Operation User FMUL lt ea gt y FPx B W L S D Source FPx FPx User FPy FPx D FNEG lt ea gt y FPx B W L S D Source FPx User FPy FPx D FPx D FPx FPx FNOP none none PC 2 PC FPU Pipeline Synchronized User FRESTORE lt ea gt y none FPU State Frame Internal FPU State Super FSABS lt ea gt y FPx B W L S D Absolute Value of Source FPx round User FPy FPx D destination to single FPx D Absolute Value of FPx FPx round destination to single FSADD l
143. Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W zE Ay 001 reg number Ay xxx L S Ay EE lt data gt 111 100 Ay Ay d16 Ay die PC dg Ay Xi dg PC Xi 5 10 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE to MACSR Operation Move to the MAC Status Register Source MACSR Assembler Syntax MOVE L Ry MACSR MOVE L lt data gt MACSR Attributes Size longword MOVE to MACSR Description Moves a 32 bit value from a register or an immediate operand into the MACSR MACSR 15 14 Source lt ea gt bit Instruction 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 j OMC S U FA R T N Z V y et 7 6 5 4 B 2 H 13 12 11 10 8 7 6 4 3 2 1 0 1 0 1 0 1 0 Source Effective Address Format 1 0 Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay lt data gt 111 100 Ay Ay di6 Ay di6 PC dg Ay Xi dg PC
144. Source Destination gt Destination Assembler Syntax MULS W lt ea gt y Dx 16 x 16 gt 32 MULS L lt ea gt y Dx 32 x 32 32 Attributes Size word longword Description Multiplies two signed operands yielding a signed result This instruction has a word operand form and a longword operand form In the word form the multiplier and multiplicand are both word operands and the result is a longword operand A register operand is the low order word the upper word of the register is ignored All 32 bits of the product are saved in the destination data register In the longword form the multiplier and multiplicand are both longword operands The destination data register stores the low order 32 bits of the product The upper 32 bits of the product are discarded Note that CCR V is always cleared by MULS unlike the 68K family processors Condition X N Z V C X Not affected Codes 0 0 N Set if result is negative cleared otherwise oqes Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 0 0 Register Dx 1 1 1 Source Effective Address Word Mode Register Instruction Fields Word e Register field Specifies the destination data register Dx e Effective Address field Specifies the source operand lt ea gt y use only those data addressing modes listed in the following table Addressi
145. VBR 0x10 PC JMP lt ea gt y none Source Address PC ISA_A JSR lt ea gt y none SP 4 SP nextPC SP Source PC ISA_A LEA lt ea gt y Ax L lt ea gt y Ax ISA_A LINK Ay lt displacement gt W SP 4 gt SP Ay gt SP SP gt Ay SP d gt SP ISA A LSL Dy Dx L CCRIX C Dx lt lt Dy 0 ISA_A lt data gt Dx L CCRIX C Dx lt lt lt data gt 0 LSR Dy Dx L 0 Dx gt gt Dy CCR X C ISA_A lt data gt Dx L 0 Dx gt gt lt data gt CCR X C MAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx MAC Ry RxSF lt ea gt y Rw W L ACCx Ry Rx lt lt gt gt SF ACCx ACCx lt ea gt y amp MASK Rw MOV3Q lt data gt lt ea gt x L Immediate Data Destination ISA_B MOVCLR ACCy Rx L Accumulator Destination 0 Accumulator EMAC MOVE lt a gt y lt ea gt X B W L Source Destination ISA_A MACcr Dx L where MACcr can be any MAC control register MAC lt ea gt y MACcr L ACCx ACCext01 ACCext23 MACSR MASK MAC MOVE from CCR CCR Dx W ISA_A MOVE to CCR lt ea gt y CCR W ISA_A MOVEA lt ea gt y Ax WELL Source Destination ISA_A MOVEM list lt ea gt x L Listed Registers Destination ISA_A lt ea gt y list Source Listed Registers MOVEQ lt data gt Dx BoL Immediate Data Destination ISA_A MSAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF ACCx MAC Ry RxSF lt ea gt y Rw W L ACCx Ry Rx lt lt gt gt SF AC
146. a data register the destination lt ea gt mode is invalid for a data register In addition SUBA is used when the destination is an address register SUBI and SUBQ are used when the source is immediate data Condition Codes Instruction Format X N Z V C 15 14 O lt NZX 7 6 5 4 Set the same as the carry bit Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Set if an overflow is generated cleared otherwise Set if an carry is generated cleared otherwise 3 2 1 0 4 0 Register Opmode Effective Address Mode Register Instruction Fields e Register field Specifies the data register e Opmode field 4 72 Byte Longword 010 Operation Dx lt ea gt y Dx 110 lt ea gt x Dy gt lt ea gt x ColdFire Family Programmer s Reference Manual M MOTOROLA SU B Subtract SU B Instruction Fields continued e Effective Address field Determines addressing mode For the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY
147. abled case unless the enabled exception occurred on a FMOVE OUT in which case the destination is unaffected If desired the user OPERR handler can overwrite the default result 11 12 ColdFire Family Programmer s Reference Manual M MOTOROLA Overview 11 1 9 Overflow OVFL An overflow exception is detected for arithmetic operations in which the destination is a floating point data register or memory when the intermediate result s exponent is greater than or equal to the maximum exponent value of the selected rounding precision Overflow occurs only when the destination is S or D precision format overflows for other formats are handled as operand errors At the end of any operation that could potentially overflow the intermediate result is checked for underflow rounded and then checked for overflow before it is stored to the destination If overflow occurs FPSR OVFL INEX are set Even if the intermediate result is small enough to be represented as a double precision number an overflow can occur if the magnitude of the intermediate result exceeds the range of the selected rounding precision format See Table 11 10 Table 11 10 OVFL Exception Enabled Disabled Results Condition OVFL Description Exception 0 The values stored in the destination based on the rounding mode defined in FRCR MODE disabled RN Infinity with the sign of the intermediate result RZ Largest magnitude number with the sign of the intermed
148. agnitude of the intermediate result is too small to be represented in the selected rounding precision Table 11 11 shows results when the exception is enabled or disabled M MOTOROLA Chapter 11 Exception Processing 11 13 Overview Table 11 11 UNFL Exception Enabled Disabled Results Condition UNFL Description Exception 0 The stored result is defined below The UNFL exception also sets FPSR INEX if the UNFL disabled exception is disabled RN Zero with the sign of the intermediate result RZ Zero with the sign of the intermediate result RM For positive underflow 0 For negative underflow smallest negative normalized number RP For positive underflow smallest positive normalized number For negative underflow 0 Exception 1 The result written to the destination is the same as for the exception disabled case unless the enabled exception occurs on a FMOVE OUT in which case the destination is unaffected If desired the user UNFL handler can overwrite the default result The UNFL exception does not set FPSR INEX if the UNFL exception is enabled so the exception handler can set FPSR INEX based on results it generates 11 1 11 Divide by Zero DZ Attempting to use a zero divisor for a divide instruction causes a divide by zero exception When a divide by zero is detected FPSR DZ is set Table 11 12 shows results when the exception is enabled or disabled Table 11 12 DZ Exception Enabled Disabled Results C
149. aining the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z V C X Not affected Codes 0 0 N Setifthe msb of the result is set cleared otherwise odes Z Setif the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 43 12 t 10 9 8 7 6 5 4 3 2 4 0 Format 0 0 0 0 0 0 0 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Destination register field Specifies the destination data register Dx 4 64 ColdFire Family Programmer s Reference Manual M MOTOROLA PEA PEA Push Effective Address All ColdFire Processors Operation SP 4 SP lt ea gt y SP Assembler Syntax PEA L lt ea gt y Attributes Description Computes the effective address and pushes it onto the stack The effective address is a longword address Size longword Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 Format 0 1 0 0 1 0 0 0 0 1 Source Effective Address Mode Register Instruction Field e Effective Address field Specifies the address lt ea gt y to be pushed onto the stack use only those control addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register D
150. al purpose register The accumulator extension bytes are stored as shown in the following table Note the position of the LSB of the extension within the combined 48 bit accumulation logic is dependent on the operating mode of the EMAC integer versus fractional Accumulator Extension Destination Byte Data Bits ACCext1 15 8 31 24 ACCext1 7 0 23 16 ACCext0 15 8 15 8 ACCext0 7 0 7 0 MACSR Not affected Instruction 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 0 1 1 1 0 0 0 Register Rx Instruction Field e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 6 10 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE from MOVE from ACCext23 Move from Accumulator ACCext23 2 and 3 Extensions Operation Accumulator 2 and 3 extension words Destination Assembler syntax MOVE L ACCext23 Rx Attributes Size longword Description Moves the contents of the four extension bytes associated with accumulators 2 and 3 into a general purpose register The accumulator extension bytes are stored as shown in the following table Note the position of the LSB of the extension within the combined 48 bit accumulation logic is dependent on the operating mode of the EMAC integer versus fractional Accumulator Extension Destination Byte Data Bits ACCext3 15 8 31 24 ACCext3
151. alted state M mororoLa Chapter 11 Exception Processing Overview Table 11 3 Exceptions Vector Number Type Description 0 1 Reset Access error Asserting the reset input signal RSTI causes a reset exception which has the highest exception priority and provides for system initialization and recovery from catastrophic failure When assertion of RSTT is recognized current processing is aborted and cannot be recovered The reset exception places the processor in supervisor mode by setting SR S and disables tracing by clearing SR T It clears SR M and sets SR I to the highest level Ob111 priority level 7 Next VBR is cleared Configuration registers controlling operation of all on chip memories are invalidated disabling the memories Note Implementation specific supervisor registers are also affected at reset After RSTI is negated the processor waits a number of cycles before beginning the reset exception process During this time certain events are sampled including the assertion of the debug breakpoint signal If the processor is not halted it initiates the reset exception by performing two longword read bus cycles The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC After the initial instruction is fetched from memory program execution begins at the address in the PC If an access error or address error occurs before the first instruction e
152. an carry is generated cleared otherwise Instruction 15 14 43 12 u 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 0 1 0 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Destination Register field Specifies the destination data register Dx M mororoLA Chapter 4 Integer User Instructions 4 75 SUBQ SUBQ Subtract Quick All ColdFire Processors Operation Destination Immediate Data Destination Assembler Syntax SUBQ L lt data gt lt ea gt x Attributes Size longword Description Operates similarly to SUB but is used when the source operand is immediate data ranging in value from 1 to 8 Subtracts the immediate value from the operand at the destination location The size of the operation is specified as longword The immediate data is zero filled to a longword before being subtracted from the destination When adding to address registers the condition codes are not altered Condition X N Z V C X Set the same as the carry bit Codes N Set if the result is negative cleared otherwise odes Z Set if the result is zero cleared otherwise V Set if an overflow is generated cleared otherwise C Set if an carry is generated cleared otherwise Instruction 15 14 13 12 11 10 8s 7 6 5 43 2 1 0 Format 0 1 0 1 Data 1 1 0 Destination Effective Address Mode
153. at longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W _ Ax xxx L Ax 010 reg number Ax lt data gt En Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi dg PC Xi e Bit Number field Specifies the bit number Bit Number Dynamic Specified in a Register Instruction 15 14 43 12 u 10 9 8 7 6 5 44 3 2 1 0 Format 0 0 0 0 Data Register Dy 1 1 1 Destination Effective Address Mode Register Instruction Fields e Data Register field Specifies the data register Dy that contains the bit number e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax d45 PC dg Ax Xi 110 reg number Ax dg PC Xi M MOTOROLA Chapter 4 Integer User I
154. aximum and minimum values For single and double precision normalized numbers the implied integer bit is one and the exponent can be zero tal Min lt Exponent lt Max Fraction Any bit pattern Sign of Mantissa 0 or 1 Figure 1 19 Normalized Number Format 1 7 1 2 Zeros Zeros can be positive or negative and represent real values 0 0 and 0 0 See Figure 1 20 Sign of Mantissa 0 or 1 Figure 1 20 Zero Format 1 7 1 3 Infinities Infinities can be positive or negative and represent real values that exceed the overflow threshold A result s exponent greater than or equal to the maximum exponent value indicates an overflow for a given data format and operation This overflow description ignores the effects of rounding and the user selectable rounding models For single and double precision infinities the fraction is a zero See Figure 1 21 Sign of Mantissa 0 or 1 Figure 1 21 Infinity Format M mororoLA Chapter 1 Introduction 1 17 Floating Point Data Formats 1 7 1 4 Not A Number When created by the FPU NANs represent the results of operations having no mathematical interpretation such as infinity divided by infinity Operations using a NAN operand as an input return a NAN result User created NANs can protect against uninitialized variables and arrays or can represent user defined data types See Figure 1 22 E Exponent Maximum Fraction Any nonzero bit pattern Sign of Mantissa 0 or 1 Figu
155. ber NAN 554 oDC NextFP or Fault Floating point input denormalized number 56 60 0E0 0F0 Reserved 61 OF4 Fault Unsupported instruction 62 63 OF8 OFC Reserved 64 255 100 3FC Next User defined interrupts Fault refers to the PC of the faulting instruction Next refers to the PC of the instruction immediately after the faulting instruction NextFP refers to the PC of the next floating point instruction a A O N If the divide unit is not present 5202 5204 5206 vector 5 is reserved On V2 and V3 all debug interrupts use vector 12 vector 13 is reserved If the FPU is not present vectors 48 55 are reserved Some devices do not support this exception refer to Table 11 3 ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers This allows any handler to effectively disable interrupts if necessary by raising the interrupt mask level in the SR M MOTOROLA Chapter 11 Exception Processing Overview 11 1 1 Supervisor User Stack Pointers A7 and OTHER A7 The V4 architecture supports two unique stack pointer A7 registers the supervisor stack pointer SSP and the user stack pointer USP This support provides the required isolation between operating modes as dictated by the virtual memory management scheme provided by the MMU Note that only the SSP is used during creation of the exception stack frame The hardware implementation of these tw
156. bit operands are used the upper or lower word of each register must be specified Condition N Z V N Set if the msb of the result is set cleared otherwise Cod Z Set if the result is zero cleared otherwise odes V Set if an overflow is generated unchanged otherwise MACSR Instruction 15 14 13 Format 1 fo 1 11 10 9 8 7 6 5 Reston Jo fo me SZ Scale 1 U Lx U Ly Factor 12 4 3 2 1 0 Ea Lo Register Ry Instruction Fields e Register Rx 6 11 9 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e Register Ry 3 0 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 e sz field Specifies the size of the input operands 0 word longword e Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none O1 product lt lt 1 10 reserved 11 product gt gt 1 M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 13 MSAC Multiply Subtract MSAC Instruction Fields continued e U Lx Specifies which 16 bit operand of the source register Rx is used for a word sized operation 0 lower word 1 upper word e U Ly Specifies which 16 bit operand of the source register Ry is used for a
157. cal operations with longword integer data operands A similar set of immediate instructions ANDI ORI and EORI provides these logical operations with longword immediate data Table 3 4 summarizes the logical operations Table 3 4 Logical Operation Format Instruction Operand Syntax Operand Size Operation AND lt ea gt y Dx L Source amp Destination Destination Dy lt ea gt x L ANDI lt data gt Dx L Immediate Data amp Destination Destination EOR Dy lt ea gt x L Source Destination Destination EORI lt data gt Dx L Immediate Data Destination Destination NOT Dx L Destination Destination OR lt ea gt y Dx L Source Destination Destination Dy lt ea gt x L ORI lt data gt Dx L Immediate Data Destination Destination 3 1 4 Shift Instructions The ASR ASL LSR and LSL instructions provide shift operations in both directions All shift operations can be performed only on registers Register shift operations shift longwords The shift count can be specified in the instruction operation word to shift from 1 to 8 places or in a register modulo 64 shift count The SWAP instruction exchanges the 16 bit halves of a register Table 3 5 is a summary of the shift operations In Table 3 5 C and X refer to the C bit and X bit in the CCR M mororoLA Chapter 3 Instruction Set Summary 3 7 Instruction Summary Table 3 5 Shift Operation Format
158. ccumulate Instructions Continued Instruction Operand Syntax PST DDATA move MACSR CCR PST 0x1 move MACSR Rx PST 0x1 move MASK Rx PST 0x1 msac l Ry Rx PST 0x1 msac Ry Rx lt ea gt y Rw ACCx PST 0x1 PST 0xB DD source operand msac l Ry Rx ACCx PST 0x1 msac Ry Rx lt ea gt y Rw PST 0x1 PST 0xB DD source PST 0xB DD destination msac w Ry Rx PST 0x1 msac w Ry Rx lt ea gt y Rw ACCx PST 0x1 PST 0xB DD source operand msac w Ry Rx ACCx PST 0x1 msac w Ry Rx lt ea gt y Rw PST 0x1 PST 0xB DD source PST 0xB DD destination Table 10 3 shows the PST DDATA specification for floating point instructions note that lt ea gt y includes FPy Dy Ay and lt mem gt y addressing modes The optional operand capture and display applies only to the lt mem gt y addressing modes Note also that the PST DDATA values are the same for a given instruction regardless of explicit rounding precision Table 10 3 PST DDATA Values for User Mode Floating Point Instructions Instruction Operand Syntax PST DDATA fabs sz lt ea gt y FPx PST 0x1 89B source fadd sz lt ea gt y FPx PST 0x1 89B source focc w lt label gt if taken then PST 5 else PST 0x1 fcmp sz lt ea gt y FPx PST 0x1 89B source fdiv sz lt ea gt y FPx PST 0x1 89B source fint sz lt ea gt y FPx PST 0x1
159. ception is generated vector 14 If the format is valid the frame is loaded into the FPU starting at the specified location and proceeding through higher addresses FRESTORE ignores the vector specified in the byte at lt ea gt y 1 because all vectors are generated from FPCR and FPSR exception bits This vector is provided for the handler FRESTORE does not normally affect the FPU programming model except the NULL state frame It is generally used with FMOVEM to fully restore the FPU context including floating point data and system control registers For complete restoration FMOVEM first loads the data registers then FRESTORE loads the internal state FPCR and FPSR Table 8 1 lists supported state frames If the frame format is not 0x00 0x05 or OxES the processor responds with a format error exception vector 14 and the internal FPU state is unaffected Table 8 1 State Frames State Format Description NULL 0x00 FRESTORE of this state frame is like a hardware reset of the FPU The programmer s model enters reset state with NANS in floating point data registers and zeros in FPCR FPSR and FPIAR IDLE 0x05 AFRESTORE of the IDLE or EXCP state frame yields the same results The FPU is restored to idle state waiting for initiation of the next instruction with no exceptions pending However if an EXCP OxES FPSR EXC bit and corresponding FPCR enable bit are set the FPU enters exception state In this state
160. cluding 0 The 3 bit immediate operand is sign extended to a longword operand and all 32 bits are transferred to the destination location Not affected Set if result is negative cleared otherwise Set if the result is zero cleared otherwise Always cleared Always cleared Condition X N Z V C Codes de 0 0 O lt NZX Instruction 5 14 13 12 11 10 9 8 7 saa da Ol irc fala Instruction Fields e Immediate data field 3 bits of data having a range 1 1 7 where a data value of 0 represents 1 e Destination Effective Address field Specifies the destination operand lt ea gt x use only data addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 AX 001 reg number Ax xxx L 111 001 Ax 010 reg number Ax lt data gt AX 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi 110 reg number Ax dg PC Xi En MOV3Q V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported L M mororoLA Chapter 4 Integer User Instructions 4 43 MOVE Move Data from Source to Destination MOVE All ColdFire Processors Operation Source Destination Assembler Syntax MOVE sz lt ea gt y lt ea gt x Attributes Size byte word longword Descripti
161. ctive Address Mode Register 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt y shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay d4g PC 111 010 dg Ay Xi dg PC Xi 7 28 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FMOVE FMOVE to FPIAR Move to the Floating to FPIAR Point Instruction Address Register Operation Source FPIAR Assembler syntax FMOVE L lt ea gt y FPIAR Attributes Format longword Description Loads the floating point instruction address register from an effective address Exceptions are not taken upon execution of this instruction FPSR Not affected Instruction 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt y shown in the following table Addressing Mode Mode Register Addressing
162. d move b lt ea gt y lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination move l lt ea gt y lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination move w lt ea gt y lt ea gt x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy lt data gt CCR PST 0x1 movea l lt ea gt y Ax PST 0x1 PST 0xB DD source movea w lt ea gt y Ax PST 0x1 PST 0x9 DD source movem list lt ea gt X PST 0x1 PST OxB DD destination movem lt ea gt y list PST 0x1 PST OxB DD source 3 moveg l lt data gt Dx PST 0x1 muls lt ea gt y Dx PST 0x1 PST 0xB DD source operand muls w lt ea gt y Dx PST 0x1 PST 0x9 DD source operand mulu l lt ea gt y Dx PST 0x1 PST 0xB DD source operand mulu w lt ea gt y Dx PST 0x1 PST 0x9 DD source operand mvs b lt ea gt y Dx PST 0x1 0x8 source operand mvs w lt ea gt y Dx PST 0x1 0x9 source operand mvz b lt ea gt y Dx PST 0x1 0x8 source operand mvz w lt ea gt y Dx PST 0x1 0x9 source operand neg l Dx PST 0x1 negx l Dx PST 0x1 nop PST 0x1 10 3 User Instruction Set Table 10 1 PST DDATA Specification for User Mode Instructions Continued Instruction Operand Syntax PST DDATA not l Dx PST Ox1 or l lt ea gt y Dx PST 0x1
163. d access to undefined or unimplemented control register space produces undefined results Condition Codes Instruction Format Not affected 15 14 13 12 14 10 8 7 6 5 4 2 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 A D Register Ry Control Register Rc Instruction Fields e A D field Specifies the type of source register Ry data register address register e Register Ry field Specifies the source register Ry e Control Register Rc field Specifies the control register affected using the values shown in Table 8 3 M MOTOROLA Chapter 8 Supervisor Privileged Instructions MOVEC 8 14 Move Control Register Table 8 3 ColdFire CPU Space Assignments Name CPU Space Assignment Register Name Memory Management Control Registers CACR 0x002 Cache control register ASID 0x003 Address space identifier register ACRO 0x004 Access control registers 0 ACR1 0x005 Access control registers 1 ACR2 0x006 Access control registers 2 ACR3 0x007 Access control registers 3 MMUBAR 0x008 MMU base address register Processor Miscellaneous Registers VBR 0x801 Vector base register PC 0x80F Program counter Local Memory and Module Control Registers ROMBARO 0xC00 ROM base address register 0 ROMBAR1 0xC01 ROM base address register 1 RAMBARO 0xC04 RAM base address register 0 RAMBAR1 OxC05 RAM bas
164. des listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax 001 reg number Ax xxx L 111 001 Ax 010 reg number Ax lt data gt _ Ax 011 reg number Ax Ax 100 reg number Ax d 6 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi En 4 6 ColdFire Family Programmer s Reference Manual M MOTOROLA ADDX Add Extended ADDX All ColdFire Processors Operation Source Destination CCR X Destination Assembler Syntax ADDX L Dy Dx Attributes Size longword Description Adds the source operand and CCR X to the destination operand and stores the result in the destination location The size of the operation is specified as a longword Set the same as the carry bit Set if the result is negative cleared otherwise Cleared if the result is non zero unchanged otherwise Set if an overflow is generated cleared otherwise Set if an carry is generated cleared otherwise Condition X N Z V C Codes 5 i 5 O lt NZX Normally CCR Z is set explicitly via programming before the start of an ADDX operation to allow successful testing for zero results upon completion of multiple precision operations Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 0 1 Register Dx 1 1 olo lofo Register Dy
165. e FSADD lt ea gt y FPx B W L S D Source FPx FPx round destination to single FPU FPy FPx FSDIV lt ea gt y FPx B W L S D FPx Source FPx round destination to single FPU FPy FPx D FSMOVE lt ea gt y FPx B W L S D Source Destination round destination to single FPU FSMUL lt ea gt y FPx B W L S D Source FPx FPx round destination to single FPU FPy FPx D 3 14 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Set Additions Table 3 14 ColdFire User Instruction Set Summary Continued Instruction Operand Syntax Ms Operation ISA FSNEG lt ea gt y FPx B W L S D Source FPx round destination to single FPU FPy FPx D FPx D FPx FPx round destination to single FSQRT lt ea gt y FPx B W L S D Square Root of Source FPx FPU FPy FPx D FPx D Square Root of FPx FPx FSSQRT lt ea gt y FPx B W L S D Square Root of Source FPx round destination FPU FPy FPx D to single FPx D Square Root of FPx FPx round destination to single FSSUB lt ea gt y FPx B W L S D FPx Source FPx round destination to single FPU FPy FPx D FSUB lt ea gt y FPx B W L S D FPx Source FPx FPU FPy FPx D FTST lt ea gt y B W L S D Source Operand Tested FPCC FPU ILLEGAL none none SP 4 gt SP PC gt SP gt PC SP 2 SP ISA_A SR SP SP 2 gt SP Vector Offset SP
166. e destination address register use the control addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt Ay Ay r d1 Ay 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 M mororoLA Chapter 4 Integer User Instructions 4 39 LINK Link and Allocate LINK All ColdFire Processors Operation SP 4 SP Ay SP SP Ay SP d SP Assembler Syntax LINK W Ay lt displacement gt Attributes Size Word Description Pushes the contents of the specified address register onto the stack Then loads the updated stack pointer into the address register Finally adds the displacement value to the stack pointer The displacement is the sign extended word following the operation word Note that although LINK is a word sized instruction most assemblers also support an unsized LINK Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 1 0 0 1 0 1 0 Register Ay Word Displacement Instruction Fields e Register field Specifies the address register Ay for the link e Displacement field Specifies the two s complement integer to be added to the stack pointer 4 40 ColdF
167. e 3 11 lists the available operations Table 3 10 Dyadic Floating Point Operation Format Instruction operand Operand Size Operation Syntax F lt dop gt lt ea gt y FPx B W L S D FPx lt Function gt Source FPx FPy FPx Table 3 11 Dyadic Floating Point Operations Instruction F lt dop gt Operation FADD FSADD FDADD Add FCMP Compare FDIV FSDIV FDDIV Divide FMUL FSMUL FDMUL Multiply FSUB FSSUB FDSUB Subtract The monadic floating point instructions provide several arithmetic functions requiring one input operand such as FABS Unlike the integer counterparts to these functions e g NEG a source and a destination can be specified The operation is performed on the source operand and the result is stored in the destination which is always a floating point data register All data formats are supported Table 3 12 gives the general format for these monadic instructions Table 3 13 lists the available operations M MOTOROLA Chapter 3 Instruction Set Summary 3 11 Instruction Set Additions Table 3 12 Monadic Floating Point Operation Format Instruction Operand Operand Size Operation Syntax F lt mop gt lt ea gt y FPx B W L S D Source lt Function gt FPx FPy FPx FPx FPx lt Function gt FPx Table 3 13 Monadic Floating Point Operations Instruction F lt mop gt Operation FABS FSABS FDABS Absolu
168. e Immediate Byte and Word X CMPI L Compare Immediate Longword X X X CPUSHL Push and Possibly Invalidate Cache X X DIVS Signed Divide x X X DIVU Unsigned Divide x X X EOR Logical Exclusive OR X X X EORI Logical Exclusive OR Immediate X X X EXT EXTB Sign Extend X X X HALT Halt CPU X X X ILLEGAL Take Illegal Instruction Trap X X X INTOUCH Instruction Fetch Touch X JMP Jump X JSR Jump to Subroutine X ColdFire Family Programmer s Reference Manual M MOTOROLA Table 12 2 ColdFire Instruction Set and Processor Cross Reference Continued Mnemonic LEA Description Load Effective Address LINK Link and Allocate LSL LSR Logical Shift Left and Right MOV3Q Move 3 Bit Data Quick MOVE Move MOVE from CCR MOVE from SR Move from Condition Code Register Move from the Status Register MOVE from USP Move from User Stack Pointer MOVE to CCR Move to Condition Code Register MOVE to SR Move to the Status Register x lt MOVE to USP Move to User Stack Pointer x lt MOVEA Move Address Move Control Register Move Multiple Registers Move Quick Signed Multiply Unsigned Multiply X XxX X X X X lt x x x x Xx Move with Sign Extend Move with Zero Fill Negate Negate with Extend No Operation Logical Complement Logical Inclusive OR Logical Inclusive OR Immediate Push Ef
169. e Processors Source Destination Destination Assembler Syntax OR L lt ea gt y Dx OR L Dy lt ea gt x Attributes Size longword Description Performs an inclusive OR operation on the source operand and the destination operand and stores the result in the destination location The size of the operation is specified as a longword The contents of an address register may not be used as an operand The Dx mode is used when the destination is a data register the destination lt ea gt mode is invalid for a data register In addition ORI is used when the source is immediate data Condition Codes Instruction Format X N Z V C X Not affected P 0 0 N Set if the msb of the result is set cleared otherwise Z Setif the result is zero cleared otherwise V Always cleared C Always cleared 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 Register Opmode Effective Address Mode Register Instruction Fields e Register field Specifies the data register e Opmode field 4 62 Byte Longword Operation 010 110 lt ea gt y Dx Dx Dy lt ea gt x lt ea gt x ColdFire Family Programmer s Reference Manual M MOTOROLA OR Inclusive OR Logical OR Instruction Fields continued e Effective Address field Determines addressing mode For the source operand lt ea gt y use addressing modes listed in the fol
170. e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi 4 30 ColdFire Family Programmer s Reference Manual M MOTOROLA DIVU Unsigned Divide DIVU All ColdFire Processors Starting with MCF5206e Operation Destination Source Destination Assembler Syntax DIVU W lt ea gt y Dx 32 bit Dx 16 bit lt ea gt y 16r 16q in Dx DIVU L lt ea gt y Dx 32 bit Dx 32 bit lt ea gt y 32q in Dx where q indicates the quotient and r indicates the remainder Attributes Size word longword Description Divide the unsigned destination operand by the unsigned source and store the unsigned result in the destination For a word sized operation the destination operand is a longword and the source is a word the 16 bit quotient is in the lower word and the 16 bit remainder is in the upper word of the destination For a longword sized operation the destination and source operands are both longwords the 32 bit quotient is stored in the destination To determine the remainder on a longword sized operation use the REMU i
171. e Specifier Destination 0 1 1 0 0 0 Register FPx Instruction fields e Effective Address field Specifies the addressing mode for external operands If R M 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes listed in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay d4g PC 111 010 dg Ay Xi dg PC Xi 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros e R M field Specifies the source operand address mode The operation is lt ea gt y to register The operation is register to register e Source specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy e Destination register field Specifies the destination floating point register FPx FCMP does not overwrite the register specified by this field M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 15 Instruction Descriptions FDIV Operation Floating
172. e address register 1 MPCR OxCOC Multiprocessor control register EDRAMBAR OxCOD Embedded DRAM base address register i SECMBAR OxCOE Secondary module base address register 1 MBAR OxCOF Primary module base address register Local Memory Address Permutation Control Registers PCR1U0 0xD02 32 msbs of RAM 0 permutation control register 1 PCR1LO 0xD03 32 Isbs of RAM 0 permutation control register 1 PCR2U0 0xD04 32 msbs of RAM 0 permutation control register 2 PCR2L0 0xD05 32 Isbs of RAM 0 permutation control register 2 PCR3U0 0xD06 32 msbs of RAM 0 permutation control register 3 PCR3LO 0xD07 32 Isbs of RAM 0 permutation control register 3 PCR1U1 0xDOA 32 msbs of RAM 1 permutation control register 1 PCR1L1 0xDOB 32 Isbs of RAM 1 permutation control register 1 PCR2U1 0xDOC 32 msbs of RAM 1 permutation control register 2 PCR2L1 OxDOD 82 Isbs of RAM 1 permutation control register 2 PCR3U1 OxXDOE 32 msbs of RAM 1 permutation control register 3 PCR3L1 OxDOF 32 Isbs of RAM 1 permutation control register 3 Field definitions for these optional registers are implementation specific ColdFire Family Programmer s Reference Manual MOVEC M MOTOROLA RTE Return from Exception RTE All ColdFire Processors Operation If Supervisor State Then 2 SP SR 4 SP PC SP 8 SP Adjust stack according to format Else Privilege Violation Exception Assembler Syntax RTE Attributes Unsized Description Loads the processor state infor
173. e effective address field EORI is used when the source is immediate data Not affected Set if the msb of the result is set cleared otherwise Set if the result is zero cleared otherwise Always cleared Always cleared Condition X N Z V C Codes jp jd 0 0 O lt NZX Instruction 5 14 Format Instruction Fields e Register field Specifies any of the 8 data registers for the source operand Dy e Destination Effective Address field Specifies the destination operand lt ea gt x use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi M mororoLA Chapter 4 Integer User Instructions 4 33 EORI Exclusive OR Immediate EORI All ColdFire Processors Operation Immediate Data Destination gt Destination Assembler Syntax EORI L lt data gt Dx Attributes Size longword Description Performs an exclusive OR operation on the destination operand using the immediate data and the destination operand and stores the result in the destination data register Dx The size of the operation is specified as a longword Note that the immediate data
174. e of publication of this document and the cores and optional modules that they contain are shown in Table 12 1 Table 12 1 Standard Products Standard Product Core ISA Optional Modules 5202 V2 ISA_A 5204 V2 ISA_A 5206 V2 ISA_A 5206e V2 ISA_A Divide MAC 5272 V2 ISA_A Divide MAC 5307 V3 ISA_A MAC fractional 5407 V4 ISA_B MAC fractional Divide is a required module for V3 and V4 M MOTOROLA Chapter 12 Processor Instruction Summary 12 1 12 2 Table 12 2 ColdFire Instruction Set and Processor Cross Reference Mnemonic Description V2 V3 V4 ADD Add X X X ADDA Add Address X X X ADDI Add Immediate X X X ADDQ Add Quick X X X ADDX Add with Extend X X X AND Logical AND X X X ANDI Logical AND Immediate X X X ASL ASR Arithmetic Shift Left and Right X X X Bcc B W Branch Conditionally Byte and Word X X X Bcc L Branch Conditionally Longword X BCHG Test Bit and Change X BCLR Test Bit and Clear X BRA B W Branch Always Byte and Word X X BRA L Branch Always Longword X BSET Test Bit and Set X X X BSR B W Branch to Subroutine Byte and Word X BSR L Branch to Subroutine Longword X BTST Test a Bit X X X CLR Clear X X X CMP B W Compare Byte and Word X CMPL Compare Longword X X X CMPA W Compare Address Word X CMPA L Compare Address Longword X X X CMPI B W Compar
175. e registers 1 1 Integer Unit User Programming Model Figure 1 1 illustrates the integer portion of the user programming model It consists of the following registers e 16 general purpose 32 bit registers D0 D7 AO A7 e 32 bit program counter PC e 8 bit condition code register CCR M MOTOROLA Chapter 1 Introduction 1 1 Integer Unit User Programming Model DO Data registers 31 0 AO Address registers A7 Stack pointer PC Program counter CCR Condition code register Figure 1 1 ColdFire Family User Programming Model 1 1 1 Data Registers DO D7 These registers are for bit byte 8 bits word 16 bits and longword 32 bits operations They can also be used as index registers 1 1 2 Address Registers A0 A7 These registers serve as software stack pointers index registers or base address registers The base address registers can be used for word and longword operations Register A7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling 1 1 3 Program Counter PC The program counter PC contains the address of the instruction currently executing During instruction execution and exception processing the processor automatically increments the contents or places a new value in the PC For some addressing modes the PC can serve as a pointer for PC relative addressing 1 1 4 Condition Code Registe
176. e source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d1 Ay 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 74 ColdFire Family Programmer s Reference Manual M MOTOROLA SU BI Subtract Immediate SU BI All ColdFire Processors Operation Destination Immediate Data Destination Assembler Syntax SUBI L lt data gt Dx Attributes Size longword Description Operates similarly to SUB but is used when the source operand is immediate data Subtracts the immediate data from the destination operand and stores the result in the destination data register Dx The size of the operation is specified as longword Note that the immediate data is contained in the two extension words with the first extension word bits 15 0 containing the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z V C X Set the same as the carry bit Codes N Set if the result is negative cleared otherwise 4 Z Set if the result is zero cleared otherwise V Set if an overflow is generated cleared otherwise C Set if
177. e to the Floating Point Instruction Address Register FMOVE to FPSR Move to the Floating Point Status Register FMOVEM Move Multiple Floating Point Data Registers FMUL FSMUL FDMUL Floating Point Multiply FNEG FSNEG FDNEG FNOP Floating Point Negate No Operation FRESTORE Restore Internal Floating Point State FSAVE Save Internal Floating Point State FSQRT FSSQRT FDSORT Floating Point Square Root FSUB Floating Point Subtract M MOTOROLA FTST Test Floating Point Operand Chapter 12 Processor Instruction Summary 12 5 12 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Appendix A S Record Output Format The S record format for output modules is for encoding programs or data files in a printable format for transportation between computer systems The transportation process can be visually monitored and the S records can be easily edited A 1 S Record Content Visually S records are essentially character strings made of several fields that identify the record type record length memory address code data and checksum Each byte of binary data encodes as a two character hexadecimal number the first character represents the high order four bits and the second character represents the low order four bits of the byte Figure A 1 illustrates the five fields that comprise an S record Table A 1 lists the composition of each S record field Type
178. ected cache as follows 00 reserved 01 data cache dc 10 instruction cache ic 11 both caches or unified cache bc also use this encoding for a device which has an instruction cache but not a data cache e Register Ax Specifies the address register defining the line within the cache to be pushed or invalidated Ax should be programmed as follows Ax 4 is the Isb for the address field which extends upward as required by the given cache size The algorithm for the size of the address field is as follows Range Cache size in bytes Associativity 16 Using a 16K 4 way set associative cache as an example Range 16384 4 16 256 28 Thus the address range for this cache would be Ax 11 4 Ax 1 0 specify the cache way or level where the line is located 8 2 ColdFire Family Programmer s Reference Manual M MOTOROLA FR ESTORE Restore Internal FRESTORE Floating Point State ColdFire Processors with an FPU Operation If in Supervisor State Then FPU State Frame Internal State Else Privilege Violation Exception Assembler syntax FRESTORE lt ea gt y Attributes Unsized Description Aborts any floating point operation and loads a new FPU internal state from the state frame at the effective address The frame format is specified in the byte at lt ea gt y and an internal exception vector is contained in the byte at lt ea gt y 1 If the frame format is invalid FRESTORE aborts and a format ex
179. ective Address Register Ax A Mode Register EOR 0xB 15 14 13 12 11 10 9 7 4 3 2 1 0 1 0 1 1 Register Dy 1 Destination Effective Address Mode Register AND OxC 15 14 13 12 11 10 9 7 4 3 2 1 0 1 1 0 0 Data Register Opmode Effective Address Mode Register MULU W OxC 15 14 13 12 11 10 9 7 4 3 2 1 0 1 1 0 0 Register Dx 1 Source Effective Address Mode Register MULS W OxC 15 14 13 12 11 10 9 7 4 3 2 1 0 1 1 0 0 Register Dx 1 Source Effective Address Mode Register ADD 0xD 15 14 13 12 11 10 9 7 4 3 2 1 0 1 1 0 1 Register Opmode Effective Address Mode Register 9 14 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map ADDX 0xD 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 Register Dx 1 1 0 0 0 0 Register Dy ADDA 0xD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 Destination 1 1 1 Source Effective Address Register Ax F Mode Register ASL ASR 0xE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 Count or dr 1 0 i r 0 0 Register Dx Register Dy LSL LSR 0xE 1 1 1 0 Count or dr 1 0 i r 0 1 Register Dx Register Dy FMOVE OxF2 Memory and register to register operation lt ea gt y FPx FPy FPx 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0
180. ed e Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx ox W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d 6 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi M mororoLA Chapter 4 Integer User Instructions 4 25 CMP Compare CMP All ColdFire Processors B and W supported starting with V4 Operation Destination Source cc Assembler Syntax CMP sz lt ea gt y Dx Attributes Size byte word longword byte word supported starting with V4 Description Subtracts the source operand from the destination operand in the data register and sets condition codes according to the result the data register is unchanged The operation size may be a byte word or longword CMPA is used when the destination is an address register CMPI is used when the source is immediate data Condition X N Z V C X Not affected Codes N Set if the result is negative cleared otherwise 7 Z Set if the result is zero cleared otherwise V Set if an overflow occurs cleared otherwise C Set if a borrow occurs cleared otherwise Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
181. ed and restored on context switches Figure 1 12 shows how the ACCO and ACC1 data is stored when loaded into a register Refer to Figure 1 10 and Figure 1 11 for information on the data contained in the extension bytes 31 24 23 16 15 8 7 0 ACC1 Upper ACC1 Lower ACCO Upper ACCO Lower Extension Byte Extension Byte Extension Byte Extension Byte Figure 1 12 Accumulator 0 and 1 Extensions ACCext01 Figure 1 13 shows how the ACC2 and ACC3 data is stored when loaded into a register Refer to Figure 1 10 and Figure 1 11 for information on the data contained in the extension bytes 31 24 23 16 15 8 7 0 ACC3 Upper ACC3 Lower ACC2 Upper ACC2 Lower Extension Byte Extension Byte Extension Byte Extension Byte Figure 1 13 Accumulator 2 and 3 Extensions ACCext01 1 4 4 MAC Mask Register MASK Only the low order 16 bits of the 32 bit mask register MASK are implemented When MASK is loaded the low order 16 bits of the source operand are loaded into the register When it is stored the upper 16 bits are forced to all ones When used by an instruction MASK is ANDed with the specified operand address Thus MASK allows an operand address to be effectively constrained within a certain range defined by the 16 bit value This feature minimizes the addressing support required for filtering convolution or any routine that implements a data array as a circular queue using the Ay addressing mode For MAC with load
182. ed in FPCR FSMOVE and FDMOVE round the result to single and double precision regardless of the rounding selected in FPCR Note that if the source format is longword or double precision inexact results may be created when rounding to single precision All other combinations of source formats and rounding precision produce an exact result FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 See Table 7 2 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR 7 22 ColdFire Family Programmer s Reference Manual AA MOTOROLA FMOVE Instruction Format lt ea gt y FPx FPy FPx Move Floating Point Data Register Instruction Descriptions FMOVE 15 14 13 12 11 10 9 7 6 5 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM 0 Source Specifier Destination Opmode Register FPx Instruction fields e Effective address field Determines the addressing mode for external operands If R M 1 this field specifies the location of the source operand Only the addressing modes listed in the following table can be used 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros e R M field Specifies the source operand address mode
183. ed in the instruction Condition Codes Not affected 13 12 Instruction 15 14 4 3 2 1 Format 0 li 0 0 1 1 oo D Source Effective Address Mode Register Instruction Field e Source Effective Address field Specifies the address of the next instruction lt ea gt y use the control addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt Ay Ay d16 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 38 ColdFire Family Programmer s Reference Manual M MOTOROLA L EA Load Effective Address L EA All ColdFire Processors Operation lt ea gt y Ax Assembler Syntax LEA L lt ea gt y Ax Attributes Size longword Description Loads the effective address into the specified address register Ax Condition Codes Not affected Instruction 15 14 13 12 1 10 9 8 7 6 5 4 Be Le 0 Format 0 1 0 0 Register Ax 1 1 1 Source Effective Address Mode Register Instruction Fields e Register field Specifies the address register Ax to be updated with the effective address e Source Effective Address field Specifies the address to be loaded into th
184. eger part is extracted by rounding the double precision number to an integer using the round to zero mode regardless of the rounding mode selected in the FPCR mode control byte making it useful for FORTRAN assignments Thus the integer part returned is the number that is to the left of the radix point when the exponent is zero For example the integer part of 137 57 is 137 0 Note the result of this operation is a floating point number Operation Source Destination Table In Range Zero Infinity Result Integer Forcedto AG 0 0l inf inf Round to Zero 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 See Table 7 2 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM O Source Specifier Destination Register FPx 7 20 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FINTRZ Floating Point Integer Round to Zero FINTRZ Instruction fields e Effective Address field Determines the addressing mode for external operands If R M 1 this field specifies the location
185. ement integer specifying the number of bytes between the branch and the next instruction to be executed if the condition is met e 16 bit displacement field Used when the 8 bit displacement contains 0x00 e 32 bit displacement field Used when the 8 bit displacement contains OxFF 4 14 Bcc V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported B W B W L ColdFire Family Programmer s Reference Manual M MOTOROLA BCHG Test a Bit and Change BCHG All ColdFire Processors Operation lt bit number gt of Destination CCR Z lt bit number gt of Destination lt bit number gt of Destination Assembler Syntax BCHG sz Dy lt ea gt x BCHG sz lt data gt lt ea gt x Attributes Size byte longword Description Tests a bit in the destination operand and sets CCR Z appropriately then inverts the specified bit in the destination When the destination is a data register any of the 32 bits can be specified by the modulo 32 bit number When the destination is a memory location the operation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation may be specified in either of two ways 1 Immediate Bit number is specified in a second word of the instruction 2 Register Specified data register contains the bit number Condition X N Z V C X Not affected Codes
186. enerated unchanged otherwise EV Set if accumulation overflows lower 32 bits integer or lower 40 bits fractional cleared otherwise Instruction 15 14 13 12 11 10 9 Format 1 o i 0 N D a 4 3 2 1 0 Register Rw 0 Rw Source Effective Address msb Mode Register Register Rx SZ Scale Factor U Lx U Ly Mask ACC msb Register Ry Instruction Fields e Register Rw 6 11 9 field Specifies the destination register Rw where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e ACC field Specifies the destination accumulator ACCx Bit 4 of the extension word is the msb and bit 7 of the operation word is the inverse of the Isb unlike the MAC instruction without a load The value of these two bits specify the accumulator number as shown in the following table Ext word 4 Op word 7 Accumulator 0 1 ACCO 0 0 ACC1 1 1 ACC2 1 0 ACC3 6 4 ColdFire Family Programmer s Reference Manual M MOTOROLA MAC MAC Multiply Accumulate with Load Instruction Fields continued e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W Ay
187. enorm exception is disabled all denormalized numbers are treated as zeros 1 7 2 FPU Data Format and Type Summary Table 1 11 summarizes the data type specifications for byte word longword single and double precision data formats 1 18 ColdFire Family Programmer s Reference Manual M MOTOROLA Table 1 11 Real Format Summary Floating Point Data Formats Parameter Single Precision Double Precision Data Format 31 30 23 22 0 63 62 52 51 0 s e f s e f Field Size in Bits Sign s 1 1 Biased exponent e 8 11 Fraction f 23 52 Total 32 64 Interpretation of Sign Positive fraction s 0 s 0 Negative fraction s 1 s 1 Normalized Numbers Bias of biased exponent 127 0x7F 1023 Ox3FF Range of biased exponent 0 lt e lt 255 OxFF 0 lt e lt 2047 0x7FF Range of fraction Zero or Nonzero Zero or Nonzero Mantissa 14 1 f Relation to representation of real numbers 1 8 x 29127 x 1 f Eh x 261023 x 1f Denormalized Numbers Biased exponent format minimum 0 0x00 0 0x000 Bias of biased exponent 126 0x7E 1022 0x3FE Range of fraction Nonzero Nonzero Mantissa Of O f Relation to representation of real numbers 1 8 x 27126 x O f 1 S x 271022 x 0 Signed Zeros Biased exponent format minimum 0 0x00 0 0x00 Mantissa 0 f 0 0 0 f 0 0 Signed Infinitie
188. er Type Description 3 Address error An address error is caused by an attempted execution transferring control to an odd instruction address that is if bit O of the target address is set an attempted use of a word sized index register Xi w or by an attempted execution of an instruction with a full format indexed addressing mode If an address error occurs on a JSR instruction the V4 processor first pushes the return address onto the stack and then calculates the target address On V2 and V3 processors the target address is calculated then the return address is pushed on stack If an address error occurs on an RTS instruction the V4 processor preserves the original return PC and writes the exception stack frame above this value On V2 and V3 processors the faulting return PC is overwritten by the address error stack frame Illegal instruction On V2 only some illegal opcodes 0x0000 and Ox4AFC are decoded and generate an illegal instruction exception Additionally attempting to execute an illegal line A or line F opcode generates unique exception types vectors 10 and 11 respectively If any other nonsupported opcode is executed the resulting operation is undefined V3 and V4 decode the complete 16 bit opcode and this exception is generated if execution of an unsupported instruction is attempted In addition the illegal opcodes above line A and line F also generate this exception ColdFire processors do not pr
189. erates this state frame if any FPSR EXC bits and corresponding FPCR exception enable bits are set This state typically indicates the FPU encountered an exception while attempting to complete execution of a previous floating point instruction FSAVE does not save FPU programming model registers It can be used with FMOVEM to perform a full context save of the FPU that includes floating point data and system control registers For a complete context save first execute FSAVE to save the internal state then execute the appropriate FMOVEM to store the data registers FPCR and FPSR are saved as part of the FSAVE state frame Furthermore FPCR is cleared at the end of the FSAVE preventing further exceptions if the handler includes floating point instructions FPSR Not affected FPCR Cleared M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 5 FSAVE Instruction 5 14 Save Internal Floating Point State 5 4 3 FSAVE 2 1 0 Format 1 1 Destination Effective Address Mode Register Instruction field e Effective address field Specifies the addressing mode lt ea gt x for the state frame Only modes in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dx xx W Ax xxx L EE En Ax 010 reg number Ax lt data gt Ax Ax d
190. estination ISA_A Dy lt ea gt x L SUBA lt ea gt y Ax L SUBI lt data gt Dx L Destination Immediate Data Destination ISA_A SUBQ lt data gt lt ea gt x L SUBX Dy Dx L Destination Source CCR X Destination ISA_A SWAP Dx W MSW of Dx amp LSW of Dx ISA_A TAS lt ea gt x B Destination Tested CCR ISA _B 1 bit 7 of Destination TPF none none PC 25 PC ISA_A lt data gt W PC 4 PC lt data gt L PC 6 PC TRAP lt vector gt none 1 gt S Bit of SR SP 4 gt SP nextPC SP ISA_A SP 2 gt SP SR gt SP SP 2 gt SP Format Offset SP VBR 0x80 4 n PC where n is the TRAP number TST lt ea gt y B W L Source Operand Tested CCR ISA_A 3 16 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Set Additions Table 3 14 ColdFire User Instruction Set Summary Continued Instruction Operand Syntax Men Operation ISA UNLK Ax none Ax gt SP SP Ax SP 4 SP ISA _A WDDATA lt ea gt y B W L Source DDATA port ISA A Longword supported starting with V4 Byte and word supported starting with V4 Word supported starting with V4 Supported starting with the 5206e Table 3 15 ColdFire Supervisor Instruction Set Summary Instruction Operand Syntax LL Operation ISA CPUSHL ic Ax none If data is valid and modified push cache line ISA_A dc Ax invalidate line if programmed
191. etting masks user data space in MBAR address range 0 V Valid Determines whether MBAR settings are valid 1 6 Integer Data Formats The operand data formats are supported by the integer unit as listed in Table 1 10 Integer unit operands can reside in registers memory or instructions themselves The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation Table 1 10 Integer Data Formats Operand Data Format Size Bit 1 bit Byte integer 8bits Word integer 16 bits Longword integer 32 bits 1 7 Floating Point Data Formats This section describes the optional FPU s operand data formats The FPU supports three signed integer formats byte word and longword that are identical to those supported by 1 16 ColdFire Family Programmer s Reference Manual M MOTOROLA Floating Point Data Formats the integer unit The FPU also supports single and double precision binary floating point formats that fully comply with the IEEE 754 standard 1 7 1 Floating Point Data Types Each floating point data format supports five unique data types normalized numbers zeros infinities NANs and denormalized numbers The normalized data type Figure 1 19 never uses the maximum or minimum exponent value for a given format 1 7 1 1 Normalized Numbers Normalized numbers include all positive or negative numbers with exponents between the m
192. f an address register to the user stack pointer If execution of this instruction is attempted on a V2 or V3 device or on the MCF5407 an illegal instruction exception will be taken This instruction will execute correctly on other V4 devices if CACR EUSP is set Condition Codes Not affected Instruction 15 14 13 12 Ei 10 9 8 7 6 a 3 2 1 0 Format 0 1 0 0 1 1 1 0 0 1 Instruction Field e Register field Specifies the source address register Ay 0 Register Ay MOVE to USP V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported L 8 12 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVEC Operation Assembler Syntax MOVEC L Ry Rc Attributes If Supervisor State Then Ry Rc Move Control Register All ColdFire Processors Else Privilege Violation Exception Size longword MOVEC Description Moves the contents of the general purpose register to the specified control register This transfer is always 32 bits even though the control register may be implemented with fewer bits Note that the control registers are write only The on chip debug module can be used to read control registers Note that this instruction synchronizes the pipeline Not all control registers are implemented in every ColdFire processor design Refer to the user s manual for a specific device to find out which registers are implemented Attempte
193. fective Address Generate Processor Status XI XxX XI X X X X Xx Signed Divide Remainder Unsigned Divide Remainder Return from Exception Return from Subroutine X X X XxX X KY XxX XxX XX X Xx Signed Saturate Set According to Condition Load Status Register and Stop Subtract M MOTOROLA Chapter 12 Processor Instruction Summary Subtract Address x XI Xl x x XI x x XI XI X XI X X X X X X X X X X X X X X X X X X X X X 12 3 Table 12 2 ColdFire Instruction Set and Processor Cross Reference Continued Mnemonic Description V2 V3 V4 SUBI Subtract Immediate X X X SUBQ Subtract Quick X X X SUBX Subtract with Extend X X X SWAP Swap Register Words X X X TAS Test and Set and Operand X TPF Trap False X X X TRAP Trap X X X TST Test Operand X X X UNLK Unlink X X X WDDATA Write Data Control Register X X X WDEBUG Write Debug Control Register X X X 1 The 5202 5204 and 5206 do not support this instruction 2 V4 and V4e additionally support the MOVE B W lt data gt d5 Ax 3 The 5407 does not have an MMU and therefore does not support this instruction Table 12 3 ColdFire MAC and EMAC Instruction Sets Mnemonic Description MAC EMAC MAC Multiply and Accumulate X X MOVCLR Move from Accumulator and Clear X MOVE ACC to ACC Copy Accumulator X MOVE from AC
194. flow smallest negative normalized number RP For positive underflow smallest positive normalized number For negative underflow 0 Enabled The result written to the destination is the same as for the exception disabled case unless the exception occurs on a FMOVE OUT in which case the destination is unaffected DZ Disabled The destination floating point data register is written with infinity with the sign set to the exclusive OR of the signs of the input operands Enabled The destination floating point data register is written as in the exception is disabled case INEX Disabled The result is rounded and then written to the destination Enabled The result written to the destination is the same as for the exception disabled case unless the exception occurred on a FMOVE OUT in which case the destination is unaffected 7 4 Instruction Descriptions This section describes floating point instructions in alphabetical order by mnemonic Operation tables list results for each situation that can be encountered in each instruction The top and left side of each table represent possible operand inputs both positive and negative results are shown in other entries In most cases results are floating point values numbers infinities zeros or NANs but for FCMP and FTST the only result is the setting of condition code bits When none is stated no condition code bits are set Note that if a M MOTOROLA Chap
195. g table for lt ea gt x Addressing Mode Mode Register Addressing Mode Mode Register Dx xxx W _ Ax xxx L En Ax 010 reg number Ax lt data gt Ax Ax mo d16 AX 101 reg number Ax di6 PC NK dg Ax Xi dg PC Xi M MOTOROLA Chapter 4 Integer User Instructions 4 47 MOVEM Move Multiple Registers MOVEM Instruction Fields continued Effective Address field continued For memory to register transfers use the following table for lt ea gt y Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W Ay xxx L En Ay 010 reg number Ay lt data gt Ay gas Pa Ay d 6 AY 101 reg number Ay d46 PC dg Ay Xi ous dg PC Xi Register List Mask field Specifies the registers to be transferred The low order bit corresponds to the first register to be transferred the high order bit corresponds to the last register to be transferred The mask correspondence is shown below 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 Al AO D7 D6 DS D4 D3 D2 Di DO 4 48 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVEQ Move Quick MOVEQ All ColdFire Processors Operation Immediate Data
196. g the caches CPUSHL is used to push a specific cache line and possibly invalidate it INTOUCH can be used to load specific data into the cache Both of these instructions are privileged instructions Table 3 9 summarizes these instructions 3 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Summary Table 3 9 Cache Maintenance Operation Format Instruction Operand Operand Size Operation Syntax CPUSHL ic Ax none If data is valid and modified push cache line invalidate dc Ax line if programmed in CACR synchronizes pipeline bc Ax INTOUCH Ay none Instruction fetch touch at Ay synchronizes pipeline 1 Supported starting with V4 3 1 9 Floating Point Arithmetic Instructions The floating point instructions are organized into two categories dyadic requiring two operands and monadic requiring one operand The dyadic floating point instructions provide several arithmetic functions such as FADD and FSUB For these operations the first operand can be located in memory an integer data register or a floating point data register The second operand is always located in a floating point data register The results of the operation are stored in the register specified as the second operand All FPU arithmetic operations support all data formats Results are rounded to either single or double precision format Table 3 10 gives the general format for these dyadic instructions Tabl
197. gt y Ax PST 0x1 PST 0xB DD source operand cmpa w lt ea gt y Ax PST 0x1 0x9 source operand cmpi b lt data gt Dx PST 0x1 cmpi l lt data gt Dx PST 0x1 cmpi w lt data gt Dx PST 0x1 divs lt ea gt y Dx PST 0x1 PST 0xB DD source operand divs w lt ea gt y Dx PST 0x1 PST 0x9 DD source operand divu l lt ea gt y Dx PST 0x1 PST 0xB DD source operand 10 2 ColdFire Family Programmer s Reference Manual M MOTOROLA User Instruction Set Table 10 1 PST DDATA Specification for User Mode Instructions Continued M MOTOROLA Chapter 10 PST DDATA Encodings Instruction Operand Syntax PST DDATA divu w lt ea gt y Dx PST 0x1 PST 0x9 DD source operand eor l Dy lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination eori lt data gt Dx PST 0x1 ext l Dx PST 0x1 ext w Dx PST Ox1 extb Dx PST 0x1 illegal PST 0x1 jmp lt ea gt y PST 0x5 PST 0x9 0xA 0xB DD target address jsr lt ea gt y PST 0x5 PST 0x9 0xA 0xB DD target address PST OXB DD destination operand lea l lt ea gt y Ax PST 0x1 link w Ay lt displacement gt PST 0x1 PST OxB DD destination operand Isl l Dy lt data gt Dx PST 0x1 Isr Dy lt data gt Dx PST 0x1 mov3g l lt data gt lt ea gt x PST 0x1 0xB destination operan
198. he high order part of the address the second contains the low order part of the address Generation EA Given Assembler Syntax xxx L EA Mode Field 111 EA Register Field 001 Number of Extension Words 2 15 0 First Extension Word Address High 15 0 Second Extension Word Address Low 31 y 0 Operand Pointer Contents Points to Memory Operand Figure 2 13 Absolute Long Addressing 2 2 12 Immediate Data In this addressing mode the operand is in 1 or 2 extension words Table 2 2 lists the location of the operand within the instruction word format The immediate data format is as follows Table 2 2 Immediate Operand Location Operation Length Location Byte Low order byte of the extension word Word Entire extension word Longword High order word of the operand is in the first extension word the low order word is in the second extension word Generation Operand given Assembler Syntax lt XXX gt EA Mode Field 111 EA Register Field 100 Number of Extension Words 1or2 Figure 2 14 Immediate Data Addressing M mororoLa Chapter 2 Addressing Capabilities 2 9 Stack 2 2 13 Effective Addressing Mode Summary Effective addressing modes are grouped according to the mode use Data addressing modes refer to data operands Memory addressing modes refer to memory operands Alterable addressing modes refer to alterable writable operands Control addressing m
199. he low order 16 bits are implemented When MASK is loaded the low order 16 bits of the source operand are loaded into the register When it is stored the upper 16 bits are forced to all ones When used by an instruction this register is ANDed with the specified operand address Thus MASK allows an operand address to be effectively constrained within a certain range defined by the 16 bit value This feature minimizes the addressing support required for filtering convolution or any routine that implements a data array as a circular queue using the Ay addressing mode For MAC with load operations the MASK contents can optionally be included in all memory effective address calculations 1 4 EMAC User Programming Model The following paragraphs describe the registers for the optional ColdFire EMAC unit Figure 1 8 illustrates the user programming model for the EMAC unit It contains the following registers e One 32 bit MAC status register MACSR including four indicator bits signaling product or accumulation overflow one for each accumulator PAVO PAV3 e Four 32 bit accumulators ACCx ACCO ACC1 ACC2 ACC3 e Eight 8 bit accumulator extensions two per accumulator packaged as two 32 bit values for load and store operations ACCext01 ACCext23 e One 32 bit mask register MASK 31 0 MACSR MAC status register ACCO MAC accumulator 0 ACC1 MAC accumulator 1 ACC2 MAC accumulator 2 ACC3 MAC accumulator 3
200. i6 Ax 101 reg number Ax d46 PC En dg Ax Xi dg PC Xi 8 6 ColdFire Family Programmer s Reference Manual M MOTOROLA HALT Halt the CPU HALT All ColdFire Processors Operation If Supervisor State Then Halt the Processor Core Else Privilege Violation Exception Assembler Syntax HALT Attributes Unsized Description The processor core is synchronized meaning all previous instructions and bus cycles are completed and then halts operation The processor s halt status is signaled on the processor status output pins PST O0xF If a GO debug command is received the processor resumes execution at the next instruction Note that this instruction synchronizes the pipeline The opcode for HALT is Ox4AC8 Note that setting CSR UHE through the debug module allows HALT to be executed in user mode Condition Codes Not affected Instruction 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format oo Os ro a Bee Foie co M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 7 NTO U C H Instruction Fetch Touch I NTO U C H Supported Starting with V4 Operation If Supervisor State then Instruction Fetch Touch at Ay else Privilege Violation Exception Assembler Syntax INTOUCH Ay Attributes Unsized Description Generates an instruction fetch reference at address Ay If the referenced address space is a cacheable region thi
201. iate result RM For positive overflow largest positive normalized number For negative overflow ce RP For positive overflow oo For negative overflow largest negative normalized number Exception 1 The result written to the destination is the same as for the exception disabled case unless the enabled exception occurred on a FMOVE OUT in which case the destination is unaffected If desired the user OVFL handler can overwrite the default result 11 1 10 Underflow UNFL An underflow exception occurs when the intermediate result of an arithmetic instruction is too small to be represented as a normalized number in a floating point register or memory using the selected rounding precision that is when the intermediate result exponent is less than or equal to the minimum exponent value of the selected rounding precision Underflow can only occur when the destination format is single or double precision When the destination is byte word or longword the conversion underflows to zero without causing an underflow or an operand error At the end of any operation that could underflow the intermediate result is checked for underflow rounded and checked for overflow before it is stored in the destination FPSR UNEFL is set if underflow occurs If the underflow exception is disabled FPSR INEX is also set Even if the intermediate result is large enough to be represented as a double precision number an underflow can occur if the m
202. ield Specifies a destination register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 5 6 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE MOVE from MACSR Move from the from MACSR MACSR Operation MACSR Destination Assembler Syntax MOVE L MACSR Rx Attributes Size longword Description Moves the MACSR register contents into a general purpose register Rx Rx 31 8 are cleared MACSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 0 0 1 1 0 0 0 Register Rx Instruction Field e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 7 MOVE MOVE from MASK Move from the from MASK MAC MASK Register Operation MASK Destination Assembler Syntax MOVE L MASK Rx Attributes Size longword Description Moves the MASK register contents into a general purpose register Rx Rx 31 16 are set to OxFFFF MACSR Not affected Instruction 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 1 0 1 1 0 0 0 Register Rx Instruction Field e Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 5 8 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE MACSR MOVE MACSR to CCR Move from the to CCR MACSR to the CCR O
203. ier die see Divide by Zer DZ enterregel i Inexact Result INEX naiss teen uns V4 Changes to the Exception Processing Model Chapter 12 Processor Instruction Summary Appendix A S Record Output Format ColdFire Family Programmer s Reference Manual Page Number M MOTOROLA ILLUSTRATIONS Figure E Page Number Titig Number 1 1 ColdFire Family User Programming Model 1 2 1 2 Condition Code Registet CER saint beendet ea etn ES Lin SG 1 3 1 3 ColdFire Family Floating point Unit User Programming Model 1 4 1 4 Floating Point Control Register FPCR neen enneenneeenveeenveenn 1 4 1 5 Floating Point Status Register FPSR us 1 5 1 6 MAC Unit Programming Model sn voorseerse reden seesstewsestaetounstenensetedanmestadenansdeadnnesens 1 7 1 7 MAC Status Register MACSR q tn tot min ese arend esn siennes 1 7 1 8 EMAC Programming Model iccisssavsasasssssccassacaavascevedeaspsraceetsccccdassacsataseusaceesnaccaatensns 1 8 1 9 MAC Status Register MACSR sastre dede td 1 9 1 10 EMAC Fractional Aleman nt oan senen ende dan ni net sad sega RARE 1 10 1 11 EMAC Signed and Unsigned Integer Alignment nnen eeen seenneennenn 1 10 1 12 Accumulator 0 and 1 Extensions ACCextO 1 eenen nerven eneen 1 11 1 13 Accumulator 2 and 3 Extensions ACCextO 1 eenen nere ee eren enenenn 1 11 1 14 Supervisor Programming MOAB ss nemer an es ee rt t a eine tien 1 12 1 15 SAS R SISTER RSS ES ee Neenee 1 13 1 16 Vector Base Reg
204. ing Point State ColdFire Processors with an FPU Operation If in Supervisor State Then FPU Internal State lt ea gt x Else Privilege Violation Exception Assembler syntax FSAVE lt ea gt x Attributes Unsized Description After allowing completion of any floating point operation in progress FSAVE saves the FPU internal state in a frame at the effective address After a save operation FPCR is cleared and the FPU is in idle state until the next instruction executes The first longword written to the state frame includes the format field data Floating point operations in progress when an FSAVE is encountered complete before FSAVE executes which then creates an IDLE state frame if no exceptions occurred otherwise an EXCP state frame is created State frames in Table 8 2 apply Table 8 2 State Frames State Description NULL An FSAVE generating this state frame indicates the FPU state was not modified because the last processor reset or FRESTORE with a NULL state frame This indicates that the programmer s model is in reset state with NANS in floating point data registers and zeros in FPCR FPSR and FPIAR Stores of the system registers FSAVE and FMOVEM stores do not cause the FPU change from NULL to another state IDLE An FSAVE that generates this state frame indicates the FPU finished in an idle condition and is without pending exceptions waiting for the initiation of the next instruction EXCP An FSAVE gen
205. ing Point Unit FPU User Instructions 7 3 Conditional Testing Table 7 3 FPCC Encodings Data Type N Z l NAN Normalized or Denormalized 0 0 0 0 Normalized or Denormalized 1 0 0 0 0 0 1 0 0 0 1 1 0 0 Infinity 0 0 1 0 Infinity 1 0 1 0 NAN 0 0 0 1 NAN 1 0 0 1 The inclusion of the NAN data type in the IEEE floating point number system requires each conditional test to include FPCC NAN in its boolean equation Because it cannot be determined whether a NAN is bigger or smaller than an in range number that is it is unordered the compare instruction sets FPCC NAN when an unordered compare is attempted All arithmetic instructions that result in a NAN also set the NAN bit Conditional instructions interpret NAN being set as the unordered condition The IEEE 754 standard defines the following four conditions e Equal to EQ e Greater than GT e Less than LT e Unordered UN The standard requires only the generation of the condition codes as a result of a floating point compare operation The FPU can test for these conditions and 28 others at the end of any operation affecting condition codes For floating point conditional branch instructions the processor logically combines the 4 bits of the FPCC condition codes to form 32 conditional tests 16 of which cause an exception if an unordered condition is present when the conditional test is attempted IEEE nonaware
206. instructions consist of 1 to 3 words Figure 2 1 illustrates the general composition of an instruction The first word of the instruction called the operation word or opword specifies the length of the instruction the effective addressing mode and the operation to be performed The remaining words further specify the instruction and operands These words can be conditional predicates immediate operands extensions to the effective addressing mode specified in the operation word branch displacements bit number or special register specifications trap operands argument counts or floating point command words The ColdFire architecture instruction word length is limited to 3 sizes 16 32 or 48 bits Operation Word One Word Specifies Operation and Modes Extension Word If Any Extension Word If Any Figure 2 1 Instruction Word General Format An instruction specifies the function to be performed with an operation code and defines the location of every operand The operation word format is the basic instruction word see Figure 2 2 The encoding of the mode field selects the addressing mode The register field contains the general register number or a value that selects the addressing mode when the M mororoLA Chapter 2 Addressing Capabilities 2 1 Effective Addressing Modes mode field 111 Some indexed or indirect addressing modes use a combination of the operation word followed by an extension word Figure 2 2 i
207. int number Operation En Source Destination Table In Range Zero Infinity Result Integer 0 0 0 0 inf inf 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 See Table 7 2 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM O Source Specifier Destination Register FPx 7 18 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FINT Floating Point Integer FINT Instruction fields Source Effective Address field Determines the addressing mode for external operands If R M 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi dg PC Xi
208. int arithmetic instruction is encountered this is called a pre instruction exception Exceptions set during a floating point store to memory or to an integer register are taken immediately post instruction exception Note that FMOVE is considered an arithmetic instruction because the result is rounded Only FMOVE with any destination other than a floating point register sometimes called FMOVE OUT can generate post instruction exceptions Post instruction exceptions never write the destination After a post instruction exception processing continues with the next instruction M mororoLa Chapter 11 Exception Processing 11 9 Overview A floating point arithmetic exception becomes pending when the result of a floating point instruction sets an FPSR EXC bit and the corresponding FPCR ENABLE bit is set A user write to the FPSR or FPCR that causes the setting of an exception bit in FPSR EXC along with its corresponding exception enabled in FPCR leaves the FPU in an exception pending state The corresponding exception is taken at the start of the next arithmetic instruction as a pre instruction exception Executing a single instruction can generate multiple exceptions When multiple exceptions occur with exceptions enabled for more than one exception class the highest priority exception is reported and taken It is up to the exception handler to check for multiple exceptions The following multiple exceptions are possible e Operand err
209. ion Assembler Syntax BSET sz Dy lt ea gt x BSET sz lt data gt lt ea gt x Attributes Size byte longword Description Tests a bit in the destination operand and sets CCR Z appropriately then sets the specified bit in the destination operand When a data register is the destination any of the 32 bits can be specified by a modulo 32 bit number When a memory location is the destination the operation is a byte operation and the bit number is modulo 8 In all cases bit 0 refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate Bit number is specified in the second word of the instruction 2 Register Specified data register contains the bit number Condition X N Z V C X Not affected Codes N Not affected Z Set if the bit tested is zero cleared otherwise V Not affected C Not affected Bit Number Static Specified as Immediate Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction 0 0 0 0 1 0 0 0 1 1 Destination Effective Address Format Mode Register 0 0 0 0 0 0 0 0 Bit Number 4 20 ColdFire Family Programmer s Reference Manual M MOTOROLA BSET BSET Test a Bit and Set Instruction Fields e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note th
210. ions bit manipulation 3 8 cache maintenance 3 10 data movement 3 4 descriptions 7 7 floating point arithmetic 3 11 format 2 1 integer arithmetic 3 5 logical 3 7 processor summary 12 1 program control 3 8 results exceptions 7 6 set 12 2 12 5 additions 3 12 shift 3 7 summary 3 1 system control 3 10 Index 7 Integer arithmetic instructions 3 5 Integer data formats general 1 16 in memory 1 22 in registers 1 20 Integer unit user programming model 1 1 Integer user instructions 4 1 4 84 L Logical instructions 3 7 MAC accumulator ACC 1 8 mask register MASK EMAC 1 11 MAC 1 8 status register MACSR EMAC 1 8 MAC 1 7 user instructions 5 1 5 16 user programming model 1 7 Memory integer data formats 1 22 MMU base address register MMUBAR 1 14 Modes address register indirect postincrement 2 4 regular 2 6 indirect with displacement 2 5 addressing absolute long 2 9 absolute short 2 8 direct address register 2 3 data register 2 3 effective addressing 2 2 2 10 indirect address register 2 3 predecrement address register 2 4 program counter 2 6 2 7 Module base address register MBAR 1 15 Multiply accumulate data formats 1 20 N Normalized numbers 1 17 O Operand error OPERR 11 12 Operation code map 9 1 Organization of data in registers 1 20 Overflow OVFL 11 13 Index 8 ColdFire Family Programmer s Reference Manual INDEX P Processor cros
211. ire Family Programmer s Reference Manual M MOTOROLA LSL LSR Logical Shift LSL LSR All ColdFire Processors Operation Destination Shifted By Count Destination Assembler Syntax LSd L Dy Dx LSd L lt data gt Dx where d is direction L or R Attributes Size longword Description Shifts the bits of the destination operand Dx in the direction L or R specified The size of the operand is a longword CCR C receives the last bit shifted out of the operand The shift count is the number of bit positions to shift the destination register and may be specified in two different ways 1 Immediate The shift count is specified in the instruction shift range is 1 8 2 Register The shift count is the value in the data register Dy specified in the instruction modulo 64 The LSL instruction shifts the operand to the left the number of positions specified as the shift count Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the low order bit CCRIC Operand 0 LSL CCR X lt The LSR instruction shifts the operand to the right the number of positions specified as the shift count Bits shifted out of the low order bit go to both the carry and the extend bits zeros are shifted into the high order bit 0 gt Operand gt CCRIC LSR gt CCR X
212. is always set If the name is enclosed in brackets the bit is set or cleared as appropriate If the name is not given the operation always clears the bit FCMP always clears the infinity bit because it is not used by any conditional predicate equations Operation rae Source Destination 2 AV m Table In Range Zero Infinity In Range NZ none none none N none 7 NZ N NIN none Zero N none Z ZIN none LIN none NZ NZIN none Infinity none none none none Z none _IN NIN NIN NZ 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number NOTE The NAN bit is not shown because NANSs are always handled in the same manner see Section 1 7 1 4 Not A Number FPSR FPCC See preceding operation table FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 Set if either operand is denormalized land the operands are not exactly the same and IDE is disabled cleared otherwise 7 14 ColdFire Family Programmer s Reference Manual M MOTOROLA FCMP FPSR AEXC Instruction 15 14 13 Format Floating Point Compare Instruction Descriptions FCMP See Section 7 1 Floating Point Status Register FPSR 12 11 10 9 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 Source Effective Address Mode Register 0 IRM 0 Sourc
213. is contained in the two extension words with the first extension word bits 15 0 containing the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z Vv C X Not affected Codes x 0 0 N Set if the msb of the result is set cleared otherwise al Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 1 0 1 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Register field Destination data register Dx 4 34 ColdFire Family Programmer s Reference Manual M MOTOROLA EXT EXTB Sign Extend EXT EXTB All ColdFire Processors Operation Destination Sign Extended Destination Assembler Syntax EXT W Dx extend byte to word EXT L Dx extend word to longword EXTB L Dx extend byte to longword Attributes Size word longword Description Extends a byte in a data register Dx to a word or a longword or a word in a data register to a longword by replicating the sign bit to the left When the EXT operation extends a byte to a word bit 7 of the designated data register is copied to bits 15 8 of the data register When the EXT operation extends a word to a longword bit 15 of the designated data register is copied to bits 31 16 of the data register The EXTB form copies bit 7 of the designated register to bits 31 8
214. is typically zero Attempting an RTE using this old format generates a format error on a ColdFire processor If the format field defines a valid type the processor does the following 1 Reloads the SR operand 2 Fetches the second longword operand 3 Adjusts the stack pointer by adding the format value to the auto incremented address after the first longword fetch 4 Transfers control to the instruction address defined by the second longword operand in the stack frame When the processor executes a FRESTORE instruction if the restored FPU state frame contains a nonsupported value execution is aborted and a format error exception is generated 15 24 31 64 255 32 47 Interrupt Trap Interrupt exception processing with interrupt recognition and vector fetching includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8 bit interrupt vector Executing a Trap instruction always forces an exception and is useful for implementing system calls The trap instruction may be used to change from user to supervisor mode ColdFire Family Programmer s Reference Manual M MOTOROLA Overview Table 11 3 Exceptions Continued Vector Number Type Description 48 55 Floating point See Section 11 1 4 Floating Point Arithmetic Exceptions 61 Unsupported Executing a valid DIV MAC or EMAC instruction when the required optional hardware instructio
215. ister FPx 0011010 1011010 or 1011110 FDIV OxF2 15 14 13 12 11 10 9 8 5 4 3 2 1 0 Source Effective Address 0 R M 0 Source Specifier Destination Opmode Register FPx 0100000 1100000 or 1100100 FADD OxF2 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx 0100010 1100010 or 1100110 9 16 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map FMUL OxF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Register FPx 0100011 1100011 or 1100111 FSUB OxF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Source Effective Address 0 R M 0 Source Specifier Destination Opmode Register FPx 0101000 1101000 or 1101100 FCMP OxF2 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination 0 1 1 1 0 0 0 Register FPx FTST OxF2 A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination 0 1 1 1 0 1 0 Register FPx FBcc OxF2 15 14
216. ister Rw where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W an Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 15 MSAC Multiply Subtract with Load MSAC Instruction Fields continued 5 16 Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 sz field Specifies the size of the input operands 0 word longword Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1 10 reserved 11 product gt gt 1 U Lx U Ly Specifies which 16 bit operand of the source register Rx Ry is used for a word sized operation lower word 1 upper word Mask field Specifies whether or not to use the MASK register in generating the source effective address lt ea gt y 0 do not use MASK use M
217. ister VBR Sc dd aan 1 14 1 17 MMU Base Address Register MMUBAR ennen 1 15 1 18 Module Base Address Register MBAR ss 1 16 1 19 Normalized Number Pormati s inner St UE RS eek ites 1 17 1 20 Zero Formats tn antenne nine tn nd 1 17 1 21 RM Formaten ee Len Sn TR Re nn 1 17 1 22 Notea Numiber Format seance benee 1 18 1 23 Denormalized Number Format seated eelde 1 18 1 24 Two s Complement Signed Fractional Equation 1 20 1 25 Organization of Integer Data Format in Data Registers aanne eeen neven 1 21 1 26 Organization of Addresses in Address Registers ennen enneeeeneeerenverenn 1 21 1 27 Memory Operand Adresse Es nee ne eed 1 22 1 28 Memory Organization for Integer Operands ss 1 22 2 1 Instruction Word General Format An neede daden 2 1 2 2 Instruction Word Specification Formats 2 2 2 3 Data Register DIe atd dies cats cuca daken eden ded kanaat Res ne 2 3 2 4 Address Register Direct issoria eei seaeasdeavinandesnsecuonnnecsanedobaabdeannccaunsevens 2 3 2 5 Address IRE Sis be MIT CE cai NK 2 4 2 6 Address Register Indirect with Postincrement 2 4 2 7 Address Register Indirect with Predecrement onne enne eeneveeneeenn 2 5 2 8 Address Register Indirect with Displacement 2 5 M MOTOROLA Illustrations ix Figure Number 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 7 1
218. ith the format S or D an OPERR is impossible With the format B W or L an OPERR is possible only on a conversion to integer overflow or if the source is either an infinity or a NAN On integer overflow and infinity source cases the largest positive or negative integer that can fit in the specified destination format B W or L is stored In the NAN source case a constant of all ones is written to the destination Enabled The result written to the destination is the same as for the exception disabled case unless the exception occurred on a FMOVE OUT in which case the destination is unaffected OVFL Disabled The values stored in the destination based on the rounding mode defined in FRCR MODE RN Infinity with the sign of the intermediate result RZ Largest magnitude number with the sign of the intermediate result RM For positive overflow largest positive normalized number For negative overflow oo RP For positive overflow oo For negative overflow largest negative normalized number Enabled The result written to the destination is the same as for the exception disabled case unless the exception occurred on a FMOVE OUT in which case the destination is unaffected UNFL Disabled The stored result is defined below UNFL also sets INEX if the UNFL exception is disabled RN Zero with the sign of the intermediate result RZ Zero with the sign of the intermediate result RM For positive underflow 0 For negative under
219. ive address These operands are used by the ColdFire debug module to write one of the debug control registers DRc Note that this instruction synchronizes the pipeline The memory location defined by the effective address must be longword aligned otherwise undefined operation results The debug command must be organized in memory as shown on the next page Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 1 0 1 1 1 1 Source Effective Address Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Instruction Field e Source Effective Address field Specifies the address lt ea gt y for the operation use only the addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy ox W Ay xxx L Ay 010 reg number Ay lt data gt Ay Ay d 6 AY 101 reg number Ay d46 PC dg Ay Xi dg PC Xi M MOTOROLA Chapter 8 Supervisor Privileged Instructions WDEBUG Debug Command Organization in Memory Write Debug Control Register WDEBUG 15 14 13 12 11 10 9 8 7 6 0 0 1 0 1 1 0 0 1 0 0 DRc Data 31 16 Data 15 0 Unused where e Bits 15 4 of the first word define the WDREG command to the debug module
220. ivide by zero 9 INEX Inexact result 8 IDE Input is denormalized 7 0 AEXC Accrued exception byte At the end of arithmetic operations EXC bits are logically combined to form an AEXC value that is logically ORed into the existing AEXC byte FBcc only updates IOP This operation creates sticky floating point exception bits in AEXC that the user can poll only at the end of a series of floating point operations A sticky bit is one that remains set until the user clears it 7 IOP Invalid operation 6 OVFL Overflow 5 UNFL Underflow 4 DZ Divide by zero 3 INEX Inexact result 2 0 Reserved should be cleared For AEXC OVFL AEXC DZ and AEXC INEX the next value is determined by ORing the current AEXC value with the EXC equivalent as shown in the following e Next AEXC OVFL Current AEXC OVFL EXC OVFL e Next AEXC DZ Current AEXC DZ EXC DZ e Next AEXC INEX Current AEXC INEX EXC INEX For AEXC IOP and AEXC UNFL the next value is calculated by ORing the current AEXC value with EXC bit combinations as follows e Next AEXC IOP Current AEXC IOP EXC BSUN INAN OPERR e Next AEXC UNFL Current AEXC UNFL EXC UNFL amp INEX Table 7 2 shows how the FPSR EXC bits are affected by instruction execution 7 2 ColdFire Family Programmer s Reference Manual AA MOTOROLA Conditional Testing Table 7 2 FPSR EXC Bits EXC Bit Description BSUN
221. la products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Technical Information Center 1 800 521 6274 HOME PAGE http www motorola com semiconductors Document Comments FAX 512 9335 2625 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com NetComm http www motorola com ColdFire Motorola Inc 2001 All rights reserved Introduction Addressing Capabilities Ins
222. lacement gt W SP 4 gt SP Ay gt SP SP Ay SP d SP MOV3Q lt data gt lt ea gt x L Immediate Data Destination MOVCLR ACCy Rx L Accumulator Destination 0 Accumulator MOVE lt ea gt y lt ea gt x B W L Source Destination MACcr Dx L where MACcr can be any MAC control register lt ea gt y MACcr L ACCx ACCext01 ACCext23 MACSR MASK MOVE from CCR CCR Dx W MOVE to CCR lt ea gt y CCR W MOVEA lt ea gt y Ax W L gt L Source Destination MOVEM list lt ea gt x L Listed Registers Destination lt ea gt y list Source Listed Registers MOVEQ lt data gt Dx BoL Immediate Data Destination mvs lt ea gt y Dx B W Source with sign extension Destination MVZ lt ea gt y Dx B W Source with zero fill Destination PEA lt ea gt y L SP 4 SP lt ea gt y SP UNLK Ax none Ax SP SP Ax SP 4 SP Supported starting with V4 2 EMAC instruction 3 Additional addressing modes supported starting with V4 3 1 2 Integer Arithmetic Instructions The integer arithmetic operations include 5 basic operations ADD SUB MUL DIV and REM They also include CMP CLR and NEG The instruction set includes ADD CMP and SUB instructions for both address and data operations The CLR instruction applies to all sizes of data operands Signed and unsigned MUL DIV and REM instructions include e word multiply to produce a longword product e longword multiply to produce a l
223. llowing table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L Ay lt data gt 111 100 Ay Ay dig Ay di6 PC dg Ay Xi Due dg PC Xi esi 6 20 ColdFire Family Programmer s Reference Manual M MOTOROLA MSAC Multiply Subtract MSAC Operation ACCx Ry Rx lt lt gt gt SF ACCx Assembler syntax MSAC sz Ry U L Rx U L SRACCx Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 40 bit result then subtract this product shifted as defined by the scale factor from an accumulator If 16 bit operands are used the upper or lower word of each register must be specified Condition N Z V PAVx EV N Set if the msb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if a product or accumulation overflow is MACSR generated or PAVx 1 cleared otherwise PAVx Set if a product or accumulation overflow is generated unchanged otherwise EV Setif accumulation overflows lower 32 bits in integer mode or lower 40 bits in fractional mode cleared otherwise Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 DE l1 0 Register Rx 0 ACC Rx 0 o Register Ry Isb msb SZ Scale 1 U Lx U L
224. llustrates two formats used in an instruction word Table 2 1 lists the field definitions Operation Word Format X X X X X X X X X X Effective Address Mode Register Extension Word Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D A Register W L Scale 0 Displacement Figure 2 2 Instruction Word Specification Formats Table 2 1 defines instruction word formats Table 2 1 Instruction Word Format Field Definitions Field Definition Instruction Mode Addressing mode see Table 2 3 Register General register number see Table 2 3 Extensions D A Index register type 0 Dn 1 An W L Word longword index size 0 Address Error Exception 1 Longword Scale Scale factor 00 1 01 2 10 4 11 8 supported only if FPU is present 2 2 Effective Addressing Modes Besides the operation code that specifies the function to be performed an instruction defines the location of every operand for the function Instructions specify an operand location in one of the three following ways e A register field within an instruction can specify the register to be used e An instruction s effective address field can contain addressing mode information 2 2 ColdFire Family Programmer s Reference Manual M MOTOROLA Effective Addressing Modes e The instruction s definition can imply the use of
225. lowing table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 For the destination operand lt ea gt x use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx ox W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d16 AX 101 reg number Ax di6 PC dg Ax Xi 110 reg number Ax dg PC Xi M mororoLA Chapter 4 Integer User Instructions 4 63 ORI Inclusive OR ORI All ColdFire Processors Operation Immediate Data Destination Destination Assembler Syntax ORI L lt data gt Dx Attributes Size longword Description Performs an inclusive OR operation on the immediate data and the destination operand and stores the result in the destination data register Dx The size of the operation is specified as a longword The size of the immediate data is specified as a longword Note that the immediate data is contained in the two extension words with the first extension word bits 15 0 cont
226. lt ea gt y FPx B W L S D Source FPx FPx round destination to double FPU FPy FPx D FDNEG lt ea gt y FPx B W L S D Source FPx round destination to double FPU FPy FPx D FPx D FPx gt FPx round destination to double FDSQRT lt ea gt y FPx B W L S D Square Root of Source FPx round destination FPU FPy FPx D to double FPx D Square Root of FPx FPx round destination to double FDSUB lt ea gt y FPx B W L S D FPx Source FPx round destination to double FPU FPy FPx D FINT lt ea gt y FPx B W L S D Integer Part of Source FPx FPU FPy FPx D FPx D Integer Part of FPx FPx FINTRZ lt ea gt y FPx B W L S D Integer Part of Source FPx round to zero FPU FPy FPx D FPx D Integer Part of FPx FPx round to zero FMOVE lt ea gt y FPx B W L S D Source Destination FPU FPy lt ea gt x B W L S D FPy FPx D FPcr lt ea gt x L FPcr can be any floating point control register lt ea gt y FPcr L FPCR FPIAR FPSR FMOVEM list lt ea gt x D Listed registers Destination FPU lt ea gt y list Source Listed registers FMUL lt ea gt y FPx B W L S D Source FPx FPx FPU FPy FPx D FNEG lt ea gt y FPx B W L S D Source gt FPx FPU FPy FPx D FPx D FPx FPx FNOP none none PC 2 PC FPU Pipeline Synchronized FPU FSABS lt ea gt y FPx B WL S D Absolute Value of Source FPx round FPU FPy FPx D destination to single FPx D Absolute Value of FPx FPx round destination to singl
227. ltiply Accumulate Unit EMAC User Instructions Chapter 7 Floating Point Unit FPU User Instructions 7 1 Floating Point Status Register FPSR neons eeneeeeneeenn 7 1 322 Conditional Testing ire Ga ande asid 7 3 71 3 Instruction Results when Exceptions Occur essseseseesessrssreeressersresrresreseeseresee 7 6 74 Instruction Deserupti Ons ethnie nds AR ee ae R Eee 7 7 Chapter 8 Supervisor Privileged Instructions Chapter 9 Instruction Format Summary 9 1 Operation Gode Maps Meteo nt nt ten VE te dealen 9 1 Chapter 10 PST DDATA Encodings 10 1 User InStCHCUON SOLE etende hete 10 1 10 2 Supervisor Instruction Set incendie 10 7 Chapter 11 Exception Processing 11 1 OMCIVIEW Len nn Ne nd sus tas cn de as stone ce 11 1 11 1 1 Supervisor User Stack Pointers A7 and OTHER A7 11 4 M MOTOROLA Contents vii Paragraph Number 11 1 2 11 1 3 11 1 4 11 1 5 11 1 6 11 1 7 11 1 8 11 1 9 11 1 10 11 1 11 11 1 12 11 1 13 A l A 2 A 3 viii S Record Content S Record Types S Record Creation CONTENTS Title Exception Stack Frame Definition Processor Exceptions sssssesseesrsereeressereresreesersresereseeseeseeesee Floating Point Arithmetic Exceptions nnen Branch Set on Unordered BSUN ae en Input Not A Number INAN eneen Input Denormalized Number IDE cece ceeeeeeeeereeeneeeee Op rand Error OPERR scsatensa sini Overflow OVEL ns Underflow UNBEE ren
228. mation stored in the exception stack frame located at the top of the stack into the processor The instruction examines the stack format field in the format offset word to determine how much information must be restored Upon returning from exception the processor is in user mode if SR S 0 when it is loaded from memory otherwise the processor remains in supervisor mode Note that this instruction synchronizes the pipeline The opcode for RTE is 0x4E73 Condition Codes Set according to the condition code bits in the status register value restored from the stack Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format lo Phe ee Po ae et pte on M MOTOROLA Chapter 8 Supervisor Privileged Instructions 8 15 STOP Load Status Register and Stop STOP All ColdFire Processors Operation If Supervisor State Then Immediate Data SR STOP Else Privilege Violation Exception Assembler Syntax STOP lt data gt Attributes Unsized Description Moves the immediate word operand into the status register both user and supervisor portions advances the program counter to point to the next instruction and stops the fetching and executing of instructions A trace interrupt or reset exception causes the processor to resume instruction execution A trace exception occurs if instruction tracing is enabled TO 1 when the STOP instruction begins execution or if bit 15 of the immediate
229. mber Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 MVS V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported B W ColdFire Family Programmer s Reference Manual M MOTOROLA MVZ Move with Zero Fill MVZ Supported starting with V4 Operation Source with zero fill Destination Assembler Syntax MVZ sz lt ea gt y Dx Attributes Size byte word Description Zero fill the source operand and move to the destination register For the byte operation the source operand is moved to bits 7 0 of the destination and bits 31 8 are filled with zeros For the word operation the source operand is moved to bits 15 0 of the destination and bits 31 16 are filled with zeros Not affected Always cleared Set if the result is zero cleared otherwise Always cleared Always cleared Condition X N Z V C Codes ds 0 0 O lt NZX Instruction 15 14 13 12 11 10 9 8 7 6 Ce sud us Instruction Fields 5 4 3 2 1 0 Source Effective Address e Register field Specifies the destination data register Dx e Size field Specifies the size of the operation byte operation 1 word operation e Source Effective Address field Specifies the source operand lt ea gt y use the following data addressing modes
230. ment UNLK 0x4E5 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 Register Ax MOVE to USP 0x4E6 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 0 Register Ay M MOTOROLA Chapter 9 Instruction Format Summary 9 7 Operation Code Map MOVE from USP 0x4E6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 0 1 Register Ax NOP Ox4E71 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 STOP Ox4E72 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 Immediate Data RTE 0x4E73 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 RTS Ox4E75 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 MOVEC 0x4E7B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 D A Register Ry Control Register Rc JSR 0x4E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 1 0 Source Effective Address Mode Register JMP 0x4E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 1 1 Source Effecti
231. mode M mororoLA Chapter 2 Addressing Capabilities 2 7 Effective Addressing Modes Generation EA PC Xi ScaleFactor Sign extended dg Assembler Syntax dg PC Xi Size Scale EA Mode Field 111 EA Register Field 011 Number of Extension Words 1 31 0 Program Counter Contents 31 7 0 Displacement Sign Extension Integer A 31 0 Index Register Sign Extended Value Scale Scale Value X 31 0 Operand Pointer Contents Points to Memory Operand Figure 2 11 Program Counter Indirect with Scaled Index and 8 Bit Displacement 2 2 10 Absolute Short Addressing Mode In this addressing mode the operand is in memory and the address of the operand is in the extension word The 16 bit address is sign extended to 32 bits before it is used Generation EA Given Assembler Syntax xxx W EA Mode Field 111 EA Register Field 000 Number of Extension Words 1 31 15 0 Extension Word Sign Extension Integer 31 y 0 Operand Pointer Contents Points to Memory Operand Figure 2 12 Absolute Short Addressing 2 8 ColdFire Family Programmer s Reference Manual M MOTOROLA Effective Addressing Modes 2 2 11 Absolute Long Addressing Mode In this addressing mode the operand is in memory and the operand address occupies the two extension words following the instruction word in memory The first extension word contains t
232. n Converts the source operand to double precision if necessary and calculates the square root of that number Stores the result in the destination floating point data register FPx This function is not defined for negative operands FSQRT rounds the result to the precision selected in the FPCR FSFSQRT and FDFSQRT round the result to single or double precision respectively regardless of the rounding precision selected in the FPCR Operation ae Source Destination Table In Range Zero Infinit g y Result Jx NAN 0 0 0 0 inf NAN 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number 2 Sets the OPERR bit in the FPSR exception byte FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 Set if the source operand is 0 0 0 See not 0 and is negative cleared Table 7 2 otherwise FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM 0 Source Specifier Destination Opmode Register FPx 7 38 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FSQ RT Floating Point Square Root FSQ RT Instruction fields Effective address
233. n When the destination is byte word or longword the conversion underflows to zero without causing an underflow or an operand error DZ Set if a FDIV instruction is attempted with a zero divisor cleared otherwise INEX Set under the following conditions e If the infinitely precise mantissa of a floating point intermediate result has more significant bits than can be represented exactly in the selected rounding precision or in the destination format e If an input operand is a denormalized number and the input denorm exception IDE is disabled e An overflowed result e An underflowed result with the underflow exception disabled Cleared otherwise 7 2 Conditional Testing Unlike operation dependent integer condition codes an instruction either always sets FPCC bits in the same way or does not change them at all Therefore instruction descriptions do not include FPCC settings This section describes how FPCC bits are set FPCC bits differ slightly from integer condition codes An FPU operation s final result sets or clears FPCC bits accordingly independent of the operation itself Integer condition codes bits CCR N and CCR Z have this characteristic but CCR V and CCR C are set differently for different instructions Table 7 3 lists FPCC settings for each data type Loading FPCC with another combination and executing a conditional instruction can produce an unexpected branch condition M mororoLA Chapter 7 Float
234. n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 0 Count or dr 1 0 ir 0 O Register Dx Register Dy Instruction Fields e Count or Register field Specifies shift count or register Dy that contains the shift count Ifi r 0 this field contains the shift count values 1 7 represent counts of 1 7 a value of zero represents a count of 8 Ifi r 1 this field specifies the data register Dy that contains the shift count modulo 64 e dr field specifies the direction of the shift 0 shift right shift left e i r field If i r 0 specifies immediate shift count If i r 1 specifies register shift count e Register field Specifies a data register Dx to be shifted 4 12 ColdFire Family Programmer s Reference Manual M MOTOROLA Bcc BranchConditionally Bcc All ColdFire Processors L supported starting with V4 Operation If Condition True Then PC dp PC Assembler Syntax Bcc sz lt label gt Attributes Size byte word longword longword supported starting with V4 Description If the condition is true execution continues at PC displacement Branches can be forward with a positive displacement or backward with a negative displacement PC holds the address of the instruction word for the Bcc instruction plus two The displacement is a two s complement integer that represents the relative distance in bytes from the current PC to the destinati
235. n 7 1 Floating Point Status Register FPSR 7 16 ColdFire Family Programmer s Reference Manual M MOTOROLA FDIV Instruction 5 14 Floating Point Divide Instruction Descriptions FDIV Format 1 1 Register FPx 13 12 11 10 9 6 5 1 0 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 R M 0 Source Specifier Destination Opmode Instruction fields e Effective Address field Specifies the addressing mode for external operands If R M 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes listed in the following table can be used 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros e R M field Specifies the source operand address mode The operation is lt ea gt y to register The operation is register to register Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi e Source specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M
236. n module is not present can generate a non supported instruction exception Control is then passed to an exception handler that can then process the opcode as required by the system This exception can be generated by the attempted execution of DIV MAC or EMAC instructions as follows 1 On newer V2 cores without DIV MAC or EMAC units 2 On newer V3 cores without a MAC or EMAC unit The divide unit is not optional on V3 3 On newer V4 cores attempting EMAC instructions without an EMAC unit The MAC and divide units are not optional on V4 although the MAC unit can be replaced with an EMAC Note that this exception will never be generated by the current ColdFire standard products The 5202 5204 and 5206 do not support this exception The 5206e 5272 5307 and 5407 all have divide and MAC units All of these devices will generate an unimplemented line a exception if an EMAC instruction is attempted 11 1 4 Floating Point Arithmetic Exceptions This section describes floating point arithmetic exceptions Table 11 4 lists these exceptions in order of priority Table 11 4 Exception Priorities Priority Exception Branch set on unordered BSUN Input Not a Number INAN Input denormalized number IDE Operand error OPERR Overflow OVFL Underflow UNFL Divide by zero DZ Inexact INEX CO N om A MW ND Most floating point exceptions are taken when the next floating po
237. n selected in FPCR Operation Table PER Source Destination In Range Zero Infinity Result Absolute Value Absolute Value Absolute Value 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL UNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 0 FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Source Effective Address Mode Register 0 IRM 0 Source Specifier Destination Opmode Register FPx M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 9 Instruction Descriptions FABS Floating Point Absolute Value FA BS Instruction fields e Source Effective Address field Determines the addressing mode for external operands If RM 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes listed in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi
238. nated with the 32 bit virtual address ASID is only available if a device has an MMU Refer to a specific device or core user s manual for further information 1 5 6 Access Control Registers ACRO ACR3 The access control registers ACR 0 3 define attributes for four user defined memory regions ACRO and ACRI control data memory space and ACR2 and ACR3 control instruction memory space Attributes include definition of cache mode write protect and buffer write enables Not all ColdFire processors implement all four ACRs Bit functions and positions may vary among ColdFire processor implementations Refer to a specific device or core user s manual for further information 1 5 7 MMU Base Address Register MMUBAR MMUBAR shown in Figure 1 17 defines a memory mapped privileged data only space with the highest priority in effective address attribute calculation for the data internal memory bus that is the MMUBAR has priority over RAMBARO If virtual mode is enabled any normal mode access that does not hit in the MMUBAR RAMBARs ROMBARs or ACRs is considered a normal mode virtual address request and generates its access attributes from the MMU MMUBAR is only available if a device has an MMU 1 14 ColdFire Family Programmer s Reference Manual M MOTOROLA Supervisor Programming Model Refer to a specific device or core user s manual for further information 31 16 15 1 0 BA V Figure 1 17 MMU Base Address Register
239. nd Pointer Contents Points to Memory Operand Figure 2 8 Address Register Indirect with Displacement M mororoLA Chapter 2 Addressing Capabilities 2 5 Effective Addressing Modes 2 2 7 Address Register Indirect with Scaled Index and 8 Bit Displacement Mode This addressing mode requires one extension word that contains an index register indicator possibly scaled and an 8 bit displacement The index register indicator includes size and scale information In this mode the operand is in memory The operand address is the sum of the address register contents the sign extended displacement value in the extension word s low order 8 bits and the scaled index register s sign extended contents Users must specify the address register the displacement the scale factor and the index register in this mode Generation EA An Xi ScaleFactor Sign extended dg Assembler Syntax dg An Xi Size Scale EA Mode Field 110 EA Register Field Register number Number of Extension Words 1 31 0 Address Register Contents 31 7 0 Displacement Sign Extension Integer 5 31 0 Index Register Sign Extended Value Scale Scale Value X 31 y 0 Operand Pointer Contents Points to Memory Operand Figure 2 9 Address Register Indirect with Scaled Index and 8 Bit Displacement 2 2 8 Program Counter Indirect with Displacement Mode In this mode the ope
240. ned by the accumulator and accumulator extension words when the EMAC is operating in fractional mode The upper 8 bits of the extended product are sign extended from the 40 bit result taken from the product M MOTOROLA Chapter 1 Introduction 1 9 EMAC User Programming Model 32 Operand Y 32 X Operand X 40 24 Product es EE Fee 8 40 Extended Product 8 32 8 Accumulator Upper Extension Byte 7 0 Accumulator 31 0 Lower Extension Byte 7 0 Figure 1 10 EMAC Fractional Alignment Figure 1 11 shows the data contained by the accumulator and accumulator extension words when the EMAC is operating in signed or unsigned integer mode In signed mode the upper 8 bits of the extended product are sign extended from the 40 bit result taken from the product In unsigned mode the upper 8 bits of the extended product are all zeros Operand Y 32 X Operand X 24 8 32 Product 8 8 32 Extended Product it 8 8 32 Accumulator Upper Extension Byte 7 0 Lower Extension Byte 7 0 Accumulator 31 0 Figure 1 11 EMAC Signed and Unsigned Integer Alignment 1 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Supervisor Programming Model 1 4 3 Accumulator Extensions ACCext01 ACCext23 The 32 bit accumulator extension registers ACCext01 ACCext23 allow the complete contents of the 48 bit accumulator to be sav
241. nen enne enneevenneren 1 4 Floating Point Status Register FPSR nnee eeens ev ennervennereenn 1 5 Floating Point Instruction Address Register FPIAR 1 6 MAC User Programming Model nnn aoon neee onseevenseevenseevenseevense 1 7 MAC Status Register MACSR annen M dede ee 1 7 MAC Accumulator CS loen vendere Mech lie ca ann eee be 1 8 MAC Mask Register MASK tonisnensiersinndetuntenstaheaasdintansedeerssehtalsastades 1 8 EMAC User Programming Model 1 8 MAC Status Register MACSR on b ta intenses dites iteete ss 1 8 MAG Accumulators ACC 023 Tintin nina e 1 9 Accumulator Extensions ACCext01 ACCext23 eneen 1 11 MAC Mask Register MASK sh ee et 1 11 Supervisor Programming Modele smerende dieten anale se ede 1 11 Status Resister SR nd nn At este 1 12 Supervisor User Stack Pointers A7 and OTHER A7 1 13 Vector Base Register VBR nana danse 1 14 Cache Control Register CACR nue tienen hansie ses den ee 1 14 Address Space Identifier AS UD Es Sn nn ie nee 1 14 Access Control Registers ACRO ACR3 1 14 MMU Base Address Register MMUBAR neer 1 14 RAM Base Address Registers RAMBARO RAMBAR I 1 15 ROM Base Address Registers ROMBARO ROMBARI 1 15 Module Base Address Register MBAR eee ennen 1 15 Integer Data Formats Sr nn n ent EE T EEE 1 16 Floating Point Data Formats nn A ates 1 16 Floating Point Data TY
242. ng Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 52 ColdFire Family Programmer s Reference Manual M MOTOROLA MULS Signed Multiply MULS Instruction 15 Format 0 Longword 14 13 12 11 10 8 7 6 5 4 3 2 1 0 1 1 1 0 0 Source Effective Address Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 0 0 0 Instruction Fields Longword e Source Effective Address field Specifies the source operand use only data addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC dg Ay Xi dg PC Xi e Register field Specifies a data register Dx for the destination operand the 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this register M MOTOROLA Chapter 4 Integer User Instructions 4 53 MULU
243. ng that three character pairs 3 bytes follow 0000 Address field zeros FC Checksum of the S9 record Each printable character in an S record encodes in hexadecimal ASCII in this example representation of the binary bits that transmit Figure A 2 illustrates the sending of the first S1 record Table A 2 lists the ASCII code for S records Type Record Length Address Code Data Checksum S 1 1 3 0 0 0 0 2 8 5 F ij 2 A 0101001 1 007 1 0001 001 1 000 1 001 1 007 1 001 1100001001 1100000071 110000001 110000 0011001001000001 Figure A 2 Transmission of an S1 Record A 4 ColdFire Family Programmer s Reference Manual M MOTOROLA S Record Creation Table A 2 ASCII Code Least Significant Most Significant Digit Digit k 3 A 0 NUL DLE SP 0 P p 1 SOH DC1 1 A Q a a 2 STX DC2 2 B R b r 3 ETX DC3 3 C S c s 4 EOT DC4 4 D T d t 5 ENQ NAK 5 E U e u 6 ACK SYN amp 6 F V f v 7 BEL ETB 7 G W g w 8 BS CAN 8 H X h a 9 HT EM 9 Y i y A LF SUB i J Z j z B VT ESC K k C FF FS i lt L D CR GS M m E SO RS gt N A n F Sl US O o DEL M mororoLa Appendix A S Record Output Format A 5 S Record Creation A 6 ColdFire Family Programmer s Reference Manual M MOTOROLA A Access control registers ACRO ACR3 1 14 Accumulator EMAC 1 9 extensions ACCext0
244. nly utilize S records serving the program s purpose For more information on support of specific S records refer to the user s manual for that program An S record format module may contain S records of the following types SO The header record for each block of S records The code data field S1 S2 S3 S5 S7 S8 S9 may contain any descriptive information identifying the following block of S records The header record can be used to designate module name version number revision number and description information The address field is normally zeros A record containing code data and the 2 byte address at which the code data is to reside A record containing code data and the 3 byte address at which the code data is to reside A record containing code data and the 4 byte address at which the code data is to reside A record containing the number of S1 S2 and S3 records transmitted in a particular block This count appears in the address field There is no code data field A termination record for a block of S3 records The address field may optionally contain the 4 byte address of the instruction to which control is to be passed There is no code data field A termination record for a block of S2 records The address field may optionally contain the 3 byte address of the instruction to which control is to be passed There is no code data field A termination record for a block of S1 records The address field
245. nn Se ee tel oan Gael 1 19 2 1 Instruction Word Format Field Definitions ennen eenn eeen ne enneenneeenveeenveenn 2 2 2 2 Immediate Operand Location ssl en uanddantsauanacsedeedeavanteoas 2 9 2 3 Effective Addressing Modes and Categories 2 10 3 1 INotatiOnial ONVENLLONS seeden AEN ee ala aad 3 2 3 2 Data Movement Operation Format sns tenen 3 5 3 3 Integer Arithmetic Operation FOTMAbP E End sente MR once GERS te 3 6 3 4 Logical Operation Pormat o iiiijscsisaseacadstsevcaciaasaccevs Qeseataduncaceaed es cetatbecsand tabiacteawacedeaseoens 3 7 3 5 Shift Operation Format EE Sn RE Reese fn 3 8 3 6 Bit Manipulation Operation Format ss 3 8 3 7 Program Control Operation Format nn sn alee eee 3 9 3 8 System Control Operation Format denderende tnieliseiei entes 3 10 3 9 Cache Maintenance Operation Format 258 4 cs ereen dea 3 11 3 10 Dyadic Floating Point Operation Format 3 11 3 11 Dyadic Floating Point Operations ss 3 11 3 12 Monadic Floating Point Operation Format ss 3 12 3 13 Monadic Floating Point Operations 3 12 3 14 ColdFire User Instruction Set Summary nnen made aetna oauaawted 3 12 3 15 ColdFire Supervisor Instruction Set Summary 3 17 3 16 ColdFire ISA_B Additions Summary s 3 18 3 17 MAC Instruction Set Summary ind urines ins r e 3 19 3 18 EMAC Instruction Set Enhancements Summary 3 19 3 19 Floating Point Instruction Set Summary
246. nstruction An attempt to divide by zero results in a divide by zero exception and no registers are affected The resulting exception stack frame points to the offending divide opcode If overflow is detected the destination register is unaffected An overflow occurs if the quotient is larger than a 16 bit W or 32 bit L unsigned integer Condition X N Z V C X Not affected Codes 0 N Cleared if overflow is detected otherwise set if the quotient is negative cleared if positive Z Cleared if overflow is detected otherwise set if the quotient is zero cleared if nonzero V Set if an overflow occurs cleared otherwise C Always cleared Instruction 15 14 13 132 ii 10 9 8 7 6 5 4 3 2 14 0 Format 1 0 0 0 Register Dx 0 1 1 Source Effective Address Word Mode Register M mororoLA Chapter 4 Integer User Instructions 4 31 DIVU Instruction Fields Word Unsigned Divide e Register field Specifies the destination register Dx DIVU e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 1
247. nstructions 4 21 BSR Branch to Subroutine BSR All ColdFire Processors L supported starting with V4 Operation SP 4 SP nextPC SP PC d PC Assembler Syntax BSR sz lt label gt Attributes Size byte word longword longword supported starting with V4 Description Pushes the longword address of the instruction immediately following the BSR instruction onto the system stack Branches can be forward with a positive displacement or backward with a negative displacement The PC contains the address of the instruction word plus two Program execution then continues at location PC displacement The displacement is a two s complement integer that represents the relative distance in bytes from the current PC to the destination PC If the 8 bit displacement field in the instruction word is 0 a 16 bit displacement the word immediately following the instruction is used If the 8 bit displacement field in the instruction word is all ones 0xFF the 32 bit displacement longword immediately following the instruction is used A branch to the next immediate instruction automatically uses the 16 bit displacement format because the 8 bit displacement field contains 0x00 zero offset Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Format o l1 1 0 0 lolo li 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displaceme
248. nt if 8 bit displacement OxFF Instruction Fields e _8 bit displacement field Two s complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed e 16 bit displacement field Used for displacement when the 8 bit displacement contains 0x00 e 32 bit displacement field Used for displacement when the 8 bit displacement contains OxFF BSR V2 V3 Core ISA_A V4 Core ISA_B Opcode present Yes Yes Operand sizes supported B W B W L 4 22 ColdFire Family Programmer s Reference Manual AA MOTOROLA BTST BTST Test a Bit All ColdFire Processors Operation lt bit number gt of Destination CCR Z Assembler Syntax BTST sz Dy lt ea gt x BTST sz lt data gt lt ea gt x Attributes Size byte longword Description Tests a bit in the destination operand and sets CCR Z appropriately When a data register is the destination any of the 32 bits can be specified by a modulo 32 bit number When a memory location is the destination the operation is a byte operation and the bit number is modulo 8 In all cases bit O refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate Bit number is specified in a second word of the instruction 2 Register Specified data register contains the bit number Condition X N Z V C Codes Not affected Not affected Set if the bit tes
249. nt is 16 bits and is sign extended before use e Conditional predicate field Specifies a conditional test defined in Table 7 4 NOTE A BSUN exception causes a pre instruction exception to be taken If the handler does not update the stack frame PC image to point to the instruction after FBcc it must clear the NAN bit or disable the BSUN trap or the exception recurs on returning M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 13 Instruction Descriptions FCMP Floating Point Compare FCMP Operation FPx Source Assembler Syntax FCMP fmt lt ea gt y FPx FCMP D FPy FPx Attributes Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and subtracts the operand from the destination floating point data register The result of the subtraction is not retained but is used to set floating point condition codes as described in Section 7 2 Conditional Testing Note that if either operand is denormalized it is treated as zero Thus two denormalized operands will compare as equal set FPCC Z even if they are not identical This situation can be detected with INEX or IDE The entries in this table differ from those for most floating point instructions For each combination of input operand types condition code bits that may be set are indicated If a condition code bit name is given and is not enclosed in brackets it
250. number Ay Ay 100 reg number Ay di6 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi dg PC Xi Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros R M field Specifies the source operand address mode The operation is lt ea gt y to register 0 The operation is register to register Source specifier field Specifies the source register or data format If RM 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy Destination register field Specifies the destination floating point register FPx If R M 0 and the source and destination fields are equal the input operand is taken from the specified floating point data register and the result is written into the same register If the single register syntax is used Motorola assemblers set the source and destination fields to the same value Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0011010 FNEG Rounding precision specified by the FPCR 1011010 FSNEG Single precision rounding 1011110 FDNEG Double precision rounding ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FNOP No Operation FNOP Operation None Assembler syntax FNOP Attributes Unsized Description FNOP pe
251. o program visible 32 bit registers does not uniquely identify one as the SSP and the other as the USP Rather the hardware uses one 32 bit register as the currently active A7 and the other as OTHER A7 Thus the register contents are a function of the processor operating mode if SR S 1 then A7 Supervisor Stack Pointer other_A7 User Stack Pointer else A7 User Stack Pointer other_A7 Supervisor Stack Pointer The BDM programming model supports reads and writes to A7 and OTHER A7 directly It is the responsibility of the external development system to determine the mapping of A7 and OTHER A7 to the two program visible definitions SSP and USP based on the setting of SR S This functionality is enabled by setting by the dual stack pointer enable bit CACR DSPE If this bit is cleared only the stack pointer A7 defined for previous ColdFire versions is available DSPE is zero at reset If DSPE is set the appropriate stack pointer register SSP or USP is accessed as a function of the processor s operating mode To support dual stack pointers the following two privileged MC680x0 instructions to load store the USP are added to the ColdFire instruction set architecture as part of ISA_B mov l Ay USP move to USP opcode 0x4E6 0xxx mov l USP Ax move from USP opcode 0x4E6 1xxx The address register number is encoded in the low order three bits of the opcode 11 1 2 Exception Stack Frame Definition The first long
252. oaded in step 2 Note that because ColdFire processors do not support hardware stacking of multiple exceptions it is the responsibility of the operating system to check for trace mode after processing other exception types For example when a TRAP instruction executes in trace mode the processor initiates the TRAP exception and passes control to the corresponding handler If the system requires a trace exception the TRAP exception handler must check for this condition SR 15 in the exception stack frame set and pass control to the trace handler before returning from the original exception M MOTOROLA Chapter 11 Exception Processing 11 7 Overview Vector Number Type Table 11 3 Exceptions Continued Description 10 11 12 13 Unimplemented line a opcode Unimplemented line f opcode Debug A line a opcode results when bits 15 12 of the opword are 1010 This exception is generated by the attempted execution of an undefined line a opcode as well as under the following conditions On an early V2 core or device 5202 5204 5206 when attempting to execute a MAC or EMAC instruction e On a later V2 core or device 5206e 5272 when attempting to execute an EMAC instruction On an early V3 core or device 5307 when attempting to execute an EMAC instruction A line f opcode results when bits 15 12 of the opword are 1111 This exception is generated under the following conditions When a
253. ocessor reset or a restore operation of the null state clears the FPSR FPCC m Exception Status Byte EXC AEXC Byte 31 28 27 26 25 24 23 16 15 14 13 12 11 10 9 8 7 6 5 4 3 20 N Z 1 NAN BSUN INAN OPERR OVFL UNFL DZ INEX IDE IOP OVFL UNFL DZ INEX Figure 1 5 Floating Point Status Register FPSR Table 1 3 describes FPSR fields Table 1 3 FPSR Field Descriptions Bits Field Description 31 24 FPCC Floating point condition code byte Contains four condition code bits that are set after completion of all arithmetic instructions involving the floating point data registers 31 28 Reserved should be cleared 27 N Negative M MOTOROLA Chapter 1 Introduction 1 5 Floating Point Unit User Programming Model Table 1 3 FPSR Field Descriptions Continued Bits Field Description 26 FPPC Z Zero Be _ Infinity 24 NAN Not a number 23 16 En Reserved should be cleared during the most recent arithmetic instruction or move operation 15 8 EXC Exception status byte Contains a bit for each floating point exception that might have occurred 15 BSUN Branch set on unordered 14 INAN Input not a number 13 OPERR Operand error 12 OVFL Overflow 11 UNFL Underflow 10 DZ Divide by zero 9 INEX Inexact operation 8 IDE In
254. ode by clearing SR T The occurrence of an interrupt exception also clears SR M and sets the interrupt priority mask SR I to the level of the current interrupt request M mororoLa Chapter 11 Exception Processing 11 1 Overview 2 The processor determines the exception vector number For all faults except interrupts the processor bases this calculation on exception type For interrupts the processor performs an interrupt acknowledge LACK bus cycle to obtain the vector number from peripheral The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address The processor saves the current context by creating an exception stack frame on the system stack V2 and V3 support a single stack pointer in the A7 address register therefore there is no notion of separate supervisor and user stack pointers As a result the exception stack frame is created at a 0 modulo 4 address on top of the current system stack Because V4 supports a supervisor stack pointer SSP the exception stack frame is created at a 0 modulo 4 address on top of the system stack pointed to by the SSP V2 and V3 use a simplified fixed length stack frame shown in Figure 11 1 for all exceptions V4 uses the same fixed length stack frame with additional fault status FS encodings to support the MMU In some exception types the program counter PC in the exception stack frame contains the address of the faulting instructi
255. odes refer to memory operands without an associated size These categories sometimes combine to form new categories that are more restrictive Two combined classifications are alterable memory addressing modes that are both alterable and memory addresses and data alterable addressing modes that are both alterable and data Table 2 3 lists a summary of effective addressing modes and their categories Table 2 3 Effective Addressing Modes and Categories Mode Reg Addressing Modes Syntax Field Field Data Memory Control Alterable Register Direct Data Dn 000 reg no X X Address An 001 reg no X Register Indirect Address An 010 reg no X X X X Address with Postincrement An 011 reg no X X X Address with Predecrement An 100 reg no X X En X Address with Displacement di6 An 101 reg no X X X Address Register Indirect with Scaled Index and 8 Bit Displacement dg An Xi SF 110 reg no X X X X Program Counter Indirect with Displacement d45 PC 111 010 X X X Program Counter Indirect with Scaled Index and 8 Bit Displacement dg PC Xi SF 111 011 X X X Absolute Data Addressing Short xxx W 111 000 X X X Long xxx L 111 001 X X X Immediate lt XXX gt 111 100 X X 2 3 Stack Address register A7 stacks exception frames subroutine calls and returns temporary variable storage and parameter passing and
256. of the source operand lt ea gt y Only the addressing modes listed in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay Wk T es Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi i Only if format is byte word longword or single precision If R M 0 this field is unused and should be all zeros e R M field Specifies the source operand address mode The operation is lt ea gt y to register The operation is register to register e Source specifier field Specifies the source register or data format If RM 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy e Destination register field Specifies the destination floating point register FPx If R M 0 and the source and destination fields are equal the input operand is taken from the specified floating point data register and the result is written into the same register If the single register syntax is used Motorola assemblers set the source and destination fields to the same value M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 21 Instruction Descriptions FMOVE Move Floating Point Data Regis
257. on fault in others the PC contains the next instruction to be executed next If the exception is caused by an FPU instruction the PC contains the address of either the next floating point instruction nextFP if the exception is pre instruction or the faulting instruction fault if the exception is post instruction The processor acquires the address of the first instruction of the exception handler The instruction address is obtained by fetching a value from the exception table at the address in the vector base register The index into the table is calculated as 4 x vector_number When the index value is generated the vector table contents determine the address of the first instruction of the desired handler After the fetch of the first opcode of the handler is initiated exception processing terminates and normal instruction processing continues in the handler The vector base register described in Section 1 5 3 Vector Base Register VBR holds the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this register to access the vector table VBR 19 0 are not implemented and are assumed to be zero forcing the vector table to be aligned on a 0 modulo 1 Mbyte boundary ColdFire processors support a 1024 byte vector table as shown in Table 11 1 The table contains 256 exception vectors the first 64 of which are defined by Motorola The rest are user defined interr
258. on Moves the data at the source to the destination location and sets the condition codes according to the data The size of the operation may be specified as byte word or longword MOVEA is used when the destination is an address register MOVEQ is used to move an immediate 8 bit value to a data register MOV3Q supported starting with V4 is used to move a 3 bit immediate value to any effective destination address Condition X N Z V C X Not affected Codes 0 0 N Set if result is negative cleared otherwise odes Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 Size Destination Effective Address Source Effective Address Register Mode Mode Register Instruction fields e Size field Specifies the size of the operand to be moved 01 byte operation 11 word operation 10 longword operation 11 reserved e Destination Effective Address field Specifies destination location lt ea gt x the table below lists possible data alterable addressing modes The restrictions on combinations of source and destination addressing modes are listed in the table at the bottom of the next page Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt
259. on Code Register CCR Table 1 1 describes CCR bits Table 1 1 CCR Bit Descriptions Bits Field Description 7 P Branch prediction Version 3 only Alters the static prediction algorithm used by the branch acceleration logic in the instruction fetch pipeline on forward conditional branches Refer to a V3 core or device user s manual for further information on this bit Reserved should be cleared Versions 2 and 4 6 5 Reserved should be cleared 4 X Extend Set to the value of the C bit for arithmetic operations otherwise not affected or set to a specified result 3 N Negative Set if the most significant bit of the result is set otherwise cleared 2 Z Zero Set if the result equals zero otherwise cleared 1 V Overflow Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size otherwise cleared 0 C Carry Set if a carry out of the most significant bit of the operand occurs for an addition or if a borrow occurs in a subtraction otherwise cleared M MOTOROLA Chapter 1 Introduction 1 3 Floating Point Unit User Programming Model 1 2 Floating Point Unit User Programming Model The following paragraphs describe the registers for the optional ColdFire floating point unit Figure 1 3 illustrates the user programming model for the floating point unit It contains the following registers e 8 64 bit floating point data registers
260. on PC If the 8 bit displacement field is 0 a 16 bit displacement the word after the instruction is used If the 8 bit displacement field is OxFF the 32 bit displacement longword after the instruction is used A branch to the next immediate instruction uses 16 bit displacement because the 8 bit displacement field is 0x00 Condition code specifies one of the following tests where C N V and Z stand for the condition code bits CCR C CCR N CCR V and CCR Z respectively Code Condition Encod Test Code Condition Encot Test ing ing CC HS Carry clear 0100 C LS Lower or same 0011 CIZ CS LO Carry set 0101 C LT Less than 1101 N amp VIN amp V EQ Equal 0111 Z MI Minus 1011 N GE Greater or equal 1100 N amp VIN amp V NE Not equal 0110 Z GT Greater than 1110 N amp V amp ZIN amp VEZ PL Plus 1010 N HI High 0010 C amp Z VC Overflow clear 1000 V LE Less or equal 1111 ZIN amp VIN amp V VS Overflow set 1001 V Condition Codes Not affected M mororoLA Chapter 4 Integer User Instructions 4 13 Bcc Instruction Format 15 Branch Conditionally Bcc 0 Condition 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displacement if 8 bit displacement OxFF Instruction Fields e Condition field Binary encoding for one of the conditions listed in the table e _8 bit displacement field Two s compl
261. on bytes are loaded as shown in the following table Note the position of the LSB of the extension within the combined 48 bit accumulation logic is dependent on the operating mode of the EMAC integer versus fractional Source Data Accumulator Extension Bits Affected 31 24 ACCext3 15 8 23 16 ACCext3 7 0 15 8 ACCext2 15 8 7 0 ACCext2 7 0 MACSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 1 1 1 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay 001 reg number Ay xxx L nu Ay En lt data gt 111 100 Ay Ay d16 Ay die PC dg Ay Xi dg PC Xi LL 6 18 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE to MACSR MOVE to MACSR Move to the MAC Status Register Operation Source MACSR Assembler Syntax MOVE L Ry MACSR MOVE L lt data gt MACSR Attributes Description Moves a 32 bit value from a register or an immediate operand into the MACSR Size longword MACSR 1 14 13 12 1 10 9 8 7 6 5 4 3 2 4 0
262. ondition DZ Description Exception 0 The destination floating point data register is written with infinity with the sign set to the exclusive disabled OR of the signs of the input operands Exception 1 The destination floating point data register is written as in the exception is disabled case enabled 11 1 12 Inexact Result INEX An INEX exception condition exists when the infinitely precise mantissa of a floating point intermediate result has more significant bits than can be represented exactly in the selected rounding precision or in the destination format If this condition occurs FPSR INEX is set and the infinitely precise result is rounded according to Table 11 13 Table 11 13 Inexact Rounding Mode Values Mode Result RN The representable value nearest the infinitely precise intermediate value is the result If the two nearest representable values are equally near the one whose Isb is 0 even is the result This is sometimes called round to nearest even RZ The result is the value closest to and no greater in magnitude than the infinitely precise intermediate result This is sometimes called chop mode because the effect is to clear bits to the right of the rounding point RM The result is the value closest to and no greater than the infinitely precise intermediate result possibly co RP The result is the value closest to and no less than the infinitely precise intermediate res
263. ondition Basically an operand error occurs when an operation has no mathematical interpretation for the given operands Table 11 8 lists possible operand errors When one occurs FPSR OPERR is set Table 11 8 Possible Operand Errors Instruction Condition Causing Operand Error FADD oo or ce 2 FDIV 0 0 or oo co FMOVE OUT to B W or L Integer overflow source is NAN or FMUL One operand is 0 and the other is FSQRT Source is lt 0 or c FSUB 20 0 or 20 2 Table 11 9 describes results when the exception is enabled and disabled Table 11 9 OPERR Exception Enabled Disabled Results Condition OPERR Description Exception 0 When the destination is a floating point data register the result is a double precision NAN disabled With its mantissa set to all ones and the sign set to zero positive For a FMOVE OUT instruction with the format S or D an OPERR exception is impossible With the format B W or L an OPERR exception is possible only on a conversion to integer overflow or if the source is either an infinity or a NAN On integer overflow and infinity source cases the largest positive or negative integer that can fit in the specified destination size B W or L is stored In the NAN source case a constant of all ones is written to the destination Exception 1 The result written to the destination is the same as for the exception dis
264. ongword byte word supported starting with V4 Description Operates similarly to CMP but is used when the source operand is immediate data The operation size can be byte word or longword The size of the immediate data matches the operation size Note that if size byte the immediate data is contained in bits 7 0 of the single extension word If size word the immediate data is contained in the single extension word bits 15 0 If size longword the immediate data is contained in the two extension words with the first extension word bits 15 0 containing the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z V C X Not affected Codes N Set if the result is negative cleared otherwise s Z Set if the result is zero cleared otherwise V Set if an overflow occurs cleared otherwise C Set if a borrow occurs cleared otherwise Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 1 1 0 0 Size 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Register field Specifies the destination register Dx e Size field Specifies the size of the operation 00 byte operation O1 word operation 10 longword operation 11 reserved CMPI V2 V3 Core ISA _A V4 Core ISA _B Opcode present Yes Yes Operand sizes supported L B W L 4 28 ColdFire
265. ongword product e longword divided by a word with a word quotient and word remainder e longword divided by a longword with a longword quotient e longword divided by a longword with a longword remainder REM M MOTOROLA Chapter 3 Instruction Set Summary 3 5 Instruction Summary A set of extended instructions provides multiprecision and mixed size arithmetic ADDX SUBX EXT and NEGX For devices with the optional MAC or EMAC unit MAC and MSAC instructions are available Refer to Table 3 3 for a summary of the integer arithmetic operations In Table 3 3 X refers to the X bit in the CCR Table 3 3 Integer Arithmetic Operation Format Instruction Operand Syntax Operand Size Operation ADD Dy lt ea gt x L Source Destination Destination lt ea gt y Dx L ADDA lt ea gt y Ax L ADDI lt data gt Dx L Immediate Data Destination Destination ADDQ lt data gt lt ea gt x L ADDX Dy Dx L Source Destination CCR X Destination CLR lt ea gt X B W L 0 Destination CMP lt ea gt y Dx B W L Destination Source CCR CMPA lt ea gt y Ax W L CMPI lt data gt Dx B W L Destination Immediate Data gt CCR DIVS DIVUS lt ea gt y Dx W L Destination Source Destination Signed or Unsigned EXT Dx BOW Sign Extended Destination Destination Dx WoL EXTB Dx BoL MAC Ry RxSF ACCx W L ACCx Ry Rx lt lt gt gt SF gt ACCx Ry RxS
266. operand is a 1 If an interrupt request is asserted with a priority higher than the priority level set by the new status register value an interrupt exception occurs otherwise the interrupt request is ignored External reset always initiates reset exception processing The STOP command places the processor in a low power state Note that this instruction synchronizes the pipeline The opcode for STOP is 0x4E72 followed by the immediate data Condition X N Z V C X Set to the value of bit 4 of the immediate data Codes N Set to the value of bit 3 of the immediate data gt Z Set to the value of bit 2 of the immediate data V Set to the value of bit 1 of the immediate data C Set to the value of bit 0 of the immediate data Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 Immediate Data Instruction Field e Immediate Data field Specifies the data to be loaded into the status register 8 16 ColdFire Family Programmer s Reference Manual M MOTOROLA WDEBUG WDEBUG Write Debug Control Register All ColdFire Processors Operation If Supervisor State Then Write Control Register Command Executed in Debug Module Else Privilege Violation Exception Assembler Syntax WDEBUG L lt ea gt y Attributes Size longword Description Fetches two consecutive longwords from the memory location defined by the effect
267. operation table differs from other operation tables A letter in a table entry indicates that FTST always sets the designated condition code bit All unspecified condition code bits are cleared during the operation FPSR FPCC See Section 7 2 Conditional Testing FPSR BSUN INAN IDE OPERR OVFL JUNFL DZ INEX EXC 0 See Table 7 2 0 0 0 0 Set if denormalized and IDE is disabled cleared otherwise FPSR AEXC See Section 7 1 Floating Point Status Register FPSR Instruction 5 14 4 3 2 1 0 iis EE eN 1 1 0 1 0 0 IRM O Source Specifier Destination Register FPx 7 42 ColdFire Family Programmer s Reference Manual AA MOTOROLA Instruction Descriptions FTST Test Floating Point Operand FTST Instruction fields Effective address field Determines the addressing mode for external operands If R M 1 this field specifies the source operand location lt ea gt y Only modes in the following table can be used 7 Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay di6 Ay 101 reg number Ay d46 PC 111 010 dg Ay Xi dg PC Xi Only if format is byte word longword or single precision If R M 0 this field is unused and must be
268. or OPERR and inexact result INEX e Overflow OVFL and inexact result INEX e Underflow UNFL and inexact result INEX e Divide by zero DZ and inexact result INEX e Input denormalized number IDE and inexact result INEX e Input not a number INAN and input denormalized number IDE In general all exceptions behave similarly If the exception is disabled when the exception condition exists no exception is taken a default result is written to the destination except for BSUN exception which has no destination and execution proceeds normally If an enabled exception occurs the same default result above is written for pre instruction exceptions but no result is written for post instruction exceptions An exception handler is expected to execute FSAVE as its first floating point instruction This also clears FPCR which keeps exceptions from occurring during the handler Because the destination is overwritten for floating point register destinations the original floating point destination register value is available for the handler on the FSAVE state frame The address of the instruction that caused the exception is available in the FPIAR When the handler is done it should clear the appropriate FPSR exception bit on the FSAVE state frame then execute FRESTORE If the exception status bit is not cleared on the state frame the same exception occurs again Alternatively instead of executing FSAVE an exception handler could
269. or field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1 10 reserved 11 product gt gt 1 U Lx U Ly Specifies which 16 bit operand of the source register Rx Ry is used for a word sized operation lower word 1 upper word Mask field Specifies whether or not to use the MASK register in generating the source effective address lt ea gt y 0 do not use MASK use MASK Register Ry field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 9 5 MOVE MOVE from ACC Move from from ACC Accumulator Operation Accumulator Destination Assembler syntax MOVE L ACC Rx Attributes Size longword Description Moves a 32 bit value from the accumulator into a general purpose register Rx When operating in fractional mode MACSR F I 1 if MACSR S U is set the accumulator contents are rounded to a 16 bit value and stored in the lower 16 bits of the destination register Rx The upper 16 bits of the destination register are zero filled The value of the accumulator is not affected by this rounding operation MACSR Not affected Instruction i5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 o 1 olo al 1 1 olo 0 Register Rx Instruction Field e Register Rx f
270. or or user mode 12 M Master interrupt state Cleared by an interrupt exception It can be set by software during execution of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer 11 Reserved should be cleared 10 8 l Interrupt priority mask Defines the current interrupt priority Interrupt requests are inhibited for all priority levels less than or equal to the current priority except the edge sensitive level 7 request which cannot be masked 7 0 CCR Condition code register see Figure 1 2 and Table 1 1 1 5 2 Supervisor User Stack Pointers A7 and OTHER_A7 The V2 and V3 architectures support a single stack pointer A7 The initial value of A7 is loaded from the reset exception vector address offset 0 The V4 architecture supports two independent stack pointer A7 registers the supervisor stack pointer SSP and the user stack pointer USP This support provides the required isolation between operating modes as dictated by the virtual memory management scheme provided by the memory management unit MMU Note that a device without an MMU such as V2 and V3 has a single stack pointer The hardware implementation of these two programmable visible 32 bit registers does not uniquely identify one as the SSP and the other as the USP Rather the hardware uses one 32 bit register as the currently active A7 and the other as OTHER_ A7 Thus the register contents are a function of
271. ormat 0111010 tfotfotfotfo fit li To Instruction Field e Register field Specifies the destination data register Dx M MOTOROLA Chapter 8 Supervisor Privileged Instructions 0 Register Dx 8 9 MOVE MOVE from USP move from User Stack Pointer from USP Supported Starting with V4 Operation If Supervisor State Then USP Destination Else Privilege Violation Exception Assembler Syntax MOVE L USP Ax Attributes Size longword Description Moves the contents of the user stack pointer to the specified address register If execution of this instruction is attempted on a V2 or V3 device or on the MCF5407 an illegal instruction exception will be taken This instruction will execute correctly on other V4 devices if CACR EUSP is set Condition Codes Not affected Instruction 15 14 13 12 Ei 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 1 0 0 1 1 0 1 Register Ax Instruction Field e Register field Specifies the destination address register Ax MOVE from USP V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported L 8 10 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE to SR Operation Attributes MOVE Move to the Status Register to SR All ColdFire Processors If Supervisor State Then Source SR Else Privilege Violation Exception Assembler Syntax MOVE W lt ea gt y SR Size word Description Moves the data in the
272. ource operand and l Dy lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination andi lt data gt Dx PST 0x1 asl Dy lt data gt Dx PST 0x1 asr l Dy lt data gt Dx PST 0x1 bcc b w if taken then PST 0x5 else PST 0x1 bchg b l lt data gt lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bchg b l Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l lt data gt lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination belr b Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bra b w PST 0x5 bset b lt data gt lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bset b l Dy lt ea gt x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bsr b w l PST 0x5 PST 0xB DD destination operand btst b l lt data gt lt ea gt x PST 0x1 PST 0x8 DD source operand btst b l Dy lt ea gt x PST 0x1 PST 0x8 DD source operand clr b lt ea gt X PST 0x1 PST 0x8 DD destination operand cir l lt ea gt X PST 0x1 PST 0xB DD destination operand clr w lt ea gt X PST 0x1 PST 0x9 DD destination operand cmp b lt ea gt y Dx PST 0x1 0x8 source operand cmp l lt ea gt y Dx PST 0x1 PST 0xB DD source operand cmp w lt ea gt y Dx PST 0x1 0x9 source operand cmpa l lt ea
273. ource register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy Destination register field Specifies the destination floating point register FPx Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0101000 FSUB Rounding precision specified by the FPCR 1101000 FSSUB Single precision rounding 1101100 FDSUB Double precision rounding M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 41 Instruction Descriptions FTST Test Floating Point Operand FTST Operation Source Operand Tested FPCC Assembler syntax FTST fmt lt ea gt y FTST D FPy Attributes Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and sets the condition code bits according to the data type of the result Note that for denormalized operands FPCC Z is set because denormalized numbers are normally treated as zero When Z is set INEX is set if the operand is a denormalized number and IDE is disabled INEX is cleared if the operand is exactly zero 1 Operation LE Source Destination Table In Range Zero Infinity Result none NIZ NZ NI 1 If the source operand is a NAN refer to Section 1 7 1 4 Not A Number Note that the
274. ovide illegal instruction detection on extension words of any instruction including MOVEC Attempting to execute an instruction with an illegal extension word causes undefined results Divide by zero Attempting to divide by zero causes an exception vector 5 offset 0x014 Note that this exception cannot be generated unless the device has a divide unit Privilege violation Caused by attempted execution of a supervisor mode instruction while in user mode Trace Trace mode which allows instruction by instruction tracing is enabled by setting SR T If SR T is set instruction completion for all but the STOP instruction signals a trace exception The STOP instruction has the following effects 1 The instruction before the STOP executes and then generates a trace exception In the exception stack frame the PC points to the STOP opcode 2 When the trace handler is exited the STOP instruction is executed loading the SR with the immediate operand from the instruction 3 The processor then generates a trace exception The PC in the exception stack frame points to the instruction after STOP and the SR reflects the value loaded in the previous step If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets SR T hardware loads the SR and generates a trace exception The PC in the exception stack frame points to the instruction after STOP and the SR reflects the value l
275. peration MACSR CCR Assembler Syntax MOVE L MACSR CCR Attributes Size longword Description Moves the MACSR condition codes into the Condition Code Register The opcode for MOVE MACSR to CCR is OxA9CO MACSR Not affected Condition X N Z V C X Always cleared Codes 0 0 N Set if MACSR N 1 cleared otherwise odes Z Set if MACSR Z 1 cleared otherwise V Set if MACSR V 1 cleared otherwise C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 44 3 2 1 0 Format 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 9 MOVE to ACC MOVE to ACC Moveto Accumulator Operation Source Accumulator Assembler syntax MOVE L Ry ACC MOVE L lt data gt ACC Attributes Size longword Description Moves a 32 bit value from a register or an immediate operand into the accumulator Condition N Z V N Set if the msb of the result is set cleared otherwise Codes 0 Z Set if the result is zero cleared otherwise V Always cleared MACSR Instruction 15 14 43 12 t 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 0 0 0 1 0 0 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand lt ea gt y use addressing modes listed in the following table Addressing Mode Mode
276. pulations are executed In addition to the general MOVE instructions there are several special data movement instructions MOV3Q MOVEM MOVEQ MVS MVZ LEA PEA LINK and UNLK MOV3Q MVS and MVZ are ISA _B additions to the instruction set The FMOVE instructions move operands into out of and between floating point data registers FMOVE also moves operands to and from the FPCR FPIAR and FPSR For operands moved into a floating point data register FSMOVE and FDMOVE explicitly select single and double precision rounding of the result FMOVEM moves any combination of floating point data registers Table 3 2 lists the general format of these integer and floating point data movement instructions 3 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Summary Table 3 2 Data Movement Operation Format Instruction Operand Syntax Operand Size Operation FDMOVE FPy FPx D Source Destination round destination to double FMOVE lt ea gt y FPx B W L S D Source Destination FPy lt ea gt x B W L S D FPy FPx D FPcr lt ea gt x L FPer can be any floating point control register FPCR lt ea gt y FPcr L FPIAR FPSR FMOVEM list lt ea gt x D Listed registers Destination lt ea gt y list Source Listed registers FSMOVE lt ea gt y FPx B W L S D Source Destination round destination to single LEA lt ea gt y Ax L lt ea gt y Ax LINK Ay lt disp
277. put denormalization 7 0 AEXC Accrued exception byte Contains 5 exception bits the IEEE 754 standard requires for exception disabled operations These exceptions are logical combinations of bits in the EXC byte AEXC records all floating point exceptions since the user last cleared AEXC 7 IOP Invalid operation 6 OVFL Underflow 5 UNFL Divide By Zero 4 DZ Inexact Operation 3 INEX Input Denormalization 2 0 Reserved should be cleared 1 2 3 Floating Point Instruction Address Register FPIAR The ColdFire operand execution pipeline can execute integer and floating point instructions simultaneously As a result the PC value stacked by the processor in response to a floating point exception trap may not point to the instruction that caused the exception For those FPU instructions that can generate exception traps the 32 bit FPIAR is loaded with the instruction PC address before the FPU begins execution In case of an FPU exception the trap handler can use the FPIAR contents to determine the instruction that generated the exception FMOVE to from the FPCR FPSR or FPIAR and FMOVEM instructions cannot generate floating point exceptions and so do not modify FPIAR A reset or a null restore operation clears FPIAR M MOTOROLA 1 6 ColdFire Family Programmer s Reference Manual MAC User Programming Model 1 3 MAC User Programming Model The following paragraphs describe
278. r CCR Consisting of 5 bits the condition code register CCR the status register s lower byte is the only portion of the SR available in the user mode Many integer instructions affect the CCR and indicate the instruction s result Program and system control instructions also use certain combinations of these bits to control program and system flow 1 2 ColdFire Family Programmer s Reference Manual M MOTOROLA Integer Unit User Programming Model The condition codes meet two criteria 1 Consistency across Instructions meaning that all instructions that are special cases of more general instructions affect the condition codes in the same way Uses meaning that conditional instructions test the condition codes similarly and provide the same results whether a compare test or move instruction sets the condition codes and Instances meaning that all instances of an instruction affect the condition codes in the same way 2 Meaningful results with no change unless it provides useful information Bits 3 0 represent a condition of the result generated by an operation Bit 5 the extend bit is an operand for multiprecision computations Version 3 processors have an additional bit in the CCR bit 7 the branch prediction bit The CCR is illustrated in Figure 1 2 7 6 5 4 38 2 14 0 PP X IN Z2 V je The P bit is implemented only on the V3 core Figure 1 2 Conditi
279. r This field is ignored when using fractional operands 00 none O1 product lt lt 1 10 reserved 11 product gt gt 1 5 2 ColdFire Family Programmer s Reference Manual M MOTOROLA MAC Multiply Accumulate MAC Instruction Fields continued e U Lx Specifies which 16 bit operand of the source register Rx is used for a word sized operation 0 lower word 1 upper word e U Ly Specifies which 16 bit operand of the source register Ry is used for a word sized operation 0 lower word 1 upper word M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 3 MAC MAC Multiply Accumulate with Load Operation ACC Ry Rx lt lt gt gt SF ACC lt ea gt y Rw Assembler syntax MAC sz Ry U L Rx U L SE lt ea gt y amp Rw where amp enables the use of the MASK Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 32 bit result then add this product shifted as defined by the scale factor to the accumulator If 16 bit operands are used the upper or lower word of each register must be specified In parallel with this operation a 32 bit operand is fetched from the memory location defined by lt ea gt y and loaded into the destination register Rw If the MASK register is specified to be used the lt ea gt y operand is ANDed with MASK prior to being used by the instruction Condition N Z V N Set if the m
280. ramming model updates associated with the write instruction are complete The NOP instruction can be used to help identify write access errors A NOP is not executed until all previous operations including any pending writes are complete Thus if any previous write terminates with an access error it is guaranteed to be reported on the NOP V3 Access errors are reported only in conjunction with an attempted store to write protected memory Thus access errors associated with instruction fetch or operand read accesses are not possible V4 If the MMU is disabled access errors are reported only in conjunction with an attempted store to write protected memory Thus access errors associated with instruction fetch or operand read accesses are not possible The condition code register is updated if a write protect error occurs during a CLR or MOV3Q operation to memory Internal memory accesses that fault generate an access error exception MMU TLB misses and access violations use the same fault If the MMU is enabled all TLB misses and protection violations generate an access error exception To quickly determine if a fault is due to a TLB miss or another type of access error new FS encodings described in Table 11 2 signal TLB misses on instruction fetch instruction extension fetch data read and data write ColdFire Family Programmer s Reference Manual M MOTOROLA Overview Table 11 3 Exceptions Continued Vector Numb
281. rand is in memory The address of the operand is the sum of the address in the program counter PC and the sign extended 16 bit displacement integer in the extension word The value in the PC is the address of the extension word PC 2 This is a program reference allowed only for reads 2 6 ColdFire Family Programmer s Reference Manual M MOTOROLA Generation EA PC dig Assembler Syntax d 6 PC EA Mode Field 111 EA Register Field 010 Number of Extension Words 1 Effective Addressing Modes Program Counter 15 Displacement Sign Extension Operand Pointer Memory 31 0 Contents 0 Integer 31 0 Contents Points to Operand Figure 2 10 Program Counter Indirect with Displacement 2 2 9 Program Counter Indirect with Scaled Index and 8 Bit Displacement Mode This mode is similar to the mode described in Section 2 2 7 Address Register Indirect with Scaled Index and 8 Bit Displacement Mode except the PC is the base register The operand is in memory The operand address is the sum of the address in the PC the sign extended displacement integer in the extension word s lower 8 bits and the sized scaled and sign extended index operand The value in the PC is the address of the extension word PC 2 This is a program reference allowed only for reads Users must include the displacement the scale and the index register when specifying this addressing
282. rder by instruction mnemonic Not all instructions are supported by all ColdFire processors DIVS U and REMS U are supported starting with the 5206e The original ColdFire Instruction Set Architecture ISA A is supported by V2 and V3 cores The V4 core supports ISA_B which encompasses all of ISA _ A extends the functionality of some ISA_A instructions and adds several new instructions These extensions can be identified by a table which appears at the end of each instruction description where there are ISA_B differences M mororoLa Chapter 4 Integer User Instructions 4 1 ADD Operation Source Destination Destination Add All ColdFire Processors Assembler Syntax ADD L lt ea gt y Dx ADD L Dy lt ea gt x Attributes Size longword ADD Description Adds the source operand to the destination operand using binary addition and stores the result in the destination location The size of the operation may only be specified as a longword The mode of the instruction indicates which operand is the source and which is the destination as well as the operand size The Dx mode is used when the destination is a data register the destination lt ea gt x mode is invalid for a data register In addition ADDA is used when the destination is an address register ADDI and ADDQ are used when the source is immediate data Condition Codes Instruction Format X N Z V C
283. re 1 22 Not a Number Format If an input operand to an operation is a NAN the result is an FPU created default NAN When the FPU creates a NAN the NAN always contains the same bit pattern in the mantissa all mantissa bits are ones and the sign bit is zero When the user creates a NAN any nonzero bit pattern can be stored in the mantissa and the sign bit 1 7 1 5 Denormalized Numbers Denormalized numbers represent real values near the underflow threshold Denormalized numbers can be positive or negative For denormalized numbers in single and double precision the implied integer bit is a zero See Figure 1 23 LA Exponent 0 Fraction Any nonzero bit pattern Sign of Mantissa 0 or 1 Figure 1 23 Denormalized Number Format Traditionally the detection of underflow causes floating point number systems to perform a flush to zero The IEEE 754 standard implements gradual underflow the result mantissa is shifted right denormalized while the result exponent is incremented until reaching the minimum value If all the mantissa bits of the result are shifted off to the right during this denormalization the result becomes zero Denormalized numbers are not supported directly in the hardware of this implementation but can be handled in software if needed software for the input denorm exception could be written to handle denormalized input operands and software for the underflow exception could create denormalized numbers If the input d
284. re Family Programmer s Reference Manual M MOTOROLA Chapter 10 PST DDATA Encodings This chapter specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction basis In general the PST DDATA output for an instruction is defined as follows PST 0x1 PST 0x8 0x9 0xB DDATA operand where the definition is optional operand information defined by the setting of the CSR The CSR provides capabilities to display operands based on reference type read write or both A PST value 0x8 0x9 or OxB identifies the size and presence of valid data to follow on the DDATA output 1 2 or 4 bytes Additionally for certain change of flow branch instructions CSR BTB provides the capability to display the target instruction address on the DDATA output 2 3 or 4 bytes using a PST value of 0x9 OxA or OxB For V2 and V3 devices PST and DDATA are separate ports and real time trace information is displayed on both ports concurrently Starting with V4 the PST and DDATA outputs are combined into a single port Real time trace information appears as a sequence of 4 bit data values with no alignment restrictions that is the processor status PST values and operands DDATA may appear on either nibble of PSTDDATA 7 0 The upper nibble PSTDDATA 7 4 is the most significant and yields values first Note that the combined PSTDDATA output still displays proce
285. rent devices Table 1 6 Implemented Supervisor Registers by Device Name 5202 5204 See 5272 5307 5407 SR V V V V OTHER_A7 VBR V y V V y V CACR V V V y y V ASID ACRO N N V ACR1 V N N v ACR2 x ACR3 y MMUBAR ROMBARO ROMBAR1 RAMBARO V V V y V RAMBAR1 V MBAR y V V y V 1 5 1 Status Register SR The SR shown in Figure 1 15 stores the processor status the interrupt priority mask and other control bits Supervisor software can read or write the entire SR user software can read or write only SR 7 0 described in Section 1 1 4 Condition Code Register CCR The control bits indicate processor states trace mode T supervisor or user mode S and master or interrupt state M SR is set to 0x27xx after reset 1 12 ColdFire Family Programmer s Reference Manual M MOTOROLA Supervisor Programming Model 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 System byte Condition code register CCR TII S M l pi X N Z VIIc The P bit is implemented only on the V3 core Figure 1 15 Status Register SR Table 1 7 describes SR fields Table 1 7 Status Field Descriptions Bits Name Description 15 T Trace enable When T is set the processor performs a trace exception after every instruction 14 Reserved should be cleared 13 S Supervisor user state Indicates whether the processor is in supervis
286. ress field zeros in this example 48 ASCHH 44 ASCIID 52 ASCIIR 1B The checksum First S1 Record S1 S record type S1 indicating that it is a code data record to be loaded verified at a 2 byte address 13 Hexadecimal 13 decimal 19 indicating that 19 character pairs representing 19 bytes of binary data follow 0000 A 4 character 2 byte address field hexadecimal address 0000 indicating where the data that follows is to be loaded The next 16 character pairs of the first S1 record are the ASCII bytes of the actual program code data In this assembly language example the program hexadecimal opcodes are sequentially written in the code data fields of the S1 records M mororoLa Appendix A S Record Output Format A 3 S Record Creation Opcode Instruction 285F MOVE L A7 A4 245F MOVE L A7 A2 2212 MOVE L A2 D1 226A0004 MOVE L 4 A2 A1 24290008 MOVE L FUNCTION A1 D2 237C MOVE L FORCEFUNC FUNCTION A1 The rest of this code continues in the remaining S1 record s code data fields and stores in memory location 0010 etc 2A The checksum of the first S1 record The second and third S1 records also contain hexadecimal 13 decimal 19 character pairs and end with checksums 13 and 52 respectively The fourth S1 record contains 07 character pairs and has a checksum of 92 S9 Record S9 S record type S9 indicating that it is a termination record 03 Hexadecimal 03 indicati
287. rforms no explicit operation It is used to synchronize the FPU with an integer unit or to force processing of pending exceptions For most floating point instructions the integer unit can continue executing the next instruction once the FPU has any operands needed for an operation thus supporting concurrent execution of integer and floating point instructions FNOP causes the integer unit to wait for all previous floating point instructions to complete It also forces any exceptions pending from the execution of a previous floating point instruction to be processed as a pre instruction exception The opcode for FNOP is 0xF280 0000 FPSR Not affected Instruction 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE FNOP uses the same opcode as the FBcc W lt label gt instruction with cc F nontrapping false and lt label gt 2 which results in a displacement of 0 M MOTOROLA Chapter 7 Floating Point Unit FPU User Instructions 7 37 Instruction Descriptions FSQ RT Floating Point Square Root FSQ RT Operation Square Root of Source FPx Assembler syntax FSQRT fmt lt ea gt y FPx FSORT D FPy FPx FSORT D FPx FrSQRT mt lt ea gt y FPx FrSQRT D FPy FPx FrSQRT D FPx where r is rounding precision S or D Attributes Format byte word longword single precision double precision Descriptio
288. ributes Format longword Description Moves the contents of the floating point instruction address register to an effective address Exceptions are not taken upon execution of this instruction FPSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Destination Effective Address Mode Register 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt x shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W Ax 001 reg number Ax xxx L a Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax eres Me dg Ax Xi dg PC Xi 7 26 ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Descriptions FMOVE FMOVE from FPSR Move from the Floating from FPSR Point Status Register Operation FPSR Destination Assembler syntax FMOVE L FPSR lt ea gt x Attributes Format longword Description Moves the contents of the FPCR to an effective address A 32 bit transfer is always performed even though the FPSR does not have 32 implemented bits Unimplemented bits of a control register are read as zeros Exceptions are not taken upon exec
289. rwise set if the quotient is negative cleared if positive Z Cleared if overflow is detected otherwise set if the quotient is zero cleared if nonzero V Set if an overflow occurs cleared otherwise C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 14 0 Format 1 0 0 0 Register Dx 1 1 1 Source Effective Address Word Mode Register M mororoLA Chapter 4 Integer User Instructions 4 29 DIVS Instruction Fields Word Signed Divide e Register field Specifies the destination register Dx DIVS e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 Instruction 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Format 0 1 0 1 1 0 0 Source Effective Address Longword Mode Register 0 Register Dx 1 0 0 0 0 0 0 0 Register Dx Instruction Fields Longword e Register field Specifies the destination register Dx Note that this field appears twice in the instruction format
290. s 31 16 15 14 1 0 Not used msb Lower order word Isb Word 16 bits 31 30 1 0 msb Longword Isb Longword 32 bits Figure 1 25 Organization of Integer Data Format in Data Registers Because address registers and stack pointers are 32 bits wide address registers cannot be used for byte size operands When an address register is a source operand either the low order word or the entire longword operand is used depending on the operation size When an address register is the destination operand the entire register becomes affected despite the operation size If the source operand is a word size it is sign extended to 32 bits and then used in the operation to an address register destination Address registers are primarily for addresses and address computation support The instruction set explains how to add to compare and move the contents of address registers Figure 1 26 illustrates the organization of addresses in address registers 31 16 15 0 Sign Extended 16 Bit Address Operand 31 0 Full 32 Bit Address Operand Figure 1 26 Organization of Addresses in Address Registers Control registers vary in size according to function Some control registers have undefined bits reserved for future definition by Motorola Those particular bits read as zeros and must be written as zeros for future compatibility All operations to the SR and CCR are word size operations For all CCR operations the upper b
291. s Biased exponent format maximum 255 OxFF 2047 0x7FF Mantissa 0 f 0 0 0 f 0 0 NANs Sign Don t care 0 or 1 Biased exponent format maximum 255 OxFF 255 Ox7FF Fraction Nonzero Nonzero M MOTOROLA Chapter 1 Introduction Multiply Accumulate Data Formats Table 1 11 Real Format Summary Continued Parameter Single Precision Double Precision Representation of fraction Nonzero bit pattern created by user XXXXX XXXX XXXXX XXXX Fraction when created by FPU 11111 1111 11111 1111 Approximate Ranges Maximum positive normalized 3 4 x 10 8 1 8 x 10908 Minimum positive normalized 1 2 x 10758 2 2 x 107308 Minimum positive denormalized 1 4 x 10745 4 9 x 107324 1 8 Multiply Accumulate Data Formats The MAC and EMAC units support 16 or 32 bit input operands of the following formats e Two s complement signed integers In this format an N bit operand value lies in the range DAS operand lt 2N D 1 The binary point is right of the Isb e Unsigned integers In this format an N bit operand value lies in the range 0 lt operand lt 2N 1 The binary point is right of the Isb e Two s complement signed fractionals In an N bit number the first bit is the sign bit The remaining bits signify the first N 1 bits after the binary point Given an N bit number djy_ 4y 24y 3 4244 its value is given by the equation in Figure 1 24 N 1 1 N value l ay_ V2 ai
292. s a numerical listing of the ColdFire family instructions in binary format Wherever the binary encoding for an entire nibble of an instruction is predefined the hex value for that nibble appears on the right side of the page otherwise a dash is used to show that it is variable 9 1 Operation Code Map Table 9 1 lists the encoding for bits 15 12 and the operation performed Table 9 1 Operation Code Map Bits 15 12 Hex Operation 0000 0 Bit Manipulation Immediate 0001 1 Move Byte 0010 2 Move Longword 0011 3 Move Word 0100 4 Miscellaneous 0101 5 ADDQ SUBQ Scc TPF 0110 6 Bcc BSR BRA 0111 7 MOVEQ MVS MVZ 1000 8 OR DIV 1001 9 SUB SUBX 1010 A MAC EMAC instructions MOV3Q 1011 B CMP EOR 1100 C AND MUL 1101 D ADD ADDX 1110 E Shift 1111 F Floating Point Debug Cache Instructions M MOTOROLA Chapter 9 Instruction Format Summary 9 1 Operation Code Map ORI 0x008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Register Dx Upper Word of Immediate Data Lower Word of Immediate Data BTST Ox0 Bit number dynamic specified in a register Data Register Dy Destination Effective Address Effective Address BCHG 0x0 Bit number dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Data Register Dy
293. s instruction can be used to prefetch a 16 byte packet into the processor s instruction cache If the referenced instruction address is a non cacheable space the instruction effectively performs no operation Note that this instruction synchronizes the pipeline The INTOUCH instruction can be used to prefetch and with the later programming of CACR lock specific memory lines in the processor s instruction cache This function may be desirable in systems where deterministic real time performance is critical Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 1 0 0 0 0 1 0 1 Register Ay Instruction Fields e Register field Specifies the source address register Ay INTOUCH V2 V3 Core ISA_A V4 Core ISA_B Opcode present No Yes Operand sizes supported 8 8 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVE from SR Move from the Status Register All ColdFire Processors Operation If Supervisor State Then SR Destination Else Privilege Violation Exception Assembler Syntax MOVE W SR Dx Attributes Size word MOVE from SR Description Moves the data in the status register to the destination location The destination is word length Unimplemented bits are read as zeros Condition Codes Not affected Instruction 15 14 13 12 E 10 9 8 7 6 5 a 3 2 1 0 F
294. s is shown in Table 10 5 Table 10 5 PST DDATA Specifications for Supervisor Mode Instructions Instruction Operand Syntax PST DDATA cpushl dc Ax PST Ox1 ic Ax bc Ax frestore lt ea gt y PST 0x1 fsave lt ea gt X PST 0x1 halt PST 0x1 PST OxF intouch Ay PST 0x1 move Ay USP PST 0x1 move USP Ax PST 0x1 M mororoLa Chapter 10 PST DDATA Encodings 10 7 Supervisor Instruction Set Table 10 5 PST DDATA Specifications for Supervisor Mode Instructions Continued Instruction Operand Syntax PST DDATA move w SR Dx PST 0x1 move w Dy lt data gt SR PST 0x1 PST 0x3 movec Ry Rc PST 0x1 8 ASID rte PST 0x7 PST 0xB DD source operand PST 3 PST 0xB DD source operand DD PST 0x5 PST 0x9AB DD target address stop lt data gt PST 0x1 PST OxE wdebug l lt ea gt y PST 0x1 PST 0xB DD source PST OxB DD source The move to SR and RTE instructions include an optional PST 0x3 value indicating an entry into user mode Additionally if the execution of a RTE instruction returns the processor to emulator mode a multiple cycle status of OxD is signaled Similar to the exception processing mode the stopped state PST OxE and the halted state PST OxF display this status throughout the entire time the ColdFire processor is in the given mode 10 8 ColdFire Family
295. s program execution by transferring control to the given location as part of the RTE return from exception instruction The instruction restart recovery model requires program visible register changes made during execution to be undone if that instruction subsequently faults The V4 Operand Execution Pipeline OEP structure naturally supports this concept for most instructions program visible registers are updated only in the final OEP stage when fault collection is complete If any type of exception occurs pending register updates are discarded For V4 cores most single cycle instructions already support precise faults and instruction restart Some complex instructions do not Consider the following memory to memory move mov 1 Ay Ax copy 4 bytes from source to destination On a V4 processor this instruction takes 1 cycle to read the source operand Ay and 1 to write the data into Ax Both the source and destination address pointers are updated as part of execution Table 11 15 lists the operations performed in execute stage EX M MOTOROLA Chapter 11 Exception Processing 11 15 Overview Table 11 15 OEP EX Cycle Operations EX Cycle Operations 1 Read source operand from memory Ay update Ay new Ay old Ay 4 2 Write operand into destination memory Ax update Ax new Ax old Ax 4 update CCR A fault detected with the destination memory write is reported during the second cycle
296. s reference 12 2 12 5 exceptions 11 5 Program control instructions 3 8 Program counter PC general 1 2 indirect displacement 2 6 scaled index and 8 bit displacement 2 7 Programming model EMAC user 1 8 FPU user 1 4 integer unit user 1 1 MAC user 1 7 supervisor 1 11 R RAM base address registers RAMBARO RAMBARI 1 15 Registers ABLR ABHR 8 18 access control ACRO ACR3 1 14 address A0 A7 1 2 cache control CACR 1 14 condition code CCR 1 2 data DO D7 1 2 data organization 1 20 DBR DBMR 8 18 floating point control FPCR 1 4 data FPO FP7 1 4 instruction address FPIAR 1 6 status 7 1 status FPSR 1 5 integer data formats 1 20 MAC mask MASK EMAC 1 11 MAC 1 8 MAC status MACSR EMAC 1 8 MAC 1 7 MMU base address MMUBAR 1 14 module base address MBAR 1 15 RAM base RAMBARO RAMBARI 1 15 ROM base address ROMBARO ROMBARI 1 15 status SR 1 12 vector base VBR 1 14 11 2 ROM base address registers ROMBARO ROMBARI 1 15 M MOTOROLA INDEX S Shift instructions 3 7 S record content A 1 creation A 3 types A 2 Stack 2 10 Stack pointers supervisor user 1 13 11 4 Status register SR 1 12 Supervisor instruction descriptions 8 1 8 18 instruction set 10 7 programming model 1 11 Supervisor user stack pointers 1 13 11 4 System control instructions 3 10 U Underflow UNFL 11 13 User instruction set 10 1 10 7 V Vector base register 1 14
297. saturation no 16 bit rnd 32 bit rounding Temp 47 8 ACC 47 8 rounded by contents of 7 0 if Temp 47 39 0x00_0 or OxFF_1 then Temp 39 8 Rx else if Temp 47 then Ox7FFF_FFFF Rx else 0x8000_0000 Rx 6 6 ColdFire Family Programmer s Reference Manual M MOTOROLA MOVCLR MOVCLR Movefrom Accumulator and Clear if MACSR OMC S U 11 saturation 16 bit rounding Temp 47 24 ACC 47 24 rounded by the contents of 23 0 if Temp 47 39 0x00_0 or OxFF_1 then 0 Rx 31 16 Temp 39 24 Rx 15 0 else if Temp 47 then 0x0000_7FFF Rx else 0x0000_8000 Rx 0 ACCx ACCextx MACSR PAVx Condition N Z V PAVx EV N Not affected Codes 0 Z Not affected V Not affected MACSR PAVx Cleared EV Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 E 2 1 0 Format 1 OF l1 o 0 ACC 1 1 1 0 0 Register Rx Instruction Fields e ACC Specifies the destination accumulator The value of bits 10 9 specify the accumulator number e Register Rx field Specifies a destination register operand where 0x0 is DO 0x7 is D7 0x8 is AO OxF is A7 M MOTOROLA Chapter 6 EMAC User Instructions 6 7 MOVE MOVE from ACC Move from from ACC Accumulator Operation Accumulator Destination Assembler syntax MOVE L ACCy Rx Attributes Size longword Description Moves a 32 bit value from an accumulator into a general purpose register Rx
298. sb of the result is set cleared otherwise Codes Z Set if the result is zero cleared otherwise V Set if an overflow is generated unchanged otherwise MACSR Instruction 15 14 13 12 11 10 9 8 7 6 5 deka or 4 0 Format 1 0 1 0 Register Rw 0 1 Rw Source Effective Address Mode Register Register Rx SZ Scale 0 rU Lx U Ly Mask 0 Register Ry Factor Instruction Fields e Register Rw 6 11 9 field Specifies the destination register Rw where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e Source Effective Address field specifies the source operand lt ea gt y use addressing modes in the following table ColdFire Family Programmer s Reference Manual Addressing Mode Mode Register Addressing Mode Mode Register Dy xxx W an Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d 6 PC dg Ay Xi dg PC Xi M MOTOROLA MAC Multiply Accumulate with Load MAC Instruction Fields continued Register Rx field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 sz field Specifies the size of the input operands 0 word longword Scale Fact
299. simply clear appropriate FPSR exception bits optionally alter FPCR and then return from the exception Note that exceptions are never taken on FMOVE to or from the status and control registers and FMOVEM to or from the floating point data registers At the completion of the exception handler the RTE instruction must be executed to return to normal instruction flow 11 10 ColdFire Family Programmer s Reference Manual M MOTOROLA Overview 11 1 5 Branch Set on Unordered BSUN A BSUN results from performing an IEEE nonaware conditional test associated with the FBcc instruction when an unordered condition is present Any pending floating point exception is first handled by a pre instruction exception after which the conditional instruction restarts The conditional predicate is evaluated and checked for a BSUN exception before executing the conditional instruction A BSUN exception occurs if the conditional predicate is an IEEE non aware branch and FPCC NAN is set When this condition is detected FPSR BSUN is set Table 11 5 shows the results when the exception is enabled or disabled Table 11 5 BSUN Exception Enabled Disabled Results Condition BSUN Description Exception 0 The floating point condition is evaluated as if it were the equivalent IEEE aware conditional disabled predicate No exceptions are taken Exception 1 The processor takes a floating point pre instruction exception Enabled The BSUN exception is uniq
300. sing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt 111 100 Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 4 54 ColdFire Family Programmer s Reference Manual M MOTOROLA MULU Unsigned Multiply MULU Instruction 15 Format 0 Longword 14 13 12 11 10 8 7 6 5 4 3 2 1 0 1 1 1 0 0 Source Effective Address Mode Register 0 Register Dx 0 0 0 0 0 0 0 0 0 0 0 Instruction Fields Longword e Source Effective Address field Specifies the source operand use only data addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d 6 AY 101 reg number Ay di6 PC dg Ay Xi dg PC Xi e Register field Specifies a data register Dx for the destination operand the 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this regis
301. ssing mode If R M 1 this field specifies the location of the source operand lt ea gt y Only the addressing modes listed in the following table can be used Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W Ay xxx L Ay 010 reg number Ay lt data gt Ay 011 reg number Ay Ay 100 reg number Ay d16 Ay 101 reg number Ay d45 PC 111 010 dg Ay Xi dg PC Xi 1 Only if format is byte word longword or single precision If R M 0 this field is unused and must be all zeros The operation is lt ea gt y to register The operation is register to register R M field Specifies the source operand address mode e Source Specifier field Specifies the source register or data format If R M 1 specifies the source data format See Table 7 6 If R M 0 specifies the source floating point data register FPy e Destination Register field Specifies the destination floating point register FPx e Opmode field Specifies the instruction and rounding precision Opmode Instruction Rounding Precision 0100010 FADD Rounding precision specified by FPCR 1100010 FSADD Single precision rounding 1100110 FDADD Double precision rounding 7 12 ColdFire Family Programmer s Reference Manual M MOTOROLA
302. ssor status and debug data in a manner that is compatible with the displays generated with the separate PST and DDATA outputs For further information refer to the debug section of a device or core user s manual Note that not all instructions are implemented on all cores and devices Refer to Chapter 12 Processor Instruction Summary for further information 10 1 User Instruction Set Table 10 1 shows the PST DDATA specification for user mode instructions Rn represents any Dn An register The y suffix denotes the source and x denotes the destination operand For a given instruction the optional operand data is displayed only for those effective addresses referencing memory The DD nomenclature refers to the DDATA outputs M mororoLA Chapter 10 PST DDATA Encodings 10 1 User Instruction Set Table 10 1 PST DDATA Specification for User Mode Instructions Instruction Operand Syntax PST DDATA add lt ea gt y Dx PST 0x1 PST 0xB DD source operand add Dy lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination adda lt ea gt y Ax PST 0x1 PST 0xB DD source operand addi lt data gt Dx PST 0x1 addq lt data gt lt ea gt x PST 0x1 PST 0xB DD source PST OxB DD destination addx Dy Dx PST 0x1 and l lt ea gt y Dx PST 0x1 PST 0xB DD s
303. t ea gt y FPx B W L S D Source FPx FPx round destination to single User FPy FPx D FSAVE lt ea gt x none Internal FPU State FPU State Frame Super FSDIV lt ea gt y FPx B W L S D FPx Source FPx round destination to single User FPy FPx D FSMOVE lt ea gt y FPx B W L S D Source Destination round destination to single User FSMUL lt ea gt y FPx B W L S D Source FPx FPx round destination to single User FPy FPx D FSNEG lt ea gt y FPx B W L S D Source FPx round destination to single User FPy FPx D FPx D FPx FPx round destination to single FSQRT lt ea gt y FPx B W L S D Square Root of Source FPx User FPy FPx D FPx D Square Root of FPx FPx FSSQRT lt ea gt y FPx B W L S D Square Root of Source FPx round destination User FPy FPx D to single FPx D Square Root of FPx FPx round destination to single FSSUB lt ea gt y FPx B W L S D FPx Source FPx round destination to single User FPy FPx D FSUB lt ea gt y FPx B W L S D FPx Source FPx User FPy FPx D FTST lt ea gt y B W L S D Source Operand Tested FPCC User M MOTOROLA Chapter 3 Instruction Set Summary 3 21 Instruction Set Additions 3 22 ColdFire Family Programmer s Reference Manual M MOTOROLA Chapter 4 Integer User Instructions This section describes the integer user instructions for the ColdFire Family detailed discussion of each instruction description is arranged in alphabetical o
304. t number e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W 111 000 Ax xxx L 111 001 Ax 010 reg number Ax lt data gt 111 100 AX 011 reg number Ax Ax 100 reg number Ax d 6 AX 101 reg number Ax di6 PC 111 010 dg Ax Xi 110 reg number Ax dg PC Xi 111 011 4 24 ColdFire Family Programmer s Reference Manual M MOTOROLA C LR Clear an Operand C LR All ColdFire Processors Operation 0 gt Destination Assembler Syntax CLR sz lt ea gt x Attributes Size byte word longword Description Clears the destination operand to 0 The size of the operation may be specified as byte word or longword Condition X N Z Vv C X Not affected 0 1 0 0 N Always cleared Codes Z Always set V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 0 0 1 0 Size Destination Effective Address Mode Register Instruction Fields e Size field Specifies the size of the operation 0 byte operation 1 word operation 10 longword operation 11 reserv
305. t ways 1 Immediate The shift count is specified in the instruction shift range is 1 8 2 Register The shift count is the value in the data register Dy specified in the instruction modulo 64 For ASL the operand is shifted left the shift count equals the number of positions shifted Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the low order bit The overflow bit is always zero CCR C lt Operand 0 ASL CCR X lt For ASR the operand is shifted right the number of positions shifted equals the shift count Bits shifted out of the low order bit go to both the carry and the extend bits the sign bit msb is shifted into the high order bit msb Operand ASR y CCRIC gt CCR X M mororoLA Chapter 4 Integer User Instructions 4 11 ASL ASR Arithmetic Shift ASL ASR x lt Condition X N Z V C Set according to the last bit shifted out of the operand Codes 0 unaffected for a shift count of zero 7 Set if the msb of the result is set cleared otherwise Set if the result is zero cleared otherwise Always cleared Set according to the last bit shifted out of the operand cleared for a shift count of zero O lt NZ Note that CCR V is always cleared by ASL and ASR unlike on the 68K family processors Instructio
306. te Value FINT Extract Integer Part FINTRZ Extract Integer Part Rounded to Zero FNEG FSNEG FDNEG Negate FSQRT FSSQRT FDSQRT Square Root 3 2 Instruction Set Additions This section contains tables which summarize the baseline instruction set as well as the instructions that are added through ISA_B and the optional MAC EMAC and Floating Point Units Table 3 14 shows the entire user instruction set in alphabetical order Table 3 15 shows the entire supervisor instruction set in alphabetical order In these tables the ISA column has the following definitions e ISA A Part of the original ColdFire instruction set architecture e ISA B Added with V4 ISA B also contains all ISA_ A instructions e MAC Part of the original ColdFire MAC instruction set e EMAC Additional MAC instructions included in the EMAC e FPU Floating Point Unit instructions Table 3 14 ColdFire User Instruction Set Summary Instruction Operand Syntax p Operation ISA ADD Dy lt ea gt x L Source Destination Destination ISA A lt ea gt y Dx L ADDA lt ea gt y Ax L ADDI lt data gt Dx L Immediate Data Destination Destination ISA_A ADDQ lt data gt lt ea gt x L ADDX Dy Dx L Source Destination CCR X Destination ISA_A AND lt ea gt y Dx L Source amp Destination Destination ISA_A Dy lt ea gt x L ANDI lt data gt Dx E Immediate Data amp Destination
307. ted is zero cleared otherwise Not affected Not affected zz 2 O lt NZX Bit Number Static Specified as Immediate Data Instruction 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 1 0 0 0 0 0 Destination Effective Address Mode Register 0 0 0 0 0 0 0 0 Bit Number Instruction Fields e Destination Effective Address field Specifies the destination location lt ea gt x use only those data alterable addressing modes listed in the following table Note that longword is allowed only for the Dx mode all others are byte only Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W Ax xxx L Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax di6 Ax 101 reg number Ax d 6 PC dg Ax Xi dg PC Xi M MOTOROLA Chapter 4 Integer User Instructions 4 23 BTST BTST Test a Bit Instruction Fields continued e Bit Number field Specifies the bit number Bit Number Dynamic Specified in a Register Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format o o 0 O Data Register Dy 1 o 0 Destination Effective Address Mode Register Instruction Fields e Data Register field Specifies the data register Dy that contains the bi
308. ter M MOTOROLA Chapter 4 Integer User Instructions 4 55 MVS Operation Move with Sign Extend Supported starting with V4 Source with sign extension Destination Assembler Syntax MVS sz lt ea gt y Dx Attributes Size byte word MVS Description Sign extend the source operand and move to the destination register For the byte operation bit 7 of the source is copied to bits 31 8 of the destination For the word operation bit 15 of the source is copied to bits 31 16 of the destination Not affected Always cleared Always cleared O lt NZX 4 3 Set if result is negative cleared otherwise Set if the result is zero cleared otherwise 2 1 0 Condition X N Z V C Codes 1 0 0 Instruction 15 14 13 12 11 10 Format 0 1 1 1 Register Dx 1 0 Size Source Effective Address Mode Register Instruction Fields 4 56 Register field Specifies the destination data register Dx Size field Specifies the size of the operation byte operation 1 word operation Source Effective Address field specifies the source operand lt ea gt y use only data addressing modes from the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xxx W 111 000 Ay 001 reg number Ay xxx L 111 001 Ay 010 reg nu
309. ter Dx The size of the operation is specified as a longword The size of the immediate data is specified as a longword Note that the immediate data is contained in the two extension words with the first extension word bits 15 0 containing the upper word and the second extension word bits 15 0 containing the lower word Condition X N Z V C X Not affected Codes 0 0 N Set if the msb of the result is set cleared otherwise odes Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 0 0 0 0 0 1 0 1 0 0 0 0 Destination Register Dx Upper Word of Immediate Data Lower Word of Immediate Data Instruction Fields e Destination Register field specifies the destination data register Dx 4 10 ColdFire Family Programmer s Reference Manual M MOTOROLA ASL ASR Arithmetic Shift ASL ASR All ColdFire Processors Operation Destination Shifted By Count Destination Assembler Syntax ASd L Dy Dx ASd L lt data gt Dx where d is direction L or R Attributes Size longword Description Arithmetically shifts the bits of the destination operand Dx in the direction L or R specified The size of the operand is a longword CCR C receives the last bit shifted out of the operand The shift count is the number of bit positions to shift the destination register and may be specified in two differen
310. ter Rn Any address or data register Rx Ry Any destination and source registers respectively Xi Index register can be any address or data register all 32 bits are used Subfields and Qualifiers lt data gt Immediate data following the instruction word s Identifies an indirect address in a register dh Displacement value n bits wide example dig is a 16 bit displacement SZ Size of operation Byte B Word W Longword L Isb msb Least significant bit most significant bit LSW MSW Least significant word most significant word SF Scale factor for an index register ColdFire Family Programmer s Reference Manual M MOTOROLA Instruction Summary Table 3 1 Notational Conventions Continued Register Names CCR Condition Code Register lower byte of status register PC Program Counter SR Status Register USP User Stack Pointer ic dc bc Instruction data or both caches unified cache uses bc Condition Codes 7 General case C Carry bit in CCR cc Condition codes from CCR N Negative bit in CCR V Overflow bit in CCR X Extend bit in CCR Z Zero bit in CCR Not affected or applicable Miscellaneous lt ea gt X lt ea gt y Destination and source effective address respectively lt label gt Assembly program label list List of registers for example D3 DO MAC Operations ACC ACCx MAC accumulator register
311. ter 6 Enhanced Multiply Accumulate Unit EMAC User Instructions M MOTOROLA Chapter 5 Multiply Accumulate Unit MAC User Instructions 5 1 MAC Multiply Accumulate MAC Operation ACC Ry Rx lt lt gt gt SF ACC Assembler syntax MAC sz Ry U L Rx U L SF Attributes Size word longword Description Multiply two 16 or 32 bit numbers to yield a 32 bit result then add this product shifted as defined by the scale factor to the accumulator If 16 bit operands are used the upper or lower word of each register must be specified Condition N Z V N Set if the msb of the result is set cleared otherwise Cod Z Set if the result is zero cleared otherwise odes V Set if an overflow is generated unchanged otherwise MACSR Instruction 15 14 13 Format 1 fo 1 12 11 10 9 8 7 6 5 4 3 2 1 0 ER Register Rx olr o fo Register Ry sz Scale O JU Lx U Ly J Factor Instruction Fields e Register Rx 6 11 9 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e Register Ry 3 0 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 e sz field Specifies the size of the input operands 0 word longword e Scale Factor field Specifies the scale facto
312. ter 7 Floating Point Unit FPU User Instructions 7 7 Instruction Descriptions PC relative effective address is specified for an FPU instruction the PC always holds the address of the 16 bit operation word plus 2 To understand the results of floating point instructions under exceptional conditions overflow NAN operand etc refer to Table 7 5 Table 7 6 shows data format encoding used for source data and for destination data for FMOVE register to memory operations Table 7 6 Data Format Encoding Source Data Format Description 000 Longword integer L 001 Single precision real S 100 Word integer W 101 Double precision real D 110 Byte integer B 7 8 ColdFire Family Programmer s Reference Manual M MOTOROLA FABS Operation Assembler Syntax Attributes Floating Point Absolute Value Absolute value of source FPx FABS fmt lt ea gt y FPx FABS D FPy FPx FABS D FPx FrABS fmt lt ea gt y FPx FrABS D FPy FPx FrABS D FPx where r is rounding precision S or D Instruction Descriptions FABS Format byte word longword single precision double precision Description Converts the source operand to double precision if necessary and stores its absolute value in the destination floating point data register FABS rounds the result to the precision selected in FPCR FSABS and FDABS round to single or double precision respectively regardless of the rounding precisio
313. ter FMOVE Operation Source Destination Assembler Syntax FMOVE fmt lt ea gt y FPx FMOVE fmt FPy lt ea gt x FMOVE D FPy FPx FrMOVE fmt lt ea gt y FPx FrMOVE D FPy FPx where r is rounding precision S or D Attributes Format byte word longword single precision double precision Description Moves the contents of the source operand to the destination operand Although the primary function of FMOVE is data movement it is considered an arithmetic instruction because conversions from the source operand format to the destination operand format occur implicitly Also the source operand is rounded according to the selected rounding precision and mode Unlike MOVE FMOVE does not support a memory to memory format For such transfers MOVE is much faster than FMOVE to transfer floating point data FMOVE supports memory to register register to register and register to memory operations memory here can include an integer data register if the format is byte word longword or single precision Memory and register to register operations use a command word encoding different from that used by the register to memory operation these two operation classes are described separately Memory and register to register operations lt ea gt y FPx FPy FPx Converts the source operand to a double precision number if necessary and stores it in the destination floating point data register FPx FMOVE rounds the result to the precision select
314. tes are loaded as shown in the following table Note the position of the LSB of the extension within the combined 48 bit accumulation logic is dependent on the operating mode of the EMAC integer versus fractional Source Data Accumulator Extension Bits Affected 31 24 ACCext1 15 8 23 16 ACCext1 7 0 15 8 ACCext0 15 8 7 0 ACCext0 7 0 MACSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 0 1 0 1 0 1 1 0 0 Source Effective Address Mode Register Instruction Fields e Source Effective Address field Specifies the source operand use addressing modes listed in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg number Dy xx W Ay 001 reg number Ay xxx L LL Ay En lt data gt 111 100 Ay Ay d16 Ay d16 PC dg Ay Xi dg PC Xi LL M mororoLA Chapter 6 EMAC User Instructions 6 17 MOVE to ACCext23 move to Accumulator 2 and 3 Extensions MOVE to ACCext23 Source Accumulator 2 and 3 extension words Assembler syntax MOVE L Ry ACCext23 MOVE L lt data gt ACCext23 Operation Attributes Size longword Description Moves a 32 bit value from a register or an immediate operand into the four extension bytes associated with accumulators 2 and 3 The accumulator extensi
315. the registers for the optional ColdFire MAC unit Figure 1 6 illustrates the user programming model for the MAC unit It contains the following registers e 32 bit MAC status register MACSR e 32 bit accumulator register ACC e 32 bit MAC mask register MASK 31 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register Figure 1 6 MAC Unit Programming Model 1 3 1 MAC Status Register MACSR The MACSR shown in Figure 1 7 contains an operational mode field and a set of flags 7 4 3 0 Operational Mode Flags omc su FA RTIN z v C Figure 1 7 MAC Status Register MACSR 31 8 Table 1 4 describes MACSR fields Table 1 4 MACSR Field Descriptions Bits Field Description Reserved should be cleared OMF Operational mode field Defines the operating configuration of the MAC unit OMC Overflow saturation mode S U Signed unsigned operations F I Fraction integer mode R T Round truncate mode Flags Flags Contains indicator flags from the last MAC instruction execution N Negative Zero Z Vv Overflow C Carry This field is always zero M MOTOROLA Chapter 1 Introduction 1 7 EMAC User Programming Model 1 3 2 MAC Accumulator ACC This 32 bit register contains the results of MAC operations 1 3 3 MAC Mask Register MASK The mask register MASK is 32 bits of which only t
316. therwise EV Setif accumulation overflows lower 32 bits in integer mode or lower 40 bits in fractional mode cleared otherwise Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 DE l1 0 Register Rx 0 ACC Rx 0 o Register Ry Isb msb SZ Scale o rU Lx U Ly ACC Factor msb Instruction Fields e Register Rx 6 11 9 field Specifies a source register operand where 0x0 is DO 0x7 is D7 Ox8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e ACC field Specifies the destination accumulator ACCx Bit 4 of the extension word is the msb and bit 7 of the operation word is the Isb The value of these two bits specify the accumulator number as shown in the following table Ext Op word word 4 7 0 Accumulator ACCO ACC1 ACC2 ACC3 0 0 1 1 0 1 1 e Register Ry 3 0 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 6 2 ColdFire Family Programmer s Reference Manual M MOTOROLA MAC Multiply Accumulate MAC Instruction Fields continued sz field Specifies the size of the input operands 0 word longword Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1
317. ting instruction overlap Because the NOP instruction is specified to perform a pipeline synchronization in addition to performing no operation the execution time is multiple cycles In cases where only code alignment is desired it is preferable to use the TPF instruction which operates as a 1 cycle no operation instruction The opcode for NOP is 0x4E71 Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 Format 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 wo D 4 60 ColdFire Family Programmer s Reference Manual M MOTOROLA NOT Logical Complement NOT All ColdFire Processors Operation Destination Destination Assembler Syntax NOT L Dx Attributes Size longword Description Calculates the ones complement of the destination operand and stores the result in the destination location The size of the operation is specified as a longword Condition X N Z V C X Not affected Codes 0 0 N Set if result is negative cleared otherwise Z Set if the result is zero cleared otherwise V Always cleared C Always cleared Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 0 1 1 0 1 0 0 0 0 Register Dx Instruction Fields e Register field Specifies data register Dx M mororoLA Chapter 4 Integer User Instructions 4 61 OR Operation Inclusive OR Logical OR All ColdFir
318. truction Set Summary Integer User Instructions MAC User Instructions EMAC User Instructions FPU User Instructions Supervisor Instructions Instruction Format Summary PST DDATA Encodings Exception Processing Processor Instruction Summary S Record Output Format Index ES INID N IND Introduction Addressing Capabilities Instruction Set Summary Integer User Instructions MAC User Instructions EMAC User Instructions FPU User Instructions Supervisor Instructions Instruction Format Summary PST DDATA Encodings Exception Processing Processor Instruction Summary S Record Output Format Index Paragraph Number 1 1 1 1 1 1 1 2 1 1 3 1 1 4 1 2 1 2 1 1 2 1 1 1 22 1 2 3 1 3 1 3 1 1 3 2 1 3 3 1 4 1 4 1 1 4 2 1 4 3 1 4 4 1 5 1 5 1 1 5 2 1 5 3 1 5 4 1 5 5 1 5 6 1 5 7 1 5 8 1 5 9 1 5 10 1 6 1 7 1 7 1 CONTENTS Page Hile Number Chapter 1 Introduction Integer Unit User Programming Model 1 1 Data Registers DO DIE ARN 1 2 Address Registers AQ A7 s sisivsssdentvsuciaacrtagederasacesdevaesdaateausdents tasedarasessadeouses 1 2 Program Counter PC resect caidas da nn es n s 1 2 Condition Code Register CCR ss oversiverrnvensnarseenserssaarsesrssenande enawesaddekeend 1 2 Floating point Unit User Programming Model 1 4 Floating Point Data Registers FPO FP7 nnen enneevenneevennervenn 1 4 Floating Point Control Register FPCR an
319. ttempting to execute an undefined line f opcode When attempting to execute an FPU instruction when the FPU is not present When attempting to execute an FPU instruction when the FPU is present but has been disabled in the CACR The debug interrupt exception is caused by a hardware breakpoint register trigger Rather than generating an IACK cycle the processor internally calculates the vector number 12 for V2 and V3 12 or 13 depending on the type of breakpoint trigger for V4 Additionally SR M I are unaffected by the interrupt On V4 separate exception vectors are provided for PC breakpoints vector 13 and for address data breakpoints vector 12 In the case of a two level trigger the last breakpoint determines the vector The two unique entries occur when a PC breakpoint generates the 0x034 vector 14 Format error When an RTE instruction executes the processor first examines the 4 bit format field to validate the frame type For a ColdFire processor attempted execution of an RTE where the format is not equal to 4 5 6 7 generates a format error The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to RTE The selection of the format value provides limited debug support for porting code from M68000 applications On M68000 Family processors the SR was at the top of the stack Bit 30 of the longword addressed by the system stack pointer
320. ue in that the exception is taken before the conditional predicate is evaluated If the user BSUN exception handler fails to update the PC to the instruction after the excepting instruction when returning the exception executes again Any of the following actions prevent taking the exception again e Clearing FPSR NAN e Disabling FPCR BSUN e Incrementing the stored PC in the stack bypasses the conditional instruction This applies to situations where fall through is desired Note that to accurately calculate the PC increment requires knowledge of the size of the bypassed conditional instruction 11 1 6 Input Not A Number INAN The INAN exception is a mechanism for handling a user defined non IEEE data type If either input operand is a NAN FPSR INAN is set By enabling this exception the user can override the default action taken for NAN operands Because FAOVEM FMOVE FPCR and FSAVE instructions do not modify status bits they cannot generate exceptions Therefore these instructions are useful for manipulating INANs See Table 11 6 Table 11 6 INAN Exception Enabled Disabled Results Condition INAN Description Exception 0 If the destination data format is single or double precision a NAN is generated with a mantissa disabled of all ones and a sign of zero transferred to the destination If the destination data format is B W or L a constant of all ones is written to the destination Exception 1 The result written
321. ult possibly 20 11 14 ColdFire Family Programmer s Reference Manual AA MOTOROLA Overview FPSR INEX is also set for any of the following conditions e Ifan input operand is a denormalized number and the IDE exception is disabled e An overflowed result e An underflowed result with the underflow exception disabled Table 11 14 shows results when the exception is enabled or disabled Table 11 14 INEX Exception Enabled Disabled Results Condition INEX Description Exception 0 The result is rounded and then written to the destination disabled Exception 1 The result written to the destination is the same as for the exception disabled case unless the enabled exception occurred on a FMOVE OUT in which case the destination is unaffected If desired the user INEX handler can overwrite the default result 11 1 13 V4 Changes to the Exception Processing Model When an MMU is present in a ColdFire device all memory references require support for precise recoverable faults This section details the changes in the ColdFire exception processing model due to the presence of an MMU The ColdFire instruction restart mechanism ensures that a faulted instruction restarts from the beginning of execution that is no internal state information is saved when an exception occurs and none is restored when the handler ends Given the PC address defined in the exception stack frame the processor reestablishe
322. upt vectors Table 11 1 Exception Vector Assignments Vector Numbers Vector Offset Hex Stacked Program Counter Assignment 0 000 Initial stack pointer SSP for V4e 004 Initial program counter 2 008 Fault Access error ColdFire Family Programmer s Reference Manual M MOTOROLA Vector Numbers Overview Table 11 1 Exception Vector Assignments Continued Vector Offset Hex Stacked Program Counter Assignment 3 00C Fault Address error 4 010 Fault Illegal instruction 52 014 Fault Divide by zero 6 7 018 01C Reserved 8 020 Fault Privilege violation 9 024 Next Trace 10 028 Fault Unimplemented line a opcode 11 02C Fault Unimplemented line f opcode 12 030 Next Non PC breakpoint debug interrupt 13 034 Next PC breakpoint debug interrupt 14 038 Fault Format error 15 03C Next Uninitialized interrupt 16 23 040 05C Reserved 24 060 Next Spurious interrupt 25 31 064 07C Next Level 1 7 autovectored interrupts 32 47 080 0BC Next Trap 0 15 instructions 484 oco Fault Floating point branch on unordered condition 494 0C4 NextFP or Fault Floating point inexact result 504 0C8 NextFP Floating point divide by zero 514 OCC NextFP or Fault Floating point underflow 524 ODO NextFP or Fault Floating point operand error 534 0D4 NextFP or Fault Floating point overflow 544 0D8 NextFP or Fault Floating point input not a num
323. ution of this instruction FPSR Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 1 0 0 0 Destination Effective Address Mode Register 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Instruction field e Effective Address field Specifies the addressing mode lt ea gt x shown in the following table Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg number Dx xxx W Ax xxx L Ax 010 reg number Ax lt data gt Ax 011 reg number Ax Ax 100 reg number Ax d46 Ax 101 reg number Ax d4g PC dg Ax Xi dg PC Xi M mororoLA Chapter 7 Floating Point Unit FPU User Instructions 7 27 Instruction Descriptions FMOVE to FPCR Move to the Floating Operation Source FPCR Assembler syntax FMOVE L lt ea gt y FPCR Attributes Format longword Point Control Register FMOVE to FPCR Description Loads the FPCR from an effective address A 32 bit transfer is always performed even though the FPCR does not have 32 implemented bits Unimplemented bits are ignored during writes must be zero for compatibility with future devices Exceptions are not taken upon execution of this instruction FPSR Not affected Instruction 15 14 13 12 11 10 7 6 5 4 3 2 1 0 Format 1 1 1 1 0 0 0 0 0 Source Effe
324. ve Address Mode Register ADDQ 0x5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 Data 0 1 0 Destination Effective Address Mode Register 9 8 ColdFire Family Programmer s Reference Manual M MOTOROLA Operation Code Map Scc 0x5 C 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 1 Condition 1 1 0 0 Register Dx SUBQ 0x5 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 1 Data 1 1 0 Destination Effective Address Mode Register TPF 0x51F 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 1 0 0 0 1 1 1 1 1 Opmode Optional Immediate Word Optional Immediate Word BRA 0x60 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 1 0 0 0 0 0 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displacement if 8 bit displacement OxFF BSR 0x61 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 1 0 0 0 0 1 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displacement if 8 bit displacement OxFF Bcc 0x6 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 1 0 Condition 8 bit displacement 16 bit displacement if 8 bit displacement 0x00 32 bit displacement if 8 bit displacement OxFF MOVEQ Ox7 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 1 1 Register Dx 0
325. word of the exception stack frame Figure 11 1 holds the 16 bit format vector word F V and 16 bit status register The second holds the 32 bit program counter address 31 28 27 26 25 18 17 16 15 0 A7 gt FORMAT FS 3 2 VEC FS 1 0 Status Register 0x04 Program Counter 31 0 Figure 11 1 Exception Stack Frame Table 11 2 describes F V fields FS encodings added to support the MMU are noted 11 4 ColdFire Family Programmer s Reference Manual M MOTOROLA Table 11 2 Format Vector Word Overview Bits Field Description 31 28 FORMAT Format field Written with a value of 4 5 6 7 by the processor indicating a 2 longword frame format FORMAT records any longword stack pointer misalignment when the exception occurred A7 at Time of Exception Bits 1 0 A7 at First Instruction of Handler FORMAT 00 Original A7 8 0100 01 10 Original A7 9 Original A7 10 0101 0110 11 Original A7 11 0111 27 26 FS 3 2 Fault status Defined for access and address errors and for interrupted debug service routines 0000 Not an access or address error nor an interrupted debug service routine 0001 Reserved 0010 Interrupt during a debug service routine for faults other than access errors New in V4 0011 Reserved 0100 Error for example protection fault on instruction fetch 0101 TLB miss on opword of instruction fetch New in V4 MMU onl
326. x di6 PC 111 010 dg Ax Xi 110 reg number Ax dg PC Xi 111 011 The Ax addressing mode is allowed only for word and longword operations 4 82 ColdFire Family Programmer s Reference Manual M MOTOROLA UNLK Unlink UNLK All ColdFire Processors Operation Ax SP SP Ax SP 4 SP Assembler Syntax UNLK Ax Attributes Unsized Description Loads the stack pointer from the specified address register then loads the address register with the longword pulled from the top of the stack Condition Codes Not affected Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 1 1 0 0 1 0 1 1 Register Ax Instruction Field e Register field Specifies the address register Ax for the instruction M mororoLA Chapter 4 Integer User Instructions 4 83 WD DATA Write to Debug Data WDDATA All ColdFire Processors Operation Source DDATA Signal Pins Assembler Syntax WDDATA sz lt ea gt y Attributes Size byte word longword Description This instruction fetches the operand defined by the effective address and captures the data in the ColdFire debug module for display on the DDATA output pins The size of the operand determines the number of nibbles displayed on the DDATA output pins The value of the debug module configuration status register CSR does not affect the operation of this instruction The execution of this instruction generates
327. xecutes the processor enters a fault on fault halted state Caused by an error when accessing memory ColdFire cores handle access errors differently V2 For an access error on an instruction fetch the processor postpones the error reporting until the instruction at the faulted reference is executed Thus faults that occur during instruction prefetches that are followed by a change of instruction flow do not generate an exception When the processor attempts to execute an instruction with a faulted opword or extension word the access error is signaled and the instruction is aborted the programming model is not altered by the faulted instruction If an access error occurs on an operand read the processor immediately aborts the current instruction execution and initiates exception processing Any address register changes caused by the auto addressing modes An and An have already occurred In addition if the error occurs during the execution of a MOVEM instruction loading from memory registers may contain memory operands Due to the processor pipeline implementation a write cycle may be decoupled from the execution of the instruction causing the write Thus if an access error occurs on an operand write the signaling of the error is imprecise Accordingly the PC contained in the exception stack frame represents the location in the program when the access error is signaled not necessarily the instruction causing the fault All prog
328. y xxx W 111 000 Ay xxx L 111 001 Ay 010 reg number Ay lt data gt Ay a Ay d 6 AY 101 reg number Ay di6 PC 111 010 dg Ay Xi 110 reg number Ay dg PC Xi 111 011 M MOTOROLA Chapter 4 Integer User Instructions 4 65 P U LS E Generate Unique Processor Status P U LS E All ColdFire Processors Operation Set PST 0x4 Assembler Syntax PULSE Attributes Unsized Description Performs no operation The processor state other than the program counter is unaffected However PULSE generates a special encoding of the Processor Status PST output pins making it very useful for external triggering purposes The opcode for PULSE is Ox4ACC Condition Codes Not affected Instruction i5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 4 66 ColdFire Family Programmer s Reference Manual M MOTOROLA REMS Signed Divide Remainder REMS All ColdFire Processors Starting with MCF5206e Operation Destination Source Remainder Assembler Syntax REMS L lt ea gt y Dw Dx 32 bit Dx 32 bit lt ea gt y 32r in Dw where r indicates the remainder Attributes Size longword Description Divide the signed destination operand by the signed source and store the signed remainder in another register If Dw is specified to be the same register as Dx the DIVS instruction is executed rather than
329. y ACC Factor msb Instruction Fields e Register Rx 6 11 9 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 Note that bit 6 of the operation word is the msb of the register number field e ACC field Specifies the destination accumulator ACCx Bit 4 of the extension word is the msb and bit 7 of the operation word is the Isb The value of these two bits specify the accumulator number as shown in the following table Ext Op word word 4 7 0 Accumulator ACCO ACC1 ACC2 ACC3 0 0 1 1 0 1 1 e Register Ry 3 0 field Specifies a source register operand where 0x0 is DO 0x7 is D7 0x8 is AO OXF is A7 M mororoLA Chapter 6 EMAC User Instructions 6 21 MSAC Multiply Subtract MSAC Instruction Fields continued 6 22 sz field Specifies the size of the input operands 0 word longword Scale Factor field Specifies the scale factor This field is ignored when using fractional operands 00 none 01 product lt lt 1 10 reserved 11 product gt gt 1 U Lx Specifies which 16 bit operand of the source register Rx is used for a word sized operation 0 lower word 1 upper word U Ly Specifies which 16 bit operand of the source register Ry is used for a word sized operation 0 lower word
330. y 0110 TLB miss on extension word of instruction fetch New in V4 MMU only 0111 IFP access error while executing in emulator mode New in V4 MMU only 1000 Error on data write 1001 Error on attempted write to write protected space 1010 TLB miss on data write New in V4 MMU only 1011 Reserved 1100 Error on data read 1101 Attempted read read modify write of protected space New in V4 MMU only 1110 TLB miss on data read or read modify write New in V4 MMU only 1111 OEP access error while executing in emulator mode New in V4 MMU only 25 18 VEC Vector number Defines the exception type It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts See Table 11 1 See bits 27 26 17 16 FS 1 0 This generally refers to taking an I O interrupt while in a debug service routine but also applies to other fault types If an access error occurs during a debug service routine FS is set to 0111 if it is due to an instruction fetch or to 1111 for a data access This applies only to access errors with the MMU present If an access error occurs without an MMU FS is set to 0010 1 11 1 3 Processor Exceptions Table 11 3 describes ColdFire core exceptions Note that if a ColdFire processor encounters any fault while processing another fault it immediately halts execution with a catastrophic fault on fault condition A reset is required to force the processor to exit this h
331. y generates line sized transfers if the operand address reaches a 0 modulo 16 boundary and there are four or more registers to be transferred For these line sized transfers the operand data is never captured nor displayed regardless of the CSR value The automatic line sized burst transfers are provided to maximize performance during these sequential memory access operations Table 10 2 shows the PST specification for multiply accumulate instructions Table 10 2 PST DDATA Values for User Mode Multiply Accumulate Instructions Instruction Operand Syntax PST DDATA mac Ry Rx PST 0x1 mac l Ry Rx lt ea gt y Rw ACCx PST 0x1 PST 0xB DD source operand mac Ry Rx ACCx PST 0x1 mac l Ry Rx ea Rw PST 0x1 PST 0xB DD source operand mac w Ry Rx PST 0x1 mac w Ry Rx lt ea gt y Rw ACCx PST 0x1 PST 0xB DD source operand mac w Ry Rx ACCx PST 0x1 mac w Ry Rx ea Rw PST 0x1 PST 0xB DD source operand move l Ry lt data gt ACCext01 PST 0x1 move l Ry lt data gt ACCext23 PST 0x1 move Ry lt data gt ACCx PST 0x1 move Ry lt data gt MACSR PST 0x1 move l Ry lt data gt MASK PST 0x1 move ACCext01 Rx PST 0x1 move ACCext23 Rx PST 0x1 move ACCy ACCx PST 0x1 move ACCy Rx PST 0x1 M mororoLA Chapter 10 PST DDATA Encodings 10 5 User Instruction Set Table 10 2 PST DDATA Values for User Mode Multiply A
332. yte is read as all zeros and is ignored when written despite privilege mode The write only MOVEC instruction writes to the system control registers VBR CACR etc M mororoLA Chapter 1 Introduction 1 21 Organization of Data in Registers 1 9 2 Organization of Integer Data Formats in Memory The byte addressable organization of memory allows lower addresses to correspond to higher order bytes The address N of a longword data item corresponds to the address of the MSB of the highest order word The lower order word is located at address N 2 leaving the LSB at address N 3 see Figure 1 27 The lowest address nearest 0x00000000 is the location of the MSB with each successive LSB located at the next address N 1 N 2 etc The highest address nearest OxFFFFFFEP is the location of the LSB 31 24 23 16 15 8 7 0 Longword 0x0000_0000 Word 0x0000_0000 Word 0x0000_0002 Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003 Longword 0x0000_0004 Word 0x0000_0004 Byte 0x0000 0004 Byte 0x0000 0005 Word 0x0000 0006 Byte 0x0000 0006 Byte 0x0000 0007 Word OxFFFF_FFFC Byte OxFFFF_FFFC Byte OxFFFF_FFFD Longword OxFFFF_FFFC Word OxFFFF_FFFE Byte OxFFFF_FFFE Byte OxFFFF_FFFF Figure 1 27 Memory Operand Addressing Figure 1 28 illustrates the organization of data formats in memory A base address that selects one byte in memory the base byte
333. zes the instruction set supported by the floating point unit Table 3 19 Floating Point Instruction Set Summary Operand A Super Instruction Operand Syntax Size Operation User FABS lt ea gt y F Px B W L S D Absolute Value of Source FPx User FPy FPx D FPx D Absolute Value of FPx FPx FADD lt ea gt y F Px B W L S D Source FPx FPx User FPy FPx D FBcc lt label gt W L If Condition True Then PC d PC User FCMP lt ea gt y F Px B W L S D FPx Source User FPy FPx D FDABS lt ea gt y F Px B W L S D Absolute Value of Source FPx round User FPy FPx D destination to double FPx D Absolute Value of FPx FPx round destination to double FDADD lt ea gt y FPx B W L S D Source FPx FPx round destination to double User FPy FPx D FDDIV lt ea gt y FPx B W L S D FPx Source FPx round destination to double User FPy FPx D FDIV lt ea gt y FPx B W L S D FPx Source FPx User FPy FPx D FDMOVE FPy FPx D Source Destination round destination to double User FDMUL lt ea gt y FPx B W L S D Source FPx FPx round destination to double User FPy FPx D FDNEG lt ea gt y FPx B W L S D Source FPx round destination to double User FPy FPx D FPx D FPx gt FPx round destination to double FDSQRT lt ea gt y FPx B W L S D Square Root of Source FPx round destination User FPy FPx D to double FPx D Square Root of F

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