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Correction for Incorrect Description Notice RL78/G13 Descriptions in

1. X 10 3 p When the high speed on chip oscillator clock is selected E During self programming When high speed system clock is selected S 6 0 1 0 0625 0 05 0 03125 0 01 0 10 20 30 40 5059560 24 2 7 Supply voltage Voo V 13 NE SAS 26 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Cycle time Tcv us Tcv vs Voo LS low speed main mode When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Tcv vs Voo LV low voltage main mode 10 1 0 0 125 0 1 0 01 0 10 20 30 40 50560 1 8 Supply voltage Vo V 10 T 10 5 ke 0 E E o gt o 0 25 0 1 0 01 20 30 40 505560 Supply voltage Vo V When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected 13 NE SAS 27 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C AC Timing Test Points Vin Vox Vin VoH INe 2m Test points lt VN ai External System Clock Timing 1 fex 1 fexs EXCLK EXCLKS TI TO Timing tri a
2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVsso EVss1 and Vss pin However do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lot x 0 7 n x 0 01 Example Where n 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allo wed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS 1 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVss1 0 V 3 5 Input voltage high Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Normal input buffer P01 P03 P04 P10 P11 P13 to P17 P43 P44 P53 to P55 P80 P81 P142 P143 TTL
3. Value of current at which the device operation is guaranteed even if the current flows from the E Vopo EVpp1 Voo pins to an output pin Do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lon x 0 7 n x 0 01 Example Where n 80 and lou 10 0 mA Total output current of pins 710 0 x 0 7 80 x 0 01 8 7 mA However the current that is allo wed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin POO P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 do not output high level in N ch open drain mode Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS e RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt EVppo EVpp1 x Vpp lt 5 5 V Vss EVsso EVssi 0 V 2 5 Output current Per pin for POO to P07 P10 to P17 Note 1 low Remark Conditions P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P11
4. TxDq 1 Transfer rate 2 High Low bit width Baud rate error tolerance RxDq Remarks 1 Rb Q Communication line TxDq pull up resistance Co F Communication line TxDq load capacitance Ve V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 7tENESAS E RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO only 1 2 Ta 40 to 85 C 2 7 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcy1 gt 2 fc k 4 0 V lt EVopo lt 5 5 V 2 7 V lt Vo lt 4 0 V Co 20 pF Rb 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt V lt 2 7 V Co 20 pF Rb 2 7 KQ SCKp high level 4 0 V x EVppo lt 5 5 V width 2 7 V lt Vo lt 4 0V 20 pF Rb 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V
5. 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 a fF WO ND 8 Total current flowing into Voo and EVppo including the input leakage current flowing when the level of the input pin is fixed to Vpp EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V x Voo lt 5 5 Vg1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo x 5 5 V 1 MHz to 4 MHz Rega
6. Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS RL78 G13 Ta 40 to 85 C 1 6 V x EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVss1 0 V 5 5 Input leakage current high CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection Input leakage current low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection On chip pll up resistance Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso In input port
7. 27 V 50 pF Rb 2 7 KQ 4 0 V EVppo lt 5 5 V 100 ete 2 7V lt Vo lt 4 0V Co 100 pF Ro 2 8 KQ 2 7 V lt EVppo lt 4 0 V 100 ete 2 3V lt Vb lt 2 7V C 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 100 ete 1 6 V lt Ve lt 2 0 V Co 100 pF Ro 5 5 KQ Hold time when SCLr L 4 0 V lt EVbpo lt 5 5 V 2 7V lt Vo lt 4 0V Co 50 pF Rb 2 7 kQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V 50 pF Rb 2 7 KQ 4 0 V lt EVpp0 x 5 5 V 2 7 V xVe 4 0V C 100 pF Rb 2 8 kQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V Co 100 pF Rb 2 7 kQ 2 4 V EVppo lt 3 3 V 1 6V Vo lt 2 0 V C 100 pF Rb 5 5 KQ Hold time when SCLr H 4 0 V lt EVppo lt 5 5 V 2 7 V Vs lt 4 0 V Cb 50 pF Re 2 7 KQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V 50 pF Rb 2 7 KQ 4 0 V x EVppo x 5 5 V 2 7 V xVe x 4 0V Co 100 pF Rb 2 8 KQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V Co 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6V x Ve x 2 0 V Co 100 pF Rb 5 5 kQ Notes Caution and Remarks are listed on the next page 7tENESAS 42 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 8 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode 2 2 Ta 40 to 105 C 2 4 V lt EVppo E
8. Internal reference voltage Temperature sensor output voltage Refer to 29 6 1 1 Reference voltage VBGR Reference voltage AVREFM Refer to 29 6 1 3 1 When reference voltage AVrerr ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI2 to ANI14 internal reference voltage and temperature sensor output voltage Ta 40 to 85 C 1 6 V lt AVrerp lt Voo lt 5 5 V Vss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 10 bit resolution Note 3 AVnerP Voo 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnere lt 5 5 V NO 4 Conversion time 10 bit resolution Target pin ANI2 to ANI14 3 6 V lt Voo lt 5 5 V 2 7 V lt VoD lt 5 5 V 1 8 V lt Voo lt 5 5 V 1 6 V lt Voo lt 5 5 V 10 bit resolution Target pin Internal reference voltage and temperature sensor output voltage HS high speed main mode 3 6 V lt VoD lt 5 5 V 2 7 V lt VoD lt 5 5 V 2 4 V lt VoD lt 5 5 V 5 5 5 9 9 9 Zero scale error e 10 bit resolution Note 3 AVnere Vop 9 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnere lt 5 5 V NO 4 Full scale error 10 bit resolution Note 3 AVrerp Voo 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnErP lt 5 5 V et
9. LV low voltage main mode 1 6 V x EVppo lt 5 5 V NM NM BR mM BR oC PCLBUZO PCLBUZ1 output frequency HS high speed main mode 4 0 V lt EVppo lt 5 5 V o 2 7 V lt EVppo lt 4 0 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVppo lt 1 8 V LS low speed main mode 1 8 V lt EVppo lt 5 5 V 1 6 V lt EVppo lt 1 8 V LV low voltage main mode 1 8 V x EVppo x 5 5 V 1 6 V lt EVppo lt 1 8 V NI BR mM BR NM AJ Interrupt input high level width low level width INTPO 1 6 V lt Voo lt 5 5 V INTP1 to INTP11 1 6 V lt EVbppo lt 5 5 V Key interrupt input low level width KRO to KR7 1 8 V lt EVppo x 5 5 V 1 6 V lt EVppo lt 1 8 V RESET low level width Note and Remark are listed on the next page 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Note The following conditions are required for low voltage interface when Evopo lt Voo 1 8 V lt EVppo lt 2 7 V MIN 125 ns 1 6 V lt EVppo lt 1 8 V MIN 250 ns Remark fwck Timer array unit operation clock frequency Operation clock to be set by the CKSmn0 CKSmn_1 bits of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 7 Minimum Instruction Execution Time during Main System Clock Operation Tcv vs Voo HS high speed main mode 10
10. tkcy1 2 1 6 V lt Vo lt 2 0 Vo 50 50 50 C 30 pF Ro 5 5 KQ Note Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page 7tENESAS 1 RL78 G13 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 2 3 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Slp setup time to SCKpt 4 Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V xVe amp 4 0V Co 30 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 KQ MIN MAX LS low speed main MIN Mode MAX LV low voltage main Mode MIN MAX 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote 30 pF Rb 5 5 KQ Slp hold time from SCKp1 ete 4 0 V lt EVppo lt 5 5 V 2 V Ve x 4 0V Co 30 pF Ro 1 4 KQ 2 7 V lt EVppo
11. EVppo 5 5 V lou 0 6 mA P20 to P27 P150 to P156 2 4 V lt Voo lt 5 5 V loi2 400 wA P60 to P63 4 0 V EVppo lt 5 5 V los 15 0 mA 4 0 V EVppo lt 5 5 V lors 5 0 mA 2 7 V EVppo lt 5 5 V lors 3 0 mA 2 4 V EVppo lt 5 5 V lors 2 0 mA Caution P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS RL78 G13 TA 40 to 105 C 2 4 V x EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 5 5 Input leakage current high CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVppo P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection Input leakage current low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 P20 to P27 P137 P150 to P1
12. 1 2 2 Transfer rate x 2 Cb x Rox In 1 Vo 1 x 100 96 Transfer rate Baud rate error theoretical value x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when the conditions described in the C onditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer 7tENESAS m RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 The smaller maximum transfer rate derived by using fwck 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V x EVbppo lt 4 0 V and 2 3 V lt V lt 2 7 V Maximum transfer rate L bps Cox Rox In 1 ec x3 1 2 0 Transfer rate x 2 Cb x Rox In 1 Vb ple Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 4 This value as an example is calculated when the conditions described in the C onditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 5 Use it with EVppo gt Vb 6 The smaller maximum transfer rate derived by using fwck 6 or the following expression is t
13. 2 7 V lt EVppo lt 4 0 V 2 3Vx Vox 2 7 V C 50 pF Re 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 7 V x Vs x 4 0 V C 100 pF Ro 2 8 kQ 2 7 V lt EVppo lt 4 0 V 2 3 V Vs x 2 7 V 100 pF Ro 2 7 KQ 1 8 V lt EVooo lt 3 3 V 1 6V lt Vo lt 2 0 Vote 100 pF Ro 5 5 kQ Notes 1 The value must also be equal to or less than fuck 4 2 Use it with EVppo Vb 3 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SDAr pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vu see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 7tENESAS 55 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Simplified lC mode connection diagram during communication at different potential Vb Vb Rb Rb SDAr microcontroller RL78 User device SCLr SCL Simplified l C mode serial transfer timing during communication at different potential 1 fsc tLow tHIGH SCLr SDAr tHD DAT tsu
14. 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 20 to 64 pin products TA 40 to 85 C 1 6 V lt EVppo x Voo x 5 5 V Vss EVsso 0 V 1 2 Parameter Conditions Supply loot Operating HS high fiu 32 MHz Basic Voo 5 0 V 2 4 mA current Note mode D operation Va 30V 24 TA Normal Voo 5 0 V 4 6 7 0 mA operation Vap 3 0 V 46 70 mA fiu 24 MHz Normal Voo 5 0 V 3 7 5 5 mA operation Vap 3 0 V 37 5 5 mA fiu 16 MHz Normal Voo 5 0 V 27 4 0 mA operation Von 3 0 V 27 40 mA LS low fin 8 MHz Nomal Von 3 0 V 1 2 1 8 mA speed main operation Von 2 0 V 12 18 mA mode e 5 LV low fiu 24MHz Nomal Voo 3 0 V 1 2 1 7 mA voltage main operation Vap 2 0 V 12 17 mA mode HS high fmx 20 MHz Normal Square wave input 3 0 4 6 mA speed main Voo 5 0 V operation Resonator connection 3 2 4 8 mA mode fmx 20 MHz Normal Square wave input 3 0 4 6 mA Voo 3 0 V operation Resonator connection 3 2 4 8 mA fmx 10 MHz Normal Square wave input 1 9 2 7 mA Voo 5 0 V operation Resonator connection 1 9 2 7 mA fmx 10 MHz Normal Square wave input 1 9 2 7 mA Voo 3 0 V operation Resonator connection
15. Voo 5 5 V 1 MHz to 32 MHz 2 4 V Voo 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo lt 5 5 V1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 5 5 V 1 MHz to 4 MHz HS high speed main mode only 2 7 V lt Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo lt 5 5 V 1 MHz to 16 MHz High speed on chip oscillator clock accuracy 1 8 V x Voo lt 5 5 V 1 0 Ta 20 C to 85 C 1 5 Ta 40 C to 20 C 1 6 V lt Voo lt 1 8 V 5 0 Ta 20 C to 85 C 5 5 Ta 40 C to 20 C 2 4 V lt Voo lt 5 5 V 2 0 Ta 85 C to 105 C 1 0 Ta 20 C to 85 C 1 5 Ta 40 C to 20 C Serial array unit UART CSI fcLk 2 supporting 16 Mbps fctk 4 Simplified I C communication UART CSI fcLk 4 Simplified C communication Normal mode Fast mode Fast mode plus Normal mode Fast mode Voltage detector Rise detection voltage 1 67 V to 4 06 V 14 levels Fall detection voltage 1 63 V to 3 98 V 14 levels Rise detection voltage 2 61 V to 4 06 V 8 levels Fall detection voltage 2 55 V to 3 98 V 8 levels 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Remark The electrical characteristics of the products G Industrial applications TA 40 to 105 C are different from those of the products A Consumer ap plications and D Industria applications For details refer to
16. m Unit number n Channel number mn 00 4 This value is valid only when CSIOO s peripheral I O redirect function is not used 7tENESAS ne RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcv1 2 4 fcik 4 0 V lt EVopo lt 5 5 V 2 7 V Vo lt 4 0 V C 30 pF Rb 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3V x Vox 2 7 V C 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V 30 pF Rb 5 5 kQ SCKp high level 4 0 V x EVppo x 5 5 V width 2 7 V lt Vo x 4 0V 30 pF Ro 1 4 KQ 2 7 V EVopo lt 4 0 V tkcy1 2 tkcy1 2 tkcy1 2 2 3V lt Vb lt 2 7V 170 170 170 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Ve lt 2 0 V ots 30 pF Rb 5 5 KQ SCKp low level 4 0 V lt EVopo lt 5 5 V tkcy1 2 tkcy1 2 tkcy1 2 width 2 7 V lt V o lt 4 0 V 12 50 50 30 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V tkcy1 2 tkcy1 2
17. 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and SCKp pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected CSI mode connection diagram during communication at different potential Slave Vb pA SCKp SCK RL78 microcontroller Slip SO User device SOp SI Remarks 1 R O Communication line SOp pull up resistance Ce F Communication line SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communi
18. 85 C 3 128 pin products and flash ROM 384 to 512 KB of 44 to 100 pin products TA 40 to 85 C 1 6 V lt EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current Note 1 HS high Speed main mode Note 7 LS low speed main mode Note 7 Conditions fin 32 MHz Voo 5 0 V Voo 3 0 V fiu 24 MHz 74 Voo 5 0 V Voo 3 0 V fiu 16 MHz 74 fiu 8 MHz Voo 5 0 V Voo 3 0 V Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 7 fiu 4 MHz Voo 3 0 V Voo 2 0 V HS high speed main mode Note 7 fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 20 MHz 3 Voo 3 0 V Square wave input Resonator connection fux 10 MHzN 3 Voo 5 0 V Square wave input Resonator connection fux 10 MHz o 3 Voo 3 0 V Square wave input Resonator connection LS low speed main mode Note 7 fux 8 MHZ Voo 3 0 V Square wave input Resonator connection fux 8 MHzNote 3 Voo 2 0 V Square wave input Resonator connection Subsystem clock operation fsus 32 768 kHz 5 Ta 40 C Square wave input Resonator connection fsus 32 768 kHz gt Ta 25 C Square wave input Resonator connection fsue 32 768 kHz e Ta 50 C Square wave input Reso
19. HS high speed 2 7 V lt Vo lt 5 5 V clock fmain main mode 0 03125 24VxVp 27V 0 0625 operation LS low speed main mode 1 8V lt Vo0 lt 5 5V 0 125 LV low voltage 1 6 V lt Vo lt 5 5 V main mode 0 25 Subsystem clock fsus operation 1 8V lt Vo0 lt 5 5V 28 5 In the self programming main mode mode HS high speed 2 7 V lt Voo lt 5 5 V 0 03125 24VxVp 27V 0 0625 LS low speed main mode 18V lt Vo0 lt 5 5V 0 125 LV low voltage 1 8 V lt Voo lt 5 5 V main mode 0 25 External system clock frequency 2 7 V lt Voo lt 5 5 V 1 0 2 4 V lt Voo lt 2 7 V 1 0 1 8 V lt Voo lt 2 4 V 1 0 1 6 V lt Voo lt 1 8 V 1 0 fexs 32 External system clock input high level width low level width tExH text 2 7 V lt Voo lt 5 5 V 24 2 4 V lt Voo lt 2 7 V 30 1 8 V lt Voo lt 2 4 V 60 1 6 V lt Voo lt 1 8 V 120 texus tEXLS 13 7 TIOO to TIO7 T110 to TI17 input high level width low level width ttik tri 1 fuck 10 TOO0 to TO07 TO10 to TO17 output frequency fro HS high speed main mode 4 0 V lt EVbppo lt 5 5 V o 2 7 V lt EVppo lt 4 0 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVppo lt 1 8 V LS low speed main mode 1 8 V x EVppo x 5 5 V 1 6 V x EVppo lt 1 8 V
20. P10 to P17 P30 P31 4 0 V lt EVooo lt 5 5 V 80 0 PSO to P57 P64 to P67 P70 to P77 P80 tol 2 7 Y lt Ev lt 4 0 V 19 0 P87 P90 to P97 P100 P101 P110 to P117 P146 P147 1 8 V lt EVppo lt 2 7 V 10 0 When duty lt 70 1 6 V lt EVbpo lt 1 8 V 5 0 Total of all pins 1 6 V lt EVppo x 5 5 V 135 0 When duty lt 70 3 Note 4 Per pin for P20 to P27 P150 to P156 1 6 V lt Voo lt 5 5 V 0 Nee Total of all pins 1 6 V lt Voo lt 5 5 V 1 5 When duty lt 70 3 Value of current at which the device operation is guaranteed even ifthe current flows from the E Vppo EVpp1 Voo pins to an output pin However do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lon x 0 7 n x 0 01 Example Where n 80 and lou 10 0 mA Total output current of pins 710 0 x 0 7 80 x 0 01 8 7 mA However the current that is allo wed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin The applied current for the products for industrial application R5F100xxDxx R5F101xxDxx is 100 mA P00 P02 to P04 P10 to P
21. Re 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 KQ MIN MAX LS low speed main MIN Mode MAX LV low voltage main Mode MIN MAX 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 VN 30 pF Rb 5 5 KQ Slp hold time from SCKp4 ete 4 0 V lt EVppo lt 5 5 V 2 V Ve x 4 0V Co 30 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 23VxVex27V 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote 30 pF Ro 5 5 KQ Delay time from SCKpT to SOp output Note 1 Notes 1 4 0 V x EVppo x 5 5 V 2 V xVe x 4 0V Co 30 pF Re 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3V x Vox 2 7 V 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Ve lt 2 0 V ote Co 30 pF Rb 5 5 KQ When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 7tENESAS d RL78 G13 CHAPTER 29 ELECTRICAL SPECIFIC
22. ViW VoH Vi VoH Test points Vi VoL p REC Vi VoL 30 5 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions HS high speed main Mode MIN MAX Transfer rate N fuci 12 Note Theoretical value of the 2 6 maximum transfer rate fcuk 32 MHz fuck fei Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evopo lt Vpp 2 4 V EVppo lt 2 7 V MAX 1 3 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 2 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 7tENESAS zh RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to
23. Voo lt 5 5 V Vss EVsso EVssi 0 V Conditions Instruction cycle minimum Main HS high speed 2 7 V lt Von x 5 5 V 0 03125 instruction execution time system main mode 24V xVmo 27 V 0 0625 clock fuain i i operation Subsystem clock fsus 24V Vpx55V 28 5 operation In the self HS high speed 2 7 V lt Von x 5 5 V 0 03125 programming main mode 24V xVp 27 V 0 0625 mode External system clock frequency fex 2 7V lt Vo0 lt 5 5V 1 0 24 V lt Voo lt 2 7 V 1 0 fexs 32 External system clock input high texn tex 2 7 V lt Voo lt 5 5 V 24 level width low level width 24V lt Voo lt 27V 30 texus 13 7 texLs TIOO to TIO7 TI10 to TI17 input trin 1 fuck 10 high level width low level width tri TOOO to TOO7 TO10 to TO17 fro HS high speed 4 0 V EVppo x 5 5 V output frequency main mode 2 7 V lt EVopo lt 4 0 V 2 4 V EVppo lt 2 7 V PCLBUZO PCLBUZ1 output HS high speed 4 0 V EVppo 5 5 V frequency main mode 2 7 V EVopo lt 40 V 2 4 V lt EVppo lt 2 7 V Interrupt input high level width INTPO 2 4 V lt Voo lt 5 5 V low level width INTP1 to INTP11 2 4 V lt EVopo lt 5 5 V Key interrupt input low level width KRO to KR7 2 4 V lt EVppo lt 5 5 V RESET low level width Note The following conditions are required for low voltage interface when Evopo lt Vop 2 4V lt
24. fcLk 2 7 V EVppo lt 4 0 V fuck 6 Note 1 2 3V lt Vo lt 2 7V i Theoretical value 5 3 of the maximum transfer rate Note 4 fuck fcLK 1 8 V x EVppo lt 3 3 V fuck 6 fuck 6 fuck 6 Notes 1 to Notes 1 2 Notes 1 2 1 6 V lt Vo lt 2 0 V 3 Theoretical value 5 3 of the maximum transfer rate Note 4 fuck fei Transfer rate in the SNOOZE mode is 4800 bps only Use it with EVppo gt Vb The following conditions are required for low voltage interface when Evopo lt Vp 2 4 V EVppo lt 2 7 V MAX 2 6 Mbps 1 8 V lt EVppo lt 2 4 V MAX 1 3 Mbps The maximum operating frequencies of the CPU peripheral hardware clock fck are HS high speed main mode 32 MHz 2 7 V lt Voo x 5 5 V 16 MHz 2 4 V Vop lt 5 5 V LS low speed main mode 8 MHz 1 8 V lt Voo x 5 5 V LV low voltage main mode 4 MHz 1 6 V x Voo x 5 5 V Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Viu and Vit see the DC characteristics with TTL input buffer selected Vo V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 3 fuck Serial array unit operation clock frequency Operation cl
25. lt 24 MHz 72 fuck 16 MHz lt fuck lt 20 MHz 64 fuck 8 MHz lt fuck x 16 MHz 52 fuck 4 MHz lt fuck lt 8 MHz 32 fuck fuck lt 4 MHz 20 fuck SCKp high low level width 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V tkcy2 2 24 tkcy2 2 36 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V oe tkcy2 2 100 Slp setup time to SCKp e 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V 1 fuck 40 2 7 V lt EVppo x 4 0 V 2 3V lt Vb lt 2 7V 1 fuck 40 2 4 V lt EVppo x 3 3 V 1 6 V lt Vb lt 2 0 V 1 fuck 60 Slp hold time from SCKp1 ete 1 fmck 62 Delay time from SCKp to SOp output 4 4 0 V lt EVppo 5 5 V 2 7 V lt Vo lt 4 0 V 30 pF Rb 1 4 KQ 2 fuck 240 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V C 30 pF Rb 2 7 KQ 2 fuck 428 2 4 V lt EVppo lt 8 3 V 1 6 V lt V lt 20V C 30 pF Ro 5 5 kQ Notes Caution and Remarks are listed on the next page 7tENESAS 2 fuck 1146 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 Transfer rate in the SNOOZE mode MAX 1 Mbps 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0
26. lt 4 0 V 2 3Vx Vox 2 7 V C 100 pF Rb 2 7 kQ 1 8 V lt EVbpo lt 3 3 V 16VxVox2 0 Vote 100 pF Rb 5 5 kQ 7tENESAS ud RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 10 Communication at different potential 1 8 V 2 5 V 3 V simplified Pc mode 2 2 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Data setup time 4 0 V lt EVppo lt 5 5 V 1 fuck 1 fwck 1 fuck reception 2 7 V Vex 4 0 V 135 Notes id 1 90 t 1 90 50 pF Rb 2 7 kQ 2 7 V EVppo lt 4 0 V 1 fuck 1 fuck 1 fuck 2 3V lt Vb lt 27V 135 9e 190 190 ote lote Cb 50 pF Rb 2 7 KQ 4 0 V x EVppo 5 5 V 1 fuck 1 fuck 1 fuck 2 7 V lt Vo lt 4 0 V 190 e 190 190 Note 3 Note 3 C 100 pF Ro 2 8 KQ 2 7 V EVppo lt 4 0 V 1 fuck 1 fuck 1 fuck 2 3 V lt Ve lt 2 7 V 190 Ns 190 190 Note 3 Note 3 C 100 pF Ro 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 fuick 1 fuck 1 fuck 1 6 V lt Vo lt 2 0 V Note 190 Noes 190 190 Note 3 Note 3 C 100 pF Ro 5 5 KQ Data hold time HD DAT 4 0 V lt EVppo lt 5 5 V 305 0 805 0 305 transmission 2 7 V lt Vb lt 4 0 V C 50 pF Rb 2 7 KQ
27. 0 V maximum speed A D converter reference voltage current Temperature sensor operating current LVD operating lvi current Notes 1 7 Self programming operating current Notes 1 9 IrsP BGO operating Igco current Notes 1 8 SNOOZE operating current Notes 1 2 3 Note 1 Note 10 IsNoz ADC operation The mode is performed The A D conversion operations are performed Low voltage mode AVrerr Voo 3 0 V CSI UART operation Current flowing to Vpp When high speed on chip oscillator and high speed system clock are stopped Current flowing only to the r eal time clock RTC excluding the operating current of the lo w speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the v alues of either Ipp1 or Ipp2 and Inrc when the real time clock operates in operation mode or HALT mode When the low speed on chip oscillator is selected Fit should be a dded pp2 subsystem clock operation includes the operational current of the real time clock Current flowing only to the 12 bit interval timer excluding the op erating current of the lo w speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the v alues of either Ipp or Ipp2 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscil
28. 10 12 13 n Channel number n 7 0 2 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 49 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt EVppo EVpn1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time e 4 0 V EVbro x 5 5 V 24 MHz lt fuck 14 2 7 V lt Vo lt 4 0 V fuck 20 MHz lt fuck lt 24 MHz 12 fuck 8 MHz lt fuck lt 20 MHz 10 fuck 4 MHz lt fuck lt 8 MHz 8 fuck fuck 4 MHz 6 fuick 2 7 V EVppo lt 4 0 V 24 MHz lt fuck 20 23V lt Vo lt 2 7V fuck 20 MHz lt fuck lt 24 MHz 16 fuck 16 MHz lt fuck lt 20 MHz 14 fuck 8 MHz lt fuck x 16 MHz 12 fuck 4 MHz lt fuck lt 8 MHz 8 fuck fuck 4 MHz G fuck 1 8 V lt EVppo lt 3 3 V 24 MHz lt fuck 48 16V Ve 20 Vete fuck 20 MHz lt fuck x24 MHz 36 fuck 16 MHz lt fick x20 MHz 32 fuck 8 MHz fuck x 16 MHz 26 fuck 4 MHz lt fuck lt 8 MHz 16 fuc
29. 11 of 12 RENESAS TECHNICAL UPDATE TN RL A005A E 15 Supply Voltage Rise Time Old Specifications in Supply Voltage Rise Time in page 1045 added 16 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Old Specifications in Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics in page 1046 extended 17 Chapter 30 ELECTRICAL SPECIFICATIONS G TA 40 to 105 C TARGET Old Specifications in Chapter 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C in pages 1048 to 1098 fixed c 2013 Renesas Electronics Corporation All rights reserved RENESAS Date Apr 5 2013 New Refer to page 68 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 New Refer to page 69 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C MCYG AB 12 0384 New Refer to pages 2 to 54 in Technical Update Exhibit Chapter 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C MCYG AB 12 0385 Page 12 of 12 RENESAS TECHNICAL UPDATE EXHIBIT To our valued customers MCYG AB 12 0384 1 RL78 G13 March 15 2013 Technical Update Exhibit Dia Uchimura Chapter 29 ELECTRICAL M CO Solution Business Unit PECIFICATION A si nd A ede 3 MCU Business Division Brand Strategy Department Renesas Electronics Corporation Rep Seiya Indo Thank you for your continued su
30. 2 18 tkcy1 2 50 tkcy1 2 50 2 4 V lt EVppo x 5 5 V tkcvi 2 38 tkcy1 2 50 tkcvi 2 50 1 8 V lt EVppo lt 5 5 V tkcy1 2 50 tkcy1 2 50 tkcy1 2 50 1 7 V lt EVopo lt 5 5 V tkcy1 2 100 tkcy1 2 100 tkcy1 2 100 1 6 V lt EVbppo lt 5 5 V tkcy1 2 100 tkcy1 2 100 Slp setup time to SCKp Note 1 4 0 V x EVppo lt 5 5 V 110 110 2 7 V lt EVop0 x 5 5 V 110 110 2 4 V lt EVppox 5 5 V 110 110 1 8 V lt EVopo lt 5 5 V 110 110 1 7 V lt EVopo lt 5 5 V 220 220 1 6 V lt EVbppo lt 5 5 V 220 220 Slp hold time from SCKp1 ee 1 7 V lt EVopo lt 5 5 V 19 19 1 6 V lt EVbppo lt 5 5 V 19 19 Delay time from SCKpJ to SOp 1 7 V x EVbppo x 5 5 V C230 pFNete 4 Note 3 output 1 6 V x EVbppo x 5 5 V C230 pres Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp4 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and
31. 2 4 V lt EVpb lt 5 5 V 1 fuck 580 Cb 100 pF Ro 3 KQ ik Data hold time transmission tHD DAT 2 7 V EVppo 5 5 V Co 50 pF Rb 2 7 KQ 2 4 V EVppo lt 5 5 V C 100 pF Rb 3 KQ Notes 1 The value must also be equal to or less than fuck 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the normal input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page 434 NE SAS a RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Simplified lC mode mode connection diagram during communication at same potential Voo Rb SDAr SDA User device RL78 microcontroller SCLr SCL Simplified IC mode serial transfer timing during communication at same potential 1 fsc SCLr SDAr tHD DAT tsu DAT Remarks 1 R O Communication line SDAr pull up resistance Ce F Communication line SDAr SCLr load capacitance 2 r IIC number r 00 01 10 11 20 21 30 31 g PIM number g 0 1 4 5 8 14 h POM number g 0 1 4 5 7 to 9 14 3 fuck Serial array unit operation clock frequency Operation clock to b
32. 20 pF Rb 2 7 KQ SCKp low level 4 0 V lt EVopo lt 5 5 V tkcy1 2 tkcy1 2 tkcy1 2 width 27V lt V o lt 4 0 V 7 50 50 20 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 20 pF Rb 2 7 KQ Slp setup time 4 0 V lt EVppo lt 5 5 V to SCKpT 2 7 V Vo 4 0 V 20 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V 20 pF Rb 2 7 KQ Slp hold time 4 0 V lt EVppo lt 5 5 V rom p Vo lt 4 0 V from SCKpT ete 2 7 V Ve 4 0 V 20 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 23VxVoex27V 20 pF Rb 2 7 KQ Delay time from 4 0 V lt EVpp0 lt 5 5 V SCKp to SOp 2 7 V Ve x 4 0 V Note 1 output Cb 20 pF Ro 1 4 KQ 2 7 V lt EVbpo lt 4 0 V 2 3 V lt V x 2 7 V 20 pF Rb 2 7 KQ Notes Caution and Remarks are listed on the next page 7tENESAS a RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO only 2 2 Ta 40 to 85 C 2 7 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Slp setup time 4 0 V lt EVppo
33. 3 V 1 6 V lt Vo lt 2 0 V SCKp high level width 4 0 V lt EVooo lt 5 5 V 2 7 V lt Vo lt 4 0 V C 30 pF Ro 1 4 KQ tkcy1 2 150 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 KQ tkcy1 2 340 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Ro 5 5 KQ tkcy1 2 916 SCKp low level width 4 0VxEVppox 5 5 V 2 7 V lt Vo 4 0 V Co 30 pF Ro 1 4 KQ tkcy1 2 24 2 7 V xEVppo lt 4 0 V 2 3 V x Vo lt 2 7 V 30 pF Rb 2 7 KQ tkcy1 2 36 2 4 V lt EVppo lt 3 3 V 1 6 V x Vo lt 2 0 V 30 pF Ro 5 5 KQ tkcy1 2 100 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Viu and Vit see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page 434 NE SAS 34 RL78 G13 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 2 3 Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt Voo x 5 5 V Vss EVsso EVssi 0 V Parameter Slp setup time to SCKpT CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40
34. CKPmn 0 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Sip pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg 7tENESAS 32 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Remarks 1 g PIM and POM numbers g 0 1 4 5 8 14 2 fuck Serial array unit operation clock frequency p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 During communication at same potential CSI mode slave mode SCKp external clock input 1 2 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter SCKp cycle time Note 5 Conditions 4 0VxEVppo lt 5 5 V 20 MHz fuck HS high speed main Mode MIN MAX 8 fuck LS low speed main Mode MIN MAX LV low voltage main Mode MIN MAX fuck lt 20 MHz G fuck 2 7 V lt EVooo lt 5 5 V 16 MHz lt fuck 8 fuck fuck lt 16 MHz G fuck G fuck G fuck 2 4 V lt EVooo lt 5 5 V 6 fuck and 500 G fuck and 500 G fuck and 500 1 8VxEVppox 5 5 V 6 fuck and 750 G fuck and
35. LA Note 4 5 operation Resonator connection 5 3 9 4 LA Ta 70 C fsus 32 768 kHz Normal Square wave input 5 7 13 3 LA poten operation pe Resonator connection 5 8 13 4 LA Ta 85 C fsus 32 768 kHz Normal Square wave input 10 0 46 0 LA notes operation pe Resonator connection 10 0 46 0 LA Ta 105 C Notes and Remarks are listed on the next page 7tENESAS 15 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 Total current flowing into Voo EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped 3 When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped W hen AMPHS 1 1 Ultra low power consumption oscillation Ho wever not inclu ding the current flo wing into the 12 bit interv al timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vo
36. MAX MIN MAX SCLr clock frequency 2 7 V lt EVppo 5 5 V Cb 50 pF Ro 2 7 KQ 1 8 V EVppo 5 5 V C 100 pF Ro 3 KQ 1 8 V EVppo lt 2 7 V C 100 pF Ro 5 KQ 1 7 V EVppo lt 1 8 V Cb 100 pF Ro 5 KQ 1 6 V lt EVppo lt 1 8 V Co 100 pF Rb 5 KQ Hold time when SCLr L 2 7 V lt EVbppo lt 5 5 V Cb 50 pF Ro 2 7 KQ 1 8 V EVppo 5 5 V Co 100 pF Rb 3 KQ 1 8 V EVppo lt 2 7 V Co 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V Co 100 pF Rb 5 KQ 1 6 V lt EVppo lt 1 8 V Co 100 pF Rb 5 KQ Hold time when SCLr H 2 7 V EVppo 5 5 V Cb 50 pF Ro 2 7 KQ 1 8 V EVppo 5 5 V Cb 100 pF Rh 3 KQ 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V C 100 pF Rb 5 KQ 1 6 V lt EVppo lt 1 8 V Cb 100 pF Ro 5 KQ Notes and Caution are listed on the next page and Remarks are listed on the page after the next page 7tENESAS 36 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 5 During communication at same potential simplified Pc mode 2 2 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Data setup
37. P07 P32 to P37 170 mA P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Output current low Per pin POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of all pins POO to P04 P07 P32 to P37 170 mA P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin P20 to P27 P150 to P156 1 Total of all pins 5 Operating ambient In normal operation mode 40 to 85 temperature In flash memory programming mode Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as th
38. SPECIFICATIONS A D Ta 40 to 85 C ADREFM 1 target pin ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpn1 lt Voo lt 5 5 V 1 6 V lt AVrerp lt Voo lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 10 bit resolution EVppo AVnere Vpp Notes 3 4 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnere lt 5 5 V NOS Conversion time 10 bit resolution Target ANI pin ANI16 to ANI26 3 6 V lt VoD lt 5 5 V 39 2 7 V lt VDD lt 5 5 V 39 1 8 V lt VoD lt 5 5 V 39 1 6 V lt VoD lt 5 5 V 95 Zero scale error Notes 1 2 10 bit resolution EVppo AVnere Vpp Notes 4 1 8 V lt AVrere lt 5 5 V 0 35 1 6 V lt AVnere lt 5 5 VMS 0 60 Full scale error Notes 1 2 10 bit resolution EVDDo AVrerp Vpp Notes 3 4 1 8 V x AVrere lt 5 5 V 0 35 1 6 V lt AVnere lt 5 5 VMS 0 60 Integral linearity error Note 1 10 bit resolution EVppo AVnere Vpp Notes 34 1 8 V lt AVrere lt 5 5 V 3 5 1 6 V lt AVnere lt 5 5 V Nete 6 0 Differential linearity error ete 10 bit resolution EVppo AVnere Vpp Notes 3 4 1 8 V x AVrere 5 5 V 2 0 1 6 V lt AVnere lt 5 5 V Noe 12 5 Analog input voltage ANI16 to ANI26 Notes 1 E
39. clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 7tENESAS ne RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 5 2 Serial interface IICA Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Vpp x 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode Standard Mode Fast Mode MAX MIN MAX SCLAO clock frequency Fast mode fc k 2 3 5 MHz Standard mode fck gt 1 MHz Setup time of restart condition tsu sTA Hold time tHD sTA Hold time when SCLAO L tow Hold time when SCLAO H tHiGH Data setup time reception tsu DAT Note 2 Data hold time transmission tHD DAT Setup time of stop condition tsu sto Bus free time teur Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MA X of tub pAr is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics lou lot1 Voui VoL must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communica
40. fmx 10 MHz Normal Square wave input Voo 3 0 V operation Resonator connection Subsystem fsus 32 768 kHz Normal Square wave input clock Note 4 operation operation Ta 40 C fsus 32 768 kHz Nomal Square wave input Note operation Resonator connection Resonator connection Ta 25 C fsus 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 50 C fsus 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 70 C fsus 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 85 C fsus 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 105 C Notes and Remarks are listed on the next page 7tENESAS H RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 Total current flowing into Voo and EVopo including the input leakage current flowing when the level of the input pin is fixed to Voo EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped 3 When high speed sy
41. input buffer 4 0 V lt EVpp0 lt 5 5 V TTL input buffer 3 3 V lt EVppo lt 4 0 V 2 0 TTL input buffer 1 6 V lt EVppo lt 3 3 V 1 5 P20 to P27 P150 to P156 0 7Vop P60 to P63 0 7EVppo 6 0 P121 to P124 P137 EXCLK EXCLKS RESET 0 8Vop Voo Input voltage low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Normal input buffer 0 0 2EVppo P01 P03 P04 P10 P11 P13 to P17 P43 P44 P53 to P55 P80 P81 P142 P143 TTL input buffer 4 0 V lt EVpp0 lt 5 5 V TTL input buffer 3 3 V lt EVppo lt 4 0 V TTL input buffer 1 6 V lt EVppo lt 3 3 V P20 to P27 P150 to P156 P60 to P63 0 3EVppo P121 to P124 P137 EXCLK EXCLKS RESET 0 2Vop Caution The maximum value of Vin of pins P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 is EVppo even in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 6 V lt EVppo EVppi lt Vpp lt 5 5 V Vss EVsso EVssi 0 V 4 5 Output voltage high Conditions POO to P07 P
42. into the RT C is includ ed However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz Regarding the value for current operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is Ta 25 C 7tENESAS us RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 Peripheral Functions Common to all products Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions MIN Low speed on m 0 20 LA chip oscillator operating current RTC operating Irro NS 0 02 LA current a 12 bit interval jj Meteo 4 5 0 22 uA timer operating 4 current Watchdog timer lwor fi 15 kHz 0 22 uA operating current A D conver
43. lt 4 0 V 23VxVex27V 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote 30 pF Ro 5 5 KQ Delay time from SCKp4 to SOp output Note 1 Notes 1 4 0 V x EVppo x 5 5 V 2 V xVe x 4 0V Co 30 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Ve lt 2 0 V ote 30 pF Ro 5 5 KQ When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page 7tENESAS a RL78 G13 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Slp setup time to SCKpJ N Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V xVe amp 4 0V Co 30 pF
44. lt 5 5 V to SCKp4 e 2 7 V Vo 4 0 V Co 20 pF Ro 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3VxVox2 V 20 pF Rb 2 7 KQ Slp hold time 4 0 V x EVppo x 5 5 V from SCKp4 ete 2 7 V Vo 4 0 V C 20 pF Rb 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt V lt 2 7 V 20 pF Rb 2 7 KQ Delay time from SCKpT 4 0 V lt EVppo 5 5 V to 2 7V lt Vb lt 4 0V SOp output C 20 pF Re 1 4 KQ 2 7 V lt EVooo lt 4 0 V 2 3 V lt V lt 2 7 V 20 pF Rb 2 7 KQ Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks 1 R O Communication line SCKp SOp pull up resistance Ce F Communication line SCKp SOp load capacitance V V Communication line voltage 2 p CSI number p 00 m Unit number m 0 n Channel number n 0 g PIM and POM number g 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of seri al mode registe r mn SMRmn
45. n 0 to 3 g PIM number g 0 1 4 5 8 14 2 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of seri al mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 7tENESAS 2 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at same potential 2912 SCKp SCK RL78 Slp SO User device microcontroller SOp SI CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 2 tKL1 2 tkun2 SCKp tsik1 2 tksn 2 ain Slp tkso1 2 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 2 SCKp tsik1 2 tksi1 2 a Slp tkso1 2 __ SOp 35 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 2 m Unit number n Channel number mn 00 to 03 10 to 13 5 During communication at same potential simplified ic mode 1 2 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN
46. ns 1 6 V lt Vo lt 2 0 V 9e 573 573 573 30 pF Rb 5 5 KQ Caution Transfer rate in the SNOOZE mode MAX 1 Mbps Use it with EVppo 2 Vb When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output b ecomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 7tENESAS 21 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at different potential Slave Vb SCKp RL78 microcontroller Slp SO User device SOp SI Remarks 1 Re O Communication line SOp pull up resistance Ce F Communication line SOp load capacitance Vo V C
47. rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RT C is includ ed However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz Regarding the value for current operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is Ta 25 C 7tENESAS 1 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5
48. see the DC characteristics with TTL input buffer selected Remarks 1 V V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of seri al mode registe r mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 7tENESAS ao RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Ta 40 to 105 C 2 4 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX Transfer rate Transmission 4 0 V EVppo x 5 5 V Note 1 2 7 Vs Vos 4 0V Theoretical value of the 2 6 Note maximum transfer rate Cb 50 pF Ro 1 4 KO Vo 2 7 V 2 7 V EVpro lt 4 0 V 2 3V lt Vb lt 2 7V Theoretical value of the maximum transfer rate 50 pF Rb 2 7 KO Vb 2 3 V 2 4 V EVpro lt 3 3 V 1 6 V lt Vo lt 2 0 V Theoretical value of the maximum transfer rate 50 pF Rb 5 5 KO Vb 1 6 V Notes 1 The smaller maximum transfer rate derived by using fuck 12 or the following expression is the valid maximum transfer rate Expression for ca
49. 0 bit resolution 3 6 V lt VDD lt 5 5 V Target pin ANIO to ANI14 27V Vpp 55 V ANI16 to ANI26 1 8V lt Vpp lt 5 5V 1 6V lt Vpp lt 5 5V Conversion time 10 bit resolution 3 6 V lt Voo lt 5 5 V Target pin internal reference 27V Vpp 55 V voltage and temperature sensor output voltage HS high speed main mode 9 l la la la 2 4 V lt VoD lt 5 5 V Zero scale error etes t 2 10 bit resolution 1 8V lt Vpp lt 5 5V 1 6V lt Vpp lt 5 5V Note 3 Full scale error etes 1 2 10 bit resolution 1 8 V lt Voo lt 5 5 V 1 6 V lt Voo lt 5 5 V Note 3 Mere 10 bit resolution 1 8 V lt VDD lt 5 5 V 1 6 V lt VDD lt 5 5V Note 3 Integral linearity error Differential linearity error N 10 bit resolution 1 8 V lt VDD 5 5 V 1 6 V lt Voo lt 5 5 V Note 3 Analog input voltage ANIO to ANI14 ANI16 to ANI26 Internal reference voltage output Vecer e 2 4 V lt VDD lt 5 5 V HS high speed main mode Temperature sensor output voltage Vimpsas Note 4 2 4 V lt VoD lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When the conversion time is set to 57 ws min and 95 ws max 4 Refer to 29 6 2 Temperature sensor internal reference voltage characteristics 7tENESAS in RL78 G13 4 W
50. 0 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 POO to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin Total of all pins P20 to P27 P150 to P156 Operating ambient temperature In normal operation mode In flash memory programming mode 40 to 105 Storage temperature Note Total operating time in 85 C to 105 C 10 000 hours Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 7tENESAS 65 to 150 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 2 Oscillator Characteristics 30 2 1 X1 XT1 oscillator characteristics Ta 40 to 105 C 2 4 V lt Voo 5 5 V Vss 0 V Resonator Conditions X1 clock oscillation Ceramic resonator 2 7
51. 1 9 2 7 mA LS low fmx 8 MHz Normal Square wave input 1 1 1 7 mA speed main Voo 3 0 V operation Resonator connection 1 1 1 7 mA mode fmx 8 MHz Normal Square wave input 1 1 1 7 mA Voo 2 0 V operation Resonator connection 1 1 1 7 mA Subsystem fsus 32 768 kHz Nomal Square wave input 4 1 4 9 LA clock A operation Resonator connection 4 2 5 0 LA operation Ta 40 C fsus 32 768 kHz Nomal Square wave input 4 1 4 9 LA Md operation Resonator connection 4 2 5 0 uA Ta 25 C fsus 32 768 kHz Normal Square wave input 4 2 5 5 LA Noto operation Resonator connection 4 3 5 6 uA Ta 50 C fsus 32 768 kHz Normal Square wave input 4 3 6 3 LA ica operation Resonator connection 4 4 6 4 LA Ta 70 C fsus 32 768 kHz Normal Square wave input 4 6 7 7 LA Note d operation Resonator connection 4 7 7 8 uA Ta 85 C Notes and Remarks are listed on the next page 7tENESAS H RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into Voo and EVppo including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flas
52. 10 RO1UH0146EJ0210 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C This chapter describes the electrical specifications for the products G Industrial applications Ta 40 to 105 C Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 With products not provided with an EVppo EVbo EVsso or EVss pin replace EVooo and EV with Vpp or replace EVsso and EVss with Vss 3 The pins mounted depend on the product Refer to 2 1 Port Function to 2 2 1 With functions for each product There are following differences between the products G Industrial applications TA 40 to 105 C and the pro ducts A Consumer applications and D Industrial applications Parameter Operating ambient temperature Application A Consumer applications D Industrial applications 40 to 85 C G Industrial applications 40 to 105 C Operating mode Operating voltage range HS high speed main mode 2 7 V
53. 10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 4 0 V EVppo lt 5 5 V lou 10 0 mA 4 0 V EVppo lt 5 5 V lou 3 0 mA 2 7 V EVppo 5 5 V lou 2 0 mA 1 8 V EVbpo lt 5 5 V lou 21 5 mA 1 6 V lt EVopo lt 5 5 V lou 1 0 mA P20 to P27 P150 to P156 1 6 V x Voo x 5 5 V lon2 100 u A Output voltage low Caution P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 P20 to P27 P150 to P156 4 0 V EVppo lt 5 5 V lou 20 mA 4 0 V EVppo lt 5 5 V lo 8 5 mA 2 7 V EVppo 5 5 V lo 3 0 mA 2 7 V EVppo 5 5 V lou 1 5 mA 1 8 V EVppo lt 5 5 V lo 0 6 mA 1 6 V EVppo lt 5 5 V lo 0 3 mA 1 6 V x Voo x 5 5 V loi2 400 u A P60 to P63 4 0 V EVppo lt 5 5 V lors 15 0 mA 4 0 V EVppo lt 5 5 V lors 5 0 mA 2 7 V EVppo 5 5 V lors 3 0 mA 1 8 V EVppo lt 5 5 V lors 2 0 mA 1 6 V EVppo lt 5 5 V lors 1 0 mA P144 do not output high level in N ch open drain mode
54. 10000H xz6to08Ato C Eto G J L 00000H to OFFEH FEFO0H to FFEEFH x 6 to 8 Ato C E to G J L 00000H to 07FFFH FF700H to FFEFFH R5F100xF R5F101xF 98304 x 8 bit 8192 x 8 bit R5F100xD R5F101xD 49152 x 8 bit 3072 x 8 bit 10000H z P FFE E FF x 6 to 8 Ato C Eto G J L 00000H to OBFFFH FF300H to FFEFFH R5F100xG R5F101xG 1 72x i 1 X i R5F100xE R5F101xE 65536 x 8 bit 4096 x 8 bit 10000H X zAto C Eto G J L M P 00000H to 1EEFEH ECFO0H to FFEFEH x 6to 8 Ato C E to G J L 00000H to OFFFH FEFOOH to FFEFFH R5F100xH R5F101xH 1 x i 1 x i R5F100xF R5F101xF 98304 x 8 bit 8192 x 8 bit 20000H x E to G J L M P S 00000H to 2FFFEH EBEQOH to FEEFFH x A to C E to G J L M P 00000H to 17FFFH FDFOOH to FFEFFH R5F100xJ R5F101xJ 262144 x 8 bit 20480 x 8 bit R5F100xG R5F101xG 131072 x 8 bit 12288 x 8 bit 20000H x F G J L M P S 00000H to 3FFFEH EAFQO0H to FFEFFH x A to C E to G J L M P 00000H to 1FFFFH FCFOOH to FFEFFH R5F100xK R5F101xK 393216 x 8 bit 4576 x i R5F100xH R5F101xH 196608 x 8 bit 16384 x 8 bit 30000H x z E G J L M P S 00000H to 5FFFEH F9F00H to FFEFFH x E to G J L M P S 00000H to 2FFFFH FBFOOH to FFEFFH R5F100xL R5F101xL 524288 x 8 bit 32768 x 8 bit R5F100xJ R5F101xJ 262144 x 8 bit 20480 x 8 bit 40000H F G J L M P S 00000H to ZFFFEH EZEO00H to FFEFFH x F G J L M P S 00000H to 3FFFFH FAF00H to FFEFFH R5F100xK R5F101xK
55. 105 C 2 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 105 C 2 4 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX SCKp cycle time tkcy1 2 4 fcik 2 7 V lt EVopo lt 5 5 V 250 2 4 V lt EVopo lt 5 5 V 500 SCKp high low level width 4 0 V lt EVbopo lt 5 5 V tkcv1 2 24 2 7 V lt EVopo lt 5 5 V tkcy1 2 36 2 4 V lt EVopo lt 5 5 V tkcy1 2 76 Slp setup time to SCKpf N 4 0 V lt EVppo lt 5 5 V 66 2 7 V lt EVopo lt 5 5 V 66 2 4 V lt EVopo lt 5 5 V 113 Slp hold time from SCKp1 N 38 Delay time from SCKp to C 30 pr SOp output Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip setup time becomes to SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Sip pin and the normal output mode for the SOp pin and SCKp pin by usin
56. 15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 do not output high level in N ch open drain mode Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS e RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 5 Output current Note 1 low 5 Notes 1 Conditions Per pin for POO to P07 P10 to P17 20 0 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Per pin for P60 to P63 15 0 Note Total of POO to P04 P07 P32 to P37 4 0 V lt EVon lt 5 5 V 70 0 P40 to P47 P102 to P106 P120 P425 5 7V lt Ev e 40V 150 to P127 P130 P140 to P145 When duty lt 70 1 8 V x EVppo lt 2 7 V 9 0 1 6 V x EVppo lt 1 8 V 4 5 Total of P05 P06 P10 to P17 P30 A40 V lt EVopo lt 5 5 V 80 0 P31 P50 to P57 P60 to P67 SISE EAN m P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 1 8 V lt EVoo lt 2 7 V 20 0 P147 1 6 V lt EVoro lt 1 8 V 10 0 When duty lt 70 Total of all pins 150 0 When duty lt 70 e3 Per pin for P20 to P27 P150 to P156 Q4 06 Total of all pins 1 6 V lt Voo lt 5 5 V 5 0 When duty lt 70
57. 30 1 to 30 10 30 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C 1 2 Parameter Symbols Conditions Ratings Supply voltage Voo 0 5 to 6 5 EVppo EVpo1 EVopo EVpo1 0 5 to 6 5 V EVsso EVss1 EVsso EVss1 0 5 to 0 3 V REGC pin input voltage Virecc REGC 0 3 to 2 8 V and 0 3 to Voo 40 3 Input voltage Vu POO to P07 P10 to P17 P30 to P37 P40 to P47 0 3 to EVppo 0 3 V P50 to P57 P64 to P67 P70 to P77 P80 to P87 and 0 3 to Voo 0 3Ne e P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi2 P60 to P63 N ch open drain 0 3 to 6 5 V Vis P20 to P27 P121 to P124 P137 P150 to P156 0 3 to Von 40 3 V EXCLK EXCLKS RESET Output voltage Voi POO to P07 P10 to P17 P30 to P37 P40 to P47 0 3 to EVppo 0 3 V P50 to P57 P60 to P67 P70 to P77 P80 to P87 and 0 3 to Vop 0 3 2 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Vo2 P20 to P27 P150 to P156 0 3 to Von 40 3 N V Analog input voltage Van ANI16 to ANI26 0 3 to EVppo 0 3 V and 0 3 to AVrer 0 3 Netes 2 3 Vai2 ANIO to ANI14 0 3 to Voo 0 3 V and 0 3 to AVner 0 3Netes 2 3 Notes 1 Connect the REGC pin to Vss viaa c apacitor 0 47 to 1 4F This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it 2 Must be 6 5 V or lower 3 Do not exc
58. 30 6 3 POR circuit characteristics Ta 40 to 105 C Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Minimum pulse width Note Minimum time required for a POR reset when Von exceeds below Vror This is also the minimum time required for a POR reset from when Voo exceeds below 0 7 V to when Voo exceeds Vror while STOP mode is entered or the main system clock is stopped through setting bit O HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC TPw Supply voltage Vpp VEDR or 0 7 V 999 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 105 C Vppr lt Voo lt 5 5 V Vss 0 V Parameter Conditions Detection Supply voltage level Power supply rise time voltage Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Minimum pulse width 55 lt I lt l lt l lt l lt lt lt l
59. 31 morn SCKp1 17 V lt EVo00 lt 5 5 V Affucick 4 HfucK Affucic 250 250 250 1 6 V lt EVppo 5 5 V 1 fuck 1 fuck 250 250 Delay time from C 30 27V xEVppox5 5V 2 fuck 2 fuck 2 fuck SCKpl to SOp pF Note4 44 110 110 Note 3 output 2 4 V lt EVopo lt 5 5 V 2lfmck 2lfmck 2lfmck 44 110 110 1 8 V lt EVppo lt 5 5 V 2 fmck 2 fuck 2 fuck 110 110 110 1 7 V lt EVop0 lt 5 5 V 2 fuck 2 fuck 2 fuck 220 220 220 1 6 V lt EVppo 5 5 V 2 fuck 2 fuck 220 220 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SOp output lines 5 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution Select the normal input buffer for the Slp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number
60. 393216 x 8 bit 24576 x 8 bit 60000H x F G J L M P S 00000H to 5FFFFH F9F00H to FFEFFH R5F100xL R5F101xL 524288 x 8 bit 32768 x 8 bit 80000H x F G J L M P S 00000H to 7FFFFH F7F00H to FFEFFH c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 9 of 12 RENESAS TECHNICAL UPDATE TN RL A005A E Date Apr 5 2013 6 Figure 24 3 Format of Option Byte 000C2H 010C2H Old New Figure 24 3 Format of Option Byte 000C2H 010C2H Figure 24 3 Format of Option Byte 000C2H 010C2H Address 000C2H 010C2H Address 000C2H 010C2H 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CMODE1 C5MODEO 1 0 FRQSEL3 FROSEL2 FRQSEL1 FRQSELO CMODE1 C5MODEO 1 0 FRQSEL3 FROSEL2 FRQSEL1 FRQSELO Setting of flash operation mode Setting of flash operation mode CMODE 1 CMODEO Operating Frequency Operating Voltage CMODE1 CMODEO Operating Frequency Operating Voltage Range Range Range Range o o LV low voltage main mode 1to 4 MHz 1 6 to 5 5 V o oo LV low voltage main mode 1to 4 MHz 1 6 to 5 5 V O0 1 9 LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V ow 0o LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V 1 to 16 MHz 2 4 to 5 5 V 1 to 16 MHz 2 4 to 5 5 V 1 1 HS high speed main mode 1 1 HS high speed main mode 1 to 32 MHz 2 7 to 5 5 V 1 to 32 MHz 2 7 to 5 5 V Other than above Setting prohibited Other than above Setting prohibited F f the high spe
61. 5 5 V Target pin internal reference 27V Vpp 55 V voltage and temperature 24VxVppx5 5V alala S la 9 sensor output voltage HS high speed main mode Zero scale error s 10 bit resolution D lt 5 5V Full scale error s 2 10 bit resolution D lt 5 5V Integral linearity error 10 bit resolution D lt 5 5V Differential linearity error 10 bit resolution D lt 5 5V Analog input voltage ANIO to ANI14 ANI16 to ANI26 Internal reference voltage output Veer Note 2 4 V lt VDD lt 5 5 V HS high speed main mode Temperature sensor output voltage Vrwesas Pete 3 2 4 V lt VDD lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 30 6 2 Temperature sensor internal reference voltage characteristics 7tENESAS m RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVrerm ANI1 ADREFM 1 target pin ANIO ANI2 to ANI14 ANI16 to ANI26 Ta 40 to 105 C 2 4 V lt EVppo EVpp lt Vpp lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Veser Reference voltage AVrerm 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 b
62. 5 V Vss EVsso EVssi 0 V 1 2 Parameter Conditions Supply lop Operating HS high fiu 32 MHz Basic Voo 5 0 V 2 3 mA current N mode speed main operation Z cu eet pe Voo 3 0 V 2 3 mA Normal Voo 5 0 V 5 2 9 2 mA operation Yop 3 0 V 52 92 mA fiu 24 MHz Normal Voo 5 0 V 4 1 7 0 mA operation Van 3 0 V 4 1 70 mA fiu 16 MHz Nomal Voo 5 0 V 3 0 5 0 mA operation Yop 3 0 V 30 50 mA HS high fmx 20 MHz Normal Square wave input 3 4 5 9 mA oen Voo 5 0 V operation Resonator connection 3 6 6 0 mA mode fmx 20 MHz Normal Square wave input 3 4 5 9 mA Vop 3 0 V operation Resonator connection 3 6 6 0 mA fux 10 MHz Normal Square wave input 2 1 3 5 mA Voo 5 0 V operation Resonator connection 2 1 3 5 mA fmx 10 MHz Normal Square wave input 2 1 3 5 mA Voo 3 0 V operation Resonator connection 2 1 3 5 mA Subsystem fsus 32 768 kHz Normal Square wave input 4 8 5 9 LA Note 4 clock f operation Resonator connection 4 9 6 0 uA operation Ta 40 C fsus 32 768 kHz Normal Square wave input 4 9 5 9 LA Note 4 operation Resonator connection 5 0 6 0 LA Ta 25 C fsus 32 768 kHz Normal Square wave input 5 0 7 6 LA Note 4 5 operation Resonator connection 5 1 7 7 uA Ta 50 C fsus 32 768 kHz Normal Square wave input 5 2 9 3
63. 56 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection On chip pll up resistance Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso In input port 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 20 to 64 pin products Ta 40 to 105 C 2 4 V lt EVppo x Vpp x 5 5 V Vss EVsso 0 V 1 2 Parameter Conditions Supply Operating HS high fiu 32 MHz Basic Voo 5 0 V current 1 Note mode speed main operation vo 3 0 V mode Note 5 Normal Voo 5 0 V operation Yop 3 0 V fin 24 MHz Nomal Voo 5 0 V operation Yop 3 0 V fiu 16 MHz Normal Voo 5 0 V operation Yop 3 0 V HS high fmx 20 MHz Normal Square wave input speed main yy 5 0 V operation mo d le Note 5 Resonator connection fmx 20 MHz Normal Square wave input Voo 3 0 V operation Resonator connection fmx 10 MHz Normal Square wave input Voo 5 0 V operation Resonator connection
64. 7 P120 P125 to P127 P130 P140 to P147 Per pin for P60 to P63 15 0 Note Total of POO to P04 P07 P32 to P37 4 0 V lt EVon0 lt 5 5V 40 0 P40 to P47 P102 to P106 P120 P425 5 7V lt Ev lt 40V 150 to P127 P130 P140 to P145 When duty lt 70 2 4 V EVppo lt 2 7 V 9 0 Total of P05 P06 P10 to P17 P30 4 0 V lt EVppo lt 5 5 V P31 P50 to P57 P60 to P67 27V zEVos A0 V P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 When duty lt 70 2 4 V EVppo lt 2 7 V Total of all pins When duty lt 70 Per pin for P20 to P27 P150 to P156 Total of all pins 24VxVopx5 5V When duty lt 709 3 Value of current at which the device operation is guaranteed even if the current flo ws from an output pin to the EVsso EVss and Vss pin Do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lot x 0 7 n x 0 01 Example Where n 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allo wed to flow into one pin does not vary depending on the duty factor A current higher than the absol
65. 750 6 fuck and 750 1 7 V lt EVppo lt 5 5 V 6 fuck and 1500 G fuck and 1500 G fwck and 1500 1 6 V lt EVppo lt 5 5 V G fuck and 1500 G fuck and 1500 SCKp high low level width Notes Caution and Remarks are listed on the next page 4 0VxEVpp x 5 5 V tkcv2 2 7 tkcv2 2 7 tkcy2 2 7 2 7 V lt EVooo lt 5 5 V tkcv2 2 8 tkcv2 2 8 tkcv2 2 8 1 8VxEVppox 5 5 V tkcv2 2 18 tkcv2 2 18 tkcv2 2 18 1 7 V lt EVppo lt 5 5 V tkcv2 2 66 tkcv2 2 66 tkcv2 2 66 1 6 V lt EVopo lt 5 5 V tkcv2 2 66 tkcy2 2 66 7tENESAS 33 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 4 During communication at same potential CSI mode slave mode SCKp external clock input 2 2 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main LS low speed main LV low voltage main Mode Mode Mode MIN MAX MIN MAX MIN MAX Slp setup time 2 7 V lt EVooo lt 5 5 V 1 fmck 20 1 fuck 30 1 fuck 30 to SCKpt 9 1 8V lt EVow lt 5 5 V 1 fucic30 1 Mick 30 4 fox 30 1 7 V EVppo x 5 5 V 1 fuck 40 1 fuck 40 1 fmck 40 1 6 V lt EVppo lt 5 5 V 1 fuck 40 1 fuck 40 Slp hold time 1 8 V lt EVppo lt 5 5 V 1 fuck 31 1 fuck 31 1 fuck
66. 8 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 6 2 Temperature sensor internal reference voltage characteristics Ta 40 to 85 C 2 4 V x Voo lt 5 5 V Vss 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient FvrwPs Temperature sensor that depends on the temperature Operation stabilization wait time tame 29 6 3 POR circuit characteristics Ta 40 to 85 C Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Minimum pulse width Note Minimum time required for a POR reset when Vb exceeds below Vror This is also the minimum time required for a POR reset from when Vm exceeds below 0 7 V to when Voo exceeds Vror while STOP mode is entered or the main system clock is stopped through setting bit 0 HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC TPw Supply voltage Vpp Vppr or 0 7 V 434 NE SAS 9n RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 85 C Vppn lt Voo lt 5 5 V Vss 0 V Parameter Conditions Detection Supply volta
67. A005A E Date Apr 5 2013 4 When the SSECm bit is 1 if a parity error framing error or overrun error occurs flags PEFmn FEFmn or OVFmn is not set nor an error interrupt INTSREq is generated To set the SSECm bit to 1 clear flags PEFmn FEFmn and OVFmn before setting the SWCO bit to 1 and read bits 7 to 0 RxDq in the SDRm1 register Table 12 3 UART Reception Baud Rate Setting in SNOOZE Mode UART reception baud rate in SNOOZE mode High speed on chip oscillator fiu 32 MHz 1 0 9 24 MHz 1 0 9 16 MHz 1 0 05 12 MHz x 1 0 9 feu 12 79 1 60 2 19 8 MHz 1 0 9 feu 2 105 2 27 1 53 6 MHz 1 0 9 79 4 MHz 1 0 05 3 MHz 1 0 9 feu 122 79 1 60 2 19 05 Baud rate 4800 bps Operating clock fuck fork 12 fa 127 fax 124 fer 2 for 12 SDRmn 15 9 105 79 1 1 Maximum acceptable value 2 27 1 60 2 27 1 60 2 27 Minimum acceptable value 1 53 2 18 1 53 2 19 1 53 2 MHz 1 0 fork 2 1 2 27 71 5494 1 MHz x 1 0 fou I2 105 2 27 1 57 Note When the high speed on chip oscillator clock accuracy is at 1 5 or 2 0 the acceptable range is limited as follows fiu 1 5 Subtract 0 5 from the maximum acceptable value of fin 1 0 and add 0 5 to the minimum acceptable value of fin 1 0 fiu 2 0 Subtract 1 0 from the maximum acceptable value of
68. AL SPECIFICATIONS G Ta 40 to 105 C 5 The smaller maximum transfer rate derived by using fwc 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 4 V x EVppo lt 3 3 V and 1 6 V lt Vo lt 2 0 V Maximum transfer rate bps C x Rex In 1 x3 Vb 1 1 5 Transferrate x 2 Cox Rex In 1 7 3 Baud rate error theoretical value M o M 100 95 Transfer rate d x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 6 This value as an example is calculated when the conditions described in the C onditions column are met Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpo tolerance When 64 to 100 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected UART mode connection diagram during communication at different potential Vb TxDq RL78 microcontroller User device RxDq 7tENESAS 32 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C UART mode bit width during communi
69. ATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at different potential Master SCKp User device RL78 Sip microcontroller SOp Remarks 1 Rb Q Communication line SCKp SOp pull up resistance Ce F Communication line SCKp SOp load capacitance Vo V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 49 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcvi tki tn SCKp Slp SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcvi SCKp SOp Output data Remarks 1 p CSI number p 7 00 01 10 20 30 31 m Unit number m 7 00 01 02
70. Analog input voltage ANI16 to ANI26 ANIO to ANI14 0 3 to EVppo 0 3 and 0 3 to AVner 4 0 3Netes 2 3 0 3 to Voo 0 3 and 0 3 to AVrer 4 0 3Netes 2 3 Notes 1 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it 2 Must be 6 5 V or lower 3 Do not exceed AVrer 0 3 V in case of A D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the p ort pins 2 AVner side reference voltage of the A D converter 3 Vss Reference voltage 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Absolute Maximum Ratings TA 25 C 2 2 Parameter Symbols Conditions Ratings Output current high POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of all pins POO to P04
71. C Ta 70 C Ta 85 C Notes and Remarks are listed on the next page 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 a fF WO ND 8 Total current flowing into Voo EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo 5 5 V 1 MHz to 16 MHz LS lo
72. CAL SPECIFICATIONS G Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt Voo x 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX Slp setup time 4 0 V lt EVpp lt 5 5 V 2 7 V lt Vo lt 4 0 V to SCKp4 N C 30 pF Re 4 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo x 2 7 V C 30 pF Ro 2 7 KQ 2 4 V lt EVooo lt 3 3 V 1 6 V lt Vs lt 2 0 V C 30 pF Ro 5 5 KQ Sip hold time 4 0 V lt EVo00 lt 5 5 V 2 7 V lt Ve lt 4 0 V from SCKpJ C 30 pF Rb 4 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo x 2 7 V 30 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Rb 5 5 KQ Delay time from SCKpT to 4 0V xEVppo 5 5 V 2 7 V lt Vo lt 4 0 V SOp output C 30 pF Re 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 KQ 2 4 V lt EVooo lt 3 3 V 1 6 V lt Vb lt 2 0 V 30 pF R 5 5 KQ Note When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mod
73. DAT Remarks 1 R O Communication line SDAr SCLr pull up resistance Ce F Communication line SDAr SCLr load capacitance Ve V Communication line voltage 2 r IIC number r 00 01 10 20 30 31 g PIM POM number g O 1 4 5 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 434 NE SAS 8e RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 5 2 Serial interface IICA 1 C standard mode Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MIN MAX MIN MAX SCLAO clock frequency Standard mode 2 7 V lt EVopo lt 5 5 V fake MHZ 18 V lt EV lt 5 5 V 1 7 V lt EVopo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Setup time of restart tsusr 27V amp EVpro 5 5 V condition 1 8 V lt EVopo lt 5 5 V 1 7 V lt EVooo lt 5 5 V 1 6 V lt EVopo 5 5 V Hold time te tupsrA 2 7 V lt EVbpo lt 5 5 V 1 8 V lt EVbpo 5 5 V 1 7 V x EVppo x 5 5 V 1 6 V x EVppo x 5 5 V Hold time when SCLAO 2 7 V lt EVppo 5 5 V Ls 1 8 V lt EVo00 lt 5 5 V 1 7 V lt EVppo x 5 5 V 1 6 V lt EVopo lt 5 5 V H
74. Date Apr 5 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document Category MPU MCU No TN RL AO005A E Rev 1 00 Correction for Incorrect Description Notice information Title RL78 G13 Descriptions in the Hardware User s Manual Cat Technical Notification Rev 2 10 Changed ategory Lot No Applicable RL78 G13 Reference Product R5F100xxx R5F101xxx All lots Document RL78 G13 User s Manual Hardware Rev 2 10 R01UHO0146EJ0210 Sep 2012 This document describes misstatements found in the RL78 G13 User s Manual Hardware Rev 2 10 RO1UH0146EJ0210 Corrections Applicable Item Contents Specifications extended Specifications changed Incorrect descriptions revised Incorrect descriptions revised Incorrect descriptions revised Specifications extended 29 3 2 Supply current characteristics Pages 998 to 1010 Incorrect descriptions revised 29 4 AC characteristics Page 1011 Specifications extended 29 3 1 Pin characteristics Pages 993 and 994 Incorrect descriptions revised 29 5 1 Serial array unit Pages 1014 to 1036 Specifications changed 29 5 2 Serial interface IICA Page 1037 Specifications changed 29 6 1 A D converter characteristics Pages 1038 to 1041 Specifications extended 29 6 2 Temperature Sensor Internal Reference Voltage Page 1042 Specifications changed Characteristics 29 6 3 POR circuit characterist
75. ECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcvi 2 tkui2 to2 SCKp tsik1 2 tksn 2 ale Slp tkso1 2 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcv1 2 SCKp tsiki 2 tksi1 2 gt a Slp Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 2 m Unit number n Channel number mn 00 to 03 10 to 13 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 4 During communication at same potential simplified Pc mode Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX SCLr clock frequency 2 7 V lt EVppo 5 5 V Co 50 pF Rb 2 7 KQ 2 4 V EVppo lt 5 5 V C 100 pF Rb 3 kQ Hold time when SCLr L 2 7 V EVppo 5 5 V 1200 Co 50 pF Rb 2 7 KQ 2 4 V EVppo lt 5 5 V 4600 C 100 pF Rb 3 kQ Hold time when SCLr H 2 7 V lt EVppo 5 5 V 1200 C 50 pF Rb 2 7 KQ 2 4 V EVppo 5 5 V 4600 Cb 100 pF Ro 3 KQ Data setup time reception tsu DAT 2 7 V lt EVppo 5 5 V 1 fuck 220 Note2 Co 50 pF Rb 2 7 KQ
76. EVppo lt 2 7 V MIN 125 ns Remark fwck Timer array unit operation clock frequency Operation clock to be set by the CKSmn0 CKSmn_1 bits of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 7 7tENESAS i RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Minimum Instruction Execution Time during Main System Clock Operation Tcv vs Voo HS high speed main mode 10 1 0 During self programming When high speed system clock is selected Cycle time Tcv us 0 1 0 0625 0 05 0 03125 0 01 30 40 505560 27 Supply voltage Voo V AC Timing Test Points Vin Vox Viu VoH o bn Test points lt AM External System Clock Timing 1 fex 1 fexs EXCLK EXCLKS When the high speed on chip oscillator clock is selected 13 NE SAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C TI TO Timing m tr je trip TIOO to TIO7 T110 to TI17 m 1 fro TOOO to TOO7 TO10 to TO17 Interrupt Request Input Timing INTPO to INTP11 Key Interrupt Input Timing mi tkr KRO to KR7 RSL RESET RESET Input Timing 7tENESAS 23 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 5 Peripheral Functions Characteristics AC Timing Test Points
77. ICAL SPECIFICATIONS A D Ta 40 to 85 C 10 Communication at different potential 1 8 V 2 5 V 3 V simplified Pc mode 1 2 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCLr clock frequency 4 0 V x EVppo 5 5 V 2 7 V V 4 0V Cb 50 pF Ro 2 7 KQ 2 7 V lt EVppo lt 4 0 V 2 3V x Vox 2 7 V C 50 pF Re 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 V x Vo 4 0 V C 100 pF Rb 2 8 kQ 2 7 V EVppo lt 4 0 V 2 3 V lt V lt 2 7 V C 100 pF Rb 2 7 kQ 1 8 V lt EVbpo lt 3 3 V 1 6 V lt Vb lt 2 0 Ve C 100 pF Ro 5 5 KQ Hold time when SCLr 4 0 V x EVppo lt 5 5 V ms 27V Vox 4 0 V C 50 pF Rb 2 7 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt V lt 2 7 V C 50 pF Rb 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 7 V lt V 4 0 V C 100 pF Rb 2 8 kQ 2 7 V lt EVppo lt 4 0 V 2 3V x Vox 2 7 V C 100 pF Rb 2 7 kQ 1 8 V x EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V ee C 100 pF Ro 5 5 KQ Hold time when SCLr 4 0 V EVppo lt 5 5 V H 27V Vs 40 V C 50 pF Rb 2 7 KQ 2 7 V lt EVppo lt 4 0 V 2 3V x Vox 2 7 V C 50 pF Re 2 7 KQ 4 0 V lt EVppo x 5 5 V 2 V x Vo 4 0 V C 100 pF Rb 2 8 kQ 2 7 V lt EVppo
78. IFICATIONS A D Ta 40 to 85 C Simplified lC mode mode connection diagram during communication at same potential Voo Rb SDAr SDA User device RL78 microcontroller SCLr SCL Simplified IC mode serial transfer timing during communication at same potential 1 fscL SCLr SDAr tHD DAT tsu DAT Remarks 1 R O Communication line SDAr pull up resistance Ce F Communication line SDAr SCLr load capacitance 2 r IIC number r 00 01 10 11 20 21 30 31 g PIM number g 0 1 4 5 8 14 h POM number g 0 1 4 5 7 to 9 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 7tENESAS 2 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions IHS high speed LS low speed LV low voltage main Mode main Mode main Mode Transfer rate 4 0 V lt EVppo lt 5 5 V fwck 6 fuck 6 Notes 1 2 3 Caution Remarks MIN MAX MIN MAX MIN MAX Note 1 Note 1 2 7 V lt Vb lt 4 0 V Theoretical value 5 3 1 3 of the maximum transfer rate Note 4 fuck
79. Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evopo lt Vpp 2 4 V EVppo lt 2 7 V MAX 2 6 Mbps 1 8 V lt EVppo lt 2 4 V MAX 1 3 Mbps 1 6 V lt EVppo lt 1 8 V MAX 0 6 Mbps 3 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 32 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V Vop lt 5 5 V LS low speed main mode 8 MHz 1 8 V x Voo 5 5 V LV low voltage main mode 4 MHz 1 6 V x Voo lt 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 2 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 7tENESAS 30 RL78 G13 CHAPTE
80. R 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 During communication at same potential CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX SCKp cycle time tkcy1 2 2 fc k 4 0 V lt EVop0 lt 5 5 V 62 5 250 500 2 7 V lt EVooo lt 5 5 V 83 3 250 500 SCKp high low level 4 0 V lt EVppo lt 5 5 V tkcvi 2 tkcy1 2 tkcv 2 width 7 50 50 2 7 V lt EVppo 5 5 V tkcy1 2 tkcvi 2 tkcy1 2 10 50 50 Sip setup time to SCKpf 4 0 V lt EVbpo lt 5 5 V 23 110 110 Note 1 2 7 V lt EVppo lt 5 5 V 33 110 110 Slp hold time from SCKp 2 7 V lt EVobo lt 5 5 V 10 10 Note 2 Delay time from SCKp to C 20 pr Note 3 SOp output Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPm
81. Remark tsuinit The segment shows that it is necessar y to finish specifying the initial communication settings within 100 ms from when the resets end tsu How long from when the TOOLO pin is placed at the low level until an external reset ends tup How long to keep the T OOLO pinatthe low level from when the extern al and internal res ets end excluding the processing time of the firmware to control the flash memory 7tENESAS TU RENESAS TECHNICAL UPDATE EXHIBIT To our valued customers MCYG AB 12 0385 1 RL78 G13 March 15 2013 Technical Update Exhibit Dia Uchimura Chapter 30 ELECTRICAL M CO Solution Business Unit PECIFICATION Ts Ms to io 3 MCU Business Division Brand Strategy Department Renesas Electronics Corporation Rep Seiya Indo Thank you for your continued support for Renesas Electronics products Please be advised that the misstatements found in the following Users Manual have been fixed The second and following pages in this document include Chapter 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C which has been updated by the Correction for incorrect description notice RL78 G13 Descriptions in the User s Manual Hardware Rev 2 10 changed TN RL AOO5A E 1 Applicable products RL78 G13 R5F100xxG 2 Reference documents Correction for incorrect description notice RL78 G13 Descriptions in the Users Manual Hardware Rev 2 10 changed TN RL AO05A E RL78 G13 Users Manual Hardware Rev 2
82. Renesas Electronics Corporation All rights reserved Page 2 of 12 stENESAS RENESAS TECHNICAL UPDATE TN RL A005A E Date Apr 5 2013 1 3 1 3 Internal Data Memory Space Incorrect Correct Cautions 2 While self programming is being executed or the data flash being rewriting do not allocate the RAM address which is used in stack data buffer the branch of vectored interrupt servicing or the transfer destination or source R5F100xA R5F101xA x 2610 8 Ato C EtoG FEE20H to FFEDFH R5F100xC R5F101xC x 6 to 8 A to C E to G J L FFE20H to FFEDFH by DMA in the address between FFE20H to FFEDFH R5F100xD R5F101xD x 6 to 8 Ato C Eto G JL FFE20H to FFEDFH FF300H to FF309H F 1 F F 3 The RAM area in the products listed below cannot be used when using R5F100xG R5F101xG x A to C to G J L M P FFE20H to FFEDFH the self programming function or rewriting the data flash because they are R5F100xH R5F101xH x E t9 G J L M P S FFE20H to FFEDFH used by libraries RT tti RSE TOLO EE Gal M P oree EEEa EEEREN EAEOI So ERAON R5F100xD R5F101xD x 6 to 8 A to C E to G J L FF300H to FF309H R5F100xK R5F101xK x E G J La M P S FFE20H to FFEDEH F 7 R5F100xE R5F101xE x 6 to 8 A to C E to G J L FEFOOH to FF309H R5F100xJ R5F101xJ x F G J L M P FAF00H to FB309H R5F100xL R5F101xL x F G J L M P S FZF00H to F8309H c 2013 Renesas Electronics Corporation All rig
83. SNOOZE mode UART reception baud rate must be set differently from normal operation Refer to Table 12 3 to set registers SPSm and SDRmn 15 9 e Set bits EOCmn and SSECmn to enable or disable the error interrupt INTSREO when a communication error occurs Set the SWCm bit in the serial standby control register m SSCm to 1 just before entering STOP mode After initialization set the SSm1 bit to 1 in the serial channel start register m SSm When the MCU detects the RxDq pin edge input input the start bit after entering STOP mode the UART reception is started Cautions 1 The SNOOZE mode can only be specified when the high speed on chip oscillator clock fiu is selected for fcuk 2 The transfer rate in SNOOZE mode is 4800 bps only 3 When the SWCm bit is 1 UARTq can be used only when the reception is started in STOP mode If UARTq is used with other SNOOZE function or interrupts concurrently and the reception is started in state other than STOP mode as described below the UARTq cannot receive data correctly and may cause a framing error or parity error The case the UARTq reception is started from the moment the SWCm bit is set to 1 before the MCU enters STOP mode The case the UARTq reception is started in SNOOZE mode The case the UARTq reception is started from the moment the MCU exits STOP mode and enters normal mode using interrupts before the SWCm bit is set to 0 Page 4 of 12 RENESAS TECHNICAL UPDATE TN RL
84. V Voo 3 0 V fiu 16 MHz Voo 5 0 V Voo 3 0 V LS low speed main mode Note 7 fiu 8 MHz Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 7 fiu 4 MHz Voo 3 0 V Voo 2 0 V HS high speed main mode Note 7 LS low speed main mode Note 7 fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connection fmx 20 MHZ 3 Voo 3 0 V Square wave input Resonator connection fmx 10 MHz e e3 Voo 5 0 V Square wave input Resonator connection fux 10 MHZ 3 Voo 3 0 V fux 8 MHZ Voo 3 0 V Square wave input Resonator connection Square wave input Resonator connection fux 8 MHz Voo 20V Square wave input Resonator connection Subsystem clock operation fsus 32 768 kHz Ta 40 C Square wave input Resonator connection fsus 32 768 kHz Ta 25 C Square wave input Resonator connection fsus 32 768 kHz e Ta 50 C Square wave input Resonator connection fsus 32 768 kHz Ta 70 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 85 C Square wave input Resonator connection STOP mode 8 Ta 40 C Ta 25 C Ta 50 C Ta 70 C Ta 85 C Notes and Remarks are listed on the next page
85. V lt Voo lt 5 5 V Note frequency fx crystal resonator 24V lt Vo lt 2 7V XT1 clock oscillation Crystal resonator frequency fx e Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer ofthe oscill ator circuit mou nted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator and XT1 oscillator refer to 5 4 System Clock Oscillator 30 2 2 On chip oscillator characteristics Ta 40 to 105 C 2 4 V x Voo x 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency s High speed on chip oscillator 20 to 85 C 2 4 VxVops5 5 V clock frequency accuracy 40 to 20 C 24 VeVopz5 5 V 85 to 105 C 2 4 VxVpbox5 5 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed
86. Vppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX Data setup time reception 4 0 V lt EVppo x 5 5 V 1 fuck 340 2 7 V Vo 4 0 V Noaz 50 pF Rb 2 7 KQ 2 7 V EVopo lt 4 0 V 1 fuck 340 2 3V lt Vo lt 2 7V ee Co 50 pF Rb 2 7 KQ 4 0 V EVopo lt 5 5 V 1 fuck 760 2 7 V Vo 4 0 V SURE C 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 1 fuck 760 2 3 V lt Vo lt 2 7 V note C 100 pF Rb 2 7 KQ 2 4 V EVppo lt 3 3 V 1 fuck 570 1 6V lt Vb lt 2 0V Note 2 Co 100 pF Rb 5 5 kQ Data hold time transmission tHD DAT 4 0 V lt EVppo 5 5 V 2 7 V lt Vo lt 4 0 V 50 pF Rb 2 7 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 50 pF Rb 2 7 KQ 4 0 V lt EVppo x 5 5 V 2 7 V xVe x 4 0V Co 100 pF Rb 2 8 kO 2 7 V lt EVppo lt 4 0 V 2 3V lt Vb lt 2 7V Co 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6V x Vo x 2 0 V Co 100 pF Rb 5 5 KQ Notes 1 The value must also be equal to or less than fwck 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the N ch open drain output Voo tolerance When 20 to 52 pin produ
87. al linearity error Add 0 5 LSB to the MAX value when AVnere Voo Refer to 30 6 2 Temperature sensor internal reference voltage characteristics 7tENESAS d RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 When reference voltage AVrere ANIO ADREFP1 0 ADREFPO 1 reference voltage AVnErw ANIT ADREFM 1 target pin ANI16 to ANI26 Ta 40 to 105 C 2 4 V lt EVppo EVpn1 lt Voo lt 5 5 V 2 4 V lt AVnere lt Voo lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Conditions Resolution Noret 10 bit resolution 2 4 V lt AVreFP lt 5 5 V EVppo lt AVnere Vpp 3 4 Overall error Conversion time 10 bit resolution 3 6 V lt Vpop lt 5 5 V Target pin ANI16 to 27V lt Vpp lt 5 5V ANI26 24VxVppx5 5V Zero scale error es t 10 bit resolution 2 4 V AVnere lt 5 5 V EVDpDo x AVnerP Voo Notes 3 4 Full scale error etes t 10 bit resolution 2 4 V lt AVnerp lt 5 5 V EVDpDo lt AVnerP Voo Notes 3 4 Integral linearity error 10 bit resolution 2 4 V lt AVnerP lt 5 5 V EVppo lt AVrerp Vpp Notes 3 4 Differential linearity error N 10 bit resolution 2 4 V lt AVrere lt 5 5 V EVppo lt AVrerp Vpp Notes 3 4 Analog input voltage ANI16 to ANI26 AVREFP and EVopo Notes 1 Excludes quantization
88. arameters Conditions High speed on chip oscillator clock frequency s High speed on chip oscillator 20 to 85 C 1 8 VxVppx5 5 V clock frequency accuracy 1 6 V lt Voo lt 1 8 V 40 to 20 C 1 8 VxVopx5 5 V 1 6 VxVop 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time 7tENESAS 5 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 3 DC Characteristics 29 3 1 Pin characteristics Ta 40 to 85 C 1 6 V x EVppo EVpp1 lt Voo x 5 5 V Vss EVsso EVssi 0 V 1 5 Output current Per pin for POO to P07 P10 to P17 1 6 V lt EVbppo lt 5 5 V high te Notes 1 Caution Remark Conditions P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of POO to P04 P07 P32 to P37 4 0V lt EVon lt 5 5V P40 to P47 P102 to P106 P120 27V lt EVo0 lt 40V P125 to P127 P130 P140 to P145 When duty lt 70 1 8 V lt EVppo lt 2 7 V 5 0 1 6 V x EVppo lt 1 8 V 2 5 Total of P05 P06
89. cate at different potential Use other CSI for communication at different potential 434 NE SAS m RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing slave mode during communication at different potential SCKp Slp SOp When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcv2 tkL2 tku2 Output data CSI mode serial transfer timing slave mode during communication at different potential SCKp Slp SOp When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcv2 tku2 tkL2 Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS i RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 8 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode 1 2 Ta 40 to 105 C 2 4 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX SCLr clock frequency 4 0 V lt EVopo lt 5 5 V 2 7 V Vo 4 0 V 50 pF Rb 2 7 KQ 2 7 V lt EVppo lt 4 0 V 400 e 2 3 V V
90. cation at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance I esp o LEE euet etel TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 Rb Q Communication line TxDq pull up resistance C F Communication line TxDq load capacitance Ve V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g O 1 8 14 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 134 NE SAS ae RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt Voo x 5 5 V Vss EVsso EVssi 0 V Parameter SCKp cycle time Conditions tkcy1 gt 4 ferk 4 0 V lt EVbppo 5 5 V 2 7 V lt Vo lt 4 0 V 30 pF Re 1 4 KQ HS high speed main Mode MIN MAX C 30 pF Rb 2 7 kQ 2 7 V lt EVooo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 5 5 kQ 2 4 V lt EVppo lt 3
91. cts EVpp tolerance When 64 to 100 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vi see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 7tENESAS a RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Simplified lC mode connection diagram during communication at different potential Vb Vb Rb Rb SDAr microcontroller PE User device SCLr SCL Simplified l C mode serial transfer timing during communication at different potential 1 fsc tLow THIGH SCLr SDAr tHD DAT tsu DAT Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpo tolerance When 64 to 100 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vi see the DC characteristics with TTL input buffer selected Remarks 1 R O Communication line SDAr SCLr pull up resistance Ce F Communication line SDAr SCLr load capacitance Ve V Communication line voltage 2 r IIC number r 00 01 10 20 30 31 g PIM POM number g 0 1 4 5 8 14 3 fuck Serial array unit operation
92. e 2 7 V lt EVppo lt 5 5 V 2 fuck 66 to SOp output 24V lt EVopo lt 5 5 V 2 fuck 113 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip hold time becomes from SCKpv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SOp output lines 5 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution Select the normal input buffer for the Slp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM number g 0 1 4 5 8 14 2 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of seri al mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 CSI mode connection diagram during communication at same potential SCKp SCK Slp SO User device microcontroller SOp Sl 7tENESAS 26 RL78 G13 CHAPTER 30 ELECTRICAL SP
93. e 4 Integral linearity error 10 bit resolution Note 3 AVnere Vop 1 8 V lt AVare lt 5 5 V 1 6 V lt AVrerp lt 5 5 V NO 4 Differential linearity error 1 10 bit resolution Note 3 AVnerP Voo 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVrerp lt 5 5 V NO 4 Analog input voltage ANI2 to ANI14 Internal reference voltage output 2 4 V lt VpD lt 5 5 V HS high speed main mode Note 5 Veer Temperature sensor output voltage 2 4 V lt VpD lt 5 5 V HS high speed main mode 7tENESAS Note 5 Vimps2s 61 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Excludes quantization error 1 2 LSB This value is indicated as a ratio FSR to the full scale value When AVrere Vm the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVnere Voo Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVnere Voo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Vo Values when the conversion time is set to 57 ws min and 95 ws max Refer to 29 6 2 Temperature sensor internal reference voltage characteristics 7tENESAS 2 RL78 G13 2 When reference voltage AVrere ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 CHAPTER 29 ELECTRICAL
94. e input pin is fixed to V pb EVppo and EVpp1 or Vss EVsso and EVss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped oo When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V x Voo lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V x Voo x 5 5 V 1 MHz to 4 MHz Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the TYP value is TA 25 C 7tENESAS 20 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to
95. e on chip debug function is used 2 With products not provided with an EVopo EVoo1 EVsso or EVss pin replace EVooo and EVpo with Voo or replace EVsso and EVss with Vss 3 The pins mounted depend on the product Refer to 2 1 Port Function to 2 2 1 With functions for each product 7tENESAS 2 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C 1 2 Parameter Supply voltage Symbols Vop Conditions Ratings 0 5 to 6 5 EVoppo EVpp1 EVopo EVpp1 0 5 to 6 5 EVsso EVss1 EVsso EVss1 0 5 to 0 3 REGC pin input voltage ViREGC REGC 0 3 to 2 8 and 0 3 to Voo 0 3 1 Input voltage Vu POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 0 3 to EVppo 0 3 and 0 3 to Von 0 3 P60 to P63 N ch open drain 0 3 to 6 5 P20 to P27 P121 to P124 P137 P150 to P156 EXCLK EXCLKS RESET 0 3 to Vpp 40 3Note Output voltage POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 0 3 to EVppo 0 3 and 0 3 to Voo 0 3 Ne P20 to P27 P150 to P156 0 3 to Vpp 40 3 ete
96. e register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 7tENESAS 36 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode connection diagram during communication at different potential Master microcontroller User device Remarks 1 R O Communication line SCKp SOp pull up resistance Ce F Communication line SCKp SOp load capacitance Vo V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 37 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcvi SCKp Slp SOp Output data CSI mode serial transfer timing master mode during communication at different potential Wh
97. e reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage Vivo11 Vroc1 Vroco 0 0 1 falling reset voltage Vivo10 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage Vroc1 Vroco 0 1 O falling reset voltage LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage Vpoc1 Vroco 0 1 1 falling reset voltage LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 Rising release reset voltage Falling interrupt voltage L L I S S S S SI S S S S SI c c cx xc cp cp cf cp cp xx 29 6 5 Power supply voltage rising slope characteristics Ta 40 to 85 C Vss 0 V Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 29 4 AC Charact
98. e set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions HS high speed main Mode MIN MAX Transfer rate Reception 4 0 V lt EVppo lt 5 5 V fiuck 12 Note 2 7 V lt Ve lt 4 0 V Theoretical value of the 2 6 maximum transfer rate faux 32 MHZ fuck fck 2 7 V lt EVppo lt 4 0 V fuck 12 Note 2 3V lt Vb lt 2 7V Theoretical value of the 2 6 maximum transfer rate fetk 32 MHz fuck fei 2 4 V EVppo lt 3 3 V fuck 12 Notes 1 2 1 6 V lt Veo lt 2 0 V Theoretical value of the 2 6 maximum transfer rate fcuk 32 MHz fuck fc K Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evppo lt Vpp 2 4 V x EVoppo lt 2 7 V MAX 1 3 Mbps Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Viu and Vi
99. ed on chi FRQSEL3 FRQSEL2 FRQSEL1 FRQSELO THERE o ace aun Other than above Setting prohibited Note Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H Caution Be sure to set bit 5 to 1 and bit 4 to O Other than above Note Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H Caution Be sure to set bit 5 to 1 and bit 4 to O c 2013 Renesas Electronics Corporation All rights reserved Page 10 of 12 RENESAS RENESAS TECHNICAL UPDATE TN RL A005A E T 29 3 1 Pin characteristics Incorrect Fixed typo in Note 3 in pages 993 and 994 8 29 3 2 Supply current characteristics Incorrect Fixed typo in Notes and typical values of IDD2 and IDD3 in pages 998 to 1010 9 29 4 Old Specifications of the external system clock frequency and external system clock input high level width low level width in page 1011 extended AC Characteristics 10 29 5 1 Serial array unit Incorrect Fixed typo in 29 5 1 Serial array unit in pages 1014 to 1036 11 29 5 2 Serial Interface IICA Incorrect Fixed typo in 29 5 2 Serial interface IICA in page 1037 12 29 6 1 A D converter characteristics Old Specifications of 29 6 1 A D converter characteristics in pages 1038 to 1041 extended 13 29 6 2 Temperature Sensor Internal Reference Characteristics Incorrect Fixed typo in 29 6 2 Temperature Sensor Internal R
100. eed AVrer 0 3 V in case of A D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the p ort pins 2 AVne side reference voltage of the A D converter 3 Vss Reference voltage 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Absolute Maximum Ratings TA 25 C 2 2 Parameter Output current high Symbols Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Ratings Total of all pins 170 mA POO to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin Total of all pins P20 to P27 P150 to P156 Output current low Per pin Total of all pins 170 mA POO to P07 P10 to P17 P30 to P37 P4
101. eference Voltage Characteristics in page 1042 Voltage 14 29 6 3 POR circuit characteristics Incorrect Fixed typo in 29 6 3 POR circuit characteristics in page 1042 c 2013 Renesas Electronics Corporation All rights reserved RENESAS Date Apr 5 2013 Correct Refer to pages 6 and 7 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 Correct Refer to pages 11 to 24 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 New Refer to page 25 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 Correct Refer to pages 29 to 56 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 Correct Refer to pages 57 to 60 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 New Refer to pages 61 to 65 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 Correct Refer to page 66 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C MCYG AB 12 0384 Correct Refer to page 66 in Technical Update Exhibit Chapter 29 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C MCYG AB 12 0384 Page
102. en DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcvi SCKp Slp SOp Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number m 00 01 02 10 12 13 n Channel number n 0 2 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 38 RL78 G13 7 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input TA 40 to 105 C 2 4 V lt EVDDO EVDD1 lt VDD lt 5 5 V VSS EVSSO EVSS1 0 V HS high speed main Mode Parameter Note 1 SCKp cycle time CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Conditions 4 0 V x EVppo x 5 5 V 24 MHz lt fuck MIN MAX 28 fuck 2 7V lt VWb lt 40V 20 MHz lt fuck 24 MHz 24 fuck 8 MHz lt fuck lt 20 MHz 20 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 fuck 2 7 V EVppo lt 4 0 V 24 MHz lt fuck 40 fuck 23V lt Vb lt 27V 20 MHz lt fick 24 MHz 32 fuck 16 MHz lt fuck lt 20 MHz 28 fuck 8 MHz lt fuck lt 16 MHz 24 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 fuck 24V lt EVppo lt 3 3 V 24 MHz lt fuck 96 fuck 16V lt VWb lt 20V 20 MHz lt fuck
103. ent of the RL78 microcontrollers is the sum of the v alues of either Ipp or Ipp2 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscillator is selected Iri should be added Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The supply current of the RL78 is the sum of Ipb1 Ipp2 or loos and Iwpr when the watchdog timer operates Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lanc when the A D converter is in operation 7tENESAS 13 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of pp1 Ipp2 or Ipp3 and lvo when the LVD circuit is in operation 8 Current flowing only during data flash rewrite 9 Current flowing only during self programming 10 For shift time to the SNOOZE mode see 18 3 3 SNOOZE mode Remarks 1 fit Low speed on chip oscillator clock frequency 2 fsu amp Subsystem clock frequency XT 1 clock oscillation frequency 3 fck CPU peripheral hardware clock frequency 4 Temperature condition of the TYP value is Ta 25 C 13 NE S AS 20 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 4 AC Characteristics TA 40 to 105 C 2 4 V lt EVppo EVpp1 lt
104. eristics 7tENESAS s RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Note The value depends on the P OR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected I l STOP mode Operation mode Data retention mode STOP instruction execution Standby release signal interrupt request 29 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions CPU peripheral hardware clock 1 8 V lt VoD lt 5 5 V frequency Number of code flash rewrites Retained for 20 years Ta 85 C Note Note 1 2 3 Number of data flash rewrites Retained for 1 years TA 25 C Notes 1 000 000 Note 1 2 3 Retained for 5 years TA 85 C 3 100 000 Retained for 20 years TA 85 C 3 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memor y and the results obtained from reliability testing by Renesas Electronics Corporation 29 9 Dedicated Flash Me
105. error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVnere Vov Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVrere Vpp Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Vo 4 When AVrerr lt EVpoo Voo the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVnere Vov Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVnere Vpp Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVnere Voo 7tENESAS ae RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to ANI26 internal reference voltage and temperature sensor output voltage Ta 40 to 105 C 2 4 V x EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Reference voltage VoD Reference voltage Vss Parameter Conditions Resolution Overall error 10 bit resolution 24V xVpDx5 5V Conversion time 10 bit resolution 3 6V lt Vpp lt 5 5V Target pin ANIO to ANI14 27V lt Vpp lt 5 5V ANI16 to ANI26 2 4 V lt VDD lt 5 5 V 10 bit resolution 3 6 V lt VoD lt
106. esolution 3 6 V lt Vp Target pin ANI2 to ANI14 27 y yp 2 4 V VDI 10 bit resolution 3 6 V lt Vb Target pin Internal 27V x VD reference voltage and temperature sensor output voltage HS high speed main mode 95 l la 9 2 4 V VD Zero scale error 55 1 2 10 bit resolution 2 4 V lt AVrere lt 5 5 V AVnerp Voo Pete Full scale errorNtes t 10 bit resolution 2 4 V lt AVrere lt 5 5 V AVnerp Vpp Pete Integral linearity error 10 bit resolution 2 4 V lt AVnere lt 5 5 V AVnere Vpp efe Noe 10 bit resolution 2 4 V lt AVnere lt 5 5 V Note 3 AVnerP Voo Differential linearity error Analog input voltage ANI2 to ANI14 Internal reference voltage output Veer Note 4 2 4 V lt VoD lt 5 5 V HS high speed main mode Temperature sensor output voltage Vrupsos Not 4 2 4 V lt VoD lt 5 5 V HS high speed main mode Notes are listed on the next page 7tENESAS aG RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 Excludes quantization error 1 2 LSB This value is indicated as a ratio FSR to the full scale value When AVrere lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVnere Vov Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVrere Vpp Integral linearity error Differenti
107. esonator connection fsus 32 768 kHz 5 Ta 50 C fsus 32 768 kHz 5 Ta 70 C Square wave input Resonator connection Square wave input Resonator connection fsus 32 768 kHz 5 Ta 85 C fsus 32 768 kHz Ta 105 C Square wave input Resonator connection Square wave input Resonator connection Ta 40 C Ta 25 C Ta 50 C Ta 70 C Ta 85 C Ta 105 C Notes and Remarks are listed on the next page 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 a Ff WO ND Total current flowing into Voo EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing
108. fiu 1 0 and add 1 0 to the minimum acceptable value of fiu 1 0 Remarks Maximum and minimum acceptable values in the above table are the baud rate acceptable values in UART reception Make sure to set the baud rate for transmission within this range c 2013 Renesas Electronics Corporation All rights reserved zu Page 5 of 12 sKENESAS RENESAS TECHNICAL UPDATE TN RL A005A E 3 18 3 2 STOP mode Incorrect Figure 18 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock omitted Notes 2 STOP mode release time i d whi V the oscillation stabilization time set by OST Wait When vectored interrupt servicing is carried out 10 to 11 clocks When vectored interrupt servicing is not carried out 4 to 5 clocks 2 When high speed system clock external clock input is used as CPU clock 3 When high speed on chip oscillator clock is used as CPU clock omitted Notes 2 STOP mode release time Wait When vectored interrupt servicing is carried out 7 clocks When vectored interrupt servicing is not carried out 1 clock c 2013 Renesas Electronics Corporation All rights reserved RENESAS Date Apr 5 2013 Correct Figure 18 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock omitted Notes 2 STOP mode release time Supply of the clock
109. g port input mode register g PIMg and port output mode register g POMg Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM and POM numbers g 0 1 4 5 8 14 2 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 7tENESAS 25 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 During communication at same potential CSI mode slave mode SCKp external clock input Ta 40 to 105 C 2 4 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Note 5 SCKp cycle time Conditions 4 0 V x EVppo lt 5 5 V 20 MHz fuck MIN 16 fuck MAX fuck lt 20 MHz 12 fwck 2 7 V lt EVooo lt 5 5 V 16 MHz lt fuck 16 fuck fuck lt 16 MHz 12 fuck 2 4 V lt EVopn0 lt 5 5 V 16 fuck 12 fuck and 1000 SCKp high low level width 4 0 V lt EVppox 5 5 V tkcv2 2 14 2 7 V lt EVppox 5 5 V tkcy2 2 16 2 4 V lt EVppox 5 5 V tkcy2 2 36 Slp setup time to SCKpf et 2 7 V lt EVppo lt 5 5 V 1 fuck 40 24VxEVppox 5 5 V 1 fuck 60 Slp hold time 24VxEVppox 5 5 V 1 fuck 62 from SCKp1 e Delay time from SCKp C 2 30 pF
110. ge level Power supply rise time voltage Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Vivp10 Power supply rise time Power supply fall time Vivo11 Power supply rise time Power supply fall time Vivo12 Power supply rise time Power supply fall time Power supply rise time Power supply fall time Minimum pulse width 5 i5i i I I Detection delay time 7tENESAS gu RL78 G13 LVD Detection Voltage of Interrupt amp Reset Mode CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C Vppn lt Voo lt 5 5 V Vss 0 V Parameter Interrupt and reset Vivo13 Conditions Vpoc2 Veoc1 Vroco 0 0 0 falling reset voltage mode Vivo12 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage Vivo11 LVIS1 LVISO 0 1 Rising releas
111. h rewrite 2 When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer e 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo x 5 5 V1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V x Voo x 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V x Voo x 5 5 V 1 MHz to 4 MHz Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the TYP value is TA 25 C 7tENESAS is RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 1 Flash ROM 16 to 64 KB of 20 to 64 pin products Ta 40 to 85 C 1 6 V x EVppo x Voo x 5 5 V Vss EVsso 0 V 2 2 Parameter Supply current Note 1 HS high Speed main mode Note 7 Conditions fiu 32 MHz 4 Voo 5 0 V Voo 3 0 V fiu 24 MHz 74 Voo 5 0
112. he valid maximum transfer rate Expression for calculating the transfer rate when 1 8 V lt EVppo lt 3 3 V and 1 6 V lt V lt 2 0 V Maximum transfer rate 1 15 bps Cox Re x In 1 7 x 3 1 1 5 Transfer rate x 2 Cox Rex In 177 7 1l Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 7 This value as an example is calculated when the conditions described in the C onditions column are met Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Viu and Vit see the DC characteristics with TTL input buffer selected UART mode connection diagram during communication at different potential RL78 microcontroller User device RxDq 7tENESAS m RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance Se UII ee Se ey
113. hen reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVrerm ANI1 ADREFM 1 target pin ANIO ANI2 to ANI14 ANI16 to ANI26 Ta 40 to 85 C 2 4 V lt Voo lt 5 5 V 1 6 V lt EVpp EVpp1 lt Vpp Vss EVsso EVssi 0 V Reference voltage Veer Reference voltage AVrerm 0 V HS high speed main mode Parameter Resolution CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions Conversion time 8 bit resolution 24VxVppx5 5V 39 Zero scale error es 8 bit resolution 24VxVppx5 5V 0 60 Note 1 Integral linearity error 8 bit resolution 2 4 V lt VoD lt 5 5 V 2 0 Differential linearity error N 8 bit resolution 24VxVppx5 5V 1 0 Analog input voltage Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 29 6 2 Temperature sensor internal reference voltage characteristics 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVRerm Integral linearity error Add 0 5 LSB to the MAX value when reference voltage AVrerm Note 3 Vecer Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVRerm 7tENESAS RL7
114. hts reserved Page 3 of 12 RENESAS RENESAS TECHNICAL UPDATE TN RL A005A E 2 12 6 3 SNOOZE mode function Incorrect SNOOZE mode makes UART operate reception by RxDq pin input detection while the STOP mode Normally UART stops communication in the STOP mode But using the SNOOZE mode makes reception UART operate unless the CPU operation by detecting RxDq pin input Only following channels can be set to the SNOOZE mode 24 to 64 pin products UARTO e 80 to 128 pin products UARTO and UART2 When using the SNOOZE mode function set the SWCm bit of serial standby control register m SSCm to 1 just before switching to the STOP mode Cautions 1 The SNOOZE mode can only be specified when the high speed on chip oscillator clock is selected for fctk h i ransf i A 9600 bps c 2013 Renesas Electronics Corporation All rights reserved RENESAS Date Apr 5 2013 Correct SNOOZE mode makes UART operate reception by RxDq pin input detection while the STOP mode Normally UART stops communication in the STOP mode But using the SNOOZE mode makes reception UART operate unless the CPU operation by detecting RxDq pin input Only following channels can be set to the SNOOZE mode 20 to 64 pin products UARTO 80 to 128 pin products UARTO and UART2 When using UARTq in SNOOZE mode execute the following settings before entering STOP mode Refer to Flowcharts of SNOOZE mode operation in Figure 12 93 and Figure 12 95 In
115. ics Page 1042 Specifications changed Supply Voltage Rise Time Page 1045 Specifications added 29 7 Data Memory STOP Mode Low Supply Voltage Page 1046 Specifications extended Data Retention Characteristics Chapter 30 ELECTRICAL SPECIFICATIONS m G TA 40 to 105 C TARGET Pages 1048 to 1098 Specifications fixed Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 12 aQENESAS RENESAS TECHNICAL UPDATE TN RL A005A E Date Apr 5 2013 Corrections in the User s Manual Hardware Corrections and Applicable Items for corrections 5 Figure 24 3 Format of Option Byte Page 934 Page 10 000C2H 010C2H 7 9 29 4AC characteristics Page1011 Page11 29 6 2 Temperature Sensor Internal Reference Voltage Characteristics Page 1042 Page 11 29 6 3 POR circuit characteristics Page 1042 Supply Voltage Rise Time Page 1045 Page 12 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 1046 Page 12 Chapter 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C TARGET Pages 1048 to 1098 Page 12 ine Correct Gray hatched Revision History RL78 G13 User s Manual Hardware Rev 2 10 Correction for Incorrect Description Notice Document Number TN RL A005A E Mar 15 2013 First edition issued No 1 to 17 in corrections This notice c 2013
116. input buffer 0 0 32 V 2 4 V lt EVppo lt 3 3 V Vis P20 to P27 P150 to P156 0 0 3Vpbp V Vita P60 to P63 0 0 3EVppo Vis P121 to P124 P137 EXCLK EXCLKS RESET 0 0 2Vpp Caution The maximum value of Vin of pins P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 is EVppo even in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 4 5 Conditions Output voltage POO to P07 P10 to P17 P30 to P37 4 0 V lt EVppo lt 5 5 V high P40 to P47 P50 to P57 P64 to P67 lou 3 0 mA P70 to P77 P80 to P87 P90 to P97 2 7 V lt EVopo lt 5 5 V P100 to P106 P110 to P117 P120 lout 2 0 mA P125 to P127 P130 P140 to P147 2 4 V EVppo lt 5 5 V lou 21 5 mA P20 to P27 P150 to P156 2 4 V lt Voo lt 5 5 V lou2 100 u A Output voltage POO to P07 P10 to P17 P30 to P37 4 0V lt EVppo lt 5 5 V low P40 to P47 P50 to P57 P64 to P67 lon 8 5 mA P70 to P77 P80 to P87 P90 to P97 ygy lt EVon 55 V P100 to P106 P110 to P117 P120 ib 230 mA P125 to P127 P130 P140 to P147 2 7 V EVppo 5 5 V lou 1 5 mA 2 4 V
117. is stopped 18 us to whichever is longer 65 us or the oscillation stabilization time set by OSTS Wait When vectored interrupt servicing is carried out 10 to 11 clocks When vectored interrupt servicing is not carried out 4 to 5 clocks Remark The time to stop clock supply varies depending on the temperature conditions and STOP mode time 2 When high speed system clock external clock input is used as CPU clock 3 When high speed on chip oscillator clock is used as CPU clock omitted Notes 2 STOP mode release time Supply of the clock is stopped 18 to 65 us Wait When vectored interrupt servicing is carried out 7 clocks When vectored interrupt servicing is not carried out 1 clock Remark The time to stop clock supply varies depending on the temperature conditions and STOP mode time Page 6 of 12 RENESAS TECHNICAL UPDATE TN RL A005A E 4 18 3 53 SNOOZE Mode Incorrect In SNOOZE mode transition wait status to be only following time When vectored interrupt servicing is carried out HS High speed main mode 6 79 to 12 4 us 7 clocks c 2013 Renesas Electronics Corporation All rights reserved RENESAS Date Apr 5 2013 Correct The MCU transits from STOP mode to SNOOZE mode or from SNOOZE mode to normal operation after time shown below elapses Transit time from STOP mode to SNOOZE mode 18 to 65 us Remark The transit time from STOP mode to SNOOZE mode varies depending on the tempera
118. istics Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions CPU peripheral hardware clock 2 4 V lt VoD lt 5 5 V frequency Number of code flash rewrites Retained for 20 years Note1 2 3 Ta 85 C oe Number of data flash rewrites Retained for 1 years TA 25 C Notes 1 000 000 Note1 2 3 Retained for 5 years Ta 85 C 3 400 000 Retained for 20 years TA 85 C Notes 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 7tENESAS 53 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 9 Dedicated Flash Memory Programmer Communication UART Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo x 5 5 V Vss EVsso EVssi 0 V ransfer rate urin asn memo rogrammin r S Transf During flash ry prog ing 115 200 1 000 000 bp 30 10 Timing Specs for Switching Flash Memory Programming Modes Ta 40 to 105 C 2 4 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions How long from when an external tsuinit POR and LVD reset must end before the reset ends until the initial e
119. it resolution 2 4 V lt VDD lt 5 5 V 39 Zero scale error e 8 bit resolution 24V x Vppx5 5V 0 60 Integral linearity error 8 bit resolution 24V lt VDD lt 5 5V 2 0 Differential linearity error N 8 bit resolution 2 4 V lt VDD lt 5 5 V 1 0 Analog input voltage Vacr Note 3 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 30 6 2 Temperature sensor internal reference voltage characteristics 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVRerm Integral linearity error Add 0 5 LSB to the MAX value when reference voltage AVrerm Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVRerm 7tENESAS 2d RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 6 2 Temperature sensor internal reference voltage characteristics Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient FvrwPs Temperature sensor that depends on the temperature Operation stabilization wait time tame
120. k fuck lt 4 MHz 10 fuck Notes and Caution are listed on the next page and Remarks are listed on the page after the next page 7tENESAS 2d RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt EVppo EVpn1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp high low level 4 0 V EVopo lt 5 5 V tkcy2 2 width 2 7V lt V lt 4 0V 12 2 7 V EVppo lt 4 0 V tkcy2 2 23VxVoex2 7V 18 1 8 V EVppo lt 3 3 V 1 6 V x Vo lt 2 0 VNC 50 Slp setup time 4 0 V x EVopo lt 5 5 V 1 fuck to SCKpf PP 27V Vs 40V 20 2 7 V EVppo lt 4 0 V 1 fmcK 2 3V lt Vo lt 2 7V 20 1 8 V EVppo lt 3 3 V 1 fiuck 1 6 V lt Vb lt 2 0 V Mte 30 Slp hold time 1 fmck from SCKp1 e e 31 Delay time from tkso2 4 0 V lt EVop0 lt 5 5 V 2 7 V lt Vo lt 4 0 V 2 fmck 2 fmck 2 fmck ns SCKp to SOp output Cb 30 pF Ro 1 4 KQ 120 573 573 Note 5 2 7 V lt EVppo lt 4 0 V 2 3 V x Vo lt 2 7 V 2lfmcK 2lfmck 2Z fwck ns C 30 pF Re 2 7 KQ 214 573 573 1 8 V EVppo lt 3 3 V 2 fck Zlfuck 2 fuck
121. lator is selected Iri should be added Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The supply current of the RL 78 microcontrollers is the su m of Ipp Ipp2 or Ipps and wot when the watchdog timer is in operation Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of lpp1 or Ipp2 and lanc when the A D converter operates in an operation mode or the HALT mode 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of pp1 Ipp2 or Ipp3 and lvo when the LVD circuit is in operation 8 Current flowing only during data flash rewrite 9 Current flowing only during self programming 10 For shift time to the SNOOZE mode see 18 3 3 SNOOZE mode Remarks 1 fit Low speed on chip oscillator clock frequency 2 fsu amp Subsystem clock frequency XT 1 clock oscillation frequency 3 fck CPU peripheral hardware clock frequency 4 Temperature condition of the TYP value is Ta 25 C 13 NE S AS RL78 G13 29 4 AC Characteristics TA 40 to 85 C 1 6 V lt EVppo EVppi lt Vpp lt 5 5 V Vss EVsso EVssi 0 V Instruction cycle minimum instruction execution time CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions Main system
122. lculating the transfer rate when 4 0 V x EVppo lt 5 5 V and 2 7 V lt Vo lt 4 0 V Maximum transfer rate EM bps Cox Rox In 1 a2 x3 1 Transfer rate x 2 1 _ Transfer rate Co x Rb x In 1 25 x 100 x Number of transferred bits Baud rate error theoretical value This value is the theoretical value of the relative difference between the transmission and reception sides 2 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer 3 The smaller maximum transfer rate derived by using fuck 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt EVpp0 lt 4 0 and 2 4 V lt V lt 2 7 V Maximum transfer rate bps Cox Rex In 1 ao x3 1 2 0 Transfer rate x 2 Cp Re x In 1 77 7 as HIE Transfer rate x 100 x Number of transferred bits Baud rate error theoretical value This value is the theoretical value of the relative difference between the transmission and reception sides 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 7tENESAS a RL78 G13 CHAPTER 30 ELECTRIC
123. mal Square wave input 2 1 3 2 mA Voo 3 0 V operation Resonator connection 2 1 32 mA LS low fmx 8 MHz Nomal Square wave input 1 2 2 0 mA eae Voo 3 0 V operation Resonator connection 1 2 2 0 mA mode fux 8 MHz Normal Square wave input 1 2 2 0 mA Voo 2 0 V operation Resonator connection 1 2 2 0 mA Subsystem fsus 32 768 kHz Normal Square wave input 4 8 5 9 LA Note 4 1 clock operation Resonator connection 4 9 6 0 u operation Ta 40 C fsus 32 768 kHz Normal Square wave input 4 9 5 9 LA Note 4 operation Resonator connection 5 0 6 0 LA Ta 25 C fsus 32 768 kHz Normal Square wave input 5 0 7 6 LA Note 4 tion opera Resonator connection 5 1 7 7 LA Ta 50 C fsus 32 768 kHz Normal Square wave input 5 2 9 3 LA mee operation pe Resonator connection 5 3 9 4 LA Ta 70 C fsus 32 768 kHz Normal Square wave input 5 7 13 3 LA Toe operation pe Resonator connection 5 8 13 4 uA Ta 85 C Notes and Remarks are listed on the next page 7tENESAS 15 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into Voo EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing in
124. mory Programmer Communication UART Ta 40 to 85 C 1 8 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V 7tENESAS 22 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 10 Timing Specs for Switching Flash Memory Programming Modes Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions How long from when an external tsuinit POR and LVD reset must end before the reset ends until the initial external reset ends communication settings are specified How long from when the TOOLO pin POR and LVD reset must end before the is placed at the low level until an external reset ends external reset ends How long the TOOLO pin must be POR and LVD reset must end before the kept at the low level after an external external reset ends reset ends excluding the processing time of the firmware to control the flash memory time OOH reception m gt TOOLRxD TOOLTxD mode TOOLO EEF 1 2 3 4 RESET i 723 us t i processing 7 tsu tsuiNiT Y it i 1 The low level is input to the TOOLO pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting
125. n fux 20 MHz e e3 Voo 3 0 V Square wave input Resonator connection fmx 10 MHz e e3 Voo 5 0 V Square wave input Resonator connection fux 10 MHz Voo 3 0 V fsus 32 768 kHz Ta 40 C Square wave input Resonator connection Square wave input Resonator connection fsus 32 768 kHz 5 Ta 25 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 50 C Square wave input Resonator connection fsus 32 768 kHz e Ta 70 C Square wave input Resonator connection fsus 32 768 kHz e Ta 85 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 105 C Square wave input Resonator connection Ta 40 C Ta 25 C Ta 50 C Ta 70 C Ta 85 C Ta 105 C Notes and Remarks are listed on the next page 7tENESAS RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 a FW ND Total current flowing into Voo and EVopo including the input leakage current flowing when the level of the input pin is fixed to V pp EVopo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flo wing into the A D converter LVD circuit I O port and on chi p pull up pull down resistors and the current flowing during data flash
126. n 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Sip pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 This value is valid only when CSIOO s peripheral I O redirect function is not used 2 p CSI number p 00 m Unit number m 0 n Channel number n 0 9 PIM and POM numbers g 1 3 fmck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 7tENESAS a RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Conditions LS low speed main Mode LV low voltage main Mode MIN MAX MIN MAX tkcy1 2 4 fcrk 2 7 V EVppo x 5 5 VI 500 2 4 V lt EVppo 5 5 V 500 1 8 V lt EVppo lt 5 5 V 500 1 7 V lt EVppo 5 5 V 1000 1 6 V lt EVooo lt 5 5 V 1000 SCK p cycle time SCKp high low level width 4 0 V lt EVbppo lt 5 5 V tkcy1 2 12 tkcy1 2 50 tkcy1 2 50 2 7 V lt EVpp0 lt 5 5 V tkcy1
127. nator connection fsus 32 768 kHz Ta 70 C Square wave input Resonator connection fsue 32 768 kHz e Ta 85 C Square wave input Resonator connection Ta 40 C Ta 25 C Ta 50 C Ta 70 C Ta 85 C Notes and Remarks are listed on the next page 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 a fF WO ND 8 Total current flowing into Voo EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to Vop EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval
128. o x 5 5 V1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the TYP value is TA 25 C 7tENESAS 16 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current Note 1 HS high speed main mode Note 7 Conditions fin 32 MHz Note4 Voo 5 0 V Voo 3 0 V fiu 24 MHz Voo 5 0 V Voo 3 0 V fin 16 MHz Vop 5 0 V Voo 3 0 V HS high speed main mode Note 7 fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 20 MHz 3 Voo 3 0 V Square wave input Resonator connection fux 10 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 10 MHz 3 Voo 3 0 V Square wave input Resonator connection Subsystem clock operation fsus 32 768 kHz 5 Ta 40 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 25 C Square wave input R
129. ock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 7tENESAS ae RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Conditions HS high LS low speed LV low speed main main Mode voltage main Mode Mode MIN MAX MIN MAX MIN MAX Parameter Transfer rate Transmission 4 0 V EVopo x 5 5 V Notes 1 2 7V lt Vb lt 4 0V Theoretical value of the maximum transfer rate Cp 50 pF Rb 1 4 KO Vb 2 7V 2 7 V lt EVppo lt 4 0 V 2 3 V lt V lt 2 7 V Theoretical value of the maximum transfer rate 50 pF Rb 2 7 KQ Vo 2 3 V 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Theoretical value of the maximum transfer rate 50 pF Rb 5 5 KO Vo 1 6 V The smaller maximum transfer rate derived by using fwck 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt EVppo x 5 5 V and 2 7 V lt Vb lt 4 0 V Maximum transfer rate Es bps Co x Rox In 1 44 x3
130. of Rb communication line pull up resistor at that time in each mode are as follows Standard mode C 400 pF Rb 2 7 kQ 7tENESAS ae RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 C fast mode Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MAX MIN MAX SCLAO clock frequency Fast mode 2 7 V EVopo lt 5 5 V fak2 3 5 MHZ rou Evo e55V Setup time of restart tsu sta 27V lt EVpp0 lt 5 5 V condition 1 8 V lt EVo00 lt 5 5 V Hold time tyosta 2 7 V lt EVppo lt 5 5 V 1 8 V lt EVo00 lt 5 5 V Hold time when SCLAO 2 7 V lt EVopo lt 5 5 V Li 1 8 V lt EVo00 lt 5 5 V Hold time when SCLAO 2 7 V lt EVopo lt 5 5 V H 1 8 V lt EVppo lt 5 5 V Data setup time tsupat 27V lt EVbppo 5 5 V reception 1 8 V lt EVopo lt 5 5 V Data hold time tuopar 2 7V lt EVppo lt 5 5 V transmission 1 8 V x EVppo x 5 5 V Setup time of stop tsusro 2 7 V lt EVooo lt 5 5 V condition 1 8 V lt EVo00 lt 5 5 V Bus free time 2 7 V lt EVooo lt 5 5 V aiala lala laia 9 8 la la 8 l la a 9 1 8 V x EVppo x 5 5 V Notes 1 The first clock pulse is generated after this period when the start res
131. old time when SCLAO 27V lt EVo0 lt 5 5 V H 4 8 V lt EVo00 lt 5 5 V 1 7 V x EVppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Data setup time tsupar 2 7 V lt EVon0 lt 5 5 V reception 1 8 V lt EVo00 lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Data hold time 2 7 V lt EVppo lt 5 5 V yer 2 transmission 1 8 V lt EVppo lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVppo x 5 5 V Setup time of stop 2 7 V lt EVppo lt 5 5 V condition 1 8 V lt EVbopo lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVbppo lt 5 5 V Bus free time 2 7 V lt EVopo lt 5 5 V 1 8 V lt EVbppo lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V 7tENESAS xi RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MA X oftub pAr is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics lou lot1 Voui VoL must satisfy the values in the redirect destination Remark The maximum value of Cb c ommunication line capacitance and the value
132. ommunication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 32 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcv2 tkL2 tku2 SCKp Slp SOp Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcv2 tku2 tkL2 SCKp SOp Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 7tENESAS 53 RL78 G13 CHAPTER 29 ELECTR
133. on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time 7tENESAS 5 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 3 DC Characteristics 30 3 1 Pin characteristics Ta 40 to 105 C 2 4 V x EVppo EVpp1 x Vpp lt 5 5 V Vss EVsso EVssi 0 V 1 5 Conditions Output current Per pin for POO to P07 P10 to P17 2 4 V lt EVop0 lt 5 5 V 3g Nee high te Notes 1 Caution Remark P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of POO to P04 P07 P32 to P37 4 0V lt EVon lt 5 5V P40 to P47 P102 to P106 P120 27V lt EVo0 lt 40V P125 to P127 P130 P140 to P145 When duty lt 70 Total of P05 P06 P10 to P17 P30 P31 4 0V lt EVon lt 5 5V P50 to P57 P64 to P67 P70 to P77 P80 05 7 y lt EVom lt 4 0V P87 P90 to P97 P100 P101 P110 to P117 P146 P147 When duty lt 70 Total of all pins 2 4 V lt EVon0 lt 5 5 V When duty lt 70 Per pin for P20 to P27 P150 to P156 2 4 V lt Voo lt 5 5 V 2 4 V x EVppo lt 2 7 V 2 4 V x EVppo lt 2 7 V Total of all pins 2 4 V lt Voo lt 5 5 V When duty lt 70 3
134. ose of the port pins 7tENESAS 7 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 2 Oscillator Characteristics 29 2 1 X1 XT1 oscillator characteristics Ta 40 to 85 C 1 6 V lt Von lt 5 5 V Vss 0 V Parameter Resonator Conditions X1 clock oscillation Ceramic resonator 2 7 V lt Voo lt 5 5 V frequency fx crystal resonator 24V Vpp 27 V 1 8 V x Voo lt 24 V 1 6 V lt Voo lt 1 8 V XT1 clock oscillation Crystal resonator frequency fx Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer ofthe oscill ator circuit mou nted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator and XT1 oscillator refer to 5 4 System Clock Oscillator 29 2 2 On chip oscillator characteristics Ta 40 to 85 C 1 6 V lt Voo lt 5 5 V Vssz OV Oscillators P
135. ote 1 HS high speed main mode Note 7 LS low speed main mode Note 7 Conditions fin 32 MHz Note4 Voo 5 0 V Voo 3 0 V fiu 24 MHz Voo 5 0 V Voo 3 0 V fin 16 MHz fiu 8 MHz Voo 5 0 V Voo 3 0 V Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 7 fin 4 MHz Voo 3 0 V Voo 2 0 V HS high speed main mode Note 7 fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 20 MHZ 3 Voo 3 0 V Square wave input Resonator connection fux 10 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 10 MHZ 3 Voo 3 0 V Square wave input Resonator connection LS low speed main mode Note 7 fux 8 MHz Voo 3 0 V Square wave input Resonator connection fux 8 MHz Vop 2 0 V Square wave input Resonator connection Subsystem clock operation fsus 32 768 kHz 5 Ta 40 C Square wave input Resonator connection fsus 32 768 kHz Ta 25 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 50 C Square wave input Resonator connection fsus 32 768 kHz Ta 70 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 85 C Square wave input Resonator connection Ta 40 C Ta 25 C Ta 50
136. pport for Renesas Electronics products Please be advised that the misstatements found in the following Users Manual have been fixed The second and following pages in this document include Chapter 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C which has been updated by the Correction for incorrect description notice RL78 G13 Descriptions in the User s Manual Hardware Rev 2 10 changed TN RL AOO05A E 1 Applicable products RL78 G13 R5F100xxA R5F101xxA R5F100xxD R5F101xxD 2 Reference documents Correction for incorrect description notice RL78 G13 Descriptions in the Users Manual Hardware Rev 2 10 changed TN RL AO05A E RL78 G13 Users Manual Hardware Rev 2 10 RO1UH0146EJ0210 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C This chapter describes the electrical specifications for the products A Consumer applications Ta 40 to 85 C and D Industrial applications Ta 40 to 85 C Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when th
137. rding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fii High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is TA 25 C 7tENESAS 1 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Supply current 1 Note Operating mode Conditions HS high fin 32 MHz Notes Voo 5 0 V speed main Voo 3 0 V mode Voo 5 0 V Voo 3 0 V fiu 24 MHz Voo 5 0 V Voo 3 0 V fin 16 MHz Von 5 0 V Voo 3 0 V LS low fiu 8 MHz Voo 3 0 V speed main Voo 2 0 V mode LV low fiu 4 MHz Voo 3 0 V voltage Voo 2 0 V main mode Note 5 HS high fmx 20 MHZ Square wave input ene Voo 5 0 V Resonator connection mode fux 20 MHZ Square wave input Voo 3 0 V Resonator connection fux 10 MHz Square wave input Voo 5 0 V Resonator connection fux 10 MHz Nor
138. stem clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the TYP value is Ta 25 C 7tENESAS is RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 1 Flash ROM 16 to 64 KB of 20 to 64 pin products Ta 40 to 105 C 2 4 V lt EVppo x Vpp x 5 5 V Vss EVsso 0 V 2 2 Parameter Supply current Note 1 HS high Speed main mode Note 7 Conditions fiu 32 MHz 4 Voo 5 0 V Voo 3 0 V fiu 24 MHz 74 Voo 5 0 V Voo 3 0 V fiu 16 MHz 74 Voo 5 0 V Voo 3 0 V HS high speed main mode Note 7 Subsystem clock operation fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connectio
139. t 5 5 V Setup time of stop tsusto 2 7 V lt EVbppo 5 5 V condition Bus free time teur 2 7 V lt EVooo lt 5 5 V Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MA X oftub pAr is during normal transfer and a wait stateis inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics lou lot1 Vou1 VoL must satisfy the values in the redirect destination Remark The maximum value of Cb c ommunication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode plus C 120 pF Rb 1 1 KQ IICA serial transfer timing SCLAn tHD STA SDAAn Restart Stop condition condition condition condition Remark n 90 1 7tENESAS 98 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 6 Analog Characteristics 29 6 1 A D converter characteristics Classification of A D converter characteristics Input channel ANIO to ANI 14 Reference voltage AVREFP Reference voltage AVREFM Refer to 29 6 1 1 Reference Voltage Reference voltage VDD Reference voltage Vss Refer to 29 6 1 3 ANI16 to ANI26 Refer to 29 6 1 2
140. t l lt lt lt lt lt lt Detection delay time LVD Detection Voltage of Interrupt amp Reset Mode Ta 40 to 105 C Vppr lt Voo x 5 5 V Vss 0 V Parameter Conditions Interrupt and reset VPoc2 Vroc1 Vroco 0 1 1 falling reset voltage mode LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 2 0 1 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 2 0 0 Rising release reset voltage Falling interrupt voltage 7tENESAS 52 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 6 5 Power supply voltage rising slope characteristics Ta 40 to 105 C Vss 0 V rene sm SiS i Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 30 4 AC Characteristics 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 105 C Vss 0 V Note The value depends on the P OR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected d STOP mode Operation mode Data retention mode A STOP instruction execution Standby release signal interrupt request 30 8 Flash Memory Programming Character
141. tart condition is detected 2 The maximum value MA X oftub pAr is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics lou lot1 Voui VoL must satisfy the values in the redirect destination Remark The maximum value of Cb c ommunication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode Cb 320 pF Rb 1 1 KQ 7tENESAS 29 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 IC fast mode plus Ta 40 to 85 C 1 6 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode LS low speed main Mode LV low voltage main Mode MIN MAX Fast mode plus 27 V lt EVppo lt 5 5 V fcuk gt 10 MHz SCLAO clock frequency fscL Setup time of restart tsu sta 27V lt EVooo lt 5 5 V condition Hold time tuo sta 2 7 V lt EVppo lt 5 5 V Hold time when SCLAO trow qo Hold time when SCLAO tHicH pp 2 7 V lt EVppo 5 5 V 2 7 V lt EVppo lt 5 5 V Data setup time tsupar 27V lt EVpp0 lt 5 5 V reception Data hold time transmission tuopar 2 7V lt EVppo l
142. ter laoc St When conversion at Normal mode AVnere Voo 5 0 V 1 3 1 7 mA A 6 operating current maximum Speed ow voltage mode AVrere Voo 3 0 V 0 5 0 7 mA A D converter lapngr NO 75 0 LA reference voltage current Temperature Irups Note t 75 0 LA sensor operating current LVD operating y Notes 1 7 0 08 uA current Self rsp Notes t 2 50 12 20 mA programming 3 operating current BGO operating lgco tes t 2 50 1220 mA current SNOOZE Isnoz ADC operation The mode is performed 0 50 1 10 mA operating current The A D conversion operations are 1 20 2 04 mA performed Loe voltage mode AVnere Voo 3 0V CSI UART operation 0 70 1 54 mA Notes 1 2 3 Current flowing to the Vobp When high speed on chip oscillator and high speed system clock are stopped Current flowing only to the r eal time clock RTC excluding the operating current of the lo w speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the v alues of either Ipp1 or Ipp2 and Inrc when the real time clock operates in operation mode or HALT mode When the low speed on chip oscillator is selected Fi should be a dded pp2 subsystem clock operation includes the operational current of the real time clock Current flowing only to the 12 bit interval timer excluding the op erating current of the lo w speed on chip ocsillator and the XT1 oscillator The supply curr
143. time reception tsu DaAT 2 7 V lt EVppo 5 5 V 1 fuck 1 fuck 1 fuck C 50pF R 27ko 85 145 145 Note2 Note2 1 8 V EVppo lt 5 5 V 1 fuck 1 fuck 1 fuck C 100 pF Rb 3 KQ 145 145 145 Note2 Note2 Note2 1 8 V lt EVppo lt 2 7 V 1 fuck 1 fuck 1 fuck Cb 100 pF Rb 5kQ 230 no eris Note2 Note2 Note2 1 7 V EVppo lt 1 8 V 1 fuck 1 fuck 1 fuck Cb 100 pF Rb 5kQ 290 Pes pies Note2 Note2 Note2 1 6 V x EVppo lt 1 8 V 1 fuck 1 fuck C 100 pF Rb 5 kO 290 290 Note2 Note2 Data hold time transmission 2 7 V EVppo 5 5 V 0 305 0 Cb 50 pF Ro 2 7 KQ 1 8 V EVppo 5 5 V 0 355 0 Co 100 pF Rb 3 KQ 1 8 V EVppo lt 2 7 V 0 405 0 Co 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V 0 405 0 Co 100 pF Rb 5 KQ 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ Notes 1 The value must also be equal to or less than fuck 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the normal input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page 7tENESAS 37 RL78 G13 CHAPTER 29 ELECTRICAL SPEC
144. timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V x Voo lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V x Voo x 5 5 V 1 MHz to 4 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fii High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is TA 25 C 7tENESAS 22 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 4 Peripheral Functions Common to all products TA 40 to 85 C 1 6 V lt EVppo EVppi lt Vpp lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions Low speed on chip oscillator operating current RTC operating IRTC current Notes 1 2 3 12 bit interval Topps ae timer operating current Watchdog timer lwor fi 15 kHz operating current 5 A D converter lapc 59 When Normal mode AVrerp Voo 5 0 V operating current conversion at Low voltage mode AVrerp Voo 3
145. tion line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 KQ Fast mode Cb 320 pF Rb 1 1 KQ IICA serial transfer timing SCLAn THD STA SDAAn Stop Start Restart Stop condition condition condition condition Remark n 0O 1 7tENESAS s RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 30 6 Analog Characteristics 30 6 1 A D converter characteristics Classification of A D converter characteristics Reference Voltage Reference voltage AVREFP Reference voltage VDD Reference voltage VBGR Input channel Reference voltage AVREFM Reference voltage Vss Reference voltage AVREFM ANIO to ANI 14 Refer to 30 6 1 1 Refer to 30 6 1 3 Refer to 30 6 1 3 ANI16 to ANI26 Refer to 30 6 1 2 Internal reference voltage Refer to 30 6 1 1 Temperature sensor output voltage 1 When reference voltage AVnErP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI2 to ANI14 internal reference voltage and temperature sensor output voltage Ta 40 to 105 C 2 4 V lt AVnerP lt Voo x 5 5 V Vss 0 V Reference voltage AVnere Reference voltage AVrerm 0 V Parameter Conditions Resolution Overall error 10 bit resolution 2 4 V lt AVnere lt 5 5 V Note 3 AVnerP Voo Conversion time 10 bit r
146. to 105 C Conditions 4 0 V lt EVpp0 lt 5 5 V 2 7 V lt Vo 4 0 V 30 pF Rb 1 4 KQ HS high speed main Mode MIN MAX 2 7 V lt EVooo lt 4 0 V 2 3 V lt Vo x 2 7 V 30 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Ro 5 5 KQ Slp hold time from SCKp1 N 4 0 V lt EVooo lt 5 5 V 2 7 V lt Vo lt 4 0 V 30 pF Rb 1 4 KQ 2 7 V lt EVooo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Rb 2 7 KQ Delay time from SCKp to SOp output 4 0 V lt EVpp0 lt 5 5 V 2 7 V lt Vo 4 0 V Co 30 pF Re 1 4 KQ 2 7 V lt EVppo 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 KQ 2 4 V lt EVooo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Ro 5 5 KQ Note When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page 134 NE SAS RL78 G13 CHAPTER 30 ELECTRI
147. to the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped 3 When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS 1 1 Ultra low power consumption oscillation However not including the current flowing into the 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 5 5 V 1 MHz to 32 MHz 2 4 V Voo lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V x Voo x 5 5 V1 MHz to 8 MHz LV low voltage main mode 1 6 V x Voo x 5 5 V 1 MHz to 4 MHz Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fin High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the TYP value is TA 25 C 7tENESAS 16 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current N
148. triH TIOO to TIO7 TI10 to TI17 I 1 fro TOO00 to TO07 TO10 to TO17 Interrupt Request Input Timing INTPO to INTP11 Key Interrupt Input Timing tkn KRO to KR7 mi RSL RESET 7tENESAS 28 RESET Input Timing RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 29 5 Peripheral Functions Characteristics AC Timing Test Points ViW VoH Vi VoH Test points Vi VoL i n dn Vi VoL 29 5 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 85 C 1 6 V lt EVppo EVppi lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Transfer rate 2 4 V lt EVopo lt 5 5 V fuck 6 fuck 6 fuck 6 bps Note 2 Note 2 Note 2 Theoretical value of the 5 3 13 0 6 Mbps maximum transfer rate fuck fork Note 1 8 V lt EVbppo 5 5 V fuck 6 fmck 6 fmck 6 bps Note 2 Theoretical value of the 5 3 1 3 0 6 Mbps maximum transfer rate fuck fork Notes 1 7 V lt EVbppo x 5 5 V fuck 6 fmck 6 fuck 6 bps Note 2 Note 2 Theoretical value of the 5 3 1 3 0 6 Mbps maximum transfer rate fuck fork Notes 1 6 V lt EVppo lt 5 5 V fuck 6 fuck 6 bps Note 2 Theoretical value of the 1 3 0 6 Mbps maximum transfer rate Note 3 fuck fcuk
149. ture conditions and STOP mode time Transit time from SNOOZE mode to normal operation When vectored interrupt servicing is carried out HS High speed main mode 4 99 to 9 44 us 7 clocks LS Low speed main mode 1 10 to 5 08 us 7 clocks LV Low voltage main mode 16 58 to 25 40 us 7 clocks When vectored interrupt servicing is not carried out HS High speed main mode 4 99 to 9 44 us 1 clock LS Low speed main mode 1 10 to 5 08 us 1 clock LV Low voltage main mode 16 58 to 25 40 us 1 clock Page 7 of 12 RENESAS TECHNICAL UPDATE TN RL A005A E Date Apr 5 2013 9 22 3 6 Invalid memory access detection function Incorrect Correct Figure 22 10 Invalid access detection area Figure 22 10 Invalid access detection area Possibility access r Accessibility Fetching instructions nstruction fetch Read Write execute Read Write execution FFFFFH FFFFFH Special function register SFR Special function register SFR 256 byte 256 bytes FFFOOH NG FFFOOH NG FFEFFH General purpose register FFEFFH General purpose register FFEEOH 32 byte K FFEEOH SANIES os FFEDFH FFEDFH Note Note RAM ok RAM OK yyyyyH 2z72z2zH Mirror OK Mirror OK NG NG NG NG Data flash memory Data flash memory F1000H F1000H FOFFFH FOFFFH Reserved eser
150. ut speed main yo 5 0 V operation mo d e Note 5 Resonator connection fmx 20 MHz Normal Square wave input Voo 3 0 V operation Resonator connection fmx 10 MHz Normal Square wave input Voo 5 0 V operation Resonator connection fmx 10 MHz Normal Square wave input Voo 3 0 V operation Resonator connection LS low fmx 8 MHz Nomal Square wave input speed main yo 3 0 V operation mode Note 5 Resonator connection fmx 8 MHz Nomal Square wave input Voo 2 0 V operation Resonator connection Subsystem fsus 32 768 kHz Normal Square wave input clock met operation operation Ta 40 C Resonator connection fsus 32 768 kHz Normal Square wave input eee operation Resonator connection Ta 25 C fsus 32 768 kHz Normal Square wave input Non operation Resonator connection Ta 50 C fsus 32 768 kHz Normal Square wave input Notes operation Resonator connection Ta 70 C fsus 32 768 kHz Normal Square wave input 3 operation Resonator connection Ta 85 C Notes and Remarks are listed on the next page 7tENESAS 13 RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into Voo EVopo and EVpp1 including the input leakage current flowing when the level of th
151. ute maximum rating must not flow into one pin Unless specified otherwise the characteristics of alternate function pins are the same as those of th e port pins 7tENESAS 4 RL78 G13 CHAPTER 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C TA 40 to 105 C 2 4 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 3 5 Conditions Input voltage Vini POO to P07 P10 to P17 P30 to P37 Normal input buffer 0 8EVppo EVopo V high P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vin2 P01 P03 P04 P10 P11 TTL input buffer 2 2 EVopo V P13 to P17 P43 P44 P53 to P55 4 0 V lt EVppo lt 5 5 V P80 P81 P142 P143 TTL input buffer 2 0 EVopo V 3 3 V lt EVppo lt 4 0 V TTL input buffer 1 5 EVppo V 2 4 V lt EVppo lt 3 3 V Vina P20 to P27 P150 to P156 0 7Vbb Voo V Vina P60 to P63 0 7EVppo 6 0 V Vins P121 to P124 P137 EXCLK EXCLKS RESET 0 8Vpp Voo V Input voltage low Vi POO to P07 P10 to P17 P30 to P37 Normal input buffer 0 0 2EVppo V P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vir2 P01 P03 P04 P10 P11 TTL input buffer 0 0 8 V P13 to P17 P43 P44 P53 to P55 4 0 V lt EVppo lt 5 5 V P80 P81 P142 P143 TTL input buffer 0 0 5 V 3 3 V EVppo 4 0 V TTL
152. ved F0800H OK F0800H OK FO7FFH FO7FFH OK OK Special function register 2nd SFR NG Special function register 2nd SFR NG 2 Kbyte 2 Kbytes F0000H F0000H EFFFFH EFFFFH EF000H OK EF000H OK EEEEEH mea PERERA ete hope A TERENE Reserved NG NG NG Reserved Me NG NG YAYAH eee FY XXXXXH XXXXXH OK OK Code flash memory Nee OK OK Code flash memory Note 00000H 00000H c 2013 Renesas Electronics Corporation All rights reserved Page 8 of 12 RENESAS RENESAS TECHNICAL UPDATE TN RL A005A E Note Code flash memory and RAM address of each product are as follows Date Apr 5 2013 Note Code flash memory area RAM area and the detected lowest address of each product are as follows Code flash memory RAM Products 00000H to xxxxxH yyyyyH to EFEEFH Detected lowest R5F100xA R3E101xA 16384 x 8 bit 2048 x 8 bit E TES RAM address for x 6to 8 Ato C Eto G FFE FE700H to FEEFFH Products 00000H to xxxxxH zzzzzH to FFEFFH read instruction R5F100xC R5F101xC 32168 x 8 bit 2048 x 8 bit fetch execution x 6to 8 Ato C E to G J L FEE FEZ00H to EFEEEH yyyyyH R5F100xD R5F101xD 49152 x 8 bit 3072 x 8 bit R5F100xA R5F101xA 16384 x 8 bit 2048 x 8 bit 10000H xz6to08 Ato C Eto G J L 00000H to OBFEFH EE300H to FFEFFH x 6 to 8 A to C E to G 00000H to 03FFFH FF700H to FFEFFH R5F100xE R5E101xE 65536 x 8 bit 4096 x 8 bit R5F100xC R5F101xC 32768 x 8 bit 2048 x 8 bit
153. w speed main mode 1 8 V x Voo lt 5 5 Vg1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo x 5 5 V 1 MHz to 4 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock fre quency X1 clock oscillation frequency or external main system clock frequency 2 fii High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is TA 25 C 7tENESAS us RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 128 pin products and flash ROM 384 to 512 KB of 44 to 100 pin products Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Vpp lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Conditions Supply Operating HS high fin 32 MHz Basic Voo 5 0 V current 1 Note mode speed main operation Von 3 0 V mode Normal Voo 5 0 V operation y 3 0 V fin 24 MHz Nomal Voo 5 0 V operation Van 3 0 V fin 16 MHzN 3 Normal Voo 5 0 V operation Yop 3 0 V LS low fin 8 MHz Nomal Von 3 0 V speed main operation Vow 2 0V mode Note 5 LV low fin 4 MHzN Nomal Von 3 0 V voltage main operation Voo 20 V mode Note 5 HS high fmx 20 MHz Normal Square wave inp
154. xcludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVaere Voo Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVaere Vo AVREFP and EVopo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Voo 4 When AVnere EVppo Voo the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVnere Vov Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVaere Voo Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVnere Voo 5 When the conversion time is set to 57 ws min and 95 ws max 7tENESAS RL78 G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to ANI26 internal reference voltage and temperature sensor output voltage Ta 40 to 85 C 1 6 V x EVppo EVpp1 x Voo lt 5 5 V Vss EVsso EVssi 0 V Reference voltage VoD Reference voltage Vss Parameter Conditions Resolution Overall error 10 bit resolution 1 8 V xVpp 5 5V 1 6 V lt Voo lt 5 5 V Note 3 Conversion time 1
155. xternal reset ends communication settings are specified How long from when the TOOLO pin POR and LVD reset must end before the is placed at the low level until an external reset ends external reset ends How long the TOOLO pin must be POR and LVD reset must end before the kept at the low level after an external external reset ends reset ends excluding the processing time of the firmware to control the flash memory A V RESET a a 4 BK m 723 us tub processing OOH reception time TOOLRxD TOOLTxD mode TOOLO A ff em tsuINIT mI Su LE V M E e V eds 1 The low level is input to the TOOLO pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsuinit The segment shows that it is necessar y to finish specifying the initial communication settings within 100 ms from when the resets end tsu How long from when the TOOLO pin is placed at the low level until an external reset ends tup How long to keep the T OOLO pinatthe low level from when the extern al and internal res ets end excluding the processing time of the firmware to control the flash memory 7tENESAS 9n

Correction for Incorrect Description Notice RL78/G13 Descriptions in

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