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DX1 User Manual - Blue Chip Technology

1. 51 ISA BUS SIGNAL DESCRIPTIONS eene I e 51 MESA LOCAL BUS nune iM COURIR See 56 IBI TH RITIENE 56 VL Bus Signal Definitions eese ener 56 BCT DX1 SBC I O ADDRESS MAP n 61 INTERRUPT ASSIGNMENTS enini ET 62 DMA ASSIGNMENT S e emn nennen sense nennt te enun ases es s se 62 APPENDIX ese 63 POST ERROR er reete e REP EUM NIE EE eee ER e RUE uA 63 APPENDIX B e 67 CONFIGURATION JUMPERS unan a na e ne enne eene sehen Ul Sabu 67 APPENDIX C u a sect eec ke veveesese 69 CONNECTOR DETAILS nee beca ct ese eiui a el 69 P1 FLOPPY 34 WAY HEADER esee eee eene 69 P2 HARD DRIVE 40 WAY HEADER n rnnt nnn 70 P3 COM 2 10 WAYHEADBR e 70 Blue Chip Technology Ltd 01270173 doc Contents P4 RS422 485 SERIAL 10 WAY HEADER 71 P5 PARALLEL 26 WAY HEADEFR a 71 FEATURE 26 WAY HEADER 72 P7 VIDEO 15 WAY CONDENSED D TYPE eren enne 72 8 POST 2 HEADER
2. Cache memory esteomplse EM EM m NM E0000H adapter ROM control completed 00 System configuration displayed Passing control to INT 19H bootstrap Loader now 9E 9F 1 A2 A3 A4 A5 A6 A7 A8 9 01270173 doc Blue Chip Technology Ltd Appendix APPENDIX B Configuration Jumpers Area of Influence J J J J J J J J Bypass Links for 5 volt and 3 3 volt CPU operation ALE signal to IDE hard disk drive IDE Ground Link Connects pin 34 of P2 to ground Serial port 1 RS485 termination Serial port 2 RS485 termination This link will be hard wired and is not to be altered without first consulting Blue Chip Technology This link will be hard wired and is not to be altered without first consulting Blue Chip Technology On board speaker Enable Power Save Switch 2 3 4 5 6 Printer Interrupt selection 12 On board Video Controller 13 Blue Chip Technology Ltd CPU speed selection A 4 by 2 row of pins exists on the PCB To select the required processor frequency fit the links as per the table WEB present L link absent Page 67 EF GH Remove ALL for 3 3 volt CPU None No ALE connected to IDE 1 2 interface ALE connected to IDE interface None Pin 34 floats 1 2 Pin 34 is grounded 1 2 100R amp 100nF across I P None No termination on board 1 2 100R amp 100nF across O P Not Allowed Not Allowed
3. 22 BIOS Hard Disk Type 47 RAM Area As described in the Set up details previously the AMIBIOS supports type 47 user definable input This data is stored at either 0 300h in lower system RAM or The top 1 of applications memory If the latter 1 selected the information will be stored in shadow RAM if shadowing is enabled Wait for lt F1 gt If any Error If any of the tests run during the POST cause an error then this message will be displayed If this message is enabled then after displaying it the DX 1 will halt waiting for F1 to be pressed If you expect errors during the POST or do not wish the boot to be halted if any error occurs then disable this option System Boot Up Num Lock If you wish the numeric keypad to be active after a boot then select ON If however you wish the lt and keys to be available after power up then set this option to OFF Numeric Processor Test This option enables or disables the AMIBIOS test for a maths co processor The settings are Enabled or Disabled Floppy Drive Seek at Boot If enabled a seek is performed on floppy drive A at system boot time The options are Enabled or Disabled By disabling this option the boot time can be reduced If very old 360KB drives are used it may be necessary to enable this option to ensure that the heads are recalibrated before any data is accessed 01270173 doc Blue Chip Technology Ltd BIOS Page 23 System Boot Up Sequence The de
4. 4554 47 48 91 AF 50 2 53 01270173 doc Blue Chip Technology Ltd Appendix 65 54 55 56 57 58 59 60 61 62 63 64 65 67 80 81 82 Command byte written and global initialisation complete 84 85 87 88 The power on screen message is displayed a gt The Wait message is displayed System and video BIOS shadowing successful Setup options are programmed Mouse test and initialisation done 0 Floppy Disk check identify that the drive needs initialising Memory size adjusted because of mouse support and hard disk type 47 Pre initialisation for expansion ROM operation completed Set timer data area and parallel printer base address 90 91 92 93 94 gt Set asynchronous base addresses a Initialisation for coprocessor test completed 54 55 56 57 58 5 60 62 63 765 65 66 67 80 80 8 34 8 86 87 58 59 8A 8C 9D 90 91 92 93 im 96 95 11 99 9A 9B 9 partially initialised Blue Chip Technology Ltd 01270173 doc 66 Appendix Coprocessor initialised Extended keyboard flags checked Keyboard ID command sue f Keyboard ID lag reset has teen done
5. Second Serial Port Mode 85232 Second Serial Port 485 FULL 9 Quik Disk Boot ROM Disabled SSD Boot ROM Disabled 9 CardTrick Boot ROM Disabled 9 BIOS Extensions Disabled SES PSPS PSPSPS SPSS SPSS PSPSPS PSPSPS SPSS SPSS ES PSPS PSPSPS BOPISIE BEEBE BEEBE ERE BEEBE SRE BRE ER RGR EGR E EO esc Exit lote sel Ctrl Pu Pd Modify Fl Help F2 F3 Color PRE BEEBE S F5 01d Values F6 BIOS Setup Defaults F7 Power On Defaults PRE BE BREOD Programming Option The options are Manual and Automatic During the POST the BIOS identifies all peripherals in the system If automatic mode is selected then the items shown in the previous screen plot will be mapped around those found by the POST This mode will override all the settings shown in the screen plot In manual mode you have control as to how the following functions are configured 01270173 doc Blue Chip Technology Ltd BIOS Page 35 On Board Floppy Drive This option enables the floppy controller on the DX1 This setting can either be Enabled or Disabled On Board IDE Drive This option enables the IDE controller on the DX1 This setting can either be Enabled or Disabled First Serial Port Address This option allows the first serial port address to be configured as either 03F8h Com1 03E8h Com3 or Disabled The interrupt selection will be made automatically to Coml and 3 will be Interru
6. 8 Data bit OCD 9 Daabit4 HD 10 Data bit HD P3 Com 2 10 way header Data Set Ready Ready To Send 6 Clear To Send Data Terminal Ready 8 Ringing Indicator o 0 Volts Ground 01270173 doc Blue Chip Technology Ltd Appendix 71 4 RS422 485 Serial 10 way header 5 Volts via 10KQ 5_ sve Transmic Data 6 ve Receive 7 ve Transmit Data 8 sve Transmit Data gt Lo vons via 10K P5 Parallel 26 way header Note This pinout is different from the normal 25 way D type itself 5 0000 7 8 Select input 9 Data bins 10 Volts Ground Blue Chip Technology Ltd 01270173 doc 72 Appendix P6 Feature 26 way header Pf Volts Ground 2 Pixel Datao 3 LO Volts Ground f o 4 Pixel Datat 5 Volts Ground 6 Pixel Data 7 Enable Video 8 Pixel Data3 9 EnabdeSyn 10 Pixel Dataa 20 P7 Video 15 way condensed D type 5 O Volts Ground 6 Volts Ground 7 O Volts Ground 8 Volts Ground Volts Ground p is Net Used P8 Post 12 way header PSP ATDatabitd PAT Data bitS AT Data bit 6 AT Data bit 7 POST decode 0 Volts Ground 1r sv L gt 01270173 doc Blue Chip Technology Ltd Appendix 73 P9 Mouse 6 pin mini DIN 0 Volts Ground 5 Volts fused Mouse Cloc
7. The BCT DX 1 provides two byte wide sockets that allow one Flash and one SRAM devices to be fitted on the main PCB These Solid State Disks can be used in a virtually identical manner as normal floppy disk drives The advantages of the SSD are that their environmental specifications are much superior to mechanical drives they occupy no extra space and they are much faster The two byte wide sockets are located at IC20 Flash and IC27 SRAM The Flash device can selected between 128KB 256KB 512KB 1 or 2MB 32 pin DIL component The SRAM device can be either 128KB or 512KB in size again with a 32 pin DIL profile Please see the preferred parts at the end of this Appendix for further details To enable either the Flash and or SRAM devices 1 From a Power up Reset or lt CTRL gt lt ALT gt lt DEL gt enter the BIOS Set up by pressing lt DEL gt when the Press DEL to enter Setup message is displayed 2 Enter the Standard CMOS Set Up and configure the floppy and hard drives as required For simplicity let us assume that all drives are Disabled 3 Escape back to the main menu and enter the DX 1 Peripheral Management Set up Set the Quik Disk Boot ROM option to Enabled Ensure that the SSD Boot ROM option is Disabled Ensure that the CardTrick Boot ROM option is disabled Set the BIOS Extensions to Enabled Escape back to the main menu and press lt F10 gt to save and Exit Une Programming Flash 1
8. AT AS A sp A10 All A12 A13 Al4 15 16 A17 18 A19 A20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 B29 0 Volts Ground Blue Chip Technology Ltd 01270173 doc 78 Appendix ISA Bus AT Connections C Large gold fingers under P16 main Component side D Large gold fingers under P16 on passive Component side C rao po mos lt ps Co MEMR ro DREQO C10 D10 C12 D12 C13 D13 C14 Di4 CI DIS C16 16 C D17 C18 01270173 doc Blue Chip Technology Ltd Appendix 79 VESA Local Bus Connector MCA style gold connector ata S s 9 vec o pas Blue Chip Technology Ltd 01270173 doc 80 Appendix 50 01270173 doc Blue Chip Technology Ltd APPENDIX D CMOS RAM Map Appendix D Page 81 A map of CMOS configured by the AMIBIOS for the Blue Chip Technology DX1 SBC is shown in the following table uan Description 00h OFh Standard IBM AT compatible RTC and Status Register data definitions Blue Chip Technology Ltd 0 No Drive 1 360 KB Drive 1 2 MB Drive 720 KB Drive 1 44 MB Drive 2 88 MB Drive Mouse Support Option Above 1 MB Memory Test Memory Test Tick Sound Memory Parity Error Check Hit DEL Message Display Hard Disk Type 47 RAM Area Wait for F1 if Any Error Floppy Drive Type Bits 7 4
9. 9406 sz wo 17 e 5 o Tt 6 J 6 4 6555 X 65 J 17 20 7 8 26e wm 8 73 5 X 6535 73 17 30 9 90 15 X 6535 X 90 17 112 Not Available 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 51 ISA BUS amp VESA LOCAL BUS DETAILS ISA Bus Signal Descriptions The following is a description of the ISA Bus signals All signal lines compatible AEN O Address Enable is used to degate the microprocessor and other devices from the T O channel to allow DMA transfers to take place When this line is active the controller has control of the address bus the data bus Read command lines memory and I O and the Write command lines memory and I O BALE O Buffered Address latch enable is provided by the bus controller and is used on the system board to latch valid addresses and memory decodes from the microprocessor It is available to the 1 0 channel as an indicator of a valid microprocessor or address when used with AEN Microprocessor addresses SAO through SA19 are latched with the falling edge of BALE BALE is forced high during DMA cycles CLK O This is the system clock The clock has a 50 duty cycle This signal should only be used for synchronisation It is not intended for uses requiring a fixed frequency DACKO through DACK3 and DACKS through DACK7 O DMA Acknowledge 0 thro
10. Create a bootable floppy disk containing the image that is to be programmed into the flash disk 2 Boot the system and ensure that the Quik Disk Boot ROM is enabled and that one of floppy disk drives is enabled as a 1 44MB drive Blue Chip Technology Ltd 01270173 doc 94 Appendix F 3 Bootthe system to DOS and at the DOS prompt run the PROGFLAS EXE utility provided on the DX 1 Flash Software diskette The syntax for running PROGFLAS is PROGFLAS lt DRIVE gt Where DRIVE specifies the floppy disk drive that contains the disk image Le or B 4 As PROGFLAS executes it will display the message Formatting flash disk and then Programming sector n of x Where is the current sector and x is the total number of sectors to be programmed 5 When programming is complete the floppy disk drive can be removed and when the system is rebooted it will boot off the flash disk Programming the SRAM The SRAM can be formatted using the MS DOS format utility and can then be accessed as a normal floppy disk drive using the standard DOS file handiling functions COPY etc 01270173 doc Blue Chip Technology Ltd 95 Daughter Board SSD The BCT DX 1 provides the facility for a Daughter Board SSD to be fitted to connectors P11 and P13 This Solid State Disk can be used in a virtually identical manner as normal floppy disk drives The advantages of the SSD are that their environm
11. Factory Hard Wired Not Allowed Factory Hard Wired Factory Hard Wired 2 3 None On board audio disabled 1 2 On board audio enabled P Donotuse No interrupt selected IRQ 7 selected LPT2 IRQ 5 selected Not Allowed Disabled Processor Frequency 20MHz 01270173 doc 68 Appendix B Selects either Internal or External Selects External Battery Battery supply Selects Internal Battery CMOS Memory clear Not Allowed Either selects to power CMOS or Battery Connected clears the CMOS and SRAM Clears CMOS and SRAM VESA local bus speed VESA LB operation lt 33MHz VESA LB operation gt 33MHz 01270173 doc Blue Chip Technology Ltd APPENDIX Connector Details Appendix G P1 Floppy 34 way header 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 0 Vol 1 3 5 7 11 13 15 17 19 21 23 25 27 29 31 33 Blue Chip Technology Signal Pin No s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground s Ground 2 2 2 2 2 Head Select Disk Change 2 4 10 12 14 16 18 0 2 4 6 8 30 32 34 01270173 doc Page 69 70 Appendix 2 Hard Drive 40 way header 5 Databito HD 6 Data bing HD 7 Data bitS HD
12. If the new password confirmation is entered without error the end user presses lt Esc gt to return to the Main Set up Menu Password Storage The password is stored in CMOS RAM after Set up completes The next time the systems boots you must enter the password if the password function is present and has been enabled Password Options Control Prompt Enter CURRENT Password appears if the Password Option is enabled When and if the prompt appears is dependent upon the options chosen in the Advanced CMOS Set up If Always was set the prompt appears every time the system is powered on If Set up was set the prompt will not appear when the system is powered on but is displayed when Set up is run Using a Password You should keep a record of the new password when the password is changed If you forget the password and password protection is enabled the only way to boot the system will be to disable the CMOS RAM This is achieved on the DX1 by setting J15 across pins 2 3 CLR for approximately 2 minutes Ensure that J15 is reset across position 1 2 NORM before powering on the system Note All CMOS RAM contents will be lost as a result of this action It is important that you keep a record of any changes you make to any of the Set up screens so that they will not be lost forever Auto Detect Hard Disk This option detects the hard disk parameters for non standard hard disk drives ESDI or IDE interfaces It displays the parameters that
13. 03A0 Bi synchronous 1 03B0 03DF Video Adapter 03E8 Serial Port 3 03F0 03F7 Floppy Diskette Controller 8 03FF Serial Port 1 Blue Chip Technology Ltd 01270173 doc 62 ISA amp VESA Bus Details Interrupt Assignments Device Occupied on DX1 default Interrupt NMI 7 10 11 12 13 14 15 Keyboard Output Buffer Full Cascaded from Interrupt 9 Parity Check generates IOCHCK on error Y Serial Port 2 also 4 6 amp 8 if sharing interrupts Serial Port 1 also 3 5 amp 7 if sharing interrupts Parallel Port 2 Floppy Diskette Controller Unassigned Assignments DMA Channel 0 01270173 doc 8 16 bit Device Peripherals 8 bit Used for Refresh Circuitry 8 bit Available 8 bit Diskette Drive 8 bit vailable 16 bit Cascaded to 1st DMA controller 16 bit Available 16 bit Available 16 bit Available Occupied on DX1 default Blue Chip Technology Ltd Appendix 63 APPENDIX POST Error Codes The BIOS performs a Power On Self Test after a reset or reboot During the POST the microprocessor indicates the state of the test by writing codes to the T O port address 80 hex The DX1 offers on board decode of this information and can drive the option POST display without modification The following codes indicate the progress of the microprocessor during the test Code Description Hex 01 Processor register test starting NM
14. 16 bit 1 wait state I O cycle It is derived from an address decode I O CS 16 is active low and should be driven with an open collector or tri state driver capable of sinking 20 mA IOR 10 Read instructs an I O device to drive its data onto the data bus It may be driven by the system microprocessor or DMA controller or by a microprocessor or DMA controller resident on the I O channel This signal is active low IOW 10 I O Write instructs an device to read the data on the data bus It may be driven by any microprocessor or DMA controller in the system This signal is active low IRQ3 to IRQ7 IRQ9 to IRQ12 and IRQIA to 15 D Interrupt Requests 3 through 7 9 through 12 and 14 through 15 are used to signal the microprocessor that an 1 0 device needs attention The interrupt requests are prioritised with IRQ9 through IRQ12 and IRQ14 through IRQI5 having the highest priority IRQO9 is the highest and IRQ3 through IRQ7 having the lowest priority IRQ7 is the lowest An interrupt request is generated when an IRQ line is raised from low to high The line must be held high until the microprocessor acknowledges the interrupt request Interrupt Service routine 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 53 LA17 through LA23 These signals unlatched are used to address memory and I O devices within the system They give the system up to 16MB of address ability These signals
15. 2 14 Accessing Set up i i eade tees e tede 14 Setup Key Uses xtA seme tee ei 15 Using the CMOS Set up Program sese esent eene 17 19 19 Floppy Disk Configuration eese uu au SS sS 19 Hard Disk Corifiguration iesms rii e dea e bett e eive reg het 19 qe tee He dee ee E e t ee ee 19 leet uci reete e ee UR busua e 19 Using the Advanced CMOS Set up es esee eene 20 Help Screens inii er tn Yee SV 21 Typematic Rate Programming Typematic Rate Delay and Typematic Rate 21 Above IMB Memory Test eese esee 21 Blue Chip Technology Ltd 01270173 doc Contents Memory Test Tick Sound upa naa aaa ash qa u as 21 Memory Parity Error Check nee 21 Hit DEL Message Display aaa asna 21 Hard Disk Type47 RAM 22 Wait for lt 1 gt Lf Error iecit ese e SURE tes 22 System Boot Up Num Lock esses esent 22 Numeric Processor isses tre e doter 22 Floppy Drive Seek at Boot esses esee ener eene 22 System Boot Up Sequences o sete ete icit te eee beue 23 External Cache Memory aa sunan anasu tenerent enne 23 Internal Cache Memory a aan E nennen nennen nnne 23 TurboSwich FWROHOn see redet eee eet 23 Fast Gate 20 Option ai
16. 2 Enabled Adaptor ROM Shadow CC00 16K 1 2 Enabled Adaptor ROM Shadow D000 16K 1 Enabled Adaptor ROM Shadow D400 16K 1 2 Enabled Adaptor ROM Shadow D800 16K 1 2 Enabled Adaptor ROM Shadow DC00 16K 1 Enabled Blue Chip Technology Ltd 01270173 doc 84 Appendix D Adaptor ROM Shadow E000 16K Adaptor ROM Shadow E400 16K Adaptor ROM Shadow E800 16K Adaptor ROM Shadow EC00 16K System BIOS Shadow F000 64K Video ROM Shadow C000 16K Video ROM Shadow C400 16K Numeric Processor Test IDE Block Mode Transfer 0 Disabled 1 Enabled Bits 6 5 CPU Internal Clock Mode 00 2X Bit 4 IDE Standby Mode 0 Disabled 1 Enabled Bits 3 0 Auto KeyLock Timeout 0000 Disabled 0 2 Min 0100 4 Min 0 6 Min 0 8 Min 0 10 Min 1011 0 12 Min 1101 1110 14 Min 1111 C 38h 3Dh Encrypted Password Extended CMOS Checksum High Byte includes 34h 3Dh Extended CMOS Checksum Low Byte includes 34h 3Dh amn 35h 36h 37h 3Eh 3Fh 40h 01270173 doc Blue Chip Technology Ltd Appendix D Page 85 Bit 7 6 Cache Read Option 01 3 2 2 2 1 2 1 1 1 Bits 5 4 Cache Write Option 01 2 W S 1 0 W S Bit 3 Refresh Cycle PageMode FastPage Bits 1 0 DRAM Wait State s 01 2 W S 1 0 W S on Cacheable Block 2 Enal 0 Disable Enabled on Cacheable Block 1 0 Disable Enabled Bit 6 CoProcessor Ready 0 Delay 11 o Delay Check ELBA Signa 0 in TI in T2
17. Caci Q gt C000 C3FF Shadow RAI 00 Disab 10 Cache C400 C7FF Shadow RAM 00 Disable 10 Cache C800 CBFF Shadow RAM 00 Disable 10 Cache CC00 CFFF Shadow RAM 00 Disable 10 Cache 01270173 doc Blue Chip Technology Ltd Appendix E Bits 7 6 D000 D3FF Shadow RAM 00 0 Bits 5 4 D400 D7FF Shadow RAM 00 0 Bits 3 2 D800 DBFF Shadow RAM 00 0 Bits 1 0 DC00 DFFF Shadow RAM 00 0 Bits 5 0 Refresh Divider 000000 000010 000100 000110 Disable Cache Disable Cache Disable Cache Disable Cache Bits 5 3 Keyboard Clock Select 000 010 100 111 Bits 2 0 AT Clock Select 000 010 100 111 Blue Chip Technology Ltd CPUCLK 6 CPUCLK 4 CPUCLK 2 7 2 MHz CPUCLK 6 CPUCLK 4 CPUCLK 2 CPUCLK 8 000001 000011 000101 CPUCLK 5 CPUCLK 3 9 5 MHz CPUCLK 5 CPUCLK 3 7 2 MHz Page 91 01270173 doc 92 Appendix E Bit 7 Data Location of Local Bus 0 ISA Bus PD Bus Bits 6 5 LOWA20 RC Emulation 00 None 0 Both Bit 4 Stretch 0WS Signal Option 0 Do Not ATCL Bits 3 0 IO Recovery Time of ISA PC 0000 0 0 1 1 BCLK 0010 2 2 BCL 3 3 BCLK 0100 5 3 7 3 BCLK 0110 9 3 12 3 BCLK 1100 5 5 BCL 7 7 BCLK 1110 9 9 BCL 12 12BCLK 01270173 doc Blue Chip Technology Ltd 93 APPENDIX F Solid State Disk Operation SSD Quick Disk SSD
18. Clock CMOS RAM and any installed SRAM on the DX1 or its Daughter Board when there is no power applied to the board Under normal conditions the battery should last for several years Great care should be taken with this battery under NO circumstances should the outputs be shorted be exposed to temperatures in excess of 100 C be burned be immersed in water be unsoldered be recharged be disassembled If the battery is mistreated in any way there will be a possibility of fire explosion and harm The DX1 makes provision for an external battery to be fitted at connector P14 This should have an output of 6 Volts capacity of 1 8AH and be fitted with a 10K series resistor for safety Please see the Appendix covering the Configuration Jumpers for further details Backplane The DX is capable of driving upto a 14 slot multilayer backplane with the appropriate termination Backplanes are available with three possible types of termination None Not recommended for backplanes with more than 2 3 slots Resistive Recommended for small backplanes 12 slots RC Preferred The actual values of termination depend upon the particular installation Please contact Blue Chip Technology for assistance 01270173 doc Blue Chip Technology Ltd DX1 Peripheral Components Page 47 Memory Map Typical Memory Map for a IMByte DX1 1 100000 BIOS Shadow BIOS F0000 EC000 E8000 E4000 E0000 DFFFF Available F
19. D400 D7FF Shadow Disabled 9 Refresh Cycle Slow D800 DBFF Shadow Disabled 9 CoProcessor Ready Delay 119 DCOO0 DFFF Shadow Disabled 9 Check Signal in 2 Refresh Divider AS Non Cacheable Block1 Enable Disabled Data Location of Local Bus PD Bus Non Cacheable Block 1 Size 4MB LOWA20 RC Emulation Both O9 Non Cacheable Block 1 Base Stretch OWS Signal Option Do Not lt Non Cacheable Block2 Enable Disabled Hardware Parity Check Enabled Non Cacheable Block 2 Base ISR ERE ERB ERE EE ERR ER ERR ERE REE REAR REBAR RRB SESS OKB 3 Esc Exit 5 1 Ctrl Pu Pd Modify Fl Help F2 F3 Color 2112121212 ppp Pp PRO 5 1 Values F6 BIOS Setup Defaults Blue Chip Technology Ltd Ld 1151515311 F7 Power On Defaults 01270173 doc 26 BIOS Auto Config Function The settings are Auto or Manual If this option is set to Enabled the following ADVANCED CHIPSET SET UP options are automatically configured to optimal settings by AMIBIOS based on the DX1 and CPU frequency Cache Read Option Cache Write Option DRAM Type DRAM Wait State s Keyboard Clock Select AT Clock Select and IO Recovery Time of ISA PCB Hold PD Bus Cache Read Option The settings are 3 2 2 2 3 1 1 1 or 2 1 1 1 Cache Write Option This option se
20. Department for assistance Blue Chip Technology Ltd 01270173 doc Page 2 Introduction Limitations of Liability In no event shall Blue Chip Technology be held liable for any loss expenses or damages of any kind whatsoever whether direct indirect Incidental or consequential arising from the design or use of this product or the support materials supplied with this product Trademarks IBM PC AT and PS 2 are trademarks of International Business Machines Corporation AMI Hi Flex BIOS is a trademark of American Megatrends Inc Intel is a registered trademark of Intel Corporation 80486SX 80486DX are registered trademarks of the Intel Corporation VESA VL Bus is a registered trademark of the Video Electronics Standards Association 01270173 doc Blue Chip Technology Ltd Specification Page 3 SPECIFICATION The BCT DX1 CPUs are single slot high performance computers that provide 100 IBM PC AT compatibility They offer the very highest level of integration currently available on an AT plug in card In addition they support on board VL Bus SVGA controller and will support up to two additional VL Bus expansion slot On board Features Choice of 25MHz 80486SX 33MHz 80486DX 66MHz 80486DX2 80486DX4 100 or P24T microprocessor Optional 256K Direct mapped one way set associative write back cache memory with software control via set up menu Up to 64MB of DRAM memory supports 1 x 36 4MB x 36 8MB x 36 and 16MB x 36 SIMM mod
21. a e ab eee e ee 23 Password Checking eese ener 24 ROM Shad OW ii 24 Boot Sector Virus Protection eese in eris 24 Using the Advanced Chipset csecsenc esee trennen 25 Using the DX 1 Extended Set up sss eerte 34 Programming Option e teo d RR mereri neg 34 On Board Floppy Drive iR SUD ee Redes 35 On Bo rd IDE Drive zoroan i d dear te er tees ARR IRIS ERATES 35 First Serial Port Address e enne ener 35 Second Serial Port Address 33 Parallel Port Addtress ga aa n eie Wa asthe cotta ee RE 35 Parallel Port Mode esee A eee X Ree HER 36 EX 36 First Serial Port s e t e ER 36 First Serial Port 465 Modes aus eene ea eu Re yn 36 Second Serial Port Mode o e e ae e ren 36 Second Serial Port 485 enne 36 Quick Disk Boot seen rennen nennen 36 SS D Boot ROM n i suiit d ERE RET REOR EH RE RIT dede 36 CardTrick Boot ee en eh eee d Ue ERR s 37 DONAR PE 37 Auto Configuration with Defaults esee 37 Change Passwords oder RIO er ERREUR PR RES 37 Bypassing Password Support esses esee nenne 37 Enabling Password Support ess trennen 37 Ifa Password is Used ieiunii eerte 37 P
22. atya diane 72 P9 MOUSE 6 PIN MINI DIN a 73 P10 SSD CONNECTOR 8 WAY HEADER enne 73 PIISCOM AT 9 WAY D 73 P12 PERIPHERAL 20 WAY HEADER es 73 P13 KEYBOARD 6 PINMINIDIN rennes 74 P14 BATTERY 4 WAY HEADER 74 P15 BACKPLANE UTILITY CONNECTOR 10 WAY HEADER 74 P16 AT EXPANSION CONNECTOR 75 P17 PC XT EXPANSION CONNECTOR 76 ISA BUS XT CONNECTIONS 77 ISA Bus AT CONNECTIONS ee eiecti 78 VESA LOCAL BUS CONNECTOR 79 MCA STYLE GOLD EDGE CONNECTOR 79 APPENDIX 81 CMOS RAM inca roe arcas tr u etse kayay 81 APPENDIX 89 CHIPSET REGISTER S ae e e em 89 iesietu oa roiie AA 93 SOLID STATE DISK OPERATION 80 s 93 Quick DISK dee 93 Programming the Flash esee 95 Programming the SRAM eene eerte eene 94 DAUGHTER BOARD SSD eie oic dete ide
23. be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of CO000h C3FFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory Blue Chip Technology Ltd 01270173 doc 30 BIOS C400 C7FF Shadow RAM This option specifies if the contents of the ROM memory area from C4000 C7FFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 contents of C4000h C7FFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory The contents of C4000h C7FFFFh are shadowed from ROM to RAM and can be written to or read from cache memory The contents of C400h C7FFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of C400h C7FFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory C800 CBFF Shadow RAM This option specifies if the contents of the ROM memory area from C8000 CBFFFh are shadowed to RAM and if these contents can be stored in cache memory Into 486 The contents of C8000h CBFFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory Cached The contents of C8000h CBFFFFh are shadowed from ROM to RAM and can be writt
24. cacheable It is always driven by the cache controller If LKEN is asserted one clock before LRDY and held until RDYRTN is asserted during the last read in a cache line the line is placed in the CPU cache Local Device This VL Bus target output signals the VL Bus that the current cycle is a VL Bus cycle The VL Bus controller samples the LDEV on the rising edge of LCLK one cycle after ADS If the System bus controller detects LDEV asserted the current does not start a system IO bus cycle For cache hit and DRAM cycles LDEV is ignored Blue Chip Technology Ltd 01270173 doc 60 ISA amp VESA Bus Details LRDY Local Ready LRDY begins the handshake that terminates the current active bus cycle The active LBT drives this LRDY only during the time of the cycle that it has claimed as its own While the VL Bus is inactive LRDY is pulled high by the DX1 Since the VL Bus is normally a not ready bus the CPU must wait until LRDY is asserted low to terminate an active VL Bus cycle LBS16 Local Bus Size 16 LBS 16 forces the CPU or VL Bus master to run multiple 16 bit transfers to a VL Bus target that cannot accept 32 bit data transfers in a single clock cycle It is a shared signal driven only by the active VL Bus target While the VL Bus is inactive this signal is pulled high BRDY Burst Ready BRDY terminates the current active burst cycle BRDY is syncronised to LCLK and is asserted low one LC
25. electronics by the operating system thereby acting as an extension to the System BIOS for the new electronics 01270173 doc Blue Chip Technology Ltd BIOS Page 11 AMI Hi Flex System BIOS Features Keyboard Speed Switching Enable Cache Memory Memory Detection Password Support Auto detection of IDE Hard Drive Parameters Auto detection of Processor Type and Speed Auto detection of Memory Size and Type Customisation of the System User definable Hard Disk Types PS 2 Mouse Support Boot Sector Virus Support Local Peripheral Support Shadow RAM Support Keyboard Typematic Rate and Delay Num Lock Power on Status Fast Gate A20 Support Hot Keys The Hi Flex AMIBIOS provides hot keys to switch speed and cache operation These key operations are lt Ctrl gt lt Alt gt and lt gt Selects High Speed lt Ctrl gt lt Alt gt and lt gt Selects Low Speed lt Ctrl gt lt Alt gt lt Shift gt and lt gt Enables External Cache lt Ctrl gt lt Alt gt lt Shift gt and lt gt Disables External Cache lt Ctrl gt lt Alt gt and lt DEL gt Causes a Soft Reset All keys should be pressed together Blue Chip Technology Ltd 01270173 doc 12 BIOS AMIBIOS Power on Self Test The Hi Flex AMIBIOS provides all IBM standard POST routines as well as enhanced AMIBIOS routines All POST checkpoint codes are written to the POST display at location 80 hex if fitted See the POST error codes Appendix A POS
26. gated on the system bus when BALE is high and are latched on the falling edge of BALE These signals are generated by the microprocessor or DMA Controller They also may be driven by other microprocessors or DMA controllers that reside on the I O channel SBHE 10 Bus High Enable system indicates a transfer of data on the upper byte of the data bus SD8 through SD15 16 bit devices use SBHE to condition data bus buffers tied to SD8 through SD15 SD0 through SD15 I O These signals provide data bus bits 0 through 15 for the microprocessor memory and I O devices DO is the least significant bit and D15 is the most significant bit All 8 bit devices on the I O channel should use DO through D7 for communications to the microprocessor The 16 bit devices will use DO through D15 To support 8 bit devices the data on D8 through D15 will be gated to DO through D7 during 8 bit transfers to these devices 16 bit microprocessor transfers to 8 bit devices will be converted to two 8 bit transfers 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 55 SMEMR O MEMR I O These signals instruct the memory devices to drive data onto the data bus SMEMR is active only when the memory decode is within the low IMB of memory space MEMR is active on all memory read cycles MEMR may be driven by any microprocessor or DMA controller in the system SMEMR is derived from MEMR and the decode of the
27. it detects and allow the you to accept or reject the parameters If accepted these parameters are displayed for the hard disk drive in Standard CMOS Set up 01270173 doc Blue Chip Technology Ltd BIOS Page 39 Note that when an Auto Detect is run on a drive which is not present drive D in most systems then there will be a delay before the test is completed Pressing the ESC key will override this delay Write to CMOS and Exit The configuration settings in Standard Set up Advanced CMOS Set up Advanced Chipset Set up Peripheral Set up Password and Auto Detect Hard Disk are stored in the CMOS RAM when this option is selected A CMOS RAM checksum is calculated and written to CMOS RAM control is then passed to the BIOS You are asked to confirm or deny the action by entering either lt Y gt or lt N gt Press lt Y gt and lt Enter gt to save the new system parameters and continue the boot process Press lt N gt and lt Enter gt to return to the Main Menu Do Not Write to CMOS and Exit This option passes control to the ROM BIOS without writing any changes to the CMOS RAM Press lt Y gt and lt Enter gt to continue the boot process without saving any system parameters changed in Set up Press lt N gt and lt Enter gt to return to the Main Menu Blue Chip Technology Ltd 01270173 doc 40 DX1 Peripheral Components DX1 PERIPHERAL COMPONENTS Video The DX1 Single Board Computer has an on board VESA Local Bu
28. mode can be supported by your monitor paying particular attention to interlaced and non interlaced modes 01270173 doc Blue Chip Technology Ltd DX1 Components IBM Standard Video Modes Mode VESA No No 45 7 Dp Colours 16 256K 16 256K 4 256K 2 256K Mono 16 256K 16 256K Mono 16 256K 2 256K 16 256K 256 256K Char v Row Char Cell Cirrus Logic Extended Video Modes 5C 5C 2 1 109 102 102 102 103 103 5c 103 5D 5D 0A 109 102 102 102 103 103 103 104 104 104 104 100 x37 100 x 37 100 x 37 100 x 37 Mode Screen Format Page 41 Display i 56 70 16256K 128x48 8x16 1024x768 Graphics 56 70 104 16256K 128x48 8x16 1024x768 Graphics 58 72 Blue Chip Technology Ltd 01270173 doc 42 DX1 Peripheral Components e J 640 480 Graphics 315 60 640 480 Graphics 379 72 800 600 Graphics 352 56 e 800 600 Graphis 378 60 66 3 j j 640x480 Graphics 315 60 6 10 640 480 Graphs 379 72 567 13 32xK 800 600 Graphics 315 56 ope 256 256K 160x48 8x16 1280x1024 Graphics 48 87 1 2 16M 80x30 8x16 640x480 Graphics 315 60 re nemen pee 95 de
29. the CMOS RAM becomes corrupted the system is re configured with the default values stored in the System BIOS There are two sets of BIOS values stored in the BIOS the BIOS default values and the Power On default values The Power on default settings consist of the safest set of parameters These settings should be used if the system is behaving erratically They should work in the majority of cases but do not provide optional system performance characteristics Accessing Set up Set up is accessed by pressing the DEL key on the keyboard when the screen displays the message Hit lt DEL gt if you want to run Set up If you press DEL too late reset the DX1 and try again 01270173 doc Blue Chip Technology Ltd BIOS Page 15 Set up Key Use Keystroke Returns to the previous screen Move the cursor from one option to the next lt PgUp gt and Modify the default value of the options for the highlighted parameter lt PgDn gt If there are fewer than 10 options lt Ctrl gt lt PgUp gt and lt Ctrl gt lt PgDn gt lt Ctrl gt lt PgUp gt operate like lt PgUp gt and lt PgDn gt lt Ctrl gt lt PgDn gt _ Ctrl can also be used to increment a setting Fl Displays help Changes background colours Changes foreground colours F5 Restores the values resident when the current Set up session began These values are taken from the CMOS RAM if it was uncorrupted at the start of the session Otherwise the AMIBIOS S
30. type of drive connected without requiring reference to drive manuals Hard Disk Types Hard disk drive types are identified by the following parameters Parameter Description A designation for a hard disk drive with predefined parameters Cylinders The number of cylinders in the disk drive The number of heads Write The size of a sector gets progressively smaller as the track diameter Precom diminishes Yet each sector must still hold 512 bytes Write pensation precompensation circuitry difference in sector size by boosting the write current for sectors on inner tracks This parameter is the track number where write precompensation begins Landing The number is the cylinder location where the heads normally park Zone when the system is shut down Sectors The number of sectors per track Hard drives that use MFM have 17 sectors per track RLL drives have 26 sectors per track RLL and ESDI drives have 34 sectors per track SCSI and IDE drives may have even more sectors per track Capacity The formatted capacity of the drive based on the following formula Number of heads Number of cylinders Number of sectors per cylinder 512 bytes per sector A table of the 46 standard hard disk types is shown on the following page Blue Chip Technology Ltd 01270173 doc 50 DX1 Peripheral Components S eid acan eano Cylinders Heads compensation Zone Sectors 3 J es 6 3 6 J 1v7 83 4
31. 565 65 965 25 269 65 5265 65 965 25 09 65 05 269 65 9S 65 9 6 25 9 or Typematic Rate Programming Enabled BootSector Virus Protection Disabled Typematic Rate Delay msec 500 CPU Internal Clock Mode 1X Typematic Rate Chars Sec 30 IDE Block Mode Transfer Disabled Above 1 MB Memory Test Disabled IDE Standby mode Disabled 9 Memory Test Tick Sound Enabled Auto Key Lock Timeout Disabled Memory Parity Error Check Enabled e Hit DEL Message Display Enabled o Hard Disk Type 47 RAM Area 0 300 e Wait For Fl If Any Error Enabled e System Boot Up Num Lock On 9 Numeric Processor Test Enabled Weitek Processor Absent Floppy Drive Seek At Boot Enabled e 9 System Boot Up Sequence C2 0D 9 System Boot Up CPU Speed High External Cache Memory Enabled Internal Cache Memory Enabled Password Checking Option Setup Esc Exit lt Sel Ctrl Pu Pd Modify Fl Help F2 F3 Color epey o pp pO 5 1 Values F6 BIOS Setup Defaults F7 Power On Defaults 01270173 doc Blue Chip Technology Ltd BIOS Page 21 Help Screens Help can be invoked at any time by pressing lt F1 gt Typematic Rate Programming Typematic Rate Delay and Typematic Rate The control of Ty
32. B E lock 1 Base Reserved Bits 7 0 lock 1 Size Reserved lock 2 Base Reserved Bits 7 0 lock 2 Size pA D gt gt Bit 7 Memory Remapping 0 Disabled 1 Enabled Blue Chip Technology Ltd 01270173 doc Appendix D Bits 7 6 F Segment Shadow RAM 00 0 Bits 5 4 E Segment Shadow RAM 00 0 Bits 7 6 C3FF Shadow RAM 00 0 Bits 5 4 C7FF Shadow RAM 00 0 Bits 3 2 CBFF Shz 00 0 Bits 1 0 CCO0 CFFF Sha 0 0 00 0 DC00 DFFF Shadow RAM 00 0 Bit 6 Hold Bits 5 0 Refresh Divider 000000 000010 000100 000110 01270173 doc Disa Cache Disal Disable Cache Disable Cache low RAM Disable Cache low RAM Disable Cache Disable Cache adow RAM DBFF Shadow RAM Disable Cache Disable Cache Disable Cache Blue Chip Technology Ltd Bits 2 0 Reserved Bit 6 Appendix D 3 Keyboard Clock Select CPUCLK 6 CPUCLK 5 CPUCLK 4 CPUCLK 3 CPUCLK 2 9 5 MHz 1 7 2 MHz ck Select 000 CPUCLK 5 010 CPUCLK 3 00 7 2 MHz PD Bus ATCLK 1 1 BCLK 3 3 BCLK 7 3 BCLK 12 3 BCLK 7 7 BCLK K K K K K K 12 12BCLK AUTO Config Function 0 1 Disabled Enabled Bit 5 Hardware Parity Check 0 55h SFh Data Location of Local Bus 0 Bus LOWA20 RC Emulation 00 one 0 Both Stretch OWS Sig
33. Byte 0101 Read Only Read every 500mS to reset timer every 500mS to reset timer If the Watchdog is enabled and I O location 0101 hex is not read within 500ms 500ms to 2s variation possible the Watchdog will generate a Reset to both the DX1 and the AT bus To ensure the Watchdog function is disabled on power up reset a write to bit 1 of I O location 0101H is required MOV Dx 0101 MOV Al 02 OUT DX AL Once enabled I O location 0101 HEX should be read at least every 5001 500ms to 2 s variation possible If this location is not read action the time out period a Reset will be generated to both the DX1 and the AT backplane EPROM The E PROM is accessed through a single register at port 100HEX The E7PROM s individual control lines are arranged as follows Port 100 hex 7 5 4 3 2 1 0 Data In Clock for serial data Chip Select Data Out Blue Chip Technology includes drivers for this function on the diskettes supplied with the DX if you wish to access this device Blue Chip Technology Ltd 01270173 doc 44 DX1 Peripheral Components Serial Ports The DX1 provides 2 serial ports Both these ports offer 16C550 type controll including 16 byte buffers for enhanced throughput Both channels can be configured as either RS232 or RS485 interfaces The two on board serial ports can be configured as RS232 or RS485 by writing to I O port 104 hex On power up both the serial ports default as set in the DX 1 Extended Se
34. CBs Solid State Disk section updated ECN97 011 refers Contents i yuuonuvO 1 HNuusigl UO 3 ON BOARD FEATURES retire onere egre i n tede 3 MEMORY OPTIONS S 5 POWER REQUIREMENT er e eit eerte Pe oe E ede 6 ELECTROMAGNETIC COMPATIBILITY nee ene ene enne enne 6 ENVIRONMENT S tese 8 EMC SPECIBICATTION a oin rr e FOR 8 PHYSICA aaah e ete et e 8 BIOS EEEE NTE A 9 System BIOS cs ie bnt e ete eet ei eire 9 Video BIQS s ete rete o scene bra ee e Ree ETE 10 Keyboard BIOS aspa u niaaa eee epar dente ete ones 10 Expansion ROMS p me a Rep d 10 AMI HEFLEX SYSTEM eere tr eve t HERR T I RH nets 11 Features be gua etic 11 dol da eed amie tiv e rete 11 AMIBIOS Power on Self nennen 12 POST Error Messages and Beep eee 12 AMIBIOS SET UP nto rnnt eet inei rete tees 13 Standard CMOS Set up ee s ea ete ei eas 13 Advanced CMOS Set up eene trennen nenne nnne 13 Advanced Chipset Set UP er riens 13 Dx Extended Set Up orreen un a 13 SR tee NO de e 13 Running the AMIBIOS Set up
35. DXI Single Board Computer Blue Chip Technology User Manual DX1 User Manual Document Part N 0127 0173 Document Reference DX 0127 0173 doc Document Issue Level 2 0 Manual covers PCBs identified Issue 2 x amp 3 x x is any digit All rights reserved No part of this publication may be reproduced stored in any retrieval system or transmitted in any form or by any means electronic mechanical photocopied recorded or otherwise without the prior permission in writing from the publisher For permission in the UK contact Blue Chip Technology Information offered in this manual is correct at the time of printing Blue Chip Technology accepts no responsibility for any inaccuracies This information is subject to change without notice All trademarks and registered names acknowledged Blue Chip Technology Ltd Chowley Oak Tattenhall Chester Cheshire CH3 9EX Telephone 01829 772000 Facsimile 01829 772001 Amendment History Issue Issue Amendment Details Level Date 11 05 95 PMD Corrections to Version 1 6 06 06 95 Video Driver Information added ECN95 079 1 9 04 06 96 EGW Added information to Technical Section ECN96 060 Update to J13 link selection for 9054 amp 9154 frequency synthesisers ECN 96 107 External battery voltage modified was 3 6 V New front sheet Previous filename was DXMAN1_9 doc 11 04 96 EGW Minor corrections New frequency synthesiser jumper settings J13 for Iss 3 P
36. DYRTN for one LCLK cycle when DMA or system IO bus master command ends WBACK Write Back WBACK is currently reserved for future use on write back cache systems This pin is tied high on the DX1 card ID 0 4 Identifier pins These pins allow the VL Bus target to identify the type and speed of the host CPU The settings are static levels and for the DX1 processor are set as follows ID0 0 ID1 1 486 CPU ID2 1 0 wait state write ID3 1 Fit link J16 for CPU speed gt 33MHz ID4 0 Reserved ADR 0 31 Address Bus The address bus furnishes the physical memory or IO port address to the VLbus target During VL Bus master cycles the VLbus device acting as bus master drives the addres bus If no VL bus target claims the transfer the VLbus controller drives the VLbus master address to the system DAT 0 31 Data Bus This is a bi directional data path between VL Bus devices and the CPU During read transfers the active VL Bus target drives data onto the DAT O 31 If the read is initiated from a system IO bus master or DMA the data is driven onto the system IO bus by the VL Bus controller During write transfers the CPU DMA slave or bus master drives data onto the data bus BE 0 3 determine which byte lane s of the data bus are valid Blue Chip Technology Ltd 01270173 doc 58 ISA amp VESA Bus Details 0 3 Byte Enables The byte enables indicate which byte lanes of the 32 bit data
37. Drive A Type Bits 3 0 Drive B Type bit settings same as A 10h lih 2h System Boot Up Num Lock No drive Hard drive Type 1 14 1 0 300h Hard Disk Type 16 255 actual Hard Drive Type is in CMOS RAM 1 Hard Disk Data Bits 7 4 Hard Disk Drive C Type Bits 3 0 Hard Disk Drive D Type Same as C 01270173 doc 82 c Ia Ju t3 01270173 doc Bit 7 Appendix D Typematic Rate Programming 1 Enabled Bits 6 5 Typematic Rate Delay in milliseconds 00 10 250 ms 750 ms Bits 4 2 Typematic Rate in characters per second 000 010 100 110 Equipment Byte 6 cps 10 cps 15 cps 24 cps Bits 7 6 Number of Floppy Drives 00 01 10 Bits 5 4 Monitor 001 01 10 11 1 Drive 2 Drives Reserved Not CGA or MDA 40x25 CGA 80x25 CGA MDA Monochrome Display Enabled Keyboard Enabled Math coprocessor Installed Floppy Drive Installed 1 Enabled 0 On 500 ms 100 ms 8 cps 12 cps 20 cps 30 cps 1 Enabled 1 Enabled Hard Disk C Drive Type 0 15 16 255 Reserved Hard Drive Type 16 255 Hard Disk D Drive Type Same as Drive C above User Define Drive C of Cylinders Low Byte User Defined Drive C of Cylinders High Byte User Defined Drive C Number of Heads Define Define Define Define Define Drive C Landing Zone Low Byte Drive C Landing Zo
38. I disabled next 02 03 Power on delay complete Keyboard initialisation w Sending BAT command to the keyboard controller BAT verified A Keyboard command code byte sent c u CMOS RAM shutdown register test passed OF 10 CMOS RAM status register initialised 04 05 06 07 08 09 0 0 OD 10 12 13 15 16 17 imc Base 64KB memory read write test passed Memory refresh started 12 13 14 15 16 17 18 19 1B 20 21 22 23 Blue Chip Technology Ltd 01270173 doc 64 Appendix t2 ER System configuration before vector initialisation completed 8042 input port read Turbo initialisation completed 31 Video display read write or retrace test failed Nn video display read write test passed New cursor position has read and saved Interrupts ar are enabled if the diagnostics switch is on 4 49 4 emory test started No soft reset was performed P o 1 4 olaja 4 ips emory size display has begun The display is updated during the test Memory test below 1MB is completed Memory size has been adjusted for memory relocation above 1MB Memory test above 1MB complete CPU registers saved Un N _24 25 27 28 29 2B OC 2E 28 30 La 33 mom 35_ 36 37 _38 3B 40 4 _ 43 44
39. LK period at the end of each burst transfer If LRDY and BRD Y are asserted at the same time BRD Y is ignored and the current burst cycle returns to non burst cycles Tri state control of BRD Y follows the same rules as LRDY While the VL Bus is inactive this signal is pulled high Local Request used in conjunction with LGNT is used by a VL Bus device to gain control of the VL Bus and become an active local bus master When the VL Bus device asserts LREQ the VL Bus controller responds by asserting LGNT The VL Bus then has control of the VL Bus and may hold the bus until the VL Bus controller removes LGNT While the VL Bus is inactive this signal is pulled high IRQ Interrupt Request Line 9 IRQO line is a high asserted level triggered interrupt that is electrically connected to the IRQ9 on the ISA bus 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 61 BCT DX1 SBC I O Address DX1 default 0000 001 Y 0020 003F 0040 005 0060 006 0070 007 0080 008 00A0 00BF 00C0 00F0 OOF OOF8 OOFF Maths Coprocessor 0100 010 Watchdog E7PROM Byte Wide Socket amp Software selection of serial ports O1FO O1F8 Hard Fixed Disk Controller 0200 0207 0278 027F Parallel Printer Port 2 0208 021A EMS Page registers either 208 or 218 etc 02 8 02EF 02 8 2 0300 031F 0360 036F 0378 037F 0380 038F
40. OS This controls the local electronics It also provides the interface to the hardware for the operating system Video BIOS This controls the interface between the video hardware and the computer Keyboard BIOS This controls the keyboard matrix operation interacts with switches LEDs etc and communicates with the PC Each of these BIOS s will now be described System BIOS The primary function of the System BIOS is to provide a series of software interrupts functions and sub functions that perform specific system tasks such as writing or reading to and from disks and video screens The operating system uses the System BIOS as the route to communicate and control the microprocessor and its immediate peripherals This exchange of data occurs via a strict protocol The secondary function of the System BIOS is the series of tests and initialisations that occur after power on The results of these operations are written to the POST display if fitted as they are completed thereby indicating its progress Blue Chip Technology Ltd 01270173 doc 10 BIOS The System BIOS the DX1 is contained in a 128KB EPROM of this space the System BIOS occupies 64KB The EPROM is located at address F0000 hex and continues to FFFFF hex The supplier of the BIOS is AMI currently the leading supplier of PC BIOS s in the world BCT have selected this supplier because of their experience support and commitment to future developments in t
41. SIEEBBBDDIDSSIEEEBBBDDSES O 13X 14X 15X ai 175 18H 199 Month Jan Feb e UU QUU quU dU Date 01 02 03 31 20H 21H 22H 23H 24H 25H du Year 1901 1902 D 27x 28X m 30H 314 1 209 JUGE AI Qoo qi aeta 3M 4 5X 6X 7X 8H 9 Blue Chip Technology Ltd 01270173 doc 18 BIOS DIO ESC Exit Lote Select F2 F3 Color PU PD Modify PABEN BEND BENE BOSE BESE BOSE BED 01270173 doc Blue Chip Technology Ltd BIOS Page 19 Date This entry allows you to set the Date Month and Year Ranges for each value are shown in the lower left corner of the CMOS Set up Screen Time This entry allows you to set the Hours Minutes and Seconds The clock operates in 24 hour mode that means that for PM time add 12 to the hour e g enter 6 35 PM as 18 35 00 Floppy Disk Configuration The DX1 supports None 360KB 720KB 1 2MB 1 44MB amp 2 88MB drives The BIOS supports two drives A and B Hard Disk Configuration Two hard disk drives are supported directly by the BIOS C and D Each drive can select drive types from 1 to 46 In addition type 47 is user definable allowing customised parameters for the drive to be entered Both drives can be set to a different type 47 if required To set the values for type 47 use and gt keys to select the appropriate field and then type in as required A complete list of the 46 hard disk type is contain
42. T Error Messages and Beep Codes If the BIOS cannot configure the display controller it will communicate the identification of fatal errors except error code 8 via a series of beeps These errors will only occur during power on tests The beep codes are as follows Timer is not functioning Alternatively memory in the first 64KB faulty 8042 Gate A20 Failure BIOS cannot switch to protected mode 7 Processor Exception Interrupt CPU generated an exception interrupt Error error EB indu Video adapter is not responding or its Error memory is faulty ROM Checksum Error ROM checksum embedded in the ROM does not match the calculated value ENT T FM The shutdown register in the CMOS Read Write Error RAM failed Check access to CMOS Cache Memory Bad Do Not The cache memory test failed Cache Enable Cache memory is disabled Do not press lt CTRL gt ALT lt SHIFT gt lt gt to enable cache memory What to do if the DX1 Beeps If the system beeps 1 2 or 3 times Re seat the SIMMs If the DX1 still beeps replace the SIMMs checking the access time 6 times Check the keyboard connections If the beeps persist change the keyboard 4 5 7 8 9 10 or 11 Contact Blue Chip Technology 01270173 doc Blue Chip Technology Ltd BIOS Page 13 AMIBIOS Set up The Hi Flex AMIBIOS Set up utility is divided into five parts Standard CMOS Set up The Hi Flex AMIBIOS Standard CMOS Set up permits the user to
43. ached The contents of D0000h D3FFFFh are shadowed from ROM to RAM and can be written to or read from cache memory Disabled The contents of D0000h D3FFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory but cannot be written to or read from cache memory Blue Chip Technology Ltd 01270173 doc 32 BIOS D400 D7FF Shadow RAM This option specifies if the contents of the ROM memory area from D4000 D7FFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 The contents of D4000h D7FFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory The contents of D4000h D7FFFFh are shadowed from ROM to RAM and can be written to or read from cache memory The contents of D4000h D7FFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of D4000h D7FFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory D800 DBFF Shadow RAM This option specifies if the contents of the ROM memory area from D8000 DBFFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 The contents of D8000h DBFFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cac
44. adiate or behave as if keys are pressed when subject to interference Under these circumstances it may be beneficial to add a ferrite clamp on the keyboard lead as close as possible to the connector A suitable type is the Chomerics type H8FE 1004 AS e Ensure that the screens of any external cables are bonded to a good RF earth at the remote end of the cable Failure to observe these recommendations may invalidate the EMC compliance Warning This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures Blue Chip Technology Ltd 01270173 doc 8 Specification Environment Operating Temperature 0 C to 60 C Storage Temperature 20 C to 70 C Relative Humidity 90 non condensing EMC Specification A Blue Chip Technology Icon industrial PC fitted with this card meets the following specification Emissions EN 55022 1995 Radiated Class Conducted Class amp B Immunity EN 50082 2 1995 incorporating Electrostatic Discharge IEC 801 2 1991 Performance Criteria Radio Frequency Susceptibility 50140 1993 Performance Criteria A Fast Burst Transients 801 4 1988 Performance Criteria A Physical Size 339 x 122mm Occupies one AT VESA slot 01270173 doc Blue Chip Technology Ltd BIOS Page 9 BIOS Overview There are several types of Basic Input Output Systems BIOS in a PC system System BI
45. are valid when BALE is high LA17 through LA23 are not latched during microprocessor cycles and therefore do not stay valid for the whole cycle Their purpose is to generate memory decodes for wait state memory cycles These decodes should be latched by I O adapters on the falling edge of BALE These signals also may be driven by other microprocessors or DMA controllers that reside on the I O channel Master I This signal is used with a DRQ line to gain control of the system A processor or controller on the I O channel may issue DRQ to a DMA channel in cascade mode and receive a Upon receiving the DACK an I O microprocessor may pull Master low which will allow it to control the system address data and control lines a condition known as tri state After Master is low the I O microprocessor must wait one system clock period before driving the address and data lines and two clock periods before issuing a Read or Write command If this signal is held low for more than 15 microseconds system memory may be lost because of a lack of refresh MEMCS16 D 16 Chip Select signals the system board if the present data transfer is a 1 wait state 16 bit memory cycle It must be derived from the decode of LA17 through LA23 MEM CS 16 should be driven with an open collector or tri state driver capable of sinking 20 mA OSC O Oscillator OSC is a high speed clock with a 70 nan
46. assword Stordg ete RU ettet 38 Password Options Control 1 eee 38 Usinge Password 5 settore dee e e tpi ET steels 38 01270173 doc Blue Chip Technology Ltd Contents Auto Detect Hard Disk iac ace 36 Write i0 CMOS and Exit S S un eene EE lias asks eee EHE RIO 39 Do Not Write to CMOS and Exit esses eee sree 39 DX1 PERIPHERAL COMPONENTS 40 MIDEOQ 2220 tient et 40 IBM Standard Video Modes 4I Cirrus Logic Extended Video Modes se eee 4I MIDEO DRIVERS L ln n Eee eee tones eoe genes eeeee Eure eese evedr eee E 42 VIDEO DRIVER INSTALLATION INSTRUCTIONS eene enne 42 WATCHDOG TIMER nnne esas esse serene nn 43 PEE 43 SERIAL PORTS deett detective ete a D NS u SSS e ee E e eee esse 44 BYTE WIDE SSD USER SOCKETS l 45 BATTERY unn ndn LE 46 MEMORY MAP sa aaa 47 Typical Memory Map for a IMByte DX sss eene 47 DISK DRIVES screens RURSUM 48 redet e ER P ee EFE E RATEN 48 Hard Drives IDE x s teet er eee ette 49 HARD DISK TYPES u gaa u tercer eave eine S hpa 49 ISA BUS amp VESA LOCAL BUS DETAILS
47. atible providing on board local bus SVGA with a GUI accelerator and a VL Bus expansion slot The VL Bus specification states that up to 3 VL Bus devices can be supported As the DX board has on board VL Video control a further 2 VL Bus devices can be added to the VL expansion slot Connection to this expansion slot can be achieved using Blue Chip Technology passive backplanes VL Bus Signal Definitions RESET System Reset This low asserted signal is a master reset that is asserted after system power up and prior to any valid CPU cycles It is driven by the DX1 card to all bus masters and targets There is no guaranteed relationship between the rising or falling edges of RESET and the phase of LCLK Local CPU Clock The LCLK VL Bus clock signal is a 1X clock that follows the same phase as the 486 CPU LCLK is driven by the DX1 to all VL Bus masters and targets The rising edge of the clock signifies the change of CPU states RDYRTN Ready Return RDYRTN establishes a handshake so the VL Bus target knows when the cycle has ended RDYRTN is driven by the DX1 to all VL Bus masters and targets 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 57 For DX1 cards with CPU speeds up to 33MHz RDYRTN is asserted on the same LCLK as LRDY At CPU speeds greater than 33MHz RDYRTN will trail LRDY due to clock re synchronisation During or system IO bus master cycles the VL Bus controller asserts R
48. bled The contents of E0000h EFFFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory 01270173 doc Blue Chip Technology Ltd BIOS Page 29 F Segment Shadow RAM This option specifies if the contents of the ROM memory segment from F0000 FFFFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 The contents of F0000h are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory The contents of F0000h FFFFFFh are shadowed from ROM to RAM and can be written to or read from cache memory The contents of F0000h cannot be shadowed from ROM to and cannot be written to or read from cache memory Enabled The contents of F0000h FFFFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory C000 C3FF Shadow RAM This option specifies if the contents of the ROM memory area from C0000 C3FFFh are shadowed to RAM and if these contents can be stored in cache memory Into 486 The contents of CO000h C3FFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory Cached The contents of CO000h C3FFFFh are shadowed from ROM to RAM and can be written to or read from cache memory The contents of C0000h C3FFFFh cannot
49. bus are involved with the current VL Bus transfer BE 0 3 are driven by the CPU for all CPU initiated transfers During system IO bus master or cycles the VL Bus controller drives 0 3 according to the values of address bits 0 1 and SBHE During VL Bus master transfers the active bus master device drives BE 0 3 M IO Memory IO Status This CPU output indicates the type of access currently executing A memory cycle is indicated by M IO driven high a low indicates an IO cycle is driven by the CPU for all CPU initiated cycles During system IO bus master or DMA cycles the VL Bus controller drives M IO according to the values of MEMR MEMW IOR and IOW During VL Bus master transfers the active bus master device drives W R Write or Read Status This CPU output indicates the type of access currently executing A write cycle is indicated by W R driven high a low indicates an read cycle W R is driven by the CPU for all CPU initiated cycles During system IO bus master or DMA cycles the VL Bus controller drives W R according to the values of MEMR MEMW IOR and IOW During VL Bus master transfers the active bus master device drives W R D C Data or Code Status The data code status signal indicates whether the current cycle is transferring data or code During VL Bus master transfers the VL Bus acting as bus master drives D C BLAST Burst Last This signal indicates that the ne
50. configure and set system components such as floppy drives hard disk drives time and date monitor type and keyboard These options are discussed on page 17 Advanced CMOS Set up The Advanced CMOS Set up allows the user to configure more advanced parts of memory operation and peripheral support These options are discussed on page 20 Advanced Chipset Set up The Advanced Chipset configures the UMC 82C491 specific features and is discussed further on page 25 Dx 1 Extended Set up The DX 1 Extended Set up configures the on board floppy IDE serials and parallel devices These are all controlled by the SMC 37C663 device In addition it provides configuration of the Quick Disk SSD and Daughter Board SSD facilities These options are discussed further on page 34 Utilities The AMIBIOS provides support for Password security access This will be discussed further on page 37 Blue Chip Technology Ltd 01270173 doc 14 BIOS Running the AMIBIOS Set up The system parameters such as amount of memory disk drives video displays and numeric co processors are stored in CMOS RAM When the DX1 is turned off a back up battery on board the DX1 provides power to the CMOS RAM thereby retaining the system parameters Each time the DX1 is powered on it is configured with these values unless the CMOS RAM has been corrupted The AMIBIOS Set up resides in the ROM BIOS and is available each time the DX1 is switched on If for some reason
51. e e oe ped eee 95 APPENDIX esceadectesensedeetesonseseetoss seas 96 CONNECTOR AND JUMPER LINK PCB POSITIONS 96 01270173 doc Blue Chip Technology Ltd Introduction Page 1 INTRODUCTION This manual describes the Blue Chip Technology BCT DX1 processor card There are several versions of the card these will be identified where appropriate We strongly recommend that you study this manual carefully before attempting to change the configuration Whilst all necessary information is available in this manual we would recommend that unless you are confident you contact your supplier to effect any changes This card uses the UMC 82C491 amp 82C493 VLSI devices they provide a complete AT compatible environment with VESA VL Bus compatible local bus support WARNING The devices on this card can be fatally damaged by static electricity Ensure that you touch a suitable ground to discharge any static build up before touching the card This should be repeated if the handling is for any length of time Information offered in this manual is correct at the time of printing Blue Chip Technology accept no responsibility for any inaccuracies This information is subject to change without notice If this product proves to be defective Blue Chip Technology is only obliged to replace or refund the purchase price at Blue Chip Technology s discretion Please contact our Customer Support
52. e enabled for either the On board SSD or Daughter Board SSD devices to operate If you do not require SSD operation you should Disabled this option thereby releasing 16KB of higher memory Auto Configuration with Defaults By selecting this option you automatically configure the system using the default values These values are worst case values for system performance but are the most stable values in the harsh conditions where we expect our products to be used If you experience any erratic problems with DX1 we strongly suggest that you configure with default values and test the system again Change Passwords The Hi Flex AMIBIOS has an optional password feature The system can be configured so that you have to enter a password every time the system boots or when the AMIBIOS Set up is executed Bypassing Password Support You can bypass the password support by pressing lt Enter gt when the password prompt appears Enabling Password Support The password check option is enabled in Advanced CMOS Set up by choosing either Always or Set up The password which can up to 6 characters in length is stored in CMOS RAM If a Password is Used You must type correctly the current password when enter CURRENT Password Blue Chip Technology Ltd 01270173 doc 38 BIOS appears After the current password has been correctly entered the user is asked to retype it If the password information is incorrect an error message appears
53. e the board can be installed in a variety of computers certain conditions have to be applied to ensure that the compatibility is maintained It meets the requirements for an industrial environment Class A product subject to those conditions e The board must be installed in a computer system which provides screening suitable for the industrial environment e Any recommendations made by the computer system manufacturer supplier must be complied with regarding earthing and the installation of boards e The board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal to metal i e earth contact e Most EMC problems are caused by the external cabling to boards It is imperative that any external cabling to the board is totally screened and that the screen of the cable connects to the metal end bracket of the board and hence to earth It is recommended that round screened cables with a braided wire screen are used in preference to those with a foil screen and drain wire Use metal connector shells which connect around the full circumference of 01270173 doc Blue Chip Technology Ltd Specification Page 7 the screen they are far superior to those which earth the screen by a simple pig tail e The keyboard will play an important part in the compatibility of the processor card since it is a port into the board A fully compatible keyboard must be used otherwise the keyboard itself may r
54. ed in the Technical Reference section of this manual on page 49 Display This entry allows the user to select MDA monochrome CGA or EGA PGA VGA display controllers If your system is to operate without a display then select Disabled Failure to do this will result in an error being generated during the power on diagnostics check Keyboard The DX1 keyboard interface can be connected to either AT or PS 2 keyboards The default setting is Enabled If your system is to operate without a keyboard then select Disabled Failure to do this will result in an error being generate during the power on diagnostics check Blue Chip Technology Ltd 01270173 doc 20 BIOS Using the Advanced CMOS Set up The default condition for the Advanced CMOS Set up Menu is as shown below By using T keys you can select the parameter to be changed Once positioned on the parameter to be modified the lt PgUp gt and lt PgDn gt keys rotate the available options The value selected when the menu 15 exited is the one that will be written to CMOS should you decide to commit your changes to CMOS NAS CSS 2526965 565 65 96S 25 26965 5269 65 96S 25 9 65 05 269 65 5 25 9 250 TRY AMIBIOS SETUP PROGRAM ADVANCED CMOS SETUP x C 1993 American Megatrends Inc All Rights Reserved CSC EBES ESBS EBB S PPEPEEEPEEEEEPPEPEEEEEGEPPEP NES IS 25 26965
55. efault is Full Second Serial Port Mode The DX 1 provides software control of the serial port modes The settings can be RS232 or RS485 422 The power up condition of both serial ports is controlled by the BIOS Set up The default is RS232 Please note that RS485 connections for both the serial ports are made through a special connector P4 Second Serial Port 485 Mode Once the serial mode is set to RS485 the port can be configured as either Half or Full duplex Half duplex is a 2 wire implementation whilst Full duplex is a 4 wire system Quick Disk Boot Rom This option allows the selection of the On board Flash amp SRAM Solid State Disk SSD located in two 32 pin bytewide sockets found below the EPROM device SSD Boot Rom This option allows the selection of the optional Daughter Board Flash amp SRAM Solid State Disk SSD unit if fitted to connectors P17 amp P10 SSD Note The Quick Disk Silicon Disk and the Daughter Board Silicon Disk options should not be Enabled at the same time This will cause an error during power up 01270173 doc Blue Chip Technology Ltd BIOS Page 37 CardTrick Boot Rom This option allows the selection of the Flash device to act as a bootable disk drive Please contact Blue Chip Technology for further information BIOS Extensions The DX 1 provides Solid State Disk SSD BIOS support via an Expansion ROM located at memory addresses C800 0 to CBFF F 16KB This BIOS Expansion ROM must b
56. en to or read from cache memory Disabled The contents of C8000h CBFFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of C8000h CBFFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory 01270173 doc Blue Chip Technology Ltd BIOS Page 31 CC00 CFFF Shadow RAM This option specifies if the contents of the ROM memory area from CC000 CFFFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 The contents of CC000h CFFFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory The contents of CC000h CFFFFFh are shadowed from ROM to and can be written to or read from cache memory The contents of CC000h CFFFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of CC000h CFFFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory D000 D3FF Shadow RAM This option specifies if the contents of the ROM memory area from D0000 D3FFFh are shadowed to RAM and if these contents can be stored in cache memory Into 486 The contents of D0000h D3FFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory C
57. ental specifications are much superior to mechanical drives they occupy no extra space and they are much faster The Daughter Board SSD allows up to 4MBytes of Flash and 512KBytes of SRAM to be fitted Various configurations of the card are available please contact BCT for further details 1 2 From a Power up Reset lt CTRL gt lt ALT gt lt DEL gt enter the BIOS Set UP see page 14 for information on how to enter the BIOS Set Up Enter the Standard CMOS Set Up and configure the floppy and hard drives as required For simplicity let us assume that all drives are Disabled Escape back to the main menu and enter the DX 1 Extended Set Up Set the Daughter Board Disk option to Enabled Ensure that the Quick Disk Silicon Disk option is Disabled Set the C800 CBFF Internal ROM SSD expansion BIOS to Enabled Escape back to the main menu and press lt F10 gt to save and Exit Blue Chip Technology Ltd 01270173 doc 96 Appendix G APPENDIX G Connector and Jumper Link PCB Positions A diagram showing the positions of the various connectors and links follows 01270173 doc Blue Chip Technology Ltd Appendix G Page 97 BIOS FLASH SRAM EPROM Socket Socket mE E J16 E ngj Regl P12 P15 LI Battery B t Blue Chip Technology Ltd 01270173 doc
58. ents of the specified block of system memory cannot be written to or read from cache memory These options permit the user to specify an area of memory Block 1 or Block 2 that cannot be cached The settings are Enabled or Disabled Blue Chip Technology Ltd 01270173 doc 28 BIOS Non cacheable Block 1 Base Non cacheable Block 2 Base These options set the base address or beginning of areas of memory whose contents cannot be written to or read from cache memory The base address must begin on a boundary equal to the Non cacheable Block Size setting The settings are 0 KB through 16384 KB Memory Remapping If this option is enabled the contents of system memory between A0000h and FFFFFh that have not been shadowed to RAM from ROM are moved to the top of system memory The settings are Enabled or Disabled E Segment Shadow RAM This option specifies if the contents of the ROM memory segment from E0000 EFFFFh are shadowed to RAM and these contents can be stored in cache memory Into 486 The contents of E0000h EFFFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory Cached The contents of E0000h EFFFFFh are shadowed from ROM to RAM and can be written to or read from cache memory Disabled contents of E0000h EFFFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Ena
59. et up Program The default condition for the CMOS Set up Menu is as shown below This menu sets the basic system parameters such as date time floppy disk and hard disk types By using the T keys you can select the parameter to be changed Once positioned on the parameter to be modified the lt PgUp gt and lt PgDn gt keys rotate the available options The value selected when the menu is exited 15 the one that will be written to CMOS should you decide to commit your changes to CMOS FRE EKER ORE ERE ERE BEER EEE ERR ER EERE BEER EERE BEER PP BIOS SETUP PROGRAM STANDARD CMOS SETUP 138 American Megatrends Inc All Rights Reserved e LORE EERE III IBI III IIS ISI SIBI IIIS 55 Bepppp pspsspPspbopbpsbpsspsbsbpsbPsbPPbPPB o Date mn date year Tue Jan 01 1980 Base Memory 640KB Time hour min sec 00 00 00 Ext Memory 4096 Cyln Head WPcom LZone Sect Size Hard Disk Type Not Installed Hard Disk D Type Not Installed Floppy Drive A 4 MB 3 EBBES ERR BESS Floppy Drive Not Installed GSunXtMonX TueXWedX ThuXFri X Sat G Primary Display VGA PGA EGA DC Jeep ceca SEE gt BE gt BE a gt Keyboard Installed 30H 31H 1X 2X 3X 4H 58 7X 8X 9X 10H 11X 129 s nn SS pee NU CESEBEBBBBBPISHI
60. et up default values are used F6 Loads all features in the Advanced CMOS Set up Advanced Chipset Set up with the AMIBIOS Set up defaults F7 Loads all features in the Advanced CMOS Set up Advanced Chipset with the Power On defaults Saves all the changes made to Set up and continues the boot process The DX1 AMIBIOS Set up main Menu is shown below The options are selected by using the T and keys and then pressing Enter AMIBIOS SET UP PROGRAM BIOS SET UP UTILITIES Copyright 1993 c American Megatrends Inc All Rights Reserved STANDARD CMOS SET UP ADVANCED CMOS SET UP ADVANCED CHIP SET SET UP DX 1 EXTENDED SET UP AUTO CONFIGURATION WITH BIOS DEFAULTS AUTO CONFIGURATION WITH POWER ON DEFAULTS PERIPHERAL SET UP CHANGE PASSWORD AUTO DETECT HARD DISK HARD DISK UTILITY WRITE TO CMOS AND EXIT DO NOT WRITE TO CMOS AND EXIT Standard CMOS Set up for changing Time Date Hard Disk Type etc Blue Chip Technology Ltd 01270173 doc 16 BIOS Each option is described in detail on the pages identified as follows Main Menu Option Described on Page STANDARD CMOS SET UP ADVANCED CMOS SET UP ADVANCED CHIP SET SET UP DX 1 EXTENDED SET UP AUTO CONFIGURATION WITH BIOS DEFAULTS AUTO CONFIGURATION WITH POWER ON DEFAULTS CHANGE PASSWORD AUTO DETECT HARD DISK HARD DISK UTILITY WRITE TO CMOS AND EXIT DO NOT WRITE TO CMOS AND EXIT 01270173 doc Blue Chip Technology Ltd BIOS Page 17 Using the CMOS S
61. fault boot sequence is drive A and then C This would mean that if drive 15 not ready then the boot occurs from C The alternative is to boot from drive C and if C 1 not ready then drive A Hence the settings are either A C or C A External Cache Memory The default is Enabled If your DX1 is configured with external cache 256KB then this will then be used The option is to Disable the cache Internal Cache Memory This option enables the CPU internal cache memory The settings are Enabled or Disabled The BIOS Set up default is Enabled Turbo Switch Function This option enables the externally mounted hardware Turbo switch the settings are Enabled or Disabled The default is Enabled Always ensure that a switch is connected when the setting is Enabled so that noise does not cause false selection of speed states Fast Gate A20 Option Gate A20 controls the method of accessing memory addresses above 1 MB by enabling or disabling access to the processor line A20 To provide XT compatibility address line A20 must always be low and therefore the option should be Disabled However some applications both enter protected mode and shut down through the BIOS For this software Gate A20 must be constantly enabled and disabled via the keyboard controller 8042 which slows down the processing Fast Gate A20 is another method for handling Gate A20 using the UMC491 internal circuitry It speeds programs that constantly change f
62. he memory The contents of D8000h DBFFFFh are shadowed from ROM to RAM and can be written to or read from cache memory Disabled The contents of D8000h DBFFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory Enabled The contents of D8000h DBFFFFh are shadowed from ROM to RAM but cannot be written to or read from cache memory 01270173 doc Blue Chip Technology Ltd BIOS Page 33 DC00 DFFF Shadow RAM This option specifies if the contents of the ROM memory area from DC000 DFFFFh are shadowed to RAM and if these contents can be stored in cache memory Setting Into 486 The contents of DC000h DFFFFFh are shadowed from ROM to RAM and can be written to or read from the internal cache memory on the 486 but not to external secondary cache memory Cached The contents of DC000h DFFFFFh are shadowed from ROM to RAM and can be written to or read from cache memory Disabled The contents of DC000h DFFFFFh cannot be shadowed from ROM to RAM and cannot be written to or read from cache memory RAM but cannot be written to or read from cache memory Refresh Divider The settings are 1 2 4 8 16 32 or 64 Data Location of Local Bus The settings are ISA Bus or PD Bus LOWA20 RC Emulation The settings are None GA20 or Both Stretch 0WS Signal Option The settings are Do Not or 1 2 ATCLK Hardware Parity Check When this option is set to Enabled the AMIBIOS enables the hard
63. his critical area of a PC AT design Video BIOS The Video BIOS acts as an interface between the System BIOS and the video hardware It is critical that this interface is compatible fast and reliable The Video BIOS provides a relatively high level of access to the hardware The on board video hardware on the DX1 is based on the Cirrus Logic GD5424 26 28 29 This device offers proven VGA compatibility as well as providing enhanced GUI acceleration in a single device It is supported by up to 2MB of video memory The Video BIOS co exists in the System BIOS EPROM but locates in the address range C0000 to C7FFF hex Keyboard BIOS The Keyboard BIOS is contained in the 8042 or 8742 keyboard controller This device provides a parallel interface to the microprocessor bus allowing a bi directional streams of data to be passed between the PC and the keyboard The BIOS is programmed into the 8042 It occupies none of the memory map Expansion ROMs Most PCs allow add on cards to be inserted into the backplane If software is required to control the electronics on the card the supplier may choose to provide this software in the form of an expansion ROM or adapter ROM On power on the PC once initialised checks for the presence of ROMs within the memory space of C8000 to DFFFF hex If present the code within the ROM is run and the specific hardware on the card controlled accordingly In addition this software can then be used as the interface to the
64. hnology Ltd Using Advanced Chipset BIOS Page 25 The default condition for the Advanced Chipset Set up Menu is as shown below By using the T keys you can select the parameter to be changed Once positioned on the parameter to be modified the lt PgUp gt and lt PgDn gt keys rotate the available options The value selected when the menu is exited is the one that will be written to CMOS should you decide to commit your changes to CMOS SREBR RRR REE EEE EERE REBAR SIII SIII SIISII ISI III IIIS PREPPEREEFEEEEEERPERPEREREEEREPRER Non Cacheable Block 2 Size 16MB BIOS SETUP PROGRAM ADVANCED CHIPSET SETUP C American Megatrends Inc All Rights Reserved WCGPEPPPPEPPPPPPPEPPEPPPEPPEPPEPPEPPEPPEPPEPPEPPPEPP2CPPPEPP AUTO Config Function Enabled Memory Remapping Enabled Cache Read Option 3 1 1 1 F Segment Shadow Into 486 Cache Write Option 1 W S 9 E Segment Shadow Disabled DRAM FastPage C000 C3FF Shadow RAI Into 486 DRAM Wait State s 1 W S C400 C7FF Shadow Into 486 Keyboard Clock Select CPUCLK 4 C800 CBFF Shadow Disabled Clock Select CPUCLK 4 CC00 CFFF Shadow Disabled IO Recovery Time 5 3 BCLK D000 D3FF Shadow Disabled Hold PD Bus 1 2 T
65. k 6 NotUsed P10 SSD Connector 8 way header P11 Com 1 9 way D PS Volts Ground 6 Data Set Ready 7 Ready ToSend_ s Clear To Send Indicator PE P12 Peripheral 20 way header Do Asdosve Audo ve 3 Reeve 4 Reset ve Ground 5 High Speed LED ve 6 HighSpeedLED ve 7 Keylock ve 8 Keylock ve Groun 9 Power LED ve Power LED Ground Blue Chip Technology Ltd 01270173 doc 74 Appendix P13 Keyboard 6 pin mini DIN Keyboard Data 0 Volts Ground 5 Volts fused Keyboard Clock L 6 P14 Battery 4 way header 3 6 VoltsDC I O key _ 3 _ Volts Ground PP Volts Ground 3 _ High Speed LED ve 4 HSLED ve Ground 5 Power LED ve 6 Power LED ve Ground 7 _ Keylock ve 8 Keylock ve Ground 9 Turbo Switch ve 10 Turbo Switch ve Ground 01270173 doc Blue Chip Technology Ltd Appendix 75 P16 Expansion Connector Blue Chip Technology Ltd 01270173 doc 76 Appendix 17 PC XT Expansion Connector L5 sp Volts 505 I 33 35 37 39 41 43 45 47 49 51 53 55 57 59 01270173 doc Blue Chip Technology Ltd Appendix 77 ISA Bus XT Connections A Large gold fingers under P17 on main Component side B Large gold fingers under P17 on passive Component side AG sp3 nao
66. low IMB of memory When microprocessor on the I O channel wishes to drive MEMR it must have the address lines valid on the bus for one system clock period before driving MEMR active Both signals are active low SMEMW O MEMW These signals instruct the memory devices to store the data present on the data bus SMEMW is active only when the memory decode is within the low 1 MB of the memory space MEMW is active on all memory write cycles MEMW may be driven by any microprocessor controller in the system SMEMW is derived from MEMW and the decode of the low IMB of memory When a microprocessor the I O channel wishes to drive MEMW it must have the address lines valid on the bus for one system clock period before driving MEMW active Both signals are active low T C O Terminal Count provides a pulse when the terminal count end of for any DMA channel is reached Blue Chip Technology Ltd 01270173 doc 56 ISA amp VESA Bus Details VESA Local Bus Description With the ever increasing performance demands of complex software applications the PCs 8MHz ISA bus can become a bottleneck By connecting peripheral devices onto the processors local bus this bottleneck can be freed opening up the bus to the full processor bandwidth Typical peripheral devices which benefit from local bus are video disks and LAN network adapters The DX1 is designed to be VESA VL Bus comp
67. nal Option 0 Do Not Bits 3 0 IO Recovery Time of ISA PCB 0000 0 0 BCL 0010 2 2 BCL 0100 5 3 BCL 0110 9 3 BCL 1100 5 5 BCL 1110 9 9 BCL L ll l lC V Disabled Enabled Page 87 Reserved Bits 7 0 Device 1 Timeout Bits 7 0 Device 2 Timeout Bits 7 0 Device 4 Timeout mum Bits 7 0 Device 3 Timeout Bits 7 0 Device 5 Timeout Blue Chip Technology Ltd 01270173 doc 88 Appendix D cm 01270173 doc Blue Chip Technology Ltd Appendix E Page 89 APPENDIX E Chipset Registers The AMIBIOS for the Blue Chp Technology DX1 SBC sets the following values in the chipset registers ort AUTO Config Function 0 Disabled Enabled Hardware Parity Check 0 Disabled Enabled Read Option 01 3 2 2 2 1 2 1 1 1 Cache Write Option 01 1 Refresh Cycle PageMode FastPage DRAM Wait State s 01 2W S 1 0 W S Non Cacheable Block 2 Enable 0 Disabled Enabled Non Cacheable Block 1 Enable 0 Disabled Enabled Blue Chip Technology Ltd 01270173 doc 90 Appendix E Bit 6 CoProcessor Ready 0 Delay 1T 1 No Delay Bit 5 Check ELBA Signal in TI in T2 a E eable Block 1 Base Bits 7 0 Non Cacheable Block 1 Size eable Block 2 Base Reserved Bits 7 0 Non Cacheable Block 2 Size Q o a a a a Q gt Memory Remapping 0 Q F Segment Shadow RAM 00 Disab 0 Cache E Segment Shadow RAM 00 Disab C5 0
68. ne High Byte Drive C Write Precompensation Cylinder Low Byte Drive C Write Precompensation Cylinder High Byte Drive C Control Byte 80h if of heads is equal or greater than 8 Blue Chip Technology Ltd N gt E N a gt D N a t2 oo gt N D gt D a ERE Ui Appendix D Page 83 User Defined Drive C of Sectors User Defined Drive D of Cylinders Low Byte User Defined Drive D of Cylinders High Byte User Defined Drive D Number of Heads User Defined Drive D Write Precompensation Cylinder Low Byte User Defined Drive D Write Precompensation Cylinder High Byte User Defined Drive D Control Byte 80h if of heads is equal or ereater than 8 User Defined Drive D Landing Zone Low Byte User Defined Drive D Landing Zone High Byte User Defined Drive D of Sectors Configuration Options Bit 7 Weitek Processor resent Bit 6 Floppy Drive Seek At Boot Enabled Bit 5 System Boot Up Sequence 12 C Bit 4 System Boot Up CPU Speed 1 High Bit 3 External Cache Memory Enabled Bit 2 Internal Cache Memory Enabled Bit 1 Fast Gate A20 Option Enabled Bit 0 Turbo Switch Function 1 Enabled nformation Flag Bit 7 BIOS Size 1 128 KB Bits 6 0 Reserved Boot Sector Virus Protection 1 2 Enabled Password 0 Always 1 Setup Adaptor ROM Shadow C800 16K 1
69. notes INTERLACED modes denotes 32K Direct Colour 256 colour Mixed Mode Shaded modes required 2MBytes of video memory fitted Video Drivers Blue Chip Technology provide drivers for a wide range of operating systems and popular applications Diskettes containing drivers required for DOS amp Windows are shipped with the DX board For other operating systems please contact Blue Chip Technology Video driver installation instructions To identify the type of video adapter present on your BCT DX1 CPU card From the MS DOS command line run IDCHIP EXE from the Display drivers amp utilities diskette to determine the video chipset in use Select either the 5424 or the 5428 9 MS Windows 3 1 Drivers diskette depending upon the type of chipset detected you will not require the other MS Windows 3 1 Drivers diskette Proceed to install the application drivers utilities and Windows drivers as required from the two remaining diskettes by running INSTALL EXE 01270173 doc Blue Chip Technology Ltd DX1 Peripheral Components Page 43 Watchdog Timer The DX1 is fitted with a simple hardware Watchdog function It can be enabled or disabled via software allowing the user to decide whether their application requires protection against potential processor failure or not The Watchdog is controlled as follows 0101 Write Only Bit 1 0 Disable Watchdog operation 1 Enable every SOOmS N operation
70. or Expansion adapters CBFFF C8000 Video BIOS Shadow BIOS C0000 640KB BFFFF 0000 9 Base Memory 00000 Blue Chip Technology Ltd 01270173 doc 48 DX1 Peripheral Components Disk Drives Floppy Drives The DX1 has built in support for two floppy disk drives These drives can be any permutation of the following 360KB 720KB 1 2MB 1 44MB 2 88MB The BIOS Set up allows you to configure the drives for your installation A standard PC 34 way ribbon cable with twisted lines can be connected to two drives both set as drive 1 as opposed to 0 This is possible because the IBM convention twists the drive select and motor control lines between the two drive connections Remember that only one drive in the chain should be terminated That should be the drive furthest from the DX1 Without correct termination drive operation can be unreliable In high noise environments it may be necessary to use shielded ribbon cable Do not extend the cable length beyond 1 metre 01270173 doc Blue Chip Technology Ltd DX1 Peripheral Components Page 49 Hard Drives IDE The BCT DX1 SBC provides support for two IDE hard disk drives The built in BIOS support allows each drive to be selected from 46 different drive types In addition type 47 can be configured specifically to your requirements for each of the two drives The built in Auto detection utility can be invaluable in providing an efficient way of establishing the
71. osecond period 14 31818 MHz This signal is not synchronous with the system clock It has a 50 duty cycle OWS D The Zero Wait State OWS signal tells the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles In order to run memory cycle to a 16 bit device without wait cycles OWS is derived from an address decode gated with a Read or Write command In order to run a memory cycle to an 8 bit device with a minimum of two wait states OWS should be driven active on system clock after the Read or Write command is active gated with the address decode for the device Memory Read and Write commands to a 8 bit device are active on the falling edge of the system clock 0WS is active Blue Chip Technology Ltd 01270173 doc 54 ISA amp VESA Bus Details low and should be driven with an open collector or tri state driver capable of sinking 20 mA Refresh I O This signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I O channel Reset Drive O Reset drive is used to reset or initialise system logic at power up time or when the power supply drops below its minimum level This signal is active high SAO through SA19 I O Address bits 0 through 19 are used to address memory and I O devices within the system These twenty address lines in addition to LA17 through LA23 allow access of up to 16MB of memory SAO through SAI9 are
72. pematic Rate Programming allows the auto repeat and delay before repeat to be selected The defaults are as shown above The Typematic Rate Delay describes the delay before auto repeat starts The Typematic Rate is the frequency of the key generation once in auto repeat Above 1 Memory Test By enabling this test any RAM above 1MB will be exercised by the POST diagnostics thereby taking longer to boot If your is not fitted with more than of RAM or you wish to shorten the boot time set this option to disabled If you wish to ensure maximum DRAM integrity then set this option to Enabled Memory Test Tick Sound This option selects whether an audible indication of the presence of memory during the POST is generated or not Once either lt ESC gt or DEL is depressed the audio is disabled Memory Parity Error Check This option selects whether the parity circuit is active on the system RAM We strongly recommend that this is set to enabled at all times thereby providing communication of any RAM corruption If this option is not required select disabled This option must be set if you are using SIMM units without parity bits i e 32 bits wide Hit DEL Message Display Disabling this option removes this message prompt from appearing during power up This may be required when you do not wish to draw attention to existence of the Setup Menus within the BIOS The default is enabled Blue Chip Technology Ltd 01270173 doc
73. pt 4 Disabled will remove the Interrupt connection Second Serial Port Address This option allows the second serial port address to be configured as either 02F8h Com2 O2E8h Com4 or Disabled The interrupt selection will be made automatically to Com 2 and 4 will be Interrupt 3 Disabled will remove the Interrupt connection Parallel Port Address This option allows the parallel port address to be configured as 03BCh LPT1 0378h LPT1 0278h LPT2 or Disabled The interrupt selection is made using J11 For LPT1 J11 should be set to across 1 2 Interrupt 7 For LPT2 J11 should be set to across 2 3 Interrupt 5 Blue Chip Technology Ltd 01270173 doc 36 BIOS Parallel Port Mode This option can be either Normal or Extended Normal setting is for standard printer operation Extended setting provides bi directional operation IRQ Active State This option can be set as either High or Low First Serial Port Mode The DX 1 provides software control of the serial port modes The settings can be RS232 or RS485 422 The power up condition of both serial ports is controlled by the BIOS Set up The default is RS232 Please note that RS485 connections for both the serial ports are made through a special connector P4 First Serial Port 485 Mode Once the serial mode is set to RS485 the port can be configured as either Half or Full duplex Half duplex is a 2 wire implementation whilst Full duplex is a 4 wire system The d
74. rom addressing conventional memory to addressing memory addresses above 1MB from real mode to protected mode and back Network operating systems in particular benefit from this enhanced circuitry Blue Chip Technology Ltd 01270173 doc 24 BIOS Password Checking Option This option enables a password check every time the systems boots or Set up is executed The settings are Always or Set up If Always is selected the user password prompt appears every time the system is turned If Set up 15 chosen the password prompt appears if Set up is executed ROM Shadow ROM shadow 1 a technique in which the BIOS code is copied from slower ROM to faster RAM The BIOS 1 executed from the For each of the areas of memory identified in the Set up table the option is there to Enable or Disable shadowing for that particular area The default is that both the Video and System areas are shadowed Care must be taken where expansion cards are occupying an area that 1 set for shadowing If the expansion card has its own internal RAM located at the address that is shadowed then its operation will be corrupted examples are network cards For such cards the setting should be Disabled Boot Sector Virus Protection When enabled the BIOS issues a warning when any program or Virus issues a Disk Format command or attempts to write to the boot sector of the hard disk The settings are Enabled or Disabled 01270173 doc Blue Chip Tec
75. s Super VGA controller This is achieved using one of the following Cirrus Logic video controllers CL GD5424 26 28 29 The chip used will depend upon your order specifications The Video Controllers provide the following features 100 hardware and software compatibility with IBM VGA display standards VESA Local Bus interface Hardware cursor up to 64 x 64 pixels Enhanced BLT Engine for GUI acceleration Resolutions up to 1280 x 1024 x 64K colours 2MB Video Memory required High performance Write Buffer architecture 1MByte Video Memory standard Order Time Option of 2MBytes of Video Memory avaiable Feature connector support 32 bit Display memory interface 132 column Text mode support Extensive drivers are available for DOS Windows 3 1 amp OS 2 0 Should you require to disable the on board video circuitry this can be achieved by setting J12 to position 1 2 DIS The analogue video output is presented on the condensed 15 way D type connector P7 located on the rear panel of the DX1 The feature connector P6 is a 26 way pin header located towards the top right corner of DX1 The following tables identify the video modes supported by the on board video controller and BIOS As well as describing the resolutions and colours offered by a mode it also presents the horizontal and vertical frequencies that will be presented to the attached monitor in the selected mode Please take great care to ensure that the selected
76. t Up screen in the BIOS Control Bit Control Bit Area Of Influence Bito 0 fulDupexCOM O FulDupexCOM2 Bi2 0 RS232modeCOM 0 RS232modCOM2 Port 104 hex 7 51413 2 1 0 232 485 232 485 COM 2F H COMI F H COM 2 COM 1 01270173 doc Blue Chip Technology Ltd DX1 Peripheral Components Page 45 Byte Wide SSD User Sockets The two 32 pin Bytewide user sockets can be used for SRAM or FLASH devices Each device is mapped into an 16K page in memory and a page register selects which 16K page within the device is currently accessible Socket 1 is mapped to memory address E000 0000 top socket Socket 2 is mapped to memory address E400 0000 bottom socket The page control register 15 located at port 102 Bits 0 4 of port 102 select one of 32 pages Bit 5 of port 102 enables the VPP for FLASH devices when SET There is also a device enable register at port 103Hex which will enable the memory decode for the user sockets BitO 0 Enable socket 1 E000 gt E3FF 1 disable socket 1 Bitl 0 Enable socket 2 E400 gt E7FF 1 disable socket 2 Bit2 0 Enable external SSD 800 gt 1 disable external SSD Blue Chip Technology Ltd 01270173 doc 46 DX1 Peripheral Components Battery The DX1 is fitted with an on board Lithium battery bottom left hand corner of DX board This battery provides power for the Real Time
77. ts the number of wait states inserted before all write operations to secondary cache memory The settings are 0 W S 1 W S or 2 W S The BIOS Set up default is 1 W S The Power On default is 2 W S DRAM Type This option specifies the type of DRAM used for system memory The settings are Page Mode or Fast Page DRAM Wait State s This option sets the number of wait states inserted before all DRAM system memory operations The settings are 0 W S 1 W S or 2 W S Keyboard Clock Select This option sets the source of the keyboard clock The settings are CPUCLK 6 CPUCLK 5 CPUCLK 4 CPUCLK 3 CPUCLK 2 9 5 MHz or 7 2 MHz 01270173 doc Blue Chip Technology Ltd BIOS Page 27 AT Clock Select This option sets the source of the AT Clock ATCLK The settings are CPUCLK 6 CPUCLK 5 CPUCLK 4 CPUCLK 3 CPUCLK 2 CPUCLK S or 7 2 MHz IO Recovery Time The settings are 0 0 BCLK 1 1 BCLK 2 2 3 3 5 2 7 3 BCLK 9 3 BCLK 12 3 BCLK 5 5 BCLK 7 7 BCLK 9 9 BCLK or 12 12BCLK Hold PD Bus The settings are 1 2 T or 2 3 T Refresh Cycle The settings are Slow or Fast Coprocessor READY This option sets the length of the delay of the coprocessor READY signal The settings are Delay 1T or No Delay Check ELBA Signal This option sets the length of the delay before the ELBA signal is checked The settings are in T1 or in T2 Non cacheable Block1 Enable Non cacheable Block2 Enable If disabled the cont
78. ugh 3 and 5 through 1 are used to acknowledge DMA requests DRQO through DRQ7 They are active low DRQ0 through DRQ3 and DRQ5 through DRQ7 D Requests 0 through 3 and 5 through 7 are asynchronous channel requests used by peripheral devices and the I O channel microprocessors to gain DMA service or control of the system They are prioritised with DRQO having the highest priority and DRQ7 having the lowest A request is generated by bringing a DRQ line to an active level A DRQ line must be held high until the corresponding DMA Request Acknowledge DACK line goes active DRQO through DRQ3 will perform 8 bit DMA transfers DRQS through DRQ7 will perform 16 bit transfers Blue Chip Technology Ltd 01270173 doc 52 ISA amp VESA Bus Details I O CHCK D I O channel check provides the system board with parity error information about memory or devices on the I O channel When this signal is active it indicates an uncorrectable system error CHRDY I T O channel ready is pulled low not ready by a memory or I O device to lengthen I O or memory cycles Any slow device using this line should drive it low immediately upon detecting its valid address and a Read or Write command Machine cycles are extended by an integral number of clock cycles This signal should be held low for no more than 2 5 microseconds I O CS16 1 I O 16 bit Chip Select signals the system board that the present data transfer is a
79. ules High performance memory Page Interleave access AMI BIOS with built in set up program Hardware EMS support LIM 3 2 amp 4 0 compatible Selectable Shadow RAM for system amp video BIOS Selectable Bus speed Automatic or Manual Peripheral Configuration Local bus SVGA controller with GUI accelerator and up to 2MB of video memory amp VESA VL bus connector On board optional solid state disk up to 2 MBytes of flash and 512K bytes of battery backed SRAM I D E controller 2 drives Floppy controller Intel 8272 compatible supporting 360KB 720KB 1 2MB 1 44MB amp 2 88MB drives 2 asynchronous serial ports 16C550 compatible software selectable as RS232C or 5485 selectable as either full or half duplex Bi directional parallel port AT compatible keyboard port PS 2 Mouse port check configuration Customer sign on information held in EEPROM POST header Software selectable Watchdog timer On board Power Good generation On board speaker with additional external drive circuitry Blue Chip Technology Ltd 01270173 doc 4 Specification e On board Lithium battery e layer PCB using Surface Mount Technology SMT The DX1 can support memory configurations from 1MB up to 64MB This is achieved by offering 4 72 pin SIMM carriers that can take modules in size from 256K x 36 bits data and 32 4 parity bits to 16 x 36 bits The DX board can also accommodate SIMM units without parity However please ens
80. ure that the BIOS is set correctly for this condition The following table shows the memory configurations supported by the DX1 Always ensure that you observe full static precautions before attempting to handle the DX1 and memory modules 01270173 doc Blue Chip Technology Ltd Specification Page 5 Memory Options Option Banko Banki Bank2 Bank3 Total DRAM 2 25K 26K 3 Jj 256 25K 25K 256K 256K pr s peces F o j 25K 256 256K Note The four banks are made up of four 72 pin SIMM carriers All SIMMs must have an access time of 70ns or faster e g 60ns All SIMMs modules quoted above are 32 bits wide 4 bytes SIMMs modules without parity can be used with the BIOS set accordingly Blue Chip Technology Ltd 01270173 doc 6 Specification Power Requirement The DX1 requires 5Vdc only The actual current consumption varies with configuration The following table should be used as a guideline to the total power requirement CPU Option Typical Current 4865 25 MHz 486DX 33 MHz 486DX2 66 MHz 486DX4 100 MHz Contact BCT All the above requirements are for DX1 configurations fitted with 4MB of DRAM Electromagnetic Compatibility This product meets the requirements of the European EMC Directive 89 336 EEC and is eligible to bear the CE mark It has been assessed operating in a Blue Chip Technology Icon industrial PC However becaus
81. ware parity check The settings are Enabled or Disabled Blue Chip Technology strongly advise that this is enabled to improve data integrity at all times when using SIMM units with parity bits i e 36 bits Blue Chip Technology Ltd 01270173 doc 34 BIOS Using the DX 1 Extended Set up The default condition for the DX 1 Extended Set up Menu is as shown below using the T4 keys you can select the parameter to be changed Once positioned on the parameter to be modified the lt PgUp gt and lt PgDn gt keys rotate the available options The value selected when the menu is exited is the one that will be written to CMOS should you decide to commit your changes to CMOS FRE QGREEBEE ERE BEEBE ERE RR ER EERE BEER EERE BEERS BRE BRS NES SES 25 6965 569 65 965 25 269 65 9265 65 96S 25 9 65 05 269 65 9S 25 9 6 25 0 SETUP PROGRAM DX1 SETUP 1993 American Megatrends Inc All Rights Reserved SE ERSE SEE ERE EBBEE DDB EBBECEREEDEE SDB E MBE DPE 9 Programming Option Auto On Board Floppy Drive Enabled e On Board IDE Drive Enabled First Serial Port Address 3F8H Second Serial Port Address 2F8H e 9 Parallel Port Address 378H IR Active State High Parallel Port Mode Normal First Serial Port Mode 85232 9 First Serial Port 485 Mode FULL
82. xt time BRDY is asserted the burst cycle will complete During VL Bus master transfers the VL Bus acting as bus master drives BLAST A VL Bus master that does not support burst transfers must drive this signal low whenever it controls the VL Bus 01270173 doc Blue Chip Technology Ltd ISA amp VESA Bus Details Page 59 ADS Address data Strobe During ISA DMA or ISA bus master transfers the VL Bus controller acts as the active host on behalf of the ISA bus ADS is strobed by the VL Bus controller for one clock cycle after the address bus and status lines are valid on the VL Bus During VL Bus master transfers ADS is strobed by the active VL Bus master for one clock cycle after the address and status lines are valid LEADS Local External Address Data Strobe The VL Bus controller or active VL Bus master asserts this signal whenever an address is present on the VL Bus that performs a CPU cache invalidation cycle A VL Bus master must drive this signal while it owns the bus LGNT Local Bus Grant LGNT is used in conjunction with LREQ to establish a VL Bus arbitration protocol When the VL Bus device asserts LREQ the VL Bus controller responds by asserting LGNT The active VL Bus device then has control of the bus and may own the bus until it no longer needs the bus or the VL Bus controller removes LGNT to preempt the active VL Bus master LKEN Local Cache Enable This signal is asserted if the current VL Bus cycle is

DX1 User Manual - Blue Chip Technology

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