MCF51MM Tower Story Hardware Specification
Contents
1. 10 4 6 SDRAM INTEREAGE eee rra _ _ 11 4 7 NAND FLASH 11 4 8 ACCELEROMETER 11 4 9 37737333 22 12 4 10 TEMPERATURE SENSOR lessen 13 4 11 AUDIO HEADERS m eee 13 4 12 USER INTERFACES eren rne aal eee 13 4 13 RESET CONFIGURATION senno oo oo 14 4 13 1 Default Configuration J5 3 4 and 1 2 15 4 13 2 Parallel Configuration 75 3 4 1 2 16 4 13 3 Serial Configuration 75 OFF OFF generet tenete nennen netten nenne 17 4 14 JUMPERS SWITCHES ccccccccccecssssssececececessnnaececececsensaeseecceceeseseeecececseneseaesececsesessaaeseeececeesasececececsesaaeseeeceesensaseeeeeeees 20 4 15 CUT TRACE PADS llt 21 MCF5441X Tower Mod2. Function i Function n n 1 No Connect 2 No Connect 3 TXD 4 CTS 5 RXD 6 RTS 7 No Connect 8 No Connect 9 GND 10 3 3V Table 6 J1 amp J3 4 6 SDRAM Interface The MCF5441x is capable of supporting 256MB DDR2 500 1 8V SDRAM at 250MHz SDRAM Clock To reduce cost the TWR M54418 uses an 8 bit memory bus to interface to 128MB Micron MT47H128M8 DDR2 SDRAM 4 7 NAND Flash Memory Interfaces The TWR M54418 uses a 16 bit 2Gbit 48 pin TSOP NAND Flash device MT29F2G164A The NAND Flash device may uses up to 256MB 2048 blocks at 64 pages per block The first four pages of block 0 may use for boot code with an 8 bit bus interface The NAND signals are shared with FlexBus signals Pin Assignments must be set correctly for access to work properly for each Mode NAND or FlexBus The MCF5441x is capable of booting from NAND Flash Memory device 4 8 Accelerometer An MMA7361L accelerometer is connected to three ADC inputs There are 4 GPIO signals used to configure the MMA7361L that are optional on the TWR MCF5441X The MMA7361L is wired as shown here as recommended in the MMA7361L Data Sheet POWER SUPPLY Logic Input 9 g Select Og Detect gt 13 Logic Self Test 2 Vpp Input Xout MMA7361L 3 3 nF r Vpp g Select P1 Og Detect P2 Y bid Self Test Accelerometer Microcontroller MCF5441X Tower Module Hardware Specification Page 11 of 31 freesc
3. freescale 5441 Tower Module User Manual Rev 1 1 Freescale Semiconductor Inc Microcontroller Solutions Group e gt e 2 freescale semiconductor Contents 1 PURPOSE E 3 2 REFERENCE 0 01 8 BL D On E Ec M 3 3 OVERVIEW e 3 e sucess Sead dE Eee dc Gees 3 3 22 TWR MCES4ATX OVERVIEW 0 5 4 HARDWARE SPECIFICATION vscssiscsssssnscsssissocessesssstcacesesscssentsdantccvessseseovecssssaecsenssosessecsedasnsvsoesssecesseassnoscsstssssccesests 6 4 1 6 AD 7 4 SYSTEM POWE R 8 4 4 DEBUG INTERFACE 8 4 4 1 Stardard 8 4 4 2 OSBDM Bootloader MOU ce 10 4 4 3 OSBDM Debug Imena e 1 10 4 5 RS232 HEADERS 2 gt
4. CAN ADC DAC mcPWM etc 32 768 kHz RTC 25 MHz RefCIk SDRAM Interface 26 Pin Header Reset GPIO ADC Temp Sensor Speaker DS18B20 Header E Freescale Silicon External Connectors Memory Devices Interface ICs Power Rails 4 2 Clocking The MCF54418 requires 2 clocks sources in order to enable proper internal timing A 25 MHz crystal is connected to EXTAL to generate several clocks including the CPU clock and peripherals clock The EXTAL can also use a 50MHz clock from the Tower Elevator selected via jumper J2 A 32 768 kHz crystal is connected to RTC_XTAL and RTC_EXTAL for Real Time Clock usage Clock Selection Pin External clock source 1 2 Onboard 25Mhz clock 2 3 Table 1 J2 Headers The MCF54418 s core clock speed is default to 250 MHz on the TWR MCF54418 platform The DDR2 SDRAM bus speed is set at 250 MHz to generate a 500 MHz data rate The system bus clock is set at 125MHz All clock speeds such as CPU SYSTEM SDHC USB and be programmable to desire frequency with software modification and jumpers MCF5441X Tower Module Hardware Specification Page 7 of 31 freescale semiconductor To fully support the DDR2 interface a VCO of 500 MHz is required In order to supply a VCO of 500MHz the clock multiplier should be adjusted based on the input reference clock Clock Source PLL Multiplier SW1 Dip 7 8 settings 50MHz 10x 0 0 On On 25MH
5. B59 IRQ D Interrupt PC3 IRQ3 x B60 IRQ C Interrupt PC3 IRQ3 x B61 IRQ B Interrupt PC2 IRQ2 x B62 IRQ Interrupt PC1 IRQ1 x B63 ALE FB CS1 b Flexbus PA7 FB_ALE x B64 FB_CS0_b Flexbus PB3 FB_CSO X B65 GND Power Ground X B66 FB_AD15 Flexbus FB_AD15 X B67 FB_AD16 Flexbus FB_AD16 NFC_IOO x B68 FB_AD17 Flexbus FB_AD17 NFC_IO1 x B69 FB AD18 Flexbus FB AD18 NCF IO2 x B70 FB_AD19 Flexbus FB_AD19 NFC_IO3 x B71 FB_R W_b Flexbus PA5 FB RW NFC WE x B72 FB_OE_b Flexbus PA6 FB_OE NFC_RE x B73 FB_D7 Flexbus FB_AD31 x B74 FB_D6 Flexbus FB_AD30 x B75 FB D5 Flexbus FB AD29 x B76 FB_D4 Flexbus FB_AD28 x B77 FB_D3 Flexbus FB_AD27 x B78 FB_D2 Flexbus FB_AD26 x B79 FB Flexbus FB AD25 x B80 FB_DO Flexbus FB_AD24 x B81 GND Power Ground X B82 3 3V Power 3 3V Power X MCF5441X Tower Module Hardware Specification Page 26 of 31 z freescale semiconductor gt e TWR MCF5441X Secondary Connector Side C Group Used Ci 5V Power 5 0V Power X C2 GND Power Ground x C3 3 3V Power 3 3V Power 3 3V Power 3 3V Power X C5 GND Power Ground x C6 GND Power Ground x C7 SCL2 I2C2 C8 SDA2 12C 2 C9 GPIO25 GPIO C10 USB STOP ULPI ULPI_STP x 11 USB ULPI USB_CLKIN x C12 GPIO GPIO C13 MDC Ethernet RMII1 MDC x C14 ETH MDIO Ethernet RMII1 MDIO x 15 ETH_RXCLK Ethernet
6. CT7 CT12 CT4 and CT10 Using a solder iron create a connection between pads 1 and 3 Note that it is not possible to disconnect the default signals routing PST 3 0 for the these signals they are used for OSBDM functionality For more details regarding the Cut Trace pad options and the pad numbering refer to the Cut Trace Pad section of this document 4 9 Potentiometer The TWR MCF5441X includes an on board potentiometer to allow the user to simulate an analog input MCF5441X Tower Module Hardware Specification Page 12 of 31 ey freescale semiconductor By default voltage level from the potentiometer is connected to the ADC channel 4 of the MCF54418 If desired the connection to the potentiometer can be disconnected and the ADC channel of the MCF54418 can be connected to the edge connectors for use on a module connected to the TWR ELEV To change the connection of ADC 4 use the Cut Trace pad CT14 Using a tool with a razor blade tip sever the connection between the pads 1 and 2 of the CT14 Using a solder iron make a connection between pad 1 and pad 3 For more details regarding the Cut Trace pad options and the pad numbering refer to the Cut Trace Pad section of this document 4 10 Temperature Sensor TWR M54418 uses 1 wire interface OWIO to interact with temperature sensor Maxim DS18B20 digital thermometer The sensor device is powered from TWR MCF5441X s 3 3V power circuit The Parasite Powered method wher
7. Ethernet PJ3 RMIIO TXD1 x B20 ETH_TXDO Ethernet PJ2 RMIIO TXDO x B21 GPIO1 RTS1 GPIO UART PG2 RGPIO x B22 GPIO2 SDHC1_D1 GPIO SDHC1 PFO SDHC dat 1 X B23 GPIO3 GPIO B24 CLKINO Clock RMII_REF_CLK x x B25 CLKOUT1 Clock B26 GND Power Ground X B27 AN7 ADC B28 AN6 ADC ADC_IN6 x B29 5 ADC ADC_IN5 x B30 AN4 ADC ADC_IN4 x x B31 GND Power Ground X B32 DAC1 DAC B33 TMR3 Timer B34 TMR2 Timer B35 GPIO4 GPIO PB6 GPIO x B36 3 3V Power 3 3V Power X B37 PWM7 PWM B38 PWM6 PWM B39 PWM5 PWM PG7 PWM_B2 x B40 4 PWM 2 x B41 CANRX CAN PC7 CAN1_RX x MCF5441X Tower Module Hardware Specification Page 25 of 31 2 freescale semiconductor gt 524 TWR MCF5441X Primary Connector Side B Group Usage B42 CANTX CAN 1 x B43 1WIRE 1 Wire B44 SPIO_MISO SPI 0 PD5 DSPIO_SIN SBF_DI x B45 SPIO_MOSI SPI 0 PD4 DSPIO SOUT SBF DO x B46 SPIO_CSO SPI 0 PD7 DSPIO 50 55 X B47 SPIO_CS1 SPI 0 PCO DSPIO PCS1 BSF CS X B48 SPIO_CLK SPI 0 PD6 DSPIO SCK SBF CK x B49 GND Power Ground x B50 SCL1 12 1 PEO I2C5 SCL x B51 SDA1 I2C1 7 12 5 SDA x B52 GPIO5 GPIO PG3 RGPIO x B53 USB_DP_PDOWN USB PI6 x B54 USB_DM_PDOWN USB PI7 x B55 IRQ H Interrupt PC6 IRQ7 x B56 IRQ G Interrupt PC6 IRQ7 X B57 IRQ F Interrupt PC4 IRQ4 x B58 IRQ E Interrupt PC4 IRQ4 x
8. details on the USB Bootloader refer to Application Note AN3561 on the Freescale website http www freescale com The USB Bootloader communicates with a GUI application running on a host PC The GUI application can be found on the Freescale website search keyword JM60 GUI Refer to section 2 5 and 3 3 of AN3561 for details on installing and running the application Note The JM60 GUI Installer should be run before connecting the OSBDM in Bootloader Mode to a host USB port Otherwise the JM60 USB device will not be recognized and the proper drivers will not be loaded 4 4 3 OSBDM Debug Interface The OSBDM circuit is designed so that it can program the on board MCF54418 device The steps necessary to operate the OSBDM in this mode are listed here 1 Ensure that J10 is not shunted J10 holds JM60 in reset 2 Connect J7 2x3 header from TWR MCF54418 to target debug connector Pi Function i Function n 1 BKDG MS 2 5V 3 NC 4 RESET_b 5 NC 6 5V Table 5 J7 JM60 BKGD Headers 4 5 RS232 Headers MCF54418 includes ten UART modules The TWR M54441X provides two RS232 transceivers on UARTO UART4 Two 2x5 pin headers are provided allowing access to the RS232 interfaces J1 UARTO and J3 UART4 A 2x5 adaptor to Female DB9 serial cable must be used in order to establish serial communication MCF5441X Tower Module Hardware Specification Page 10 of 31 2 freescale semiconductor
9. semiconductor J5 BOOTMOD 1 0 3 4 1 2 Description 00 ON ON Boot from Flexbus with default RCON 01 override default via data bus FB_AD 7 0 NAND FlexBus The is the typical boot mode for the TWR MCF5441X 10 OFF ON Override default and boot from serial boot facility with load configuration and optional booting from internal SRAM If not booting from internal SRAM serial RCON configuration will decide the boot source at address O either from FlexBus or NAND Flash Table 9 J5 Headers 11 OFF OFF 4 13 1 Default Configuration J5 3 4 and 1 2 ON ON If the BOOTMOD pins are 00 during reset the MCF5441x s RCON register determines the chip configuration after reset regardless of the states of the external data pins The RCON register specifies the following default configuration for the MCF5441x VCO clock is 50 MHz CPU clock at 25 MHz e System bus clock is 12 5 MHz FlexBus clock is 6 25 MHz MCF5441X Tower Module Hardware Specification Page 15 of 31 ey freescale semiconductor 4 13 2 Parallel Configuration J5 3 4 and 1 2 ON OFF If the BOOTMOD pins are 01 during reset the MCF5441x configuration after reset is determined according to the levels driven onto the FB_AD 7 0 pins On the TWR MCF5441X the FB AD 7 0 pins are actively driven by two 4 bit buffers enabled when the MCF5441x RSTOUT signal is asserted The values driven by the buffer are set by the SW1 DIP s
10. 3 Connect GPIO to LED 1 CT14 ADC 4 1 2 Connects Potentiometer to ADC 4 1 3 Connects ADC 4 to TWR ELEV AN4 CT15 OWIO 3 4 Connects OWIO to on board 1 3 4 Connects OWIO to temperature sensor GPIO PD3 temperature sensor and allows additional One Wire to be connected via TWR ELEV 1 2 4 Connect s GPIO PD3 to CAN Silent Mode pin on TWR ELEV MCF5441X Tower Module Hardware Specification Page 22 of 31 2 freescale semiconductor e gt oe s Tower Elevator Connections TWR MCF5441X Primary Connector Side A Group Usage Used 1 5V Power 5 0V Power X A2 GND Power Ground X A3 3 3V Power 3 3V Power X A4 ELE_PS_SENSE Power Elevator Power Sense X A5 GND Power Ground x A6 GND Power Ground x A7 SCLO 12C 0 PB2 I2CO SLC x 8 SDAO 12C 0 1 2 0 SDA x 9 GPIO9 CTS1 GPIO UART PGO RGPIO x A10 GPIO8 SDHC_D2 GPIO SDHC1 PF1 SDHC dat 2 x 11 GPIO7 SD_WP_DET GPIO SD SDHC1 PG4 RGPIO SDHC_write_protect x 12 5 Ethernet A13 ETH MDC Ethernet PI1 RMIIO MDC x 14 Ethernet PIO RMIIO MDIO x 15 ETH_RXCLK Ethernet 16 ETH_RXDV Ethernet PJ7 RMIIO CRS DV x 17 ETH_RXD3 Ethernet A18 ETH_RXD2 Ethernet 19 ETH_RXD1 Ethernet PJ6 RMIIO RXD1 x A20 ETH_RXDO Ethernet PJ5 RMIIO RXDO x A21 SSI_MCLK SSI 4 5510 MCLK x A22 SSI_BCLK SSI PH3
11. C16 ETH RXDV Ethernet RMIIi CRS DV x C17 GPIO GPIO C18 GPIO GPIO C19 RXD1 Ethernet RMII1 RXD1 x C20 ETH RXDO Ethernet RMII1 RXDO x C21 USB DATAO ULPI ULPI_DATAO x C22 USB DATA1 ULPI ULPI DATA1 x C23 USB_DATA2 ULPI ULPI_DATA2 x C24 USB_DATA3 ULPI ULPI_DATA3 x C25 USB DATA4 ULPI ULPI_DATA4 x C26 GND Power Ground 27 11 ADC C28 AN10 ADC C29 AN9 ADC C30 AN8 ADC C31 GND Power Ground X C32 GPIO GPIO C33 TMR9 Timer C34 TMR8 Timer C35 GPIO GPIO C36 3 3V Power 3 3V Power 37 PWM11 PWM C38 PWM10 PWM C39 PWM9 PWM C40 PWM8 PWM C41 RXD2 UART 2 PE4 UART2_RXD x x MCF5441X Tower Module Hardware Specification Page 27 of 31 z freescale semiconductor e gt e TWR MCF5441X Secondary Connector Side C Group Usage C42 TXD2 UART 2 PE3 UART2_TXD x x C43 RTS2 UART 2 5 2 5 x x C44 CTS2 UART 2 PE6 RGPIO UART2_CTS x x 45 RXD3 UART 3 C46 TXD3 UART 3 C47 RTS3 UART 3 C48 CTS3 UART 3 C49 GND Power Ground X C50 LCD D4 LCD4 Display C51 LCD D5 LCD5 Display C52 LCD D6 LCD6 Display C53 LCD D7 LCD7 Display C54 LCD D8 LCD8 Display C55 LCD 9 LCD9 Display C56 LCD D10 LCD10 Display C57 LCD D11 LCD11 Display C58 TMR16 Timer C59 TMR15 Timer C60 TMR14 Timer C61 TMR13 Timer C62 LCD D15 LCD15 Display C63 LCD D16 LCD16 Display
12. C64 LCD D17 LCD17 Display C65 GND Power Ground X C66 FB BE3 LCD28 Flexbus Display C67 FB BE2 LCD29 Flexbus Display C68 FB BE1 LCD30 Flexbus Display C69 FB BEO LCD31 Flexbus Display C70 FB TSIZEO LCD32 Flexbus Display PAO FB TSIZ 0 x C71 FB_TSIZE1 LCD33 Flexbus Display PA1 FB_TSIZ 1 x C72 FB TS LCD34 Flexbus Display C73 FB TBST LCD35 Flexbus Display C74 TB TA LCD36 Flexbus Display C75 FB CS4 LCD37 Flexbus Display C76 FB CS3 LCD38 Flexbus Display C77 FB CS2 LCD39 Flexbus Display C78 FB CS1 LCD40 Flexbus Display C79 GPIO LCD41 GPIO C80 LCD D23 LCD23 Display C81 GND Power Ground C82 3 3V Power 3 3V Power MCF5441X Tower Module Hardware Specification Page 28 of 31 2 freescale semiconductor gt e 2 TWR MCF5441X Secondary Connector Side D Group Used Di 5V Power 5 0V Power X D2 GND Power Ground x D3 3 3V Power 3 3V Power X D4 3 3V Power Elevator Power Sense x 05 GND Power Ground x D6 GND Power Ground x D7 SPI2 CLK SPI2 D8 SPI2 CS1 SPI2 D9 SPI2 CSO SPI2 D10 SPI2 MOSI SPI2 011 SPI2_MISO SPI 2 012 ETH_COL Ethernet 013 ETH_RXER Ethernet RMII1_RXER x 014 ETH_TXCLK Ethernet 015 _ Ethernet RMII1_TXEN x 016 017 PHO DIP Switches x 018 PH1 DI
13. DM control signals and are available on J11 The JTAG_EN input signal to the MCF5441x determines the debug mode BDM or JTAG This signal is controllable by J6 as shown below Debug Mode Pin JTAG No shunt BDM Shunt on 1 2 Table 3 J6 Headers The TCLK and PSTCLK signals are the only two multiplexed signals that switch input output state depending on which debug mode is selected In BDM mode the PSTCLK is an output from the MCF5441x to the external BDM control interface In JTAG mode TCLK is the test clock input The standard 26 pin BDM header defines pin 24 as PSTCLK A common practice is to place TCLK on pin 6 of this header J8 is available to control the routing of the multiplexed TCLK_PSTCLK signal to the 26 pin debug header J11 as shown below TCLK_PSTCLK Routing Pin TCK PSTCLK on J11 pin 24 1 2 TCK PSTCLK on J11 pin 6 2 3 Table 4 J8 Headers MCF5441X Tower Module Hardware Specification Page 9 of 31 freescale semiconductor 4 4 2 OSBDM Bootloader Mode The MC9S08JM60 device used in the OSBMD circuit is preprogrammed with OSBDM debugger firmware and a USB Bootloader Jumper J10 determines which application will run following a power on reset If Bootloader Mode is chosen Jumper ON J10 the bootloader will executed allowing in circuit reprogramming of the JM60 flash memory via USB This enables the OSBDM firmware to be upgraded by the user when upgrades become available For
14. P Switches x D19 ETH_TXD1 Ethernet RMII1_TXD1 x D20 ETH_TXDO Ethernet RMII1_TXDO x D21 ULPI_NEXT ULPI PE7 RGPIO ULPI_NXT x D22 USB_DIR ULPI PD2 RGPIO ULPI_DIR x D23 USB DATA5 ULPI ULPI DATAS x D24 USB_DATA6 ULPI ULPI_DATA6 x D25 USB_DATA7 ULPI ULPI_DATA7 x D26 GND Power Ground x D27 LCD_HSYNC LCD24 Display D28 LCD_VSYNC LCD25 Display D29 AN13 ADC D30 AN12 ADC D31 GND Power Ground x D32 LCD_CLK LCD26 Display D33 TMR11 Timer D34 TMR10 Timer D35 GPIO GPIO D36 3 3V Power 3 3V Power 037 PWM15 PWM D38 PWM14 PWM D39 PWM13 PWM D40 PWM12 PWM D41 CANRX1 CAN MCF5441X Tower Module Hardware Specification Page 29 of 31 z freescale semiconductor e gt e TWR MCF5441X Secondary Connector Side D Group D42 CANTX1 CAN D43 GPIO GPIO D44 LCD_OE LCD27 Display D45 LCD DO LCDO Display D46 LCD LCD1 Display D47 LCD_D2 LCD2 Display D48 LCD_D3 LCD3 Display D49 GND Power Ground x D50 GPIO GPIO 051 052 LCD_D12 LCD12 Display D53 LCD_D13 LCD13 Display D54 LCD_D14 LCD14 Display D55 IRQ P Interrupt D56 IRQ O Interrupt D57 Interrupt D58 IRQ M Interrupt D59 IRQ L Interrupt D60 IRQ K Interrupt D61 IRQ J Interrupt D62 IRQ I Interrupt D63 LCD D18 LCD18 Display D64 LCD D19 LCD19 Display D65 GND Power Gro
15. SSIO_BCLK x A23 SSI_FS SSI PH5 SSIO FS x A24 SSI_RXD SSI PH7 SSIO RXD x A25 SSI_TXD SSI 6 5510 TXD x A26 GND Power Ground x A27 AN3 ADC ADC_IN3 DACO_OUT x x A28 AN2 ADC ADC_IN2 x x A29 AN1 ADC ADC_IN1 x x A30 ANO ADC ADC_INO x x A31 GND Power Ground x A32 DACO DAC A33 TMR1 Timer PD1 RGPIO T21IN T2OUT x A34 TMRO Timer PDO RGPIO T11IN T1OUT x 5 GPIO6 GPIO PB5 GPIO x A36 3 3V Power 3 3V Power A37 PWM3 PWM PF1 PWM B1 x A38 PWM2 PWM PF2 PWM A1 x A39 PWM1 PWM PG6 PWM_BO x A40 PWMO PWM PG5 PWM 0 x MCF5441X Tower Module Hardware Specification Page 23 of 31 z freescale semiconductor e gt oe TWR MCF5441X Primary Connector Side A Group Usage Used A41 RXDO UART 0 PE5 RGPIO UART6_RXD x x A42 TXDO UART 0 PE6 RGPIO UART6_TXD x x A43 RXD1 UART 1 PE1 RGPIO UART5 RXD x X A44 TXD1 UART 1 PE2 RGPIO UART5_TXD X x 45 A46 GPIO GPIO A47 GPIO GPIO A48 GPIO GPIO A49 GND Power Ground x 50 GPIO GPIO 51 GPIO A52 GPIO GPIO 53 GPIO GPIO 54 USBO DM USB 0 USBO DM x 55 USBO DP USB 0 USBO DP x 56 USBO ID USB 0 A57 USBO VBUS USB 0 58 TMR7 Timer 59 TMR6 Timer A60 TMR5 Timer A61 TMR4 Timer A62 RSTIN_b Reset RESET x 63 RSTOUT_b Reset RSTOUT x 64 CLKOUTO Clock PB7 FB_CLK x A65 GND P
16. ale semiconductor Figure 1 MMA7361L Connection Diagram By default the control signals are not connected but can be enabled using Cut Trace pads By default the MMZ7361L is configured to operate in normal mode with 1 58 sensitivity and no self test functionality The MMA7361L Accelerometer is connected as follows to the MCF54418 MPU Configuration Accelerometer MCF54418 Pad ADC_INO CT3 Yout ADC_IN1 CT6 Zout ADC_IN2 CT9 g Select PST O GPIO2 CT7 nSleep PST 1 GPIO3 CT12 Self Test PST 2 GPIO4 CT4 Og Detect PST 3 GPIO5 10 Table 7 Accelerometer Connection to MCF54418 By default the analog signals from the accelerometer are connected to the ADC channels 0 2 of the 54418 If desired the connection to the accelerometer can be disconnected and the ADC channels of the MCF54418 be connected to the edge connectors for use on a module connected to the TWR ELEV To change the connection of ADC O 1 and 2 use the Cut Trace pads CT3 CT6 and CT9 respectively Using a tool with a razor blade tip sever the connection between the pads 1 and 2 of each required Cut Trace implementation Using a solder iron make a connection between pad 1 and pad 3 By default the control signals for the MMA7361L accelerometer are not connected to the MCF54418 To change the connection of the control signals G Select nSleep Self Test and Og Detect use the respective Cut Trace pads
17. e 11 Serial Boot Facility 7 BYTE Header MCF5441X Tower Module Hardware Specification Page 17 of 31 e P freescale semiconductor Override Serial RCON Function SBF RCON 31 30 BOOT Port size 00 32 bit 32 bit muxed address 01 8 bit 24 bit non muxed address 10 16 bit 16 bit non muxed address 11 16 bit 16 bit non muxed address SBF RCON 29 Boot Memory 0 NAND Flash 1 FlexBus SBF RCON 28 27 Reserved RCON 26 FB ALE select 0 FB TS 1 FB ALE SBF RCON 25 Oscillator mode 0 Crystal oscillator mode 1 Oscillator bypass mode RCON 24 PLL mode 0 Disabled 1 Enabled SBF RCON 23 22 PLL Reference Divider CR REFDIV 00 1 01 2 Override Serial RCON Function 10 Reserved 11 Reserved SBF_RCON 21 16 PLL reference Clock Multiplier PLL_CR FBKDIV SBF_RCON 15 FlexBus Half Clock Enable 0 FlexBus Runs at Fsys 2 1 FlexBus Runs at Fsys 4 SBF RCON 14 10 NFC Clock Frequency PLL DR OUTDIV5 5 RCON 9 5 Internal Bus Clock Frequency PLL DR OUTDIV5 SBF RCON A 0 Core Bus Clock Frequency DR OUTDIV5 Table 12 Serial Boot Facility RCON Bit Definitions MCF5441X Tower Module Hardware Specification Page 18 of 31 freescale semiconductor The value of BLL 15 0 of serial boot header 7 byte will determine whether t
18. e the power source is from data bus is not used in this platform By default the One Wire digital temperature sensor is connected to the OWIO port on the MCF54418 Using Cut Trace pad CT15 the signal can be connected to the TWR ELEV connector for connection to additional One Wire devices This signal can also be used to control the operating mode of a CAN transceiver on an external Tower System module For the CAN use case the will be configured as a GPIO and should be disconnected from any One Wire devices To disconnect the signal from the on board temperature sensor cut the trace between pads 1 and 2 of CT15 For more details regarding the Cut Trace pad options and the pad numbering refer to the Cut Trace Pad section of this document 4 11 Audio Headers DAC The TWR MCF5441X uses National Semiconductor LM4889 Audio Power Amplifier to drive signal from DAC1 OUT up to 1W into an 8Q speaker 1 Output 2 Output Table 8 J4 Headers 4 12 User Interfaces e Three push buttons MCF5441X Tower Module Hardware Specification Page 13 of 31 freescale semiconductor IRQ1 SW3 o IRQ2 SW5 o MCUreset SW2 e One 8 way DIP switch for controlling Parallel Reset Configuration e One 2 way DIP Switch for additional GPIOs Assuming BDM DDATA 3 2 are disabled Four LEDs driven directly by MPU output pins The LEDs are concurrently connected to the LED s and the edge connector for GPIO access to ex
19. he code will continue to load from SPI memory at offset 7 to internal SRAM and boot from internal SRAM If the value of BLL 15 0 is cleared the serial boot facility will not continue to access SPI memory after offset 6 Instead it will depend on the SBF_RCON bit 29 to determine whether the code will continue to load at address 0 either from FlexBus or NAND flash N gt io o a ie TA uj a o ea gt 9 c o O o o E 4 O o 5 no c O 2 e e e N N N N N N E x x 2 5 9 x 9 T3 o z oz 5 S 9 I Soo 2 wn L 76 ke zn 5 2 35 zm 9 a gt gt o a 2 2 2 rm Zoo e Oa n t Mm o ai N Table 13 Easy Configurable Serial RCON MCF5441X Tower Module Hardware Specification Page 19 of 31 2 freescale semiconductor 4 14 Jumpers Switches The TWR MCF5441X implements a number of configuration jumpers switches and headers Refer to this section for a quick overview of each For more details refer to the specific section related to the functionality of the specific jumper switch or header Jum
20. lternate Sink Trace Cut Pad Dual Mode Connection Figure 2 Cut Trace Pad Details MCF5441X Tower Module Hardware Specification Page 21 of 31 e 22 freescale semiconductor The TWR MCF5441X implements the following Cut Trace pads Function Primary Setting Alternative Setting CT1 UART5 TXD 1 2 Connects TXD to TWR ELEV 1 3 Connects TXD to JM60 CT2 5 RXD 1 2 Connects RXD to TWR ELEV 1 3 Connects RXD to JM60 CT3 ADC 0 1 2 Connects Accelerometer 1 3 Connects ADC 0 to TWR ELEV ANO X axis to ADC 0 5 2 5 2 is connected to PST2 redundant 1 3 Connects PST2 to Accelerometer Self_Test connection CT5 GPIO PG3 1 2 Connects GPIO to TWR ELEV 1 3 Connect GPIO to LED 4 CT6 ADC_1 1 2 Connects Accelerometer 1 3 Connects ADC_1 to TWR ELEV AN1 Y axis to ADC_1 CT7 PSTO PSTO is connected to PSTO redundant 1 3 Connects PSTO to Accelerometer G Select connection CT8 GPIO PG2 1 2 Connects GPIO to TWR ELEV 1 3 Connect GPIO to LED 3 CT9 ADC 2 1 2 Connects Accelerometer 1 3 Connects ADC 2 to TWR ELEV AN2 Z axis to ADC 2 CT10 PST3 PST3 is connected to PST3 redundant 1 3 Connects PST3 to Accelerometer Og connection Detect 11 GPIO PG1 1 2 Connects GPIO to TWR ELEV 1 3 Connect GPIO to LED 2 12 PST1 PST1 is connected to PST1 redundant 1 3 Connects PST1 to Accelerometer nSleep connection CT13 GPIO PGO 1 2 Connects GPIO to TWR ELEV 1
21. nal SRAM Support for booting from SPI compatible flash Support for booting from NAND flash Crossbar switch technology XBS for concurrent access to peripherals or RAM from multiple bus masters 64 channel DMA controller DDR1 DDR2 Controller USB 2 0 On the Go controller with ULPI support Two smart card ports Two 10 100 Ethernet Controllers IEEE 1588 2002 SDHC host controller Two CAN modules Cryptographic acceleration unit CAU Random number generator Synchronous serial interface SSI Four 32 bit timers with DMA support Four DMA supported serial peripheral interface DSPI Ten UARTs Six DC bus interface 12 bit ADC A multi channel PWM Two DACs MCF5441X Tower Module Hardware Specification Page 4 of 31 gt freescale semiconductor ADC NIC Background debug module JTAG Joint Test Acton Group intertace CAU Cryptography acceleration unit mcPWM Motor control pulse modulator DAC PIT timers DSPi serial peripheral Interface PLL Phase locked loop module eDMA Enhanced direct memory access module RGPIO GPIO eSDHC Enhanced Secure Digital host controller RNG Random number generator X Enchance unit RTC Real time clock EPORT Edge port module interface GPIO General purpose input output module USB Universal Serial Bus On the Go controller Inter intergrated Circ
22. ower Ground X A66 FB_AD14 Flexbus FB_AD14 X A67 FB_AD13 Flexbus FB_AD13 x A68 FB_AD12 Flexbus FB_AD12 x A69 FB_AD11 Flexbus FB_AD11 x A70 FB_AD10 Flexbus FB_AD10 x A71 FB_AD9 Flexbus FB_AD9 x A72 FB AD8 Flexbus AD8 x A73 FB_AD7 Flexbus FB_AD7 x A74 FB_AD6 Flexbus FB_AD6 x 75 FB_AD5 Flexbus FB_AD5 x A76 FB_AD4 Flexbus FB_AD4 x A77 FB_AD3 Flexbus FB_AD3 x A78 FB_AD2 Flexbus FB_AD2 x A79 FB_AD1 Flexbus FB_AD1 x 80 FB_ADO Flexbus FB_ADO x 81 GND Power Ground x A82 3 3V Power 3 3V Power MCF5441X Tower Module Hardware Specification Page 24 of 31 2 freescale semiconductor e gt e s TWR MCF5441X Primary Connector Side B Group Usage 1 5V Power 5 0V Power Xx B2 GND Power Ground X B3 3 3V Power 3 3V Power X B4 ELE_PS_SENSE Power Elevator Power Sense X B5 GND Power Ground X B6 GND Power Ground X B7 SPI1_CLK SDHC1_CLK SPI 1 SDHC1 PG5 SDHC x B8 SPI1_CS1 SDHC1_CS1 SPI 1 SDHC1 9 SPI1_CSO SDHC1 CSO SPI 1 SDHC1 PF2 SDHC_dat 3 x B10 SPI1_MOSI SDHC1_CMD SPI 1 SDHC1 PG6 SDHC_cmd X B11 SPI1 MISO SDHC1_DO SPI 1 SDHC1 PG7 SDHC_dat 0 X B12 ETH_COL Ethernet B13 ETH_RXER Ethernet PJ4 RMIIO RXER x B14 ETH_TXCLK Ethernet B15 ETH_TXEN Ethernet PJO RMIIO TXEN x B16 ETH_TXER Ethernet B17 ETH_TXD3 Ethernet B18 ETH_TXD2 Ethernet B19 ETH_TXD1
23. pers Description Header J1 UARTO Header 12 Clock Source 25Mhz External Jumper J4 Audio Speaker Header J5 Boot Mode Jumpers J6 BDM JTAG mode Jumper 17 JM60 BKGD MS Header J8 TCK PSTCLK_OSBDM Jumper 19 USB Mini OSBDM PWR J10 JM60 IRQ Boot Mode Jumper 111 26 BDM Header J12 MCU Reset Jumper J13 Primary Elevator Connection J14 Secondary Elevator Connection Table 14 Jumpers Headers Summary Switches Description Pushbuttons SW1 RCON Boot Settings Switch for BOOTMOD 01 SW2 MCU Reset Push Button SW3 IRQ1 Push Button SW4 User Input Switch GPIOHO GPIOH1 SW5 IRQ2 Puch Button Table 15 Switches Push Buttons Summary MCF5441X Tower Module Hardware Specification Page 20 of 31 e 22 e z freescale semiconductor 4 15 Cut Trace Pads Cut Trace pads have been implemented on the TWR MCF5441X in place of configuration jumpers to ease board area constraints Physical Implementation Schematic View Default Source Default Sink 2 1 2 EN Alternate Sink Alternate Source 4 Alternate Sink 3 Trace Cut Pad Default Connection Default Source Default Sink 1 2 1 2 9 3 4 Alternate Sink Alternate Source Alternate Sink 3 4 Trace Cut Pad Alternate Connection Default Source 2 Default Sink 1 2 Alternate Sink 3 d Alternate Source A
24. ternal Tower System modules If required the signals from the MCF54418 can be disconnected from either the LED s or the TWR ELEV GPIO s The connection to the LEDs is made between pads 1 and 2 The connection to the TWR ELEV GPIO s is made between pads 1 and 3 Refer to the table below for details regarding which signal corresponds to which LED and TWR ELEV GPIO MCF54418 Configuration Signal Name pis TAYR ETEV ONIO Cut Trace Pad GPIO_GO LED1 Amber GPIO9 A9 CT3 GPIO G1 LED2 Yellow GPIO7 A11 CT6 GPIO G2 LED3 Green GPIO1 B21 CT9 GPIO G3 LED4 Orange Red GPIOS B52 CT7 For more details regarding the Cut Trace pad options and the pad numbering refer to the Cut Trace Pad section of this document 4 13 Reset Configuration TWR MCF54441X has three boot mode options e Boot with default configuration constants specified in the RCON register Boot with NAND NOR with configuration data specified by the Flexbus FB_AD 7 0 pins Boot with configuration data obtained from an external SPI memory through the serial boot facility The boot modes are determined by the jumper configuration of J5 at reset Placing a jumper on pins 1 2 of JS causes BOOTMOD O0 to be low 0 Placing a jumper on pins 3 4 of J5 causes BOOTMOD 1 to be low 0 In the table below ON implies that the respective jumper is shunted MCF5441X Tower Module Hardware Specification Page 14 of 31 2 freescale
25. uit 3 2 TWR MCF5441X Overview The TWR MCF5441X provides hardware to evaluate as many of the configurations of the MCF5441x family as possible The TWR MCF5441X features Tower compatible processor board MCF54418 in a 256 MAPBGA package DDR2 SDRAM 128 MByte A NAND Flash memory device 256MByte Two RS232 headers 2x5 pins Standard 26 pin BDM Header MCF5441X Tower Module Hardware Specification Page 5 of 31 2 freescale semiconductor MC9S08JM60 based Open Source BDM OSBDM circuit Standard 6 pin BKGD MS Header MMA7361L three axis accelerometer Wire Digital Temperature Sensor Four LEDs DIP Switches and push buttons for user input Potentiometer Audio Speaker Header Only uses 4889 audio power amplifier 4 Hardware Specification This section provides specification details for the TWR MCF5441X board R26 R28 c ee Af Tuo set IK 42414 41454 BOOT SETTING m ON 2 OD Lir 4 1 Microcontroller The microcontroller on the TWR MCF5441X will be a member of the highly integrated 32 bit microprocessor family based on the Coldfire V4m with MMU EMAC and CAU units MCF5441X Tower Module Hardware Specification Page 6 of 31 freescale semiconductor FEC RMII High Speed PCle Expansion Connectors USB ULPI Analog Timers IRQs FlexBus UARTs 2 2 Switches d i bus CAN etc SPI USB Ethernet SSI SDHC UARTs Hexbus
26. ule Hardware Specification Page 2 of 31 gt D 2 freescale semiconductor 1 Purpose This document provides design and usage information for the Freescale TWR M54418 evaluation development and reference platform The TWR MCF5441X platform provides and evaluation system for the Freescale MCF5441x ColdFire V4m embedded microprocessor family The MCF54418 is the superset device in the family and is the processor featured on this platform This allows evaluation and development for the entire MCF5441x family on an existing Tower system 3 Reference Documents MCF54418 Reference Manual TWR M544418 Quick Start Guide TWR M54418 Schematics MCF54418 Data Sheet MMA7361L Data Sheet Three Axis Accelerometer DDR2 SDRAM Specification JESD79 2C Tower Overview Presentation Tower Mechanical Specification DS18B20 Data Sheet Temperature Sensor DS18B20 Application Note 120 Using an API to Control the DS1WM 1 Wire Bus Master 152007 Data Sheet Class D audio power amplifier with 6 12dB gains MC9S08JM60 Reference Manual Cut Trace Pads Overview 3 1 MCF5441x Overview The following is a brief summary of the functional blocks in the MCF5441x superset device Version 4 ColdFire Core with MMU and EMAC o CPU 250 MHz 16 KBytes instruction cache and 16 KBytes data cache MCF5441X Tower Module Hardware Specification Page 3 of 31 e gt oe 2 freescale semiconductor 64 Kbytes inter
27. und x 066 FB_AD20 LCD42 Flexbus Display FB_AD20 x D67 FB_AD21 LCD43 Flexbus Display FB_AD21 x 068 FB_AD22 LCD44 Flexbus Display FB_AD22 x 069 FB_AD23 LCD45 Flexbus Display FB_AD23 x D70 FB_AD24 LCD46 Flexbus Display FB_AD24 x D71 FB_AD25 LCD47 Flexbus Display FB_AD25 x D72 FB_AD26 LCD48 Flexbus Display FB_AD26 x D73 FB_AD27 LCD49 Flexbus Display FB_AD27 x D74 FB_AD28 LCD50 Flexbus Display FB_AD28 x D75 FB_AD29 LCD51 Flexbus Display FB_AD29 x D76 FB_AD30 LCD52 Flexbus Display FB_AD30 x D77 FB AD31 LCD53 Flexbus Display FB AD31 x D78 LCD_D20 LCD20 Display D79 LCD D21 LCD21 Display D80 LCD D22 LCD22 Display D81 GND Power Ground x D82 3 3V Power 3 3V Power x MCF5441X Tower Module Hardware Specification Page 30 of 31 gt P freescale semiconductor ey 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2008 All rights reserved MCF5441X Tower Module Hardware Specification Page 31 of 31
28. witch settings For SW1 a value of 0 implies that the dip is switched On Override Pins in Reset Function SW1 DIP 1 Boot Memory 0 Default NAND Flash 1 FlexBus SW1 2 PLL mode 0 Disabled 1 Default Enabled SW1 3 Oscillator mode 0 Default Crystal oscillator mode 1 Oscillator bypass mode SW1 4 FB ALE select 0 FB TS B 1 Default FB ALE SW1 6 5 BOOT Port size 00 32 bit 32 bit muxed address 01 8 bit 24 bit non muxed address 10 Default 16 bit 16 bit non muxed address 11 16 bit 16 bit non muxed address SW1 8 7 PLL Multiplier 00 Default Fvco 10 x Fref 01 Fvco 15 x Fref 10 Fvco 16 x Fref 11 Fvco 20 x Fref Table 10 SW1 8 way DIP switch MCF5441X Tower Module Hardware Specification Page 16 of 31 freescale semiconductor 4 13 3 Serial Configuration J5 OFF OFF If the BOOTMOD pins are 11 during reset then the chip configuration after reset is determined by data obtained from an external SPI memory through serial boot using the SBF DI SBF DO SBF CS and SBF_CLK signals The internal configuration signals are driven to reflect the data being received from the external SPI memory to allow for module configuration See Table below BYTE Address Data Contents 0 0 0000 BLDIV 3 0 0 1 BLL 7 0 Ox2 BLL 15 8 Ox3 RCON 7 0 Ox4 RCON 15 8 0 5 RCON 23 16 Ox6 RCON 31 24 Tabl
29. z 20x 1 1 Off Off Note VCO must be in the range from 240 500 MHz USB frequency must be 60M Hz SDHC frequency must not be greater than 250MHz and NAND frequency must not be greater than 80M Hz 4 3 System Power The TWR MCF5411X board is powered by 5V either from the OSBDM circuit via the miniAB USB connector or the Tower Elevator power connections Power regulation circuitry is capable of providing 1 2V 1 8V and if needed 3 3V from either of the power source 4 4 Debug Interface TWR MCF5441X provides two debug interfaces a standard BDM an Open Source OSBDM 4 4 1 Stardard BDM The primary debug port on the TWR MCF5441X is referred to as the background debug module or BDM The standard 26 pin BDM header J11 is provided on the TWR M54441X for attachment of an external BDM control interface MCF5441X Tower Module Hardware Specification Page 8 of 31 gt z freescale semiconductor Function Function 1 RSTOUT b 2 TMS BKPT b 3 GND 4 DSCLK 5 GND 6 TCK 7 RSTIN b 8 TDI DSI 9 3V3 10 TDO DSO 11 GND 12 PST3 13 PST2 14 PST1 15 PSTO 16 DDATA3 17 DDATA2 18 DDATA1 19 DDATAO 20 GND 21 NC 22 NC 23 GND 24 PSTCLK OSBDM 25 3V3 26 NC Table 2 BDM Headers The MCF5441x also features IEEE 1149 1 Test Access Port JTAG test logic that can be used for boundary scan testability The access pins for JTAG are multiplexed over the B
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