Data Sheet
Contents
1. HT82V863R CCD Digital Signal Processor Features nput Supports Ye Mg Cy G colour filters for NTSC PAL 270 320 410 470 sensors Output NTSC PAL Analog CVBS Automatic CCD Defect compensation Up to 50 bad pixels and 4 consequential bad pixels correction Automatic Back Light compensation Programmable False Colour suppression Programmable High Light suppression Programmable Sharpness enhancement Programmable Colour Saturation and Hue function Programmable Contrast and Brightness function Programmable GAMMA curve ntegrate a 96 step CCD timing generator Support AE AWB algorithm function Support OSD function ntegrate a 2 D DNR function ntegrate the digital WDR ntegrate the digital Line Lock function to reduce colour rolling ntegrate a NTSC PAL video encoder ntegrate a 10 bit DAC Support CCIR656 digital out ntegrate a one channel 6 bit ADC ntegrate OTP ROM with ISP function for multiple programming codes Support Mirror function Support a master interface for external EEPROM to store parameters Support a slave interface for communication with an external host Embedded LVR and POR circuits Embedded 3 3V to 1 8V regulator Single 3 3V power supply 64 80 LQFP package Rev 1 00 General Description The HT82V863R is a single chip digital image processor for Ye Cy Mg and G colour CCD v2. Symbol Parameter Remark Unit Min Max Min Max fsk Clock Frequency 100 400 kHz Clock High Time 4000 600 ns tow Clock Low Time 4700 1200 ns in SDA and SCL Rise Time Note 1000 300 ns t SDA and SCL Fall Time Note 300 300 ns tuosta START Condition Hold Time 2 the first clock pulse 4000 600 ns tusa START Condition Setup Time on 1 SIART 3590 as tup paT Data luput Hold Time 0 0 ns tsu pat Data luput Setup Time 200 100 ns tsu sto STOP Condition Setup Time 4000 600 ns Output Valid from Clock 3500 900 ns tur Bus Free Time before a new transmission can start 4700 1200 tsp con stant Noise suppression time 100 50 ns twr Write Cycle Time 5 5 ms A D Converter Interface Timing Rev 1 00 ADON START 12 i September 30 2011 f Functional Description CCD Interface The CCD interface is used to capture the image and receive the CMYG CFA CCD raw data and the control signals generated from the analog front end module Then the CCD raw data together with the control signals will be correctly manipulated such as for black clamp operation bad pixel compensation etc The processed raw data and control signals will be eventually sent to the Colo
3. 4 Vertical shift register clock for Vertical Driver VD V2 4 Vertical shift register clock 2 for Vertical Driver VD V1 4 Vertical shift register clock 1 for Vertical Driver PVSS Pad ground pin PCLK O 12 Pixel Clock Output GPIO8 B 4 GPIO 8 PWM 3 output GPIO9 B 4 GPIO 9 UART Receiver data input GPIO10 B 4 GPIO 10 GPIO11 B 4 11 GPIO4_MSDA B U 4 GPIO 4 or Master mode Data Input Output GPIO3 MSCL B U 4 GPIO 3 or Master mode Clock Output PVDD33 P 13 3 pad power GPIO2 SSDA B U 4 2 or Slave mode Data Input Output GPIO1 SSCL B U 4 GPIO 1 or Slaver mode Clock Input Rev 1 00 4 September 30 2011 f 82 863 Description Name DIR PUL mA PVDD65 P 16 5 pad power PVSS P Pad ground pin CCIR CLK 12 CCIR656 Encoder Clock Output DVSS P Digital ground pin DVDD18 P 11 8 digital power pin PVDDREG 13 3 regulator power pin AVSS DAC and Regulator Ground pin PLL VCO AO VCO Output AVSS P DAC and Regulator Ground pin AVDD 3 3V OP and
4. s level Equalizing Pulse and Sync Pulse Interval Timing Table equalizing pulse and sync pulse interval timing Symbol Characteristics us NTSC PAL p Duration of equalizing pulse 2 3 0 1 2 35 0 1 9 Duration of field synchronizing pulse 27 1 27 3 r Interval between field synchronizing pulse 4 7 0 1 4 7 0 2 5 Build up timing 10 to 90 50 25 0 2 0 1 Rev 1 00 8 September 30 2011 f HT82V863R A Details of Line Synchronizing Signal Table Details of line synchronizing signal Symbol Characteristics us NTSC PAL d Synchronizing pulse 4 7 0 1 4 7 0 2 Build up time of the line blanking pulse lt 0 48 0 3 0 1 Build up time of the line synchronizing pulse lt 0 25 0 240 1 b Line blanking interval 9 2 10 3 12 0 2 Front porch 1 27 2 22 1 940 3 9 Start of sub carrier burst 4 71 5 71 5 6 0 1 Duration of sub carrier burst 2 23 3 11 9 1 cycles 2 25 0 23 10 1 cycles H Nominal line period 03 5555 64 CCIR656 Encoder Interface Timing The CCIR656 Encoder connects to the digital component video signals using 525 lines for NTSC systems or 625 lines for PAL systems The data stream 15 a sequence of 8 bit bytes transmitted at a rate of 27 MBbyte s The video pixel data horizontal scan lines are delimited in the stream using 4 byte long SAV Start of Active Video and EAV End of Active
5. DIN3 DIN2 DIN1 DINO PVDD33 AFE OBP AFE PBLK AFE ADCLP Rev 1 00 6 1718 19 2021 2223 2425 26 2728 29303132 PIN 154 71 NSO 0049 O oa 34V MO aav SSAd 7 JdMd SOld9 SHO 90199 rl eadAd 7 NI 1 dO dNI dO SSAV L 7 O3GIA 2 646362616059585756 5554 53 LNOX 251504 HT82V863R 64 LQFP A 38L1 PVDD65 37L GPIO1 SSCL 361 GPIO2 SSDA 35E1 PVDD33 34 331 4 MSDA Py B U LI lt lt lt lt lt lt MT Ty oo Ol I I I I I I OL 1 Cj 9 WV S OA 2 500 0 lo U U e VIDEO VREF BIAS COMP FSA AVDD AVSS PLL VCO AVSS PVDDREG DVDD18 DVSS CCIR_CLK 55 PVDD65 HT82V863R 80 LQFP A PVDD33 C HT82V863R GPIO1 SSCL GPIO2 SSDA GPIO3 MSCL 4 MSDA September 30 2011 f Pin Description HT82V863R Description Name DIR TYP PUL mA CCIR D3 4 CCIR656 Encoder Data Output bit CCIR D2 4 656 Encoder Data Output bit 2 CCIR_D1 O 4 CCIR656 Encoder Data Output bit 1 CCIR_DO O 4 CCIR656 Encoder Data Output bit
6. 2 4 V lbp Operating current 80 mA Vr Schmitt trigger input low voltage 0 8 171 V Vi Schmitt trigger input high voltage 1 6 2 0 V Input pull up pull down resistance V 70V or V Vcc 75 Characteristics Clock Characteristics Symbol Parameter Min Typ Max Unit Oscillator Clock Frequency 500ppm 28 7 500 2 Oscillator Clock Duty Cycle 45 50 55 Reset Characteristics Symbol Parameter Min Typ Max Unit test N External System Reset pulse width 1 ms Rev 1 00 6 September 30 2011 HT82V863R CCD Input Interface Timing Symbol Parameter ue Min Typ Max Unit Vop Conditions fs Conversion Frequency 3 0V 0 5 20 MHz Clock Cycle Time 3 0V 50 ns tk Clock Rising Time 3 0V 2 ns t Clock Falling Time 3 0V 2 ns t Clock Low Period 3 0V 29 ns ty Clock High Period 3 0V 23 ns twr SHR Pulse Width 3 0V 11 ns two SHD Pulse Widh 3 0V 11 gt ns lor SHR Sampling Aperture 3 0V 4 ns top SHD Sampling Aperture 3 0V 4 ns tsip Data Pulse Setup 3 0V 2 ns Data Pulse Hold 3 0V 5 ns Sampling Pulse 3 0 1 ns tsupe Enable Pulse Setup 3 0V 10 5 tuoipE Enable Puls
7. 0 063 0 004 J 0 018 0 030 K 0 004 0 008 a 0 Dimensions mm Symbol Min Nom Max A 11 90 12 10 B 9 90 10 10 C 11 90 12 10 D 9 90 10 10 E 0 40 F 0 16 G 1 35 1 45 1 60 0 10 J 0 45 0 75 K 0 10 0 20 a 0 T Rev 1 00 16 September 30 2011 HT82V863R Copyright 2011 by HOLTEK SEMICONDUCTOR INC The information appearing in this Data Sheet is believed to be accurate at the time of publication However Holtek assumes no responsibility arising from the use of the specifications described The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves the right to alter its products without prior notification For the most up to date information please visit our web site at http www holtek com tw Rev 1 00 17 September 30 2011
8. DAC Power pin FSA AO DAC Full Scale Adjust Control COMP AO DAC Compensation pin BIAS AO Current Source Bias Pin VREF Al Bandgap Reference Voltage Output VIDEO AO DAC VIDEO Output AVDD 3 3V OP and DAC Power pin AVSS P OP and DAC Ground pin OP INP Al Buffer Positive Input OP_OUT AO Buffer Output ADC IN Al Converter Analog Input GPIO7 B U GPIO 7 27MHz Clock input CCIR_D7 O 4 CCIR656 Encoder Data Output bit 7 CCIR D6 4 656 Encoder Data Output bit 6 PVDD33 13 3 pad power GPIO 6 or PWM 2 output or UART Transmitter data output TXD or Ses 5 CUL 4 GPIO5 PREF B U 4 GPIO 5 or PWM 1 output or Power Line Reference Clock Input PVSS P Pad ground pin AFE CK 4 SPI Clock Output for AFE AFE DO 4 SPI Data Output for AFE tput UART Transmitter tput TXD or R x T 5 RST 5 Reset Active Low CCIR D5 4 CCIR656 Encoder Data Output bit 5 CCIR D4 4 CCIR656 Encoder Data Output bit 4 XOUT O Oscillator output XIN Oscillator input for MCLK Note DIR pin direction B bi directional O output I input
9. 0 55 P Pad ground AFE DIN9 Data input bit 9 DIN8 CCD Data input bit 8 DIN Data input bit 7 AFE DING CCD Data input bit 6 PVDD33 P 13 3 pad power DIN5 CCD Data input bit 5 DIN4 Data input bit 4 AFE DIN3 CCD Data input bit AFE DIN2 CCD Data input bit 2 DIN1 CCD Data input bit 1 AFE DINO CCD Data input bit 0 PVSS P Pad ground pin PVDD33 P 13 3 pad power AFE OBP O 4 Clamp pulse output for optical black function AFE PBLK 4 Blanking pulse output for AFE AFE ADCLP 4 Clamp pulse output for AFE AFE SHD O 4 Sample hold pulse output for data AFE SHP O 4 Sample hold pulse output for reference PVSS Pad ground pin CCD H2 12 Horizontal shift register Clock 2 for CCD CCD H1 12 Horizontal shift register Clock 1 for CCD CCD RG 12 Reset pulse output for CCD PVDD33 P 13 3 pad power VD VSUB 4 substrate bias pulse output for Vertical Driver VD VSG2 4 pulse 2 for Vertical Driver VD VSG1 4 Readout pulse 1 for Vertical Driver VD V4 4 shift register clock 4 for Vertical Driver VD V3
10. 0 280 C 0 350 0 358 D 0 272 0 280 0 016 0 005 0 009 0 053 0 057 H 0 063 0 002 0 006 J 0 018 0 030 K 0 004 0 008 0 7 Dimensions mm Symbol Min Nom Max A 8 90 9 10 B 6 90 7 10 8 90 9 10 D 6 90 7 10 0 40 F 0 13 0 23 G 1 35 1 45 H 1 60 0 05 0 15 J 0 45 0 75 K 0 09 0 20 O 72 1 00 19 September 30 2011 f HT82V863R 80 pin 10mmx10mm Outline Dimensions gt i _________ 60 41 12 ie m AF A B L L X E 80 21 1 20 Dimensions in inch Symbol Min Nom Max A 0 469 0 476 B 0 390 0 398 C 0 469 0 476 D 0 390 0 398 E 0 016 0 006 0 053 0 057
11. Analog input AO Analog output TYP pin type T tri state OD open drain 5 Schmitt trigger P Power pin PUL pin internal pull up down 750 resistor D pull down U pull up mA pin driving current capability Rev 1 00 5 September 30 2011 f HT82V863R Absolute Maximum Ratings Power Supply Voltage Ve 0 3V 4 3V Output Voltage V yinemi 0 5 VON V Input Voltage V 0 3V V 0 Storage Temperature A0 Ce 1507 Note These are stress ratings only Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device Functional operation of this device at other conditions beyond those listed in the specification 15 not implied and prolonged exposure to extreme conditions may affect device reliability Recommended Operating Conditions Symbol Parameter Min Typ Max Unit Vog Power supply 3 0 3 3 3 6 V Vin Input voltage 0 Vec V Top Operating temperature 20 25 70 C fox Input clock frequency 28 7 MHz D C Characteristics Symbol Parameter Condition Min Typ Max Unit Vit Input low voltage 0 8 V Input high voltage 2 0 V 0 4 V Output high voltage
12. Video code sequences Individual pixels in a line are coded in YCbCr 4 2 2 format After an SAV code 4 bytes 15 sent the first 8 bits of Cb chroma U data are sent and then 8 bit data of followed by 8 bit data of Cr chroma V for the next pixel and then 8 bits of Y TV System PAL 625 lines NTSC 525 lines V digital field blanking Start 1 Line 624 Line 1 Field 1 a Finish V 0 Line 23 Line 10 Start V 1 Line 311 Line 264 Field 2 Finish V 0 Line 336 Line 273 F digital field identification Field 1 F 0 Line 1 Line 4 Field 2 F 1 Line 313 Line 266 Video DatField Blanking Definition Rev 1 00 September 30 2011 f Horizontal Timing HT82V863R BT 601 H SIGNAL START OF DIGITAL ACTIVE LINE NEXT LINE START OF DIGITAL LINE EAV CODE BLANKING CO SITED CODE CO SITED 1716 1728 One Scan Line Parallel Interface Data SPI Interface Timing SYNCHRONOUS DATA TIMING Symbol Parameter Conditions Min Max Units Tex SK Clock Frequency 0 250 kHz SK High Time 1 us SK Low Time 1 us tes Minimum CS Low Time 1 us 5 0 2 5 ton DO Hold Time 70 ns tois DI Setup Time 0 4 us CS Hold Time 0 ns ton DI Hold Time 0 4 Us Output Delay 2 us ts
13. be up to 16x16 font size The scaling factor can be up to 8 times on both the horizontal direction and vertical direction Back Light Compensation BLC The Back Light Compensation will provide perfect exposure for an object in front of very strong back light no matter whether the main object is moving toward the center upper lower left right part or any location in the screen The HT82V863R device provides a smart adaptive BLC algorithm to perform compensation followed by the exposure level with a fast speed so that no matter where on the screen the main object is moving to it always provides a clear picture DWDR Digital WDR is a proprietary algorithm to provide clear images even under back light circumstances where there are both very bright and very dark areas simultaneously in the view of the camera In short DWDR allows the viewer to see details in both areas CCIR656 Encoder The CCIR656 Encoder accepts the data stream derived from the Colour Image Processor and converts the data into ITU_R BT656 digital output signals Interface The device integrates an OTP ROM for firmware storage The firmware can be easily programmed into the OTP ROM using the In System Programming function and the interface Programming Considerations All configurations in this device are displayed in a user interface window as part of the relevant development tool system Therefore the detailed configuration and definition
14. e Hold 3 0V 10 ns laupot OUTCK Setup 3 0V 0 ns buie OUTCK Hold 3 0V 10 ns Unt 3 state Disable Delay 3 0V Active High Z 20 ns Ds 3 state Disable Delay 3 0V High ZActive 20 ns ADC Output Data Delay 3 0V 18 ns tod Reference Sampling Data Sampling gt SHR twp 15 D 0 de 4 1 SHD Sd E TA lt gt tHOLDE e 4 tsuPE BLK tL CLP CCDCLP ADCLP tSUPOC ork J J LJ LJ LJ L to Note Normally the AFE ASIC registers are set to ignore OUTCK and only use ADCK Rev 1 00 7 September 30 2011 pore P HT82V863R TV Encoder Output Interface Timing Colour I Field blanking period 19 mannm 13201 i T BH JR 1 3H AH TRI 4o interval Pre equ Vertical sync FPest equalizing mterva pulse interval pulse mterval Reference Line vertical sub carrier phase colour field I Colour field II Field blanking Start of H d held Pre equalizi Vertical sme Peost equalizing pulse itera pulse interval pulse interval Reference sub carner phase colour field II NTSC Vertical Timing Blanking level
15. ideo camera systems It receives CFA patterns from colour CCDs and generates NTSC PAL CVBS signals using internal video encoders and the 10 bit DAC In addition it also provides an AE AWB algorithm timing generation module together with other circuitry The device contains a microcontroller in which an OTP ROM is integrated internally to implement the basic camera functions such as the AE AWB algorithm The video camera system consists of a CDS AGC ADC IC HT82V842A DSP IC HT82V863R Vertical Driver IC HT82V805 and CCD sensors It also provides a proprietary function to eliminate so called line crawl and automatic CCD defect compensation function to correct up to 30 bad pixels and 4 consequential bad pixels September 30 2011 LVR POR Reset Image Processor CCD Timid Timing AE AWB Generator Control Rev 1 00 2 HT82V863R 1 8V Power 3 3V Power output input 3 3V to 1 8V 1 3V Trigger LVR POR Regulator NTSC PAL Video Encoder Digital CCIR656 Output September 30 2011 Pin Assignment DIN9 DIN8 DIN7 DING PVDD33 DIN5 AFE_DIN4 AFE_DIN3 AFE_DIN2 AFE DIN1 DINO PVSS PVDD33 AFE OBP AFE PBLK AFE ADCLP 03 CCIR D2 D1 CCIR DO PVSS DIN8 DIN7 AFE DING PVDD33 DIN5 DIN4
16. s are not mentioned in this document Refer to the corresponding user s manual for more detailed configuration information September 30 2011 OO R System Application Diagram HT82V805 HT82V863R 1 Pu CFEC ER CCIR656 CCD Sensor Lens OTP ROM Data SRAM 2 Rev 1 00 14 September 30 2011 HT82V863R Package Information Note that the package information provided here is for consultation purposes only As this information may be updated at regular intervals users are reminded to consult the Holtek website http www holtek com tw english literature package pdf for the latest version of the package information 64 pin LQFP 7mmx7mm Outline Dimensions B gt EE E 48 33 amem 32 AF A B E 64 17 1 16 Dimensions in inch Symbol 0 350 0 358 B 0 272
17. ur Image Processor to perform further image signal manipulations Colour Image Processor The heart of the surveillance camera is the Colour Image Processor in which the raw data derived from the CCD interface is processed In addition to the colour mosaic interpolation several colour image processor main functions include the edge extraction and enhancement colour correction auto exposure support and white balance colour space transform gamma correction and false colour suppression Timing Generator This is a programmable 96 step precision timing generator embedded with a DLL to perform timing fine tuning and to generate all the CCD data related control timings TV Encoder This provides a 10 bit YCbCr digital input interface to accept the data stream sent from the Colour Image Processor or equivalent circuitry and to convert the data into the NTSC or PAL TV composite signal or Y C signal Line Lock A Line Lock function is available on most CCTV cameras and is used to prevent picture colour rolling on the monitor which results from the difference between the surveillance camera exposure frequency and the AC power line frequency Colour rolling will cause a vital picture information loss and will be irritating for the viewer Rev 1 00 13 HT82V863R A D Converter The device provides a 6 bit A D Converter OSD Generator The device can generate up to 4 lines with a maximum of 16 characters each of which can
18. y CS to Status Valid 1 us ise CS to DO in Hi Z CS2ViL 0 4 Hs twe Write Cycle Time 15 ms Rev 1 00 10 September 30 2011 HT82V863R Interface Timing Data allowed to change uc SDA SCL NUNC Start Address or NoACK Stop condition acknowledge state condition valid Device address Word address DATA 5 TP Start R W ACK ACK ACK Stop Byte Write Timing Device address Word address DATAn DATA 1 DATA n x t spa 5 Start Stop Page Write Timing Device address DATA 7 Stop spa 5 leo Start ACK No ACK Current Read Timing Device address Word address Device address DATA 0 7 Stop SDA 1111 Start Start Random Read Timing Device address DATAn DATA n 1 DATA ______ ________ IEEE SPAS _______ Start ACK ACK No ACK Sequential Read Timing 11 September 30 2011 Rev 1 00 f gt tre Hy SCL SDA M y tspP OUT ON jg ow ISU STA le tHD STA _____ Valid tSU DAT tsu sTO PLUS HT82V863R Standard Mode Vec 5VE10
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