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1. Figure 19 Power Circuit Topology 12V O RT9214 3V3 RT9167 1V8 Kendin Switch RT9214 5V USB RT9194 1V8 DDR2 Enable RT9173 VTT 0 9V 3V3 1V8 DDR2 astral 1V3 IntelfPIXP435 sas Network Processoj RT9194 Enable 1V3 PNX1700 3V3 RT9194 2V5 DDR Enable IV3 PNX1700 Other names and brands may be claimed as the property of others B6537 01 Table 24 Power Consumption Estimation Sheet 1 of 2 Intel 1XP435 Multi Service Residential Gateway Reference Platform power consumption estimation standby mode Current p Legend Device Name Device Part Volts omer mW milliamps mA Power mW IXP43X network CPU processors 667 MHz core 1 3 610 733 IXP43X network Memory Subsystem processors 667 MHz 1 0 3 3 327 1079 MT47H32M16CC 5E 2 Flash 28F128J3A Ethernet Switch KSZ8995M 2 5 100 250 C Misc Logic Clock Buffer LED Logic 3 3 50 165 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 48 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel Table 24 Power Consumption Estimation Sheet 2 of 2 Intel 1XP435 Multi Service Residential Gateway Reference Platform power consumption estimation standby mode Current Power Legend Device Name Device Part Volts in P
2. opt DDRII SDRAM 1 D DQ 31 16 Intel IXP 435 DB A 12 0 CS I 9 pasy a CASH WE LDM UDM LL 9 BA I 0 gt CKE L PRIORE 5 LDQSUDOS LLL opT DDRII SDRAM 2 DDR DM R 3 2 3 8 June 2007 MII Interface The IXP435 reference platform supports four 10 100 Mbps Ethernet LAN ports and one 10 100Mbps WAN port Both the LAN and WAN ports are supported by the Kendin KS8995M 10 100Mbps Ethernet switch through the two MII buses that connect to the IXP43X network processors See Table 13 for the WAN port switch setting The auto MDI MDIX feature must be available for all LAN ports This interface uses a 5 gang RJ 45 connector with integrated magnetics The Kendin KS8995M component is used in the IXP435 reference platform design The KS8995M contains five physical layer transceivers and five MAC units with an integrated Layer 2 switch The Port 5 of KS8995M is configured to a single PHY mode See Table 13 for the WAN port switch settings Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Document Number 316848 Revision 001US 31 Figure 11 Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide NPE Function Connections Switch Controller SP Ether NP
3. Note The is create command is entered on a single line lt IMAGE NAME gt lt IMAGE LENGTH gt and FLASH ADDRESS are placeholders for arguments that are required by the fis create command lt IMAGE NAME gt The name that identifies the image in flash A corresponding load command can use this name IMAGE LENGTH The length in bytes of the image previously loaded into RAM Use the length as determined in step 8 lt IMAGE ADDRESS gt The location in flash where the image will be written Check the output of the fis list command to see the segments that have been programmed as available Note Flash updates using JTAG tool EPI Majic BDI2000 and VisionICE are supported Contact your Intel sales representative for additional information A 2 Creating a Backup Copy of RedBoot As a precaution before updating the primary RedBoot image create a backup RedBoot image in flash The backup version can be used in case there is a problem updating the primary RedBoot image and or the new image fails to operate properly Follow the steps mentioned below to load an additional copy of RedBoot into flash 1 Load the redboot ROM bin image into flash gt load r v b 0x00160000 redboot ROM bin gt fis create Redboot bak b 0x00100000 I 0x0007A000 f 0x51000000 e 0x00000000 Note The fis create command is entered on a single line 2 Switch off the power to the board 3 Verify that RedBoot boots The following
4. e S Video composite video and YCbCr YPbPr for Video outputs e S Video and composite video for Video inputs e I2S and S PDIF stereo audio outputs and input e Two JTAG for IXP43X network processors and Media processor e Two FXS RJ11 Port VoIP function e One FXO RJ11 Port e One 10 100 Mbps Ethernet port for WAN e Four 10 100 Mbps Ethernet ports for LAN e One 2KByte EEPROM for Media processor e One Serial port for debug used Mezzanine cards that are optional and that can be purchased separately include Intel IXPDSM465 ADSL UTOPIA level 2 mezzanine card Intel IXPVM465 Analog Voice mezzanine card 4 FXS 1 FXO Intel IXPFRM465 Quad T1 E1 mezzanine card Intel IXPETM465 Ethernet PHY mezzanine cards The listed mezzanine cards have the same design as the one for the Intel IXDP465 Development Platform This document will not describe information on the above mezzanine cards Refer to the Intel IXDP465 Development Platform User s Guide for features and description of the mezzanine card hardware design Functional and Physical Layout of the Intel I1XP435 Multi Service Residential Gateway Reference Platform The connections between the devices on the baseboard and mezzanine cards are shown in Figure 1 Details of the devices are described in the following sections Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 12 June 2007 Document Number 316848 Revision 001US Intel IXP435 Mul
5. 3 3V B23 PCI HST AD27 B53 PCI HST AD7 A24 GND A54 PCI HST AD6 B24 PCI HST AD25 B54 3 3V A25 PCI_LHST_AD24 A55 PCILHST_AD4 B25 3 3V B55 PCI HST AD5 A26 PCI HST IDSELO A56 GND B26 PCI HST CBE N3 B56 PCI HST AD3 A27 3 3V A57 PCI HST AD2 B27 PCI HST AD23 B57 GND A28 PCI_LHST_AD22 A58 PCI_HST_ADO B28 GND B58 PCI_LHST_AD1 A29 PCI_LHST_AD20 A59 3 3V B29 PCI HST AD21 B59 3 3V A30 GND A60 PCI HST REQ64 NO B30 PCI HST AD19 B60 PCI HST ACK64 NO A31 PCI_LHST_AD18 A61 5 0V B31 3 3V B61 5 0V A32 PCI_LHST_AD16 A62 5 0V B32 PCI HST AD17 B62 5 0V 3 3 Media Processor The audio video function is controlled by PNX1702 Nexperia Media Processor of Philips which interfaces with the IXP43X network processors through the PCI interface The PNX1702 Media Processor is a complete Audio Video Graphics system on a chip that contains a high performance 32 bit VLIW processor the TriMedia TM3260 The TriMedia TM3260 is capable of software video and audio signal processing and general purpose control processing It is capable of running a pSOS operating system with real time signal processing tasks in a single programming and task scheduling environment An abundance of interfaces make the PNX1702 suitable for networked Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 19 a n tel Intel 1XP435 Multi Service Residential Ga
6. Purpose This document provides detailed design information for the Intel IXP435 Multi Service Residential Gateway Reference Platform The IXP435 reference platform includes the basic blocks of an Intel IXP43X Product Line of Network Processor based system DDR memory PCI and connectors through which UTOPIA level 2 MII FXS FXO T1 E1 and power devices are connected Several mezzanine cards designed used in IXDP465 platform in conjunction with the IXP435 multi service residential gateway reference platform plug in through the UTOPIA level 2 or MII connector I ntended Audience The intended audience for this document includes hardware architects and developers who are developing both hardware and software for applications based on the Intel IXP43X Product Line The IXP435 reference platform is designed to meet the market requirements for a flexible customer oriented platform This platform demonstrates the capabilities of the IXP43X product line of network processors in a system and enables software development of the IXP43X product line of network processors Customers can base their designs on portions of the IXP435 reference platform design Prerequisites The Intel IXP435 Multi Service Residential Gateway Reference Platform supports all available features of the Intel IXP43X Product Line of Network Processors Many features such as the network processor engine NPE functions are enabled by a specific revision of the Intel
7. 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment RAM Red Hat certified release version 2 02 built 15 43 18 Nov 23 2006 Platform IXP435 reference platform xscaie BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc RAM 0x00000000 0x08000000 0x00196c68 0x07f d1000 available FLASH 0x50000000 0x51000000 128 blocks of 0x00020000 bytes each Executing boot script in 3 000 seconds enter C to abort Load the primary RedBoot image to overwrite the current image in flash load r v b 0x00200000 redboot ROM bin Using default protocol TFTP N Raw file loaded 0x00200000 0x00278edb assumed entry at 0x00200000 fis unlock RedBoot fis create RedBoot b 0x00200000 1 0x0007A000 f 0x50000000 e 0x00000000 An image named RedBoot exists continue y n y Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 56 June 2007 Document Number 316848 Revision 001US User s Guide I ntel 1XP435 Multi Service Residential Gateway Reference Platform n tel Unlock from 0x51fe0000 0x52000000 Erase from 0x51fe0000 0x52000000 Program from 0x07f e0000 0x08000000 at 0x51fe0000 Lock from 0x51fe0000 0x52000000 fis lock RedBoot Lock from 0x50000000 0x50080000 3 Reset the board by powering it off and on and verify that RedBoot starts up gt Trying NPE C success Using NPE C with PHY
8. Figure 1 e PCI Device 0 Media Processor e PCI Device 1 Mini PCI 1 connector e PCI Device 2 Mini PCI 2 connector e PCI Device 3 PCI Slot The IXP43X network processors act as the PCI host and all other devices act as PCI targets The IXP435 reference platform supports only PCI 33 MHz bus operation with PCI 2 2 compliance The IXP435 reference platform supports two external 32 bit Mini PCI devices 3 3V only and allows capabilities such as wireless LAN for example 802 11 a b g and PCI version 2 2 is used Table 5 describes the IDSEL mapping and GPIO mapping on the PCI devices of the IXP435 reference platform The IDSEL signals are connected to the PCI AD bus and these GPIO pins are for interrupt function See the following tables for pin assignment details I DSEL and GPI O Mapping on the PCI Devices SLOT ID Device Interrupt GPIO IDSEL Slot 0 Media Processor PNX1702 GPIO11 PCI AD31 Slot 1 Mini PCI 1 GPIO10 PCI AD30 Slot 2 Mini PCI 2 GPIO9 PCI AD29 Slot 3 PCI slot GPIO8 PCI_AD28 PCI Clocking The 33 MHz is generated by the IXP43X network processors through the GPIO 14 and a four port zero delay buffer Cypress CY2305 drives the four PCI devices clocks and the network processor PCI clock Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 18 June 2007 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residenti
9. PCB board uses a 6 layer 3 signals 2 grounds and 1 power FR4 PCB construction The PCB stack up is listed in Table 26 Table 26 PCB Stack Up Layer Description 1 Top Signal 1 2 GND 1 3 Signal 2 4 GND 2 5 PWR 1 6 Bottom Signal 2 58 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 52 Document Number 316848 Revision 001US m User s Guide I ntel 1XP435 Multi Service Residential Gateway Reference Platform n tel 6 0 Regulatory Guidelines The Intel IXP435 Multi Service Residential Gateway Reference Platform complies with the following regulatory conditions EMI FCC Part 15 and CISPR 22 EN55022 for Class B PTT USA FCC TIA 968 A Issue 8 Industry Canada CS 03 Japan JATE EU TBR 21 Taiwan PSTN 01 Korea RLL and China Telecom YD T 514 e Immunity CISPR 24 EN55024 Safety IEC 60950 1 This product contains encryption logic and must meet all applicable export regulations for sale outside the United States of America The IXP435 reference platform complies with the requirements of the RoHS Directive 6 1 Environmental Guidelines The IXP435 reference platform complies with the environmental conditions defined in Table 27 Table 27 Environmental Ranges Lus so a Humidity As Measured From ange Range 0 509C Ambient temp Measured from the component with maximum power consumption on the Operational ext
10. claimed as the property of others B6538 01 3 20 Clocking The IXP435 reference platform implements the following clock schemes 1 33 MHz oscillator is used to provide 33 MHz clock input to the IXP43X network processors 2 GPIO14 is used to generate the 33 MHz PCI clock A clock buffer is used to distribute this PCI clock to all the PCI devices 3 GPIO15 is used to generate the Expansion bus clock 4 25 MHz crystal is used to provide the input clock for the Ethernet Switch Kendin 8995M 5 27 MHz crystal is used to provide the input clock for the Media Processor Philips PNX1702 6 27 MHz crystal is used to provide the input clock for the video encoder Philips SAA7104 7 24 576 MHz crystal is used to provide the input clock for the video decoder Philips SAA7118 8 2 048 MHz oscillator is used to provide to the HSS Clock of the IXP43X network processors optional 858 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 50 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform intel 4 0 Key Components of the Intel XP435 Multi Service Residential Gateway Reference Platform The Intel IXP435 Multi Service Residential Gateway Reference Platform is implemented with the following key components Table 25 Overvie
11. connector Serial Port DB 9 Connector Pin Definitions UART Signal UARTO DCD B L UARTO TXD B L UARTO RXD B L UARTO DTR B L UARTO GND B L UARTO DSR B L UARTO CIS B L UARTO RTS B L UARTO RI B L Wl OM NID mH AJ WwW N eR Serial Port Pull Ups Pull Downs The Receive signal lines are pulled down through a 5KQ resistor on the RS 232 side within the transceiver Since data signals are inverted the IXP43X network processors might see a pull up on these lines An unpopulated pull up shall be placed on the IXP43X network processors side receive signals to allow additional signal conditioning in case the internal pull down is not strong enough A 10KQ resistor strength is suggested in the Intel XP43X Product Line of Network Processors Datasheet for these pull ups Table 17 shows the serial port resistor signal and values Serial Port Resistors Signal Pull to Value Resistor Value URT_CTSO_N T3 3V 10 KO URT RXDO GND 10 KO URT CTS1 N T3 3V 10 KO URT_RXD1 GND 10 KQ FXS and FXO Functions FXS Ports The IXP435 reference platform has integrated two Si3216 wideband SLIC codecs from Silicon Laboratories to support two FXS ports in the VoIP applications The Si3216 is a dual mode wideband 50 Hz 7 KHz narrowband 200 Hz 3 4 KHz codec with 16 bit 16 KHz sampling Both the Si3216 SLIC Codecs are connected to the HSS port of the IXP43X network processors
12. information is displayed Trying NPE C success Using NPE C with PHY 1 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 55 A 3 Note Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Ethernet eth0 MAC address 00 07 e9 16 34 72 IP 192 168 200 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 02 built 15 43 18 Nov 22 2006 Platform IXP435 reference platform xscaie BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc RAM 0x00000000 0x08000000 0x0002a350 0x07f c1000 available FLASH 0x50000000 0x51000000 128 blocks of 0x00020000 bytes each Executing boot script in 3 000 seconds enter C to abort Once you have verified that the RedBoot image is functional you can update the primary image Using RedBoot to Update RedBoot RedBoot must execute from RAM to program the image into flash since the primary RedBoot image runs from flash Follow the steps mentioned below to update the primary image 1 Load and execute redboot RAM srec load v redboot RAM srec Using default protocol TFTP Entry point 0x00100040 address range 0x00100000 0x001761d4 gt go Trying NPE C success Using NPE C with PHY 1 Ethernet eth0 MAC address 00 07 e9 16 34 72 IP 192 168 200
13. memory for implementation The I2C EEPROM of 2 Kbytes is implemented for the Media Processor Table 7 Supported Memory Configuration for Media Processor pose Memory PAR memory Number era Sari Suggested Memory Device echnology Arrangement of Chips system Size 256 MBit 16M x 16 P 1 64 MB erc NAM Figure 6 PNX1702 and DDR Memory Topology Aowsa Haa PNX1702 DQ 15 0 DQS 1 0 DQM 1 0 DQ 31 16 DQS 3 2 Other names and brands may be claimed as the property of others DDR MEMORY 1 DDR MEMORY 2 A 12 0 BA 1 0 RAS CAS WE CS CK ci CLK DQ 15 0 DQS 1 0 DQM 1 0 A 12 0 BA 1 0 RAS CAS WE CS CK CL CLK DQ 15 0 DQS 1 0 DQM 1 0 B6529 01 The boot modes are defined by the state of the BOOT_MODE 7 0 pins at reset time Place adequate pull ups and pull downs on the system board to select the correct mode The different boot modes based on the state of the BOOT_MODE 7 0 pins are described in Table 8 June 2007 Document Number 316848 Revision 001US Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 21 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Table 8 PNX1702 Configuration Strapping Boot Mode Settings Boot mode GPIO Default value Function Description bits Pins upon bootup P 7 11 0 EN PCI ARB 1 Enables the internal PCI system arbite
14. port 2 activity Link active D12 1 Green Blinking Green VoIP port 1 activity Link active D12 2 Green Blinking Green VoIP port 2 activity Link active D13 1 Green Blinking Green FXO port 1 activity Link active D13 2 Green Blinking Green Table 21 provides indication for the RJ45 Jack Green Link activity Yellow 10 100 Mbps illuminates when connected to a 100 Mbps network Table 21 Ethernet LED Indicators LEDs of RJ45 Jack LED Indication when on Color 5 Ethernet LEDs Traffic status Link activity Green 5 Ethernet LEDs Traffic status 10 100 Mbps Yellow Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 43 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 17 Expansion Bus and LED Circuit Topology Dg GREEN LED X2 Power on indicator i R678 PRET ER EE 470 i SYSTEM RESET al EEE nm v vr 1 13 RESET LED Ta 03414 L3 5 C421 D tuF hH j 4 E PB CS2 N oer 3 15 Debug Circuitry An Intel 10 100 EthernetPro Adapter card using the Intel 82559 Ethernet PHY component can be plugged into a PCI slot and used as the debug Ethernet port 3 16 visionl CE Raven Emulator I nterface The Intel IXP43X Product Line of Network Processors can be controlled during debug through a JTAG interface t
15. ships with 16 Mbytes The FLASH STS pin on the flash is unused It is pulled up through a 4 7 KO resistor since it is an open drain output A 0 1 pF ceramic capacitor is connected between each of the three Vcc pins of the device and the ground In addition a 4 7 uF electrolytic capacitor is placed between VCC and GND at the array s power supply connection NAND Flash The IXP435 reference platform has integrated 64 MB NAND type Flash memory for storing persistent image and data larger than 16M bytes The R B pin should be pulled high GPIO12 is used as the chip select for the NAND Flash The NAND Flash is connected on the expansion bus EX D 7 0 Expansion bus addresses 0 and 1 are assigned for the ALE address latch enable and CLE command latch enable function accordingly Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Document Number 316848 Revision 001US 29 intel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide 3 7 3 DDRII Memory The memory controller of the IXP43X network processors support 128 256 512 Mbit 1 Gbit DDR SDRAM and 256 512 Mbit DDRII SDRAM technologies The total memory size supported are 32 Mbytes to 1 Gbytes for 32 bit DDR SDRAM and 64 MBytes to 512 MBytes for DDRII SDRAM The IXP435 reference platform is populated with 128 MB DDRII 400 MHz memory Two MT47H32M16
16. the SPI control interface of SLICs are also driven by the SPI port of the IXP43X network processors Two GPIOs are used for SLICs interrupts The Si3216 chips are used as the linefeed interface and two RJ11 ports are provided for connection to the telephone Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Document Number 316848 Revision 001US 39 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 15 Intel 1XP43X Product Line of Network Processors and SLI C CODEC Topology Interface between Intel IXP 435 Network Processor and SLIC CODEC SLIC A IRQ N GPIO3 SLIC_RST_N1 SSP_SFRM SSP_SCLK SSP_TXD SSP_RXD HSS_TXCLKO PCM_CLK HSS TXDATAO PCM RXDATA HSS RXDATAO PCM TXDATA HSS RXFRAMEO PCM FRAME Intel IXP435 SLIC CODEC 3216 Network Processor B6535 01 3 12 2 FXO Port and Failover Port The FXO port of the IXP435 reference platform is designed with Si3050 from Silicon Laboratories for compliance with the regulations set by the major Telcos The failover relay will route the FXS ports to the telephone line in the power failure condition Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 40 Document Number 316848 Revision 001US User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform Figure 16 Intel IXP43X Product Line of Network Processors and
17. 001US 28 User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform n tel 3 6 2 3 6 3 3 7 Table 11 3 7 1 3 7 2 June 2007 Expansion Bus Clock Generation The expansion bus clock is generated from a GPIO 15 and its frequency is software selectable by writing to the GPIO Clock Register Expansion Bus Chip Selects The IXP435 reference platform supports up to 4 devices on the expansion bus The expansion bus chip selects listed in Table 11 are assigned to allow for support of the Intel IXDP465 Development Platform mezzanine cards that is legacy support Also the connectors used are identical in size and pinout as those used on the Intel IXDP465 Development Platform A second connector on each mezzanine card allows for expansion of the expansion data bus to 32 bits and future expansion Memory Subsystem Expansion Bus Chip Select Assignments Chip Select Device Assignment CSO P30 NOR Flash csi UTOPIA 2 and MII connector CS2 LED circuit CS3 For test only The IXP435 reference platform has 128 Mbytes DDRII memory 16 Mbytes NOR Flash memory and 64 Mbytes NAND Flash memory BootROM You can install either an Intel StrataFlash Embedded Memory P30 or PC28F128J3D memory on the IXP435 reference platform The flash is connected to the expansion bus of the IXP43X network processors The IXP435 reference platform supports 8 Mbytes to 16 Mbytes of flash and
18. 1 Ethernet ethl MAC address 00 03 47 df 32 aa IP 192 168 200 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 02 built 15 43 18 Nov 23 2006 Platform IXP435 reference platform Intel XScale processor BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc RAM 0x00000000 0x08000000 0x0002a350 0x07fc1000 available FLASH 0x50000000 0x51000000 128 blocks of 0x00020000 bytes each RedBoot gt 4 Use the RedBoot fis list command to review the flash segment content as known to RedBoot Example RedBoot gt fis list Name FLASH addr Mem addr Length Entry point RedBoot 0x50000000 0x50000000 0x00080000 0x00000000 redboot bak 0x50800000 0x50800000 0x00080000 0x00000000 FIS directory Ox51FE0000 Ox51FE0000 0x0001F000 0x00000000 RedBoot config Ox51FFF000 O0x51FFF000 0x00001000 0x00000000 58 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 57 n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 58 Document Number 316848 Revision 001US
19. 2007 16 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel Figure 4 Intel 1XP43X Product Line Functional Block Diagram HSS UTOPIA2 MII North AHB 133 32 MHz x 32 bits MII North AHB Arbiter High Speed UART 921 Kbaud om Interrupt APB 66 66 MHz x 32 bits Queue Status Bus 16 32 Bits DDRII I ECC DDR 266 SI Lm QUEUE AHB AHB MEMORY DBE 400 d MANAGER BRIDGE CONTROLLER Master UNIT om BRIDGE 266 400 South AHB 133 32 MHz x 32 bits South A AHB pimens Arbiter USB Port USB Port Expansion Bus PCI Intel XScale Controller Controller Controller Controller Processor Version 2 0 Version 2 0 8 16 bit 32 bit 33 MHz 80 MHz 32 KBI CACHE UTMI UTMI 32 KB D CACHE 2 KB MINI D CACHE 2 0 PHY 2 0 PHY 266 400 533 667 MHz Controller MPI 133 32 MHz 200 MHz x 64 bits Host Host Master on South AHB Bus Arbiters XI master on North AHB Slave Only AHB Slave APB Master B6514 01 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 17 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Table 5 3 2 1 PCI Interface The IXP435 reference platform supports the following four PCI devices as shown in
20. 9 312 1 CSI E 39 3 12 2 FXO Port and Failover POU sensis aasan aa 4595 95 a ni ra dana dA nsns nns nnn nnn 40 SUS er Le en EE 42 3 14 LED Indicators 2 oie enia tace dator sapete Se weew slab Meh ds Deed Gale abentvan Deb ere div E ean 43 3 15 MBI sreeceUig ee cR mE 44 3 16 visionICE Raven Emulator Interface ssssessesseesseeeeee nennen ense nnn 44 3 17 Additional JTAG Connectors c ssasa ss ago c asse cs eas aaa gran ea Re naei e KaR RRR anas nana nnn 45 oM DIM MO IIR TTT 46 cM aBee T 49 3 20 NES dedu EET H 50 4 0 Key Components of the Intel IXP435 Multi Service Residential Gateway Reference Platform a sene one rede wis na pr cun xen aptas eI uu treinta eR Goa e e LR PR RR RR ake 51 5 0 Mechanical and PCB Stack Up ccc nemen nnn 52 6 0 Regulatory Guidelines sese eee 53 6 1 Environmental Guidelines sssssssssesssseseessee esee n nasus ana sus ansa rn sn nn 53 6 2 Quality Requirements wiccictisiecenscst bestie nacre te suada cre dRE RD cabt dac a a eG E ERE RO SEN De RM LA ea 53 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 3 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide A Updating the Int
21. B_TXDATA1 110 EX_ADDR3 31 5 0V 71 ETHB_CRS 111 EX_ADDR2 32 3 3V 72 ETHB TXDATAO 112 EX ADDR5 33 5 0V 73 12V 113 EX ADDR4 34 3 3V 74 2 5V 114 EX_ADDR7 35 5 0V 75 12V 115 EX_ADDR6 36 3 3V 76 2 5V 116 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 35 intel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Table 14 Intel 1XP435 Multi Service Residential Gateway Reference Platform MII Mezzanine Connector Pin Definition Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 37 5 0V 77 12V 117 GND 38 3 3V 78 2 5V 118 EX_ADDR9 39 5 0V 79 12V 119 EX_ADDR8 40 3 3V 80 2 5V 120 3 8 1 Multi Gang J ack The IXP435 reference platform contains a 5 port RJ 45 gang jack with integrated magnetics Each port has two LEDs one green one yellow controlled by the PHY The software programs the PHY through the MII interface to illuminate the LEDs according to certain events such as activity half full duplex 10 100 MHz and so on Figure 14 shows the integrated magnetics within the gang jack Figure 14 RJ 45 Jack with Integrated Magnetics RX 1 1 RX L CT 4 e RX 2 2 RX d 1CT 1CT 9 erp RECEIVE LED 10 TX 3 3 TX e CT 5 e YELLOW d amp 11 TX 6 6 TX RIGHT 1CT 1CT i5 HED TRANSMIT 4 70 5 7 0 001 pF 8 0 8 B6534 01 Intel IXP435 Multi Serv
22. CC 5E 32M x 16bit The DDRII implementation on the IXP435 reference platform is solder on board Table 12 Supported DDRII Memory Configurations DDRSDRAM DDR SDRAM of 3 Total Page Technology Arrangement Banks Address Size Leaf Select Memory Size Size Row Column DDR BA 1 DDR BA O 1 128 MB 4 KB 32M 8 13 10 ADDR 27 ADDR 26 2 256 MB 4 KB 256 Mbit 1 64 MB 2 KB 16M 16 13 9 ADDR 26 ADDR 25 2 128 MB 2 KB 1 256 MB 4 KB 64M 8 14 10 ADDR 28 ADDR 27 2 512 MB 4 KB 512 Mbit 1 128 MB 4 KB 32M 16 13 10 ADDR 27 ADDR 26 2 256 MB 4 KB Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 30 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel Figure 10 DDRII Memory Topology BANKO 20611901 WVAAS Wadd Network Processor DDR CS RO DPS a DQ 1 0 D DQB 0 D MA 12 0 _ Md A 2 0 DDR CS RO D CS N 0 CS D RAS N 1 i RAS DCAS IN _ CARR D WEN _ os wee D DM 3 9 DPR DM RTOs LDM UDM D BA I 0 LJ 4 4 9 RAI D CKE 0 4T1 4 9 CKE D S DDR _DQS_R 1 0 che D DQS 3 0 e _ 1 4111 BDDR DOs I0 5 LDQS UDQS D ODI 0
23. CI Peripheral Component Interface PHY Physical Layer Layer 1 Interface Reserved A field that may be used by an implementation Software should not modify reserved fields or depend on any values in reserved fields RX Receive HSS is receiving from off chip SDRAM Synchronous Dynamic Random Access Memory Ti Type 1 trunk line TX Transmit HSS is transmitting off chip UART Universal Asynchronous Receiver Transmitter UTOPIA Universal Test and Operation PHY Interface for ATM DVI Digital Video Interface CVBS Composite Video Baseband Signal LCD Liquid Crystal Display CCIR 656 CCIR Recommendation 656 WAN Wide Area Network 858 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 10 Document Number 316848 Revision 001US User s Guide I ntel 1XP435 Multi Service Residential Gateway Reference Platform n tel 2 0 2 1 June 2007 Intel 1XP435 Multi Service Residential Gateway Reference Platform Hardware Design This chapter provides detailed design information of all interfaces components and features contained on the Intel IXP435 Multi Service Residential Gateway Reference Platform The Intel IXP43X Product Line of Network Processors is positioned to enable both cost sensitive Gateways and Converged Access Platforms CAP The platform has integrated SLIC codecs and DAA circuitry for VoIP and Philips PNX1702 Nexperia media processor to support media centric applications s
24. CK 10KQ pull up 10 GND GND 11 RTCK GND 12 GND GND 13 TDO 10KQ pull up 14 GND GND 15 SRST_N Reset circuitry BDMR 16 GND GND 17 DBGRQ 18 GND GND 19 DGBACK 20 GND GND Note The J2 must be ON for ICE mode and J3 must be ON for normal mode 3 17 Additional J TAG Connectors As debug development tools for Media Processor JTAG connectors CON2 are provided as shown in Table 23 Table 23 Additional J TAG Connectors pull down DNP i i Pin Connect Pin Pin Name Connect To Pin Name To 1 DBG RST N 10KQ pull up 2 GND GND 10KQ pull up option for 10KQ 3 TDI pull down DNP 4 GND GND 5 TDO 10KQ pull up 6 GND GND 7 TMS 10KQ pull up 8 GND GND 9 TCK 10KQ pull up option for 10KQ 10 GND GND June 2007 Intel IXP435 Multi Service Residential Gateway Reference Platform Document Number 316848 Revision 001US User s Guide 45 a n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 18 JTAG Interface Locations CON4 CON2 B6542 01 3 18 Power Power rails are generated on the IXP435 reference platform The following voltages are provided 12V 3 3V 1 3V 1 4V 1 8V 0 9V 2 6V 5V and GND The power sequences are mentioned below 1 12V 3 3V gt 1 8V gt 0 9V gt 1 3V IXP43X network processors 2 12V gt 3 3V gt 1 4VDSP gt 2 6V 3 12V gt 5V The 3 3 V I O voltage VCCP and the 1 8 V I O voltage VC
25. CM are powered up at least 1 us before the core voltage VCC The core voltage VCC of the IXP43X network processors must not become stable prior to 3 3 V I O voltage VCCP or the 1 8 V I O voltage VCCM Sequencing between VCCP and VCCM can occur in any order with respect to one another e VCCP prior to VCCM e VCCM prior to VCCP Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 46 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel e VCCP simultaneously to VCCM The VUSBAUPLL VUSBCORE VCCA 1 3V follow the VCC voltage power up pattern The VCCP OSC Vccpusb and Vccaubg voltage 3 3V follows the VCCP voltage power up pattern The value for TPOWER UP should be at least 1 us after the later of VCCP and VCCM reaches stable power The TPOWER UP timing parameter is measured between the later of the I O power rails VCCP at 3 3 V or VCCM at 1 8 V and VCC at 1 3 V The USB ports of IXP43X network processors have a special requirement on power up sequence if USB V5ref is connected to a 5V power supply The USB V5ref ports to be powered up are e USB Vbref prior to VCCP e If USB Vbref is powered up simultaneously to VCCP Voltage level at pin USB V5ref must be equal to or higher than VCCP No special power sequence is required for the Media Processor PNX1702 To enable MM CKE remain low at power up it is
26. D Ground 19 EXPB A9 I 20 EXPB CLK I 21 DGND Ground 22 DGND Ground 23 EXPB DO IO 24 EXPB D2 UO 25 EXPB_D1 UO 26 EXPB_D4 UO 27 ADSL_RST_N GPIO 4 28 ADSL_GPIO1 GPIO 5 29 EXPB_D3 UO 30 EXPB_D6 UO 31 EXPB DS UO 32 EXPB_D7 UO 33 DGND Ground 34 DGND Ground 35 EXPB_WR_N I 36 EXPB_RD_N I 37 RESERVED 38 RESERVED 39 RST_N I 40 UTP_CS_N I 41 DGND Ground 42 DGND Ground 43 EXPB_ALE I 44 3 3 VD Power 45 TDI I 46 3 3 VD Power 47 TDO Oo 48 3 3 VD Power 49 DGND Ground 50 DGND Ground 51 3 3 VD Power 52 3 3 VD Power 53 TCK I 54 TMS I 55 2 5 VD Power 56 2 5 VD Power 57 DGND Ground 58 DGND Ground 59 EXPB A21 I 60 EXPB A22 I Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 37 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Table 15 Utopia Mezzanine Connector Pin Definition Sheet 2 of 2 Pin Name Signal type Pin Name Signal type 61 DGND Ground 62 DGND Ground 63 3 3 VD Power 64 DSL IOWAIT N O 65 3 3 VD Power 66 DGND Ground 67 DGND Ground 68 EXPB_A23 I 69 UTP_RX_CLK I 70 DGND Ground 71 DGND Ground 72 UTP_TX_CLK I 73 UTP_RXD1 O 74 DGND Ground 75 RESERVED 76 UTP_TXD2 I 77 UTP_RXDO O 78 UTP_TX_EN I 79 UTP_RXD2 O 80 DGND Ground 81 UTP_RX_CLAV O 82 UTP_TXDO I 83 DGND Ground 84 UTP_TXD1 I 85 UTP_T
27. E MAC On Chip Frame Buffers 10 100 MAC 1 10 100 MAC 2 10 100 MAC 3 10 100 MAC 4 10 100 MAC 5 net C Ether NPE MAC net A KS8995MA Other names and brands may be claimed as the property of others 10 100 PHY 1 10 100 PHY 2 10 100 PHY 3 10 100 PHY 4 10 100 PHY 5 i B6532 01 Figure 12 NPE A UTOPI A MII Pin Switches Topology GPIO 0 Intel UTOPIA Connector GPIO 4 IXP435 For ADSL Module cpio 5 Network GPIO 5 Processor GPIO 0 Intef SW Kendin Switch8995M IXP435 For WAN port GPIO 4 4 amp 5 Network Processor GPIO 0 GPIO 5 SW MII 0 Connector GPIO 4 687 For VDSL Module GPIO 5 NPEA SPST DIP SWITCH B6533 01 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 32 Document Number 316848 Revision 001US User s Guide I ntel 1XP435 Multi Service Residential Gateway Reference Platform Table 13 WAN Port Multi function Switch Settings intel Function SW 4 SW 5 SW 6 SW 7 SW 3 for GPIO 0 4 5 Pin 1 2 3 ON Ethernet switch 1 Pin 3 OFF Pin 4 5 6 OFF ra 8995M WAN All ON others ON All OFF All OFF Pin 7 ON Pin 8 OFF Pin 1 2 3 ON MII Connector for i Intel LXT972 LAN All OFF All OFF Fina OFF All ON ea module Others ON Pin 7 ON Pin 8 OFF Pin 1 2 3 ON U
28. GPIO7 are used to do these control Refer to Table 18 for setting these values Ethernet FXS and FXO Control Description SSP CSO GPIO 6 SSP CS1 GPIO 7 Ethernet switch 1 X FXS select 0 FXO select 0 1 Do not connect the FXS FXO and Failover to the PSTN These ports must be connected in the laboratory environment only GPIO The GPIOs are mapped to many purposes on the IXP435 reference platform The GPIO signals are used as interrupt and clock source to some peripherals The default state for GPIO 14 and 15 are user programmable output with the default state being a 33 MHz output The clocks are supplied to the Expansion bus clock GPIO 14 and PCI clock GPIO 15 respectively Refer to Table 19 for GPIO assignment Because of hardware limitations some GPIOs are shared with the mezzanine card for NPE A These shared signals involve installing 0Q resistors that do not come factory installed For further information refer the baseboard schematics for exact resistor installation options that support different NPE A related platform configurations Intel IXP43X Product Line of Network Processors GPIO Assignment Intel I XPAXX Product Line of PET SUSCIPI Network Processors Net Name Description VDSL Interrupt MII connector GPIOO DSL_INT_N used or ADSL Interrupt UTOPIA connector used GPIO1 REMOTE_IR SW_KEY_N Lu receive data SW KEY GPIO2 SLIC IR
29. Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 4 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel 21 Ethernet LED Indicators ooo ERR Ext a eni mU AK AEEA 43 22 JTAG COMMCCCOIS E 45 23 Additional JTAG Connectors icti I ed de sans e bx mee rod bx E Codecs AKS KRA TR al YS Vah 45 24 Power Consumption EStifmablOri es caer eee eztoe rue tic a E uias ne a ER DR x nS 48 25 Overview of the Key Components aX 95 2 55 aX nna avra rasa Rae ska ERR KE EN RR RR YR na dR aR Y 51 26 PCB Stack Up iius ee erra kh a Ra FREE RDKRE etnies tava SQAR 4 DRY RPTARERIPRA Y reds SESTRSXSRR ra Eas 52 27 Environmental Ranges cesses tke stands saa 520 Y AT O ed yas fe Rr YORK TAE a ER ERR EFIE GA 53 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 5 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Revision History Date Revision Description June 2007 001 Initial release Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 6 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel 1 0 1 1 1 2 1 3 June 2007 Introduction
30. Q N Interrupt for FXS and FXO GPIO3 SLIC RST N FXS Reset and FXO Reset GPIO4 VDSL_RST ADSL_RST_N VDSL Reset ADSL SW Reset GPIO5 VDSL RLS ADSL GPIO1 VDSL Release ADSL Test SPI Chip Select for DMUX VOIP GPIO6 SSP_CSO and Switch GPIO7 sep CS1 SPI Chip Select for DMUX FXS and FXO GPIO8 PCI3_IRQ_N PCI Slot IRQ GPIO9 PCI2_IRQ_N Mini PCI IRQ GPIO10 PCI1 IRQ N Mini PCI IRQ WiFi used GPIO11 DSP IRQ N For Media Processor PNX1702 PCI interface GPIO12 NAND CS N NAND Flash chip select GPIO13 IO RESET N All of peripheral Reset GPIO14 PCI CLK PCI Clock GPIO15 EXP CLK Expansion Bus Clock Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 42 June 2007 Document Number 316848 Revision 001US m User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform n tel 3 14 LED Indicators Expansion bus and latch circuit are used for LED indicators function Refer to Table 20 for LED indicator Table 20 LED I ndicators LED LED Indication when on posed init Color Reset System is in reset D9 1 Green Power LED 12V powered up D9 2 Green Wireless LAN Mini PCI 1 activity Link active D10 1 Green Blinking Green Wireless LAN Mini PCI 2 activity Link active D10 2 Green Blinking Green PCI Slot activity Link active D11 1 Green Blinking Green USB port 1 activity Link active D1i 2 Green Blinking Green USB
31. S User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform intel Table 14 Intel 1XP435 Multi Service Residential Gateway Reference Platform MII Mezzanine Connector Pin Definition Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX ADDR11 41 5 0V 81 2 EX_ADDR10 42 3 3V 82 3 EX_ADDR13 43 TEST 83 VDSL_RST_N1 4 EX_ADDR12 44 GPIO 4 of the IXP43X 84 network processors EX_DATA1 5 EX_ADDR1i5 45 GND 85 EX DATAO 6 EX ADDRi14 46 GND 86 EX DATA3 7 GND 47 87 VDSL RLS GPIO 5 of EX DATA2 8 GND 48 the IXP43X network 88 processors MIIO GPIOO 9 EX ADDR17 49 z 89 MIIO_GPIO1 10 EX_ADDR16 50 RST_N 90 EX_DATA5 ir EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 ETHB TXEN 92 EX DATA7 13 EX ADDR21 53 93 EX DATA6 14 EX ADDR20 54 ETHB RXDV 94 GND 15 EX ADDR23 55 GND 95 GND 16 EX ADDR22 56 ETHB RXCLK 96 EX DATA9 17 GND 57 ETHB_RXDATA3 97 EX_DATA8 18 GND 58 GND 98 EX_DATA11 19 EX_CLK_MIIO 59 ETHB_RXDATA2 99 EX_DATA10 20 EX_RD_N 60 ETHB_TXCLK 100 21 GND 61 ETHB_RXDATA1 101 22 EX_WR_N 62 ETHB_COL 102 EX_DATA13 23 EX_ALE 63 ETHB_RXDATAO 103 EX_DATA12 24 EX_RDY_NO 64 ETHB_TXDATA3 104 EX_DATA15 25 EX_IOWAIT_N 65 GND 105 EX_DATA14 26 ETHB_INT_N GPIO 0 66 ETHB_TXDATA2 106 GND 27 EX_CS_N4 67 ETH_MDC 107 GND 28 3 3V 68 GND 108 EX_ADDR1 29 69 ETH_MDIO 109 EX_ADDRO 30 3 3V 70 ETH
32. Sheet 1 of 2 Speed Factory Part Speed EX_ADDR 23 EX_ADDR 22 EX_ADDR 21 Actual Core Speed 667 MHz 1 X X 667 MHz 667 MHz 0 0 0 667 MHz 667 MHz 0 0 1 533 MHz 667 MHz 0 1 0 266 MHz Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide 26 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform Table 10 Configuration Strapping Clock Settings JP3 Sheet 2 of 2 intel Speed Factory Part Speed EX ADDR 23 EX ADDR 22 EX ADDR 21 Actual Core Speed 667 MHz 0 1 1 400 MHz 533 MHz 1 X X 533 MHz 533 MHz 0 0 0 533 MHz 533 MHz 0 0 1 533 MHz 533 MHz 0 1 0 266 MHz 533 MHz 0 1 1 400 MHz 400 MHz 1 X X 400 MHz 400 MHz 0 0 0 400 MHz 400 MHz 0 0 1 400 MHz 400 MHz 0 1 0 266 MHz 400 MHz 0 1 1 400 MHz 266 MHz X X X 266 MHz June 2007 Document Number 316848 Revision 001US Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 27 Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide l n tel 7 Figure 9 shows the location and default settings of all Expansion Bus Address Strap Switches Figure 9 J P3 Switch Location B6540 01 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision
33. TMS 2 2 2 SCALER SCALER FILTER TCK BORDER VIDEO bins TRIPLE DAC GREEN VBS CVBS GENERATOR ENCODER RED_CS_CVBS SAA7104E HD SAA7105E OUTPUT PIXEL CLOCK CRYSTAL TIMING I C BUS T x HSM CSYNC SYNTHESIZER OSCILLATOR GENERATOR CONTROL TVD FSVGC CBO SDA SCL RESET 27 MHz VSVGC HSVGC TTX_SRES TTXRQ_XCLKO2 Other names and brands may be claimed as the property of others B6530 01 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 Document Number 316848 Revision 001US User s Guide 24 m User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform n tel 3 5 Audio DAC Philips UDA1334BTS component is used as the audio output circuit The UDA1334BTS supports the I2S bus data format with word lengths of up to 24 bits and the LSB justified serial data format with word lengths of 16 20 and 24 bits The UDA1334BTS has basic features such as de emphasis at 44 1 KHz sampling rate and mute The high level view of the UDA1334BTS Audio DAC is shown in Figure 8 Figure 8 Audio DAC Block Diagram V bpp V ssp 5 LX BCK 3 WS DIGITAL INTERFACE DATAI UDA1334BTS DE EMPHASIS p SYSCLK l S MUTE DEEM INTERPOLATION FILTER SFORO NOISE SHAPER VOUTL VOUTR VopA Vesa VregpAC B6531 01 3 6 Expansion Bus Loading The IXP435 reference platform is tuned to drive up to 4 loads yet the devices on the expansion bus may not be able to quickly drive such a l
34. TOPIA Connector for Pin3 ON Pin3 ON Pin 4 5 6 OFF ADSL module are Others OFF Others OFF pare Pin 7 ON Pin 8 OFF June 2007 Document Number 316848 Revision 001US Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 33 L n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 13 UTOPIA MII Pin Switches Location SW3 4 5 6 7 sanina B6541 01 Enabling of HSS and Ethernet coprocessors in NPE A may have a performance impact to the Ethernet throughput thus the LAN and the WAN port are connected to NPE C and NPE A respectively In addition to the Ethernet WAN port one WAN MII mezzanine interface that is NPE A is available for connectivity to the other transport module Hardware dip switch is used to disable the WAN connection to the KS8995M Ethernet switch Table 14 shows the pin definition of the WAN MII mezzanine interface this interface is compatible with the MII mezzanine interfaces on the Intel IXDP465 Development Platform baseboard Note The MII and UTOPIA signal pins are shared the hardware dip switch should be configured to select the proper signal set The MII signal Expansion Bus signals and three GPIO pins GPIO 0 4 amp 5 are routed to the MII mezzanine connector Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 34 Document Number 316848 Revision 001U
35. Voice DAA Topology GPIO2 GPIO3 SSP SFRM SSP SCLK SSP TXD SSP RXD HSS TXCLKO HSS TXDATAO HSS RXDATAO HSS RXFRAMEO Intel IXP435 Network Processor and VOICE DATA Other names and brands may be claimed as the property of others Interface between Intel IXP 435 Network Processor FXO_INT_N FXO RESET N PCM RXDATA PCM TXDATA PCM FRAME 13050 B6536 01 The FXS and FXO circuit has an external PCM Clock source that is implemented on 2 048 MHz Oscillator circuit 20ppm The jumpers J8 and J9 are used to select the required PCM Clock source internal PCM Clock source or external PCM Clock source The default value is set for internal PCM Clock source which comes from the HSS interface of the IXP43X network processors The default value for J8 and J9 are opened The FXO reset signal is controlled in the same way as FXS reset signal that originates from GPIO 3 The FXO interrupt signal is controlled in the same way as the FXS interrupt signal that originates from GPIO 2 June 2007 Document Number 316848 Revision 001US Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 41 intel Table 18 Warning 3 13 Note Table 19 Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide The Ethernet switches FXS and FXO are shared with one SPI bus of the IXP43X network processors two Demultiplexers and two GPIOs GPIO6 and
36. XD7 I 86 UTP_TXD3 I 87 UTP_TXD4 I 88 UTP_TXD5 I 89 UTP_TXD6 I 90 DGND Ground 91 DGND Ground 92 UTP_TX_CLAV O 93 UTP_RXD7 0 94 UTP_TX_SOC I 95 UTP_RXD3 Oo 96 DGND Ground 97 UTP_RXD5 0 98 UTP_RXD4 O 99 UTP_RX_SOC 0 100 UTP_RXD6 Oo 101 UTP RX EN I 102 RESERVED 103 DGND Ground 104 DGND Ground 105 UTP RXA4 I O 106 UPT_TXA4 I O 107 UTP RXA3 I O 108 UTP TXA3 I O 109 DGND Ground 110 UTP TXA2 I O 111 UTP RXA2 I O 112 DGND Ground 113 UTP RXA1 I O 114 UTP TXA1 I O 115 UTP RXAO I O 116 UTP TXAO I O 117 RESERVED 118 RESERVED 119 5 VD Power 120 5 VD Power 3 10 USB 2 0 Two Type A USB host receptacles are provided at the board edge the USB host interface is compliant with USB2 0 The interface is capable of operation at 1 5 Mbits s 12 Mbits s and 480 Mbits s 3 11 Serial Port One asynchronous serial I O port UART with flow control is provided The port is routed to 9 pin DB connectors with RTS and CTS flow control The system supports baud rates of 115200 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 38 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform Table 16 3 11 1 Table 17 3 12 3 12 1 June 2007 intel The port is wired according to the RS 232 specification for data communication equipment Straight serial cable connects to the host PC Table 16 shows the pin definitions for the serial port DB 9
37. ached to the PCI XIO bus 10 Set up the PNX1702 system in host assisted mode and allows the host CPU to finish to configure the PNX1702 1 0 1 11 BOOT MODE system and start the TM3260 CPU B 11 Boot from an I2C EEPROM attached to the I2C interface EEPROMs of 2 to 64 KB are supported The entire system can be initialized in a custom fashion by the boot commands contained in the EEPROM This mode can be used for standalone or host assisted boot mode when the other internal boot scripts are not meeting the specific requirements of the application In this mode the boot script is in the EEPROM to define and understand the EEPROM content The default state of the BOOT_MODE 3 0 pins are determined by the internal pull ups and pull downs present in the I Os of PNX1702 The BOOT_MODE 7 4 pins must be pulled up or down at board level to ensure proper boot operation Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 22 Document Number 316848 Revision 001US m User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform n tel 3 4 Video Encoder Philips SAA7104H component is used as the video output circuit on the IXP435 reference platform The SAA7104H is an advanced next generation video encoder that converts PC graphics data at a maximum 1280 X 1024 resolution optionally 1920 X 1080 interlaced to PAL 50 Hz or NTSC 60 Hz video signals A prog
38. al Gateway Reference Platform intel Table 6 PCI Host Slot Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal Al PCI HST TRST NO A33 3 3V B1 PCI 12V NO B33 PCI HST CBE N2 A2 12 0 V A34 PCI HST FRAME N B2 PCI_LHST_TCKO B34 GND A3 PCI_HST_TMSO A35 GND B3 GND B35 PCILHST_IRDY_N A4 PCI_HST_TDIO A36 PCI_LHST_TRDY_N B4 PCI_LHST_TDOO B36 3 3V A5 5 0 V A37 GND B5 50V B37 PCI HST DEVSEL N A6 PCI HST INTA N A38 PCI HST STOP N B6 5 0V B38 GND A7 PCI HST INTC N A39 3 3V B7 PCI HST INTR N B39 PCI HST LOCK N A8 5 0 V A40 PCI HST SMBCLKO B8 PCI HST INTD N B40 PCI HST PERR N A9 A41 PCI HST SMBDATO B9 PCI HST PRSNT1 NO B41 3 3V A10 3 3V A42 GND B10 B42 PCI HST SERR N All l A43 PCI HST PAR B11 PCI HST PRSNT2 NO B43 3 3V A14 A44 PCI HST AD15 B14 B44 PCI HST CBE N1 A15 PCI HST RST N A45 3 3V B15 GND B45 PCI HST AD14 A16 3 3V A46 PCI HST AD13 B16 PCI HST CLKO B46 GND A17 PCILHST_GNT_NO A47 PCI HST AD11 B17 GND B47 PCI HST AD12 A18 GND A48 GND B18 PCI HST REQ NO B48 PCI HST AD10 A19 A49 PCI HST AD9 B19 3 3V B49 PCI HST M66ENO A20 PCI HST AD30 A50 GND B20 PCI HST AD31 B50 GND A21 3 3V A51 GND B21 PCI HST AD29 B51 GND A22 PCI_LHST_AD28 A52 PCI_LHST_CBE_NO B22 GND B52 PCI HST ADS A23 PCI HST AD26 A53
39. arge load To compensate for this the timings on the expansion bus are adjusted using network processor internal registers If an edge rises slowly due to low drive strength the IXP43X network processors must wait an extra cycle before the value is read There are no buffers to increase drive strength on the expansion bus although customers can choose to add buffers in their own designs 3 6 1 Expansion Bus Configuration Straps The expansion bus address lines EX ADDR23 EX ADDRO are used for configuration strapping options during boot up At the de assertion of reset the values on these lines are read to determine the board configuration The default configuration strapping is shown in Table 9 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 25 intel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Only address bits EX ADDR 23 21 are connected to the DIP switch The strapping options are connected through pull down resistors If the line is not pulled down the weak pull up internal to the IXP43X network processors will pull the line high Table 9 Configuration Strapping Options ER ADDR Name Description Bit 23 21 Clock Setting See Table 10 for details 20 17 Customer Customer defined bits 16 12 Reserved Reserved DDRI or DDRII mode selection 11 DDR M
40. ation Web Paget Designing Embedded Networking Applications 3 E Essential Insights for Developers of Intel IXPAXX N A AL QUEE Network Processor Systems Ixp EET http NX1702 Nexperia Media Processor of Philips N A R w www semiconductors philips com T This document is available at http www intel com design network products npfamily docs ixp4xx htm Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 8 June 2007 Document Number 316848 Revision 001US User s Guide I ntel 1 XP435 Multi Service Residential Gateway Reference Platform n tel Table 2 Related ntel Documentation Sheet 2 of 2 Title Saadi Location Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Customizing 254308 IXP4XX Documentation Web Paget RedBoot Application Note Intel IXDP465 Development Platform User s Manual IXP4XX Documentation Web Paget Intel xScale Core Developer s Manual 273473 IXP4XX Documentation Web Paget t This document is available at http www intel com design network products npfamily docs ixp4xx htm Table 3 Related External Documentation Title and Revision Location PCI Bus Specification Rev 2 2 http www pcisig com MiniPCl Specification 1 0 http www pcisig com UTOPIA Level 2 Specification Revision 1 0 http www atmforum com U
41. ay Reference Platform Primary Side Placement i5 ca Network Processor SW ome Sw FXO FXS FXS video 1702 POWER CODEC CODEC CODEC Decoder Circuit Circuit Circuit Circuit Ee Audi Encoder Jg das Power Switch B6516 01 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 14 m User s Guide I ntel 1XP435 Multi Service Residential Gateway Reference Platform n tel Figure 3 Intel 1XP435 Multi Service Residential Gateway Reference Platform Bottom Side Placement Mini PCI 2 suid oz vido1n 858 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 15 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide 3 0 Design Solution Description 3 1 Intel 1XP43X Product Line of Network Processors The Intel IXP435 Multi Service Residential Gateway Reference Platform is populated with 667 MHz IXP43X network processors Jumpers are provided to configure the default core execution speed through the hardware strapping configurations A 33 33 MHz oscillator acts as the input clock signal to the IXP43X network processors The high level view of the IXP43X network processors is shown in Figure 4 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June
42. ay cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s Web Site Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details BunnyPeople Celeron Celeron Inside Centrino Centrino logo Core Inside FlashFile i960 InstantIP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Core Intel Inside Intel Inside logo Intel Leap ahead Intel Leap ahead logo Intel NetBurst Intel NetMerge Intel NetStructure Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel Viiv Intel vPro Intel XScale Itanium Itanium Inside MCS MMX Oplus OverDrive PDCharm Pentium Pentium Inside skoool Sound Mark The Journey Inside VTune Xeon and Xeon Inside are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2007 Intel Corporation All rights reserved Intel IXP435 Multi Service Resi
43. dential Gateway Reference Platform User s Guide June 2007 2 Document Number 316848 Revision 001US m User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel Contents 1 0 Introduction ooi ies a a Deua E EURO Pra DE Ert UIN EUNT MUR EVE DODGE 7 1 1 PUI DOSCr m LP O 7 1 2 Intended Audience onere sere esca aa rk AEEA nr EAEE ci qe culi dea x Ra EG ad 7 uc EM PREMEQUISILES MEME T m 7 1 4 Related Documernitation secicesccieoindashiede cioe prr bi er Rr porAR PRSE NUR UN VR OUR NUT M RONDE MEME E 8 15 TERMINOLOGY AME Tm 9 2 0 Intel 1XP435 Multi Service Residential Gateway Reference Platform Hardware Desig EE 11 2 1 Overview of the Intel IXP435 Multi Service Residential Gateway Reference Platform 11 2 2 Functional and Physical Layout of the Intel IXP435 Multi Service Residential Gateway Reference Platfottri 2 dics coute zie 08 sence epe a Re wapa AARAA E ENTRE RM HEX MERDA 12 2 3 Component Placement cecceecect senses eens Vc kae hates 0 99 ARRA RAA TAYR RR KANG ARRA AR KER X Ea RX 5 14 3 0 Design Solution Description ssssssssssssse emen eene 16 3 1 Intel IXP43X Product Line of Network ProCeSSOrS eene 16 3 2 PGCLIntefface eee e dae ape d AAA aa mE dames lt u UN En SERA EERRA VEI AAAA NER DR M RS 18 3 2 1 PCIL CIOCKIIg uir en eea eee aeo iens aet bci afe EA i RR Ru tated EY GUN iud 18 3 3 Media Proces
44. e One UART Internal Bus Performance Monitoring Unit 16 GPIOs Four internal timers Synchronous Serial Protocol SSP port It is recommended that users have access to the documents listed in Table 2 and refer to them when necessary This document does not explore the IXP43X product line internal architecture but describes the processor s interfaces to peripherals that are used on the IXP435 reference platform Schematics and a bill of materials are available in the IXP435 reference platform Documentation Kit zip file that can be obtained through your local Intel sales representative Related Documentation Table 2 and Table 3 list the documentation from Intel and other sources that provide additional information for the development of hardware and software based on the IXP43X product line Related ntel Documentation Sheet 1 of 2 Title ic iE Location Intel 1XP435 Multi Service Residential Gateway N A Through your local Intel sales Reference Platform Documentation Kit representative Intel 1XP43X Product Line of Network Processors Through your local Intel sales 316843 Developer s Manual representative Intel 1XP43X Product Line of Network Processors Through your local Intel sales 316842 Datasheet representative Intel IXP400 Software Programmer s Guide 252539 IXP4XX Documentation Web Paget Intel IXP400 Software Specification Update 307310 IXP4XX Document
45. el 1 XP435 Multi Service Residential Gateway Reference Platform Flash Memory cres re nose en eene ke Pa xke us paces de kau ae ga ESTA Rare se TR EXT PryRawau a e EUR A TRT 54 A 1 Generic Flash Updating Using RedBoot sse cece e eee eee tenes ee ee eee eee menm 54 A 2 Creating a Backup Copy of RedBoot s ssczrs vrec os ve nese ee eee eee eee ee nR rnas swana TRS r 55 A 3 Using RedBoot to Update REdBoot ccccececeeeee tees ee ee eee tees eaten yanan gR aR RAO n 56 Figures 1 Intel IXP435 Multi Service Residential Gateway Reference Platform Functional Block Diagram 2 222 e a ceded Z aT an para RR r TEE al RABANUS dest Unt M P AEL 13 2 Intel IXP435 Multi Service Residential Gateway Reference Platform Primary Side Placement eei ssa tetas testae k d eR DXPA V A DEC EpE RM SER EA 14 3 Intel IXP435 Multi Service Residential Gateway Reference Platform Bottom Side Placerrient 2 ssrin te 25 e 43525 CES eria a EEA eed anne dad teagan HORN Pa 15 4 Intel IXP43X Product Line Functional Block Diagram sese 17 5 Philips PNX1702 Media Processor Functional Block Diagram sss 20 6 PNX1702 and DDR Memory Topology ccs sss ec rr rex rcas cece iniunat iE Ea 21 7 Video Encoder Functional Block DiaQram cccceceeeee nets eee eee eee eee eee eee a eens eens eee teens 24 8 Audio DAC Block Diagram eei ioter nhanh estes A TROER aa ceeds aided I RENER anaes 25 9 IPS THT s e 10 LOCATION TT 28 10 DDRII Memory TIOpOlOQg
46. ernal to 0 80 board processor Must be less than 70 C with ambient of 50 C Ambient pera a System non condensing temperature must be maintained at 50 C as measured at least 2 inches from containing the system under test product 6 2 Quality Requirements The IXP435 reference platform meets the Quality and Reliability requirements defined by 25GS3000 and IQUAL for Product Type Boards Product Sub type Reference Design Development Platform Usage Segment Home Network Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 53 m e n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Appendix A Updating the Intel 1XP435 Multi Service Note Note A 1 Residential Gateway Reference Platform Flash Memory RedBoot is the primary bootloader and it is used to boot Linux RedBoot is also used to update RedBoot The IXP435 reference platform is shipped with RedBoot v2 02 installed It reports its version as follows RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 02 built 15 43 18 Nov 23 2005 Platform IXP435 reference platform XScale BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc Once the IXP435 reference platform is running with your OS set up you may want to organize the flash content for your particular design Leaving the RedB
47. he IXP435 reference platform 1 VCC and VCC33 power supplies must reach steady state 2 Hold PWRON RST N and RESET IN N asserted for 2000 ns 3 De assert PWRON RST N signal goes high with the help of a pull up resistor 4 Continue to hold RESET IN N asserted for at least 10nSec more after releasing PWRON RST N 5 De assert RESET IN N signal goes high with the help of a pull up resistor 6 The network processor asserts DLL LOCK indicating that the processor has successfully come out of Reset Refer to the Intel IXP43X Product Line of Network Processors Datasheet for further information Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 49 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 20 Reset Circuit Topology Inte IXP 435 Network Processor Power TI TPS3825 on key POWER RESET N delay circuit POWER RESET N 200ms delay RESET IN N Flash Memory TI TPS3825 Tue delay REN MII I PCI 1 Connector ese zi Key ganna D MII I PCI_2 Connector ln Media Processor PNX U c Software m AND IO RESET ALL N PCI Slot Reser ET IO_RESET_N gate Ethernet Switch GPIO 13 Intel IXP435 Network Processor Peripheral GPIO1 Intel 9 1XP435 Network Processor PNX1700 POWER RESET N SAA7104 7118 RESET N IO RESET ALL N M RESET OUT N POR IN N Other names and brands may be
48. ice Residential Gateway Reference Platform User s Guide June 2007 36 Document Number 316848 Revision 001US User s Guide I ntel I XP435 Multi Service Residential Gateway Reference Platform intel 3 9 UTOPI A 2 Interface The IXP435 reference platform supports UTOPIA level 2 interface through a 2x60 pin mezzanine card connector Amp 5 179010 5 The pins of the UTOPIA 2 interface are multiplexed with MII interface NPE A The UTOPIA level 2 and Expansion Bus signals are routed to this connector to allow a variety of DSL PHY modules to be configured including PHY modules from the Intel IXDP465 Development Platform See Table 15 for the connector pin definitions Note All the IXP43X product line of network processors engine NPE functions require Intel supplied software For information about using this software see the Intel XP400 Software Programmer s Guide For information about the availability of this enabling software contact your Intel sales representative Table 15 Utopia Mezzanine Connector Pin Definition Sheet 1 of 2 Pin Name Signal type Pin Name Signal type 1 12VD Power 2 12VD Power 3 DGND Ground 4 DGND Ground 5 UTP_INT_N GPIO 0 0 6 EXPB_AO I 7 DGND Ground 8 EXPB_A2 I 9 EXPB_A1 I 10 DGND Ground 11 EXPB_A3 I 12 EXPB_A4 I 13 DGND Ground 14 EXPB_A6 I 15 EXPB A5 I 16 EXPB A8 I 17 EXPB A7 I 18 DGN
49. intel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 Document Number 316848 Revision 001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which m
50. mW milliamps D ProSLIC CODEC FXS Si3216 Si3201 3 3 47 155 DC DC RING Si3216 12 0 0 F Media system PNX1702 3 3 400 1240 DDR 2 5 Video and Audio In Out 3 3 G FXO S13050 3 3 40 132 Total 3814 3 19 Reset Logic The IXP435 reference platform implements the following reset scenarios 1 Power switch Power on reset Key This logic will reset all internal logic of the IXP43X network processors to a known state after the PLL has achieved a locked state The Power on the reset signal is 1 3V 2 HW Push button reset Hardware reset Key This logic will reset the IXP43X network processors and all the peripheral devices on board 3 SW Push button reset Software reset Key This reset logic will output the reset signal to the GPIO 1 of the IXP43X network processors The IXP43X network processors will reload and configure some parameters 4 JTAG reset from JTAG connector of the IXP43X network processors for any debug probe like EPI MAJIC probe This reset logic will reset the IXP43X network processors and all the peripheral devices on board 5 IO reset GPIO 13 This will reset all the peripheral devices This is implemented through GPIO 13 on the IXP43X network processors Software is able to control this reset logic Note The SW Push button reset Software reset key output is shared with IR Remote receive signal to output the reset signal to GPIO 1 of the IXP43X network processors Following are the reset sequencing requirements for t
51. niversal Serial Bus Specification Revision 1 1 http www usb org JEDEC Double Data Rate DDR SDRAM Specification JESD79D http www jedec org 1 5 Terminology Table 4 lists the acronyms and common terms used in this manual Table 4 List of Terminology Sheet 1 of 2 Acronym Description ADSL Asymmetric Digital Subscriber Line Assert Logically active value of a signal or bit ATM Asynchronous Transfer Mode CPE Customer Premise Equipment DDR Double Data Rate DMA Direct Memory Access DSL Digital Subscriber Line E1 Euro 1 trunk line FXO Foreign Exchange Office FXS Foreign Exchange Subscriber GPIO General Purpose Input Output HSS High Speed Serial port IP Internet Protocol IXP Internet Exchange Processor LAN Local Area Network LSB Least Significant Byte MAC Media Access Controller MDIO Management Data Input Output mezzanine A circuit board that attaches to the development platform baseboard and provides additional card functionality Mezzanine cards may be stackable Also called daughtercard Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 9 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Table 4 List of Terminology Sheet 2 of 2 Acronym Description MII Media Independent Interface MSB Most Significant Byte NPE Network Processor Engine P
52. o the processor The Macraigor Raven and Wind River Systems visionPROBE visionICE systems can plug into the JTAG interface through a 20 pin connector CON4 The main difference between the Raven and visionICE systems is the specific implementation of nTRST for each debugger The Macraigor Raven implementation actively drives nTRST high and low The Wind River Systems visionPROBE visionICE can configure nTRST active or open collector only drive low The application note Recommended JTAG Circuitry for Debug with Intel XScale Microarchitecture Doc Number 273538 001 located at http www intel com design iio applnots 273538 htm Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide June 2007 44 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform intel The Macraigor Raven and Wind River Systems visionPROBE visionICE systems will plug into the JTAG interface through a 20 pin connector defined in Table 22 Table 22 JTAG Connectors Pin Fin Connect To Pin Z Pin Name Connery Name To 1 VTREF 3 V3 2 VSUPPLY 3V3 10KQ pull up for ICE debug used 10KQ pull down for normal operation TRST also 3 TRST N generated from reset circuit whenever system 4 GND GND reset asserted and from Corelis test equipment 5 TDI 10KQ pull up 6 GND GND 7 TMS 10KQ pull up 8 GND GND 9 T
53. ode 0 DDRII mode 400 MHz Default 1 DDRI mode 266 MHz 1 EX IOWAIT N is sampled during the read write Expansion bus cycles Default 0 EX IOWAIT N is ignored for read and write cycles to Chip select 0 if EXP TIMING CSO is configured to Intel mode 10 IOWAIT_CSO Typically IOWAIT_CSO must be pulled down to Vss when attaching a Synchronous Intel StrataFlash on Chip select 0 If EXP_TIMING_CSO is reconfigured to Intel Synchronous mode during boot up the Expansion bus controller only ignores EX_IOWAIT_N during write cycles 9 EXP_MEM_DRIVE See the values defined for Bit 5 EXP_DRIVE USB CLOCK Controls the USB clock select 8 1 USB Host clock is generated internally Default 0 USB Host clock 48 MHz is generated from GPIO 1 7 Reserved Reserved 6 Reserved Reserved Expansion bus low medium high drive strength The drive strength depends on the configuration of EXP DRIVE and EXP MEM DRIVE Bit 9 00 Reserved 5 EXE DRIVE 01 Medium drive 10 Low drive Default 11 High drive 4 Reserved Reserved 3 Reserved Reserved Enables the PCI Controller arbiter 2 PCI_ARB 0 PCI arbiter disabled 1 PCI arbiter enabled Default Configures the PCI Controller as PCI bus host 1 PCI_ HOST 0 PCI as non host 1 PCI as host Default Specifies the data bus width of the Flash memory device found on Chip Select 0 0 8 16 0 16 bit data bus Default 1 8 bit data bus Table 10 Configuration Strapping Clock Settings J P3
54. oot image in place is recommended A host system connects through a network or serial port to provide the images The procedures in this section assume that you have a host system set up to support loading images from a TFTP server The Host system setup and installation are beyond the scope of this document For detailed information on using the RedBoot v2 02 software and host system requirements refer to the Intel IXP400 Software RedBoot v2 02 Software Release Notes This appendix provides the following procedures that are required to maintain the boot images in flash e Updating flash Generic steps that apply to any bootloader or image to be placed into flash and made available at system Start Up to run e Creating a backup copy of RedBoot e Using RedBoot to update RedBoot e Using the VisionICE to load RedBoot These procedures cover typical scenarios for using the IXP435 reference platform RedBoot commands entered at the RedBoot command prompt are prefaced with an gt and appear in boldface type Generic Flash Updating Using RedBoot Place the image to be loaded in the tftp root directory On Linux this is tftpboot Switch off the power to the board Connect the board to the network and serial console Switch on the power to the board Ur Wes er ores Boot to the RedBoot prompt Press C Ctrl C if necessary to cancel the boot script execution The default fconfig setting has no boot script 6 Use the fis lis
55. r 0 Disables the internal PCI system arbiter Informs the boot scripts of the total memory size available on the system board This information is crucial to set up properly the PCI configuration management in host assisted mode The pin code is as follows 000 256 MB Reserved recommended not to use 6 4 10 8 101 MEM SIZE 001 256 MB Reserved recommended not to use 010 8 MB 011 16 MB 100 32 MB 101 64 MB 110 128 MB 111 256 MB DDR SDRAM devices support different types of CAS latencies However they do not support all the combinations PNX1702 offers the possibility to program the MMI and therefore the DDR SDRAM devices with the appropriate CAS latency at boot time This is crucial for 3 3 0 CAS LATENCY standalone boot from Flash memory devices since 8 KB of data is stored into the main memory during the execution of the boot scripts 0 2 5 clock periods 1 3 clocks periods This pin has a double functional mode If BOOT_MODE 1 0 00 01 or 10 Boot from Flash memory ROM WIDTH 0 8 bit data wide ROM 2 l IIC_FASTMODE 1 16 bit data wide ROM If BOOT_MODE 1 0 11 Boot from I2C EEPROM 0 100 KHz 1 400 KHz The main boot mode is determined as follows 00 Set up the system and start the TM3260 CPU from a 8 or 16 bit NOR Flash memory or ROM attached to the PCI XIO bus 01 Set up the system and start the TM3260 CPU from a 8 or 16 bit NAND Flash memory or ROM att
56. rammable scaler and anti flicker filter maximum 5 lines ensures properly sized and flicker free TV display as CVBS or S video output Alternatively the three Digital to Analog Converters DACs can output RGB signals together with a TTL composite sync to feed SCART connectors When the scaler interlacer is bypassed a second VGA monitor can be connected to the RGB outputs and separate H and V syncs also thus serving as an auxiliary monitor at maximum 1280 1024 resolution 60 Hz PIXCLK 85 MHz Alternatively this port can provide Y PB and PR signals for HDTV monitors The device includes a sync clock generator and on chip DACs All inputs intended to interface with the host graphics controller are designed for low voltage signals between down to 1 1 V and up to 3 6 V The high level view of the Video Encoder SAA7104E is shown in Figure 7 Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 23 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Figure 7 Video Encoder Functional Block Diagram VppAi VbDpa2 VbDpa3 VppA4 Vssai Vssa2 Vpppi Vbpbp2 Vopp3 Vppp4 Vsspi Vssp2 Vssp3 Vssp4 TRST DUMP INPUT d HGB TO Y Cs Cr Ra FORMATTER UPSAMPLING MATRIX TDI TDO MEAM HORIZONTAL VERTICAL VERTICAL
57. required to have the 1 3VDSP come up before the 2 5V This is a JEDEC DDR specification requirement The total maximum power based on worst case estimates is 12V 3 5A though it is unlikely that this much power will actually be used The external power adapter should supply 12Vdc 3 5A on the IXP435 reference platform A power on off switch may be implemented for the flexibility to turn on off the input power supply The input power to the platform is 12Vdc 3 5A nominal There are eight power regulators on board The power consumption estimation and power circuit topology for the IXP435 reference platform is shown in Figure 19 and Table 24 s Regulator 1 RT9214 12Vdc input 3 3Vdc output e Regulator 2 RT9214 12Vdc input 5Vdc output USB e Regulator 3 RT9194 12Vdc input 3 3V control for output 1 8Vdc DDRII e Regulator 4 RT9173 1 8Vdc input 0 9V output DDRII VTT e Regulator 5 RT9167 3 3Vdc input 1 8V output Kendin switch e Regulator 6 RT9214 12Vdc input 1 8V DDRII control for output 1 3Vdc IXP43X network processors e Regulator 7 RT9194 12Vdc input 3 3V control for output 1 4Vdc DSP e Regulator 8 RT9194 12Vdc input 1 3V control for output 2 6Vdc DDR Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 47 intel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide
58. sor iecore rA b SIR iN aE E EAE ERFA EE T ER M EA ANEA ENANTA EA 19 3 4 Video les Ta L oen exte dda tedaeticuies e rnas temi iur ches pidada ea aada ndia eua Rau Edd 23 3 5 Usb 25 316 Expansion Bus Loading zs ea vra Te TRT r a 4 nx ga da CR ya eu aa RW RR XERE REPE E CR au 25 3 6 1 Expansion Bus Configuration Straps cccceceeeeeee eect eee e tees eens meme nene 25 3 6 2 Expansion Bus Clock Generation eee ee e ee e e e e eee 29 3 6 3 Expansion Bus Chip Selects iae YV 99 9 aa d 9 NAN e ka seda ua maa ca ERR a R NaN a Ra Ya 29 3 7 Memory SUubSystelmi iicicee ener enn xwe pax reet ka Fa REFER Rr Pe FERE ens enna RI FEIER R Riad REA 29 cA EE Too 0 M 29 cav EB PX BEJ Ii EE 29 3 7 3 DDRII MGemOLly ieri tenun t nune ka nana an e RE RA FRARG KR RR Ri NA RETE gu AE DENSa sient 30 co NEM iciic tUH m 31 3 9 1 Multi Garig Jack eiie eene ta nor ata tae negra een id Rex secta pr Ure wen tatu o E READA nude 36 3 9 UTOPIA 2 Interface besos cie akian aiana aba cbiea sl mea ARX ORRa EAT RDRRO RANTS 37 3 10 USB AU C 38 3 11 Serial lt Ta 2e eut Ex RA RA TEARPA DAN RRUARADA NIA MENFE EEE EA AA AEA RANET earner 38 3 11 1 Serial Port Pull Ups Pull Downs esees Hmmm 39 3 12 FXS and FXO lt ie gle iine ecaa IE cue rode c dee xot del cede Na OR nr vaio EEEE Ea 3
59. ss e ee e eee e eee eee eee 18 6 PCI H st Slot Pin Assignments iuicesee secet resa sa sac shined saeua YT aX RR A ER ERR a VE YES Y NX ck 19 7 Supported Memory Configuration for Media Processor ssssseseseeeeeenen nnne 21 8 PNX1702 Configuration Strapping Boot Mode Settings sssssssseeemm 22 9 Configuration Strapping Options cece eect eee mem menm eme a aa eese 26 10 Configuration Strapping Clock Settings JP3 cssssssessssssseenee mnn 26 11 Expansion Bus Chip Select Assignments sss resse eres eee eee s esse r sne nee eee nennen enne 29 12 Supported DDRII Memory Conngurations s sese sss e eee e e e e e e ee e ee e ee e emen 30 13 WAN Port Multi function Switch Settings s sse eee eee ee e ee e ee e ee Kee 33 14 Intel IXP435 Multi Service Residential Gateway Reference Platform MII Mezzanine Connector Pin DETINIGION mp TT 35 15 Utopia Mezzanine Connector Pin Definition cesses 37 16 Serial Port DB 9 Connector Pin Definitions esses enemies 39 17 Serial Port ResISLOFS ii iiis ect ke cessa ke e saxa ee X EAR ETERNI ERR RR A IQEATEKDATR RA ER NR ATLAS 39 18 Ethernet FXS and FXO Control cccccccceeeeece eee eee sees eene nsn nnne ase sean sanas nnn nnn 42 19 Intel IXP43X Product Line of Network Processors GPIO Assignment 42 20 LED IndicatOrS rtr eie tesa ka ten bd qe MN Kex yess a nassau ER DK nes NEUE Dr KU nd 43
60. supplied software Refer to Table 2 Related Intel Documentation on page 8 for a list of hardware software and platform documents that will assist in the development process In particular the following documents provide details on available features s Intel XP43X Product Line of Network Processors Datasheet has a complete list of available product features s Intel IXP400 Software Programmer s Guide provides information on the features that are enabled in a particular software release The IXP435 reference platform features that require enabling by software supplied by Intel are summarized in Table 1 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Document Number 316848 Revision 001US 7 intel Table 1 Note 1 4 Table 2 Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Intel 1XP435 Multi Service Residential Gateway Reference Platform Features Summary Features that do not require enabling Features that require enabling software from software I ntel Encryption Authentication AES AES CCM 3DES DES ae Intel XScale Processor up to 667 MHz SHA 1 SHA 256 SHA 384 SHA 512 MD 5 PCI v 2 2 33 MHz Host Option One High Speed Serial HSS interface Two USB 2 0 Host Controller Two Network Processor Engines NPEs DDRII DDRI SDRAM interface Up to two MII interfaces Slave Interface Expansion bus One UTOPIA Level 2 interfac
61. t command to view the existing flash partitions and their content If you are updating an existing image that is in the FIS partition list then you must unlock the partition before you can update it using the command fis unlock NAME Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 54 June 2007 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform n tel If there was no previous image then it is not possible to give NAME as an argument for the fis unlock command so it is recommended to unlock it using the command fis unlock f FLASH ADDRESS 1 IMAGE LENGTH When the update is complete lock the partition using the command fis lock NAME 7 Load the image into RAM using the RedBoot load command load r v b 0x01600000 image bin 8 Check the output of the load command for the image length RedBoot reports this address range 0x00100000 0x00181234 The image length to store is 0x00181234 minus 0x00100000 This value is used when storing the image to flash 9 Use the fis unlock command to prevent the occurrence of an error report which states Illegal command Not a String 0x25DB8 gt fis unlock f FLASH ADDRESS 1 IMAGE LENGTH 10 Use the fis create command to store the image to flash fis create IMAGE NAME b 0x01600000 1 IMAGE LENGTH f FLASH ADDRESS e 0x00000000
62. teway Reference Platform User s Guide Figure 5 audio visual products The processor is assisted by several image and video processing accelerators that support image scaling and compositing The high level view of the PNX1702 Media Processor is shown in Figure 5 Philips PNX1702 Media Processor Functional Block Diagram CORE 658 S a 3 CEVES cves 7 sHs sHvs QC lt Stereo IN LVDS E channei IN LCO JTAG COR 656 x 7 1 Asdo gt Remgte Cortrcl stereo our es 46 SPOF VO 40100 Ethernet LAN USB IDE ATAPI IDE ATAPI Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 20 The Video data in function is provided on a connector for S Video and CVBS input The Video data out function supports S Video Component DVI CVBS CCIR 656 and LCD operation The CVBS and S Video OUT and Y Cb Cr are provided on a connector plate provided with the board An SPDIF output unit outputs a high speed serial data stream primarily used to transmit digital SPDIF formatted audio data to an external audio equipment The Media Processor has a JTAG port that can be used for debugging The Media Processor supports 64 Mbytes DDR memory using two chips each of 16M x 16 configuration Bus frequency can be up to 200 MHz June 2007 Document Number 316848 Revision 001US User s Guide I ntel XP435 Multi Service Residential Gateway Reference Platform intel The Media Processor does not need any Flash
63. ti Service Residential Gateway Reference Platform User s Guide intel Figure 1 Intel 1XP435 Multi Service Residential Gateway Reference Platform Functional Block Diagram A i2Vdc I Power Circuit TUER REN REL DET JI Flesh PFE i NAND Flask EOR DDRII RAM PAPERS 1 Q 16Nxte z EI DDRII oe Ie race DELIS UTOPIA Pail USB2D Host Port USB2D Bi UTOP IAN P E A EA Mil Conecbr ean PEH T SUCEGU ie ael foe KS22995 ERE isis Femak Lheked IF SLIC CODEC mke m F es VOC E DATA mam Kum Ku R BE 2 lac EEPROM PCIShbt S E GOE Banan JTAG spree REMOTER Philips PC Bas 0 PNX1 7 OX DDR SDRAM M Mis Chee 246MX16 a G a n G S 2c 9 video nier Video Connector 1 Bark al 3 ang YCbCUYPbPI3XRCA 21MHZ ITU E56 Video Decode ai lt Pillpe S887 113 CVBS ideo In 1XRCA p4 576ME Ba Audio ADC Philips Audio In 2XRCA or Stereo Jad MI UDA1364 e 2 qu 25 Audio DAC Philips Audio Out 2XRCA Sieber UDA1334 JPDIF Qut 1XRCA S PDIF Mh PCI Coriecipr 2 beuuz PDIF In 1XRCA June 2007 Document Number 316848 Revision 001US Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide 13 Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide i n te I l 2 3 Component Placement The component layout of the Intel IXP43X Product Line of Network Processors is shown in Figure 2 and Figure 3 Figure 2 Intel 1XP435 Multi Service Residential Gatew
64. uch as triple play Overview of the Intel 1XP435 Multi Service Residential Gateway Reference Platform Figure 1 shows the block diagram of the IXP435 reference platform The IXP435 reference platform comprises the following e Memory subsystem e Networking subsystem e I O subsystem e Power and reset subsystem s VoIP subsystem e Media subsystem The following sections describe the high level design of each subsystem respectively s Intel IXP43X Product Line of Network Processors e Media processor Philips PNX1702 e NOR Flash Memory 16 MB for IXP43X network processors s NAND Flash Memory 64 MB for IXP43X network processors e DDRII 128 MB for IXP43X network processors s DDR Memory 64 MB for Media processor e Video encoder Philips SAA7104H e Audio DAC Philips UDA1334 e Video decoder Philips SAA7118 e Audio ADC Philips UDA1361 e Two SLIC CODEC Silicon Laboratories Si3216 and Si3201 e Voice Data DAA Silicon Laboratories Si3050 and Si3019 e Ethernet Switch Kendin 8995M e USB 2 0 host connector Two ports e Two Mini PCI slots Intel IXP435 Multi Service Residential Gateway Reference Platform User s Guide Document Number 316848 Revision 001US 11 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide Note 2 2 e One PCI Slot s One 120 pin MII connector e One 120 pin UTOPIA connector e Infrared remote control use GPIO of IXP43X network processors
65. w of the Key Components Component Description Package QTY Manufacturer Intel IXP43X Product Line of Network Intel s network processor 460 Pin PBGA 1 Intel Processors MT47H32M16CC 5E DDRII SDRAM 400MHz 84 ball FBGA 2 Micron K4H561638F UC LB3 DDR Memory 66 TSOP II 2 Samsung KSZ8995M 5 Port 10 100 Managed Switch 128 Pin PQFP 1 Micrel PC28F128J3D 75 NOR Flash Memory 64 Ball Easy BGA 1 Intel PC28F128P30T85 NOR Flash Memory 64 Ball Easy BGA 1 Intel K9F1208U0M PCBO NAND Flash 48 Pin TSOP 1 Samsung PNX1702bH G 500MHz Media processor BGA456 1 Philips SAA7104H Video encoder QFP64 Philips SAA7118E Video decoder BGA156 1 Philips UDA1334TS Audio DAC SSOP16 1 Philips UDA1361TS Audio ADC SSOP16 1 Philips Si3216 FT SLIC CODEC TSSOP 38 2 pM Si3201 FS Linefeed IF SOIC 16 1 SU S Haan nz TSS0P 20 l T PNN Si3019 FS Line Side SOIC 16 1 SU ies RT9214PS Power SOP 8 3 Richtek RT9194PE Power SOT 23 6 3 Richtek RT9167A18PS Power SOP 8 1 Richtek RT9173PS Power SOP 8 1 Richtek CY2305SZ 1H Clock buffer SOIC 8 2 Cypress TPS3825 33DBVR Processor supervisory circuit SOT23 5 2 Ti SS Intel IXP435 Multi Service Residential Gateway Reference Platform June 2007 User s Guide Document Number 316848 Revision 001US 51 m n tel Intel 1XP435 Multi Service Residential Gateway Reference Platform User s Guide 5 0 Mechanical and PCB Stack Up The Intel IXP435 Multi Service Residential Gateway Reference Platform Printed Circuit Board PCB is 12 x8 The
66. y itx prn oa tcm abuse erba Ri aaa sleeinbed UD M MER NER cal 31 11 NPE F n tion ConriectlOris eexeessusu inue e ren me Rue ru nn NR t ERR ERU E ERR DINER A NER UN ER pa RR DUAE dls 32 12 NPE A UTOPIA MII Pin Switches Topology ssssssse mmm nre 32 13 UTOPIA MII Pin Switches Location xx ee ee eee 34 14 RJ 45 Jack with Integrated Magnetics sss emen 36 15 Intel IXP43X Product Line of Network Processors and SLIC CODEC Topology 40 16 Intel IXP43X Product Line of Network Processors and Voice DAA Topology s 41 17 Expansion Bus and LED Circuit TOpOlogy cceeeeeee eee e eee eee meme nene 44 18 JTAG Interface Locations uiis isi iiec rema IRR ERA aa xe DIR Y HAN afa DXX dR ERIR SERE aa MAE RI 46 19 Power Circuit IOpology eren naninira Rene F a Eu Res ce O EASE AEE Du ee RS EAR RARE FERES 48 20 Reset Circuit Topology ada 405 a en ese use 9 RA X NS i ade Pasa Xe RR REA ER a FER REP RAN Dei 50 Tables 1 Intel IXP435 Multi Service Residential Gateway Reference Platform Features Summary 8 2 Related Intel Documentation cry a 94 Y ra iussis etras sens nga RE ERR Ra RA IR DAR GR KRAX RI N RVR S HR 034 8 3 Related External Documentation enin ecu nexa c 0 He nga rugas aane sa pire xa Ea naga resa ae Ria ga 9 4 List of Terminology nera ttbi pa uere tma Dee pes PRA tide PIRA Te baked SAESP a ARIA PDA TRgR sd anes gine 9 5 IDSEL and GPIO Mapping on the PCI Devices s

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