RHF1201KSO-01V - STMicroelectronics
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1. 25 30 35 40 45 25 30 35 capa load pF capa load pF PCB layout precautions A ground plane on each layer of the PCB with multiple vias dedicated for inter connexion is recommended for high speed circuit applications to provide low parasitic inductance and resistance The goal is to have a common ground plane where AGND and DGND are connected with the lowest DC resistance and lowest AC impedance The separation of the analog signal from the digital output is mandatory to prevent noise from coupling onto the input signal Power supply bypass capacitors must be placed as close as possible to the IC pins to improve high frequency bypassing and reduce harmonic distortion All leads must be as short as possible especially for the analog input so as to decrease parasitic capacitance and inductance To minimize the transition current when the output changes the capacitive load at the digital outputs must be reduced as much as possible by using the shortest possible routing tracks One way to reduce capacitive load is to remove the ground plane under the output digital pins and layers at high sampling frequencies Choose the smallest possible component sizes SMD DoclD012585 Rev 7 29 38 Definitions of specified parameters RHF1201 6 6 1 6 2 30 38 Definitions of specified parameters Static parameters Differential non linearity DNL2. The average deviation of any output code width from the ideal code width of 1 LSB Integral non linearity INL An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code The INL is the deviation from this ideal line for each transition Dynamic parameters Spurious free dynamic range SFDR The ratio between the power of the worst spurious signal not always a harmonic and the amplitude of the fundamental tone signal power over the full Nyquist band Expressed in dBc Total harmonic distortion THD The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line Expressed in dB Signal to noise ratio SNR The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band f 2 excluding DC fundamental and the first five harmonics SNR is reported in dB Signal to noise and distortion ratio SINAD Similar ratio as for SNR but including the harmonic distortion components in the noise figure not DC signal Expressed in dB The effective number of bits ENOB is easily deduced from the SINAD using the formula SINAD 6 02 x ENOB 1 76 dB When the applied signal is not full scale FS but has an amplitude Ag the SINAD expression becomes SINAD 6 02 x ENOB 1 76 dB 20 log Ap FS ENOB is expressed in bits Effective resolution bandwidth For
3. lt T RHF1201 WI life augmented Rad hard 12 bit 50 Msps A D converter Datasheet production data Ceramic SO48 package Applications e Digital communication satellites e Space data acquisition systems e Aerospace instrumentation e Nuclear and high energy physics TNT Description The upper metallic lid is not electrically connected to any The RHF1201 is a 12 bit 50 Msps sampling pins nor to the IC die inside the package us frequency analog to digital converter that uses pure ELDRS free CMOS 0 25 um technology Features combining high performance radiation robustness and very low power consumption e Qml V qualified smd 5962 05217 The device is based on a pipeline structure and e Rad hard 300 kRad Si TID digital error correction to provide excellent static linearity Specifically designed to optimize the speed power consumption ratio the RHF1201 integrates a proprietary track and hold structure e Failure immune SEFI and latchup immune SEL up to 120 MeV cm4 mg at 2 7 V and 125 E making it ideal for IF sampling applications up to e Hermetic package 150 MHz A voltage reference network is e Wide sampling range integrated in the circuit to simplify the design and minimize external components A tri state e Tested at 50 Msps capability is available on the outputs to allow Optimwatt M adaptive power 44 mW at common bus sharing Output data can be coded 0 5 Msps and 100 mW at 50 Msps in two different fo
4. internal or external VIN VINB 2Vp p EN Figure 18 shows an isolated differential input solution The input signal is fed to the transformer s primary while the secondary drives both ADC inputs The transformer must be matched with generator output impedance 50 Qin this case for proper matching with a 50 Q generator The tracks between the secondary and Vin and Vinb pins must be as short as possible DoclD012585 Rev 7 21 38 User manual RHF1201 Figure 18 Differential implementation using a balun ADT1 1 C 50 Q track 1 1 Short track Analog input signal 50 Q output 3 E 100 pF RHF1201 VINB REFM ra External INCM 470 nF ceramic 100 nF ceramic as close as possible as close as optional to the transformer possible to INCM pin the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04545 The input common mode voltage of the ADC INCM is connected to the center tap of the transformer s secondary in order to bias the input signal around the common voltage see Table 7 Internal reference voltage The INCM is decoupled to maintain a low noise level on this node Ceramic technology for decoupling provides good capacitor stability across a wide bandwidth Single ended mode Figure 19 shows an example of how to drive RHF1201 in single ended and DC coupled This is the optimized configuration recommended For more explanations see Section 5 2 Driving the a
5. differential input VIN VINB level VREFP VREFM code 4095 FS full scale 2 VREFP VREFM oe VIN VINB level 0 code 2047 level VREFP VREFM code 0 AM04541 5 3 2 Single ended mode output code In single ended mode Vin or Vinb is constant and equal to Vbias If Vin Vbias A sin at and Vinb Vbias with A peak of input signal then Vin Vinb A sin at and A Vrefp Vrefm for maximum swing on input Table 12 Single ended mode output codes with Vinb Vbias and A Vrefp Vrefm 20 38 DocID012585 Rev 7 Ly RHF1201 5 4 User manual Design examples The RHF1201 is designed to obtain optimum performance when driven on differential inputs with a differential amplitude of two volts peak to peak 2 V This is the result of 1 V5 on the Vin and Vinb inputs in phase opposition Figure 17 For all input frequencies it is mandatory to add a capacitor on the PCB between Vin and Vinb to cut the HF noise The lower the frequency the higher the capacitor The RHF1201 is specifically designed to meet sampling requirements for intermediate frequency IF input signals In particular the track and hold in the first stage of the pipeline is designed to minimize the linearity limitations as the analog frequency increases Differential mode 3 Figure 17 shows an example of how to drive RHF1201 in differential and DC coupled Figure 17 Example 2 V differential input INCM VREFM
6. RHF1201 operating modes Analog input differential SRC Most significant amplitude bit MSB aaa LEA CERRO LET es HA pases NN E Vin Ving below minimum range pH fe xa on mon Hin High impedance Low slew rate low ki rate Data format select DFSB when set to low level Vj the digital input DFSB provides a two s complement digital output MSB This can be of interest when performing some further signal processing When set to high level V 4 DFSB provides a standard binary output coding Digital inputs Output enable OEB when set to low level Vj all digital outputs remain active When set to high level Vj all digital output buffers are in high impedance state while the converter goes on sampling When OEB is set to a low level again the data arrives on the output with a very short Ton delay This feature enables the chip select of the device Figure 11 Timing diagram summarizes this functionality Slew rate control SRC when set to high level Vj all digital output currents are limited to a clamp value so that any digital noise power is reduced to the minimum When set to low level V the output edges are twice as fast DoclD012585 Rev 7 27 38 User manual RHF1201 5 8 2 28 38 Digital outputs Out of range OR this function is implemented at the output stage to automatically detect any digital data that is over the full scale range For data within the range OR remains in a low level s
7. and Vbias A 0 4 V The 0 4 V is a problem because only 0 2 V is allowed Finally the practical input voltage Vin is Vin 0 5 V 0 7 V sin at gt CMinput maximum 0 85 V A Vbias 1 2 V and Vbias A 0 2V Particular case where Vrefm 0 V and cannot be changed In some applications a dual mode can be requested differential mode and single ended mode with a preference for differential mode first Let s take a typical example for differential mode Vrefp 1 V Vrefm 0 V Vbias INCM 0 5 V This safe configuration gives a full scale at 2 Vpp 1 Vpp on each input with Vbias 0 5 V and A 0 5 V Here you can use all digital output codes from 0 to DIE Now let s go to single ended mode by keeping Vrefp 1 V Vrefm 0 V Vbias INCM Vinb 0 5 V What would be the maximum swing allowed on Vin and what would be the resulting code So Full scale 2 x Vrefp Vrefm 2 V CMref 0 5 V and CMref 0 2V 0 7 V DoclD012585 Rev 7 Ly RHF1201 9 2 3 5 3 3 User manual By definition the limitation on the lower side is 0 2 V The limitation of Vin on the upper side is given by this equation Vinmax Vbias lt 0 7V So Vinmax 0 9 V Finally 0 2V lt Vin lt 0 9V that gives 1433 lt Output Code decimal lt 2867 Here the full scale is not usable but is a limited range only INCM biasing As previously discussed INCM is an input output that s used to bias the internal OT
8. be any value from Table 4 However ifthe INCM value is used to bias analog inputs Vin and Vinb Cminput becomes dependent on INCM In this case the setting of INCM must be chosen to respect the eguation CMinput lt CMref 0 2V Now let s see what happens when the RHF1201 is driven in differential mode and single ended mode We will use a sinusoidal input signal for ease of computation but the results presented after can be easily extrapolated to another kind of signal shape Differential mode biasing In differential mode we have e Vin Vbias A sin at and Vinb Vbias A sin at with A peak of input signal e Vbias can be provided by the source signal or by INCM which is the DC biasing of the sinusoidal input signal As by definition AC components are in opposite phase for Vin and Vinb at any time on the signal we have CMinput Vbias In differential mode to keep a safe operation of the RHF1201 analog inputs we have to respect Vbias lt CMref 0 2V and referring to Table 4 for the maximum input signal allowed we have A Vbias lt 1 6V and Vbias A2 0 2V DoclD012585 Rev 7 15 38 User manual RHF1201 5 2 2 16 38 Figure 14 RHF1201 in recommended differential mode 2 3V to 2 7V Internal or External AVCC VREFP Maximum DC value INCM Internal or External VREFP VREFM 2 0 2V NI AGND Single ended mode biasing In single ended mode the biasing consideration is differe
9. can be found in Table 7 Internal reference voltage When you force externally a voltage on Vrfep INCM pin a sink or a source current must be provide by the driver and this current is expressed with the following eguation External Vrefp INCM force Internal Vrefp INCM Isink or source Vrefp INCM Rout Depending on the difference between the external and internal value the current can be positive or negative source sink Example 1 You wanted to force Vrefp at 1 2 V and on the RHF1201 internal Vrefp 0 85 V As Rout for Vrefp 39 Q the current provided by the driver will be positive and equal to 1 2 0 85 39 9 mA DoclD012585 Rev 7 Ly RHF1201 User manual Example 2 You wanted to force INCM at 0 4 V and on the RHF1201 internal INCM 0 5 V As Rout for INCM 50 Q the current provided by the driver will be negative and equal to 0 4 0 5 50 2 mA Figure 22 Equivalent internal schematic of Vrefp and INCM inputs Vrefp or INCM Input pin External force Rout Of internal Vrefp or INCM Internal Vrefp or INCM Of course the external voltage references with the configuration shown in Figure 23 must be decoupled by using ceramic capacitors to achieve optimum linearity versus frequency Figure 23 Decoupling of Vrefp and INCM inputs when using external voltage force As close as possible to the ADC pins DC source VCCA VREFP VIN INCM REFMODE VREFM AM04575 Note The use of ceramic tec
10. 012585 Rev 7 RHF1201 2 3 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 3 Absolute maximum ratings CCIE Ves oa Analog inputs bottom limit 5 top limit 0 6 V gt AVec 0 6 V INB External references bottom limit gt top limit 0 6 V gt AVcc 0 6 V INCM Thermal resistance junction to case iN 1 Human body model a 100 pF capacitor is charged to the specified voltage then discharged through a 1 5 QW resistor between two pins of the device This is done for all couples of connected pin combinations while the other pins are floating Table 4 Operating conditions Eee e CCI RE EI E RE CINE CA Wwe Pigi sup vote E 25 2 Vv Yeon _ Detainenatbutersunpy 23 25 a7 v Vues Dora cupuoutersuppy 23 25 34 v ere ones ie lol ta v nen Bse iene IE L I I I lt lt lt EE TINY Vin amp Vin Minimum input voltage versus GND e ae DFSB E Digital inputs 2 lt lt Please note that driving externally Vrefp and INCM inputs induces some constraints Refer to Section 5 5 2 External voltage reference for more information 2 See Table 9 for thresholds DoclD012585 Rev 7 9 38 Timing characteristics RHF1201 3 10 38 Timing characteristics Table 5 Timing table DC Clock duty cycle Fs 45 Msps Ce ww Data output delay E fall of clock to data AA 10 pF load ee EE Tpa Data pipeline de
11. 12585 Rev 7 3 38 Description RHF1201 1 Description 1 1 Block diagram Figure 1 Block diagram Biasing current VCCBI VCCBE AM04556 2 4 38 DoclD012585 Rev 7 RHF1201 Description 1 2 Pin connections Figure 2 Pin connections top view GNDBI 48 DGND GNDBE DGND VCCBE 46 CLK NC DGND NC 144 DVCC OR L6 DVCC MSB D11 AVCC D10 8 AVCC D9 9 40 AGND D8 INCM D7 AGND D6 VINB D5 AGND D4 VIN D3 AGND D2 VREFM D1 VREFP LSB DO IPOL DR AGND NC AVCC NC AVCC VCCBE DFSB GNDBE OEB VCCBI SRC a DoclD012585 Rev 7 5 38 Description RHF1201 1 3 Pin descriptions Table 2 Pin descriptions en ie men now pin nano Deion now de fee Cl fare E laga pm pm eem mmt epe emm mmt Dep eme em Dep eme emt epe mmm emt blk k7 blk E Bee e ee Em 23 GNDBE Digital buffer ground ov fa DGND Digital ground ove 6 38 DocID012585 Rev 7 Ly RHF1201 Description 1 4 Equivalent circuits Figure 3 Analog inputs Figure 4 Output buffers VIN or VINB Zin 1 Cs Fs AM04531 Figure 5 Clock input Figure 6 Data format input AM04532 AM04533 Figure 7 Slew rate control input Figure 8 Output enable input AM04534 AM04535 3 DoclD012585 Rev 7 7 38 Description RHF1201 Figure 9 VREFP and INCM input VREFP INCM Input impedance 39 Q Input impedance 50 Q AM04536 Figure 10 VREFM input VREFM High input impedance AM04537 2 8 38 DocID
12. 2xVrefp 1 8 V then Vrefp 0 9 V Vbias 1 6 V 1 8V 2 0 7 V then Vin 0 7 V 1 8V 2 xsin t 0 7 V 0 9Vxsin ot then A 0 9V Vinb Vbias Vin 0 7 V With these settings we can calculate CMref 0 2 V 0 65 V and CMinput 0 7 V 0 9Vxsin t 2 Then CMinput is maximum when sin at 1 that gives CMinputmax 1 15 V which is far beyond the limit of 0 65 Vpreviously calculated The range of Vin allowed is 0 2 V to 0 65 V that is even below the half scale requested initially A solution to this problem would be to increase the CMref value which is done by increasing Vrefm and Vrefp Let s take Vrefm 0 5 V and calculate Vrefp to have CMref 0 2 V 1 15 V The solution is Vrefp 1 4 V that is the maximum allowed in Table 4 Of course this solution is suitable but if you want to have some margin tolerance to detect a clipping input you have to change some parameters So the only way is to reduce the input swing in accordance with the maximum Vrefp and Vrefm allowed in Table 4 With Vrefp 1 3 V Vrefm 0 5 V CMref 0 2 V 1 1V CMinput maximum 1 1V that gives Vbias 1 1 V A 2 With A 0 8 V Vbias 0 7 V gt Vinpp 1 6V A Vbias 1 5 V Vbias A 0 1 V By reducing the input amplitude by 200 mVpp we are able to find a solution that fits the limits given in Table 4 plus a possible clipping detection With this example we can see that the main limitation in single ended mode on the condit
13. A amplifiers of RHF1201 So INCM can be any value from Table 4 However depending on the INCM value the performance can change slightly For RHF1201 and for INCM from 0 4 V to 1V no impact on performance can be observed For INCM from 0 2V to 0 4V and 1V to 1 1V it s possible to have under boundary conditions a typical loss of one bit of ENOB So if you have the choice keep the value of INCM value in the range 0 4 V to 1 V Please note also that driving externally INCM input induces some constraints Please refer to Section 5 5 2 External voltage reference for more information Output code vs analog input and mode usage Whatever the configuration chosen differential or single ended the two following equations are always true for RHF1201 e The full scale of analog input is defined by Full scale 2 x Vrefp Vrefm e he output code is defined also as Output code f Vin Vinb vs full scale Finally we got for DFSB 1 sa EFFx Vin VinB Output code 12 bits SD Vrefr 7FF and for DFSB 0 Output code 12 bits FFF x Vin VinB 2x Vrefp Vrefm PE opus DoclD012585 Rev 7 19 38 User manual RHF1201 5 3 1 Differential mode output code In this mode the DC component of Vin and Vinb is naturally subtracted We get the following table Table 11 Differential mode output codes anan e e I 099 89 Figure 16 shows the code behavior for DFSB 1 Figure 16 Equivalent Vin Vinb
14. a given sampling rate and clock jitter this is the analog input frequency at which the SINAD is reduced by 3 dB and the ENOB is reduced by 0 5 bits DoclD012585 Rev 7 Ly RHF1201 Definitions of specified parameters Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output on the output bus Also called data latency it is expressed as a number of clock cycles When powering off to on there is a delay of several clock cycles before the ADC can achieve a reliable and stable signal conversion During this delay some conversion artifacts may appear DoclD012585 Rev 7 31 38 3 Package information RHF1201 7 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 32 38 DocID012585 Rev 7 Ly RHF1201 7 1 3 Package information S048 package information Figure 26 Ceramic SO48 package outline N 2 Places b N Places 1 The upper metallic lid is not electrically connected to any pins nor to the IC die inside the package Connecting unused pins or metal lid to ground or to the power supply will not affect the electrical characteristics Table 14 Ceramic SOA8 mechanical data 6 9m wm o
15. dded DFS OEB and SRC values in Table 4 Changed VINCM values in Table 4 Removed Fin values from Table 4 Removed output capacitive load values from Table 9 Changed clock threshold values in Table 9 Added PSRR values in Table 10 Added Figure 13 on page 14 to Figure 44 Modified Figure 16 Figure 19 and Figure 18 Added 7 on page 33 and in the Pin connections diagram on the Cover page y DoclD012585 Rev 7 RHF1201 Revision history Table 17 Document revision history e e Updated Figure 1 Block diagram Updated Figure 3 Analog inputs Figure 4 Output buffers Updated Table 4 Table 5 and Figure 11 added new text Updated Table 6 Table 8 Rewording and new Section 5 1 Power consumption optimization Section 5 2 Driving the analog input how to correctly bias the 24 July 2014 RHF1201 Section 5 3 Output code vs analog input and mode usage Section 5 4 Design examples Section 5 5 Reference connections Section 5 6 Clock input Section 5 7 Reset of RHF1201 Section 5 8 RHF1201 operating modes Section 5 9 Digital output load considerations Section 5 10 PCB layout precautions Added Section 8 Ordering information Section 9 Other information Corrected Table 5 Timing tabl 08 July 2015 7 pia i i Corrected Figure 11 Timing diagram DoclD012585 Rev 7 37 38 RHF1201 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right
16. hnology is preferable to ensure large bandwidth stability of the capacitor Ly DoclD012585 Rev 7 25 38 User manual RHF1201 5 6 5 7 26 38 Clock input The quality of the converter very much depends on the accuracy of the clock input in terms of jitter The use of a low jitter crystal controlled oscillator is recommended The following points should also be considered e The clock s power supplies must be independent of the ADC s output supplies to avoid digital noise modulation at the output e When powered on the circuit needs several clock periods to reach its normal operating conditions e The square clock must respect the values in Table 5 and Table 9 The signal applied to the CLK pin is critical to obtain full performance from the RHF1201 It is recommended to use a square signal with fast transition times and to place proper termination resistors as close as possible to the device Reset of RHF1201 To reset the RHF 1201 its mandatory to apply several clock periods At power up without any clock signal applied to RHF 1201 the device is not reset In this case parameters like Vrefp INCM and Rout will not be in line with values in Table 7 2 DoclD012585 Rev 7 RHF1201 5 8 5 8 1 3 User manual RHF1201 operating modes Extra functionalities are provided to simplify the application board as much as possible The operating modes offered by the RHF 1201 are described in Table 13 Table 13
17. ion to maximize the full digital swing 0 to 212 will come from the CMinput maximum vs Vrefp and Vrefm allowed We can see also with the previous example to fit the large full swing reguested you need three different biasing values Vrefp Vrefm Vbias INCM or four if the Vbias value is not compatible with the INCM range allowed More generally if the number of different biasing values is a problem it s possible to work in single ended with two different biasing values By setting INCM Vrefm Vbias Vinb Vrefp 2 you can have a simple single ended as represented in Figure 19 DoclD012585 Rev 7 17 38 User manual RHF1201 18 38 Figure 15 RHF1201 in recommended single ended mode 2 3V to 2 7V Internal or External INCM Internal or External VREFP 2 AGND External However we can calculate that the main limitation will come from Vrefm maximum value 0 5 V Let us take Vrefm INCM Vbias Vinb 0 5 V and Vrefp 1 V gt the input swing allowed on Vin is 1Vpp centered at 0 5 V gt A 0 5 V Here CMref 0 75 V and CMinput maximum 0 75 V So for an input voltage Vin from 0 V to 1 V the output code will vary from O to 21 Now let s see how much the maximum input amplitude Vin can be in order to go in saturation mode bit OR set to 1 As CMref 0 2 V 0 95 V the theoretical input voltage Vin allowed can be Vin 0 5 V 0 9V sin t Here CMinput maximum 0 95 V but A Vbias 1 4 V
18. lay pipeline Data pipeline delay Data ready rising egge LL mur INS de ES after data change Duty cycle 50 T Falling edge of OEB to 4 3 on digital output valid data Rising edge of OEB to digital output tri state eraser r smesse ar 2 Ty is linked to the duty cycle conditioned by the duration of the low level of DR signal 1 Guaranteed by design Figure 11 Timing diagram Tpd Tod Data output DR HZ state AM06133 The input signal is sampled on the rising edge of the clock while the digital outputs are synchronized on the falling edge of the clock The duty cycles on DR and CLK are the same The rising and falling edges of the OR pin are synchronized with the falling edge of the DR pin DoclD012585 Rev 7 Ly RHF1201 Electrical characteristics unchanged after 300 kRad 4 Electrical characteristics unchanged after 300 kRad Unless otherwise specified the test conditions in the following tables are AVcc DVcc VCCBI VCCBE 2 5 V Fs 50 Msps differential input configuration rin 15 MHz VREFP internal VREFM 0 V Tamh 25 C Table 6 Analog ia CE SE input differential voltage Vin VINB FS Vp p pae impedance vs INCM amp Fs 13Msps k Effective resolution bandwidth 1 BEEN 95 1 See Section 6 Definitions of specified parameters for more information 2 Optimized differential input 2 Vp p 3 Zin 1 Fs x C with C 1 2 pF Table 7 Internal reference
19. mary Failed component list list of components that have failed during screening Group A summary Qci electrical test Group B summary Qci9 mechanical test Group E acl wafer lot radiation test QML V flight 3 1 PIND particle impact noise detection 2 SEM scanning electron microscope 3 QCI quality conformance inspection DoclD012585 Rev 7 35 38 Revision history 10 Revision history RHF1201 Table 17 Document revision history KALA ms A 01 Sep 2006 Initial release in new format n E B 36 38 Updated failure immune and latchup immune value to 120 MeV cm mg Updated package mechanical data Removed reference to non rad hard components from Section 5 4 2 External voltage reference on page 24 Changed cover page graphic Changed Figure 2 Added Chapter 1 4 Equivalent circuits Added Note 1 under Table 3 Expanded Table 4 with additional parameters Modified Test conditions and Vrefp Vincm in Table 7 Improved readability in Table 13 Added Figure 16 to Figure 18 Modified Figure 18 and Figure 20 Added Figure 21 Removed F sampling section Modified Figure 22 and Figure 16 Added Figure 12 Added ECOPACK information and updated presentation in Chapter 7 Modified description on cover page Added Table 1 Device summary on page 1 Removed RHF 1201KSO2 order code from Table 1 Removed Fs and Tck values from Table 9 Added Figure 7 and Figure 8 A
20. mic technology is preferable for a large bandwidth stability of the capacitor AM04546 3 DoclD012585 Rev 7 23 38 User manual RHF1201 9 5 5 5 1 5 5 2 24 38 Reference connections Internal voltage reference In standard configuration the ADC is biased with two internal voltage references VREFP and INCM They must be decoupled to minimize low and high frequency noise Both internal voltage references are able to drive external components The VREFM pin has no internal reference and must be connected to a voltage reference It is usually connected to the analog ground for differential mode and to Vrefp 2 for single ended mode Figure 21 Internal voltage reference setting As close as possible the ADC pins ioo nF 470 nF vov RHF1201 the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04548 External voltage reference External voltage references can be used for specific applications reguiring better linearity enhanced temperature behavior or different voltage values see Table 4 Operating conditions Internal voltage references cannot be disabled but can be forced externally As this voltage is forced on an internal resistance that is relatively low the driver will have to be able to sink or source a certain amount of current Figure 22 shows the equivalent internal schematic of Vrefp and INCM inputs Internal value of Vrefp INCM and Rout
21. nalog input how to correctly bias the RHF1201 Figure 19 Optimized single ended configuration DC coupling 2 3V to 2 7V Internal or External DC value VREFP 2 AVCC VREFP INCM Internal or External VREFP 2 10uF 100nF ceramic la as close as possible to VINB pin GND Note The use of ceramic technology is preferable to ensure large bandwidth stability of the capacitor 22 38 DocID012585 Rev 7 Ly RHF1201 User manual As some applications may require a single ended input it can be easily done with the configuration shown in Figure 19 for DC coupling and Figure 20 for AC coupling However with this type of configuration a degradation in the rated performance of the RHF1201 may occur compared with a differential configuration You should expect a degradation of ENOB of about 2 bits compared to differential mode A sufficiently decoupled DC reference should be used to bias the RHF1201 inputs An AC coupled analog input can also be used and the DC analog level set with a high value resistor R 10 QW connected to a proper DC source Cin and R behave like a high pass filter and are calculated to set the lowest possible cutoff frequency Figure 20 AC coupling single ended input configuration 50 Q track Analog input signal 500 50 Q output RHF1201 Short track 470pF 1 1 100nF ceramic ER ceramic l External INCM optional 100 nF ceramic as close as possible to INCM pin the use of a cera
22. nt because as we will see CMinput is no longer constant but dependent on the amplitude of the input signal This dependency limits considerably the possibilities of single ended use Please note also that in the demonstration below Vin is variable and Vinb is fixed but the opposite is possible simply by exchanging Vin and Vinb in the equations Let s take a typical situation with e Vin Vbias A sin t and Vinb Vbias with A peak of input signal e Vbias can be provided by the source signal or by INCM which is the DC biasing of sinusoidal input signal In this case CMinput Ax snob Vbias and CMinput is totally dependent on the amplitude of the input signal In addition as the following relationship is still true CMinput lt CMref 0 2V we now have Ax snob Vbias lt CMref 0 2V and of course referring to Table 4 for maximum input signal allowed we have A Vbias lt 1 6V DoclD012585 Rev 7 Ly RHF1201 3 User manual and Vbias A2 0 2V So depending on the settings of Vrefp Vrefm the following condition Ax snob Vbias lt CMref 0 2V can occur very soon before reaching the full scale input of RHF1201 Example you have an input sig nal in single ended that maximizes the full swing authorized for RHF1201 input 0 2 V to 1 6V which gives 1 8 Vpp in single ended The biasing settings are as follows As the full scale of ADC is defined by Vrefp Vrefm x2 if Vrefm 0 V we have
23. on can be adjusted across the entire sampling range to fulfill the requirements of applications where power saving is critical For sampling frequencies below 2 MHz the optimum resistor value is approximately 200 kOhms R pol Max R pol Average Rpol Min Sampling Frequency MHz The power consumption depends on the Rpg value and the sampling frequency Ryo is defined in Figure 13 as the optimum DoclD012585 Rev 7 13 38 User manual 14 38 E Or Li O o Figure 13 Power consumption values versus Fs ED 17 225 28 11 33 5 Sampling Frequency MHz DoclD012585 Rev 7 RHF1201 a RHF1201 5 2 5 2 1 User manual Driving the analog input how to correctly bias the RHF1201 It is mandatory to follow some simple biasing rules to reach optimal performance when driving the RHF1201 DC biasing and the AC swing must be considered in order to keep the analog input in the correct range Let s define some parameters Definition 1 The common mode of the input signal is Vin Vinb CMinput 2 Definition 2 the common mode of the reference voltage is CMref Vrefp Vrefm i 2 To have correct biasing of RHF1201 this condition must be respected at all times CMinput lt CMref 0 2V Please note that the INCM value is not a parameter from previous eguations INCM is an input output that s used to bias internal OTA amplifiers So INCM can
24. pw Pasme sg 9 Signal to noise and distortion ratio Fip 95MHz 60 mcwsws 5 Foam er wa Effective number of bits Fip 95MHz 95 Preme faf F 260 kHz Fs 2 MHz Power supply rejection ratio Rpa T ao K ta 93 each power supply at 2 5 V decoupled by 10 uF 470 nF gee oe 12 38 DoclD012585 Rev 7 RHF1201 5 5 1 a User manual User manual Power consumption optimization The polarization current in the input stage is set by an external resistor Roi When selecting the resistor value it is possible to optimize the power consumption according to the sampling frequency of the application For this purpose an external Rpa resistor is placed between the IPOL pin and the analog ground The values in Figure 12 are achieved with VREFP 1 V VREFM 0 V INCM 0 5 V and the input signal is 2 Vpp with a differential DC connection If the conditions are changed the Rpol resistor varies slightly but remains in the domain described in Figure 12 Figure 12 shows the optimum Rpa resistor value to obtain the best ENOB value It also shows the minimum and maximum values to get good results ENOB decreases by approximately 0 2 dB when you change Ryo from optimum to maximum or minimum If Roo is higher than the maximum value there is not enough polarization current in the analog stage to obtain good results If Rpg is below the minimum THD increases significantly Therefore the total dissipati
25. rmats A Data Ready signal e Optimized for 2 Von differential input raised when the data is valid on the output can SFDRupto75dBatFs 50 Msps be used for synchronization purposes Fin 15 MHz e 2 5 V 3 3 V compatible digital I O e Built in reference voltage with external bias capability Table 1 Device summary Order code 1 Quay Package ids o level finish RHF1201KSO1 Engineering RHE12OIKSOT model s048 Gold RHF1201KSO 01V 5962F0521701VXC ui 5962F0521701VXC Contact your ST sales office for information about the specific conditions for products in die form and for information about SMD packages July 2015 DoclD012585 Rev 7 1 38 This is information on a product in full production www st com Contents RHF1201 Contents 1 Bice gjedde a RR AA 5502 Bade PA oe ae ra 4 1 1 Block diagram 1 1 ee eee eens 4 1 2 PIN COMMECHONS aa 2650 E RRALALEOGOR Gd Son o or gre SOPORE GLA EROR d 5 1 3 Pin descriptions 1 55 8 doi nat pic DAA BAGA ian 6 1 4 EGQUIVAIGNUECICUNS aa uwewsoeee sua iv WG ChE DANDAN beaten 4 7 2 Absolute maximum ratings and operating conditions 9 3 Timing characteristics Lina 10 4 Electrical characteristics unchanged after 300 kRad 11 5 User MANUAL 3 25x we de EROR ICE E93 p TEFEN HEELS da 13 5 1 Power consumption optimization 13 5 2 Driving the analog input how to correctly bias the RHF1201 15 5 2 1 Differen
26. s oes ooo o0 o wer seus 160 oem oem oer wo wo loaf o o 3 om CUT 9 om ef sso we Me se 0067 oo a a8 ws ose oes oos ox DoclD012585 Rev 7 33 38 Ordering information RHF1201 8 Ordering information Table 15 Order codes RHF1201KSO1 Engineering model RHF1201KSO1 55 C to 125 C Strip pack RHF1201KSO 01V QML V flight 5962F0521701 EG 1 Specific marking only Complete marking includes the following SMD pin for QML flight only ST logo Date code date the package was sealed in YYWWA year week and lot index of week QML logo Q or Country of origin FR France Note Contact your ST sales office for information regarding the specific conditions for products in die form and QML Q versions 2 34 38 DocID012585 Rev 7 RHF1201 9 9 1 9 2 3 Other information Other information Date code The date code is structured as shown below e Engineering model EM xyywwz e QML flight model FM yywwz Where x EM only 3 assembly location Rennes France yy last two digits year ww week digits z lot index in the week Documentation Table 16 Documentation provided for QMLV flight Certificate of conformance with Group C reliability test and group D package qualification reference Precap report PIND test summary test method conformance certificate SEM report X ray report Screening sum
27. tate VoL but switches to a high level state Voy as soon as out of range data is detected Data ready DR the data ready output is an image of the clock being synchronized on the output data DO to D11 This is a very helpful signal that simplifies the synchronization of the measurement equipment or of the controlling DSP As all other digital outputs DR and OR go into a high impedance state when OEB is set to high level as shown in Figure 11 Timing diagram 2 DoclD012585 Rev 7 RHF1201 5 9 Figure 24 Output buffer fall time User manual Digital output load considerations The features of the internal output buffers limit the maximum load on the digital data output In particular the shape and amplitude of the Data Ready signal toggling at the clock frequency can be weakened by a higher equivalent load In applications that impose higher load conditions it is recommended to use the falling edge of the master clock instead of the Data Ready signal This is possible because the output transitions are internally synchronized with the falling edge of the clock Figure 25 Output buffer rise time VCCBE 3 3V SRC 1 o c E Ki pag rise time ns VCCBE 3 3V VCCBE 3 3V SRC 0 one VCCBE 2 5V VCCBE 2 5V SRC 0 SRC 0 5 10 3
28. tial mode biasing 0 0 0 eee 15 5 2 2 Single ended mode biasing aa 16 9 2 9 INCM biasing LL 19 5 3 Output code vs analog input and mode usage 19 5 3 1 Differential mode output code 20 5 3 2 Single ended mode output code 0 ee 20 5 4 Design examples llle 21 Differential mode ius actas CE on Roo CREE Ja ec Rte RC LR RS RSE CU GC 21 Single ended mode ler 22 5 5 Reference connections ccc lees 24 5 5 1 Internal voltage reference 0 0 cece 24 5 5 2 External voltage reference aa 24 5 6 CIOCKIAPUE PAA 26 5 7 Keset Ol RAF 1201 aux c atu tht mata im hbo ee een he eae ee 26 5 8 RHF1201 operating modes a 27 5 8 1 DIGHALINQUIS ocd os bs Be ore EHS EY ei eS Ate Se a a 2 5 8 2 Digital outputs a na aana aaa ees 28 5 9 Digital output load considerations 29 2 38 DocID012585 Rev 7 Ly RHF1201 10 Contents 5 10 PCB layout precautions 0 a 29 Definitions of specified parameters 30 6 1 Static parameters 30 6 2 Dynamic parameters a 30 Package information israeliana 32 7 1 S048 package information 0 0 aa 33 Ordering information 0 000 ces 34 Other information 00 0 ccc ees 35 9 1 Dato COGO idrici 35 9 2 Documentation a enn anice PA ee CHAE ew ee eee a diea 35 Revision history ei snuukeri t 36 DocID0
29. to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved a 38 38 DoclD012585 Rev 7
30. voltage VREFP Top internal reference bia rice I 0 79 0 95 1 16 Se Tee ey 9 A zu Outputresistance ofintemal Vere 2 o out Temperature coefficient of E TempCo don lamp Emax 0 12 mV C Temperature coefficient of INCM coefficient of INCM Temperature coefficient of INCM Refer to Section 5 2 Driving the analog input how to correctly bias the RHF1201 for correct biasing of RHF1201 2 Notfully tested over the temperature range Guaranteed by sampling Table 8 Static accuracy Fi 2 MHz Differential non linearity 1 Vin 1Vp p 0 5 Fs 50 Msps Fi 2 MHz Integral non linearity Vin 1Vp p 1 7 Fs 50 Msps See Section 6 for more information y DocID012585 Rev 7 11 38 Electrical characteristics unchanged after 300 kRad RHF1201 Table 9 Digital inputs and outputs Clock input CT Clock threshold IDVoc 25V IDVoc 25V 5 V ELA amplitude Square clock DC component 1 25 V DVcc 2 5 V Digital inputs Logic 0 voltage 0 25 x VCCBE y VCCBE Digital outputs V am AE High impedance leakage current OEBsetto Viu set to OEBsetto Viu Table 10 Dynamic characteristics sei reramete testconone ma ve Mer une meme E E Spurious free dynamic range Fip 95MHz 30 eme 9 sme so 9 Signal to noise ratio Fip 95MHz 6 amp 6 mcwsws 9 Ross Total harmonics distortion Fip 95MHz r2 Asse o
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