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LC872R00 SERIES USER`S MANUAL

1. 3 1 8 3 4 5 HALT and HOLD Mode Operation AS 3 1 8 3 5 Timer Counter 0 TO sanansananassasansasananuananausanansananansananaasanansauanausanansananansauanauuann 3 1 9 3 5 1 Overview rn rra 3 19 3 5 2 Eunctions 3 19 3 5 3 Circuit Configuration rro 3 20 3 5 4 Related Registers AA IA 3 25 3 6 Timers 6 and 7 6 7 0 0 0 0 3 28 3 6 1 Overview BRRRRRRRRRRRRRRRRRRRRRRRERSARRSAERSAERSAERSASERSSERSSERSSENSRERRSERRSSRRRERRREREGRERERSRERERERSRERE REGN 3 28 3 6 2 Functions A 3 28 3 6 3 Circuit Configuration rro 3 28 3 6 4 Related Registers AA IT 3 31 3 7 Serial Interface 1 SIO1 sasansasanausanansanananusananassanansananausanansananansanansasanansauanausana 3 33 3 7 1 Overview rn rra 3 33 3 7 2 Functions IIS 3 33 3 7 3 Circuit Configuration rana 3 34 3 7 4 SIO1 Communication Examples rro 3 38 3 7 5 Related Registers rhsssusushassuasshussuassuasunasunanusnansnanusanusanusanssasusassuanusanssasurasusasusae 3 42 3 8 AD Converter ADC12 sasansasanansauanausanansasanansananausananassanansananansananauuanansasanannuan 3 44 3 8 1 Overview rn rra 3 44 3 8 2 Functions IIS 3 44 3 8 3 Circuit Configuration nena 3 45 3 8 4 Related Registers ra 3 45 3 8 5 AD Conversion Example rro 3 49 3 8 6 Hints on the Use of the ADC no 3 50 11 Con
2. Interrupt control 4 gt gt IR PLA Standby control gt Flash mask ROM 1 O n 1 9 gt 90 RC 2 gt MRC RES 9 ACC CO wT 3 __ B Reset circuit 9 4 register LVD POR register lt gt gt 8101 Bus interface gt 0 4 9 gt Port 0 4 Timer 6 lt gt Port 1 PSW Timer 7 gt Port 2 gt ADC lt Port 7 INTO INT2 lt gt Stack pointer INT3 w noise filter lt gt Port2 INT4 4 On chip debugger 1 6 LC872R00 Chapter 1 1 5 Pin Functions Name Description VSSI power supply pin VDDI power supply pin LO 8 bit port POO to P07 I O specifiable in 4 bit units Pull up resistors can be turned on and off in 4 bit units HOLD release input Port 0 interrupt input Pin functions P06 Timer 6 toggle output P07 Timer 7 toggle output POO ANO to POG ANO AD converter input P05 to PO7 DBGP02 On chip debugger 0 pin P20 P21 O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Pin functions P20 P21 INT4 input HOLD release input timer OL capture input timer OH capture input Interrupt acknowledge type Rising Falling amp H level L level Falling Port 7
3. bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INT interrupt request enable bit INTIIE are set to 1 HOLD mode release signal and an interrupt request to vector address OOOBH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detected Low level detected 0 A rn ego eee 7 INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 2 3 5 External interrupt 2 3 control register 123CR 1 This register is 8 bit register for controlling ex
4. 5 axmwr Priority levels X gt gt L When interrupts of the same level occur at the same time an interrupt with the smallest vector address is given priority 1 2 LC872R00 Chapter 1 Subroutine stack levels Up to 64 levels stack is allocated in RAM e High speed multiplication division instructions e 16 bits x 8 bits 5 Tcyc execution time e 24 bits x 16 bits 12 Tcyc execution time e 16 bits 8 bits 8 Tcyc execution time e 24 bits 16 bits 12 Tcyc execution time e Oscillator circuits e Internal oscillator circuits 1 Medium speed RC oscillator circuit For system clock 1 MHz 2 Variable modulation frequency RC oscillator circuit For system clock 8 MHz e External oscillator circuit 1 High speed CF oscillator circuit For system clock with internal Rf lt 1 gt The CF oscillator circuit stops operation on a system reset When the reset is released the CF oscillator circuit resumes operation O System clock dividing function Can run on low current The minimum instruction cycle can be selected from among 300 ns 600 ns 1 2 us 2 4 us 4 8 us 9 6 us 19 2 us 38 4 us and 76 8 us at a main clock rate of 10 MHz Internal reset circuits e Power on reset POR function 1 reset is generated only at power on time 2 The POR release level can be selected from among 8 levels 1 67V 1 97V 2 07V 2 37V 2 57V 2 87V 3 86V and 4 35V b
5. Por AD analog tinput Poo None Table of Port 0 multiplexed pin functions Programmable if CMOS option is selected Port 0 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 1 Port Block Diagram PODDR FE41 Interrupt request to vector 0004B PO FEAO bit 7 Pin 7 input data PO FE40 bit 6 Pin P06 input data PO FE40 bit 5 Pin PO5 input data PO FE40 bit 4 Pin P04 input data PODDR FE41 bit 1 PO interrupt detect PO interrupt detect PO FE40 bit Pin input data PO FE40 bit 2 Pin P02 input data PO FE40 bit 1 Pin 1 input data PO FE40 bit 0 Pin POO input data PODDR FE41 bit O Port 0 Interrupt Block Diagram 2 1 872800 APPENDIX II Function outputs 7 6 P1FCR FE46 bits 7 6 D W P1FCR 24 a lt lt Low PU a R P1FCR P1 FE44 bits 7 6 D CMOS W P1 9 XOR P17 P16 5 INT2 INT1 L R P1 P1DDR FE45 bits 7 6 W P1DDR 2 aa Function output 5 3 Table of Port 1 multiplexed pin functions P1FCR FE46 bits 5 0 o abel W P1FCR C Low PU R P1FCR d 2 P1 FE44 bits 5 0 D CMOS or in C Q Nch OD pi P15 P10 lt bone lt Special input L INT3 P15 P1DDR FE45 bits 5 0 W P1DDR R P1DDR I Port 1 Block Diagram Option Output type CMOS or N
6. 1 22 3 Re _ 42 1 A Be gt a eee es A AAA NEN 49 EE A EEE 22 reer 1 yA O 2222 2272 re y FE92 FE93 FEM TT A SS o erf AAA AAA AA MAA s ft a gt gt _ LI un FE9A FE9B AI 5 Address Initial value 10872800 Remarks BIT8 B1T7 BIT6 BITS BIT3 BIT2 BITI BITO FE9C LC872R00 APPENDIX I 7k LA Initial value R 10872800 Remarks BIT8 B1T7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FEBC AI 8 1 872800 APPENDIX II o T7OUT P07 TeoUT POe 5 PO FE40 bits 7 5 D W PO Q Pin E P07 P05 6 5 R PO Low PU Hi PU Mi PO FE40 bit 4 D Q 1 8 L PO FE40 bits 3 0 D Q Pull up resistor is Not attached if Nch OD option is selected P03 P00 AD input 7 5 4 1 PODDR FE41 Port Special Funcion mpu Funcion Ouput Por imerTiogge output P06 AD analog input Timer 6 toggle output ros AD analog 5 input Noe _ Poa ADanaog4iput None Pos AD analog 3 input None AD analogzinput None
7. From POR Connect an external diode Figure 4 6 8 Sample External POR Circuit Configuration 4 33 Internal Reset 4 34 Appendixes Table of Contents Appendix l Special Functions Register SFR Appendix ll Port 0 Block Diagram Port 1 Block Diagram Port 2 Block Diagram Port 7 Block Diagram LC872R00 APPENDIX I Address Initial value R W LC872RO0 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO 0 007F R W RAM128B 9 bit long Eo TF m MOI O X PM ry wee am Kw 00009894 R R R xus ms us xr xw rm wo P ies ims ims rw wm Ra SA s si so oom Ra s sz sw ro mem ee XXXX MRCSEL RCCTD4 RCCTD3 RCCTD2 RCCTD1 RCCTDO 0 RA 0 NTT end KYB road atts Danas Xr ur wr SYS ems rro TOM
8. HALT mode entry conditions PCON register FEO7H bit 1 set to 0 and bit O to 1 HALT mode release conditions Interrupt request accepted Note 2 Resetting conditions established Note 1 Note 1 The CPU enters the reset state when the resetting conditions are established Note 2 The CPU cannot return from HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into HALT or HOLD mode Interrupt level at which the CPU entered HALT or HOLD mode No interrupt request present Interrupt request level that can release HALT mode X H and L levels L level X and H levels H level X level X level None unable to release with interrupt Fig 4 3 1 4 17 Standby Mode State Transition Diagram Reset 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or when it is running 4 4 2 Functions This series of microcontrollers provides the following three types of reset function 1 External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200 us or longer Note however that a low level of a small duration less than 200 us is likely to trigger a reset The RES can be used as a power on reset pin when it is provided with an external time constant element 2 Interna
9. j4 1 Zt 1 1 Reset undefined 1 i 1 1 1 region POUKS RES There exists an undefined region POUKS before the POR transistor starts functioning normally The POR function generates a reset only when the power is turned on starting at the VSS level The reset release voltage in this case may have some range Refer to the latest SANYO Semiconductor Data Sheet for details No stable reset will be generated if power is turned on again if the power level does not go down to the VSS level as shown in a If such a case is anticipated use the LVD function together as explained in 2 or implement an external reset circuit A reset is generated only when the power level goes down to the VSS level as shown in b and power is turned on again after this condition continues for 100ys or longer 2 Waveform observed when both POR and LVD functions are used Reset pin Pull up resistor Regs only LVD hysteresis width LVD release voltage LVHYS LVDET LVHYS LVD reset voltage LVDET i A ds nek dez m Reset period N as Reset period P i Pr Reset undefined 1 1 E bo region LVUKS p enr E i There also exists undefined region LVUKS before the transistor starts functioning normally when both POR and LVD functions are used Resets are generated bo
10. LC872R00 Chapter 4 4 Reset state entry conditions Low level applied to RES pin e All modes Reset signal generated by watchdog timer Reset signal generated by internal reset circuit HOLD mode entry conditions PCON register FEO7H bit 1 set to 1 HOLD mode All oscillators stopped Since OCR register bits 1 4 and 5 are cleared medium speed RC oscillator starts oscillation as system clock when CPU exits HOLD mode Since MRCR register bits 6 and 7 are cleared the VMRC oscillator is held stopped even after the this mode is exited CPU and peripheral modules are stopped HOLD mode release conditions INTO or INT1 level interrupt request generated Request for INT2 INT4 or port 0 interrupt generated Resetting conditions established Note 1 HALT mode e Reset Main clock stopped in reset state started after reset state is released Medium speed RC oscillator started VMRC oscillator stopped All registers initialized 4 Reset state cancellation conditions Lapse of predetermined time after resetting conditions are cancelled e Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally All oscillators retain the state established when HALT mode is entered CPU stopped Peripheral modules keep running
11. MOV 55H WDT Instruction gt Pulse stretcher circuit WDT FEOF Fig 4 5 1 Watchdog Timer Circuit 4 5 4 Related Registers 4 5 4 1 Watchdog timer control register WDT Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEOF 0H00 H000 R W WDT WDTFLG WDTB5 WDTHLT WDTCLR WDTRST WDTRUN Bit Name Function Runaway detection flag WDTFLG bit 7 0 No runaway Runaway WDTBS bit 5 General purpose flag Can be used as a general purpose flag HALT HOLD mode function control WDTHLT bit 4 0 Enables the watchdog timer 1 Disables the watchdog timer EET ES 5 NN WDTCLR bit 2 0 Disables clearing of the watchdog timer 1 Enables clearing of the watchdog timer WDTRST bit 1 0 Disables a reset when a runaway condition is detected 1 Triggers a reset when a runaway condition is detected NM S LN WDTRUN bit 0 0 Maintains watchdog timer operating state WDTFLG bit 7 Runaway detection flag This bit is set when a program runaway condition is detected by the watchdog timer The application can identify the occurrence of a runaway condition by monitoring this bit provided that WDTRST is set to 1 This bit is not reset automatically It must be reset with an instruction WDTEB5 bit 5 General purpose This bit can be used as a general purpose flag Manipulating this bit exerts no influence on the operati
12. 3 48 LC872R00 Chapter 3 8 4 4 AD conversion result register high byte ADRHC 1 This register is used to hold the higher order 8 bits of the results of an AD conversion that is carried out in the 12 bit AD conversion mode The register stores the whole 8 bits of an AD conversion that is carried out in the 8 bit AD conversion mode 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESB 0000 0000 R W ADRHC DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATA DATAO 3 8 5 AD Conversion Example 3 8 5 1 12 bit AD conversion mode 1 Setting up the 12 bit AD conversion mode Set the ADMD3 bit bit 6 of the AD mode register ADMRC to 0 2 Setting up the conversion time To set the conversion time to 1 32 frequency division set ADTM2 bit 0 of the AD conversion result register low byte ADRLC to 1 ADTMI bit 1 of the AD mode register ADMRC to 0 and bit 0 of the AD mode register ADMRC to 1 3 Setting up the input channel When using AD channel input ANS set AD control register ADCRC ADCHSEL3 bit 7 to 0 ADCHSEL2 bit 6 to 1 ADCHSEL1 bit 5 to 0 and ADCHSELO bit 4 to 1 4 Starting AD conversion Set ADSTART bit 2 of the AD control register ADCRC to 1 The conversion time is doubled after a
13. 3 When data is written into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 28 LC872R00 Chapter 3 6 3 3 Timer 6 prescaler 6 bit counter 1 This prescaler is used to define the clock period for the timer 6 determined by T6CO and T67CNT FE78 bits 4 and 5 Table 3 6 1 Timer 6 Count Clocks T6CO T6 Count Clock 0 Timer 6 prescaler and timer counter are reset 16 3 6 3 4 Timer 6 period setting register 8 bit register 1 This register defines the clock period for timer 6 2 When data is written into T6R while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 6 3 5 Timer 7 counter T7CTR 8 bit counter 1 This counter counts the number of clocks from the timer 7 prescaler T7PR The value of timer 7 counter T7CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 7 period setting register T7R when the interrupt flag T7OV is set 2 T7CO and T7C1 T67CNT FE78 bits 6 and 7 are set to 0 the timer 7 counter stops at a count value of 0 In the other cases the timer 7 counter continues operation 3 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again 3 6 3 6 Timer 7 prescaler T7PR 6 bit counter 1 This prescaler is used
14. FE11 0000 0000 TOPRR 12714 TOPRR7 TOPRR6 TOPRR5 TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO max 256Tcyc ri amp rs amp re oo 0x0 RA 0000 0000 em TONO Timer 0 capture register L TOOLS TOGAL2 TOCNO 17 XXXX TOCAH Herten register TOCAH7 TOCAHG TOCAH5 TOCAH4 TOCAH3 TOCAH2 TOCAHO FE18 AS EEES AA ESA Ferma p f ERE LATA 2 FEID Address Initial value 10872800 Remarks BIT8 B1T7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FE1E mir v mi o ym nn TE TE mm ve E 7 LE EA FE2C I rs _ o O 58405 soria SERGIS SERGIT SERGIO LC872R00 APPENDIX I Address Initial value 10872800 Remarks BIT8 B1T7 BIT6 BITS BIT4 BIT3 B
15. FE43 HHHH OHHH R W XT2PC XTCFIN Bits 7 to 4 and 2 to 0 These bits do not exist They are always read as 1 XTCFIN bit 3 CF1 and CF2 input control 1 This bit and CFSTOP OCR register bit 0 are used to select the function of the and CF2 pins between main clock and general purpose input port pins See 4 2 4 2 Oscillation control register for details 4 2 45 Variable modulation frequency RC oscillator control register MRCR 7 bit register 1 This register is 7 bit register that controls the operation of the variable modulation frequency RC oscillator circuit and selects the main clock Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEOD 00HX XXXX R W MRCR MRCSEL MRCST RCCTD4 RCCTD3 RCCTD2 RCCTDI RCCTDO MRCSEL bit 7 Variable modulation frequency RC oscillator clock select 1 When this bit is set to 1 the variable modulation frequency RC oscillator is selected as the main clock The variable modulation frequency RC oscillator clock will be the system clock if the main clock is selected as the system clock in the above mentioned OCR register 2 When this bit is set to 0 the variable modulation frequency RC oscillator clock is not selected as the main clock CF is selected as the main clock 3 This bit is cleared when the microcontroller enters HOLD mode MRCST bit 6 Variable modulation frequency RC oscillation start control 1
16. 0 0 OFF mener mera 1 maes Bits 7 to 5 These bits do not exist They are always read as 1 P7ODDR bit 4 P70 I O control A 1 or 0 in this bit controls the output N channel open drain input mode of the pin P70 Bits 3 to 1 These bits do not exist They are always read as 1 P7ODT bit 0 P70 data The value of this bit is output from pin P70 when P70DDR is set to 1 Since this bit is of N channel open drain output type however it is placed in the high impedance state when P70DT is set to 1 A 1 or 0 in this bit turns on or off the internal pull up resistor for pin P70 Port 7 3 4 3 2 External interrupt 0 1 control register 101CR 1 This register is an 8 bit register for controlling external interrupts 0 and 1 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 FESD 0000 0000 R W IO0ICR INTILH INTILV INTIIF INTIIE INTOLH INTOLV INTOIF INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P17 Pin Data 0 Falling edge detected Low level detected 0 RN NA E E 1 INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit INTIIE are set to 1 HOLD mode release signal and an interrupt request to vector a
17. TOHR6 TOHRS TOHR4 TOHR3 TOHR2 TOHRO 3 5 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE16 XXXX XXXX R TOCAL TOCAL7 TOCAL6 TOCALS TOCAL4 TOCAL3 TOCAL2 TOCAL1 TOCALO 3 5 48 Timer counter 0 capture register high byte 1 This register is a read only 8 bit register used to capture the contents of timer counter O high byte TOH on an external input detection signal Address Initial Value R W BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE17 XXXX XXXX R TOCAH TOCAH7 TOCAH6 TOCAHS TOCAH2 TOCAHI TOCAHO 3 27 T6 T7 3 6 Timer 6 and Timer 7 T6 T7 3 6 1 Overview The timer 6 T6 and timer 7 T7 incorporated in this series of microcontrollers are 8 bit timers with two independently controlled 6 bit prescalers 3 6 2 Functions 1 Timer 6 T6 Timer 6 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock It can generate at pin P06 toggle waveforms whose frequency is equal to the period of timer 6 T6 period 1 x 4 Tcyc n 1 2 3 Tcyc Period of cycle clock 2 Timer 7 T7 Timer 7 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock I
18. register and the execution of the next instruction No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts No Vector Address Selectable Level Interrupt Sources 10 0004BH HorL Port 0 e Priority levels X gt H gt L When interrupts of the same level occur at the same time the interrupt with the smallest vector address is given priority 7 1 is necessary to manipulate the following special function registers to enable interrupts and to specify their priority JE IP Initial value Name BIT6 BITS BIT4 BIT2 BIT1 BITO 0000 HH00 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO IP FE 0000 0000 ias isp p 123 4 1 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 Thisregister enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 Theregister selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 This register selects the level or L of interrupts to vector addresses 00013H to 0004 BH 4 2 LC872R00 Chapter 4 4 1 4 Related Registers 4 1 4 1 Mast
19. 17 Recommended Unused Pin Connections 1 8 1 8 Port Output Types 1 8 1 9 User Option Table 1 9 Chapter 2 Internal Configuration RUE 2 1 2 1 Memory Space 2 1 2 2 Counter PC 2 1 2 3 Memory ROM 2 2 2 4 Internal Data Memory RAM 2 2 2 5 Accumulator A Register ACC A 2 3 2 6 Register B AO 2 3 2 7 Register
20. 3 31 Ts str ode _ 1 SIT RUN bit 5 SIO1 operation flag 1 Alinthis bit indicates that SIOI is running 2 See Table 3 7 1 for the conditions for setting and clearing this bit SI REC bit 4 SIO1 receive send control 1 Setting this bit to 1 places SIOI into the receive mode 2 Setting this bit to O places SIOI into the send mode SI DIR bit 3 MSB LSB first select 1 Setting this bit to 1 places SIOI into the MSB first mode 2 Setting this bit to 0 places SIOI into the LSB first mode 3 42 LC872R00 Chapter SI1OVR bit 2 SIO1 overrun flag 1 2 3 4 In modes 0 1 and 3 this bit is set when a falling edge of the input clock is detected when SHRUN 0 This bit is set if the conditions for setting SITEND are established when SILEND 1 In mode 3 this bit is set when the start condition is detected This bit must be cleared with an instruction SI1END bit 1 Serial transfer end flag 1 2 This bit is set when serial transfer terminates see Table 3 7 1 This bit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control When this bit and SILEND are set to 1 an interrupt request to vector address 003BH is generated 3 7 5 2 D 2 3 Serial buffer 1 SBUF1 Serial buffer 1 is a 9 bit register used to store data to be handled during 5101 serial transfer The lower order 8 bits of SBUFI are transferred to the data shift register for data tra
21. P70 x x 8 bit I O port I O specifiable in 1 bit units pi Pull up resistors can be turned on and off in 1 bit units Pin functions P13 SIO1 data output P14 SIO1 data input bus I O P15 SIO1 clock I O INT3 input with noise filter input timer 0 event input timer OH capture input P16 INT2 input HOLD release input timer 0 event input timer OL capture input P17 INT1 input HOLD release input timer OH capture input P15 DBGP10 to DBGP12 On chip debugger 1 pin Interrupt acknowledge type Rising Rising Falling amp H level Falling 1 bit I O port No I O direction specifiable Pull up resistors can be turned on and off Pin functions P70 INTO input HOLD release input timer OL capture input watchdog timer output P70 AN8 AD converter input port Interrupt acknowledge type Rising Rising Falling amp H level L level Falling INTO O O x O O Continued on next page 1 7 yo Description External reset input internal reset output Ceramic resonator input Pin functions General purpose input Ceramic resonator output Pin functions General purpose input 1 6 On chip Debugger Pin Connection Requirements For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and LC872000 Series On chip Debugger Pin Conn
22. Power on reset level 8 levels 1 Due to a selection as mask ROM option the contents cannot be changed after the completion of mask ROM 2 The program start address for mask ROM version will be 00000h 1 9 1 10 2 Internal Configuration 2 1 Memory Space LC872R00 Chapter 2 LC870000 series microcontrollers have the following three types of memory space 256K bytes 128K bytes 2 banks 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared 1 Program memory space 2 Internal data memory space 3 External data memory space Address Program memory ROM bank 1 1FFFFH ROM bank 0 128KB 00000H with the stack area 16M bytes Internal data Address memory space FFFFH Reserved for system FFOOH FEFFH SFR 8 bit some 9 bit FDFFH RAM Stack 64 KB 9 bit config 0000H External data Address memory space FFFFFFH RAM 16 MB 000000H Note SFR is the area in which special function registers such as the accumulator are allocated see Appendixes 1 Figure 2 1 1 2 2 Program Counter PC Types of Memory Space The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The lower order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank sw
23. eieovo rem mw wrest ccros nccros cerpo Creo ww ocr cuser xram Restor crsror amn xref rec sewe 1 4 2 3 Circuit Configuration 4 2 3 1 clock oscillator circuit 1 This circuit is activated for oscillation by connecting a ceramic resonator and a capacitor to the CFland CF2 pins and controlling the OCR and XT2PC registers 2 The data at the CFland CF2 pins can be read as bits 2 and 3 of the OCR register 3 If they are not used for the main clock or as general purpose input ports the general purpose input configuration must be selected and CF1 and CF2 pins must be pulled down to the VSS1 level with a 100 4 2 8 2 Internal medium speed RC oscillator circuit conventional RC oscillator circuit 1 This oscillator oscillates according to the internal resistor and capacitor at 1 MHz standard 2 The clock from the medium speed RC oscillator is selected as the system clock after the reset state or after HOLD mode is released 3 Unlike main clock oscillator the medium speed RC oscillator starts oscillation at a normal frequency immediately after starting oscillation 4 2 8 3 Variable modulation frequency RC oscillator circuit 1 This circuit oscillates according t
24. 1 Falling edge of clock detected when 1 Falling edge of clock detected when lt 1 SILEND set conditions met when SIIEND 1 1 Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions SIIRUN 0 2 SIIEND set conditions SIIRUN 0 2 SIIEND set conditions met when SIIEND 1 3 Start bit detected eee ew ee Shifter data SBUFI SBUFI SBUFI SBUFI update Shifter at Shifter at Shifter at Shifter at beginning beginning beginning of beginning of of operation of operation operation operation When 8 bit data transferred met when SIIEND 1 met when SIIEND 1 When 8 bit data received Shifter gt SBUFI bits 0 to 7 Automatic Rising edge of 8th clock Rising edge of 8th clock Input data read in on stop bit Input data read in on rising edge of 9th clock Input data read in on rising edge of 9th clock update of SBUFI bit 8 Data input Ns Data 8 bit shift register SIOSF1 output Clock At time At time operation transfer ends starts bir bits bits oita bit2 bio SBUF1 FE35h 25 SIO1 output control P13 port latch P13 output control SIO1 output control BEEN P14 port latch P14 P14 output control C
25. AN6 Initial Value BITO FE40 0000 0000 PO 07 P06 POS P04 POI POO Fre ww roseus rores Porru Poumon POLDDR reo Nw TE 3 1 3 Related Registers 3 1 3 1 Port 0 data latch 1 The port 0 data latch is an 8 bit register for controlling port 0 output data and port 0 interrupts 2 When this register is read with an instruction data at pins POO to 07 is read in If PO FE40 is manipulated using NOTI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the port pins 3 Port 0 data can always be read regardless of the I O state of the port BIT FE40 0000 0000 R W PO 07 06 05 P04 P03 P02 POL POO 3 1 3 2 Port 0 data direction register PODDR 1 This register is an 8 bit register that controls the I O direction of port 0 data in 4 bit units the pull up resistors in 4 bit units and port 0 interrupts Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE41 0000 0000 R W PODDR POHPUS POLPUS POFLG POIE POHPU POLPU POHDDR POLDDR POHPUS bit 7 7 04 high low impedance pull up resistor select A 1 in this bit selects high impedance pull up resistors for pins 7 to P04 and a 0 selects low impedance pull up resistors POLPUS bit 6 PO3 POO high low impedance pull up r
26. C AO 2 4 2 8 Program Status Word PSW 2 4 2 9 Stack Pointer SP 2 2 10 Indirect Addressing Registers 2 5 2 1 1 Addressing Modes 2 6 2 1 1 1 Immediate Addressing 2 6 2 1 1 2 Indirect Register Indirect Addressing Rn 2 7 2 11 3 Indirect Register C Register Indirect Addressing Rn C 8 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off 2 8 2 1 1 5 Direct Addressing dst A 2 8 2 1 1 6 ROM Table Look up Addressing AO 2 9 2 1 1 7 External Data Memory Addressing IO 2 9 Chapter 3 Peripheral System Configuration dadas 3 1 3 1 Port 0 o 3 1 3 1 1 Overview 3 1 3 1 2 Functions A 3 1 3 1 3 Rel
27. Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE4B 0000 0000 R W 14551 FIXO FIXO FIXO FIXO 14SL3 14SL2 I4SL1 14510 bits 7 4 These bits must always be set to 0 14SL3 bit 3 INT4 pin select 14SL2 bit 2 INT4 pin select 14SL3 14SL2 Pin Assigned to INT4 0 Port P20 0 14SL1 bit 1 INT4 pin function select 14SLO bit 0 INT4 pin function select When the data change specified in the external interrupt 4 5 control register I45CR is given to the pin that is assigned to INT4 timer 0 capture signal is generated 14SL1 14SLO Function Other Than INT4 Interrupt None Po 31 we 1 b Timer OL capture signal input Timer OH capture signal input Notes 1 If timer OL capture signal input and timer OH capture signal input for INT4 are assigned to P70 or P17 to P15 at the same time the signal from port 7 or port is ignored 3 3 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 3 5 HALT and Hold Mode Operation When in HALT or HOLD mode port 2 retains the state that is established when HALT or HOLD mode is entered Port 7 3 4 Port7 3 4 1 Overview Port 7 is a 1 bit I O port equipped with programmable pull up resistors It is made up of a data control latch and a control circuit Port 7 can be used as an input port for e
28. P14 Consequently if the transmit port is assigned to the data output port P13 it is likely that data transmissions are started unexpectedly according to the changes in the state of P14 5 Starting receive operation Set SIIREC to 1 Once is set to 1 do not attempt to write data to the SCONI register until the SIIEND flag is set Detect the falling edge of receive data 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW e Clear SILEND and exit interrupt processing Return to step 4 when repeating processing Note Make sure that the following conditions are met when performing continuous reception processing with 5101 in mode UART The number of stop bits is set to 2 or greater Clearing of SILEND during interrupt processing terminates before the next start bit arrives 3 7 4 8 mode mode 2 1 Setting the clock Setup SBRI Setting the mode N Set as follows SIIMO 0 SIMI 1 SIIDIR SILE 1 0 3 Setting up the ports Designate the clock and data ports as N channel open drain output ports 4 Starting communication sending an address Load SBUFI with address data Set SIIRUN transfer a start bit SBUFI 8 bits stop bit H 5 Checking ad
29. Pin Connection Requirements 3 1 2 Functions 1 Input output port 8 bits 7 The port output data is controlled by the port 0 data latch PO FE40 in 1 bit units control of to is accomplished by POLDDR PODDR FE41 bit 0 control of P04 to P07 is accomplished by POHDDR PODDR FE41 bit 1 Ports selected as CMOS outputs by user option are provided with programmable pull up resistors The programmable pull up resistors may be of either low impedance or high impedance type The programmable pull up resistors for POO to P03 are controlled by the POLPU PODDR FE41 bit 2 Their type either low impedance or high impedance is selected by POLPUS PODDR FE41 bit 6 The programmable pull up resistors for P04 to 7 are controlled by POHPU PODDR FE41 bit 3 Their type either low impedance or high impedance is selected by POHPUS PODDR FE41 bit 7 2 Interrupt pin function POFLG PODDR FE41 bit 5 is set when an input port is specified and 0 level data is input to one of port bits whose corresponding bit in the port O data latch PO FE40 is set to 1 In this case if POIE PODDR FE41 bit 4 is 1 HOLD mode is released and an interrupt request to vector address 004BH is generated 3 1 Port 0 3 Multiplexed pin function Pin P06 also serves as the timer 6 toggle output pin P07 as the timer 7 toggle output and POO to P06 as the analog input channel pins ANO to
30. When Disable is selected no LVD reset is generated Note 2 In this configuration no operating current will flow in all modes See the sample operating waveforms of the reset circuit shown in Subsection 4 6 5 for details 2 LVD reset level option The LVD reset level can be selected from 7 level values only when Enable is selected in the LVD reset function options Select the appropriate detection level according to the user s operating conditions 3 release level option The POR release level can be selected from 8 levels only when Disable is selected in the LVD reset function options When not using the internal reset circuit set the POR release level to the lowest level 1 67V that will not affect the minimum guaranteed operating voltage Note 3 No operating current flows when the POR reset state is released Note 4 See the notes in paragraph 2 of Subsection 4 6 6 when selecting a POR release level that is lower than the minimum guaranteed operating voltage 1 67V 4 27 Internal Reset e Selection example 1 Selecting the optimum LVD reset level to keep the microcontroller running without resetting it until VDD falls below 2 7V according to the set s requirements Set the LVD reset function option to Enable and select 2 51V as the LVD reset level Set operating range VDD 2 7V LVD release voltage LVDET LVHYS LVD reset voltage LVDET Typ 2 51V e Selection exa
31. a high edge or both edges and sets the interrupt flag These two selected ports can also be used as timer 0 capture signal input 3 Hold mode release function When the interrupt flag and interrupt enable flag are set by INT4 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode medium speed RC oscillator selected as system clock When the interrupt is accepted the CPU switches from HALT mode to normal operation mode When a signal change that sets the INT4 interrupt flag is input in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INT4 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 it is recommended that INT4 be used in the double edge interrupt mode Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE48 HH00 R W P2 P21 P20 Cres mense ww ymo iras 3 11 Port 2 3 3 3 Related Registers 3 3 3 1 Port 2 data latch P2 1 The port 2 data latch is a 2 bit register for controlling port 2 output data and pull up resistors 2 When this register is read with an instruction data at pins
32. a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the type of microcontroller The ROM table look up instruction LDC can be used to reference all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 LC872R00 series 1FOOH to 1FFFH is reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM This series of microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the type of the microcontroller Nine bits are used to access addresses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table look up instruction LDC however their bit length is set to 17 bits 9 higher order bits 8 lower order bits As shown in Figure 2 4 1 the available instructions vary depending on the RAM address The efficiency of the ROM used and a higher execution speed can be attempted using these instructions properly 2 2 LC872R00 Chapter 2 FFFFH Reserved for system FFOO
33. bit 6 This bit controls the output data at pin P06 It is disabled when P06 is in input mode When P06 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 6 and the value of the port data latch 3 3 Port 0 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output 3 1 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port 0 retains the state that is established when HALT or HOLD mode is entered 3 4 LC872R00 Chapter 3 2 1 3 2 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit Control of the input output signal direction is accomplished by the data direction register in 1 bit units Port 1 can also be used as a serial interface I O port by manipulating its function control register As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units lt Notes on the flash ROM version gt Port PIS is temporarily set low when the microcontroller is reset During the reset sequence do not apply a clock or any medium voltage level signal including Hi Z to port P13 F
34. channel OD selectable in 1 bit units 3 Port Block Diagram Low PU P2 FE48 bits 1 0 W P2 P21 P20 Special input R P2 INT4 P21 P20 P2DDR FE49 bits 1 0 W P2DDR R P2DDR Special Function Input Function Output NT4 Timer OL capture Timer OH capture input NT4 Timer OL capture Timer OH capture input Table of Port 2 multiplexed pin functions Port 2 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units Interrupt request to vector 00013 I45SL FE4B Timer OL capture signal Timer OH capture signal Port 2 Interrupt Block Diagram 4 1 872800 APPENDIX II Low PU 5 a HALT HOLD _ 7 5 bit 0 D Q 9 Pin Hk P70 W P7 5 AD input 8 L R P7 INTO P7 bit 4 D Q From watchdog timer Special Function Input Function Output INTO Timer OL capture AD analog 8 input Table of Port 7 multiplexed pin functions Port 7 Block Diagram Option None 5 Port Block Diagram rje srejs ej o B Timer 0 clock input AL INT3 s Teese A B Timer OH capture signal gt L Interrupt request to vector 00013 pers pedo Era I23CR FEBE Interrupt request to vector 0001B E INT2 Sw S Timer oL capture signal E INTA L level Interrupt request to vector 00003 Interrupt r
35. contents 16 bits of either Rn Rn C or RO off as the lower order bytes of the address Examples LDW 34569 Sets up the lower order 16 bits STW RO Loads the indirect register RO with the lower order 16 bits of the address MOV 12H B Sets up the higher order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123457 to the accumulator 2 9 Table 2 4 1 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction Bit 8 RAM SFR P1 PSW Bit 1 Remarks LD LDW PI REGS PI REGHS PUSH P RAMS8 PI PUSH BA RAMH8 lt P1 RAML8 lt P1 poc REG8 lt RAM8 PI lt RAM8 POPW REGH8 lt RAMH8 REGL8 lt RAML8 PIX RAMH8 POP gt PL RAMI bit 1 POP BA gt PRAM a Same as left PEONO EL 8 lt P1 lt REGH8 Same as left computation computation computation DECW DEC 17 bits P1 lt REGH8 after EA A E EA ari PS E EX E E 5 5 P1 bitl when PSW is popped 1 lt when higher order address of PSW is popped BITS ignored INC 9 bits INC 17 bits DEC 9 bits DEC 17 bits DEC 9 bits check lower order 8 bits DEC 9 bits check lower order 8 bits Bit 8 of RAM address for storing results is set to 1 Note I is read and processed if the processing target is an 8 bit register no bit 8 Legends REGS Bit 8 of a RAM or SFR location R
36. enable status If the interrupt request is legitimate for processing the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the old state of the PC and interrupt level Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H and highest level X The interrupt function will not accept any interrupt requests of the same level or lower level than that of the interrupt that is currently being processed Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests When interrupts of the same level occur at the same time an interrupt with a smaller vector address is given priority Interrupt request enable control The master interrupt enable register IE can be used to control the enabling disabling of H and L level interrupt requests Interrupt requests of the X level cannot be disabled Interrupt disable period e Interrupts are held disabled for a period of 2Tcyc after a write is made to the IE FEO8H IP 9 register or HOLD mode is released No interrupt can occur during the interval between the execution of an instruction that loads the PCON
37. flag is supplied to the port selected from P17 and P15 When a selected level of signal is input to P17 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle interval for the duration of the input signal 3 5 Port 1 6 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INT1 or INT2 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode system clock set to medium speed RC When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When level of signal that sets an interrupt flag is input to P17 that is specified for level triggered interrupts in HOLD mode the interrupt flag is set In this case if the corresponding interrupt enable flag is set HOLD mode is released When a signal change that sets an interrupt flag is input to P16 in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however can be set neither by a rising edge occurring when P16 data which is established when HOLD mode is entered is in the high state nor by a falling edge occurring when P16 data which is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in the double edge interrupt mode 7 Multiplexed pin functions P17 is also
38. input control register XT2PC 1 register This register controls the general purpose input at the CF1 and CF2 pins Variable modulation frequency RC oscillation control register MRCR 7 bit register This register controls the start stop operation of the variable modulation frequency RC oscillator circuit The register selects either CF or variable modulation frequency RC oscillator as the main clock source The register also defines the frequency of the variable modulation frequency RC oscillator clock System clock division control register CLKDIV 3 bit register This register controls the operation of the system clock divider circuit The division ratios of i i d ores ui and are supported 4 8 16 32 64 128 MRCSEL CLKCB5 4 i2 8 Main clock CLKSGL CLKDV2 to 0 MRCST gt Variable modulation MRCSFT gt a m oscillator c e RCCTD4 to0 gt 5 5 System clock 5 SCLK 0 2 2 ium RC clock RCSTOP Internal medium speed RC oscillator fSCLK System clock frequency fCYC Cycle clock frequency minimum instruction cycle fCYC fSCLK 3 Fig 4 2 1 System Clock Generator Block Diagram 4 7 System Clock 4 2 4 Related Registers 4 2 4 1 Power control register PCON 2 bit register 1 This register is a 2 bit register used to specify the operating mode normal HALT HOLD See Section 4 3 Standby Function for the procedures to enter and exit the microco
39. is higher than that of the port inputs and the interrupt detection level Refer to the latest SANYO Semiconductor Data Sheet for the input levels e High threshold o Watchdog timer Port 7 circuit interrupt MOV 55H WDT Instruction TOLCP Figure 4 5 2 P7O INTO TOLCP Pin P70 Setting Pull up Resistor OFF 4 24 LC872R00 Chapter 4 3 The external resistor to be connected to the watchdog timer can be omitted by setting bits 4 and 0 of the port 7 control register P7 FESC to 0 and 1 and connecting a programmable pull up resistor to the P70 INTO TOLCP pin see Figure 4 5 3 The resistance of the pull up resistor to be adopted in this case varies according to the power source voltage VDD Calculate the time constant of the watchdog timer while referring to the latest SANYO Semiconductor Data Sheet I HALT HOLD R P7ODT FE5C bit 0 Watchdog timer P7O INTO TOLCP Port 7 circuit interrupt C E E A MOV 55H WDT Instruction P70DDR FESC bit 4 7 bit 0 Figure 4 5 3 Sample Application Circuit with Programmable Pull up Resistor 4 When the microcontroller enters HALT or HOLD mode with WDTHLT being set to 1 bits WDTCLR WDTRST and WDTRUN are reset To use the watchdog timer function after the microcontroller returns to the normal operating mode from HALT or HOLD mode initialize and set up the watchdog timer again fo
40. port select This bit selects the timer OL capture signal input port When set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select Noise Filter Time Constant 1 STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 When set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 Note If timer OL capture signal input or timer OH capture signal input for INT4 is assigned to P70 or P17 to P15 at the same time the signal from port 7 and port 1 is ignored 3 4 4 Options There is no user option for port 7 3 4 5 HALT and HOLD Mode Operation The pull up resistor to P70 is turned off 3 5 3 5 1 LC872R00 Chapter Timer Counter 0 TO Overview The tim
41. purpose In this case only Rn is configured as 17 bit registers 128K byte space For models with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SET1 or instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678 LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 1 gt gt 16 amp 1 Loads in PSW with bit 16 of the TBL address STW RO Loads indirect register RO with the TBL address bits 16 to 0 LDCW 1 Reads the ROM table B 78H ACC 12H MOV 1 Loads the register with 01H LDCW RO Reads the ROM table B 78H ACC 12H INC C Increments the C register by 1 LDCW R0 C Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW needs to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highest order byte of the address and the
42. the end of data transmission automatically clears 51 and releases the data port However in a case that restart condition comes just after the event SITREC must be set to 1 before exiting the interrupt STIREC is for detecting a start condition and is not set automatically It may disturb the transmission of address from the master if there is an unexpected restart just after slave s transmission when SII REC is not set to 1 by instruction 4e When a stop condition is detected an interrupt is generated and processing returns to 2 in step 7 8 Terminating communication e Set SILREC Return to in step 6 to cause communication to automatically terminate To force communication to termination clear and SIIEND release the clock port e An interrupt occurs when a stop condition is detected Then clear SILEND and SILOVR and return to 2 in step 4 3 7 5 Related Registers 3 7 5 1 SIO1 control register SCON1 1 Thisregister is an 8 bit register that controls the operation and interrupts of SIOI Address Initial Value R W Name BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SIIREC SIIDIR SIIOVR SIIEND SI1M1 bit 7 SIO1 mode control SI1MO bit 6 SIO1 mode control Table 3 7 2 5101 Operating Modes Mode SH M1 SI1M0 Operating Mode Synchronous 8 bit SIO 1 1 stop bit no parity tac m
43. to define the clock period for the timer 7 determined by T7CO and T7C1 T67CNT FE78 bits 6 and 7 Table 3 6 2 Timer 7 Count Clocks T7CO T7 Count Clock 0 Timer 7 prescaler and timer counter are reset i 16 Tcyc 3 6 3 7 Timer 7 period setting register T7R 8 bit register 1 Thisregister defines the period of timer 7 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again 3 29 Timer 6 period setting register T6R FE7Ah Timer 6 counter T6CTR Timer 6 7 control register T67CNT FE78h Set prescaler count value Timer 6 prescaler T6PR T6 overflow T6R 1 x count clock Clock 1Tcyc Timer 6 7 control register T67CNT FE78h T6 interrupt T7 interrupt Timer 7 counter T7CTR Timer 7 prescaler 1Tcyc T7PR Set prescaler count value T7 overflow Timer 6 7 control register T7R 1 x count clock T67CNT FE78h Timer 7 period setting register T7R FE7Bh Figure 3 6 1 Timer 6 7 Block Diagram 3 30 LC872R00 Chapter 3 64 Related Registers 3 6 4 1 Timer 6 7 control register T67CNT 1 This register is an 8 bit register that controls the operation and interrupts of T6 and T7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 T67CNT T7C1 T7CO T6C1 T6CO T7OV T7IE T6OV T6IE T7C1 bit 7 T7 count c
44. vector interrupt feature 1 2 Features e ROM e Flash ROM version LC87F2R04A 4096 x 8 bits Capable of onboard programming with a wide range of supply voltages 2 2 to 5 5V Block erasable in 128 byte units Data can be written in 2 byte units Mask ROM version LC872R04A 4096 x 8 bits RAM e 128 x 9 bits Minimum bus cycle time 83 3 ns 12 MHz VDD 2 7 to 5 5V 100 ns 10 MHz VDD 22 to 5 5V Note The bus cycle time here refers to the ROM read speed e Minimum instruction cycle time Tcyc 250 ns 12 MHz VDD 2 7 to 5 5V 300 ns 10 MHz VDD 2 2 to 5 5V O Ports Normal withstand voltage I O ports Ports whose I O direction can be designated in 1 bit units 11 P20 P21 P70 Ports whose I O direction can be designated in 4 bit units 8 POn e Dedicated oscillator input ports 2 CF1 XT1 CF2 XT2 Reset pin 1 RES e Power pins 2 551 VDDI 1 1 Timers e Timer 0 16 bit timer counter with a capture register Mode 0 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register x 2 channels Mode 1 8 1 timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit counter with an 8 bit capture register Mode 2 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register Mode 3 16 bit counter with a 16 bit capture register Timer 6 8 bit timer with a 6 bit prescaler with toggle outp
45. 0 The external pull up resistor Rres must always be installed even when the set s specifications inhibit the installation of the external capacitor Cres to the reset pin 4 26 LC872R00 Chapter 4 Interior of microcontroller Rres 510 Reset Cres 0 022uF Power on reset POR Low voltage detection reset LVD Pulse stretcher Figure 4 6 1 Internal Reset Circuit Configuration 4 6 4 Options The POR and LVD options are available for the reset circuit 1 LVD Reset Function Options Enable Use Disable Non use 2 LVD Reset Level Option 3 POR Release Level Option Typical Value of Min Operating Typical Value of Min Operating Selected Option VDD Value Selected Option VDD Value 1 67V 1 8V to 1 91V 2 1V to 1 97V 2 1V to 2 01V 2 2V to 2 07V 2 2V to 2 31V 2 5V to 2 37V 2 5V to 2 51V 2 7V to 2 57V 2 7V to 2 81V 3 0V to 2 87V 3 0V to 3 79V 4 0V to 3 86V 4 0V to 4 28V 4 5V to 4 35V 4 5V to The minimum operating VDD value specifies the approximate lower limit of the VDD value that the selected POR release level or LVD reset level can be effected without generating a reset 1 LVD reset function option When Enable is selected a reset is generated at the voltage that is selected by the LVD reset level option Note 1 In this configuration an operating current of several uA always flows in all modes
46. 4 5 3 Circuit Configuration A O 4 20 4 5 4 Related Registers 4 21 4 5 5 Using the Watchdog Timer 4 23 4 6 Internal Reset Function 4 26 4 6 1 Overview A 4 26 4 6 2 Eunctions A 4 26 4 6 3 Circuit Configuration 4 26 4 6 4 Options AO cu sues MUS AAA 4 27 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 4 29 4 6 6 Notes on the Use of the Internal Reset Circuit 4 30 4 6 7 Notes to be Taken When Not Using the Internal Reset 4 32 Appendix l Special Functions Register SFR Map 1 7 Appendix Il Port Block Diagrams 1 1 6 111 LC872R00 Chapter 1 1 Overview 1 1 Overview The LC872R00 series is 8 bit microcomputer that centered around a CPU running at a minimum bus cycle time of 83 3 ns integrates on a single chip a number of hardware features such as 4K byte flash ROM onboard programmable or mask ROM 128 byte RAM a sophisticated 16 bit timer counter may be divided into 8 bit timers two 8 bit timers with a prescaler an asynchronous synchronous SIO interface a 12 bit 8 channel AD converter with 12 8 bit resolution selector a system clock frequency divider an internal reset circuit and 12 source 8
47. 5 LC872R00 Chapter 4 Master interrupt enable control register IE See subsubsection 4 1 4 1 Master interrupt enable control register for details Port 7 control register P7 See subsubsection 3 4 3 1 Port 7 control register for details Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed Select the resistance R and the capacitance C such that the time constant of the external RC circuit is greater than the time interval required to clear the watchdog timer 1 2 Initializing the watchdog timer All bits of the watchdog timer control register WDT are reset when an external reset is triggered through the RES pin If the P70 INTO TOLCP pin has been charged up to the high level discharge it down to the low level before starting the watchdog timer The internal N channel transistor is used for discharging Since it has an on resistance a discharging time equal to the time constant of the external capacitance is required Set bits 0 and 4 of the port 7 control register P7 FESC to 0 0 or 1 1 to make the P70 port output open Starting discharge Load with 04H to turn on the N channel transistor at the P70 INTO TOLCP pin to start discharging the capacitor Checking the low level Checking for data at the P70 INTO TOLCP pin Read the data at the P70 INTO TOLCP pin with an LD or similar instruction A 0 indicates that the P70 INTO TOLCP pin is at th
48. 7 BIT6 5 BIT3 BIT2 BIT1 BITO FEOA 0000 0000 R W SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP SP SP 1 ROMBANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off which use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes These addressing modes use 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM in 1 byte 9 bits units if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 RAM Reserved for system Address 7FH R63 Upper R63 Lower R63 7EH 03H R1 Upper 02H R1 Lower R1 2 01H RO Upper RO 0 Figure 2 10 1 Allocation of Indirect Registers 2 11 Addressing Modes LC870000 series microcontroller
49. Almnthis bit starts the variable modulation frequency RC oscillator circuit 2 AO in this bit stops the variable modulation frequency RC oscillator circuit 3 This bit is cleared when the microcontroller enters HOLD mode RCCTD4 bit 4 RCCTDS bit 3 RCCTD2 bit 2 Variable modulation frequency RC oscillator frequency select RCCTD1 bit 1 RCCTDO bit 0 1 These bits set up the source oscillator clock counter value 2 The frequency of the clock generated by the variable modulation frequency RC oscillator is Source oscillation frequency RCCTD value 1 x 2 3 Theinitial value of RCCTD is undefined Note 1 The system clock may set to an excessively high rate depending on the count value configured This may cause malfunctions if it exceeds the operating clock range Note 2 Data may not be set up properly if the internal medium speed RC oscillator is selected as the system clock and RCCTD is rewritten with MRCSEL bit 7 set to H Be sure to set MRCSEL bit 7 to L when rewriting RCCTD while selecting the medium speed RC oscillator clock as the system clock 4 10 LC872R00 Chapter 4 Note 3 When switching the system clock secure an oscillation stabilization time of 100 us or longer after the variable modulation frequency RC oscillator circuit switches from the oscillation stopped to oscillation enabled state Note 4 The variable modulation frequency RC oscillator circuit may be of 6 or 5 bit counter
50. CMOS 8 BIT MICROCONTROLLER LC872R00 SERIES eel USER S MANUAL ium REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body o
51. CMP flag set Reload flag set TOLR 8 bit programmable timer 8 bit programmable timer with programmable prescaler with programmable prescaler Match buffer register Figure 3 5 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 Clock Clear Registers 101CR FE5Dh 123CR FESEh ISL FESFh Comparator FS I45CR FEAAh and 145SL FE4Bh need setting Capture External Clock gt TOL fe in register ISL FE5Fh Match buffer register TOLCMP flag set TOLR Ceci programmable counter Figure 3 5 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 TOH Match Match buffer register TOHCMP flag set 8 bit programmable timer gt with programmable prescaler 3 23 Clock Clear Match Capture trigger TOCAH TOCAL Registers 101CR FE5Dh I23CR FEBEh ISL FE5Fh l45CR FE4Ah and 145SL FE4Bh need setting Capture Match TOLCMP Match buffer register TOHCMP flag set TOHR TOLR lt 16 bit programmable timer with programmable prescaler Figure 3 5 3 Mode 2 Block Diagram TOLONG 1 TOLEXT 0 Capture trigger TOCAH TOCAL Registers 101 CR FE5Dh Capture I23CR FEBEh ISL FE5Fh External input and 145SL FE4Bh need setting Set in register ISL FE5Fh Match TOLCMP Match buffer register TOHCMP Reload flag set TOHR TOLR e 6 bit programmable counter Figure 3 5 4 Mode 3 Block Diagram TOLON
52. D conversion is in progress Make sure that ADSTART is set to 0 before putting the microcontroller in HOLD mode ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished AD conversion end flag ADENDF is set and at the same time the AD conversion operation control bit ADSTART is reset The end of conversion condition can be identified by monitoring ADENDF Setting ADIE generates an interrupt request to vector address 0043H at the end of conversion Never execute any instructions other than the read branch and compare on the ADCRC register FES8h while conversion processing is in progress However this does not hold true when conversion processing is to be stopped The conversion time is doubled in the following cases The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined using the conversion time calculation formula is adopted in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode The conversion result data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the l
53. Data preserved Data preserved When watchdog timer reset Data preserved Peripheral Stopped State established at entry Stopped modules time Note 2 Exit conditions Entry conditions Interrupt request Interrupt request from canceled accepted INTO to INT2 INT4 or Reset entry conditions POINT established Reset entry conditions established Normal mode Notel HALT Note Data changed on PCON register bit 0 0 PCON register bit 1 0 exit Note 1 The microcontroller switches into the reset state if it exits the current mode on the establishment of reset entry conditions Note 2 Some serial transfer functions are suspended 4 15 Standby Table 4 3 2 Reset Time Normal Mode Pin States and Operating Modes this series HALT Mode HOLD Mode On Exit from HOLD CF oscillation inverter input Oscillation not started Feedback resistor inserted between CFI and CF2 CF oscillation inverter output Oscillation not started Feedback resistor inserted between and CF2 VDD level output present regardless of CFI state Input mode Pull up resistor off CF oscillation inverter input general purpose input controlled by bit 3 of register XT2PC FE43H Oscillation enable disable controlled by register OCR Feedback resistor between CF1 and CF2 controlled by a program CF oscillation inverter input general purpose input co
54. EC bit 4 Clock Port P15 Internal clock Output Data Output Port Data I O Port P13 P14 Data transmission only Output 0 Data reception only Input 1 Data transmission reception 3 wire Input 0 N channel open Data transmission reception 2 wire S t 0 4 Setting up output data Write output data into SBUFI in the data transmission mode SII REC 0 SHREC 5 Starting operation Set SITRUN 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode e Clear SILEND and exit interrupt processing Return to step 4 when repeating processing 3 7 4 2 Asynchronous serial communication mode 1 1 Setting the baudrate Setup SBRI 2 Setting the mode e Set as follows SIIMO 1 SIIMI 0 SIIDIR SITE 1 3 Setting up the ports Data Output Port P13 Data I O Port P14 Data transmission reception 2 wire Output Input Data transmission reception 1 wire N channel open drain output 3 38 LC872R00 Chapter 4 Starting transmission e Set SIIREC to 0 and write output data into SBUFI e Set SIIRUN Note Use the 5101 data port P14 when using the SIO1 transmission only in mode In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode I is on the falling edge of data is always sensed at the data I O port
55. EGHS8 REGLS Bit 8 of the higher order byte of a RAM location or SFR bit 8 of the lower order byte RAMS Bit 8 of a RAM location RAMHS8 RAMLS 8 of the higher order byte of a RAM location bit 8 of the lower order byte 2 10 LC872R00 Chapter 3 Peripheral System Configuration This chapter describes the internal functional blocks peripheral system of this series of microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix for reference 3 1 Porto 3 1 1 Overview Port 0 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction and the pull up resistors is accomplished through the data direction register in 4 bit units This port can also serve as a pin for external interrupts and can release HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output can be selected as the output type in 1 bit units lt Notes on the flash ROM version gt Port 5 is temporarily set low when the microcontroller is reset During the reset sequence do not apply a clock or any medium voltage level signal including Hi Z to port P07 For treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and LC872000 Series On chip Debugger
56. Functions Detection of a runaway condition A program that discharges the RC circuit periodically needs to be prepared If such a program runaways it will not execute instructions that discharge the RC circuit This produces a high potential at the P70 INTO TOLCP pin and the watchdog timer detects a program runaway condition Actions to be taken following the detection of a runaway condition The microcontroller can take one of the following actions when the watchdog timer detects a runaway condition Reset program reexecution External interrupt INTO generation program continuation The priority of the external interrupt INTO can be changed using the master interrupt enable control register IE Circuit Configuration The watchdog timer is made up of a high threshold buffer a pulse stretcher circuit and a watchdog timer control register Its configuration diagram is shown in Figure 4 5 1 High threshold buffer The high threshold buffer detects the charging voltage of the external capacitor Pulse stretcher circuit The pulse stretcher circuit discharges the external capacitor for longer than the specified time to ensure reliable discharging The stretching time is from 1920 to 2048 Tcyc Watchdog timer control register WDT This register controls the operation of the watchdog timer 4 20 LC872R00 Chapter 4 INTO interrupt P70 INTO TOLCP UP gt Interrupt control circuit Reset E
57. G 1 TOLEXT 1 3 24 LC872R00 Chapter 3 5 4 Related Registers 3 5 4 1 Timer counter 0 control register TOCNT 1 This register is an 8 bit register that controls the operation and interrupts of TOL and TOH Address Initial Value R W 7 BIT6 5 BIT3 BIT2 BIT1 BITO FE10 0000 0000 TOCNT TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 0 higher and lower order bytes serve as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is g
58. G DATAS DATA4 DATA3 DATA2 DATA1 DATAO HHHO HHHO P7 1 IO 4 DDR 0 DATA P70DDR P70DT ooo 1 mre TW AI 3 Address Initial value 10872800 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FESE 0000 0000 R W 123CR gt INT3HEG INTSLEG INT3IF INT2HEG INT2LEG INT2IF INT2IE FE RA IS sm NON HON NA pc E NU ERE n i n E co O PR PEA FO PESO Merck Sli A O cit 4 424 2121 112 1 22 AAA 1 20 4815 gt 10 AE A 4 5 2 42 4 25 2 22 2 Busca aire HE SES cs nucum E A E AAA NA is AAA 22222112 4 12 22 452 ASA AAA ER p 1 oee EA A A eee Rope 4 LC872R00 APPENDIX I Address Initial value 10872800 Remarks BIT8 B1T7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FE7D FE7E 0000 0000 FSRO Flash control bit 4 is R O FSROB7 FSROB6 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ Fix to 0 Fix to 0 A AAA 2 5 AE AE A A db s AA AA Fees Feed fT 441111111 ode A ASH A AA le doo a po o A _ HR d cao oe ER
59. H 3 20 3 5 3 2 3 5 3 3 1 2 3 4 3 5 3 4 1 2 3 4 3 5 3 5 1 2 3 4 3 5 3 6 2 3 5 3 7 2 LC872R00 Chapter Programmable prescaler match register TOPRR 8 bit register This register stores the match data for the programmable prescaler Programmable prescaler 8 bit counter Start stop This register runs in modes other than HOLD mode Count clock Cycle clock period 1 Match signal A match signal is generated when the count value matches the value of register TOPRR period 1 to 256 Tcyc Reset The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop This counter is stopped and started by the 0 1 value of TOLRUN timer 0 control register bit 6 Count clock Either a prescaler match signal or an external signal can be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data needs to match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 high byte 8 bit counter Start stop This counter is stopped and started by the 0 1 value of TOHRUN timer 0 control register bit 7 Count clock Either prescaler match signal or TOL match signal can be se
60. H FEFFH SFR space FDFFH 2 900 Stack space 9 bit 0200H 01FFH 0100H Note Some registers 9 bit gt 0000H instruction direct long instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect Non bit instruction direct short Figure 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the lower order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the higher order 9 bits in SP 2 after which SP is set to SP 2 2 5 Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address FEOOH in the internal data memory space and initialized to when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO 00 0000 0000 R W AREG AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREGO 2 6 Register The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to stor
61. HSEL3 CHSEL2 CHSEL1 CHSELO ADERI START ENDF ADIE ADCHSEL3 bit 7 ADCHSEL2 bit 6 ADCHSEL1 bit 5 ADCHSELO bit 4 AD conversion input signal select These 4 bits are used to select the signal to be subject to AD conversion 3 45 12 AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSELO Signal Input Pin P00 ANO PO1 AN1 P02 AN2 P03 AN3 P04 AN4 P05 ANS5 P06 AN6 ADCRC3 bit 3 Fixed bit This bit must always be set to 0 ADSTART bit 2 AD converter operation control This bit starts 1 or stops 0 AD conversion processing Setting this bit to 1 starts AD conversion The bit is reset automatically when the AD conversion ends The time specified by the conversion time control register is required to complete the conversion The conversion time is defined using three bits 1 e the ADTM2 bit 0 of the AD conversion result register low byte ADRLC and the ADTMI and ADTMO of the AD mode register ADMRC Setting this bit to 0 stops the AD conversion No correct conversion results can be obtained if this bit is cleared when AD conversion is in progress Never clear this bit or place the microcontroller in HALT or HOLD mode while the AD conversion processing is in progress ADENDF bit 1 AD conversion end flag This bit identifies the end of AD conversion It is set 1 when AD conversion is finished Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF i
62. IT2 BITI BITO DN o FUE a o R4 WE o PO P P14 FE3E FESF WW FEAT 0060 0000 mm OOHH Hi pore purpose port input control lt 5 07 R EST AAA mm ANTE mm mre m Fimo HA el FE49 HHHH R W P2DDR P21DDR P20DDR ru 000 0000 mo A A O RT 75 EEE peo SEA EE HT AO OA A E EET HATO TE a E Fes ADORO ADGHSELS ADGHSELZ NOGHSELI ADONSELO ADGR ADSTART 0000 0000 Rw 12 bit AD mde Hbi Xo 00000000 12 bit AD conversion result L DA DATALT DAYALO 3 AXL2 FE5B 0000 0000 R W ADRHC 1 2bit AD conversion result H DATA7 DATA
63. NT3IE INT2HEG INT2LEG INT2IF LC872R00 Chapter INT3HEG bit 7 INT3 rising edge detection control INT3LEG bit 6 INT3 falling edge detection control INT3HEG INT3LEG INT3 Interrupt Conditions P15 Pin Data No edge detected Falling edge detected 0 0 Ea bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit must be cleared with an instruction as it is not cleared automatically INT3IE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P16 Pin Data No edge detected Falling edge detected 0 0 oe FRE INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when P16 data
64. P20 and P21 is read in If P2 FE48 is manipulated using the NOT1 CLR1 SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the port pins 3 Port 2 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE48 HHHH R W P2 P21 P20 3 3 3 2 Port 2 data direction register P2DDR 1 This register is a 2 bit register that controls the I O direction of port 2 data in 1 bit units Port P2n is placed in output mode when bit P2nDDR is set to 1 and in input mode when bit P2nDDR is set to 0 2 When bit P2nDDR is set to O and bit P2n of the port 2 data latch is set to 1 port P2n is an input with a pull up resistor Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE49 HHHH R W P2DDR P21DDR P20DDR Register Data Port P2n State Internal Pull up Input Output Resistor Enabled 0 0 oe Enabled Internal pull up resistor OFF o a Enabled High open CMOS N channel open drain 3 3 8 3 External interrupt 4 5 control register 145 1 This register is an 8 bit register for controlling external interrupts 4 and 5 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4A 0000 0000 R W 145 FIXO FIXO INTAHEG INT4LEG INT4IF IN
65. R W Pl P17 P16 P15 P14 P13 P12 P11 P10 3 6 LC872R00 Chapter 3 2 3 2 Port 1 data direction register P1DDR 1 This register is an 8 bit register that controls the I O direction of port 1 data in 1 bit units Port P1n is placed in output mode when bit PInDDR is set to 1 and in input mode when set to 0 2 When bit PInDDR is set to O and bit Pin of the port 1 data latch to 1 port PIn is an input with pull up resistor Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE45 0000 0000 R W PIDDR PI7DDR PI6DDR PISDDR P14DDR P13DDR P12DDR P11DDR P10DDR Register Data Port Pin State Internal Pull up Input Resistor Enabled Enabled Internal pull up resistor oa Enabled High open CMOS N channel open drain 3 2 3 3 Port 1 function control register P1FCR 1 This register is a 3 bit register that controls the multiplexed output of port 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 HH000HHH R W PIFCR PISFCR 4 P1nFCR Pin Pin Data in Output Mode P1nDDR 1 Value of port data latch P15 as SIO1 clock output data Value of port data latch P14 i f o s veo or a 71 ai f o soom SSCS The high data output at a pin that is selected as an N channel open drain output by a user option is represented by an open circuit P15FCR bit 5 P15 fun
66. R area to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when R5 contains OFDFFH and the C register contains 1 since the basic area is 3 RAM stack area 0000H to the intended address OFDFFH 1 lies outside the basic area and OFFH is placed in the ACC as the result of LD If the instruction LD R5 C is executed when RS contains OFEFFH and the C register contains 2 since the basic area is 2 SFR area FEOOH to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of the computation 0FF01 H amp OFFH 0FEO00H 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing In this addressing mode the result of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains FE02H and off has a value of 7EH 2 for example the A register FE02H 2 is designated Examples When RO
67. R00 Chapter 3 7 4 4 Bus slave mode mode 3 1 Setting the clock Setup SBRI to set the acknowledge data setup time 2 Setting the mode e Set as follows SIIMO 1 SIIMI 1 SIIDIR SIIIEz 1 SITREC 0 3 Setting up ports Designate the clock and data ports as N channel open drain output ports 4 Starting communication waiting for an address Set SIIREC 2 SIIRUN is automatically set on detection of a start bit Perform receive processing 8 bits and set the clock output to 0 on the falling edge of the 8th clock which generates an interrupt 5 Checking address data after an interrupt e Detecting a start condition sets SILOVR Check SIIRUN 1 and SIIOVR 1 to determine if the address has been received 5 is not automatically cleared Clear it by instruction Read SBUFI and check the address If no address match occurs clear SITRUN and SIIEND and exit interrupt processing then wait for a stop condition detection at in step 8 6 Receiving data e Clear SIIEND and exit interrupt processing If a receive sequence has been performed send an acknowledge and release the clock port after the lapse of SBRI value 1 x Tcyc e When a stop condition is detected SITRUN is automatically cleared and an interrupt is generated Then clear SILEND to exit interrupt processing and return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the fal
68. R2 TORI T6RO 3 31 4 3 6 43 Timer 7 period setting register T7R 1 This register is an 8 bit register for defining the period of timer 7 Timer 7 period T7R value 1 x Timer 7 prescaler value 4 16 or 64 Tcyc 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 5 BIT3 BIT2 BIT1 BITO FE7B 0000 0000 R W T7R T7R7 T7R6 T7R5 T7R4 T7R3 T7R2 T7R1 T7RO 3 6 44 0 function control register POFCR 1 This register is a 2 bit register that controls the multiplexed output function of port 0 pins It controls the toggle outputs of timer 6 and timer 7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 00HH HHHH R W 7 T6OE T7OE bit 7 This flag is used to control the timer 7 toggle output at pin 7 This flag is disabled when the pin 07 is in input mode When the pin 07 is in output mode A 0 in this bit outputs the value of the port data latch A 1 in this bit outputs the OR of the value of the port data latch and the waveform which toggles at the interval equal to the period of timer 7 T6OE bit 6 This flag is used to control the timer 6 toggle output at pin P06 This flag is disabled when pin 06 is in input mode When pin P06 is in output mode A O in this bit outputs the value
69. R3 Transfers the contents of BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FE02H and the C register contains 1 the address register FE02H 1 FEO1H is designated Examples When R3 contains 123H and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator Li STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of RAM address 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 C L1 Decrements the contents of RAM address 125H by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SF
70. T2 BIT1 BITO FEOE 0H00 XX00 R W CLKSGL 5 CLKCB4 XT2IN XTIIN RCSTOP CFSTOP CLKSGL bit 7 Clock division ratio select 1 When this bit is set to 1 clock selected by bits 4 and 5 is used as the system clock as is 2 When this bit is set to 0 the clock having a clock rate of 5 of the clock selected by bits 4 and 5 is used as the system clock Bit 6 This bit does not exist It is always read as 1 CLKCB5 bit 5 System clock select CLKCBA bit 4 System clock select 4 8 LC872R00 Chapter 4 1 CLKCBS and CLKCB4 are used to select the system clock 2 5 and CLKCBA are cleared at reset time or when HOLD mode is entered CLKCB5 CLKCB4 System clock Medium speed RC oscillator 0 0 pow p e AA iia 7 XT2IN bit 3 CF2 pin data read only XT1IN bit 2 CF1 pin data read only RCSTOP bit 1 Internal medium speed RC oscillator circuit control 1 Setting this bit to 1 stops the internal medium speed RC oscillator circuit 2 Setting this bit to 0 starts the internal medium speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the internal RC oscillator circuit is enabled for oscillation CFSTOP bit 0 Main clock oscillator circuit control 1 Setting this bit to 1 stops the oscillation of the main clock oscillator circuit 2 Setting this bit to 0 starts the oscillation of the main clock oscillator circuit 3 This bit is cleared on a reset OCR Re
71. T4IE bit 7 to FIXO bit 4 These bits must always be set to 0 INT4HEG bit 3 INT4 rising edge detection control INT4LEG bit 2 INT4 falling edge detection control INT4HEG INT4LEG INT4 Interrupt Conditions Pin Data No edge detected Falling edge detected 0 0 ra n 1 o 1 INTAIF bit 1 INT4 interrupt source flag This bit is set when the conditions specified by INT4HEG and INTALEG are satisfied When this bit and the INT4 interrupt request enable bit INT4IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 12 LC872R00 Chapter The interrupt flag however cannot be set by a rising edge occurring when INT4 data which is established when HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data which is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 it is recommended that INT4 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT4IE bit 0 INT4 interrupt request enable When this bit and INT4IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 3 34 External interrupt 4 5 pin select register I45SL 1 This register is an 8 bit register used to select the pin for the external interrupts 4 and 5 Address
72. TOHRUN 1 the match buffer register is loaded with the contents TOHR when a match signal is generated 3 2 3 5 3 8 1 2 3 5 3 9 1 2 Timer counter 0 capture register low byte TOCAL 8 bit register Capture clock External input detection signals from the P70 INTO TOLCP P16 INT2 TOIN and P20 P21 timer OL capture input pins when TOLONG timer 0 control register bit 5 is set to 0 External input detection signals from the P17 INTI TOHCP P15 INT3 TOIN and P20 P21 timer OH capture input pins when TOLONG timer 0 control register bit 5 is set to 1 Capture data Contents of timer counter 0 low byte TOL Timer counter 0 capture register high byte TOCAH 8 bit register Captureclock External input detection signals from the P17 INTI TOHCP P15 INT3 TOIN and P20 P21 timer 0H capture input pins Capture data Contents of timer counter O high byte Table 3 5 1 Timer 0 TOH TOL Count Clocks Mode TOLONG TOLEXT Count Clock TOL Count Clock TOL Count Clock 0 0 0 TOPRR match signal TOPRR match signal a o Pore inte signal Exemdsgat 1 AAA LL rra _ AA 3 22 LC872R00 Chapter Clock Clear p EL Match Capture trigger Registers 101 CR FE5Dh 123CR FES5Eh ISL FE5Fh I45CR FEAAh and 1455 need setting 4 O gt L TOCAL Capture Clear Match Capture TOH TOHCMP TOL
73. a timer module Return to step 6 when continuing data transmission Go to step 10 to terminate communication 8 Receiving data Set to 1 Clear SITEND and exit interrupt processing receive 8 bits SBUFI bit 8 acknowledge output 9 Reading received data after an interrupt Read SBUFI Return to step 8 when continuing data reception Go to step 10 to terminate communication At this moment SBUFI bit 8 data has already been presented as acknowledge data and the clock for the master side has been released 10 Terminating communication Manipulate the clock output port PISFCR 0 PISDDR 1 P15 0 and set the clock output to 0 Manipulate the data output port PI4FCR 0 PIADDR 1 P14 0 and set the data output to 0 Restore the clock output port into the original state PISFCR 1 PISDDR 1 P15 0 and release the clock output Wait for all slaves to release the clock and the clock to be set to 1 Allow for a data setup time then manipulate the data output port 14 0 PI4DDR 1 P14 1 and set the data output to 1 In this case SIO1 overrun flag SCON1 FE34 bit 2 is set but this will exert no influence on the operation of SIO1 Restore the data output port into the original state set PI4FCR to 1 then PIADDR to 1 and P14 to 0 Clear SITEND and SILOVR then exit interrupt processing Return to step 4 to repeat processing 3 40 LC872
74. ammable HALT State State established State established at State established at established at at entry time entry time entry time entry time HOLD Stopped Stopped Stopped Stopped Immediately State Running Stopped Medium speed RC after exit from established at oscillator HOLD mode entry time Note See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes System Clock e Reset clock stopped in reset state and oscillation started when reset state is cleared Medium speed RC oscillator started Variable modulation frequency RC oscillator stopped e HOLD mode All oscillators stopped Since OCR register bits 1 4 and 5 are cleared the medium speed Normal operating mode RC oscillator is activated and Start stop of oscillators designated as system clock when programmable HOLD mode is released Since MRCR register bits 6 and 7 are cleared the variable e HALT mode modulation frequency RC oscillators retain the state oscillator is stopped when HOLD established when HALT mode mode is released is entered 6 Itis necessary to manipulate the following special function registers to control the system clock CLKDIV MRCR XT2PC SLWRC Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH HH00 R W PCON PDN IDLE rene ww
75. ated Registers na 3 2 3 1 4 Options o RR RR RR 3 4 3 1 5 HALT and HOLD Mode Operation A 3 4 3 2 Port 1 ooo 3 5 3 2 1 Overview a 3 5 Contents 3 2 2 Functions rra 3 5 3 2 3 Related Registers 3 6 3 2 4 Options 3 10 3 2 5 HALT and HOLD Mode Operation 3 1 0 3 3 Port 2 See EEE EERE ES 3 1 1 3 3 1 Overview PPP LULL LCL LCE LLL 3 1 1 3 3 2 Functions shssshsusnsusnsusnsuunassnassnansuassnanunansnanusnanusnanusanssanusansuasusanssasusanssanusasusasusae 3 1 1 3 3 3 Related Registers sasashsasusasususususuussususRAsRRARRRASERSSERSESERSSEERSERESSERNSSERESRERERERERERERERERESE 3 1 2 3 3 4 Options rasasusashsususssnsusnuuunausnsuunausnansuansuunsuansuensuensusnssuenssusnusasensuensaensaunssenssenssonsee 3 13 3 3 5 HALT and HOLD Mode Operation 3 1 3 3 4 Port 7 See EERE EEE EERE ES 3 1 4 3 4 1 Overview rn rra 3 14 3 4 2 Functions 3 14 3 4 3 Related Registers eee eee A 3 1 5 3 4 4 Options
76. atest SANYO Semiconductor Data Sheet Make sure that only input voltages that fall within the specified range are supplied to pins PO0 ANO to P06 AN6 and P70 ANS Application of a voltage higher than VDD or lower than VSS to an input pin may exert adverse influences on the converted value of the channel in question or other channels Take the following preventive actions as countermeasures to keep the reduction in conversion accuracy due to noise interferences as low as possible Be sure to add external bypass capacitors several uF and several thousand pF near the VDD1 and VSS1 pins as close as possible desirably 5 mm or less Add external low pass filters RC or capacitors most suitable for noise reduction immediately close to the analog input pins To avert the adverse coupling influences use a ground that is free of noise interferences as the ground for the capacitors rough standard values are R less than 5 kO C 1000 pF to 0 1 Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur Shield both ends of analog signal lines with noise free ground shields Make sure that no digital pulses are applied to or generated out of pins adjacent to the analog input pin that 1s being subject to conversion 11 LC872R00 Chapter Correct conversion results may not be obtained because of noise interferen
77. ces if the state of port outputs is changing To minimize the adverse influences of noise interferences it is necessary to keep the line resistance across the power supply and the VDD pins of the microcontroller at minimum This should be kept in mind when designing an application circuit Adjust the amplitudes of the voltage at the oscillator pin and the I O voltages at the other pins so that they fall within the voltage range between VDD and VSS To obtain valid conversion data perform conversion operations on the input several times discard the maximum and minimum values of the conversion results and take an average of the remaining data 3 51 ADC12 LC872R00 Chapter 4 4 Control Functions 4 1 4 1 1 Interrupt Function Overview This series of microcontrollers has the capability to control three levels of multiple interrupts 1 low level L high level H and highest level X The master interrupt enable register IE and interrupt priority control register IP are used to enable or disable interrupts and to determine the priority of interrupts 4 1 2 Functions 1 Interrupt processing 2 3 4 5 Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 When the microcontroller receives an interrupt request from a peripheral module it determines the interrupt level priority and interrupt
78. cessing Note 1 HOLD mode is entered by setting bit 1 of the PCON register to 1 In this case bit 0 of the PCON register HALT mode setting flag 1s automatically set When a reset occurs or a HOLD mode release signal INTO INT1 INT2 INT4 or POINT is generated bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode Note 1 Do not allow the microcontroller to enter HALT or HOLD mode while AD conversion is in progress Make sure that ADSTART ADCRC register bit 2 is set to O before placing the microcontroller into one of the above mentioned standby modes 4 13 Standby 4 3 3 Related Registers 4 3 3 1 Power control register PCON 2 bit register 1 This register is a 2 bit register that specifies the operating mode normal HALT HOLD See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes 7 HHHH HH00 R W PCON PDN IDLE Bits 7 to 2 These bits do not exist They are always read as 1 PDN bit 1 HOLD mode setting flag 1 This bit must be set with an instruction When the microcontroller enters HOLD mode all oscillations main clock medium speed RC and variable modulation frequency RC are suspended and the OCR register bits 1 4 and 5 and the MRCR register bits 7 and 6 are cleared When the microcontroller exits HOLD mode the medium speed RC oscillator starts oscillation and is used as the syste
79. citors and clearing the watchdog timer WDTRST bit 1 Runaway time reset control This bit enables 1 or disables 0 the reset sequence when the watchdog timer detects a program runaway condition When this bit is set to 1 a reset is triggered when a program runaway condition is detected and the microcontroller reexecutes the program starting at the program start address selected by a user option When this bit is set to 0 no reset occurs when a program runaway is detected Instead an external interrupt INTO is generated and a call is made to vector address 0003H WDTRUN bit 0 Watchdog timer operation control This bit starts 1 or maintains 0 the state of the watchdog timer A 1 in this bit starts the watchdog timer function and a 0 exerts no influence on the operation of the watchdog timer This means that once the watchdog timer is started a program will not be able to stop the watchdog timer stopped by a reset Caution If WDTRST is set to 1 a reset is triggered when the pin P70 INTO TOLCP goes to the high level even if the watchdog timer is inactive The N channel transistor at pin P70 INTO TOLCP is turned on if the watchdog timer clear control bit WDTCLR is set to 1 when the watchdog timer is inactive WDTRUN 0 Keep this in mind when programming if the watchdog timer function is not to be used More current than usual may be consumed depending on the program or application circuit 4 22 4 5 4 2 4 5 4 3 4 5
80. clock is switched to the internal medium speed RC oscillator when a reset occurs hardware initialization is also carried out immediately even at power on time Switch the system clock to the main clock after the main clock is stabilized On reset the program counter is initialized to the program start address that is selected by a user option See Appendix A I Special Function Register Map for the initial values of the special function registers SFR lt Notes and precautions gt The stack pointer is initialized to OOOOH Data RAM is never initialized by a reset Consequently the contents of RAM are undefined at power on time When using the internal reset function it is necessary to implement and connect an external circuit to the reset pin according to the user s operating environment Be sure to review and observe the operating specifications circuit configuration precautions and considerations discussed in Section 4 6 Internal Reset Function 4 19 Watchdog Timer 4 5 Watchdog Timer Function 4 5 1 Overview This series of microcontrollers incorporates a watchdog timer that with an external RC circuit detects program runaway conditions The watchdog timer charges the external RC circuit that is connected to the P70 INTO TOLCP pin and when the level at the pin reaches the high level triggers a reset or interrupt regarding that a program runaway occurred 4 5 2 1 2 4 5 3
81. clock source Set oscillator control register CLKCB4 bit 4 to 1 and CLKCBS bit 5 to 0 to switch the system clock source to CF oscillator main Note 1 Do not switch the amplifier size of the CF oscillator when the system clock is set to CF oscillator main Switching the amplifier size in this case may cause unstable oscillation resulting in a system malfunction Note 2 The operating voltage range differs for the CF oscillator low and normal size amplifiers Refer to the latest edition of SANYO Semiconductor Data Sheet before using the low size CF oscillator amplifier 4 12 LC872R00 Chapter 4 4 3 Standby Function 4 3 1 Overview This series of microcontrollers supports two standby modes called HALT and HOLD modes that are used to reduce current consumption at power failure time or in program standby mode In a standby mode the execution of all instructions is suspended 4 3 2 Functions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing Some serial transfer functions are suspended HALT mode is entered by setting bit 0 of the PCON register to 1 Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode All oscillations are suspended The microcontroller suspends the execution of instructions and the peripheral circuits stop pro
82. contains 123H RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three closed closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains OFDFFH since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 lies outside the basic area and OFFH is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic area is 2 SFR area to FEFFH the intended address OFEFFH 2 OFF01H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit addr
83. ction control SIO1 clock output control This bit controls the output data at pin P15 When P15 is placed in output mpde PISDDR 1 and 15 is set to 1 OR of the SIOI clock output data and the port data latch is placed at pin P15 P14FCR bit 4 P14 function control SIO1 data output control This bit controls the output data at pin P14 When bit P14 is placed in output mpde P14DDR 1 and P14FCR is set to 1 OR of the SIO1 output data and the port data latch is placed at pin P14 If SIO1 is active SIO1 input data is taken in from pin P14 regardless of the I O state of P14 P13FCR bit 3 P13 function control SIO1 data output control This bit controls the output data at pin P13 When bit P13 is placed in output P13DDR 1 and P13FCR is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P13 3 7 Port 1 3 2 3 4 External interrupt 0 1 control register 101 1 Thisregister is an 8 bit register for controlling external interrupts O and 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIF INTIIE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INTILV INT1 Interrupt Conditions P17 Pin Data 0 Falling edge detected Low level detected 0 ee Du 1 o rising edge detected SSCS
84. ddress 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detected Low level detected 0 INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated Note INTO HOLD mode release is available only when level detection is set 3 4 3 3 External interrupt 2 3 control register 123CR 1 This register is an 8 bit register for controlling external interrupts 2 and 3 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 FESE 0000 0000 R W 123CR INT3LEG INT3IF I
85. der program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from three types of clocks generated by the main clock oscillator medium speed RC oscillator and variable modulation frequency RC oscillator 2 System clock frequency division Divides frequency of the oscillator clock selected as the system clock and supplies the resultant clock as the system clock The frequency divider circuit is made up of two stages The first stage allows the selection of division ratios of i and 5 l1 1 1 The second stage allows the selection of division ratios of gt gt gt d 1 2 4 8 167 32 64 and 3 Oscillator circuit control Allows the start stop control of the three systems of oscillators to be executed independently through microcontroller instructions The CF oscillator circuit may be either a low power dissipation type CF oscillation low amplifier or a CF oscillation normal amplifier 4 Multiplexed input pin function The CF oscillation pins CFland CF2 can also be used as general purpose input ports 5 Oscillator circuit states and operating modes Medium VMRC Mode Clock Main Clock speed RC Oscillator Oscillator System Clock Stopped Running Stopped Medium speed RC oscillator Resetreleased Running Running Stopped Medium speed RC oscillator Programmable Programmable Programmable Progr
86. dress data after an interrupt Read SBUFI SBUFI has been loaded with serial data from data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 7 1 no interrupt will be generated as SILRUN is cleared in that case If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device find out such condition by for example performing timeout processing using a timer module 3 39 SIO1 6 Sending data Load SBUFI with output data Clear and exit interrupt processing transfer SBUFI 8 bits stop bit H 7 Checking sent data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 7 1 no interrupt will be generated as SILRUN is cleared in that case If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device find out such condition by for example performing timeout processing using
87. e low level Starting the watchdog timer 1 Set bit 2 WDTCLR and bit 0 WDTRUN to 1 2 Also set bit 1 WDTRST to 1 at the same time when a reset is to be triggered when a runaway condition is detected 3 To suspend the operation of the watchdog timer in HOLD or HALT mode set bit 4 WDTHLT at the same time The watchdog timer starts functioning when bit 0 WDTRUN is set to 1 Once the watchdog timer starts operation the watchdog timer control register WDT is disabled for write it is allowed only to clear the watchdog timer and read the watchdog timer control register WDT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped only when a reset occurs or when the microcontroller enters HALT or HOLD mode with WDTHLT being set In this case bits WDTCLR WDTRST and WDTRUN are reset 4 23 Watchdog Timer 3 4 Clearing the watchdog timer Immediately when power is turned on charging the external RC circuit that is connected to the P70 INTO TOLCP pin is started When voltage at this pin reaches the high level a reset or interrupt is generated as specified in the watchdog timer control register WDT To run the program in the normal mode it is necessary to periodically discharge the RC circuit before the voltage at the P70 INTO TOLCP pin reaches the high level clearing the watchdog timer Execute the following instruction to clear the watchdog timer
88. e the results of computation In addition during an external memory access instruction LDX or STX the B register designates the higher order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEO1 0000 0000 R W BREG BREG7 BREG6 BREGS BREG4 BREG3 BREG2 BREGI BREGO 2 7 Register The C register is used with the ACC and B register to store the results of computation during the execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address FEO2H of the internal data memory space and initialized to 00H when a reset is performed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 5 CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation results a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FE06H of the internal data memory space and initialized to 00H when a reset 1s performed Address Init
89. ection Requirements 1 7 Recommended Unused Pin Connections Recommended Unused Pin Connections Board Software Port Name 1 8 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in the output mode Option Port Name Selected in Option Type Output Type Pull up Resistor Units of CMOS Programmable Note 1 00 to P07 1 bit N channel open drain No P10 to P17 iu CMOS Programmable i P20 P21 N channel open drain Programmable P70 es 1 N channel open drain Programmable Note 1 The control of the presence or absence of the programmable pull up resistors for port O and the switching between low and high impedance pull up connection is exercised in nibble 4 bit units P00 to 03 or P04 to 07 1 8 1 9 Option Name User Option Table Option Type Mask ROM Version 1 Flash ROM Version Option Selected in Units of LC872R00 Chapter 1 Option Selection Port output type 00 to P07 O O 1 bit CMOS N channel open drain P10 to P17 P20 to P21 1 bit CMOS N channel open drain CMOS N channel open drain Program start address 00000h 01E00h Low voltage detection reset function Detection function Detection level Enable Used Disable Not used 7 levels Power on reset function
90. ed No start bit side side Clock on falling released on edge of falling edge SHEND of SIITEND when when SHRUN 1 SIIRUN 1 2 2 With start bit Start bit on rising detected edge of when SIIRUN SIIRUN 0 when and SIIEND 0 Period 2 to 512 lt 8 to 2048 lt 2 to 512 lt 2 to 512Tcyc lt SILRUN Set Instruction lt Start bit Instruction Already set Already set Start bit Clear End of lt End of stop lt 1 lt 1 processing bit Stop condition condition detected detected 2 2 When Ack 1 arbitration detected lost Note 1 SIIEND Set End of lt End of stop lt 1 1 Falling bit 1 processing bit Rising edge edge of 8th of 9th clock clock 2 2 Stop Stop condition condition detected detected Note 1 If internal data output state and data port state L conditions are detected the rising edges of the first to 8th clocks the microcontroller recognizes a bus contention loss and clears SIIRUN and also stops the generation of the clock immediately Continued on next page 3 35 SIO1 Table 3 7 1 Synchronous Mode 0 UART Mode 1 Transfer Receive SHREC 0 SHREC 1 Transfer SI1REC 0 SHREC 1 Receive SIO1 Operations and Operating Modes cont Bus Master Mode 2 Transfer SI1REC 0 Receive SI REC 1 Bus Slave Mode 3 Transfer SI1REC 0 Receive SH REC 1 SIIOVR Set bit 2
91. ed with mode 3 to provide support for multi master operation The period of the output clock is programmable within the range of 2 to 512 Tcyc 4 Mode 3 Bus slave 5101 is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the generation of an acknowledge require program intervention SIOI can generate an interrupt by forcing the clock line to a low level on the falling edge of the eighth clock determined by the program 5 Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable flag is set 6 Itis necessary to control the following special function registers to control serial interface 1 SIO1 SCONI SBUFI SBRI PI PIDDR PIFCR Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SII REC SIIDIR SIIOVR SIIEND SITE res ww sum sec ssmcre sencis ssncoa senos 3 33 SIO1 3 7 3 3 D 2 3 7 3 4 2 Circuit Configuration 5101 control register 8 bit register This register controls the operation and interrupts of SIO1 5101 shift register SIOSF1 8 bit shift register This register is a shift register used to transfer and receive SIO1 data This register cannot be directly accessed with an in
92. enerated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer register of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock of TOL is the match signal for the prescaler When this bit is set to 1 the count clock of TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH and a match signal is generated while is running TOHRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated 3 25 la TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL and a match signal is generated while TOL is running TOLRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vec
93. equest to vector 0000 INTO Hu 2 L level Port 1 Port 7 Interrupt Block Diagram 6 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear no responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC872R00 SERIES USER S MANUAL Rev 1 00 December 27 2010 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit
94. er counter 0 TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions 1 2 3 4 3 5 2 2 Mode 0 8 bit programmable timer with a programmable prescaler with an 8 bit capture register x 2 channels Mode 1 8 bit programmable timer with a programmable prescaler with an 8 bit capture register 8 bit programmable counter with an 8 bit capture register Mode 2 16 bit programmable timer with a programmable prescaler with a 16 bit capture register Mode 3 16 bit programmable counter with a 16 bit capture register Functions Mode 0 8 bit programmable timer with a programmable prescaler with an 8 bit capture register x 2 channels Two independent 8 bit programmable timers TOL and run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P16 INT2 TOIN and P20 P21 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P17 INT1 TOHCP P15 INT3 TOIN and P20 P21 timer OH capture input pins TOL period TOLR 1 x TOPRR 1 x Tcyc period TOHR 1 x 1 x Period of cycle clock Mode 1 8 bit programmable timer with a programmable prescaler with an 8 bit capture
95. er interrupt enable control register IE 1 This register is a 6 bit register for controlling the interrupts Bits 6 to 4 are read only Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE08 0000 HH00 R W IE7 XFLG HFLG LFLG XCNTI XCNTO 7 bit 7 H L level interrupt enable disable control A 1 in this bit enables H and L level interrupt requests to be accepted e 0 in this bit disables H and L level interrupt request to be accepted e X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH interr
96. er that counts the number of external input detection signals from the P16 INT2 TOIN and P15 INT3 TOIN pins The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from the P17 INTI TOHCP P15 INT3 TOIN and P20 P21 timer OH capture input pins TO period TOHR TOLR 1 16 bits 5 Interrupt generation TOL or TOH interrupt request is generated at the counter interval for timer counter TOL or TOH if the interrupt request enable bit is set 6 Tt is necessary to manipulate the following special function registers to control timer counter 0 TOCNT TOL TOCAL TOCAH P7 ISL 0 D3CR P2 P2DDR I45CR I45SL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP FEI2 0000000 r TOL tora TOL2 XXXXXXXX TOCAL TOCAL7 16 TOCALS TOCALA TOCAL3 TOCAL2 TOCALO TOCAH6 TOCAHS rocana Tocana TOCAHO 3 5 3 Circuit Configuration 3 5 3 1 Timer counter 0 control register TOCNT 8 register 1 This register controls the operation and interrupts of TOL and TO
97. esistor select A 1 in this bit selects high impedance pull up resistors for pins P03 to POO and a 0 selects low impedance pull up resistors POFLG bit 5 PO interrupt source flag This flag is set when a low level is applied to a port 0 pin that is set up for input and the corresponding PO FE40 bit is set A HOLD mode release signal and an interrupt request to vector address 004BH are generated when this bit and the interrupt request enable bit POIE are set to 1 This bit must be cleared with an instruction as it is not cleared automatically POIE bit 4 PO interrupt request enable Setting this bit and POFLG to 1 generates a HOLD mode release signal and an interrupt request to vector address 004BH POHPU bit 3 7 04 pull up resistor control When this bit is set to 1 and POHDDR to 0 pull up resistors are connected to port 7 to P04 that are selected as CMOS output by user option 3 2 LC872R00 Chapter POLPU bit 2 PO3 POO pull up resistor control When this bit is set to 1 and POLDDR to 0 pull up resistors are connected to port bits PO3 to POO that are selected as CMOS output by user option POHDDR bit 1 7 4 1 0 control When this bit is set to 1 PO7 to P04 are placed into output mode and the contents of the corresponding port 0 data latch PO are output from the port When this bit is set to 0 PO7 to P04 are placed into input mode and POFLG is set when a low level is detected at a port whose corre
98. ess space is ignored and the contents of 0FEO1H B register are placed in the ACC as the result of computation OFEO1H 2 11 5 Direct Addressing dst Direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates the optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 8 LC872R00 Chapter 2 2 11 6 ROM Table Look up Addressing LC870000 series microcontrollers can read 2 byte data into the BA register pair at once using the LDCW instruction Three addressing modes Rn Rn and off are available for this
99. gister XT2PC Register CF1 CF2 State OCR Register FEOEH CFSTOP XTCFIN XT2IN 0 0 Main clock oscillator active CF2 pin data CFI pin data 0 Main clock oscillator stopped Undefined Undefined ep 1 Inhibited CF2 pin data CFI pin data 1 1 General purpose input 2 pin data CF1 pin data Note To use the CFI and CF2 pins as general purpose input port pins set XTCFIN XT2PC register FE43H bit 3 to 1 and CFSTOP OCR register bit 0 to 1 4 2 4 3 Low speed RC oscillator control register SLWRC 1 bit register This register is a 1 bit register that controls the amplifier size of the CF oscillator circuit Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7C HHHH HOHH R W SLWRC CFLAMP Bits 7 to 3 1 and 0 These bits do not exist They are always read as 1 CFLAMP bit 2 CF oscillator amplifier size select control 1 A 1 in this bit selects the low amplifier size for the CF oscillator circuit 2 0 in this bit selects the normal amplifier size for the CF oscillator circuit See Subsection 4 2 5 as a predefined procedure is required to switch the selection 4 9 System Clock 4 2 4 4 CF1 CF2 general purpose port input control register XT2PC 1 bit register 1 This register is a 1 bit register that controls the general purpose input at the CF land CF2 pins Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO
100. gister high byte ADRHC the contents of the AD conversion result register low byte ADRLC remain unchanged If this bit is set to 0 the AD converter serves as a 12 bit AD converter The conversion results are placed in the AD conversion result register high byte ADRHC and the higher order 4 bits of the AD conversion result register low byte ADRLC ADMD2 bit 5 Fixed bit This bit must always be set to 0 ADMD 1 bit 4 Fixed bit This bit must always be set to 0 ADMDO bit 3 Fixed bit This bit must always be set to 0 ADMR2 bit 2 Fixed bit This bit must always be set to 0 ADTM1 bit 1 bit 0 These bits and ADTM2 bit 0 of the AD conversion result register low byte ADRLC define the conversion time AD conversion time control ADRLC ADMRC Register AD Frequency Register Division Ratio 3 47 12 Conversion time calculation formulas 12 bit AD conversion mode Conversion time 52 AD division ratio 2 x 1 3 x 8 bit AD conversion mode Conversion time 32 AD division ratio 2 x 1 3 x Tcyc Notes The conversion time is doubled in the following cases 1 The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset 2 The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by
101. he diagram of the internal reset circuit is provided in Figure 4 6 1 Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals It is used to stretch the internal reset period and discharge the external capacitor Cres connected to the reset pin The stretching time lasts from 30 us to 100 us Capacitor Cres discharging transistor This is an N channel transistor used to discharge the external capacitor Crgs connected to the reset pin If the capacitor Cres is not to be connected to the reset pin it is possible to monitor the internal reset signal by connecting only the external pull up resistor Rags Option selector circuit The option selector circuit is used to configure the LVD options This circuit selects whether to Enable use or Disable non use the LVD and its detection levels See Subsection 4 6 4 External capacitor Cres Pull up resistor Rges After the reset signal from the internal reset circuit is released the reset period is further stretched according to the external CR time constant This enables the microcontroller to avoid repetitive entries and releases of the reset state from occurring when power on chatter occurs The circuit configuration shown in Figure 4 6 1 in which the capacitor Crrs and pull up resistor are externally connected is recommended when both POR and LVD functions are to be used The recommended constant values are Cres 0 022 uF and Rres 51
102. ial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE06 0000 0000 R W PSW CY AC PSWBS PSWB4 LDCBNK OV CY bit 7 Carry CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are following four types of carries 1 Carry resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the higher order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table look up instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table look up instruction 0 ROM ADR 0 to 1FFFF 1 ROM ADR 20000 to 3FFFF OV bit 2 Overflow flag OV is set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negati
103. itching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the respective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC Value BNK Value Reset Note 00000H 0 01E00H INTO 00003H INTI 0000BH INT2 TOL INT4 00013H o INT3 0001BH I o O 00023H EU 0002BH 00033H 0003BH 00043H 0004BH Unconditional branch PC a17 PC PC 2 r12 2048 to 2047 BE BNE DBNZ DBZ BZ BNZ PC PC nb r8 128 to 127 instructions BZW BNZW BP BN BPC nb Number of instruction bytes Call instructions 17 PC PC 2 112 2048 to 2047 PC PC 1 Areg 0 to 255 Return instructions RET RETI PC16 to 08 SP BNK is set to PCO07 to 00 SP 1 bit 8 of SP denotes the contents of RAM SP 1 address designated by the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes Note The reset time program start address can be selected through a user option in the flash version of the microcontroller In the mask version the program start address is fixed at address 00000H 2 3 Program Memory ROM This series of microcontrollers has
104. l is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P17 Port 1 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select NFSEL NFON Noise Filter Time Constant 1 Tcyc 128 Tcyc 0 0 4 9 STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 Note If timer OL capture signal input or timer OH capture signal input for INT4 is assigned to P70 and P17 to P15 at the same time the signal from port 7 and
105. l reset The internal reset function 1s available in two types the power on reset POR that triggers a reset when power is turned on and the low voltage detection reset LVD that triggers a reset when the power voltage falls below a certain level Options are available to set the power on reset resetting level to enable and disable the low voltage detection reset function and its threshold level 3 Runaway detection reset function using a watchdog timer The watchdog timer of this series of microcontrollers can be used to detect and reset runaway conditions by connecting a resistor and a capacitor to its external interrupt pin P70 INTO TOLCP and making an appropriate time constant element An example of a reset circuit is shown in Figure 4 4 1 The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power on reset circuit 1s configured Exterior of Interior of microcontroller microcontroller P70 INTO TOLCP Watchdog E Do E Internal reset circuit POR LVD Sync circuit Internal reset signal Figure 4 4 1 Sample Reset Circuit Block Diagram 4 18 LC872R00 Chapter 4 4 4 3 Reset State When a reset is generated by the RES pin internal reset circuit or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system
106. lected through the 0 1 value of TOLONG timer 0 control register bit 5 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data needs to match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the lower order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOLRUN O the match register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Timer counter 0 match data register high byte 8 bit register with a match buffer register This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the higher order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOHRUN O the match register matches TOHR e When it is active
107. ling edge of the 8th clock after which an interrupt occurs The clock counter will be cleared if a start condition is detected in the middle of receive processing In such a case another 8 clocks are required to generate an interrupt Read SBUFI and store the read data Note Bit 8 of SBUFI is not yet updated because the rising edge of 9th clock has not yet occurred Return to in step 6 to continue receive processing 7 Sending data Clear SIIREC Load SBUFI with output data Clear SIIEND and exit interrupt processing Send an acknowledge for the preceding reception operation and release the clock port after the lapse of SBR1 value 1 x Tcyc Perform a send operation 8 bits and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs 2 Go to 3 in step 7 if SIIRUN is set to 1 If SIIRUN is set to 0 implying an interrupt from 4 in step 7 clear SILEND and SILOVR and return to 1 in step 4 3 41 3 Read SBUFI and check send data as required Note 8 of SBUFI is not yet updated because the rising edge of 9th clock has not yet occurred Load SBUFI with the next output data Clear SIIEND and exit interrupt processing Release the clock port after the lapse of SBRI value 1 x Teyc Return to 1 in step7 if an acknowledge from the master is present L If there is no acknowledge presented from the master SIO1 recognizing
108. lock 4 Clock generator circuit SIO1 output control A MSB LSB first control pie por latch Baudrate P15 output control generator Serial transfer end flag SBR1 FE36h Overrun flag bit1 bitO 1 Interrupt request Figure 3 7 1 5101 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1 0 511 0 0 bit7 bit6 bit5 SCON1 FE34h bit4 bit3 bit 3 36 LC872R00 Chapter Start bit additional circuit Shift input Shift input Start stop bit additional circuit At time operation starts LSB MSB first select 8 bit shift register SIOSF1 Shift clock transfer ends Stop bit data input SIO1 output control gt gt m P13 P13 port latch P13 output control SBUF1 FE35h Stop bit input clock Clock generator circuit Baudrate Set SHEND when generator stop bit data ends SBR1 FE36h SIO1 output control P14 port latch gt gt da P14 output control Overrun flag SCON1 FE34h Interrupt request Figure 3 7 2 5101 Mode 1 Asynchronous Serial UART Block Diagram SI1M1 0 SI1M0 1 3 37 SIO1 3 7 4 5101 Communication Examples 3 7 4 1 Synchronous serial communication mode 0 1 Setting the clock Setup SBRI when using an internal clock 2 Setting the mode e Set as follows SIIMO 0 SIIMI 0 SIIDIR SITE 1 3 Setting up the ports and SII R
109. lock control T7CO bit 6 T7 count clock control T7CO T7 Count Clock Timer 7 prescaler and timer counter are stopped in the reset state 0 0 1 a0 T6C1 bit 5 T6 count clock control T6CO bit 4 T6 count clock control T6C1 T6CO T6 Count Clock Timer 6 prescaler and timer counter are stopped in the reset state 0 0 T7OV bit 3 7 overflow flag This flag is set at the interval of timer 7 period when timer 7 is running This flag must be cleared with an instruction T7IE bit 2 T7 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T7OV are set to 1 T6OV bit 1 T6 overflow flag This flag is set at the interval of timer 6 period when timer 6 is running This flag must be cleared with an instruction T6IE bit 0 T6 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T6OV are set to 1 3 6 4 2 Timer 6 period setting register T6R 1 This register is an 8 bit register for defining the period of timer 6 Timer 6 period T6R value 1 x Timer 6 prescaler value 4 16 or 64 Tcyc 2 When data is written into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7A 0000 0000 R W T6R T6R7 T6R6 T6R5 T6R4 T6R3 T6
110. m clock source 2 is cleared when a HOLD mode release signal INTO 2 INT4 or POINT 15 generated or a reset occurs 3 Bit 0 is automatically set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into HALT mode 2 This bit is automatically set when bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal Operating mode Normal mode HALT mode 4 14 LC872R00 Chapter 4 Table 4 3 1 Standby Mode Operations Reset State HALT Mode HOLD Mode Entry conditions RES signal applied PCON register PCON register Reset from watchdog Bit 1 0 Bit 1 1 ud Bit 0 1 Reset generated by the internal reset circuit Data changed on Initialized as shown in WDT bits 2 to 0 are WDT bits 2 to 0 are entry separate table cleared if WDT register cleared if WDT register FEOF bit 4 is set bit is set PCON bit 0 turns to 1 OCR register FEOE bits 5 4 and 1 are cleared MRCR register FEOD bits 7 and 6 are cleared Main clock Stopped State established at entry Stopped Internal Running State established at entry Stopped medium speed RC time oscillation Variable Stopped State established at entry Stopped modulation time frequency RC oscillation CPU Initialized Stopped Stopped See Table 4 3 2 RAM RES Undefined
111. mple 2 Selecting the optimum LVD reset level that meets the guaranteed operating conditions to VDD 2 250 ns Set the LVD reset function option to Enable and select 2 81V as the LVD reset level Microcontroller guaranteed operating range VDD 2 7V to 5 5V Tcyc 250ns LVD release voltage LVDET LVHYS Suey a a yore oe ls LVD reset voltage LVDET Typ 2 81V Operation guarantee voltage lower limit VDD 2 7V Tcyc 250ns e Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3 0V see also paragraph 1 of Subsection 4 6 7 Set the LVD reset function option to Disable and select 1 67V as the POR release level Set operating range VDD 3 1V External 3 0V detection circuit POR release voltage PORRL Typ 1 67V Note 5 The operation guarantee values voltage operating frequency shown in the examples vary with the microcontroller type Be sure to see the latest SANYO Semiconductor Data Sheet and select the appropriate voltage level 4 28 LC872R00 Chapter 4 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 1 Waveform observed when only POR is used LVD not used Reset pin Pull up resistor Regs only POR release voltage PORRL i i E E MER O a eee A Ee E ay m ID cde 0 1 Reset period I 100 8 longer
112. nd an interrupt request to vector address 0013H are generated The interrupt flag however can be set neither by a rising edge occurring when P16 data which is established when HOLD mode is entered is in the high state nor by a falling edge occurring when P16 data which is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 3 6 Input signal select register ISL 1 This register is a 5 bit register for controlling the timer 0 input and noise filter time constant Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 00HH H000 R W ISL STOHCP STOLCP NFSEL NFON STOIN STOHCP bit 7 Timer OH capture signal input port select This bit selects the timer OH capture signal input port When set to 1 a timer OH capture signal is generated when an input that satisfies the INT1 interrupt detection conditions is supplied to P17 If the INTI interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P17 When this bit is set to 0 a timer OH capture signa
113. nsmission reception at the beginning of transfer processing and the contents of the shift register are placed in the lower order 8 bits of SBUFI when 8 bit data is transferred In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data bit that is received data about the position of the stop bit Address Initial Value R W Name BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE35 3 7 5 3 1 2 3 00000 0000 R W SBUFI SBUF18 SBUF17 SBUF16 SBUFI5 SBUF14 SBUFI3 SBUF12 SBUF11 SBUFIO Baudrate generator register SBR1 This register is an 8 bit register that defines the transfer rate of SIO1 Loading this register with data causes the baudrate generating counter to be initialized immediately The transfer rate depends on the transfer mode the baudrate generator is disabled in mode 3 Modes 0 and 2 TSBRI SBRI value 1 x 2 Value range 2 to 512 Tcyc Mode 1 TSBRI z SBRI value 1 x 8Tcyc Value range 8 to 2048Tcyc Address Initial Value R W Name BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRG17 SBRG16 SBRGI5 SBRGIA SBRG13 SBRG12 SBRG11 SBRGIO 3 43 ADC12 3 8 AD Converter ADC12 3 8 1 Overview This series of microcontrollers incorporates a 12 bit resolution AD converter that has the features listed below It allows the microcontroller to take in analog signals easily 1 12 bit resolution 2 Successive appr
114. ntrolled by bit 3 of register XT2PC FE43H Oscillation enable disable controlled by register OCR Feedback resistor between CF1 and CF2 controlled by a program Input output pull up resistor controlled by a program CF oscillation inverter input general purpose input in setting established at entry time Feedback resistor between CF1 and CF2 is in the state established when HOLD mode is entered CF oscillation inverter output general purpose input is in the state established when HOLD mode is entered Feedback resistor between CF1 and CF2 is in the state established when HOLD mode is entered State established when HOLD mode is entered State established when HOLD mode is entered P00 P07 P10 P17 P20 P21 Input mode Pull up resistor off Input mode Pull up resistor off Input mode Pull up resistor off Input output pull up resistor controlled by a program Input output pull up resistor controlled by a program Input output pull up resistor controlled by a program N channel output transistor for watchdog timer controlled by a program since on time is automatically extended it takes 1920 to 2048 Tcyc for the transistor to go off Input mode Pull up resistor off N channel output transistor for watchdog timer is off automatic on time extension function is reset 4 16 Same as in normal mode
115. ntroller operating modes Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH 00 R W PCON E PDN IDLE Bits 7 to 2 These bits do not exist They are always read as 1 PDN bit 1 HOLD mode setting flag 1 This bit must be set with an instruction When the microcontroller enters HOLD mode all oscillations main clock medium speed RC and variable modulation frequency RC are suspended and the OCR register bits 1 4 and 5 and the MRCR register bits 7 and 6 are cleared When the microcontroller exits HOLD mode the medium speed RC oscillator starts oscillation and is used a system clock source 2 is cleared when a HOLD mode releasing signal INTO INT2 INT4 or POINT is generated or a reset occurs 3 Bit 0 is automatically set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into HALT mode 2 This bit is automatically set when bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal PDN IDLE Operating mode 0 Normal mode 0 4 2 4 2 Oscillation control register OCR 7 bit register 1 This register is a 7 bit register that controls the operation of the oscillator circuits selects the system clock and reads data from the CF1 and CF2 pins Bits 3 and 2 are read only Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BI
116. o the internal resistor and capacitor 2 The circuit counts the clocks with a source oscillation frequency of 16 MHz with a 5 bit counter The maximum allowable clock rate is 8 MHz 3 The circuit toggles the clock output each time the counter value matches the preset count value 4 The variable modulation frequency RC oscillator circuit is suited to generate a main clock which does not require the precision in frequency that the external CF oscillator would provide 4 6 4 2 3 4 1 4 2 3 5 1 2 3 4 4 2 3 6 1 4 2 3 7 1 4 2 3 8 1 2 3 4 2 3 9 1 CFLAMP S oscillator CF clock LC872R00 Chapter 4 Power control register PCON 2 bit register This register specifies the operating mode normal HALT HOLD Oscillation control register OCR 7 bit register This register controls the start stop operation of the oscillator circuits This register selects the system clock This register sets the division ratio of the oscillation clock to be used as the system clock to 5 The state of the CF1 and CF2 pins can be read as bits 2 and 3 of this register Low speed RC oscillation control register SLWRC 1 bit This register selects the amplifier size of the CF oscillator circuit The CF oscillator low amplification is effective for reducing power dissipation under such conditions as low voltage CF 4 MHz system frequency division ratio 1 4 to 1 16 CF1 and CF2 general purpose port
117. of the port data latch A in this bit outputs the OR of the value of the port data latch and the waveform which toggles at the interval equal to the period of timer 6 LC872R00 Chapter 3 7 Serial Interface 1 5101 3 7 1 Overview The serial interface 1 SIO1 incorporated in this series of microcontrollers provides the following four functions 1 Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system transfer clock of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial half duplex 8 data bits 1 stop bit 8 to 2048 Tcyc baudrate 3 Mode 2 Bus master start bit 8 data bits transfer clock of 2 to 512 Tcyc 4 Mode 3 Bus slave start detection 8 data bits stop detection 3 7 2 Functions 1 Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The frequency of the internal clock is programmable within the range of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop bit asynchronous serial communication The baudrate is programmable within the range of 8 to 2048 Tcyc 3 Mode 2 Bus master e 5101 is used as a bus master controller The start conditions are automatically generated but stop conditions must be generated by manipulating ports Clock synchronization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combin
118. on control circuit runs in two modes 12 and 8 bit AD conversion modes 3 8 8 2 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a circuit that controls the reference voltage generator circuit and the conversion results AD conversion end flag ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time control register The conversion results are placed in the AD conversion result registers ADRHC ADRLC 3 8 33 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 8 channels of analog signals 3 8 3 4 Automatic reference voltage generator circuit 1 The reference voltage generator circuit consists of a network of ladder resistors a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage is automatically started when an AD conversion starts and stopped when the conversion ends The reference voltage output ranges from VDD to VSS 3 8 4 Related Registers 3 8 4 1 AD control register ADCRC 1 This register is an 8 bit register that controls the operation of the AD converter Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO AD AD AD AD AD AD BES 0900 9000 RN Oe C
119. on of the functional block 4 21 Watchdog Timer WDTHLT bit 4 HALT HOLD mode function conirol This bit enables 0 or disables 1 the watchdog timer when the microcontroller is in HALT or HOLD state When this bit is set to 1 WOTCLR WDTRST and WDTRUN are reset and the watchdog timer is stopped in HALT or HOLD state When this bit is set to 0 WOTCLR WDTRST and WDTRUN remain unchanged and the watchdog timer continues operation even when the microcontroller enters HALT or HOLD state To use the watchdog timer function after the microcontroller returns to the normal operating mode from HALT or HOLD mode with this bit set to 1 initialize and set up the watchdog timer again for starting the watchdog timer function WDTCLR bit 2 Watchdog timer clear control This bit enables 1 or disables 0 the discharge of capacitance from the external capacitor when the watchdog timer is running WDTRUN 1 Setting this bit to 1 turns on the N channel transistor at pin P70 INTO TOLCP when the watchdog timer clear instruction is executed discharging the external capacitors and clearing the watchdog timer The pulse stretcher circuit also functions during this process Setting the bit to 0 disables turning on the N channel transistor at pin P70 INTO TOLCP and clearing of the watchdog timer If this bit is set to 1 when the watchdog timer is inactive WDTRUN 0 the N channel transistor at pin P70 INTO TOLCP is turned on discharging the external capa
120. or treatment of the on chip debugger pins refer to the separately available manuals entitled RD87 On chip Debugger Installation Guide and LC872000 Series On chip Debugger Pin Connection Requirements 3 2 2 Functions 1 Input output port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch P1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FEA5 Each port is provided with a programmable pull up resistor 2 Interrupt input pin function e P17 is assigned to and used to detect a low or high level or a low or high edge and set the interrupt flag e P16 and P15 are assigned to INT2 INT3 respectively and used to detect a low edge high edge or both edges and set the interrupt flag 3 Timer 0 count input function A count signal is sent to timer 0 each time a signal change that sets the interrupt flag is supplied to the port selected from P16 and P15 4 Timer OL capture input function A timer OL capture signal is generated each time a signal change that sets the interrupt flag is supplied to the port selected from P70 and P16 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle interval for the duration of the input signal 5 Timer OH capture input function A timer OH capture signal is generated each time a signal change that sets the interrupt
121. oximation 3 AD conversion mode select resolution switching 4 8 channel analog input 5 Conversion time select 3 8 2 Functions 1 Successive approximation The ADC has a resolution of 12 bits It requires some conversion time after starting conversion processing The conversion results are placed in the AD conversion result registers ADRLC ADRHC 2 conversion mode select resolution switching The AD converter supports two AD conversion modes 12 and 8 bit conversion modes so that the appropriate conversion resolution can be selected according to the operating conditions of the application Conversion mode switching is accomplished through the AD mode register ADMRC 3 8 channel analog input The signal to be converted is selected using the AD control register ADCRC from 8 types of analog signals that are supplied from P00 to P06 and P70 pins 4 Conversion time select The AD conversion time can be set to 1 1 to 1 128 frequency division ratio The AD mode register ADMRC and AD conversion result low byte register ADRLC are used to select the conversion time for appropriate AD conversion 5 Itis necessary to manipulate the following special function registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Address Initial value His 0000 0000 CHSEL3 CHSEL2 CHSEL1 3 44 LC872R00 Chapter 3 3 8 3 Circuit Configuration 3 8 3 1 AD conversion control circuit 1 The AD conversi
122. port I are ignored 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port retains the state that is established when HALT or HOLD mode is entered LC872R00 Chapter 3 3 Port2 3 3 1 Overview Port 2 is a 2 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished by the data direction register in 1 bit units Port 2 can also serve as an input port for external interrupts It can also be used as an input port for the timer 0 capture signal input or HOLD mode release signal input As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 3 2 Functions 1 Input output port 2 bits P20 and P21 The port 2 data latch P2 FE48 is used to control port output data and the port 2 data direction register P2DDR FE49 to control the I O direction of port data Each port is provided with a programmable pull up resistor 2 Interrupt input pin function The port INT4 selected out of P20 and P21 is provided with a pin interrupt function This function detects a low edge
123. r other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter OverviQeW cisco 1 1 1 4 Overview 1 1 1 2 Features 1 1 1 3 Pinout na 1 5 1 4 System Block Diagram 1 6 1 5 Pin Functions AA 1 7 1 6 On chip Debugger Pin Connection Requirements 1 8
124. r starting the operation 4 25 Internal Reset 4 6 4 6 1 This nternal Reset Function Overview series of microcontrollers incorporates internal reset functions called the power on reset POR and low voltage detection reset LVD The use of these functions contribute to a reduction in the number of externally required reset circuit components reset IC etc 4 6 2 1 2 4 6 3 Functions Power on reset POR function POR is a hardware feature that generates a reset to the microcontroller when the power is turned on This function allows the user to select the POR release level by option only when Disable of the low voltage detection reset function is selected It is necessary to use the below mentioned low voltage detection reset function together with this function or to configure an external reset circuit if chatter or a temporary power interruption may occur when the power is turned on Low voltage detection reset LVD function This function when used together with the POR function can generate a reset when power is turned on and when the power level lowers As a user option Enable use or Disable non use and the detection levels of this function can be specified Circuit Configuration The internal reset circuit consists of the POR LVD pulse stretcher circuit capacitor Cres discharging transistor external capacitor Cars pull up resistor Regs or pull up resistor alone T
125. register 8 bit programmable counter with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signals from the P16 INT2 TOIN and P15 INT3 TOIN pins TOH serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P16 INT2 TOIN and P20 P21 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P17 INTI TOHCP P15 INT3 TOIN and P20 P21 timer OH capture input pins TOL period TOLR 1 TOH period TOHR 1 x TOPRR 1 x Tcyc 3 Mode 2 16 bit programmable timer with a programmable prescaler with a 16 bit capture register Timer counter serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and are captured into the capture registers TOCAL TOCAH at the same time on external input detection signals from the P17 INT1 TOHCP P15 INT3 TOIN and P20 P21 timer OH capture input pins TO period TOHR TOLR 1 x TOPRR 1 x 16 bits 4 Mode 3 16 bit programmable counter with a 16 bit capture register Timer counter 0 serves as a 16 bit programmable count
126. rned on even if the internal reset circuit is not used For this reason when connecting an external reset IC adopt a reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level 1 67V that does not affect the minimum guaranteed operating voltage The figures provided below show sample reset circuit configurations that use reset ICs of N channel open drain and CMOS types respectively Reset IC Microcontroller Several hundred N channel open drain type RESET From POR Figure 4 6 6 Sample Reset Circuit Configuration Using an N channel Open Drain Type Reset IC Insert a protective resistor of several to dozens of kQ to prevent through current Reset IC Microcontroller CMOS type RESET From POR Figure 4 6 7 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4 32 LC872R00 Chapter 4 2 When configuring the external POR circuit without using the internal reset circuit The internal POR is active when power is turned on even if the internal reset circuit is not used as in case 1 in Subsection 4 6 7 When configuring an external POR circuit with a Cres value of 0 1uF or larger to obtain a longer reset period than with the internal POR however be sure to connect an external diode Dres as shown in Figure 4 6 8 Microcontroller RESET Cres
127. s set to 0 it indicates that no AD conversion operation is in progress This flag must be cleared with an instruction ADIE bit 0 AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes e inhibited to set ADCHSEL3 to ADCHSELO to any value from 1001 to 1111 and 0111 e Do not place the microcontroller in HOLD mode with ADSTART set to 1 Make sure that ADSTART is set to 0 before putting the microcontroller in HOLD mode Never execute any instructions other than the read branch and compare on the ADCRC register FES8h while conversion processing is in progress However this does not hold true when conversion processing is to be stopped 3 46 LC872R00 Chapter 3 8 4 2 AD mode register ADMRC 1 This register is an 8 bit register that controls AD converter operation mode Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FES9 0000 0000 R W ADMRC ADMD4 ADMD3 ADMD2 ADMD1 ADMDO ADMR2 ADTMI ADTMO ADMDMA bit 7 Fixed bit This bit must always be set to 0 bit 6 AD conversion mode control resolution select This bit selects the AD converter resolution between 12 bit AD conversion mode 0 and 8 bit AD conversion mode 1 If this bit is set to 1 the AD converter serves as an 8 bit AD converter The conversion results are placed only in the AD conversion result re
128. s support the following seven addressing modes 1 2 3 4 5 7 Immediate immediate data refers to data whose value has been established at program preparation assembly time Indirect register Rn indirect 0 lt n lt 63 Indirect register Rn C register indirect 0 lt lt 63 Indirect register RO Offset value indirect Direct ROM table look up External data memory access The rest of this section describes these addressing modes 2 11 1 Immediate Addressing The immediate addressing mode allows 8 bit 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD 12H Loads the accumulator with byte data 12H LDW 1234 Loads the BA register pair with word data 1234H PUSH 349 Loads the stack with byte data 34H ADD 56H Adds byte data 56H to the accumulator BE 78H L1 Compares byte data 78H with the accumulator for a branch 2 6 LC872R00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected register contains for example FE02H it designates the C register Example When R3 contains 123H RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator STW
129. set In this case HOLD mode is released if the corresponding interrupt enable flag is set Multiplexed pin function P70 is also used as the ANS analog input pin 3 14 LC872R00 Chapter HOLD Mode Release Interrupt Input Capture Signal Detection Input Input Output With a N channel open drain L level H level Timer OL Enabled programmable L edge H edge Note pull up resistor Note P70 HOLD mode release is available only when level detection is set Initial value R W Name BIT7 BIT6 BIT4 BIT1 HHHO HHHO P7 P70DDR FESD 00000000 rw INTILH 123CR INT3HEG ISL sroucP srorce NFSEL NFON 3 4 3 Related Registers 3 4 3 1 Port 7 control register P7 1 This register is a 2 bit register for controlling the I O of port 7 data and pull up resistors 2 When this register is read with an instruction data at pin P70 is read into bit 0 Bit 4 is loaded with bit 4 of register P7 If P7 5 is manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced as bit 0 instead of the data at port pins 3 Port 7 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FESC HHHO HHHO R W P7 P70DDR P70DT Register Data Port P70 State P70DDR Internal Pull up Resistor Enabled Open
130. sponding port 0 data latch PO bit is set to 1 POLDDR bit 0 PO3 POO I O control When this bit is set to 1 PO3 to POO are placed into output mode and the contents of the corresponding port 0 data latch PO are output from the port When this bit is set to 0 to POO are placed into input mode and POFLG is set when a low level is detected at a port whose corresponding port 0 data latch PO bit is set to 1 P07 P04 pull up resistor selection settings POHPUS POHPU Port for Which POHDDR 0 and CMOS Option is Specified Pull up resistor OFF EDEN oo 1 Low impedance pull up resistor ON High impedance pull up resistor ON 3 pull up resistor selection settings _ POLPU Port for Which POLDDR 0 and CMOS Option is Specified 0 Pull up resistor OFF EE i ae Pull up resistor OFF IE E di Low impedance pull up resistor ON High impedance pull up resistor ON 3 1 3 3 Port 0 function control register POFCR 1 Thisregister is a 2 bit register that controls the port 0 multiplexed output pin rec Porcr T7OE bit 7 This bit controls the output data at pin 7 It is disabled when 07 is in input mode When P07 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 7 and the value of the port data latch T6OE
131. struction It is accessed via SBUF1 SIO1 data register SBUF1 9 bit register The lower order 8 bits of SBUF1 are transferred to SIOSFI at the beginning of data transfer At the end of data transfer the contents of SIOSFI are placed in the lower order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUFI it is possible to check for a stop bit 5101 baudrate generator register SBR1 8 bit reload counter This is a reload counter for generating internal clocks The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 34 LC872R00 Chapter Table 3 7 1 5101 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transfer Receive Transfer Receive Transfer Receive Transfer Receive SI1REC 0 11 1 SI1REC 0 SI1REC 1 SMREC 0 SI1TREC 1 SMREC 0 SHREC 1 None None Output Input See 1 and Not required Not required See 2 below Low Low 2 below Data output 8 8 8 8 8 8 8 8 Shift data 1s Shift data 1s Shift data 1s Shift data 1s lt 8 Data input 8 8 lt lt 8 lt Input pin Input pin Input pin Input pin Stop bit None lt Output Input Input Output Input High H L H L SBUFI bit8 H L Clock 9 lt lt Low output Internal on falling edge of 8th clock Operation start SILRUN T Start bit 1 1 on left 1 on right detect
132. system reset and when the AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula is taken in the second and subsequent conversions 5 Testing AD conversion end flag Monitor ADENDF bit 1 of the AD control register ADCRC until it is set to 1 e Clear AD conversion end flag ADENDF to 0 after confirming that the ADENDF flag bit 1 is set to 1 6 Reading in the AD conversion results Read the AD conversion result high byte register ADRHC and AD conversion result register low byte ADRLC Since the conversion result data contains some errors quantization error combination error use only the valid part of the conversion data selected according to the specifications given in the latest SANYO Semiconductor Data Sheet Pass the above read data to the application software processing Return to step 4 to repeat the conversion processing 3 49 12 3 8 6 2 3 4 5 6 7 8 9 10 Hints on the Use of the ADC The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest SANYO Semiconductors Data Sheet to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion function Do not place the microcontroller in HOLD mode while A
133. t and hold the voltage level of the reset pin at the low level until the release voltage exceeds the minimum guaranteed operating voltage When POR release level is 1 67V Min guaranteed operating voltage Reset VIH level Undefined region Figure 4 6 3 Sample Release Level Waveform in Internal POR Only Configuration 4 30 3 LC872R00 Chapter 4 When temporary power interruption or voltage fluctuations shorter than several hundred us are anticipated The response time measured from the time the LVD senses a power voltage drop at the option selected level until it generates a reset signal is defined as the minimum low voltage detection width TLVDW shown in Figure 4 6 4 see SANYO Semiconductor Data Sheet If temporary power interruption or power voltage fluctuations shorter than this minimum low voltage detection width are anticipated be sure to take the preventive measures shown in Figure 4 6 5 other necessary measures LVD release voltage LVD reset voltage mal LVDET Microcontroller Figure 4 6 5 Example of Power Interruption Voltage Fluctuation Countermeasures 4 31 Internal Reset 4 6 7 1 Notes to be Taken When Not Using the Internal Reset Circuit When configuring an external reset IC without using the internal reset circuit The internal POR function is activated and the capacitor CRES discharging N channel transistor connected to the reset pin turns on when power is tu
134. t board e There are two channels of on chip debugger pins to support small pin count devices DBGP1 P1 Data security function flash ROM version e Protects the program data stored in flash memory from unauthorized read or copy Note This data security function does not necessarily provide absolute data security Package form e 245 300 mil lead free and halogen free product 55 24 225 mil lead free and halogen free product Development tools On chip debugger TCB87 B LC87F2R04A Programming board TCB87 Type C 3 wire configuration LC87F2R04A Package Programming Board 245 W87F2GM SSOP24 W87F2GS 1 4 LC872R00 Chapter 1 1 3 Pinout P7O INTO TOLCP AN8 1 24 P07 T70 DBGP02 RES 2 23 P06 AN6 T6O DBGP01 881 22 P05 AN5 DBGP00 CF1 L 4 21 P04 AN4 2 5 20 6 TOP VIEW 19 PO2 AN2 P10 17 18 PO1 AN1 8 17 POO ANO 12 16 P21 INT4 P13 SO1 DBGP12 10 15 20 4 P14 SH SB1 DBGP11 11 14 1 P17 INT1 TOHCP P15 SCK1 INT3 TOIN DBGP10 12 13 P16 INT2 TOIN SANYO MFP24S SSOP24 lead free and halogen free product 1 5 1 4 System Block Diagram
135. t can generate at pin P07 toggle waveforms whose frequency is equal to the period of timer 7 T7 period T7R 1 x 4 Teyc n 1 2 3 Tcyc Period of cycle clock 3 Interrupt generation An interrupt request to vector address 0043H is generated when the overflow flag is set at the interval of timer 6 or timer 7 period and the corresponding interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control the timer 6 T6 and timer 7 T7 T67CNT T6R T7R PODDR POFCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 R W T67CNT 7 0 T6CO T7OV T7IE T6OV T6IE re RW TE 3 6 3 Circuit Configuration 3 6 3 1 Timer 6 7 control register T67CNT 8 bit register 1 Thisregister controls the operation and interrupts of T6 and T7 3 6 3 2 Timer 6 counter T6CTR 8 bit counter 1 This counter counts the number of clocks from the timer 6 prescaler T6PR The value of timer 6 counter T6CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 6 period setting register when the interrupt flag T6OV is set 2 When 6 and T67CNT FE78 bits 4 and 5 are set to 0 the timer 6 counter stops at a count value of 0 In the other cases the timer 6 counter continues operation
136. tch data register low byte 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the lower order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode 2 The match buffer register is updated as follows When it is inactive TOLRUN O the match register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Address Initial Value RAW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLR1 TOLRO 3 26 1872800 Chapter 3 5 4 6 Timer counter 0 match data register high byte 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the higher order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode 2 The match buffer register is updated as follows When it is inactive TOHRUN 0 the match register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded with the contents TOHR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7
137. tents Chapter 4 Control Functions erre 4 1 4 1 Interrupt Function 4 1 4 1 1 Overview o 4 1 4 1 2 Functions A 4 1 4 1 3 Circuit Configuration A 4 2 4 1 4 Related Registers A 4 3 42 System Clock Generator Function 4 5 42 1 4 5 4 2 2 Functions A 4 5 4 2 3 Circuit Configuration 4 6 4 2 4 Related Registers 4 8 4 2 5 Example of Switching the CF Oscillator Amplifier Size 4 12 4 3 Standby Function 4 1 4 3 1 Overview A 4 1 3 4 3 2 Functions 4 1 4 3 3 Related Registers a 4 14 4 4 Reset Function 4 1 8 441 Overview AA 4 1 8 4 4 2 Functions a 4 1 8 4 4 3 Reset State o na 4 1 9 4 5 Watchdog Timer Function 4 20 4 5 1 Overview o a 4 20 45 2 Functions a 4 20
138. ternal interrupts 2 and 3 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W 123CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE LC872R00 Chapter INT3HEG bit 7 INT3 rising edge detection control INT3LEG bit 6 INT3 falling edge detection control INT3HEG INT3LEG INT3 Interrupt Conditions P15 Pin Data No edge detected Falling edge detected 0 0 po 1 tp 0 Rising edgedetected O INTSIF bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit must be cleared with an instruction as it is not cleared automatically INTSIE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P16 Pin Data No edge detected Falling edge detected 0 0 as 1 Rising ease deca INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal a
139. th when power is turned on and when the power level lowers The reset release voltage and entry voltage in this case may have some range Refer to the latest SANYO Semiconductor Data Sheet for details A hysteresis width LVHYS is provided to prevent repetitions of reset release and entry cycles near the detection level 4 29 Internal Reset 4 6 6 Notes on the Use of the Internal Reset Circuit 1 When generating resets only with the internal POR function When generating resets using only the internal POR function do not short the reset pin directly to VDD as when using it with the LVD function Be sure to use an external capacitor Cres of an appropriate capacitance and a pull up resistor Regs the pull up resistor alone Test the circuit extensively under the anticipated power supply conditions to verify that resets are reliably generated Microcontroller RRES RESET From POR Figure 4 6 2 Reset Circuit Configuration Using Only the Internal POR Function 2 When selecting a release voltage level of 1 67V only with the internal POR function When selecting an internal POR release level of 1 67V connect the external capacitor and pull up resistor of the values that match the power supply rise time to the reset pin and make necessary adjustments so that the reset state is released after the release voltage exceeds the minimum guaranteed operating voltage Alternatively se
140. the above formula is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode 3 8 4 3 conversion result register low byte ADRLC 1 This register is used to hold the lower order 4 bits of the results of an AD conversion carried out in the 12 bit AD conversion mode and to control the conversion time 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESA 0000 0000 ADRLC DATAL3 DATAL2 DATAL1 DATALO ADRL3 ADRL2 ADRL1 ADTM2 DATAL3 bit 7 DATAL2 bit 6 DATAL1 bit 5 DATALO bit 4 AD conversion result lower order 4 bits ADRL3 bit 3 Fixed bit This bit must always be set to 0 ADRL2 bit 2 Fixed bit This bit must always be set to 0 ADRL1 bit 1 Fixed bit This bit must always be set to 0 ADTM2 bit 0 AD conversion time control This bit and AD mode register ADMRC bits ADTMI bit 1 and ADTMO bit 0 are used to control the conversion time See the subsection on the AD mode register for the procedure to set the conversion time Note The conversion result data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductor Data Sheet
141. tor address 0013H is generated Notes TOLCMP must be cleared to 0 with an instruction When 16 bit mode is to be used TOLRUN and TOHRUN must be set to the same value to control operation TOLCMP and TOHCMP are set at the same time in the 16 bit mode 3 5 4 2 Timer 0 programmable prescaler match register TOPRR 1 This register is an 8 bit register that is used to define the clock period Tpr of timer counter 0 2 The count value of the prescaler starts at 0 when TOPRR is loaded with data 3 TOPRR 1 x Period of cycle clock Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE11 0000 0000 R W TOPRR TOPRR7 TOPRR6 TOPRRS TOPRR4 TOPRR3 TOPRR2 TOPRRO 3 5 43 Timer counter 0 low byte TOL 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or external signals Address Initial Value R W Name 7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 TOLS TOL4 TOL3 TOL2 TOL1 TOLO 3 5 4 4 Timer counter 0 high byte 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or overflow occurring in TOL Address Initial Value RAW BIT7 BITe BIT5 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHI TOHO 3 5 45 Timer counter 0 ma
142. type which is dependent on the type of the microcontroller You need to pay attention to this fact and to the correct set of development tools when using this function This series adopts a 5 bit counter Note 5 Depending on the type of SANYO microcontrollers the initial value of RCCTD is set to a frequency that is close to that of the internal medium speed RC oscillator or it is undefined The initial value of RCCTD of this series of microcontrollers is undefined 4 2 4 6 System clock divider control register CLKDIV 3 bit register This register controls the frequency division processing of the system clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOC HHHH H000 CLKDIV z z CLKDV2 CLKDV1 CLKDVO Bits 7 to 3 These bits do not exist They are always read as 1 CLKDV2 bit 2 CLKDV1 bit 1 Define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio System Clock 4 2 5 1 2 3 4 Example of Switching the CF Oscillator Amplifier Size System clock state Put the system clock into a state other than the CF oscillator main Switch the CF oscillation amplifier size to low Set CFLAMP bit 2 of the low speed RC oscillator control register to 1 Wait for the CF oscillation stabilization time Wait for the CF oscillation stabilization time specified in the SANYO Semiconductor Data Sheet Switch the system
143. upt level control flag e Alin this bit sets all interrupts to vector address 0000BH to L level e A in this bit sets all interrupts to vector address 0000BH to the X level XCNTO bit 0 00003H interrupt level control flag e Alin this bit sets all interrupts to vector address 00003H to the L level e A in this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 Thisregister is an 8 bit register that selects the interrupt level H L of interrupts to vector addresses 00013H to 0004BH Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE09 0000 0000 R W IP IP4B IP43 IP3B IP33 IP2B IIP23 IP1B IP13 Interrupt Interr Level Vector Address terrupt Leve 0004BH B EN CIC E ES 0002BH IP2B 00023H IP23 0001BH 00013 IP13 ES E 1 4 4 LC872R00 Chapter 4 4 2 System Clock Generator Function 4 2 1 Overview This series of microcontrollers incorporates three systems of oscillator circuits i e the main clock oscillator medium speed RC oscillator and variable modulation frequency VMRC RC oscillator as system clock generator circuits The medium speed RC and variable modulation frequency RC oscillator circuits have internal resistors and capacitors so that no external circuit is required The system clock can be selected from these three types of clock sources un
144. used as the timer OH capture input P16 as the timer 0 event input timer OL capture input P15 as the timer 0 event input timer OH capture input SIO1 clock I O and P14 to P13 for 5101 I O Timer 0 HOLD Count Mode Input Release Witha CMOS N channel L level H level Timer Enabled programmable open drain Ledge H edge Note Note P17 HOLD mode release is available only when level detection is set Fess HHOOOHHH PIFCR piser parce PiStCR Interrupt Input Signal Detection Capture Input Input Output Fe47_ R W errsT mxo ist STOIN Bits 7 6 5 4 and 0 of PITST FE47 are reserved for testing They must always be set to 0 3 2 3 Related Registers 3 2 3 1 Port 1 data latch P1 1 The port 1 data latch is an 8 bit register for controlling port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If P1 FE44 is manipulated using NOTI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000
145. ut Timer 7 8 bit timer with a 6 bit prescaler with toggle output e SIO 5101 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512 Tcyc transfer clock Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048 Tcyc baudrate Mode 2 Bus mode 1 start bit 8 data bits 2 to 512 Tcyc transfer clock Mode 3 Bus mode 2 start detection 8 data bits stop detection AD converter 12 bits x 8 channels 12 8 bit AD converter resolution selectable Remote control receiver circuit multiplexed with P15 SCK1 INT3 TOIN pin Noise filtering function noise filter time constant selectable from among 1 32Tcyc and 128 Watchdog timer 1 External RC watchdog timer 2 Interrupt or a reset signal selectable Interrupts 12 sources 8 vector addresses 1 Provides three levels low high and highest X of multiplex interrupt control Any interrupt request of the level equal to or lower than the current interrupt is not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the smallest vector address is given priority No Vector Address Level Interrupt Source 00003H XorL INTO 00013H INT2 TOL INT4 sw
146. ve number or negative number positive number is a positive 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC872R00 Chapter 2 3 When the higher order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the higher order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 4 1 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there is an odd number of 1s in the A register It is cleared to 0 when there is an even number of 1s in the A register 2 9 Stack Pointer SP LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the microcontroller type The SP is 16 bits long and made up of two registers SPL at address FEOA and SPH at address FEOB It is initialized to OOOOH when a reset is performed The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory Address Initial value R W Name BIT
147. which is established when HOLD mode is entered is in the high state or by a falling edge occurring when P16 data which is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 4 3 4 Input signal select register ISL 1 This register is a 5 bit register for controlling the timer 0 input and noise filter time constant Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 00HH H000 R W ISL STOHCP STOLCP NFSEL NFON STOIN STOHCP bit 7 Timer OH capture signal input port select This bit selects the timer OH capture signal input port When set to 1 a timer OH capture signal is generated when an input that satisfies the interrupt detection conditions is supplied to P17 If the INTI interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P17 When set to 0 a timer OH capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 Port 7 STOLCP bit 6 Timer OL capture signal input
148. while it is running 55H WDT This instruction turns on the N channel transistor at the P70 INTO TOLCP pin Owing to the pulse stretcher function keeps the transistor on after the MOV instruction is executed the capacitor keeps discharging for a period from a minimum of 1920 cycle times to a maximum of 2048 cycle times Detecting a runaway condition Unless the above mentioned instruction is executed periodically the external RC circuit keeps charging because the watchdog timer is not cleared As charging proceeds and the voltage at the P70 INTO TOLCP pin reaches the high level the watchdog timer considers that a program runaway has occurred and triggers a reset or interrupt In this case the runaway detection flag WDTFLG is set provided that WDTRST is set to 1 If WDTRST is found to be 1 in this case a reset occurs and execution restarts at the program start address which is selected through a user option If WDTRST is 0 an external interrupt INTO is generated and control is transferred to vector address 0003H e Hints on Use 1 2 R 5 P7O INTO To realize ultra low power operation using HOLD mode it is necessary not to use the watchdog timer at all or to disable the watchdog timer from running in HOLD mode by setting WDTHLT to 1 Be sure to set WDTCLR to 0 when the watchdog timer is not to be used The P70 INTO TOLCP pin has two input levels The threshold level of the input pins of the watchdog timer circuit
149. xternal interrupts It can also be used as an input port for a capture signal input or HOLD mode release signal input There is no user option for this port 3 4 2 1 2 3 4 5 Functions Input output port 1 bit P70 Bit 0 of the port 7 control register P7 5 is used to control the port output data and bit 4 to control the I O direction of the port data e P70 is of the N channel open drain output type The port is provided with a programmable pull up resistor Interrupt input pin function e P70 is assigned to INTO and used to detect a low or high level a low or high edge and to set the interrupt flag Timer OL capture input function A timer OL capture signal is generated each time a signal change that sets the interrupt flag is supplied to the port selected from P70 and P16 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle interval for the duration of the input signal HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode medium speed RC oscillator selected as system clock When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When a signal change such that sets the interrupt flag is input to P70 in HOLD mode the interrupt flag is
150. y configuring options e Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level 2 The use disuse of the LVD function and the low voltage threshold level 7 levels 1 91V 2 01V 2 31V 2 51V 2 81V 3 79V and 4 28V can be changed by configuring options Standby function e HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation is not stopped automatically 2 There four ways of releasing HALT mode lt 1 gt Setting the reset pin to a low level 2 Reset caused by low voltage detection 3 Reset caused by watchdog timer 4 Generating an interrupt e HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 and the medium speed RC oscillators automatically stop operation 2 There are five ways of releasing HOLD mode lt 1 gt Setting the reset pin to the low level lt 2 gt Reset caused by low voltage detection lt 3 gt Reset caused by watchdog timer 1 3 lt 4 gt Establishing an interrupt source at one of the INTO INT1 INT2 and INT4 pins INTO and INT1 HOLD mode release is available only when level detection is set lt 5 gt Establishing an interrupt source at port 0 On chip debugger function flash ROM version Supports software debugging with the microcontroller mounted on the targe

LC872R00 SERIES USER`S MANUAL

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